fifo overflow bug

[mjc0608]

In multiple example designs, the fifo in the requestor may overflow if the TX channel is full. I'm trying to solve this problem and I hope we can have some discussion. Thanks.

[ciroceissler]

Hey! Great that you are trying to solve this problem.

If you share the designs with this problem, we can try to replicate the bug and discuss more!

tks!

[mjc0608]

I tried to reproduce the bug under simulation environment but failed. I found this bug because we are trying to use hardcloud as a benchmark suite in our FPGA virtualization project and thus we deployed multiple accelerators on the same FPGA.

It seems like the bug needs the following conditions: 1) the TXC0 channel is not full, 2) the TXC1 channel is full for more than several continuous cycles (when the fifo gets full).

I think all designs that use the fifo may suffer from this bug with very little chance. However, when we deploy 9 accelerators on the same FPGA, only grayscale, gaussian, sobel, and fft cannot finish executing due to packet loss.

My current solution to workaround this issue is to let [sent_requests - received_response < size_of_fifo] and slightly enlarge the fifo to get acceptable performance. Still working on this and don't know whether this works.

[ciroceissler]

I have to think about a way to reproduce this bug using the simulator.

First, I will review the FIFO design. Then, I will create one test to force the conditions you mention above - I know you already try, but I think it is really difficult to debug without the simulator.

I will look your solution as well.

tks!

[mjc0608]

I compiled a bitstream using the method mentioned above but it does not work. I'm afraid it is due to something else. I'll keep reviewing the code and find out the reason.

Maybe the fifo is not the root cause...