Skip to content

Actions: openhwgroup/cva6

Actions

ci

Actions

Loading...
Loading

Show workflow options

Create status badge

Loading
ci.yml
2,827 workflow runs
2,827 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

doc: fix build (cva6_frontend.adoc) (#2644) ci #4038: Commit b5b316a pushed by JeanRochCoulon
December 3, 2024 06:43 42m 7s master
master
December 3, 2024 06:43 42m 7s
doc: fix build (cva6_frontend.adoc) ci #4037: Pull request #2644 synchronize by JeanRochCoulon
December 3, 2024 06:42 42m 14s ThalesSiliconSecurity:fix-doc-frontend
ThalesSiliconSecurity:fix-doc-frontend
December 3, 2024 06:42 42m 14s
doc: fix build (cva6_frontend.adoc) ci #4036: Pull request #2644 opened by ASintzoff
December 3, 2024 06:41 41m 22s ThalesSiliconSecurity:fix-doc-frontend
ThalesSiliconSecurity:fix-doc-frontend
December 3, 2024 06:41 41m 22s
fix size of vectors when AxiNumWords=1 (#2639) ci #4035: Commit 9877af5 pushed by JeanRochCoulon
December 3, 2024 06:14 42m 45s master
master
December 3, 2024 06:14 42m 45s
fix size of vectors when AxiNumWords=1 ci #4034: Pull request #2639 synchronize by AngelaGonzalezMarino
December 2, 2024 16:48 42m 3s planvtech:fix_cache_line_width_64
planvtech:fix_cache_line_width_64
December 2, 2024 16:48 42m 3s
use dcache_assoc_width (#2640) ci #4033: Commit ba8ac71 pushed by JeanRochCoulon
December 2, 2024 16:40 43m 24s master
master
December 2, 2024 16:40 43m 24s
fix size of vectors when AxiNumWords=1 ci #4032: Pull request #2639 synchronize by AngelaGonzalezMarino
December 2, 2024 08:32 41m 57s planvtech:fix_cache_line_width_64
planvtech:fix_cache_line_width_64
December 2, 2024 08:32 41m 57s
fix size of vectors when AxiNumWords=1 ci #4031: Pull request #2639 synchronize by AngelaGonzalezMarino
December 2, 2024 07:45 42m 16s planvtech:fix_cache_line_width_64
planvtech:fix_cache_line_width_64
December 2, 2024 07:45 42m 16s
use dcache_assoc_width ci #4030: Pull request #2640 synchronize by AngelaGonzalezMarino
December 2, 2024 07:45 42m 46s planvtech:use_DCACHE_ASSOC_WIDTH-param
planvtech:use_DCACHE_ASSOC_WIDTH-param
December 2, 2024 07:45 42m 46s
Bump verif/core-v-verif from b7f57c1 to 9601c80 (#2642) ci #4029: Commit 84e3a39 pushed by ASintzoff
November 29, 2024 17:03 1h 1m 0s master
master
November 29, 2024 17:03 1h 1m 0s
Altera apu agilex7 ci #4028: Pull request #2635 synchronize by AngelaGonzalezMarino
November 29, 2024 16:55 42m 24s planvtech:altera_apu_agilex7
planvtech:altera_apu_agilex7
November 29, 2024 16:55 42m 24s
use dcache_assoc_width ci #4027: Pull request #2640 synchronize by AngelaGonzalezMarino
November 29, 2024 16:55 41m 51s planvtech:use_DCACHE_ASSOC_WIDTH-param
planvtech:use_DCACHE_ASSOC_WIDTH-param
November 29, 2024 16:55 41m 51s
fix size of vectors when AxiNumWords=1 ci #4026: Pull request #2639 synchronize by AngelaGonzalezMarino
November 29, 2024 16:55 41m 18s planvtech:fix_cache_line_width_64
planvtech:fix_cache_line_width_64
November 29, 2024 16:55 41m 18s
Bump verif/core-v-verif from b7f57c1 to 9601c80 ci #4025: Pull request #2642 synchronize by ASintzoff
November 29, 2024 16:29 42m 24s dependabot/submodules/verif/core-v-verif-9601c80
dependabot/submodules/verif/core-v-verif-9601c80
November 29, 2024 16:29 42m 24s
Merge branch 'master' into dependabot/submodules/verif/core-v-verif-9… ci #4024: Commit 4ec57f3 pushed by ASintzoff
November 29, 2024 16:29 41m 48s dependabot/submodules/verif/core-v-verif-9601c80
dependabot/submodules/verif/core-v-verif-9601c80
November 29, 2024 16:29 41m 48s
Add Support for Digilent Arty-A7 100T FPGA Board ci #4023: Pull request #2581 synchronize by WorldofJARcraft
November 29, 2024 16:26 Action required cispa:arty-support
cispa:arty-support
November 29, 2024 16:26 Action required
Provide the correct environment for doc build (#2643) ci #4022: Commit aa62eec pushed by ASintzoff
November 29, 2024 16:25 41m 42s master
master
November 29, 2024 16:25 41m 42s
Provide the correct environment for doc build ci #4021: Pull request #2643 opened by valentinThomazic
November 29, 2024 16:21 42m 5s valentinThomazic:rtd
valentinThomazic:rtd
November 29, 2024 16:21 42m 5s
Altera apu agilex7 ci #4020: Pull request #2635 synchronize by AngelaGonzalezMarino
November 29, 2024 14:56 41m 45s planvtech:altera_apu_agilex7
planvtech:altera_apu_agilex7
November 29, 2024 14:56 41m 45s
use dcache_assoc_width ci #4019: Pull request #2640 synchronize by AngelaGonzalezMarino
November 29, 2024 14:56 42m 22s planvtech:use_DCACHE_ASSOC_WIDTH-param
planvtech:use_DCACHE_ASSOC_WIDTH-param
November 29, 2024 14:56 42m 22s
fix size of vectors when AxiNumWords=1 ci #4018: Pull request #2639 synchronize by AngelaGonzalezMarino
November 29, 2024 14:55 42m 1s planvtech:fix_cache_line_width_64
planvtech:fix_cache_line_width_64
November 29, 2024 14:55 42m 1s
Bump verif/core-v-verif from b7f57c1 to 9601c80 ci #4017: Pull request #2642 opened by dependabot bot
November 29, 2024 14:04 1h 0m 21s dependabot/submodules/verif/core-v-verif-9601c80
dependabot/submodules/verif/core-v-verif-9601c80
November 29, 2024 14:04 1h 0m 21s
Bump verif/core-v-verif from b7f57c1 to 9601c80 ci #4016: Commit eae2f3f pushed by dependabot bot
November 29, 2024 14:04 1h 0m 16s dependabot/submodules/verif/core-v-verif-9601c80
dependabot/submodules/verif/core-v-verif-9601c80
November 29, 2024 14:04 1h 0m 16s
Fix documentation build (#2641) ci #4015: Commit 820a8c6 pushed by ASintzoff
November 29, 2024 13:37 42m 9s master
master
November 29, 2024 13:37 42m 9s
Fix documentation build ci #4014: Pull request #2641 synchronize by valentinThomazic
November 29, 2024 13:30 41m 48s ThalesSiliconSecurity:fix-rtd-build
ThalesSiliconSecurity:fix-rtd-build
November 29, 2024 13:30 41m 48s