diff --git a/verif/docs/VerifPlans/csr_access/VP_IP000.yml b/verif/docs/VerifPlans/csr_access/VP_IP000.yml
index 664f24fee5..a62965d9d2 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP000.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP000.yml
@@ -17,7 +17,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 Machine mode RW CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -68,7 +68,7 @@ subfeatures: !!omap
           random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and read using the
           CSR instructions defined in the instruction set architecture (ISA).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -94,7 +94,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 Machine Mode CSRs in different privilege
           modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP001.yml b/verif/docs/VerifPlans/csr_access/VP_IP001.yml
index 4e72a8156c..8b16419697 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP001.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP001.yml
@@ -16,7 +16,7 @@ subfeatures: !!omap
         description: Upon reset,RISC-V CVA6 Machine RO(read only) CSR must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -42,7 +42,7 @@ subfeatures: !!omap
           random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and confirm whether
           write into RO CSRs is possible or not.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -68,7 +68,7 @@ subfeatures: !!omap
         description: Accessing RISC-V Machine read only CSRs in different privilege
           modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP002.yml b/verif/docs/VerifPlans/csr_access/VP_IP002.yml
index c615ae16e4..51ed9fa8d0 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP002.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP002.yml
@@ -17,7 +17,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 Supervisor mode RW CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -67,7 +67,7 @@ subfeatures: !!omap
           writing random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and read
           using the CSR instructions defined in the instruction set architecture (ISA).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -93,7 +93,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 Supervisor Mode CSRs in different privilege
           modes (User,Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP003.yml b/verif/docs/VerifPlans/csr_access/VP_IP003.yml
index 3267c6030f..3099b330be 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP003.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP003.yml
@@ -16,7 +16,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 User mode counter CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -51,7 +51,7 @@ subfeatures: !!omap
           two continuous reads and checking whether the value in the second read is
           greater than the value in the first read."
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -80,7 +80,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 user Mode counter CSR in different privilege
           modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/VP_IP004.yml b/verif/docs/VerifPlans/csr_access/VP_IP004.yml
index 8c7d5b8871..2250afd03e 100644
--- a/verif/docs/VerifPlans/csr_access/VP_IP004.yml
+++ b/verif/docs/VerifPlans/csr_access/VP_IP004.yml
@@ -16,7 +16,7 @@ subfeatures: !!omap
         description: Upon reset, RISC-V CVA6 Machine mode counter CSRs must initialize
           to their respective POR value.
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -52,7 +52,7 @@ subfeatures: !!omap
           tested by performing two continuous reads and checking whether the value
           in the second read is greater than the value in the first read."
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
@@ -81,7 +81,7 @@ subfeatures: !!omap
         description: Accessing RISC-V CVA6 user Machine mode counter CSRs in different
           privilege modes (User, Supervisor and Machine modes).
         reqt_doc: 
-          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html
+          https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html
         ref_mode: page
         ref_page: ''
         ref_section: ''
diff --git a/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md b/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md
index 60e8d9e63c..861c79e614 100644
--- a/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md
+++ b/verif/docs/VerifPlans/csr_access/dvplan_csr-access.md
@@ -89,7 +89,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#item-000 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -153,7 +153,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id2 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -188,7 +188,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id3 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -223,7 +223,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id5 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -254,7 +254,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id6 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -287,7 +287,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id7 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -322,7 +322,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id9 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -384,7 +384,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id13 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -417,7 +417,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id15 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -451,7 +451,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id17 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -483,7 +483,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id18 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -524,7 +524,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id20 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -588,7 +588,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id23 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -620,7 +620,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id25 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**
     
@@ -662,7 +662,7 @@ Module: CSR ACCESS VERIFICATION[](#module-csr-access-verification "Permalink
 
 ##### Item: 000[](#id27 "Permalink to this headline")
 
-*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CV32A6\_Control\_Status\_Registers.html
+*   **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01\_cva6\_user/CSR\_CV32A60X.html
     
 *   **Feature Description**