diff --git a/core/compressed_decoder.sv b/core/compressed_decoder.sv
index d75fae9121..c691dfa75b 100644
--- a/core/compressed_decoder.sv
+++ b/core/compressed_decoder.sv
@@ -44,7 +44,7 @@ module compressed_decoder #(
     is_compressed_o  = 1'b1;
     instr_o          = instr_i;
     is_macro_instr_o = 0;
-    is_zcmt_instr_o  = 1'b0;;
+    is_zcmt_instr_o  = 1'b0;
 
     // I: |    imm[11:0]    | rs1 | funct3 |    rd    | opcode |
     // S: | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
diff --git a/core/id_stage.sv b/core/id_stage.sv
index 35e9302fe1..36cf1963ad 100644
--- a/core/id_stage.sv
+++ b/core/id_stage.sv
@@ -125,9 +125,9 @@ module id_stage #(
   logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr_i;
   logic                            stall_instr_fetch;
   logic stall_macro_deco, stall_macro_deco_zcmp, stall_macro_deco_zcmt;
-  logic                                          is_last_macro_instr_o;
-  logic                                          is_double_rd_macro_instr_o;
-  logic               [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr_i;
+  logic                            is_last_macro_instr_o;
+  logic                            is_double_rd_macro_instr_o;
+  logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr_i;
 
   if (CVA6Cfg.RVC) begin
     // ---------------------------------------------------------