From fa7cd560ac0775299f092f79bef5d84660a7803d Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Wed, 27 Nov 2024 13:07:16 +0100 Subject: [PATCH 1/9] altera IPs --- .../altera/ip/cva6_intel_axi_bridge_0.ip | 3458 + .../synth/altera_avalon_st_pipeline_base.v | 222 + ...bridge_0_altera_axi_bridge_1940_72stfyq.sv | 877 + .../cva6_intel_axi_bridge_0.bsf | 626 + .../cva6_intel_axi_bridge_0.cmp | 138 + .../cva6_intel_axi_bridge_0.html | 407 + .../cva6_intel_axi_bridge_0.qgsynthc | 316 + .../cva6_intel_axi_bridge_0.qip | 41 + .../cva6_intel_axi_bridge_0.sopcinfo | 1689 + .../cva6_intel_axi_bridge_0.xml | 270 + .../cva6_intel_axi_bridge_0_bb.v | 136 + .../cva6_intel_axi_bridge_0_generation.rpt | 14 + .../cva6_intel_axi_bridge_0_inst.v | 135 + .../cva6_intel_axi_bridge_0_inst.vhd | 275 + .../synth/cva6_intel_axi_bridge_0.v | 312 + corev_apu/altera/ip/cva6_intel_jtag_uart_0.ip | 1408 + ...t_0_altera_avalon_jtag_uart_1924_v3imxwq.v | 643 + .../cva6_intel_jtag_uart_0.bsf | 130 + .../cva6_intel_jtag_uart_0.cmp | 15 + .../cva6_intel_jtag_uart_0.html | 188 + .../cva6_intel_jtag_uart_0.qgsynthc | 96 + .../cva6_intel_jtag_uart_0.qip | 45 + .../cva6_intel_jtag_uart_0.regmap | 182 + .../cva6_intel_jtag_uart_0.sopcinfo | 1028 + .../cva6_intel_jtag_uart_0.xml | 226 + .../cva6_intel_jtag_uart_0_bb.v | 14 + .../cva6_intel_jtag_uart_0_generation.rpt | 19 + .../cva6_intel_jtag_uart_0_inst.v | 13 + .../cva6_intel_jtag_uart_0_inst.vhd | 29 + .../synth/cva6_intel_jtag_uart_0.v | 32 + corev_apu/altera/ip/ed_synth_emif_fm_0.ip | 10744 +++ .../synth/altera_emif_arch_fm_afi_if.sv | 1048 + .../synth/altera_emif_arch_fm_buf_bdir_df.sv | 168 + .../synth/altera_emif_arch_fm_buf_bdir_se.sv | 87 + .../altera_emif_arch_fm_buf_udir_cp_i.sv | 74 + .../altera_emif_arch_fm_buf_udir_df_i.sv | 58 + .../altera_emif_arch_fm_buf_udir_df_o.sv | 117 + .../altera_emif_arch_fm_buf_udir_se_i.sv | 53 + .../altera_emif_arch_fm_buf_udir_se_o.sv | 58 + .../synth/altera_emif_arch_fm_buf_unused.sv | 25 + .../synth/altera_emif_arch_fm_bufs.sv | 1288 + .../synth/altera_emif_arch_fm_cal_counter.sv | 126 + .../altera_emif_arch_fm_core_clks_rsts.sv | 631 + .../altera_emif_arch_fm_hmc_amm_data_if.sv | 248 + .../altera_emif_arch_fm_hmc_ast_data_if.sv | 196 + .../synth/altera_emif_arch_fm_hmc_avl_if.sv | 375 + .../synth/altera_emif_arch_fm_hmc_mmr_if.sv | 84 + .../altera_emif_arch_fm_hmc_sideband_if.sv | 160 + .../altera_emif_arch_fm_hps_clks_rsts.sv | 109 + .../altera_emif_arch_fm_io_lane_remap.sv | 696 + .../synth/altera_emif_arch_fm_io_tiles.sv | 2110 + .../altera_emif_arch_fm_io_tiles_wrap.sv | 1864 + .../synth/altera_emif_arch_fm_local_reset.sv | 167 + .../synth/altera_emif_arch_fm_oct.sv | 36 + .../synth/altera_emif_arch_fm_phylite_if.sv | 221 + .../synth/altera_emif_arch_fm_pll.sv | 474 + .../altera_emif_arch_fm_pll_extra_clks.sv | 79 + .../synth/altera_emif_arch_fm_pll_fast_sim.sv | 118 + .../synth/altera_emif_arch_fm_regs.sv | 63 + .../synth/altera_emif_arch_fm_seq_if.sv | 248 + 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..._altera_emif_arch_fm_191_faapzxy_utils.tcl | 613 + ...th_emif_fm_0_altera_emif_ecc_191_z5lxzjq.v | 211 + .../synth/altera_emif_ecc_core.v | 908 + .../synth/altera_emif_preload_ecc_encoder.sv | 401 + .../synth/fmiohmc_ecc.v | 2673 + .../synth/fmiohmc_ecc_amm2ast.v | 181 + .../synth/fmiohmc_ecc_cb.v | 31 + .../synth/fmiohmc_ecc_decoder.v | 256 + .../synth/fmiohmc_ecc_decoder_112.v | 93 + .../synth/fmiohmc_ecc_decoder_64.v | 64 + .../fmiohmc_ecc_decoder_64_altecc_decoder.v | 222 + .../synth/fmiohmc_ecc_decoder_64_decode.v | 337 + .../synth/fmiohmc_ecc_encoder.v | 160 + .../synth/fmiohmc_ecc_encoder_112.v | 57 + .../synth/fmiohmc_ecc_encoder_64.v | 41 + .../fmiohmc_ecc_encoder_64_altecc_encoder.v | 52 + .../synth/fmiohmc_ecc_interface_fifo.v | 122 + .../synth/fmiohmc_ecc_mmr.v | 637 + .../synth/fmiohmc_ecc_pcm_112.v | 39 + .../synth/fmiohmc_ecc_sv_112.v | 145 + .../synth/fmiohmc_ecc_wrapper.v | 818 + .../synth/fmiohmc_fifo.v | 167 + ...nth_emif_fm_0_altera_emif_fm_274_2bbiayq.v | 2149 + .../ed_synth_emif_fm_0/ed_synth_emif_fm_0.bsf | 413 + .../ed_synth_emif_fm_0/ed_synth_emif_fm_0.cmp | 47 + .../ed_synth_emif_fm_0.html | 8057 ++ .../ed_synth_emif_fm_0.qgsynthc | 45277 ++++++++++ .../ed_synth_emif_fm_0/ed_synth_emif_fm_0.qip | 949 + .../ed_synth_emif_fm_0.sopcinfo | 75083 ++++++++++++++++ .../ed_synth_emif_fm_0/ed_synth_emif_fm_0.xml | 12829 +++ .../ed_synth_emif_fm_0_bb.v | 46 + .../ed_synth_emif_fm_0_generation.rpt | 33 + ...ed_synth_emif_fm_0_generation_previous.rpt | 33 + .../ed_synth_emif_fm_0_inst.v | 45 + .../ed_synth_emif_fm_0_inst.vhd | 93 + .../synth/ed_synth_emif_fm_0.v | 96 + corev_apu/altera/ip/emif_cal.ip | 624 + .../emif_cal_altera_emif_cal_274_kaypsya.v | 166 + .../synth/altera_emif_cal_iossm.sv | 494 + .../synth/altera_emif_f2c_gearbox.sv | 152 + ...f_cal_altera_emif_cal_iossm_274_yagv7fq.sv | 300 + ..._altera_emif_cal_iossm_274_yagv7fq_arch.sv | 494 + ...altera_emif_cal_iossm_274_yagv7fq_code.hex | 30722 +++++++ ...iossm_274_yagv7fq_sim_global_param_tbl.hex | 26 + ...iossm_274_yagv7fq_sim_global_param_tbl.txt | 30 + ...ssm_274_yagv7fq_synth_global_param_tbl.hex | 26 + ...ssm_274_yagv7fq_synth_global_param_tbl.txt | 30 + corev_apu/altera/ip/emif_cal/emif_cal.bsf | 100 + corev_apu/altera/ip/emif_cal/emif_cal.cmp | 12 + corev_apu/altera/ip/emif_cal/emif_cal.html | 208 + .../altera/ip/emif_cal/emif_cal.qgsynthc | 241 + corev_apu/altera/ip/emif_cal/emif_cal.qip | 65 + .../altera/ip/emif_cal/emif_cal.sopcinfo | 896 + corev_apu/altera/ip/emif_cal/emif_cal.xml | 273 + corev_apu/altera/ip/emif_cal/emif_cal_bb.v | 11 + .../ip/emif_cal/emif_cal_generation.rpt | 15 + .../emif_cal/emif_cal_generation_previous.rpt | 15 + corev_apu/altera/ip/emif_cal/emif_cal_inst.v | 10 + .../altera/ip/emif_cal/emif_cal_inst.vhd | 23 + corev_apu/altera/ip/emif_cal/synth/emif_cal.v | 26 + corev_apu/altera/ip/iddr_intel.ip | 439 + .../iddr_intel_altera_gpio_2210_id4velq.v | 58 + .../synth/altera_gpio.sv | 705 + corev_apu/altera/ip/iddr_intel/iddr_intel.bsf | 71 + corev_apu/altera/ip/iddr_intel/iddr_intel.cmp | 8 + .../altera/ip/iddr_intel/iddr_intel.html | 193 + .../altera/ip/iddr_intel/iddr_intel.qgsynthc | 446 + corev_apu/altera/ip/iddr_intel/iddr_intel.qip | 64 + .../altera/ip/iddr_intel/iddr_intel.sopcinfo | 716 + corev_apu/altera/ip/iddr_intel/iddr_intel.xml | 248 + .../altera/ip/iddr_intel/iddr_intel_bb.v | 7 + .../ip/iddr_intel/iddr_intel_generation.rpt | 17 + .../altera/ip/iddr_intel/iddr_intel_inst.v | 6 + .../altera/ip/iddr_intel/iddr_intel_inst.vhd | 15 + .../altera/ip/iddr_intel/synth/iddr_intel.v | 18 + corev_apu/altera/ip/io_pll.ip | 2038 + .../sim/io_pll_altera_iopll_1931_oypl3jq.vo | 450 + .../synth/agilex_iobank_pll.ipxact | 3214 + .../io_pll_altera_iopll_1931_oypl3jq.sdc | 179 + .../synth/io_pll_altera_iopll_1931_oypl3jq.v | 450 + ...ltera_iopll_1931_oypl3jq_all_ip_params.tcl | 827 + ...l_altera_iopll_1931_oypl3jq_parameters.tcl | 121 + ..._pll_altera_iopll_1931_oypl3jq_pin_map.tcl | 1096 + corev_apu/altera/ip/io_pll/greybox/io_pll.v | 323 + corev_apu/altera/ip/io_pll/io_pll.bsf | 126 + corev_apu/altera/ip/io_pll/io_pll.cmp | 13 + corev_apu/altera/ip/io_pll/io_pll.csv | 18 + corev_apu/altera/ip/io_pll/io_pll.html | 1397 + corev_apu/altera/ip/io_pll/io_pll.ipxact | 664 + corev_apu/altera/ip/io_pll/io_pll.ppf | 17 + corev_apu/altera/ip/io_pll/io_pll.qgsimc | 3328 + corev_apu/altera/ip/io_pll/io_pll.qgsynthc | 3328 + corev_apu/altera/ip/io_pll/io_pll.qip | 56 + corev_apu/altera/ip/io_pll/io_pll.sopcinfo | 7332 ++ corev_apu/altera/ip/io_pll/io_pll.spd | 15 + corev_apu/altera/ip/io_pll/io_pll.xml | 1079 + corev_apu/altera/ip/io_pll/io_pll_bb.v | 12 + .../altera/ip/io_pll/io_pll_generation.rpt | 65 + .../ip/io_pll/io_pll_generation_previous.rpt | 21 + corev_apu/altera/ip/io_pll/io_pll_inst.v | 11 + corev_apu/altera/ip/io_pll/io_pll_inst.vhd | 25 + .../ip/io_pll/sim/aldec/rivierapro_setup.tcl | 380 + .../ip/io_pll/sim/common/modelsim_files.tcl | 82 + .../ip/io_pll/sim/common/riviera_files.tcl | 82 + .../altera/ip/io_pll/sim/common/vcs_files.tcl | 65 + .../ip/io_pll/sim/common/vcsmx_files.tcl | 72 + .../ip/io_pll/sim/common/xcelium_files.tcl | 72 + corev_apu/altera/ip/io_pll/sim/io_pll.v | 28 + .../ip/io_pll/sim/mentor/msim_setup.tcl | 387 + .../ip/io_pll/sim/synopsys/vcs/vcs_setup.sh | 297 + .../sim/synopsys/vcsmx/synopsys_sim.setup | 15 + .../io_pll/sim/synopsys/vcsmx/vcsmx_setup.sh | 354 + .../altera/ip/io_pll/sim/xcelium/cds.lib | 22 + .../cds_libs/altera_iopll_1931.cds.lib | 21 + .../sim/xcelium/cds_libs/io_pll.cds.lib | 21 + .../altera/ip/io_pll/sim/xcelium/hdl.var | 2 + .../ip/io_pll/sim/xcelium/xcelium_setup.sh | 350 + corev_apu/altera/ip/io_pll/synth/io_pll.v | 28 + corev_apu/altera/ip/io_pll_test.ip | 2038 + corev_apu/altera/ip/iobuf.ip | 504 + .../synth/iobuf_altera_gpio_2210_ck55vhi.v | 59 + .../synth/altera_gpio.sv | 705 + corev_apu/altera/ip/iobuf/iobuf.bsf | 82 + corev_apu/altera/ip/iobuf/iobuf.cmp | 9 + corev_apu/altera/ip/iobuf/iobuf.html | 193 + corev_apu/altera/ip/iobuf/iobuf.ppf | 13 + corev_apu/altera/ip/iobuf/iobuf.qgsynthc | 446 + corev_apu/altera/ip/iobuf/iobuf.qip | 64 + corev_apu/altera/ip/iobuf/iobuf.sopcinfo | 778 + corev_apu/altera/ip/iobuf/iobuf.xml | 253 + corev_apu/altera/ip/iobuf/iobuf_bb.v | 8 + .../altera/ip/iobuf/iobuf_generation.rpt | 20 + corev_apu/altera/ip/iobuf/iobuf_inst.v | 7 + corev_apu/altera/ip/iobuf/iobuf_inst.vhd | 17 + corev_apu/altera/ip/iobuf/synth/iobuf.v | 20 + corev_apu/altera/ip/oddr_intel.ip | 437 + .../oddr_intel_altera_gpio_2210_djxpcyq.v | 58 + .../synth/altera_gpio.sv | 705 + corev_apu/altera/ip/oddr_intel/oddr_intel.bsf | 71 + corev_apu/altera/ip/oddr_intel/oddr_intel.cmp | 8 + .../altera/ip/oddr_intel/oddr_intel.html | 193 + .../altera/ip/oddr_intel/oddr_intel.qgsynthc | 446 + corev_apu/altera/ip/oddr_intel/oddr_intel.qip | 64 + .../altera/ip/oddr_intel/oddr_intel.sopcinfo | 716 + corev_apu/altera/ip/oddr_intel/oddr_intel.xml | 248 + .../altera/ip/oddr_intel/oddr_intel_bb.v | 7 + .../ip/oddr_intel/oddr_intel_generation.rpt | 17 + .../altera/ip/oddr_intel/oddr_intel_inst.v | 6 + .../altera/ip/oddr_intel/oddr_intel_inst.vhd | 15 + .../altera/ip/oddr_intel/synth/oddr_intel.v | 18 + corev_apu/altera/ip/test_mm_ccb_0.ip | 2098 + .../synth/test_mm_ccb_0_mm_ccb_1921_5zxyagi.v | 356 + ..._mm_ccb_0_mm_ccb_st_dc_fifo_1921_6qjweta.v | 122 + ..._mm_ccb_0_mm_ccb_st_dc_fifo_1921_pg4qgey.v | 121 + .../synth/altera_dcfifo_synchronizer_bundle.v | 55 + .../synth/altera_reset_synchronizer.v | 89 + .../synth/altera_std_synchronizer_nocut.v | 267 + .../test_mm_ccb_0_st_dc_fifo_1951_tfgfkki.sdc | 100 + .../test_mm_ccb_0_st_dc_fifo_1951_tfgfkki.v | 1152 + .../ip/test_mm_ccb_0/synth/test_mm_ccb_0.v | 80 + .../altera/ip/test_mm_ccb_0/test_mm_ccb_0.bsf | 248 + .../altera/ip/test_mm_ccb_0/test_mm_ccb_0.cmp | 40 + .../ip/test_mm_ccb_0/test_mm_ccb_0.html | 202 + .../ip/test_mm_ccb_0/test_mm_ccb_0.ipxact | 1314 + .../ip/test_mm_ccb_0/test_mm_ccb_0.qgsynthc | 431 + .../altera/ip/test_mm_ccb_0/test_mm_ccb_0.qip | 72 + .../ip/test_mm_ccb_0/test_mm_ccb_0.sopcinfo | 1401 + .../altera/ip/test_mm_ccb_0/test_mm_ccb_0.xml | 461 + .../ip/test_mm_ccb_0/test_mm_ccb_0_bb.v | 38 + .../test_mm_ccb_0_generation.rpt | 22 + .../ip/test_mm_ccb_0/test_mm_ccb_0_inst.v | 37 + .../ip/test_mm_ccb_0/test_mm_ccb_0_inst.vhd | 79 + corev_apu/altera/ip/vJTAG.ip | 883 + corev_apu/altera/ip/vJTAG/synth/vJTAG.v | 76 + corev_apu/altera/ip/vJTAG/vJTAG.bsf | 284 + corev_apu/altera/ip/vJTAG/vJTAG.cmp | 35 + corev_apu/altera/ip/vJTAG/vJTAG.html | 149 + corev_apu/altera/ip/vJTAG/vJTAG.qgsynthc | 57 + corev_apu/altera/ip/vJTAG/vJTAG.qip | 43 + corev_apu/altera/ip/vJTAG/vJTAG.sopcinfo | 472 + corev_apu/altera/ip/vJTAG/vJTAG.xml | 230 + corev_apu/altera/ip/vJTAG/vJTAG_bb.v | 34 + .../altera/ip/vJTAG/vJTAG_generation.rpt | 14 + corev_apu/altera/ip/vJTAG/vJTAG_inst.v | 33 + corev_apu/altera/ip/vJTAG/vJTAG_inst.vhd | 69 + 263 files changed, 288701 insertions(+) create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0.ip create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/altera_avalon_st_pipeline_base.v create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq.sv create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.bsf create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.cmp create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.html create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qgsynthc create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qip create mode 100644 corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.sopcinfo create mode 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+ 1 + + + USE_M0_AWBURST + Use AWBURST signal + 1 + + + USE_M0_AWLOCK + Use AWLOCK signal + 1 + + + USE_M0_AWCACHE + Use AWCACHE signal + 1 + + + USE_M0_AWQOS + Use AWQOS signal + 0 + + + USE_S0_AWREGION + Use AWREGION signal + 0 + + + USE_S0_AWLOCK + Use AWLOCK signal + 1 + + + USE_S0_AWCACHE + Use AWCACHE signal + 1 + + + USE_S0_AWQOS + Use AWQOS signal + 0 + + + USE_S0_AWPROT + Use AWPROT signal + 1 + + + USE_M0_WSTRB + Use WSTRB signal + 1 + + + USE_S0_WLAST + Use WLAST signal + 1 + + + USE_M0_BID + Use BID signal + 1 + + + USE_M0_BRESP + Use BRESP signal + 1 + + + USE_S0_BRESP + Use BRESP signal + 1 + + + USE_M0_ARID + Use ARID signal + 1 + + + USE_M0_ARREGION + Use ARREGION signal + 0 + + + USE_M0_ARLEN + Use ARLEN signal + 1 + + + USE_M0_ARSIZE + Use ARSIZE signal + 1 + + + USE_M0_ARBURST + Use ARBURST signal + 1 + + + USE_M0_ARLOCK + Use ARLOCK signal + 1 + + + USE_M0_ARCACHE + Use ARCACHE signal + 1 + + + USE_M0_ARQOS + Use ARQOS signal + 0 + + + USE_S0_ARREGION + Use ARREGION signal + 0 + + + USE_S0_ARLOCK + Use ARLOCK signal + 1 + + + USE_S0_ARCACHE + Use ARCACHE signal + 1 + + + USE_S0_ARQOS + Use ARQOS signal + 0 + + + USE_S0_ARPROT + Use ARPROT signal + 1 + + + USE_M0_RID + Use RID signal + 1 + + + USE_M0_RRESP + Use RRESP signal + 1 + + + USE_M0_RLAST + Use RLAST signal + 1 + + + USE_S0_RRESP + Use RRESP signal + 1 + + + M0_ID_WIDTH + ID Width + 8 + + + S0_ID_WIDTH + ID Width + 8 + + + DATA_WIDTH + Data Width + 64 + + + WRITE_ADDR_USER_WIDTH + AWUSER Width + 32 + + + READ_ADDR_USER_WIDTH + ARUSER Width + 32 + + + WRITE_DATA_USER_WIDTH + WUSER Width + 32 + + + WRITE_RESP_USER_WIDTH + BUSER Width + 32 + + + READ_DATA_USER_WIDTH + RUSER Width + 32 + + + ADDR_WIDTH + Address Width + 64 + + + USE_S0_AWUSER + Use AWUSER signal + 0 + + + USE_S0_ARUSER + Use ARUSER signal + 0 + + + USE_S0_WUSER + Use WUSER signal + 0 + + + USE_S0_RUSER + Use RUSER signal + 0 + + + USE_S0_BUSER + Use BUSER signal + 0 + + + USE_M0_AWUSER + Use AWUSER signal + 0 + + + USE_M0_ARUSER + Use ARUSER signal + 0 + + + USE_M0_WUSER + Use WUSER signal + 0 + + + USE_M0_RUSER + Use RUSER signal + 0 + + + USE_M0_BUSER + Use BUSER signal + 0 + + + AXI_VERSION + AXI Version + AXI4 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + WRITE_ACCEPTANCE_CAPABILITY + Write Acceptance Capability + 16 + + + READ_ACCEPTANCE_CAPABILITY + Read Acceptance Capability + 16 + + + COMBINED_ACCEPTANCE_CAPABILITY + Combined Acceptance Capability + 16 + + + READ_DATA_REORDERING_DEPTH + Read Data Reordering Depth + 1 + + + ACE_LITE_SUPPORT + ACE Lite Support + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + ENABLE_CONCURRENT_SUBORDINATE_ACCESS + Enable Concurrent Subordinate Access + 0 + + + NO_REPEATED_IDS_BETWEEN_SUBORDINATES + No Repeated Ids Between Subordinates + 0 + + + ENABLE_OOO + ENABLE_OOO + 0 + + + BACKPRESSURE_DURING_RESET + Backpressure During Reset + 0 + + + + + + + embeddedsw.dts.compatible + simple-bus + + + embeddedsw.dts.group + bridge + + + embeddedsw.dts.name + bridge + + + embeddedsw.dts.vendor + altr + + + + + + + board + Board + default + + + device + Device + AGFB014R24B2E2V + + + deviceFamily + Device family + Agilex 7 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>aclk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>aresetn</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>axi4</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_awid</name> + <role>awid</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awlen</name> + <role>awlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awsize</name> + <role>awsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awburst</name> + <role>awburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awlock</name> + <role>awlock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awcache</name> + <role>awcache</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_wlast</name> + <role>wlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_bid</name> + <role>bid</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arid</name> + <role>arid</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arlen</name> + <role>arlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arsize</name> + <role>arsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arburst</name> + <role>arburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arlock</name> + <role>arlock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arcache</name> + <role>arcache</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_rid</name> + <role>rid</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_rlast</name> + <role>rlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>wakeupSignals</key> + <value>false</value> + </entry> + <entry> + <key>uniqueIdSupport</key> + <value>false</value> + </entry> + <entry> + <key>poison</key> + <value>false</value> + </entry> + <entry> + <key>traceSignals</key> + <value>false</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>cva6_intel_axi_bridge_0.m0</value> + </entry> + <entry> + <key>dfhFeatureGuid</key> + <value>0</value> + </entry> + <entry> + <key>dfhGroupId</key> + <value>0</value> + </entry> + <entry> + <key>dfhParameterId</key> + </entry> + <entry> + <key>dfhParameterName</key> + </entry> + <entry> + <key>dfhParameterVersion</key> + </entry> + <entry> + <key>dfhParameterData</key> + </entry> + <entry> + <key>dfhParameterDataLength</key> + </entry> + <entry> + <key>dfhFeatureMajorVersion</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureMinorVersion</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureId</key> + <value>35</value> + </entry> + <entry> + <key>dfhFeatureType</key> + <value>3</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>axi4</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_awid</name> + <role>awid</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awlen</name> + <role>awlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awsize</name> + <role>awsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awburst</name> + <role>awburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awlock</name> + <role>awlock</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awcache</name> + <role>awcache</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_wlast</name> + <role>wlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_bid</name> + <role>bid</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arid</name> + <role>arid</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arlen</name> + <role>arlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arsize</name> + <role>arsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arburst</name> + <role>arburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arlock</name> + <role>arlock</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arcache</name> + <role>arcache</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_rid</name> + <role>rid</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_rlast</name> + <role>rlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>wakeupSignals</key> + <value>false</value> + </entry> + <entry> + <key>uniqueIdSupport</key> + <value>false</value> + </entry> + <entry> + <key>poison</key> + <value>false</value> + </entry> + <entry> + <key>traceSignals</key> + <value>false</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>issuesINCRBursts</key> + <value>true</value> + </entry> + <entry> + <key>issuesWRAPBursts</key> + <value>true</value> + </entry> + <entry> + <key>issuesFIXEDBursts</key> + <value>true</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/altera_avalon_st_pipeline_base.v b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/altera_avalon_st_pipeline_base.v new file mode 100644 index 0000000000..5a611eecdb --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/altera_avalon_st_pipeline_base.v @@ -0,0 +1,222 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/24.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ +// $Revision: #1 $ +// $Date: 2024/02/01 $ +// $Author: psgswbuild $ +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ns + +module altera_avalon_st_pipeline_base ( + clk, + reset, + in_ready, + in_valid, + in_data, + out_ready, + out_valid, + out_data + ); + + parameter SYMBOLS_PER_BEAT = 1; + parameter BITS_PER_SYMBOL = 8; + parameter PIPELINE_READY = 1; + parameter SYNC_RESET = 0; + parameter BACKPRESSURE_DURING_RESET = 0; + localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; + + input clk; + input reset; + + output in_ready; + input in_valid; + input [DATA_WIDTH-1:0] in_data; + + input out_ready; + output out_valid; + output [DATA_WIDTH-1:0] out_data; + + reg full0; + reg full1; + reg [DATA_WIDTH-1:0] data0; + reg [DATA_WIDTH-1:0] data1; + + assign out_valid = full1; + assign out_data = data1; + + // Generation of internal reset synchronization + reg internal_sclr; + generate if (SYNC_RESET == 1) begin : rst_syncronizer + always @ (posedge clk) begin + internal_sclr <= reset; + end + end + endgenerate + + generate if (PIPELINE_READY == 1) + begin : REGISTERED_READY_PLINE + + assign in_ready = !full0; + + always @(posedge clk) begin + // ---------------------------- + // always load the second slot if we can + // ---------------------------- + if (~full0) + data0 <= in_data; + // ---------------------------- + // first slot is loaded either from the second, + // or with new data + // ---------------------------- + if (~full1 || (out_ready && out_valid)) begin + if (full0) + data1 <= data0; + else + data1 <= in_data; + end + end + + if (SYNC_RESET == 0) begin : async_rst0 + always @(posedge clk or posedge reset) begin + if (reset) begin + full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0; + full1 <= 1'b0; + end else begin + // out of reset. + if(~full1 & full0)begin + full0 <= 1'b0; + end + + // no data in pipeline + if (~full0 & ~full1) begin + if (in_valid) begin + full1 <= 1'b1; + end + end // ~f1 & ~f0 + + // one datum in pipeline + if (full1 & ~full0) begin + if (in_valid & ~out_ready) begin + full0 <= 1'b1; + end + // back to empty + if (~in_valid & out_ready) begin + full1 <= 1'b0; + end + end // f1 & ~f0 + + // two data in pipeline + if (full1 & full0) begin + // go back to one datum state + if (out_ready) begin + full0 <= 1'b0; + end + end // end go back to one datum stage + end + end + end // async_rst0 + else begin // sync_rst0 + always @(posedge clk ) begin + if (internal_sclr) begin + full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0; + full1 <= 1'b0; + end else begin + // out of reset. + if(~full1 & full0)begin + full0 <= 1'b0; + end + + // no data in pipeline + if (~full0 & ~full1) begin + if (in_valid) begin + full1 <= 1'b1; + end + end // ~f1 & ~f0 + + // one datum in pipeline + if (full1 & ~full0) begin + if (in_valid & ~out_ready) begin + full0 <= 1'b1; + end + // back to empty + if (~in_valid & out_ready) begin + full1 <= 1'b0; + end + end // f1 & ~f0 + + // two data in pipeline + if (full1 & full0) begin + // go back to one datum state + if (out_ready) begin + full0 <= 1'b0; + end + end // end go back to one datum stage + end + end + end // sync_rst0 + end + else + begin : UNREGISTERED_READY_PLINE + + // in_ready will be a pass through of the out_ready signal as it is not registered + assign in_ready = (~full1) | out_ready; + + if (SYNC_RESET == 0) begin : async_rst1 + always @(posedge clk or posedge reset) begin + if (reset) begin + data1 <= 'b0; + full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0; + end + else begin + if (in_ready) begin + data1 <= in_data; + full1 <= in_valid; + end + end + end + end // async_rst1 + else begin // sync_rst1 + always @(posedge clk ) begin + if (internal_sclr) begin + data1 <= 'b0; + full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0; + end + else begin + if (in_ready) begin + data1 <= in_data; + full1 <= in_valid; + end + end + end + end // sync_rst1 + end + endgenerate +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "4XeedYC2d5cuadvCJho763aSSkl1DRkxkQvoksMJv2VSpzATyoN8DqHo//teYnH8r162T4uH+BCa200GxyJP31cBno1sEsJk77E+qkjc8lZYjykrG0EIfQmjezkrpycnghQBNehMvorEdlwQS1QrIwscD7jaPxEU/CLR7ot04MotVla9fxGEAryOoaYgp4YUIXkzbQ53M3Az+ttWfnaiDklcQ3ejpqjMrKcwpwFZLnZOgHfQXc1wEa+d8d629rnMKGC6+/UG6C1Vf+DpHQY2TRXTlqjiCa7DQWt+09iwZNx7z6JG1/OgPftrs2j/oAhLXRX25o4h2GyfYmkvMNpVQZ/rsWZl1ekB3zJULd4roRuD2ku3F85nbPvqoYsyYn2vDYZPVGW2EdsZpCsA3m2JOFQx0yxgoarghhq/JJBCph+oqrp4GBlfV81B7gFPuSQJN53pe6fW4qmVu9XDVaOlyjRZ20uk+Ale5To3hT3Z2PVBVPfsQJse+BZDLa3ADCpP6qVTGyB3h/nPBLbxM4ZPLJyhDe6VdKJe14ym8droqtLDq3SVdMKOv1AG58j1oXuFa4NqugZ+olOSOuWP0KgJEupJycsQNl5kjt4gRc+/t6GnO5vzg39EC+hI70d7WeFM07BwPJY7Sdohl9uqliRBNm0LPy3Iu6qoQXOF0l2oH0eI3Mp68Fb5AePxI2dhU85dEe/ELjXry6ypyi+1zdzhf5qZtZsqBh1F0ciJPUaFsTZw+P3bewdlkZEHyyfO7p0Nl7r6TqJeq/dz94TBgfmpPdavK9XLfkH+KDZUoONjrZ66xhLFgfjIyCEC1ivlN7uoM6cnEZZLaPHpY7V5is9++TuDiAes1kGiUu83aXcQ+22d2PtQrFG9V6lfeushvyMHKwiPbg35jV3dGNjmR5FNJatbNsKu3S/qKHJ2ZHNYOPR6/voECjaHiapdMLKl1t+l23TrQKVwCPH5SLIthPqJuiLUnjV7/+e5K+Jvr5Q9GyoILKrbWxFmik9OYfQwPMSt" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq.sv b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq.sv new file mode 100644 index 0000000000..e068fa1bd5 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/altera_axi_bridge_1940/synth/cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq.sv @@ -0,0 +1,877 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// AXI Bridge +// +// Convert "incomplete" AXI3/4 slave-side interface to +// a "complete" AXI4 master-side interface +// +// Adapts between an AXI master and slave that +// are almost symmetric, with the following +// exceptions: +// +// the master's address width >= the slave's address width +// the master's id width <= the slave's id width +// ----------------------------------------- +`timescale 1 ns / 1 ns + +module cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq +#( + // ---------------- + // Interface parameters + // ---------------- + parameter S0_ID_WIDTH = 4, + M0_ID_WIDTH = 8, + ADDR_WIDTH = 32, + DATA_WIDTH = 32, + WRITE_ADDR_USER_WIDTH = 64, + READ_ADDR_USER_WIDTH = 64, + WRITE_DATA_USER_WIDTH = 64, + WRITE_RESP_USER_WIDTH = 64, + READ_DATA_USER_WIDTH = 64, + AXI_VERSION = "AXI4", + USE_PIPELINE = 0, + LOCK_WIDTH = 1, + BURST_LENGTH_WIDTH = 8, + SYNC_RESET = 0, + // --------------- + // Master parameters + // --------------- + USE_M0_AWID = 1, + USE_M0_AWREGION = 1, + USE_M0_AWLEN = 1, + USE_M0_AWSIZE = 1, + USE_M0_AWBURST = 1, + USE_M0_AWLOCK = 1, + USE_M0_AWCACHE = 1, + USE_M0_AWQOS = 1, + + USE_M0_ARID = 1, + USE_M0_ARREGION = 1, + USE_M0_ARLEN = 1, + USE_M0_ARSIZE = 1, + USE_M0_ARBURST = 1, + USE_M0_ARLOCK = 1, + USE_M0_ARCACHE = 1, + USE_M0_ARQOS = 1, + + USE_M0_WSTRB = 1, + + USE_M0_BID = 1, + USE_M0_BRESP = 1, + + USE_M0_RID = 1, + USE_M0_RRESP = 1, + USE_M0_RLAST = 1, + + USE_M0_ARUSER = 0, + USE_M0_AWUSER = 0, + USE_M0_WUSER = 0, + USE_M0_RUSER = 0, + USE_M0_BUSER = 0, + //----------------- + // Slave parameters + //----------------- + USE_S0_AWREGION = 1, + USE_S0_AWLOCK = 1, + USE_S0_AWCACHE = 1, + USE_S0_AWQOS = 1, + USE_S0_AWPROT = 1, + + USE_S0_ARREGION = 1, + USE_S0_ARLOCK = 1, + USE_S0_ARCACHE = 1, + USE_S0_ARQOS = 1, + USE_S0_ARPROT = 1, + + USE_S0_WLAST = 1, + + USE_S0_BRESP = 1, + + USE_S0_RRESP = 1, + + USE_S0_AWUSER = 0, + USE_S0_ARUSER = 0, + USE_S0_WUSER = 0, + USE_S0_RUSER = 0, + USE_S0_BUSER = 0, + + // ---------------- + // Derived parameters + // ---------------- + STROBE_WIDTH = DATA_WIDTH / 8, + BURST_SIZE = $clog2(STROBE_WIDTH), + + ACE_LITE_SUPPORT = 0, + BACKPRESSURE_DURING_RESET = 0 + +) +( + // ---------------- + // Clock & reset + // ---------------- + input aclk, + input aresetn, + + + // ---------------- + // Master-side AXI interface + // ---------------- + output reg [M0_ID_WIDTH-1:0] m0_awid, + output [ADDR_WIDTH-1:0] m0_awaddr, + output reg [BURST_LENGTH_WIDTH-1:0] m0_awlen, + output reg [2:0] m0_awsize, + output reg [1:0] m0_awburst, + output reg [LOCK_WIDTH-1:0] m0_awlock, + output reg [3:0] m0_awcache, + output reg [2:0] m0_awprot, + output [WRITE_ADDR_USER_WIDTH-1:0] m0_awuser, + output reg [3:0] m0_awqos, + output reg [3:0] m0_awregion, + output m0_awvalid, + input m0_awready, + + output reg [M0_ID_WIDTH-1:0] m0_wid, + output [DATA_WIDTH-1:0] m0_wdata, + output reg [STROBE_WIDTH-1:0] m0_wstrb, + output reg m0_wlast, + output m0_wvalid, + output [WRITE_DATA_USER_WIDTH-1:0] m0_wuser, + input m0_wready, + + input [M0_ID_WIDTH-1:0] m0_bid, + input [1:0] m0_bresp, + input [WRITE_RESP_USER_WIDTH-1:0] m0_buser, + input m0_bvalid, + output m0_bready, + + output reg [M0_ID_WIDTH-1:0] m0_arid, + output [ADDR_WIDTH-1:0] m0_araddr, + output reg [BURST_LENGTH_WIDTH-1:0] m0_arlen, + output reg [2:0] m0_arsize, + output reg [1:0] m0_arburst, + output reg [LOCK_WIDTH-1:0] m0_arlock, + output reg [3:0] m0_arcache, + output reg [2:0] m0_arprot, + output [READ_ADDR_USER_WIDTH-1:0] m0_aruser, + output reg [3:0] m0_arqos, + output reg [3:0] m0_arregion, + output m0_arvalid, + input m0_arready, + + input [M0_ID_WIDTH-1:0] m0_rid, + input [DATA_WIDTH-1:0] m0_rdata, + input [1:0] m0_rresp, + input [READ_DATA_USER_WIDTH-1:0] m0_ruser, + input m0_rlast, + input m0_rvalid, + output m0_rready, + + output [1:0] m0_ardomain, + output [3:0] m0_arsnoop, + output [1:0] m0_arbar, + + output [1:0] m0_awdomain, + output [2:0] m0_awsnoop, + output [1:0] m0_awbar, + output m0_awunique, + + + + // ---------------- + // Slave-side AXI interface + // ---------------- + input [S0_ID_WIDTH-1:0] s0_awid, + input [ADDR_WIDTH-1:0] s0_awaddr, + input [BURST_LENGTH_WIDTH-1:0] s0_awlen, + input [2:0] s0_awsize, + input [1:0] s0_awburst, + input [LOCK_WIDTH-1:0] s0_awlock, + input [3:0] s0_awcache, + input [2:0] s0_awprot, + input [WRITE_ADDR_USER_WIDTH-1:0] s0_awuser, + input [3:0] s0_awqos, + input [3:0] s0_awregion, + input s0_awvalid, + output s0_awready, + + input [S0_ID_WIDTH-1:0] s0_wid, + input [DATA_WIDTH-1:0] s0_wdata, + input [STROBE_WIDTH-1:0] s0_wstrb, + input s0_wlast, + input [WRITE_DATA_USER_WIDTH-1:0] s0_wuser, + input s0_wvalid, + output s0_wready, + + output reg [S0_ID_WIDTH-1:0] s0_bid, + output reg [1:0] s0_bresp, + output [WRITE_RESP_USER_WIDTH-1:0] s0_buser, + output s0_bvalid, + input s0_bready, + + input [S0_ID_WIDTH-1:0] s0_arid, + input [ADDR_WIDTH-1:0] s0_araddr, + input [BURST_LENGTH_WIDTH-1:0] s0_arlen, + input [2:0] s0_arsize, + input [1:0] s0_arburst, + input [LOCK_WIDTH-1:0] s0_arlock, + input [3:0] s0_arcache, + input [2:0] s0_arprot, + input [READ_ADDR_USER_WIDTH-1:0] s0_aruser, + input [3:0] s0_arqos, + input [3:0] s0_arregion, + input s0_arvalid, + output s0_arready, + + output reg [S0_ID_WIDTH-1:0] s0_rid, + output [DATA_WIDTH-1:0] s0_rdata, + output reg [1:0] s0_rresp, + output reg s0_rlast, + output [READ_DATA_USER_WIDTH-1:0] s0_ruser, + output s0_rvalid, + input s0_rready, + + input [1:0] s0_ardomain, + input [3:0] s0_arsnoop, + input [1:0] s0_arbar, + + input [1:0] s0_awdomain, + input [2:0] s0_awsnoop, + input [1:0] s0_awbar, + input s0_awunique +); + + + localparam AX_WIDTH = (AXI_VERSION == "AXI3")? + M0_ID_WIDTH+ADDR_WIDTH+BURST_LENGTH_WIDTH+3+2+LOCK_WIDTH+4+3+WRITE_ADDR_USER_WIDTH : + M0_ID_WIDTH+ADDR_WIDTH+BURST_LENGTH_WIDTH+3+2+LOCK_WIDTH+4+3+WRITE_ADDR_USER_WIDTH+4+4 ; + localparam W_WIDTH = (AXI_VERSION == "AXI3")? + M0_ID_WIDTH+DATA_WIDTH+ADDR_WIDTH+STROBE_WIDTH+1 : + M0_ID_WIDTH+DATA_WIDTH+ADDR_WIDTH+STROBE_WIDTH+1+WRITE_DATA_USER_WIDTH ; + + localparam B_WIDTH = (AXI_VERSION == "AXI3")? + M0_ID_WIDTH+2 : + M0_ID_WIDTH+2+WRITE_DATA_USER_WIDTH; + + localparam R_WIDTH = (AXI_VERSION == "AXI3")? + M0_ID_WIDTH+DATA_WIDTH+2+1 : + M0_ID_WIDTH+DATA_WIDTH+2+1+READ_DATA_USER_WIDTH; + + localparam ACE_W = (ACE_LITE_SUPPORT == 1) ? 8 : 0; + localparam ACE_R = (ACE_LITE_SUPPORT == 1) ? 8 : 0; + + localparam PKT_AXPROT_L = 0; + localparam PKT_AXPROT_H = PKT_AXPROT_L + 3 - 1; + localparam PKT_AXCACHE_L = PKT_AXPROT_H + 1; + localparam PKT_AXCACHE_H = PKT_AXCACHE_L + 4 -1; + localparam PKT_AXLOCK_L = PKT_AXCACHE_H + 1; + localparam PKT_AXLOCK_H = PKT_AXLOCK_L + LOCK_WIDTH - 1; + localparam PKT_AXBURST_L = PKT_AXLOCK_H + 1; + localparam PKT_AXBURST_H = PKT_AXBURST_L + 2 -1; + localparam PKT_AXSIZE_L = PKT_AXBURST_H + 1; + localparam PKT_AXSIZE_H = PKT_AXSIZE_L + 3 -1; + localparam PKT_AXLEN_L = PKT_AXSIZE_H + 1; + localparam PKT_AXLEN_H = PKT_AXLEN_L + BURST_LENGTH_WIDTH -1; + localparam PKT_AXADDR_L = PKT_AXLEN_H + 1; + localparam PKT_AXADDR_H = PKT_AXADDR_L + ADDR_WIDTH -1; + localparam PKT_AXID_L = PKT_AXADDR_H + 1; + localparam PKT_AXID_H = PKT_AXID_L + M0_ID_WIDTH -1; + localparam PKT_AXUSER_L = PKT_AXID_H + 1; + localparam PKT_AXUSER_H = PKT_AXUSER_L + WRITE_ADDR_USER_WIDTH -1; + localparam PKT_AXREGION_L = PKT_AXUSER_H + 1; + localparam PKT_AXREGION_H = PKT_AXREGION_L + 4 -1; + localparam PKT_AXQOS_L = PKT_AXREGION_H + 1; + localparam PKT_AXQOS_H = PKT_AXQOS_L + 4 - 1; + + localparam PKT_WLAST_L = 0; + localparam PKT_WLAST_H = PKT_WLAST_L +1 -1; + localparam PKT_WSTRB_L = PKT_WLAST_H + 1; + localparam PKT_WSTRB_H = PKT_WSTRB_L + STROBE_WIDTH -1; + localparam PKT_WDATA_L = PKT_WSTRB_H + 1; + localparam PKT_WDATA_H = PKT_WDATA_L + DATA_WIDTH -1; + localparam PKT_WID_L = PKT_WDATA_H + 1; + localparam PKT_WID_H = PKT_WID_L + M0_ID_WIDTH -1; + localparam PKT_WUSER_L = PKT_WID_H + 1; + localparam PKT_WUSER_H = PKT_WUSER_L + WRITE_DATA_USER_WIDTH -1; + + localparam PKT_BRESP_L = 0; + localparam PKT_BRESP_H = PKT_BRESP_L + 2 -1; + localparam PKT_BID_L = PKT_BRESP_H + 1; + localparam PKT_BID_H = PKT_BID_L + M0_ID_WIDTH -1; + localparam PKT_BUSER_L = PKT_BID_H + 1; + localparam PKT_BUSER_H = PKT_BUSER_L + WRITE_DATA_USER_WIDTH -1; + + localparam PKT_RLAST = 0; + localparam PKT_RRESP_L = 1; + localparam PKT_RRESP_H = PKT_RRESP_L + 2 -1; + localparam PKT_RDATA_L = PKT_RRESP_H + 1; + localparam PKT_RDATA_H = PKT_RDATA_L + DATA_WIDTH -1; + localparam PKT_RID_L = PKT_RDATA_H + 1; + localparam PKT_RID_H = PKT_RID_L + M0_ID_WIDTH -1; + localparam PKT_RUSER_L = PKT_RID_H + 1; + localparam PKT_RUSER_H = PKT_RUSER_L + READ_DATA_USER_WIDTH -1; + + reg [M0_ID_WIDTH-1:0] s0_pipe_awid; + reg [ADDR_WIDTH-1:0] s0_pipe_awaddr; + reg [BURST_LENGTH_WIDTH-1:0] s0_pipe_awlen; + reg [2:0] s0_pipe_awsize; + reg [1:0] s0_pipe_awburst; + reg [LOCK_WIDTH-1:0] s0_pipe_awlock; + reg [3:0] s0_pipe_awcache; + reg [2:0] s0_pipe_awprot; + reg [WRITE_ADDR_USER_WIDTH-1:0] s0_pipe_awuser; + reg [3:0] s0_pipe_awqos; + reg [3:0] s0_pipe_awregion; + wire s0_pipeout_awvalid; + wire s0_pipe_awready; + + reg [M0_ID_WIDTH-1:0] s0_pipe_arid; + reg [ADDR_WIDTH-1:0] s0_pipe_araddr; + reg [BURST_LENGTH_WIDTH-1:0] s0_pipe_arlen; + reg [2:0] s0_pipe_arsize; + reg [1:0] s0_pipe_arburst; + reg [LOCK_WIDTH-1:0] s0_pipe_arlock; + reg [3:0] s0_pipe_arcache; + reg [2:0] s0_pipe_arprot; + reg [WRITE_ADDR_USER_WIDTH-1:0] s0_pipe_aruser; + reg [3:0] s0_pipe_arqos; + reg [3:0] s0_pipe_arregion; + wire s0_pipeout_arvalid; + wire s0_pipe_arready; + + reg [M0_ID_WIDTH-1:0] s0_pipe_wid; + reg [DATA_WIDTH-1:0] s0_pipe_wdata; + reg [STROBE_WIDTH-1:0] s0_pipe_wstrb; + reg [0:0] s0_pipe_wlast; + reg [WRITE_DATA_USER_WIDTH-1:0] s0_pipe_wuser; + reg s0_pipeout_wvalid; + reg s0_pipe_wvalid; + reg s0_pipe_wready; + + reg [M0_ID_WIDTH-1:0] m0_pipe_bid; + reg [1:0] m0_pipe_bresp; + reg [WRITE_RESP_USER_WIDTH-1:0] m0_pipe_buser; + reg m0_pipeout_bvalid; + reg m0_pipe_bready; + + reg [M0_ID_WIDTH-1:0] m0_pipe_rid; + reg [DATA_WIDTH-1:0] m0_pipe_rdata; + reg [1:0] m0_pipe_rresp; + reg m0_pipe_rlast; + reg [WRITE_RESP_USER_WIDTH-1:0] m0_pipe_ruser; + reg m0_pipeout_rvalid; + reg m0_pipe_rready; + + + reg [AX_WIDTH-1:0] pipein_aw; + reg [AX_WIDTH-1:0] pipeout_aw; + reg [W_WIDTH-1:0] pipein_w; + reg [W_WIDTH-1:0] pipeout_w; + reg [AX_WIDTH-1:0] pipein_ar; + reg [AX_WIDTH-1:0] pipeout_ar; + reg [B_WIDTH-1:0] pipein_b; + reg [B_WIDTH-1:0] pipeout_b; + reg [R_WIDTH-1:0] pipein_r; + reg [R_WIDTH-1:0] pipeout_r; + + generate if(ACE_LITE_SUPPORT == 1) begin + wire [ACE_W - 1:0] pipein_ace_w; + wire [ACE_W - 1:0] pipeout_ace_w; + wire [ACE_R - 1:0] pipein_ace_r; + wire [ACE_R - 1:0] pipeout_ace_r; + + assign pipein_ace_w = { s0_awdomain, + s0_awsnoop, + s0_awbar, + s0_awunique + }; + + assign pipein_ace_r = { s0_ardomain, + s0_arsnoop, + s0_arbar + }; + + + if(USE_PIPELINE == 1) begin + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (ACE_W), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) ace_w_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (s0_wvalid), + .in_ready (), + .in_data (pipein_ace_w), + .out_valid (), + .out_ready (m0_wready), + .out_data (pipeout_ace_w) + ); + + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (ACE_W), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) ace_r_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (s0_arvalid), + .in_ready (), + .in_data (pipein_ace_r), + .out_valid (), + .out_ready (m0_arready), + .out_data (pipeout_ace_r) + ); + + end + else begin + assign pipeout_ace_r = pipein_ace_r; + assign pipeout_ace_w = pipein_ace_w; + end + + assign {m0_awdomain, m0_awsnoop, m0_awbar, m0_awunique} = pipeout_ace_w; + assign {m0_ardomain, m0_arsnoop, m0_arbar} = pipeout_ace_r; + end + endgenerate + +//================================================================== +// AW Channel signal propagation +// AXI4 has optional signals. Propagate a default value to the master-side interface if the slave-side interface does not have the signal. +//====================================================================== + always_comb + begin + if (AXI_VERSION == "AXI3") begin + s0_pipe_awid = s0_awid[M0_ID_WIDTH-1:0]; + s0_pipe_awaddr = s0_awaddr; + s0_pipe_awlen = s0_awlen; + s0_pipe_awsize = s0_awsize; + s0_pipe_awburst = s0_awburst; + s0_pipe_awlock = s0_awlock; + s0_pipe_awcache = s0_awcache; + s0_pipe_awprot = s0_awprot; + s0_pipe_awuser = s0_awuser[WRITE_ADDR_USER_WIDTH-1:0]; + end else begin + if (!USE_S0_AWREGION) + s0_pipe_awregion = '0; + else + s0_pipe_awregion = s0_awregion; + if (!USE_S0_AWLOCK) + s0_pipe_awlock = '0; + else + s0_pipe_awlock = s0_awlock; + if (!USE_S0_AWCACHE) + s0_pipe_awcache = '0; + else + s0_pipe_awcache = s0_awcache; + if (!USE_S0_AWQOS) + s0_pipe_awqos = '0; + else + s0_pipe_awqos = s0_awqos; + if (!USE_S0_AWPROT) + s0_pipe_awprot = '0; + else + s0_pipe_awprot = s0_awprot; + if (!USE_S0_AWUSER) + s0_pipe_awuser = '0; + else + s0_pipe_awuser = s0_awuser[WRITE_ADDR_USER_WIDTH-1:0]; + + // non-optional signals for slave-side interface -propagate these to master-side interface + s0_pipe_awid = s0_awid[M0_ID_WIDTH-1:0]; + s0_pipe_awaddr = s0_awaddr; + s0_pipe_awlen = s0_awlen; + s0_pipe_awsize = s0_awsize; + s0_pipe_awburst = s0_awburst; + end + end + + generate if (AXI_VERSION == "AXI3") begin + assign pipein_aw = {s0_pipe_awuser,s0_pipe_awid,s0_pipe_awaddr,s0_pipe_awlen,s0_pipe_awsize,s0_pipe_awburst,s0_pipe_awlock,s0_pipe_awcache,s0_pipe_awprot}; + end else begin + assign pipein_aw = {s0_pipe_awqos,s0_pipe_awregion,s0_pipe_awuser,s0_pipe_awid,s0_pipe_awaddr,s0_pipe_awlen,s0_pipe_awsize,s0_pipe_awburst,s0_pipe_awlock,s0_pipe_awcache,s0_pipe_awprot}; + end + endgenerate + + generate if (USE_PIPELINE) begin + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (AX_WIDTH), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) aw_channel_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (s0_awvalid), + .in_ready (s0_pipe_awready), + .in_data (pipein_aw), + .out_valid (s0_pipeout_awvalid), + .out_ready (m0_awready), + .out_data (pipeout_aw) + ); + assign m0_awvalid = s0_pipeout_awvalid; + assign s0_awready = s0_pipe_awready; + + end else begin + assign pipeout_aw = pipein_aw; + assign m0_awvalid = s0_awvalid; + assign s0_awready = m0_awready; + end + endgenerate + + assign m0_awuser = pipeout_aw[PKT_AXUSER_H:PKT_AXUSER_L]; + assign m0_awid = pipeout_aw[PKT_AXID_H:PKT_AXID_L]; + assign m0_awaddr = pipeout_aw[PKT_AXADDR_H:PKT_AXADDR_L]; + assign m0_awlen = pipeout_aw[PKT_AXLEN_H:PKT_AXLEN_L]; + assign m0_awsize = pipeout_aw[PKT_AXSIZE_H:PKT_AXSIZE_L]; + assign m0_awburst = pipeout_aw[PKT_AXBURST_H:PKT_AXBURST_L]; + assign m0_awlock = pipeout_aw[PKT_AXLOCK_H:PKT_AXLOCK_L]; + assign m0_awcache = pipeout_aw[PKT_AXCACHE_H:PKT_AXCACHE_L]; + assign m0_awprot = pipeout_aw[PKT_AXPROT_H:PKT_AXPROT_L]; + generate if (AXI_VERSION == "AXI4") begin + assign m0_awqos = pipeout_aw[PKT_AXQOS_H:PKT_AXQOS_L]; + assign m0_awregion = pipeout_aw[PKT_AXREGION_H:PKT_AXREGION_L]; + end + endgenerate + +//================================================================== +// W Channel signal propagation +// AXI4 has optional signals. Propagate a default value to the master-side interface if the slave-side interface does not have the signal. +//====================================================================== + + always_comb + begin + if (AXI_VERSION == "AXI3") begin + s0_pipe_wid = s0_wid[M0_ID_WIDTH-1:0]; + s0_pipe_wdata = s0_wdata; + s0_pipe_wstrb = s0_wstrb; + s0_pipe_wlast = s0_wlast; + end else begin + if (!USE_S0_WLAST) + s0_pipe_wlast = '1; + else + s0_pipe_wlast = s0_wlast; + if (!USE_S0_WUSER) + s0_pipe_wuser = '0; + else + s0_pipe_wuser = s0_wuser[WRITE_DATA_USER_WIDTH-1:0]; + // non-optional signals for slave-side interface -propagate these to master-side interface + s0_pipe_wid = s0_wid[M0_ID_WIDTH-1:0]; + s0_pipe_wdata = s0_wdata; + s0_pipe_wstrb = s0_wstrb; + end + end + + generate if (AXI_VERSION == "AXI3") begin + assign pipein_w = {s0_pipe_wid,s0_pipe_wdata,s0_pipe_wstrb,s0_pipe_wlast}; + end else begin + assign pipein_w = {s0_pipe_wuser,s0_pipe_wid,s0_pipe_wdata,s0_pipe_wstrb,s0_pipe_wlast}; + end + endgenerate + + generate if (USE_PIPELINE) begin + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (W_WIDTH), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) w_channel_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (s0_wvalid), + .in_ready (s0_pipe_wready), + .in_data (pipein_w), + .out_valid (s0_pipeout_wvalid), + .out_ready (m0_wready), + .out_data (pipeout_w) + ); + assign m0_wvalid = s0_pipeout_wvalid; + assign s0_wready = s0_pipe_wready; + + end else begin + assign pipeout_w = pipein_w; + assign m0_wvalid = s0_wvalid; + assign s0_wready = m0_wready; + end + endgenerate + + assign m0_wid = pipeout_w[PKT_WID_H:PKT_WID_L]; + assign m0_wdata = pipeout_w[PKT_WDATA_H:PKT_WDATA_L]; + assign m0_wstrb = pipeout_w[PKT_WSTRB_H:PKT_WSTRB_L]; + assign m0_wlast = pipeout_w[PKT_WLAST_H:PKT_WLAST_L]; + generate if (AXI_VERSION == "AXI4") begin + assign m0_wuser = pipeout_w[PKT_WUSER_H:PKT_WUSER_L]; + end + endgenerate + +//================================================================== +// B Channel signal propagation +// AXI4 has optional signals. Propagate a default value to the slave-side interface if the master-side interface does not have the signal. +//====================================================================== + + always_comb + begin + if (AXI_VERSION == "AXI3") begin + m0_pipe_bid = m0_bid; + m0_pipe_bresp = m0_bresp; + end else begin + if (!USE_M0_BID) + m0_pipe_bid = '0; + else + m0_pipe_bid = m0_bid; + if (!USE_M0_BRESP) + m0_pipe_bresp = '0; + else + m0_pipe_bresp = m0_bresp; + if (!USE_M0_BUSER) + m0_pipe_buser = '0; + else + m0_pipe_buser = m0_buser; + end + end + + generate if (AXI_VERSION == "AXI3") begin + assign pipein_b = {m0_pipe_bid,m0_pipe_bresp}; + end else begin + assign pipein_b = {m0_pipe_buser,m0_pipe_bid,m0_pipe_bresp}; + end + endgenerate + + generate if (USE_PIPELINE) begin + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (B_WIDTH), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) b_channel_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (m0_bvalid), + .in_ready (m0_pipe_bready), + .in_data (pipein_b), + .out_valid (m0_pipeout_bvalid), + .out_ready (s0_bready), + .out_data (pipeout_b) + ); + assign s0_bvalid = m0_pipeout_bvalid; + assign m0_bready = m0_pipe_bready; + + end else begin + assign pipeout_b = pipein_b; + assign s0_bvalid = m0_bvalid; + assign m0_bready = s0_bready; + end + endgenerate + + assign s0_bid = pipeout_b[PKT_BID_H:PKT_BID_L]; + assign s0_bresp = pipeout_b[PKT_BRESP_H:PKT_BRESP_L]; + generate if (AXI_VERSION == "AXI4") begin + assign s0_buser = pipeout_b[PKT_BUSER_H:PKT_BUSER_L]; + end + endgenerate + + +//================================================================== +// AR Channel signal propagation +// AXI4 has optional signals. Propagate a default value to the master-side interface if the slave-side interface does not have the signal. +//====================================================================== + always_comb + begin + if (AXI_VERSION == "AXI3") begin + s0_pipe_arid = s0_arid[M0_ID_WIDTH-1:0]; + s0_pipe_araddr = s0_araddr; + s0_pipe_arlen = s0_arlen; + s0_pipe_arsize = s0_arsize; + s0_pipe_arburst = s0_arburst; + s0_pipe_arlock = s0_arlock; + s0_pipe_arcache = s0_arcache; + s0_pipe_arprot = s0_arprot; + s0_pipe_aruser = s0_aruser; // addded user signal to support HPS. This is not within AXI3 spec. + end else begin + if (!USE_S0_ARREGION) + s0_pipe_arregion = '0; + else + s0_pipe_arregion = s0_arregion; + if (!USE_S0_ARLOCK) + s0_pipe_arlock = '0; + else + s0_pipe_arlock = s0_arlock; + if (!USE_S0_ARCACHE) + s0_pipe_arcache = '0; + else + s0_pipe_arcache = s0_arcache; + if (!USE_S0_ARQOS) + s0_pipe_arqos = '0; + else + s0_pipe_arqos = s0_arqos; + if (!USE_S0_ARPROT) + s0_pipe_arprot = '0; + else + s0_pipe_arprot = s0_arprot; + if (!USE_S0_ARUSER) + s0_pipe_aruser = '0; + else + s0_pipe_aruser = s0_aruser[READ_ADDR_USER_WIDTH-1:0]; + + // non-optional signals for slave-side interface -propagate these to master-side interface + s0_pipe_arid = s0_arid[M0_ID_WIDTH-1:0]; + s0_pipe_araddr = s0_araddr; + s0_pipe_arlen = s0_arlen; + s0_pipe_arsize = s0_arsize; + s0_pipe_arburst = s0_arburst; + end + end + + generate if (AXI_VERSION == "AXI3") begin + assign pipein_ar = {s0_pipe_aruser,s0_pipe_arid,s0_pipe_araddr,s0_pipe_arlen,s0_pipe_arsize,s0_pipe_arburst,s0_pipe_arlock,s0_pipe_arcache,s0_pipe_arprot}; + end else begin + assign pipein_ar = {s0_pipe_arqos,s0_pipe_arregion,s0_pipe_aruser,s0_pipe_arid,s0_pipe_araddr,s0_pipe_arlen,s0_pipe_arsize,s0_pipe_arburst,s0_pipe_arlock,s0_pipe_arcache,s0_pipe_arprot}; + end + endgenerate + + generate if (USE_PIPELINE) begin + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (AX_WIDTH), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) ar_channel_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (s0_arvalid), + .in_ready (s0_pipe_arready), + .in_data (pipein_ar), + .out_valid (s0_pipeout_arvalid), + .out_ready (m0_arready), + .out_data (pipeout_ar) + ); + assign m0_arvalid = s0_pipeout_arvalid; + assign s0_arready = s0_pipe_arready; + + end else begin + assign pipeout_ar = pipein_ar; + assign m0_arvalid = s0_arvalid; + assign s0_arready = m0_arready; + end + endgenerate + + assign m0_aruser = pipeout_ar[PKT_AXUSER_H:PKT_AXUSER_L]; + assign m0_arid = pipeout_ar[PKT_AXID_H:PKT_AXID_L]; + assign m0_araddr = pipeout_ar[PKT_AXADDR_H:PKT_AXADDR_L]; + assign m0_arlen = pipeout_ar[PKT_AXLEN_H:PKT_AXLEN_L]; + assign m0_arsize = pipeout_ar[PKT_AXSIZE_H:PKT_AXSIZE_L]; + assign m0_arburst = pipeout_ar[PKT_AXBURST_H:PKT_AXBURST_L]; + assign m0_arlock = pipeout_ar[PKT_AXLOCK_H:PKT_AXLOCK_L]; + assign m0_arcache = pipeout_ar[PKT_AXCACHE_H:PKT_AXCACHE_L]; + assign m0_arprot = pipeout_ar[PKT_AXPROT_H:PKT_AXPROT_L]; + generate if (AXI_VERSION == "AXI4") begin + assign m0_arqos = pipeout_ar[PKT_AXQOS_H:PKT_AXQOS_L]; + assign m0_arregion = pipeout_ar[PKT_AXREGION_H:PKT_AXREGION_L]; + end + endgenerate + +//================================================================== +// R Channel signal propagation +// AXI4 has optional signals. Propagate a default value to the slave-side interface if the master-side interface does not have the signal. +//====================================================================== + + always_comb + begin + if (AXI_VERSION == "AXI3") begin + m0_pipe_rid = m0_rid; + m0_pipe_rresp = m0_rresp; + m0_pipe_rlast = m0_rlast; + end else begin + if (!USE_M0_RID) + m0_pipe_rid = '0; + else + m0_pipe_rid = m0_rid; + if (!USE_M0_RRESP) + m0_pipe_rresp = '0; + else + m0_pipe_rresp = m0_rresp; + if (!USE_M0_RLAST) + m0_pipe_rlast = '0; + else + m0_pipe_rlast = m0_rlast; + if (!USE_M0_RUSER) + m0_pipe_ruser = '0; + else + m0_pipe_ruser = m0_ruser; + end + //non-optional signals + m0_pipe_rdata = m0_rdata; + end + + generate if (AXI_VERSION == "AXI3") begin + assign pipein_r = {m0_pipe_rid,m0_pipe_rdata,m0_pipe_rresp,m0_pipe_rlast}; + end else begin + assign pipein_r = {m0_pipe_ruser,m0_pipe_rid,m0_pipe_rdata,m0_pipe_rresp,m0_pipe_rlast}; + end + endgenerate + + generate if (USE_PIPELINE) begin + altera_avalon_st_pipeline_base #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (R_WIDTH), + .PIPELINE_READY (1), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) r_channel_pipeline ( + .clk (aclk), + .reset (~aresetn), + .in_valid (m0_rvalid), + .in_ready (m0_pipe_rready), + .in_data (pipein_r), + .out_valid (m0_pipeout_rvalid), + .out_ready (s0_rready), + .out_data (pipeout_r) + ); + assign s0_rvalid = m0_pipeout_rvalid; + assign m0_rready = m0_pipe_rready; + + end else begin + assign pipeout_r = pipein_r; + assign s0_rvalid = m0_rvalid; + assign m0_rready = s0_rready; + end + endgenerate + + assign s0_rid = pipeout_r[PKT_RID_H:PKT_RID_L]; + assign s0_rdata = pipeout_r[PKT_RDATA_H:PKT_RDATA_L]; + assign s0_rresp = pipeout_r[PKT_RRESP_H:PKT_RRESP_L]; + assign s0_rlast = pipeout_r[PKT_RLAST]; + generate if (AXI_VERSION == "AXI4") begin + assign s0_ruser = pipeout_r[PKT_RUSER_H:PKT_RUSER_L]; + end + endgenerate + +/* + generate if (AXI_VERSION == "AXI3") begin + assign {m0_awid,m0_awaddr,m0_awlen,m0_awsize,m0_awburst,m0_awlock,m0_awcache,m0_awprot} = pipeout_aw; + end else begin + //assign {m0_awuser,m0_awqos,m0_awregion,m0_awid,m0_awaddr,m0_awlen,m0_awsize,m0_awburst,m0_awlock,m0_awcache,m0_awprot} = pipeout_aw; + assign {m0_awid,m0_awaddr,m0_awlen,m0_awsize,m0_awburst,m0_awlock,m0_awcache,m0_awprot} = pipeout_aw; + end + endgenerate +*/ + +endmodule + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.bsf b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.bsf new file mode 100644 index 0000000000..514f7ef74c --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.bsf @@ -0,0 +1,626 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the Intel FPGA Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 304 1064) + (text "cva6_intel_axi_bridge_0" (rect 72 0 168 12)(font "SansSerif" (font_size 11))) + (text "inst" (rect 8 1048 20 1060)(font "Arial" )) + (port + (pt 0 76) + (input) + (text "aclk" (rect 0 0 15 12)(font "SansSerif" (font_size 8))) + (text "aclk" (rect 4 65 28 76)(font "SansSerif" (font_size 8))) + (line (pt 0 76)(pt 102 76)(line_width 1)) + ) + (port + (pt 0 126) + (input) + (text "aresetn" (rect 0 0 29 12)(font "SansSerif" (font_size 8))) + (text "aresetn" (rect 4 115 46 126)(font "SansSerif" (font_size 8))) + (line (pt 0 126)(pt 102 126)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "s0_awid[7..0]" (rect 0 0 51 12)(font "SansSerif" (font_size 8))) + (text "s0_awid[7..0]" (rect 4 165 82 176)(font "SansSerif" (font_size 8))) + (line (pt 0 176)(pt 102 176)(line_width 3)) + ) + (port + (pt 0 201) + (input) + (text "s0_awaddr[63..0]" (rect 0 0 68 12)(font "SansSerif" (font_size 8))) + (text "s0_awaddr[63..0]" (rect 4 190 100 201)(font "SansSerif" (font_size 8))) + (line (pt 0 201)(pt 102 201)(line_width 3)) + ) + (port + (pt 0 226) + (input) + (text "s0_awlen[7..0]" (rect 0 0 56 12)(font "SansSerif" (font_size 8))) + (text "s0_awlen[7..0]" (rect 4 215 88 226)(font "SansSerif" (font_size 8))) + (line (pt 0 226)(pt 102 226)(line_width 3)) + ) + (port + (pt 0 251) + (input) + (text "s0_awsize[2..0]" (rect 0 0 60 12)(font "SansSerif" (font_size 8))) + (text "s0_awsize[2..0]" (rect 4 240 94 251)(font "SansSerif" (font_size 8))) + (line (pt 0 251)(pt 102 251)(line_width 3)) + ) + (port + (pt 0 276) + (input) + (text "s0_awburst[1..0]" (rect 0 0 64 12)(font "SansSerif" (font_size 8))) + (text "s0_awburst[1..0]" (rect 4 265 100 276)(font "SansSerif" (font_size 8))) + (line (pt 0 276)(pt 102 276)(line_width 3)) + ) + (port + (pt 0 301) + (input) + (text "s0_awlock" (rect 0 0 41 12)(font "SansSerif" (font_size 8))) + (text "s0_awlock" (rect 4 290 58 301)(font "SansSerif" (font_size 8))) + (line (pt 0 301)(pt 102 301)(line_width 1)) + ) + (port + (pt 0 326) + (input) + (text "s0_awcache[3..0]" (rect 0 0 69 12)(font "SansSerif" (font_size 8))) + (text "s0_awcache[3..0]" (rect 4 315 100 326)(font "SansSerif" (font_size 8))) + (line (pt 0 326)(pt 102 326)(line_width 3)) + ) + (port + (pt 0 351) + (input) + (text "s0_awprot[2..0]" (rect 0 0 61 12)(font "SansSerif" (font_size 8))) + (text "s0_awprot[2..0]" (rect 4 340 94 351)(font "SansSerif" (font_size 8))) + (line (pt 0 351)(pt 102 351)(line_width 3)) + ) + (port + (pt 0 376) + (input) + (text "s0_awvalid" (rect 0 0 43 12)(font "SansSerif" (font_size 8))) + (text "s0_awvalid" (rect 4 365 64 376)(font "SansSerif" (font_size 8))) + (line (pt 0 376)(pt 102 376)(line_width 1)) + ) + (port + (pt 0 426) + (input) + (text "s0_wdata[63..0]" (rect 0 0 62 12)(font "SansSerif" (font_size 8))) + (text "s0_wdata[63..0]" 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(line (pt 304 551)(pt 204 551)(line_width 3)) + (line (pt 304 576)(pt 204 576)(line_width 3)) + (line (pt 304 601)(pt 204 601)(line_width 3)) + (line (pt 306 776)(pt 204 776)(line_width 1)) + (line (pt 306 801)(pt 204 801)(line_width 3)) + (line (pt 306 826)(pt 204 826)(line_width 3)) + (line (pt 306 851)(pt 204 851)(line_width 3)) + (line (pt 306 876)(pt 204 876)(line_width 1)) + (line (pt 306 901)(pt 204 901)(line_width 1)) + (line (pt 304 926)(pt 204 926)(line_width 1)) + (line (pt 203 55)(pt 203 930)(line_width 1)) + (line (pt 202 55)(pt 202 930)(line_width 1)) + (line (pt 0 0)(pt 304 0)(line_width 1)) + (line (pt 304 0)(pt 304 1068)(line_width 1)) + (line (pt 0 1068)(pt 304 1068)(line_width 1)) + (line (pt 0 0)(pt 0 1068)(line_width 1)) + ) +) diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.cmp b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.cmp new file mode 100644 index 0000000000..b451768eef --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.cmp @@ -0,0 +1,138 @@ + component cva6_intel_axi_bridge_0 is + generic ( + USE_PIPELINE : integer := 1; + USE_M0_AWID : integer := 1; + USE_M0_AWREGION : integer := 0; + USE_M0_AWLEN : integer := 1; + USE_M0_AWSIZE : integer := 1; + USE_M0_AWBURST : integer := 1; + USE_M0_AWLOCK : integer := 1; + USE_M0_AWCACHE : integer := 1; + USE_M0_AWQOS : integer := 0; + USE_S0_AWREGION : integer := 0; + USE_S0_AWLOCK : integer := 1; + USE_S0_AWCACHE : integer := 1; + USE_S0_AWQOS : integer := 0; + USE_S0_AWPROT : integer := 1; + USE_M0_WSTRB : integer := 1; + USE_S0_WLAST : integer := 1; + USE_M0_BID : integer := 1; + USE_M0_BRESP : integer := 1; + USE_S0_BRESP : integer := 1; + USE_M0_ARID : integer := 1; + USE_M0_ARREGION : integer := 0; + USE_M0_ARLEN : integer := 1; + USE_M0_ARSIZE : integer := 1; + USE_M0_ARBURST : integer := 1; + USE_M0_ARLOCK : integer := 1; + USE_M0_ARCACHE : integer := 1; + USE_M0_ARQOS : integer := 0; + USE_S0_ARREGION : integer := 0; + USE_S0_ARLOCK : integer := 1; + USE_S0_ARCACHE : integer := 1; + USE_S0_ARQOS : integer := 0; + USE_S0_ARPROT : integer := 1; + USE_M0_RID : integer := 1; + USE_M0_RRESP : integer := 1; + USE_M0_RLAST : integer := 1; + USE_S0_RRESP : integer := 1; + M0_ID_WIDTH : integer := 8; + S0_ID_WIDTH : integer := 8; + DATA_WIDTH : integer := 64; + WRITE_ADDR_USER_WIDTH : integer := 32; + READ_ADDR_USER_WIDTH : integer := 32; + WRITE_DATA_USER_WIDTH : integer := 32; + WRITE_RESP_USER_WIDTH : integer := 32; + READ_DATA_USER_WIDTH : integer := 32; + ADDR_WIDTH : integer := 64; + USE_S0_AWUSER : integer := 0; + USE_S0_ARUSER : integer := 0; + USE_S0_WUSER : integer := 0; + USE_S0_RUSER : integer := 0; + USE_S0_BUSER : integer := 0; + USE_M0_AWUSER : integer := 0; + USE_M0_ARUSER : integer := 0; + USE_M0_WUSER : integer := 0; + USE_M0_RUSER : integer := 0; + USE_M0_BUSER : integer := 0; + AXI_VERSION : string := "AXI4"; + ACE_LITE_SUPPORT : integer := 0; + SYNC_RESET : integer := 0; + BACKPRESSURE_DURING_RESET : integer := 0 + ); + port ( + aclk : in std_logic := 'X'; -- clk + aresetn : in std_logic := 'X'; -- reset_n + s0_awid : in std_logic_vector(7 downto 0) := (others => 'X'); -- awid + s0_awaddr : in std_logic_vector(63 downto 0) := (others => 'X'); -- awaddr + s0_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen + s0_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize + s0_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst + s0_awlock : in std_logic_vector(0 downto 0) := (others => 'X'); -- awlock + s0_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache + s0_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot + s0_awvalid : in std_logic := 'X'; -- awvalid + s0_awready : out std_logic; -- awready + s0_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- wdata + s0_wstrb : in std_logic_vector(7 downto 0) := (others => 'X'); -- wstrb + s0_wlast : in std_logic := 'X'; -- wlast + s0_wvalid : in std_logic := 'X'; -- wvalid + s0_wready : out std_logic; -- wready + s0_bid : out std_logic_vector(7 downto 0); -- bid + s0_bresp : out std_logic_vector(1 downto 0); -- bresp + s0_bvalid : out std_logic; -- bvalid + s0_bready : in std_logic := 'X'; -- bready + s0_arid : in std_logic_vector(7 downto 0) := (others => 'X'); -- arid + s0_araddr : in std_logic_vector(63 downto 0) := (others => 'X'); -- araddr + s0_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen + s0_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize + s0_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst + s0_arlock : in std_logic_vector(0 downto 0) := (others => 'X'); -- arlock + s0_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache + s0_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot + s0_arvalid : in std_logic := 'X'; -- arvalid + s0_arready : out std_logic; -- arready + s0_rid : out std_logic_vector(7 downto 0); -- rid + s0_rdata : out std_logic_vector(63 downto 0); -- rdata + s0_rresp : out std_logic_vector(1 downto 0); -- rresp + s0_rlast : out std_logic; -- rlast + s0_rvalid : out std_logic; -- rvalid + s0_rready : in std_logic := 'X'; -- rready + m0_awid : out std_logic_vector(7 downto 0); -- awid + m0_awaddr : out std_logic_vector(63 downto 0); -- awaddr + m0_awlen : out std_logic_vector(7 downto 0); -- awlen + m0_awsize : out std_logic_vector(2 downto 0); -- awsize + m0_awburst : out std_logic_vector(1 downto 0); -- awburst + m0_awlock : out std_logic_vector(0 downto 0); -- awlock + m0_awcache : out std_logic_vector(3 downto 0); -- awcache + m0_awprot : out std_logic_vector(2 downto 0); -- awprot + m0_awvalid : out std_logic; -- awvalid + m0_awready : in std_logic := 'X'; -- awready + m0_wdata : out std_logic_vector(63 downto 0); -- wdata + m0_wstrb : out std_logic_vector(7 downto 0); -- wstrb + m0_wlast : out std_logic; -- wlast + m0_wvalid : out std_logic; -- wvalid + m0_wready : in std_logic := 'X'; -- wready + m0_bid : in std_logic_vector(7 downto 0) := (others => 'X'); -- bid + m0_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp + m0_bvalid : in std_logic := 'X'; -- bvalid + m0_bready : out std_logic; -- bready + m0_arid : out std_logic_vector(7 downto 0); -- arid + m0_araddr : out std_logic_vector(63 downto 0); -- araddr + m0_arlen : out std_logic_vector(7 downto 0); -- arlen + m0_arsize : out std_logic_vector(2 downto 0); -- arsize + m0_arburst : out std_logic_vector(1 downto 0); -- arburst + m0_arlock : out std_logic_vector(0 downto 0); -- arlock + m0_arcache : out std_logic_vector(3 downto 0); -- arcache + m0_arprot : out std_logic_vector(2 downto 0); -- arprot + m0_arvalid : out std_logic; -- arvalid + m0_arready : in std_logic := 'X'; -- arready + m0_rid : in std_logic_vector(7 downto 0) := (others => 'X'); -- rid + m0_rdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- rdata + m0_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp + m0_rlast : in std_logic := 'X'; -- rlast + m0_rvalid : in std_logic := 'X'; -- rvalid + m0_rready : out std_logic -- rready + ); + end component cva6_intel_axi_bridge_0; + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.html b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.html new file mode 100644 index 0000000000..c6783b91b4 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.html @@ -0,0 +1,407 @@ + + + + + datasheet for cva6_intel_axi_bridge_0 + + + + + + + + +
cva6_intel_axi_bridge_0 +
+
+
+ + + + + +
2024.07.05.14:38:11Datasheet
+
+
Overview
+
+
+ + + + +
+
+
+
+
+
+
+
Memory Map
+ + + + + + + + + + + + + + + + +
+ axi_bridge_0 + +
 m0
  + axi_bridge_0 + +
s0 
+ +
+
+

axi_bridge_0

altera_axi_bridge v19.4.0 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
USE_M0_AWID1
USE_M0_AWREGION0
USE_M0_AWLEN1
USE_M0_AWSIZE1
USE_M0_AWBURST1
USE_M0_AWLOCK1
USE_M0_AWCACHE1
USE_M0_AWQOS0
USE_S0_AWREGION0
USE_S0_AWLOCK1
USE_S0_AWCACHE1
USE_S0_AWQOS0
USE_S0_AWPROT1
USE_M0_WSTRB1
USE_S0_WLAST1
USE_M0_BID1
USE_M0_BRESP1
USE_S0_BRESP1
USE_M0_ARID1
USE_M0_ARREGION0
USE_M0_ARLEN1
USE_M0_ARSIZE1
USE_M0_ARBURST1
USE_M0_ARLOCK1
USE_M0_ARCACHE1
USE_M0_ARQOS0
USE_S0_ARREGION0
USE_S0_ARLOCK1
USE_S0_ARCACHE1
USE_S0_ARQOS0
USE_S0_ARPROT1
USE_M0_RID1
USE_M0_RRESP1
USE_M0_RLAST1
USE_S0_RRESP1
M0_ID_WIDTH8
S0_ID_WIDTH8
DATA_WIDTH64
WRITE_ADDR_USER_WIDTH32
READ_ADDR_USER_WIDTH32
WRITE_DATA_USER_WIDTH32
WRITE_RESP_USER_WIDTH32
READ_DATA_USER_WIDTH32
ADDR_WIDTH64
USE_S0_AWUSER0
USE_S0_ARUSER0
USE_S0_WUSER0
USE_S0_RUSER0
USE_S0_BUSER0
USE_M0_AWUSER0
USE_M0_ARUSER0
USE_M0_WUSER0
USE_M0_RUSER0
USE_M0_BUSER0
AXI_VERSIONAXI4
WRITE_ISSUING_CAPABILITY16
READ_ISSUING_CAPABILITY16
COMBINED_ISSUING_CAPABILITY16
WRITE_ACCEPTANCE_CAPABILITY16
READ_ACCEPTANCE_CAPABILITY16
COMBINED_ACCEPTANCE_CAPABILITY16
ACE_LITE_SUPPORT0
SYNC_RESET0
BACKPRESSURE_DURING_RESET0
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.01 seconds
+ + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qgsynthc b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qgsynthc new file mode 100644 index 0000000000..0290562596 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qgsynthc @@ -0,0 +1,316 @@ + + + cva6_intel_axi_bridge_0 + + + + cva6_intel_axi_bridge_0 + 1.0 + cva6_intel_axi_bridge_0 + cva6_intel_axi_bridge_0 + 0 + + + + + axi_bridge_0 + + + + ACE_LITE_SUPPORT + 0 + + + ADDR_WIDTH + 64 + + + AXI_VERSION + AXI4 + + + BACKPRESSURE_DURING_RESET + 0 + + + BURST_LENGTH_WIDTH + 8 + + + COMBINED_ACCEPTANCE_CAPABILITY + 16 + + + COMBINED_ISSUING_CAPABILITY + 16 + + + DATA_WIDTH + 64 + + + ENABLE_CONCURRENT_SUBORDINATE_ACCESS + 0 + + + ENABLE_OOO + 0 + + + LOCK_WIDTH + 1 + + + M0_ID_WIDTH + 8 + + + NO_REPEATED_IDS_BETWEEN_SUBORDINATES + 0 + + + READ_ACCEPTANCE_CAPABILITY + 16 + + + READ_ADDR_USER_WIDTH + 32 + + + READ_DATA_REORDERING_DEPTH + 1 + + + READ_DATA_USER_WIDTH + 32 + + + READ_ISSUING_CAPABILITY + 16 + + + S0_ID_WIDTH + 8 + + + SYNC_RESET + 0 + + + USE_M0_ARBURST + 1 + + + USE_M0_ARCACHE + 1 + + + USE_M0_ARID + 1 + + + USE_M0_ARLEN + 1 + + + USE_M0_ARLOCK + 1 + + + USE_M0_ARQOS + 0 + + + USE_M0_ARREGION + 0 + + + USE_M0_ARSIZE + 1 + + + USE_M0_ARUSER + 0 + + + USE_M0_AWBURST + 1 + + + USE_M0_AWCACHE + 1 + + + USE_M0_AWID + 1 + + + USE_M0_AWLEN + 1 + + + USE_M0_AWLOCK + 1 + + + USE_M0_AWQOS + 0 + + + USE_M0_AWREGION + 0 + + + USE_M0_AWSIZE + 1 + + + USE_M0_AWUSER + 0 + + + USE_M0_BID + 1 + + + USE_M0_BRESP + 1 + + + USE_M0_BUSER + 0 + + + USE_M0_RID + 1 + + + USE_M0_RLAST + 1 + + + USE_M0_RRESP + 1 + + + USE_M0_RUSER + 0 + + + USE_M0_WSTRB + 1 + + + USE_M0_WUSER + 0 + + + USE_PIPELINE + 1 + + + USE_S0_ARCACHE + 1 + + + USE_S0_ARLOCK + 1 + + + USE_S0_ARPROT + 1 + + + USE_S0_ARQOS + 0 + + + USE_S0_ARREGION + 0 + + + USE_S0_ARUSER + 0 + + + USE_S0_AWCACHE + 1 + + + USE_S0_AWLOCK + 1 + + + USE_S0_AWPROT + 1 + + + USE_S0_AWQOS + 0 + + + USE_S0_AWREGION + 0 + + + USE_S0_AWUSER + 0 + + + USE_S0_BRESP + 1 + + + USE_S0_BUSER + 0 + + + USE_S0_RRESP + 1 + + + USE_S0_RUSER + 0 + + + USE_S0_WLAST + 1 + + + USE_S0_WUSER + 0 + + + WRITE_ACCEPTANCE_CAPABILITY + 16 + + + WRITE_ADDR_USER_WIDTH + 32 + + + WRITE_DATA_USER_WIDTH + 32 + + + WRITE_ISSUING_CAPABILITY + 16 + + + WRITE_RESP_USER_WIDTH + 32 + + + + altera_axi_bridge + 19.4.0 + axi_bridge_0 + cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq + 0 + + cva6_intel_axi_bridge_0.axi_bridge_0 + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qip b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qip new file mode 100644 index 0000000000..7077674ed2 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.qip @@ -0,0 +1,41 @@ +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_TOOL_VERSION "24.1" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_axi_bridge" +set_global_assignment -library "cva6_intel_axi_bridge_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "cva6_intel_axi_bridge_0.sopcinfo"] +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name SLD_INFO "QSYS_NAME cva6_intel_axi_bridge_0 HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "cva6_intel_axi_bridge_0" -name MISC_FILE [file join $::quartus(qip_path) "cva6_intel_axi_bridge_0.cmp"] +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 7" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 7}" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "cva6_intel_axi_bridge_0" -name MISC_FILE [file join $::quartus(qip_path) "../cva6_intel_axi_bridge_0.ip"] + +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_NAME "Y3ZhNl9pbnRlbF9heGlfYnJpZGdlXzBfYWx0ZXJhX2F4aV9icmlkZ2VfMTk0MF83MnN0Znlx" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_DISPLAY_NAME "QVhJIEJyaWRnZSBJbnRlbCBGUEdBIElQ" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_VERSION "MTkuNC4w" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_DESCRIPTION "QVhJL0FIQiBicmlkZ2UgZm9yIG5ldHdvcmsgdG9wb2xvZ3kgZGV0ZXJtaW5hdGlvbg==" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL01lbW9yeSBNYXBwZWQ=" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY=" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_COMPONENT_NAME "Y3ZhNl9pbnRlbF9heGlfYnJpZGdlXzA=" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "cva6_intel_axi_bridge_0" -library "cva6_intel_axi_bridge_0" -name IP_COMPONENT_VERSION "MS4w" + + +set_global_assignment -library "altera_axi_bridge_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_axi_bridge_1940/synth/cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq.sv"] +set_global_assignment -library "altera_axi_bridge_1940" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_axi_bridge_1940/synth/altera_avalon_st_pipeline_base.v"] +set_global_assignment -library "cva6_intel_axi_bridge_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/cva6_intel_axi_bridge_0.v"] + + +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_TOOL_NAME "altera_axi_bridge" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_TOOL_VERSION "19.4.0" +set_global_assignment -entity "cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" -library "altera_axi_bridge_1940" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.sopcinfo b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.sopcinfo new file mode 100644 index 0000000000..77516c18bd --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.sopcinfo @@ -0,0 +1,1689 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + default + false + true + false + true + BOARD + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + com.altera.entityinterfaces.moduleext.AddressMap + + false + true + false + true + ADDRESS_MAP + m0 + + + com.altera.entityinterfaces.moduleext.AddressWidthType + -1 + false + true + false + true + ADDRESS_WIDTH + m0 + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + embeddedsw.dts.compatible + simple-bus + + + embeddedsw.dts.group + bridge + + + embeddedsw.dts.name + bridge + + + embeddedsw.dts.vendor + altr + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 64 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 64 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + AXI4 + false + true + true + true + + + int + 8 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 16 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + false + + aclk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + false + + aresetn + Input + 1 + reset_n + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Integer + 1 + false + true + false + true + + + java.lang.Integer + 1 + false + true + false + true + + + java.lang.Integer + 1 + false + true + false + true + + + java.lang.Integer + 16 + false + true + true + true + + + java.lang.Integer + 16 + false + true + true + true + + + java.lang.Integer + 16 + false + true + true + true + + + java.lang.Integer + 1 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + axi_bridge_0.m0 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 35 + false + true + true + true + + + java.lang.Integer + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.math.BigInteger + 18446744073709551616 + true + true + false + true + + axi4 + 18446744073709551616 + false + + s0_awid + Input + 8 + awid + + + s0_awaddr + Input + 64 + awaddr + + + s0_awlen + Input + 8 + awlen + + + s0_awsize + Input + 3 + awsize + + + s0_awburst + Input + 2 + awburst + + + s0_awlock + Input + 1 + awlock + + + s0_awcache + Input + 4 + awcache + + + s0_awprot + Input + 3 + awprot + + + s0_awvalid + Input + 1 + awvalid + + + s0_awready + Output + 1 + awready + + + s0_wdata + Input + 64 + wdata + + + s0_wstrb + Input + 8 + wstrb + + + s0_wlast + Input + 1 + wlast + + + s0_wvalid + Input + 1 + wvalid + + + s0_wready + Output + 1 + wready + + + s0_bid + Output + 8 + bid + + + s0_bresp + Output + 2 + bresp + + + s0_bvalid + Output + 1 + bvalid + + + s0_bready + Input + 1 + bready + + + s0_arid + Input + 8 + arid + + + s0_araddr + Input + 64 + araddr + + + s0_arlen + Input + 8 + arlen + + + s0_arsize + Input + 3 + arsize + + + s0_arburst + Input + 2 + arburst + + + s0_arlock + Input + 1 + arlock + + + s0_arcache + Input + 4 + arcache + + + s0_arprot + Input + 3 + arprot + + + s0_arvalid + Input + 1 + arvalid + + + s0_arready + Output + 1 + arready + + + s0_rid + Output + 8 + rid + + + s0_rdata + Output + 64 + rdata + + + s0_rresp + Output + 2 + rresp + + + s0_rlast + Output + 1 + rlast + + + s0_rvalid + Output + 1 + rvalid + + + s0_rready + Input + 1 + rready + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_reset + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Integer + 1 + false + true + false + true + + + java.lang.Integer + 1 + false + true + false + true + + + java.lang.Integer + 1 + false + true + false + true + + + java.lang.Integer + 16 + false + true + true + true + + + java.lang.Integer + 16 + false + true + true + true + + + java.lang.Integer + 16 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + axi4 + 18446744073709551616 + true + + m0_awid + Output + 8 + awid + + + m0_awaddr + Output + 64 + awaddr + + + m0_awlen + Output + 8 + awlen + + + m0_awsize + Output + 3 + awsize + + + m0_awburst + Output + 2 + awburst + + + m0_awlock + Output + 1 + awlock + + + m0_awcache + Output + 4 + awcache + + + m0_awprot + Output + 3 + awprot + + + m0_awvalid + Output + 1 + awvalid + + + m0_awready + Input + 1 + awready + + + m0_wdata + Output + 64 + wdata + + + m0_wstrb + Output + 8 + wstrb + + + m0_wlast + Output + 1 + wlast + + + m0_wvalid + Output + 1 + wvalid + + + m0_wready + Input + 1 + wready + + + m0_bid + Input + 8 + bid + + + m0_bresp + Input + 2 + bresp + + + m0_bvalid + Input + 1 + bvalid + + + m0_bready + Output + 1 + bready + + + m0_arid + Output + 8 + arid + + + m0_araddr + Output + 64 + araddr + + + m0_arlen + Output + 8 + arlen + + + m0_arsize + Output + 3 + arsize + + + m0_arburst + Output + 2 + arburst + + + m0_arlock + Output + 1 + arlock + + + m0_arcache + Output + 4 + arcache + + + m0_arprot + Output + 3 + arprot + + + m0_arvalid + Output + 1 + arvalid + + + m0_arready + Input + 1 + arready + + + m0_rid + Input + 8 + rid + + + m0_rdata + Input + 64 + rdata + + + m0_rresp + Input + 2 + rresp + + + m0_rlast + Input + 1 + rlast + + + m0_rvalid + Input + 1 + rvalid + + + m0_rready + Output + 1 + rready + + + + + 1 + altera_axi_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + AXI Bridge Intel FPGA IP + 19.4.0 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 24.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 24.1 + + + 1 + altera_axi4_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + AXI4 Subordinate + 24.1 + + + 1 + altera_axi4_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + AXI4 Manager + 24.1 + + 24.1 115 + + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.xml b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.xml new file mode 100644 index 0000000000..5299e732a8 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0.xml @@ -0,0 +1,270 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: cva6_intel_axi_bridge_0" + "Generating: cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" + + + + + + + + + + + + + + + + + + + + "Generating: cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" + + + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_bb.v b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_bb.v new file mode 100644 index 0000000000..5199082fab --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_bb.v @@ -0,0 +1,136 @@ +module cva6_intel_axi_bridge_0 #( + parameter USE_PIPELINE = 1, + parameter USE_M0_AWID = 1, + parameter USE_M0_AWREGION = 0, + parameter USE_M0_AWLEN = 1, + parameter USE_M0_AWSIZE = 1, + parameter USE_M0_AWBURST = 1, + parameter USE_M0_AWLOCK = 1, + parameter USE_M0_AWCACHE = 1, + parameter USE_M0_AWQOS = 0, + parameter USE_S0_AWREGION = 0, + parameter USE_S0_AWLOCK = 1, + parameter USE_S0_AWCACHE = 1, + parameter USE_S0_AWQOS = 0, + parameter USE_S0_AWPROT = 1, + parameter USE_M0_WSTRB = 1, + parameter USE_S0_WLAST = 1, + parameter USE_M0_BID = 1, + parameter USE_M0_BRESP = 1, + parameter USE_S0_BRESP = 1, + parameter USE_M0_ARID = 1, + parameter USE_M0_ARREGION = 0, + parameter USE_M0_ARLEN = 1, + parameter USE_M0_ARSIZE = 1, + parameter USE_M0_ARBURST = 1, + parameter USE_M0_ARLOCK = 1, + parameter USE_M0_ARCACHE = 1, + parameter USE_M0_ARQOS = 0, + parameter USE_S0_ARREGION = 0, + parameter USE_S0_ARLOCK = 1, + parameter USE_S0_ARCACHE = 1, + parameter USE_S0_ARQOS = 0, + parameter USE_S0_ARPROT = 1, + parameter USE_M0_RID = 1, + parameter USE_M0_RRESP = 1, + parameter USE_M0_RLAST = 1, + parameter USE_S0_RRESP = 1, + parameter M0_ID_WIDTH = 8, + parameter S0_ID_WIDTH = 8, + parameter DATA_WIDTH = 64, + parameter WRITE_ADDR_USER_WIDTH = 32, + parameter READ_ADDR_USER_WIDTH = 32, + parameter WRITE_DATA_USER_WIDTH = 32, + parameter WRITE_RESP_USER_WIDTH = 32, + parameter READ_DATA_USER_WIDTH = 32, + parameter ADDR_WIDTH = 64, + parameter USE_S0_AWUSER = 0, + parameter USE_S0_ARUSER = 0, + parameter USE_S0_WUSER = 0, + parameter USE_S0_RUSER = 0, + parameter USE_S0_BUSER = 0, + parameter USE_M0_AWUSER = 0, + parameter USE_M0_ARUSER = 0, + parameter USE_M0_WUSER = 0, + parameter USE_M0_RUSER = 0, + parameter USE_M0_BUSER = 0, + parameter AXI_VERSION = "AXI4", + parameter ACE_LITE_SUPPORT = 0, + parameter SYNC_RESET = 0, + parameter BACKPRESSURE_DURING_RESET = 0 + ) ( + input wire aclk, // clk.clk + input wire aresetn, // clk_reset.reset_n + input wire [7:0] s0_awid, // s0.awid + input wire [63:0] s0_awaddr, // .awaddr + input wire [7:0] s0_awlen, // .awlen + input wire [2:0] s0_awsize, // .awsize + input wire [1:0] s0_awburst, // .awburst + input wire [0:0] s0_awlock, // .awlock + input wire [3:0] s0_awcache, // .awcache + input wire [2:0] s0_awprot, // .awprot + input wire s0_awvalid, // .awvalid + output wire s0_awready, // .awready + input wire [63:0] s0_wdata, // .wdata + input wire [7:0] s0_wstrb, // .wstrb + input wire s0_wlast, // .wlast + input wire s0_wvalid, // .wvalid + output wire s0_wready, // .wready + output wire [7:0] s0_bid, // .bid + output wire [1:0] s0_bresp, // .bresp + output wire s0_bvalid, // .bvalid + input wire s0_bready, // .bready + input wire [7:0] s0_arid, // .arid + input wire [63:0] s0_araddr, // .araddr + input wire [7:0] s0_arlen, // .arlen + input wire [2:0] s0_arsize, // .arsize + input wire [1:0] s0_arburst, // .arburst + input wire [0:0] s0_arlock, // .arlock + input wire [3:0] s0_arcache, // .arcache + input wire [2:0] s0_arprot, // .arprot + input wire s0_arvalid, // .arvalid + output wire s0_arready, // .arready + output wire [7:0] s0_rid, // .rid + output wire [63:0] s0_rdata, // .rdata + output wire [1:0] s0_rresp, // .rresp + output wire s0_rlast, // .rlast + output wire s0_rvalid, // .rvalid + input wire s0_rready, // .rready + output wire [7:0] m0_awid, // m0.awid + output wire [63:0] m0_awaddr, // .awaddr + output wire [7:0] m0_awlen, // .awlen + output wire [2:0] m0_awsize, // .awsize + output wire [1:0] m0_awburst, // .awburst + output wire [0:0] m0_awlock, // .awlock + output wire [3:0] m0_awcache, // .awcache + output wire [2:0] m0_awprot, // .awprot + output wire m0_awvalid, // .awvalid + input wire m0_awready, // .awready + output wire [63:0] m0_wdata, // .wdata + output wire [7:0] m0_wstrb, // .wstrb + output wire m0_wlast, // .wlast + output wire m0_wvalid, // .wvalid + input wire m0_wready, // .wready + input wire [7:0] m0_bid, // .bid + input wire [1:0] m0_bresp, // .bresp + input wire m0_bvalid, // .bvalid + output wire m0_bready, // .bready + output wire [7:0] m0_arid, // .arid + output wire [63:0] m0_araddr, // .araddr + output wire [7:0] m0_arlen, // .arlen + output wire [2:0] m0_arsize, // .arsize + output wire [1:0] m0_arburst, // .arburst + output wire [0:0] m0_arlock, // .arlock + output wire [3:0] m0_arcache, // .arcache + output wire [2:0] m0_arprot, // .arprot + output wire m0_arvalid, // .arvalid + input wire m0_arready, // .arready + input wire [7:0] m0_rid, // .rid + input wire [63:0] m0_rdata, // .rdata + input wire [1:0] m0_rresp, // .rresp + input wire m0_rlast, // .rlast + input wire m0_rvalid, // .rvalid + output wire m0_rready // .rready + ); +endmodule + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_generation.rpt b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_generation.rpt new file mode 100644 index 0000000000..0c5a478182 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_generation.rpt @@ -0,0 +1,14 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_axi_bridge_0.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_axi_bridge_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_axi_bridge_0.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_axi_bridge_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: cva6_intel_axi_bridge_0: "Transforming system: cva6_intel_axi_bridge_0" +Info: cva6_intel_axi_bridge_0: "Naming system components in system: cva6_intel_axi_bridge_0" +Info: cva6_intel_axi_bridge_0: "Processing generation queue" +Info: cva6_intel_axi_bridge_0: "Generating: cva6_intel_axi_bridge_0" +Info: cva6_intel_axi_bridge_0: "Generating: cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq" +Info: cva6_intel_axi_bridge_0: Done "cva6_intel_axi_bridge_0" with 2 modules, 3 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_inst.v b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_inst.v new file mode 100644 index 0000000000..28ec9701f0 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_inst.v @@ -0,0 +1,135 @@ + cva6_intel_axi_bridge_0 #( + .USE_PIPELINE (INTEGER_VALUE_FOR_USE_PIPELINE), + .USE_M0_AWID (INTEGER_VALUE_FOR_USE_M0_AWID), + .USE_M0_AWREGION (INTEGER_VALUE_FOR_USE_M0_AWREGION), + .USE_M0_AWLEN (INTEGER_VALUE_FOR_USE_M0_AWLEN), + .USE_M0_AWSIZE (INTEGER_VALUE_FOR_USE_M0_AWSIZE), + .USE_M0_AWBURST (INTEGER_VALUE_FOR_USE_M0_AWBURST), + .USE_M0_AWLOCK (INTEGER_VALUE_FOR_USE_M0_AWLOCK), + .USE_M0_AWCACHE (INTEGER_VALUE_FOR_USE_M0_AWCACHE), + .USE_M0_AWQOS (INTEGER_VALUE_FOR_USE_M0_AWQOS), + .USE_S0_AWREGION (INTEGER_VALUE_FOR_USE_S0_AWREGION), + .USE_S0_AWLOCK (INTEGER_VALUE_FOR_USE_S0_AWLOCK), + .USE_S0_AWCACHE (INTEGER_VALUE_FOR_USE_S0_AWCACHE), + .USE_S0_AWQOS (INTEGER_VALUE_FOR_USE_S0_AWQOS), + .USE_S0_AWPROT (INTEGER_VALUE_FOR_USE_S0_AWPROT), + .USE_M0_WSTRB (INTEGER_VALUE_FOR_USE_M0_WSTRB), + .USE_S0_WLAST (INTEGER_VALUE_FOR_USE_S0_WLAST), + .USE_M0_BID (INTEGER_VALUE_FOR_USE_M0_BID), + .USE_M0_BRESP (INTEGER_VALUE_FOR_USE_M0_BRESP), + .USE_S0_BRESP (INTEGER_VALUE_FOR_USE_S0_BRESP), + .USE_M0_ARID (INTEGER_VALUE_FOR_USE_M0_ARID), + .USE_M0_ARREGION (INTEGER_VALUE_FOR_USE_M0_ARREGION), + .USE_M0_ARLEN (INTEGER_VALUE_FOR_USE_M0_ARLEN), + .USE_M0_ARSIZE (INTEGER_VALUE_FOR_USE_M0_ARSIZE), + .USE_M0_ARBURST (INTEGER_VALUE_FOR_USE_M0_ARBURST), + .USE_M0_ARLOCK (INTEGER_VALUE_FOR_USE_M0_ARLOCK), + .USE_M0_ARCACHE (INTEGER_VALUE_FOR_USE_M0_ARCACHE), + .USE_M0_ARQOS (INTEGER_VALUE_FOR_USE_M0_ARQOS), + .USE_S0_ARREGION (INTEGER_VALUE_FOR_USE_S0_ARREGION), + .USE_S0_ARLOCK (INTEGER_VALUE_FOR_USE_S0_ARLOCK), + .USE_S0_ARCACHE (INTEGER_VALUE_FOR_USE_S0_ARCACHE), + .USE_S0_ARQOS (INTEGER_VALUE_FOR_USE_S0_ARQOS), + .USE_S0_ARPROT (INTEGER_VALUE_FOR_USE_S0_ARPROT), + .USE_M0_RID (INTEGER_VALUE_FOR_USE_M0_RID), + .USE_M0_RRESP (INTEGER_VALUE_FOR_USE_M0_RRESP), + .USE_M0_RLAST (INTEGER_VALUE_FOR_USE_M0_RLAST), + .USE_S0_RRESP (INTEGER_VALUE_FOR_USE_S0_RRESP), + .M0_ID_WIDTH (INTEGER_VALUE_FOR_M0_ID_WIDTH), + .S0_ID_WIDTH (INTEGER_VALUE_FOR_S0_ID_WIDTH), + .DATA_WIDTH (INTEGER_VALUE_FOR_DATA_WIDTH), + .WRITE_ADDR_USER_WIDTH (INTEGER_VALUE_FOR_WRITE_ADDR_USER_WIDTH), + .READ_ADDR_USER_WIDTH (INTEGER_VALUE_FOR_READ_ADDR_USER_WIDTH), + .WRITE_DATA_USER_WIDTH (INTEGER_VALUE_FOR_WRITE_DATA_USER_WIDTH), + .WRITE_RESP_USER_WIDTH (INTEGER_VALUE_FOR_WRITE_RESP_USER_WIDTH), + .READ_DATA_USER_WIDTH (INTEGER_VALUE_FOR_READ_DATA_USER_WIDTH), + .ADDR_WIDTH (INTEGER_VALUE_FOR_ADDR_WIDTH), + .USE_S0_AWUSER (INTEGER_VALUE_FOR_USE_S0_AWUSER), + .USE_S0_ARUSER (INTEGER_VALUE_FOR_USE_S0_ARUSER), + .USE_S0_WUSER (INTEGER_VALUE_FOR_USE_S0_WUSER), + .USE_S0_RUSER (INTEGER_VALUE_FOR_USE_S0_RUSER), + .USE_S0_BUSER (INTEGER_VALUE_FOR_USE_S0_BUSER), + .USE_M0_AWUSER (INTEGER_VALUE_FOR_USE_M0_AWUSER), + .USE_M0_ARUSER (INTEGER_VALUE_FOR_USE_M0_ARUSER), + .USE_M0_WUSER (INTEGER_VALUE_FOR_USE_M0_WUSER), + .USE_M0_RUSER (INTEGER_VALUE_FOR_USE_M0_RUSER), + .USE_M0_BUSER (INTEGER_VALUE_FOR_USE_M0_BUSER), + .AXI_VERSION (STRING_VALUE_FOR_AXI_VERSION), + .ACE_LITE_SUPPORT (INTEGER_VALUE_FOR_ACE_LITE_SUPPORT), + .SYNC_RESET (INTEGER_VALUE_FOR_SYNC_RESET), + .BACKPRESSURE_DURING_RESET (INTEGER_VALUE_FOR_BACKPRESSURE_DURING_RESET) + ) u0 ( + .aclk (_connected_to_aclk_), // input, width = 1, clk.clk + .aresetn (_connected_to_aresetn_), // input, width = 1, clk_reset.reset_n + .s0_awid (_connected_to_s0_awid_), // input, width = 8, s0.awid + .s0_awaddr (_connected_to_s0_awaddr_), // input, width = 64, .awaddr + .s0_awlen (_connected_to_s0_awlen_), // input, width = 8, .awlen + .s0_awsize (_connected_to_s0_awsize_), // input, width = 3, .awsize + .s0_awburst (_connected_to_s0_awburst_), // input, width = 2, .awburst + .s0_awlock (_connected_to_s0_awlock_), // input, width = 1, .awlock + .s0_awcache (_connected_to_s0_awcache_), // input, width = 4, .awcache + .s0_awprot (_connected_to_s0_awprot_), // input, width = 3, .awprot + .s0_awvalid (_connected_to_s0_awvalid_), // input, width = 1, .awvalid + .s0_awready (_connected_to_s0_awready_), // output, width = 1, .awready + .s0_wdata (_connected_to_s0_wdata_), // input, width = 64, .wdata + .s0_wstrb (_connected_to_s0_wstrb_), // input, width = 8, .wstrb + .s0_wlast (_connected_to_s0_wlast_), // input, width = 1, .wlast + .s0_wvalid (_connected_to_s0_wvalid_), // input, width = 1, .wvalid + .s0_wready (_connected_to_s0_wready_), // output, width = 1, .wready + .s0_bid (_connected_to_s0_bid_), // output, width = 8, .bid + .s0_bresp (_connected_to_s0_bresp_), // output, width = 2, .bresp + .s0_bvalid (_connected_to_s0_bvalid_), // output, width = 1, .bvalid + .s0_bready (_connected_to_s0_bready_), // input, width = 1, .bready + .s0_arid (_connected_to_s0_arid_), // input, width = 8, .arid + .s0_araddr (_connected_to_s0_araddr_), // input, width = 64, .araddr + .s0_arlen (_connected_to_s0_arlen_), // input, width = 8, .arlen + .s0_arsize (_connected_to_s0_arsize_), // input, width = 3, .arsize + .s0_arburst (_connected_to_s0_arburst_), // input, width = 2, .arburst + .s0_arlock (_connected_to_s0_arlock_), // input, width = 1, .arlock + .s0_arcache (_connected_to_s0_arcache_), // input, width = 4, .arcache + .s0_arprot (_connected_to_s0_arprot_), // input, width = 3, .arprot + .s0_arvalid (_connected_to_s0_arvalid_), // input, width = 1, .arvalid + .s0_arready (_connected_to_s0_arready_), // output, width = 1, .arready + .s0_rid (_connected_to_s0_rid_), // output, width = 8, .rid + .s0_rdata (_connected_to_s0_rdata_), // output, width = 64, .rdata + .s0_rresp (_connected_to_s0_rresp_), // output, width = 2, .rresp + .s0_rlast (_connected_to_s0_rlast_), // output, width = 1, .rlast + .s0_rvalid (_connected_to_s0_rvalid_), // output, width = 1, .rvalid + .s0_rready (_connected_to_s0_rready_), // input, width = 1, .rready + .m0_awid (_connected_to_m0_awid_), // output, width = 8, m0.awid + .m0_awaddr (_connected_to_m0_awaddr_), // output, width = 64, .awaddr + .m0_awlen (_connected_to_m0_awlen_), // output, width = 8, .awlen + .m0_awsize (_connected_to_m0_awsize_), // output, width = 3, .awsize + .m0_awburst (_connected_to_m0_awburst_), // output, width = 2, .awburst + .m0_awlock (_connected_to_m0_awlock_), // output, width = 1, .awlock + .m0_awcache (_connected_to_m0_awcache_), // output, width = 4, .awcache + .m0_awprot (_connected_to_m0_awprot_), // output, width = 3, .awprot + .m0_awvalid (_connected_to_m0_awvalid_), // output, width = 1, .awvalid + .m0_awready (_connected_to_m0_awready_), // input, width = 1, .awready + .m0_wdata (_connected_to_m0_wdata_), // output, width = 64, .wdata + .m0_wstrb (_connected_to_m0_wstrb_), // output, width = 8, .wstrb + .m0_wlast (_connected_to_m0_wlast_), // output, width = 1, .wlast + .m0_wvalid (_connected_to_m0_wvalid_), // output, width = 1, .wvalid + .m0_wready (_connected_to_m0_wready_), // input, width = 1, .wready + .m0_bid (_connected_to_m0_bid_), // input, width = 8, .bid + .m0_bresp (_connected_to_m0_bresp_), // input, width = 2, .bresp + .m0_bvalid (_connected_to_m0_bvalid_), // input, width = 1, .bvalid + .m0_bready (_connected_to_m0_bready_), // output, width = 1, .bready + .m0_arid (_connected_to_m0_arid_), // output, width = 8, .arid + .m0_araddr (_connected_to_m0_araddr_), // output, width = 64, .araddr + .m0_arlen (_connected_to_m0_arlen_), // output, width = 8, .arlen + .m0_arsize (_connected_to_m0_arsize_), // output, width = 3, .arsize + .m0_arburst (_connected_to_m0_arburst_), // output, width = 2, .arburst + .m0_arlock (_connected_to_m0_arlock_), // output, width = 1, .arlock + .m0_arcache (_connected_to_m0_arcache_), // output, width = 4, .arcache + .m0_arprot (_connected_to_m0_arprot_), // output, width = 3, .arprot + .m0_arvalid (_connected_to_m0_arvalid_), // output, width = 1, .arvalid + .m0_arready (_connected_to_m0_arready_), // input, width = 1, .arready + .m0_rid (_connected_to_m0_rid_), // input, width = 8, .rid + .m0_rdata (_connected_to_m0_rdata_), // input, width = 64, .rdata + .m0_rresp (_connected_to_m0_rresp_), // input, width = 2, .rresp + .m0_rlast (_connected_to_m0_rlast_), // input, width = 1, .rlast + .m0_rvalid (_connected_to_m0_rvalid_), // input, width = 1, .rvalid + .m0_rready (_connected_to_m0_rready_) // output, width = 1, .rready + ); + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_inst.vhd b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_inst.vhd new file mode 100644 index 0000000000..559def949b --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/cva6_intel_axi_bridge_0_inst.vhd @@ -0,0 +1,275 @@ + component cva6_intel_axi_bridge_0 is + generic ( + USE_PIPELINE : integer := 1; + USE_M0_AWID : integer := 1; + USE_M0_AWREGION : integer := 0; + USE_M0_AWLEN : integer := 1; + USE_M0_AWSIZE : integer := 1; + USE_M0_AWBURST : integer := 1; + USE_M0_AWLOCK : integer := 1; + USE_M0_AWCACHE : integer := 1; + USE_M0_AWQOS : integer := 0; + USE_S0_AWREGION : integer := 0; + USE_S0_AWLOCK : integer := 1; + USE_S0_AWCACHE : integer := 1; + USE_S0_AWQOS : integer := 0; + USE_S0_AWPROT : integer := 1; + USE_M0_WSTRB : integer := 1; + USE_S0_WLAST : integer := 1; + USE_M0_BID : integer := 1; + USE_M0_BRESP : integer := 1; + USE_S0_BRESP : integer := 1; + USE_M0_ARID : integer := 1; + USE_M0_ARREGION : integer := 0; + USE_M0_ARLEN : integer := 1; + USE_M0_ARSIZE : integer := 1; + USE_M0_ARBURST : integer := 1; + USE_M0_ARLOCK : integer := 1; + USE_M0_ARCACHE : integer := 1; + USE_M0_ARQOS : integer := 0; + USE_S0_ARREGION : integer := 0; + USE_S0_ARLOCK : integer := 1; + USE_S0_ARCACHE : integer := 1; + USE_S0_ARQOS : integer := 0; + USE_S0_ARPROT : integer := 1; + USE_M0_RID : integer := 1; + USE_M0_RRESP : integer := 1; + USE_M0_RLAST : integer := 1; + USE_S0_RRESP : integer := 1; + M0_ID_WIDTH : integer := 8; + S0_ID_WIDTH : integer := 8; + DATA_WIDTH : integer := 64; + WRITE_ADDR_USER_WIDTH : integer := 32; + READ_ADDR_USER_WIDTH : integer := 32; + WRITE_DATA_USER_WIDTH : integer := 32; + WRITE_RESP_USER_WIDTH : integer := 32; + READ_DATA_USER_WIDTH : integer := 32; + ADDR_WIDTH : integer := 64; + USE_S0_AWUSER : integer := 0; + USE_S0_ARUSER : integer := 0; + USE_S0_WUSER : integer := 0; + USE_S0_RUSER : integer := 0; + USE_S0_BUSER : integer := 0; + USE_M0_AWUSER : integer := 0; + USE_M0_ARUSER : integer := 0; + USE_M0_WUSER : integer := 0; + USE_M0_RUSER : integer := 0; + USE_M0_BUSER : integer := 0; + AXI_VERSION : string := "AXI4"; + ACE_LITE_SUPPORT : integer := 0; + SYNC_RESET : integer := 0; + BACKPRESSURE_DURING_RESET : integer := 0 + ); + port ( + aclk : in std_logic := 'X'; -- clk + aresetn : in std_logic := 'X'; -- reset_n + s0_awid : in std_logic_vector(7 downto 0) := (others => 'X'); -- awid + s0_awaddr : in std_logic_vector(63 downto 0) := (others => 'X'); -- awaddr + s0_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- awlen + s0_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize + s0_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst + s0_awlock : in std_logic_vector(0 downto 0) := (others => 'X'); -- awlock + s0_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache + s0_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot + s0_awvalid : in std_logic := 'X'; -- awvalid + s0_awready : out std_logic; -- awready + s0_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- wdata + s0_wstrb : in std_logic_vector(7 downto 0) := (others => 'X'); -- wstrb + s0_wlast : in std_logic := 'X'; -- wlast + s0_wvalid : in std_logic := 'X'; -- wvalid + s0_wready : out std_logic; -- wready + s0_bid : out std_logic_vector(7 downto 0); -- bid + s0_bresp : out std_logic_vector(1 downto 0); -- bresp + s0_bvalid : out std_logic; -- bvalid + s0_bready : in std_logic := 'X'; -- bready + s0_arid : in std_logic_vector(7 downto 0) := (others => 'X'); -- arid + s0_araddr : in std_logic_vector(63 downto 0) := (others => 'X'); -- araddr + s0_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- arlen + s0_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize + s0_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst + s0_arlock : in std_logic_vector(0 downto 0) := (others => 'X'); -- arlock + s0_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache + s0_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot + s0_arvalid : in std_logic := 'X'; -- arvalid + s0_arready : out std_logic; -- arready + s0_rid : out std_logic_vector(7 downto 0); -- rid + s0_rdata : out std_logic_vector(63 downto 0); -- rdata + s0_rresp : out std_logic_vector(1 downto 0); -- rresp + s0_rlast : out std_logic; -- rlast + s0_rvalid : out std_logic; -- rvalid + s0_rready : in std_logic := 'X'; -- rready + m0_awid : out std_logic_vector(7 downto 0); -- awid + m0_awaddr : out std_logic_vector(63 downto 0); -- awaddr + m0_awlen : out std_logic_vector(7 downto 0); -- awlen + m0_awsize : out std_logic_vector(2 downto 0); -- awsize + m0_awburst : out std_logic_vector(1 downto 0); -- awburst + m0_awlock : out std_logic_vector(0 downto 0); -- awlock + m0_awcache : out std_logic_vector(3 downto 0); -- awcache + m0_awprot : out std_logic_vector(2 downto 0); -- awprot + m0_awvalid : out std_logic; -- awvalid + m0_awready : in std_logic := 'X'; -- awready + m0_wdata : out std_logic_vector(63 downto 0); -- wdata + m0_wstrb : out std_logic_vector(7 downto 0); -- wstrb + m0_wlast : out std_logic; -- wlast + m0_wvalid : out std_logic; -- wvalid + m0_wready : in std_logic := 'X'; -- wready + m0_bid : in std_logic_vector(7 downto 0) := (others => 'X'); -- bid + m0_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp + m0_bvalid : in std_logic := 'X'; -- bvalid + m0_bready : out std_logic; -- bready + m0_arid : out std_logic_vector(7 downto 0); -- arid + m0_araddr : out std_logic_vector(63 downto 0); -- araddr + m0_arlen : out std_logic_vector(7 downto 0); -- arlen + m0_arsize : out std_logic_vector(2 downto 0); -- arsize + m0_arburst : out std_logic_vector(1 downto 0); -- arburst + m0_arlock : out std_logic_vector(0 downto 0); -- arlock + m0_arcache : out std_logic_vector(3 downto 0); -- arcache + m0_arprot : out std_logic_vector(2 downto 0); -- arprot + m0_arvalid : out std_logic; -- arvalid + m0_arready : in std_logic := 'X'; -- arready + m0_rid : in std_logic_vector(7 downto 0) := (others => 'X'); -- rid + m0_rdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- rdata + m0_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp + m0_rlast : in std_logic := 'X'; -- rlast + m0_rvalid : in std_logic := 'X'; -- rvalid + m0_rready : out std_logic -- rready + ); + end component cva6_intel_axi_bridge_0; + + u0 : component cva6_intel_axi_bridge_0 + generic map ( + USE_PIPELINE => INTEGER_VALUE_FOR_USE_PIPELINE, + USE_M0_AWID => INTEGER_VALUE_FOR_USE_M0_AWID, + USE_M0_AWREGION => INTEGER_VALUE_FOR_USE_M0_AWREGION, + USE_M0_AWLEN => INTEGER_VALUE_FOR_USE_M0_AWLEN, + USE_M0_AWSIZE => INTEGER_VALUE_FOR_USE_M0_AWSIZE, + USE_M0_AWBURST => INTEGER_VALUE_FOR_USE_M0_AWBURST, + USE_M0_AWLOCK => INTEGER_VALUE_FOR_USE_M0_AWLOCK, + USE_M0_AWCACHE => INTEGER_VALUE_FOR_USE_M0_AWCACHE, + USE_M0_AWQOS => INTEGER_VALUE_FOR_USE_M0_AWQOS, + USE_S0_AWREGION => INTEGER_VALUE_FOR_USE_S0_AWREGION, + USE_S0_AWLOCK => INTEGER_VALUE_FOR_USE_S0_AWLOCK, + USE_S0_AWCACHE => INTEGER_VALUE_FOR_USE_S0_AWCACHE, + USE_S0_AWQOS => INTEGER_VALUE_FOR_USE_S0_AWQOS, + USE_S0_AWPROT => INTEGER_VALUE_FOR_USE_S0_AWPROT, + USE_M0_WSTRB => INTEGER_VALUE_FOR_USE_M0_WSTRB, + USE_S0_WLAST => INTEGER_VALUE_FOR_USE_S0_WLAST, + USE_M0_BID => INTEGER_VALUE_FOR_USE_M0_BID, + USE_M0_BRESP => INTEGER_VALUE_FOR_USE_M0_BRESP, + USE_S0_BRESP => INTEGER_VALUE_FOR_USE_S0_BRESP, + USE_M0_ARID => INTEGER_VALUE_FOR_USE_M0_ARID, + USE_M0_ARREGION => INTEGER_VALUE_FOR_USE_M0_ARREGION, + USE_M0_ARLEN => INTEGER_VALUE_FOR_USE_M0_ARLEN, + USE_M0_ARSIZE => INTEGER_VALUE_FOR_USE_M0_ARSIZE, + USE_M0_ARBURST => INTEGER_VALUE_FOR_USE_M0_ARBURST, + USE_M0_ARLOCK => INTEGER_VALUE_FOR_USE_M0_ARLOCK, + USE_M0_ARCACHE => INTEGER_VALUE_FOR_USE_M0_ARCACHE, + USE_M0_ARQOS => INTEGER_VALUE_FOR_USE_M0_ARQOS, + USE_S0_ARREGION => INTEGER_VALUE_FOR_USE_S0_ARREGION, + USE_S0_ARLOCK => INTEGER_VALUE_FOR_USE_S0_ARLOCK, + USE_S0_ARCACHE => INTEGER_VALUE_FOR_USE_S0_ARCACHE, + USE_S0_ARQOS => INTEGER_VALUE_FOR_USE_S0_ARQOS, + USE_S0_ARPROT => INTEGER_VALUE_FOR_USE_S0_ARPROT, + USE_M0_RID => INTEGER_VALUE_FOR_USE_M0_RID, + USE_M0_RRESP => INTEGER_VALUE_FOR_USE_M0_RRESP, + USE_M0_RLAST => INTEGER_VALUE_FOR_USE_M0_RLAST, + USE_S0_RRESP => INTEGER_VALUE_FOR_USE_S0_RRESP, + M0_ID_WIDTH => INTEGER_VALUE_FOR_M0_ID_WIDTH, + S0_ID_WIDTH => INTEGER_VALUE_FOR_S0_ID_WIDTH, + DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH, + WRITE_ADDR_USER_WIDTH => INTEGER_VALUE_FOR_WRITE_ADDR_USER_WIDTH, + READ_ADDR_USER_WIDTH => INTEGER_VALUE_FOR_READ_ADDR_USER_WIDTH, + WRITE_DATA_USER_WIDTH => INTEGER_VALUE_FOR_WRITE_DATA_USER_WIDTH, + WRITE_RESP_USER_WIDTH => INTEGER_VALUE_FOR_WRITE_RESP_USER_WIDTH, + READ_DATA_USER_WIDTH => INTEGER_VALUE_FOR_READ_DATA_USER_WIDTH, + ADDR_WIDTH => INTEGER_VALUE_FOR_ADDR_WIDTH, + USE_S0_AWUSER => INTEGER_VALUE_FOR_USE_S0_AWUSER, + USE_S0_ARUSER => INTEGER_VALUE_FOR_USE_S0_ARUSER, + USE_S0_WUSER => INTEGER_VALUE_FOR_USE_S0_WUSER, + USE_S0_RUSER => INTEGER_VALUE_FOR_USE_S0_RUSER, + USE_S0_BUSER => INTEGER_VALUE_FOR_USE_S0_BUSER, + USE_M0_AWUSER => INTEGER_VALUE_FOR_USE_M0_AWUSER, + USE_M0_ARUSER => INTEGER_VALUE_FOR_USE_M0_ARUSER, + USE_M0_WUSER => INTEGER_VALUE_FOR_USE_M0_WUSER, + USE_M0_RUSER => INTEGER_VALUE_FOR_USE_M0_RUSER, + USE_M0_BUSER => INTEGER_VALUE_FOR_USE_M0_BUSER, + AXI_VERSION => STRING_VALUE_FOR_AXI_VERSION, + ACE_LITE_SUPPORT => INTEGER_VALUE_FOR_ACE_LITE_SUPPORT, + SYNC_RESET => INTEGER_VALUE_FOR_SYNC_RESET, + BACKPRESSURE_DURING_RESET => INTEGER_VALUE_FOR_BACKPRESSURE_DURING_RESET + ) + port map ( + aclk => CONNECTED_TO_aclk, -- clk.clk + aresetn => CONNECTED_TO_aresetn, -- clk_reset.reset_n + s0_awid => CONNECTED_TO_s0_awid, -- s0.awid + s0_awaddr => CONNECTED_TO_s0_awaddr, -- .awaddr + s0_awlen => CONNECTED_TO_s0_awlen, -- .awlen + s0_awsize => CONNECTED_TO_s0_awsize, -- .awsize + s0_awburst => CONNECTED_TO_s0_awburst, -- .awburst + s0_awlock => CONNECTED_TO_s0_awlock, -- .awlock + s0_awcache => CONNECTED_TO_s0_awcache, -- .awcache + s0_awprot => CONNECTED_TO_s0_awprot, -- .awprot + s0_awvalid => CONNECTED_TO_s0_awvalid, -- .awvalid + s0_awready => CONNECTED_TO_s0_awready, -- .awready + s0_wdata => CONNECTED_TO_s0_wdata, -- .wdata + s0_wstrb => CONNECTED_TO_s0_wstrb, -- .wstrb + s0_wlast => CONNECTED_TO_s0_wlast, -- .wlast + s0_wvalid => CONNECTED_TO_s0_wvalid, -- .wvalid + s0_wready => CONNECTED_TO_s0_wready, -- .wready + s0_bid => CONNECTED_TO_s0_bid, -- .bid + s0_bresp => CONNECTED_TO_s0_bresp, -- .bresp + s0_bvalid => CONNECTED_TO_s0_bvalid, -- .bvalid + s0_bready => CONNECTED_TO_s0_bready, -- .bready + s0_arid => CONNECTED_TO_s0_arid, -- .arid + s0_araddr => CONNECTED_TO_s0_araddr, -- .araddr + s0_arlen => CONNECTED_TO_s0_arlen, -- .arlen + s0_arsize => CONNECTED_TO_s0_arsize, -- .arsize + s0_arburst => CONNECTED_TO_s0_arburst, -- .arburst + s0_arlock => CONNECTED_TO_s0_arlock, -- .arlock + s0_arcache => CONNECTED_TO_s0_arcache, -- .arcache + s0_arprot => CONNECTED_TO_s0_arprot, -- .arprot + s0_arvalid => CONNECTED_TO_s0_arvalid, -- .arvalid + s0_arready => CONNECTED_TO_s0_arready, -- .arready + s0_rid => CONNECTED_TO_s0_rid, -- .rid + s0_rdata => CONNECTED_TO_s0_rdata, -- .rdata + s0_rresp => CONNECTED_TO_s0_rresp, -- .rresp + s0_rlast => CONNECTED_TO_s0_rlast, -- .rlast + s0_rvalid => CONNECTED_TO_s0_rvalid, -- .rvalid + s0_rready => CONNECTED_TO_s0_rready, -- .rready + m0_awid => CONNECTED_TO_m0_awid, -- m0.awid + m0_awaddr => CONNECTED_TO_m0_awaddr, -- .awaddr + m0_awlen => CONNECTED_TO_m0_awlen, -- .awlen + m0_awsize => CONNECTED_TO_m0_awsize, -- .awsize + m0_awburst => CONNECTED_TO_m0_awburst, -- .awburst + m0_awlock => CONNECTED_TO_m0_awlock, -- .awlock + m0_awcache => CONNECTED_TO_m0_awcache, -- .awcache + m0_awprot => CONNECTED_TO_m0_awprot, -- .awprot + m0_awvalid => CONNECTED_TO_m0_awvalid, -- .awvalid + m0_awready => CONNECTED_TO_m0_awready, -- .awready + m0_wdata => CONNECTED_TO_m0_wdata, -- .wdata + m0_wstrb => CONNECTED_TO_m0_wstrb, -- .wstrb + m0_wlast => CONNECTED_TO_m0_wlast, -- .wlast + m0_wvalid => CONNECTED_TO_m0_wvalid, -- .wvalid + m0_wready => CONNECTED_TO_m0_wready, -- .wready + m0_bid => CONNECTED_TO_m0_bid, -- .bid + m0_bresp => CONNECTED_TO_m0_bresp, -- .bresp + m0_bvalid => CONNECTED_TO_m0_bvalid, -- .bvalid + m0_bready => CONNECTED_TO_m0_bready, -- .bready + m0_arid => CONNECTED_TO_m0_arid, -- .arid + m0_araddr => CONNECTED_TO_m0_araddr, -- .araddr + m0_arlen => CONNECTED_TO_m0_arlen, -- .arlen + m0_arsize => CONNECTED_TO_m0_arsize, -- .arsize + m0_arburst => CONNECTED_TO_m0_arburst, -- .arburst + m0_arlock => CONNECTED_TO_m0_arlock, -- .arlock + m0_arcache => CONNECTED_TO_m0_arcache, -- .arcache + m0_arprot => CONNECTED_TO_m0_arprot, -- .arprot + m0_arvalid => CONNECTED_TO_m0_arvalid, -- .arvalid + m0_arready => CONNECTED_TO_m0_arready, -- .arready + m0_rid => CONNECTED_TO_m0_rid, -- .rid + m0_rdata => CONNECTED_TO_m0_rdata, -- .rdata + m0_rresp => CONNECTED_TO_m0_rresp, -- .rresp + m0_rlast => CONNECTED_TO_m0_rlast, -- .rlast + m0_rvalid => CONNECTED_TO_m0_rvalid, -- .rvalid + m0_rready => CONNECTED_TO_m0_rready -- .rready + ); + diff --git a/corev_apu/altera/ip/cva6_intel_axi_bridge_0/synth/cva6_intel_axi_bridge_0.v b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/synth/cva6_intel_axi_bridge_0.v new file mode 100644 index 0000000000..325c013a61 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_axi_bridge_0/synth/cva6_intel_axi_bridge_0.v @@ -0,0 +1,312 @@ +// cva6_intel_axi_bridge_0.v + +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module cva6_intel_axi_bridge_0 #( + parameter USE_PIPELINE = 1, + parameter USE_M0_AWID = 1, + parameter USE_M0_AWREGION = 0, + parameter USE_M0_AWLEN = 1, + parameter USE_M0_AWSIZE = 1, + parameter USE_M0_AWBURST = 1, + parameter USE_M0_AWLOCK = 1, + parameter USE_M0_AWCACHE = 1, + parameter USE_M0_AWQOS = 0, + parameter USE_S0_AWREGION = 0, + parameter USE_S0_AWLOCK = 1, + parameter USE_S0_AWCACHE = 1, + parameter USE_S0_AWQOS = 0, + parameter USE_S0_AWPROT = 1, + parameter USE_M0_WSTRB = 1, + parameter USE_S0_WLAST = 1, + parameter USE_M0_BID = 1, + parameter USE_M0_BRESP = 1, + parameter USE_S0_BRESP = 1, + parameter USE_M0_ARID = 1, + parameter USE_M0_ARREGION = 0, + parameter USE_M0_ARLEN = 1, + parameter USE_M0_ARSIZE = 1, + parameter USE_M0_ARBURST = 1, + parameter USE_M0_ARLOCK = 1, + parameter USE_M0_ARCACHE = 1, + parameter USE_M0_ARQOS = 0, + parameter USE_S0_ARREGION = 0, + parameter USE_S0_ARLOCK = 1, + parameter USE_S0_ARCACHE = 1, + parameter USE_S0_ARQOS = 0, + parameter USE_S0_ARPROT = 1, + parameter USE_M0_RID = 1, + parameter USE_M0_RRESP = 1, + parameter USE_M0_RLAST = 1, + parameter USE_S0_RRESP = 1, + parameter M0_ID_WIDTH = 8, + parameter S0_ID_WIDTH = 8, + parameter DATA_WIDTH = 64, + parameter WRITE_ADDR_USER_WIDTH = 32, + parameter READ_ADDR_USER_WIDTH = 32, + parameter WRITE_DATA_USER_WIDTH = 32, + parameter WRITE_RESP_USER_WIDTH = 32, + parameter READ_DATA_USER_WIDTH = 32, + parameter ADDR_WIDTH = 64, + parameter USE_S0_AWUSER = 0, + parameter USE_S0_ARUSER = 0, + parameter USE_S0_WUSER = 0, + parameter USE_S0_RUSER = 0, + parameter USE_S0_BUSER = 0, + parameter USE_M0_AWUSER = 0, + parameter USE_M0_ARUSER = 0, + parameter USE_M0_WUSER = 0, + parameter USE_M0_RUSER = 0, + parameter USE_M0_BUSER = 0, + parameter AXI_VERSION = "AXI4", + parameter ACE_LITE_SUPPORT = 0, + parameter SYNC_RESET = 0, + parameter BACKPRESSURE_DURING_RESET = 0 + ) ( + input wire aclk, // clk.clk + input wire aresetn, // clk_reset.reset_n + input wire [7:0] s0_awid, // s0.awid + input wire [63:0] s0_awaddr, // .awaddr + input wire [7:0] s0_awlen, // .awlen + input wire [2:0] s0_awsize, // .awsize + input wire [1:0] s0_awburst, // .awburst + input wire [0:0] s0_awlock, // .awlock + input wire [3:0] s0_awcache, // .awcache + input wire [2:0] s0_awprot, // .awprot + input wire s0_awvalid, // .awvalid + output wire s0_awready, // .awready + input wire [63:0] s0_wdata, // .wdata + input wire [7:0] s0_wstrb, // .wstrb + input wire s0_wlast, // .wlast + input wire s0_wvalid, // .wvalid + output wire s0_wready, // .wready + output wire [7:0] s0_bid, // .bid + output wire [1:0] s0_bresp, // .bresp + output wire s0_bvalid, // .bvalid + input wire s0_bready, // .bready + input wire [7:0] s0_arid, // .arid + input wire [63:0] s0_araddr, // .araddr + input wire [7:0] s0_arlen, // .arlen + input wire [2:0] s0_arsize, // .arsize + input wire [1:0] s0_arburst, // .arburst + input wire [0:0] s0_arlock, // .arlock + input wire [3:0] s0_arcache, // .arcache + input wire [2:0] s0_arprot, // .arprot + input wire s0_arvalid, // .arvalid + output wire s0_arready, // .arready + output wire [7:0] s0_rid, // .rid + output wire [63:0] s0_rdata, // .rdata + output wire [1:0] s0_rresp, // .rresp + output wire s0_rlast, // .rlast + output wire s0_rvalid, // .rvalid + input wire s0_rready, // .rready + output wire [7:0] m0_awid, // m0.awid + output wire [63:0] m0_awaddr, // .awaddr + output wire [7:0] m0_awlen, // .awlen + output wire [2:0] m0_awsize, // .awsize + output wire [1:0] m0_awburst, // .awburst + output wire [0:0] m0_awlock, // .awlock + output wire [3:0] m0_awcache, // .awcache + output wire [2:0] m0_awprot, // .awprot + output wire m0_awvalid, // .awvalid + input wire m0_awready, // .awready + output wire [63:0] m0_wdata, // .wdata + output wire [7:0] m0_wstrb, // .wstrb + output wire m0_wlast, // .wlast + output wire m0_wvalid, // .wvalid + input wire m0_wready, // .wready + input wire [7:0] m0_bid, // .bid + input wire [1:0] m0_bresp, // .bresp + input wire m0_bvalid, // .bvalid + output wire m0_bready, // .bready + output wire [7:0] m0_arid, // .arid + output wire [63:0] m0_araddr, // .araddr + output wire [7:0] m0_arlen, // .arlen + output wire [2:0] m0_arsize, // .arsize + output wire [1:0] m0_arburst, // .arburst + output wire [0:0] m0_arlock, // .arlock + output wire [3:0] m0_arcache, // .arcache + output wire [2:0] m0_arprot, // .arprot + output wire m0_arvalid, // .arvalid + input wire m0_arready, // .arready + input wire [7:0] m0_rid, // .rid + input wire [63:0] m0_rdata, // .rdata + input wire [1:0] m0_rresp, // .rresp + input wire m0_rlast, // .rlast + input wire m0_rvalid, // .rvalid + output wire m0_rready // .rready + ); + + cva6_intel_axi_bridge_0_altera_axi_bridge_1940_72stfyq #( + .USE_PIPELINE (USE_PIPELINE), + .USE_M0_AWID (USE_M0_AWID), + .USE_M0_AWREGION (USE_M0_AWREGION), + .USE_M0_AWLEN (USE_M0_AWLEN), + .USE_M0_AWSIZE (USE_M0_AWSIZE), + .USE_M0_AWBURST (USE_M0_AWBURST), + .USE_M0_AWLOCK (USE_M0_AWLOCK), + .USE_M0_AWCACHE (USE_M0_AWCACHE), + .USE_M0_AWQOS (USE_M0_AWQOS), + .USE_S0_AWREGION (USE_S0_AWREGION), + .USE_S0_AWLOCK (USE_S0_AWLOCK), + .USE_S0_AWCACHE (USE_S0_AWCACHE), + .USE_S0_AWQOS (USE_S0_AWQOS), + .USE_S0_AWPROT (USE_S0_AWPROT), + .USE_M0_WSTRB (USE_M0_WSTRB), + .USE_S0_WLAST (USE_S0_WLAST), + .USE_M0_BID (USE_M0_BID), + .USE_M0_BRESP (USE_M0_BRESP), + .USE_S0_BRESP (USE_S0_BRESP), + .USE_M0_ARID (USE_M0_ARID), + .USE_M0_ARREGION (USE_M0_ARREGION), + .USE_M0_ARLEN (USE_M0_ARLEN), + .USE_M0_ARSIZE (USE_M0_ARSIZE), + .USE_M0_ARBURST (USE_M0_ARBURST), + .USE_M0_ARLOCK (USE_M0_ARLOCK), + .USE_M0_ARCACHE (USE_M0_ARCACHE), + .USE_M0_ARQOS (USE_M0_ARQOS), + .USE_S0_ARREGION (USE_S0_ARREGION), + .USE_S0_ARLOCK (USE_S0_ARLOCK), + .USE_S0_ARCACHE (USE_S0_ARCACHE), + .USE_S0_ARQOS (USE_S0_ARQOS), + .USE_S0_ARPROT (USE_S0_ARPROT), + .USE_M0_RID (USE_M0_RID), + .USE_M0_RRESP (USE_M0_RRESP), + .USE_M0_RLAST (USE_M0_RLAST), + .USE_S0_RRESP (USE_S0_RRESP), + .M0_ID_WIDTH (M0_ID_WIDTH), + .S0_ID_WIDTH (S0_ID_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .WRITE_ADDR_USER_WIDTH (WRITE_ADDR_USER_WIDTH), + .READ_ADDR_USER_WIDTH (READ_ADDR_USER_WIDTH), + .WRITE_DATA_USER_WIDTH (WRITE_DATA_USER_WIDTH), + .WRITE_RESP_USER_WIDTH (WRITE_RESP_USER_WIDTH), + .READ_DATA_USER_WIDTH (READ_DATA_USER_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .USE_S0_AWUSER (USE_S0_AWUSER), + .USE_S0_ARUSER (USE_S0_ARUSER), + .USE_S0_WUSER (USE_S0_WUSER), + .USE_S0_RUSER (USE_S0_RUSER), + .USE_S0_BUSER (USE_S0_BUSER), + .USE_M0_AWUSER (USE_M0_AWUSER), + .USE_M0_ARUSER (USE_M0_ARUSER), + .USE_M0_WUSER (USE_M0_WUSER), + .USE_M0_RUSER (USE_M0_RUSER), + .USE_M0_BUSER (USE_M0_BUSER), + .AXI_VERSION (AXI_VERSION), + .BURST_LENGTH_WIDTH (8), + .LOCK_WIDTH (1), + .ACE_LITE_SUPPORT (ACE_LITE_SUPPORT), + .SYNC_RESET (SYNC_RESET), + .BACKPRESSURE_DURING_RESET (BACKPRESSURE_DURING_RESET) + ) axi_bridge_0 ( + .aclk (aclk), // input, width = 1, clk.clk + .aresetn (aresetn), // input, width = 1, clk_reset.reset_n + .s0_awid (s0_awid), // input, width = 8, s0.awid + .s0_awaddr (s0_awaddr), // input, width = 64, .awaddr + .s0_awlen (s0_awlen), // input, width = 8, .awlen + .s0_awsize (s0_awsize), // input, width = 3, .awsize + .s0_awburst (s0_awburst), // input, width = 2, .awburst + .s0_awlock (s0_awlock), // input, width = 1, .awlock + .s0_awcache (s0_awcache), // input, width = 4, .awcache + .s0_awprot (s0_awprot), // input, width = 3, .awprot + .s0_awvalid (s0_awvalid), // input, width = 1, .awvalid + .s0_awready (s0_awready), // output, width = 1, .awready + .s0_wdata (s0_wdata), // input, width = 64, .wdata + .s0_wstrb (s0_wstrb), // input, width = 8, .wstrb + .s0_wlast (s0_wlast), // input, width = 1, .wlast + .s0_wvalid (s0_wvalid), // input, width = 1, .wvalid + .s0_wready (s0_wready), // output, width = 1, .wready + .s0_bid (s0_bid), // output, width = 8, .bid + .s0_bresp (s0_bresp), // output, width = 2, .bresp + .s0_bvalid (s0_bvalid), // output, width = 1, .bvalid + .s0_bready (s0_bready), // input, width = 1, .bready + .s0_arid (s0_arid), // input, width = 8, .arid + .s0_araddr (s0_araddr), // input, width = 64, .araddr + .s0_arlen (s0_arlen), // input, width = 8, .arlen + .s0_arsize (s0_arsize), // input, width = 3, .arsize + .s0_arburst (s0_arburst), // input, width = 2, .arburst + .s0_arlock (s0_arlock), // input, width = 1, .arlock + .s0_arcache (s0_arcache), // input, width = 4, .arcache + .s0_arprot (s0_arprot), // input, width = 3, .arprot + .s0_arvalid (s0_arvalid), // input, width = 1, .arvalid + .s0_arready (s0_arready), // output, width = 1, .arready + .s0_rid (s0_rid), // output, width = 8, .rid + .s0_rdata (s0_rdata), // output, width = 64, .rdata + .s0_rresp (s0_rresp), // output, width = 2, .rresp + .s0_rlast (s0_rlast), // output, width = 1, .rlast + .s0_rvalid (s0_rvalid), // output, width = 1, .rvalid + .s0_rready (s0_rready), // input, width = 1, .rready + .m0_awid (m0_awid), // output, width = 8, m0.awid + .m0_awaddr (m0_awaddr), // output, width = 64, .awaddr + .m0_awlen (m0_awlen), // output, width = 8, .awlen + .m0_awsize (m0_awsize), // output, width = 3, .awsize + .m0_awburst (m0_awburst), // output, width = 2, .awburst + .m0_awlock (m0_awlock), // output, width = 1, .awlock + .m0_awcache (m0_awcache), // output, width = 4, .awcache + .m0_awprot (m0_awprot), // output, width = 3, .awprot + .m0_awvalid (m0_awvalid), // output, width = 1, .awvalid + .m0_awready (m0_awready), // input, width = 1, .awready + .m0_wdata (m0_wdata), // output, width = 64, .wdata + .m0_wstrb (m0_wstrb), // output, width = 8, .wstrb + .m0_wlast (m0_wlast), // output, width = 1, .wlast + .m0_wvalid (m0_wvalid), // output, width = 1, .wvalid + .m0_wready (m0_wready), // input, width = 1, .wready + .m0_bid (m0_bid), // input, width = 8, .bid + .m0_bresp (m0_bresp), // input, width = 2, .bresp + .m0_bvalid (m0_bvalid), // input, width = 1, .bvalid + .m0_bready (m0_bready), // output, width = 1, .bready + .m0_arid (m0_arid), // output, width = 8, .arid + .m0_araddr (m0_araddr), // output, width = 64, .araddr + .m0_arlen (m0_arlen), // output, width = 8, .arlen + .m0_arsize (m0_arsize), // output, width = 3, .arsize + .m0_arburst (m0_arburst), // output, width = 2, .arburst + .m0_arlock (m0_arlock), // output, width = 1, .arlock + .m0_arcache (m0_arcache), // output, width = 4, .arcache + .m0_arprot (m0_arprot), // output, width = 3, .arprot + .m0_arvalid (m0_arvalid), // output, width = 1, .arvalid + .m0_arready (m0_arready), // input, width = 1, .arready + .m0_rid (m0_rid), // input, width = 8, .rid + .m0_rdata (m0_rdata), // input, width = 64, .rdata + .m0_rresp (m0_rresp), // input, width = 2, .rresp + .m0_rlast (m0_rlast), // input, width = 1, .rlast + .m0_rvalid (m0_rvalid), // input, width = 1, .rvalid + .m0_rready (m0_rready), // output, width = 1, .rready + .s0_awuser (32'b00000000000000000000000000000000), // (terminated), + .s0_awqos (4'b0000), // (terminated), + .s0_awregion (4'b0000), // (terminated), + .s0_wuser (32'b00000000000000000000000000000000), // (terminated), + .s0_buser (), // (terminated), + .s0_aruser (32'b00000000000000000000000000000000), // (terminated), + .s0_arqos (4'b0000), // (terminated), + .s0_arregion (4'b0000), // (terminated), + .s0_ruser (), // (terminated), + .m0_awuser (), // (terminated), + .m0_awqos (), // (terminated), + .m0_awregion (), // (terminated), + .m0_wuser (), // (terminated), + .m0_buser (32'b00000000000000000000000000000000), // (terminated), + .m0_aruser (), // (terminated), + .m0_arqos (), // (terminated), + .m0_arregion (), // (terminated), + .m0_ruser (32'b00000000000000000000000000000000), // (terminated), + .s0_wid (8'b00000000), // (terminated), + .s0_ardomain (2'b00), // (terminated), + .s0_arsnoop (4'b0000), // (terminated), + .s0_arbar (2'b00), // (terminated), + .s0_awdomain (2'b00), // (terminated), + .s0_awsnoop (3'b000), // (terminated), + .s0_awbar (2'b00), // (terminated), + .s0_awunique (1'b0), // (terminated), + .m0_wid (), // (terminated), + .m0_ardomain (), // (terminated), + .m0_arsnoop (), // (terminated), + .m0_arbar (), // (terminated), + .m0_awdomain (), // (terminated), + .m0_awsnoop (), // (terminated), + .m0_awbar (), // (terminated), + .m0_awunique () // (terminated), + ); + +endmodule diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0.ip b/corev_apu/altera/ip/cva6_intel_jtag_uart_0.ip new file mode 100644 index 0000000000..b01b6d290e --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0.ip @@ -0,0 +1,1408 @@ + + + + Intel Corporation + cva6_intel_jtag_uart_0 + jtag_uart_0 + 19.2.4 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + avalon_jtag_slave + + + + + + + + chipselect + + + av_chipselect + + + + + address + + + av_address + + + + + read_n + + + av_read_n + + + + + readdata + + + av_readdata + + + + + write_n + + + av_write_n + + + + + writedata + + + av_writedata + + + + + waitrequest + + + av_waitrequest + + + + + + + + + addressAlignment + Agent addressing + NATIVE + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 2 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + true + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + dfhFeatureGuid + Feature GUID + 0 + + + dfhGroupId + Group ID + 0 + + + dfhParameterId + ID + + + + dfhParameterName + Name + + + + dfhParameterVersion + Version + + + + dfhParameterData + Data (HEX/DEC) + + + + dfhParameterDataLength + Data length + + + + dfhFeatureMajorVersion + Feature major version + 0 + + + dfhFeatureMinorVersion + Feature minor version + 0 + + + dfhFeatureId + Feature ID + 35 + + + dfhFeatureType + Feature Type + 3 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + + + + + irq + + + + + + + + irq + + + av_irq + + + + + + + + + associatedAddressablePoint + Associated addressable interface + cva6_intel_jtag_uart_0.avalon_jtag_slave + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bridgedReceiverOffset + Bridged receiver offset + 0 + + + bridgesToReceiver + Bridges to receiver + + + + irqScheme + Interrupt scheme + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_avalon_jtag_uart + + QUARTUS_SYNTH + + + + + + + clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_chipselect + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_address + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_read_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_write_n + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_waitrequest + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_irq + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + cva6_intel_jtag_uart_0 + altera_avalon_jtag_uart + 19.2.4 + + + + + allowMultipleConnections + Allow multiple connections to Avalon JTAG slave + false + + + hubInstanceID + hubInstanceID + 0 + + + readBufferDepth + Buffer depth (bytes) + 64 + + + readIRQThreshold + IRQ threshold + 8 + + + simInputCharacterStream + Contents + + + + simInteractiveOptions + Options + NO_INTERACTIVE_WINDOWS + + + useRegistersForReadBuffer + Construct using registers instead of memory blocks + false + + + useRegistersForWriteBuffer + Construct using registers instead of memory blocks + false + + + useRelativePathForSimFile + useRelativePathForSimFile + false + + + writeBufferDepth + Buffer depth (bytes) + 64 + + + writeIRQThreshold + IRQ threshold + 8 + + + clkFreq + clkFreq + 300000000 + + + avalonSpec + avalonSpec + 2.0 + + + + + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.dts.compatible + altr,juart-1.0 + + + embeddedsw.dts.group + serial + + + embeddedsw.dts.name + juart + + + embeddedsw.dts.vendor + altr + + + + + + + board + Board + default + + + device + Device + AGFB014R24B2E2V + + + deviceFamily + Device family + Agilex 7 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Agilex 7"; + type = "String"; + } + } + element jtag_uart_0 + { + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_jtag_slave</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_chipselect</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>1</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>2</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>true</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureGuid</key> + <value>0</value> + </entry> + <entry> + <key>dfhGroupId</key> + <value>0</value> + </entry> + <entry> + <key>dfhParameterId</key> + </entry> + <entry> + <key>dfhParameterName</key> + </entry> + <entry> + <key>dfhParameterVersion</key> + </entry> + <entry> + <key>dfhParameterData</key> + </entry> + <entry> + <key>dfhParameterDataLength</key> + </entry> + <entry> + <key>dfhFeatureMajorVersion</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureMinorVersion</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureId</key> + <value>35</value> + </entry> + <entry> + <key>dfhFeatureType</key> + <value>3</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;addressBlock&gt; + &lt;offset&gt;0x0&lt;/offset&gt; + &lt;size&gt;8&lt;/size&gt; + &lt;usage&gt;registers&lt;/usage&gt; + &lt;/addressBlock&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;name&gt;DATA&lt;/name&gt; + &lt;displayName&gt;Data&lt;/displayName&gt; + &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;data&lt;/name&gt; + &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;8&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt; + &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt; + &lt;bitOffset&gt;0xf&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt; + &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;name&gt;CONTROL&lt;/name&gt; + &lt;displayName&gt;Control&lt;/displayName&gt; + &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt; + &lt;addressOffset&gt;0x4&lt;/addressOffset&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;resetValue&gt;0x0&lt;/resetValue&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;fields&gt; + &lt;field&gt;&lt;name&gt;re&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt; + &lt;bitOffset&gt;0x0&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;we&lt;/name&gt; + &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt; + &lt;bitOffset&gt;0x1&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ri&lt;/name&gt; + &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x8&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wi&lt;/name&gt; + &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt; + &lt;bitOffset&gt;0x9&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;ac&lt;/name&gt; + &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt; + &lt;bitOffset&gt;0xa&lt;/bitOffset&gt; + &lt;bitWidth&gt;1&lt;/bitWidth&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;/field&gt; + &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt; + &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt; + &lt;bitOffset&gt;0x10&lt;/bitOffset&gt; + &lt;bitWidth&gt;16&lt;/bitWidth&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt; </cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>cva6_intel_jtag_uart_0.avalon_jtag_slave</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_jtag_slave</key> + <value> + <connectionPointName>avalon_jtag_slave</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>3</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>300000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/altera_avalon_jtag_uart_1924/synth/cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq.v b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/altera_avalon_jtag_uart_1924/synth/cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq.v new file mode 100644 index 0000000000..f238ab9955 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/altera_avalon_jtag_uart_1924/synth/cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq.v @@ -0,0 +1,643 @@ +//Legal Notice: (C)2024 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_log_module ( + // inputs: + clk, + data, + strobe, + valid + ) +; + + input clk; + input [ 7: 0] data; + input strobe; + input valid; + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + reg [31:0] text_handle; // for $fopen + initial text_handle = $fopen ("cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_output_stream.dat"); + + always @(posedge clk) begin + if (valid && strobe) begin + // Send \n (linefeed) instead of \r (^M, Carriage Return)... + $fwrite (text_handle, "%s", ((data == 8'hd) ? 8'ha : data)); + // non-standard; poorly documented; required to get real data stream. + $fflush (text_handle); + end + end // clk + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_sim_scfifo_w ( + // inputs: + clk, + fifo_wdata, + fifo_wr, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input [ 7: 0] fifo_wdata; + input fifo_wr; + + +wire fifo_FF; +wire [ 7: 0] r_dat; +wire wfifo_empty; +wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_log, which is an e_log + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_log_module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_log + ( + .clk (clk), + .data (fifo_wdata), + .strobe (fifo_wr), + .valid (fifo_wr) + ); + + always @(posedge clk) + begin + if (fifo_wr) + $write("%c", fifo_wdata); + end + + + assign wfifo_used = {6{1'b0}}; + assign r_dat = {8{1'b0}}; + assign fifo_FF = 1'b0; + assign wfifo_empty = 1'b1; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_scfifo_w ( + // inputs: + clk, + fifo_clear, + fifo_wdata, + fifo_wr, + rd_wfifo, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input fifo_clear; + input [ 7: 0] fifo_wdata; + input fifo_wr; + input rd_wfifo; + + +wire fifo_FF; +wire [ 7: 0] r_dat; +wire wfifo_empty; +wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_sim_scfifo_w the_cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_sim_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo wfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (fifo_wdata), +// .empty (wfifo_empty), +// .full (fifo_FF), +// .q (r_dat), +// .rdreq (rd_wfifo), +// .usedw (wfifo_used), +// .wrreq (fifo_wr) +// ); +// +// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// wfifo.lpm_numwords = 64, +// wfifo.lpm_showahead = "OFF", +// wfifo.lpm_type = "scfifo", +// wfifo.lpm_width = 8, +// wfifo.lpm_widthu = 6, +// wfifo.overflow_checking = "OFF", +// wfifo.underflow_checking = "OFF", +// wfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_sim_scfifo_r ( + // inputs: + clk, + fifo_rd, + rst_n, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_rd; + input rst_n; + + +reg [ 31: 0] bytes_left; +wire fifo_EF; +reg fifo_rd_d; +wire [ 7: 0] fifo_rdata; +wire new_rom; +wire [ 31: 0] num_bytes; +wire [ 6: 0] rfifo_entries; +wire rfifo_full; +wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Generate rfifo_entries for simulation + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + bytes_left <= 32'h0; + fifo_rd_d <= 1'b0; + end + else + begin + fifo_rd_d <= fifo_rd; + // decrement on read + if (fifo_rd_d) + bytes_left <= bytes_left - 1'b1; + // catch new contents + if (new_rom) + bytes_left <= num_bytes; + end + end + + + assign fifo_EF = bytes_left == 32'b0; + assign rfifo_full = bytes_left > 7'h40; + assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; + assign rfifo_used = rfifo_entries[5 : 0]; + assign new_rom = 1'b0; + assign num_bytes = 32'b0; + assign fifo_rdata = 8'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_scfifo_r ( + // inputs: + clk, + fifo_clear, + fifo_rd, + rst_n, + t_dat, + wr_rfifo, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_clear; + input fifo_rd; + input rst_n; + input [ 7: 0] t_dat; + input wr_rfifo; + + +wire fifo_EF; +wire [ 7: 0] fifo_rdata; +wire rfifo_full; +wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_sim_scfifo_r the_cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_sim_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo rfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (t_dat), +// .empty (fifo_EF), +// .full (rfifo_full), +// .q (fifo_rdata), +// .rdreq (fifo_rd), +// .usedw (rfifo_used), +// .wrreq (wr_rfifo) +// ); +// +// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// rfifo.lpm_numwords = 64, +// rfifo.lpm_showahead = "OFF", +// rfifo.lpm_type = "scfifo", +// rfifo.lpm_width = 8, +// rfifo.lpm_widthu = 6, +// rfifo.overflow_checking = "OFF", +// rfifo.underflow_checking = "OFF", +// rfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq ( + // inputs: + av_address, + av_chipselect, + av_read_n, + av_write_n, + av_writedata, + clk, + rst_n, + + // outputs: + av_irq, + av_readdata, + av_waitrequest, + dataavailable, + readyfordata + ) + /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; + + output av_irq; + output [ 31: 0] av_readdata; + output av_waitrequest; + output dataavailable; + output readyfordata; + input av_address; + input av_chipselect; + input av_read_n; + input av_write_n; + input [ 31: 0] av_writedata; + input clk; + input rst_n; + + +reg ac; +wire activity; +wire av_irq; +wire [ 31: 0] av_readdata; +reg av_waitrequest; +reg dataavailable; +reg fifo_AE; +reg fifo_AF; +wire fifo_EF; +wire fifo_FF; +wire fifo_clear; +wire fifo_rd; +wire [ 7: 0] fifo_rdata; +wire [ 7: 0] fifo_wdata; +reg fifo_wr; +reg ien_AE; +reg ien_AF; +wire ipen_AE; +wire ipen_AF; +reg pause_irq; +wire [ 7: 0] r_dat; +wire r_ena; +reg r_val; +wire rd_wfifo; +reg read_0; +reg readyfordata; +wire rfifo_full; +wire [ 5: 0] rfifo_used; +reg rvalid; +reg sim_r_ena; +reg sim_t_dat; +reg sim_t_ena; +reg sim_t_pause; +wire [ 7: 0] t_dat; +reg t_dav; +wire t_ena; +wire t_pause; +wire wfifo_empty; +wire [ 5: 0] wfifo_used; +reg woverflow; +wire wr_rfifo; + //avalon_jtag_slave, which is an e_avalon_slave + assign rd_wfifo = r_ena & ~wfifo_empty; + assign wr_rfifo = t_ena & ~rfifo_full; + assign fifo_clear = ~rst_n; + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_scfifo_w the_cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_clear (fifo_clear), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .rd_wfifo (rd_wfifo), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_scfifo_r the_cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_clear (fifo_clear), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n), + .t_dat (t_dat), + .wr_rfifo (wr_rfifo) + ); + + assign ipen_AE = ien_AE & fifo_AE; + assign ipen_AF = ien_AF & (pause_irq | fifo_AF); + assign av_irq = ipen_AE | ipen_AF; + assign activity = t_pause | t_ena; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + pause_irq <= 1'b0; + else // only if fifo is not empty... + if (t_pause & ~fifo_EF) + pause_irq <= 1'b1; + else if (read_0) + pause_irq <= 1'b0; + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + r_val <= 1'b0; + t_dav <= 1'b1; + end + else + begin + r_val <= r_ena & ~wfifo_empty; + t_dav <= ~rfifo_full; + end + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + fifo_AE <= 1'b0; + fifo_AF <= 1'b0; + fifo_wr <= 1'b0; + rvalid <= 1'b0; + read_0 <= 1'b0; + ien_AE <= 1'b0; + ien_AF <= 1'b0; + ac <= 1'b0; + woverflow <= 1'b0; + av_waitrequest <= 1'b1; + end + else + begin + fifo_AE <= {fifo_FF,wfifo_used} <= 8; + fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; + fifo_wr <= 1'b0; + read_0 <= 1'b0; + av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); + if (activity) + ac <= 1'b1; + // write + if (av_chipselect & ~av_write_n & av_waitrequest) + // addr 1 is control; addr 0 is data + if (av_address) + begin + ien_AF <= av_writedata[0]; + ien_AE <= av_writedata[1]; + if (av_writedata[10] & ~activity) + ac <= 1'b0; + end + else + begin + fifo_wr <= ~fifo_FF; + woverflow <= fifo_FF; + end + // read + if (av_chipselect & ~av_read_n & av_waitrequest) + begin + // addr 1 is interrupt; addr 0 is data + if (~av_address) + rvalid <= ~fifo_EF; + read_0 <= ~av_address; + end + end + end + + + assign fifo_wdata = av_writedata[7 : 0]; + assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; + assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + readyfordata <= 0; + else + readyfordata <= ~fifo_FF; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Tie off Atlantic Interface signals not used for simulation + always @(posedge clk) + begin + sim_t_pause <= 1'b0; + sim_t_ena <= 1'b0; + sim_t_dat <= t_dav ? r_dat : {8{r_val}}; + sim_r_ena <= 1'b0; + end + + + assign r_ena = sim_r_ena; + assign t_ena = sim_t_ena; + assign t_dat = sim_t_dat; + assign t_pause = sim_t_pause; + always @(fifo_EF) + begin + dataavailable = ~fifo_EF; + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// alt_jtag_atlantic cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_alt_jtag_atlantic +// ( +// .clk (clk), +// .r_dat (r_dat), +// .r_ena (r_ena), +// .r_val (r_val), +// .rst_n (rst_n), +// .t_dat (t_dat), +// .t_dav (t_dav), +// .t_ena (t_ena), +// .t_pause (t_pause) +// ); +// +// defparam cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_alt_jtag_atlantic.INSTANCE_ID = 0, +// cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, +// cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, +// cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; +// +// always @(posedge clk or negedge rst_n) +// begin +// if (rst_n == 0) +// dataavailable <= 0; +// else +// dataavailable <= ~fifo_EF; +// end +// +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.bsf b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.bsf new file mode 100644 index 0000000000..b34a5aeba4 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.bsf @@ -0,0 +1,130 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the Intel FPGA Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 320 368) + (text "cva6_intel_jtag_uart_0" (rect 85 0 175 12)(font "SansSerif" (font_size 11))) + (text "inst" (rect 8 352 20 364)(font "Arial" )) + (port + (pt 0 76) + (input) + (text "clk" (rect 0 0 10 12)(font "SansSerif" (font_size 8))) + (text "clk" (rect 4 65 22 76)(font "SansSerif" (font_size 8))) + (line (pt 0 76)(pt 119 76)(line_width 1)) + ) + (port + (pt 0 126) + (input) + (text "rst_n" (rect 0 0 21 12)(font "SansSerif" (font_size 8))) + (text "rst_n" (rect 4 115 34 126)(font "SansSerif" (font_size 8))) + (line (pt 0 126)(pt 119 126)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "av_chipselect" (rect 0 0 54 12)(font "SansSerif" (font_size 8))) + (text "av_chipselect" (rect 4 165 82 176)(font "SansSerif" (font_size 8))) + (line (pt 0 176)(pt 119 176)(line_width 1)) + ) + (port + (pt 0 201) + (input) + (text "av_address" (rect 0 0 48 12)(font "SansSerif" (font_size 8))) + (text "av_address" (rect 4 190 64 201)(font "SansSerif" (font_size 8))) + (line (pt 0 201)(pt 119 201)(line_width 1)) + ) + (port + (pt 0 226) + (input) + (text "av_read_n" (rect 0 0 44 12)(font "SansSerif" (font_size 8))) + (text "av_read_n" (rect 4 215 58 226)(font "SansSerif" (font_size 8))) + (line (pt 0 226)(pt 119 226)(line_width 1)) + ) + (port + (pt 0 276) + (input) + (text "av_write_n" (rect 0 0 44 12)(font "SansSerif" (font_size 8))) + (text "av_write_n" (rect 4 265 64 276)(font "SansSerif" (font_size 8))) + (line (pt 0 276)(pt 119 276)(line_width 1)) + ) + (port + (pt 0 301) + (input) + (text "av_writedata[31..0]" (rect 0 0 74 12)(font "SansSerif" (font_size 8))) + (text "av_writedata[31..0]" (rect 4 290 118 301)(font "SansSerif" (font_size 8))) + (line (pt 0 301)(pt 119 301)(line_width 3)) + ) + (port + (pt 0 251) + (output) + (text "av_readdata[31..0]" (rect 0 0 74 12)(font "SansSerif" (font_size 8))) + (text "av_readdata[31..0]" (rect 4 240 112 251)(font "SansSerif" (font_size 8))) + ) + (port + (pt 0 326) + (output) + (text "av_waitrequest" (rect 0 0 60 12)(font "SansSerif" (font_size 8))) + (text "av_waitrequest" (rect 4 315 88 326)(font "SansSerif" (font_size 8))) + ) + (port + (pt 320 76) + (output) + (text "av_irq" (rect 0 0 25 12)(font "SansSerif" (font_size 8))) + (text "av_irq" (rect 290 65 326 76)(font "SansSerif" (font_size 8))) + (line (pt 320 76)(pt 204 76)(line_width 1)) + ) + (drawing + (text "clk" (rect 104 46 226 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 124 71 266 152)(font "SansSerif" (color 0 0 0))) + (text "reset" (rect 90 96 210 205)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 124 121 290 252)(font "SansSerif" (color 0 0 0))) + (text "avalon_jtag_slave" (rect 16 146 134 305)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "chipselect" (rect 124 171 308 352)(font "SansSerif" (color 0 0 0))) + (text "address" (rect 124 196 290 402)(font "SansSerif" (color 0 0 0))) + (text "read_n" (rect 124 221 284 452)(font "SansSerif" (color 0 0 0))) + (text "readdata" (rect 124 246 296 502)(font "SansSerif" (color 0 0 0))) + (text "write_n" (rect 124 271 290 552)(font "SansSerif" (color 0 0 0))) + (text "writedata" (rect 124 296 302 602)(font "SansSerif" (color 0 0 0))) + (text "waitrequest" (rect 124 321 314 652)(font "SansSerif" (color 0 0 0))) + (text "irq" (rect 205 46 428 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "irq" (rect 190 71 398 152)(font "SansSerif" (color 0 0 0))) + (text " cva6_intel_jtag_uart_0 " (rect 221 351 586 712)(font "SansSerif" )) + (line (pt 119 34)(pt 204 34)(line_width 1)) + (line (pt 204 34)(pt 204 351)(line_width 1)) + (line (pt 119 351)(pt 204 351)(line_width 1)) + (line (pt 119 34)(pt 119 351)(line_width 1)) + (line (pt 120 55)(pt 120 80)(line_width 1)) + (line (pt 121 55)(pt 121 80)(line_width 1)) + (line (pt 120 105)(pt 120 130)(line_width 1)) + (line (pt 121 105)(pt 121 130)(line_width 1)) + (line (pt 320 251)(pt 119 251)(line_width 3)) + (line (pt 320 326)(pt 119 326)(line_width 1)) + (line (pt 120 155)(pt 120 330)(line_width 1)) + (line (pt 121 155)(pt 121 330)(line_width 1)) + (line (pt 203 55)(pt 203 80)(line_width 1)) + (line (pt 202 55)(pt 202 80)(line_width 1)) + (line (pt 0 0)(pt 320 0)(line_width 1)) + (line (pt 320 0)(pt 320 368)(line_width 1)) + (line (pt 0 368)(pt 320 368)(line_width 1)) + (line (pt 0 0)(pt 0 368)(line_width 1)) + ) +) diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.cmp b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.cmp new file mode 100644 index 0000000000..846516068f --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.cmp @@ -0,0 +1,15 @@ + component cva6_intel_jtag_uart_0 is + port ( + clk : in std_logic := 'X'; -- clk + rst_n : in std_logic := 'X'; -- reset_n + av_chipselect : in std_logic := 'X'; -- chipselect + av_address : in std_logic := 'X'; -- address + av_read_n : in std_logic := 'X'; -- read_n + av_readdata : out std_logic_vector(31 downto 0); -- readdata + av_write_n : in std_logic := 'X'; -- write_n + av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + av_waitrequest : out std_logic; -- waitrequest + av_irq : out std_logic -- irq + ); + end component cva6_intel_jtag_uart_0; + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.html b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.html new file mode 100644 index 0000000000..0660edc253 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.html @@ -0,0 +1,188 @@ + + + + + datasheet for cva6_intel_jtag_uart_0 + + + + + + + + +
cva6_intel_jtag_uart_0 +
+
+
+ + + + + +
2024.07.30.09:07:59Datasheet
+
+
Overview
+
+
+ + + + +
+
+
+
All Components +
   + jtag_uart_0 + altera_avalon_jtag_uart 19.2.4 +
+
+
+
Memory Map
+ + + + + + + + + + +
  + jtag_uart_0 + +
avalon_jtag_slave 
+ +
+
+

jtag_uart_0

altera_avalon_jtag_uart v19.2.4 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
readBufferDepth64
readIRQThreshold8
useRegistersForReadBufferfalse
useRegistersForWriteBufferfalse
writeBufferDepth64
writeIRQThreshold8
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + +
READ_DEPTH64
READ_THRESHOLD8
WRITE_DEPTH64
WRITE_THRESHOLD8
+
+
+ + + + + +
generation took 0.00 secondsrendering took 0.04 seconds
+ + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.qgsynthc b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.qgsynthc new file mode 100644 index 0000000000..e1f3ba004e --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.qgsynthc @@ -0,0 +1,96 @@ + + + cva6_intel_jtag_uart_0 + + + + cva6_intel_jtag_uart_0 + 1.0 + cva6_intel_jtag_uart_0 + cva6_intel_jtag_uart_0 + 0 + + + + + jtag_uart_0 + + + + allowMultipleConnections + false + + + avalonSpec + 2.0 + + + clkFreq + 300000000 + + + enableInteractiveInput + false + + + enableInteractiveOutput + false + + + hubInstanceID + 0 + + + legacySignalAllow + false + + + readBufferDepth + 64 + + + readIRQThreshold + 8 + + + simInputCharacterStream + + + + simInteractiveOptions + NO_INTERACTIVE_WINDOWS + + + useRegistersForReadBuffer + false + + + useRegistersForWriteBuffer + false + + + useRelativePathForSimFile + false + + + writeBufferDepth + 64 + + + writeIRQThreshold + 8 + + + + altera_avalon_jtag_uart + 19.2.4 + jtag_uart_0 + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq + 0 + + cva6_intel_jtag_uart_0.jtag_uart_0 + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.qip b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.qip new file mode 100644 index 0000000000..c153555939 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.qip @@ -0,0 +1,45 @@ +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_TOOL_VERSION "24.1" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_jtag_uart" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name PRE_COMPILED_MODULE "ON" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name OCS_IP_FILE "/home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_jtag_uart_0.ip" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name OCS_IP_TYPE "altera_avalon_jtag_uart" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name OCS_IP_VERSION "19.2.4" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name OCS_IP_HASH "v3imxwq" +set_global_assignment -library "cva6_intel_jtag_uart_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "cva6_intel_jtag_uart_0.sopcinfo"] +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name SLD_INFO "QSYS_NAME cva6_intel_jtag_uart_0 HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "cva6_intel_jtag_uart_0" -name MISC_FILE [file join $::quartus(qip_path) "cva6_intel_jtag_uart_0.cmp"] +set_global_assignment -library "cva6_intel_jtag_uart_0" -name SLD_FILE [file join $::quartus(qip_path) "cva6_intel_jtag_uart_0.regmap"] +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 7" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 7}" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "cva6_intel_jtag_uart_0" -name MISC_FILE [file join $::quartus(qip_path) "../cva6_intel_jtag_uart_0.ip"] + +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_NAME "Y3ZhNl9pbnRlbF9qdGFnX3VhcnRfMF9hbHRlcmFfYXZhbG9uX2p0YWdfdWFydF8xOTI0X3YzaW14d3E=" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_DISPLAY_NAME "SlRBRyBVQVJUIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_VERSION "MTkuMi40" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_GROUP "SW50ZXJmYWNlIFByb3RvY29scy9TZXJpYWw=" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL3NmbzE0MDA3ODc5NTI5MzIvaWdhMTQwMTMxNzExMjEzOA==" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5NzY4OTMwMA==" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_COMPONENT_NAME "Y3ZhNl9pbnRlbF9qdGFnX3VhcnRfMA==" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "cva6_intel_jtag_uart_0" -library "cva6_intel_jtag_uart_0" -name IP_COMPONENT_VERSION "MS4w" + + +set_global_assignment -library "altera_avalon_jtag_uart_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_jtag_uart_1924/synth/cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq.v"] +set_global_assignment -library "cva6_intel_jtag_uart_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/cva6_intel_jtag_uart_0.v"] + + +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_TOOL_NAME "altera_avalon_jtag_uart" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_TOOL_VERSION "19.2.4" +set_global_assignment -entity "cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" -library "altera_avalon_jtag_uart_1924" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.regmap b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.regmap new file mode 100644 index 0000000000..25cfc7e036 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.regmap @@ -0,0 +1,182 @@ + + +cva6_intel_jtag_uart_0 + + + cva6_intel_jtag_uart_0_avalon_jtag_slave_altera_avalon_jtag_uart0x00000000 + + 0x0 + 8 + registers + + + + DATA + Data + Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost. + 0x0 + 32 + read-write + 0x0 + 0xffffffff + + data + The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO. + 0x0 + 8 + read-write + + rvalid + Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined. + 0xf + 1 + read-only + + ravail + The number of characters remaining in the read FIFO (after the current read). + 0x10 + 16 + read-only + + + + + CONTROL + Control + Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit. + 0x4 + 32 + read-write + 0x0 + 0xffffffff + + re + Interrupt-enable bit for read interrupts. + 0x0 + 1 + read-write + + we + Interrupt-enable bit for write interrupts + 0x1 + 1 + read-write + + ri + Indicates that the read interrupt is pending. + 0x8 + 1 + read-only + + wi + Indicates that the write interrupt is pending. + 0x9 + 1 + read-only + + ac + Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0. + 0xa + 1 + read-write + + wspace + The number of spaces available in the write FIFO + 0x10 + 16 + read-only + + + + + + + cva6_intel_jtag_uart_0_jtag_uart_0_avalon_jtag_slave_altera_avalon_jtag_uart0x00000000 + + 0x0 + 8 + registers + + + + DATA + Data + Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost. + 0x0 + 32 + read-write + 0x0 + 0xffffffff + + data + The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO. + 0x0 + 8 + read-write + + rvalid + Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined. + 0xf + 1 + read-only + + ravail + The number of characters remaining in the read FIFO (after the current read). + 0x10 + 16 + read-only + + + + + CONTROL + Control + Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit. + 0x4 + 32 + read-write + 0x0 + 0xffffffff + + re + Interrupt-enable bit for read interrupts. + 0x0 + 1 + read-write + + we + Interrupt-enable bit for write interrupts + 0x1 + 1 + read-write + + ri + Indicates that the read interrupt is pending. + 0x8 + 1 + read-only + + wi + Indicates that the write interrupt is pending. + 0x9 + 1 + read-only + + ac + Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0. + 0xa + 1 + read-write + + wspace + The number of spaces available in the write FIFO + 0x10 + 16 + read-only + + + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.sopcinfo b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.sopcinfo new file mode 100644 index 0000000000..500f04b680 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.sopcinfo @@ -0,0 +1,1028 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + default + false + true + false + true + BOARD + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.dts.compatible + altr,juart-1.0 + + + embeddedsw.dts.group + serial + + + embeddedsw.dts.name + juart + + + embeddedsw.dts.vendor + altr + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + false + false + true + + + java.lang.String + NO_INTERACTIVE_WINDOWS + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + long + 300000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + 2.0 + false + true + false + true + AVALON_SPEC + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 300000000 + true + true + false + true + + clock + 0 + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + false + + rst_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + true + true + + + java.math.BigInteger + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.math.BigInteger + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 35 + false + true + true + true + + + java.lang.Integer + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + 8 + false + + av_chipselect + Input + 1 + chipselect + + + av_address + Input + 1 + address + + + av_read_n + Input + 1 + read_n + + + av_readdata + Output + 32 + readdata + + + av_write_n + Input + 1 + write_n + + + av_writedata + Input + 32 + writedata + + + av_waitrequest + Output + 1 + waitrequest + + + + + + com.altera.entityinterfaces.IConnectionPoint + jtag_uart_0.avalon_jtag_slave + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + java.lang.Integer + + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + 0 + false + + av_irq + Output + 1 + irq + + + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART Intel FPGA IP + 19.2.4 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 24.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 24.1 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Agent + 24.1 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 24.1 + + 24.1 115 + + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.xml b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.xml new file mode 100644 index 0000000000..b853c4336b --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0.xml @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: cva6_intel_jtag_uart_0" + "Generating: cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" + Starting RTL generation for module 'cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq' + Generation command is [exec /opt/Quartus/quartus/linux64//perl/bin/perl -I /opt/Quartus/quartus/linux64//perl/lib -I /opt/Quartus/quartus/sopc_builder/bin/europa -I /opt/Quartus/quartus/sopc_builder/bin/perl_lib -I /opt/Quartus/quartus/sopc_builder/bin -I /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/common -I /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq --dir=/tmp/alt9934_17442513099174763394.dir/0001_jtag_uart_0_gen/ --quartus_dir=/opt/Quartus/quartus --verilog --config=/tmp/alt9934_17442513099174763394.dir/0001_jtag_uart_0_gen//cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq' + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" + Starting RTL generation for module 'cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq' + Generation command is [exec /opt/Quartus/quartus/linux64//perl/bin/perl -I /opt/Quartus/quartus/linux64//perl/lib -I /opt/Quartus/quartus/sopc_builder/bin/europa -I /opt/Quartus/quartus/sopc_builder/bin/perl_lib -I /opt/Quartus/quartus/sopc_builder/bin -I /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/common -I /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq --dir=/tmp/alt9934_17442513099174763394.dir/0001_jtag_uart_0_gen/ --quartus_dir=/opt/Quartus/quartus --verilog --config=/tmp/alt9934_17442513099174763394.dir/0001_jtag_uart_0_gen//cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq' + + + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_bb.v b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_bb.v new file mode 100644 index 0000000000..89c32e450f --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_bb.v @@ -0,0 +1,14 @@ +module cva6_intel_jtag_uart_0 ( + input wire clk, // clk.clk + input wire rst_n, // reset.reset_n + input wire av_chipselect, // avalon_jtag_slave.chipselect + input wire av_address, // .address + input wire av_read_n, // .read_n + output wire [31:0] av_readdata, // .readdata + input wire av_write_n, // .write_n + input wire [31:0] av_writedata, // .writedata + output wire av_waitrequest, // .waitrequest + output wire av_irq // irq.irq + ); +endmodule + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_generation.rpt b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_generation.rpt new file mode 100644 index 0000000000..e082881593 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_generation.rpt @@ -0,0 +1,19 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_jtag_uart_0.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_jtag_uart_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: cva6_intel_jtag_uart_0.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_jtag_uart_0.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/ip/cva6_intel/cva6_intel_jtag_uart_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: cva6_intel_jtag_uart_0.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board +Info: cva6_intel_jtag_uart_0: "Transforming system: cva6_intel_jtag_uart_0" +Info: cva6_intel_jtag_uart_0: "Naming system components in system: cva6_intel_jtag_uart_0" +Info: cva6_intel_jtag_uart_0: "Processing generation queue" +Info: cva6_intel_jtag_uart_0: "Generating: cva6_intel_jtag_uart_0" +Info: cva6_intel_jtag_uart_0: "Generating: cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq" +Info: jtag_uart_0: Starting RTL generation for module 'cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq' +Info: jtag_uart_0: Generation command is [exec /opt/Quartus/quartus/linux64//perl/bin/perl -I /opt/Quartus/quartus/linux64//perl/lib -I /opt/Quartus/quartus/sopc_builder/bin/europa -I /opt/Quartus/quartus/sopc_builder/bin/perl_lib -I /opt/Quartus/quartus/sopc_builder/bin -I /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/common -I /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /opt/Quartus/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq --dir=/tmp/alt9934_17442513099174763394.dir/0001_jtag_uart_0_gen/ --quartus_dir=/opt/Quartus/quartus --verilog --config=/tmp/alt9934_17442513099174763394.dir/0001_jtag_uart_0_gen//cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq_component_configuration.pl --do_build_sim=0 ] +Info: jtag_uart_0: Done RTL generation for module 'cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq' +Info: cva6_intel_jtag_uart_0: Done "cva6_intel_jtag_uart_0" with 2 modules, 2 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_inst.v b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_inst.v new file mode 100644 index 0000000000..0588fd6807 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_inst.v @@ -0,0 +1,13 @@ + cva6_intel_jtag_uart_0 u0 ( + .clk (_connected_to_clk_), // input, width = 1, clk.clk + .rst_n (_connected_to_rst_n_), // input, width = 1, reset.reset_n + .av_chipselect (_connected_to_av_chipselect_), // input, width = 1, avalon_jtag_slave.chipselect + .av_address (_connected_to_av_address_), // input, width = 1, .address + .av_read_n (_connected_to_av_read_n_), // input, width = 1, .read_n + .av_readdata (_connected_to_av_readdata_), // output, width = 32, .readdata + .av_write_n (_connected_to_av_write_n_), // input, width = 1, .write_n + .av_writedata (_connected_to_av_writedata_), // input, width = 32, .writedata + .av_waitrequest (_connected_to_av_waitrequest_), // output, width = 1, .waitrequest + .av_irq (_connected_to_av_irq_) // output, width = 1, irq.irq + ); + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_inst.vhd b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_inst.vhd new file mode 100644 index 0000000000..f9cacf38b5 --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/cva6_intel_jtag_uart_0_inst.vhd @@ -0,0 +1,29 @@ + component cva6_intel_jtag_uart_0 is + port ( + clk : in std_logic := 'X'; -- clk + rst_n : in std_logic := 'X'; -- reset_n + av_chipselect : in std_logic := 'X'; -- chipselect + av_address : in std_logic := 'X'; -- address + av_read_n : in std_logic := 'X'; -- read_n + av_readdata : out std_logic_vector(31 downto 0); -- readdata + av_write_n : in std_logic := 'X'; -- write_n + av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + av_waitrequest : out std_logic; -- waitrequest + av_irq : out std_logic -- irq + ); + end component cva6_intel_jtag_uart_0; + + u0 : component cva6_intel_jtag_uart_0 + port map ( + clk => CONNECTED_TO_clk, -- clk.clk + rst_n => CONNECTED_TO_rst_n, -- reset.reset_n + av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect + av_address => CONNECTED_TO_av_address, -- .address + av_read_n => CONNECTED_TO_av_read_n, -- .read_n + av_readdata => CONNECTED_TO_av_readdata, -- .readdata + av_write_n => CONNECTED_TO_av_write_n, -- .write_n + av_writedata => CONNECTED_TO_av_writedata, -- .writedata + av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest + av_irq => CONNECTED_TO_av_irq -- irq.irq + ); + diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0/synth/cva6_intel_jtag_uart_0.v b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/synth/cva6_intel_jtag_uart_0.v new file mode 100644 index 0000000000..369dffa8bf --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0/synth/cva6_intel_jtag_uart_0.v @@ -0,0 +1,32 @@ +// cva6_intel_jtag_uart_0.v + +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module cva6_intel_jtag_uart_0 ( + input wire clk, // clk.clk + input wire rst_n, // reset.reset_n + input wire av_chipselect, // avalon_jtag_slave.chipselect + input wire av_address, // .address + input wire av_read_n, // .read_n + output wire [31:0] av_readdata, // .readdata + input wire av_write_n, // .write_n + input wire [31:0] av_writedata, // .writedata + output wire av_waitrequest, // .waitrequest + output wire av_irq // irq.irq + ); + + cva6_intel_jtag_uart_0_altera_avalon_jtag_uart_1924_v3imxwq jtag_uart_0 ( + .clk (clk), // input, width = 1, clk.clk + .rst_n (rst_n), // input, width = 1, reset.reset_n + .av_chipselect (av_chipselect), // input, width = 1, avalon_jtag_slave.chipselect + .av_address (av_address), // input, width = 1, .address + .av_read_n (av_read_n), // input, width = 1, .read_n + .av_readdata (av_readdata), // output, width = 32, .readdata + .av_write_n (av_write_n), // input, width = 1, .write_n + .av_writedata (av_writedata), // input, width = 32, .writedata + .av_waitrequest (av_waitrequest), // output, width = 1, .waitrequest + .av_irq (av_irq) // output, width = 1, irq.irq + ); + +endmodule diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0.ip b/corev_apu/altera/ip/ed_synth_emif_fm_0.ip new file mode 100644 index 0000000000..88846cfdee --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0.ip @@ -0,0 +1,10744 @@ + + + + Intel Corporation + ed_synth_emif_fm_0 + emif_fm_0 + 2.7.4 + + + local_reset_req + + + + + + + + local_reset_req + + + local_reset_req + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + local_reset_status + + + + + + + + local_reset_done + + + local_reset_done + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + pll_ref_clk + + + + + + + + clk + + + pll_ref_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + pll_locked + + + + + + + + pll_locked + + + pll_locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + oct + + + + + + + + oct_rzqin + + + oct_rzqin + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + mem + + + + + + + + mem_ck + + + mem_ck + + + + + mem_ck_n + + + mem_ck_n + + + + + mem_a + + + mem_a + + + + + mem_act_n + + + mem_act_n + + + + + mem_ba + + + mem_ba + + + + + mem_bg + + + mem_bg + + + + + mem_cke + + + mem_cke + + + + + mem_cs_n + + + mem_cs_n + + + + + mem_odt + + + mem_odt + + + + + mem_reset_n + + + mem_reset_n + + + + + mem_par + + + mem_par + + + + + mem_alert_n + + + mem_alert_n + + + + + mem_dqs + + + mem_dqs + + + + + mem_dqs_n + + + mem_dqs_n + + + + + mem_dq + + + mem_dq + + + + + mem_dbi_n + + + mem_dbi_n + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + status + + + + + + + + local_cal_success + + + local_cal_success + + + + + local_cal_fail + + + local_cal_fail + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + emif_calbus + + + + + + + + calbus_read + + + calbus_read + + + + + calbus_write + + + calbus_write + + + + + calbus_address + + + calbus_address + + + + + calbus_wdata + + + calbus_wdata + + + + + calbus_rdata + + + calbus_rdata + + + + + calbus_seq_param_tbl + + + calbus_seq_param_tbl + + + + + + + + + associatedClock + associatedClock + emif_calbus_clk + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + emif_calbus_clk + + + + + + + + clk + + + calbus_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + emif_usr_reset_n + + + + + + + + reset_n + + + emif_usr_reset_n + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + + + + associatedResetSinks + Associated reset sinks + none + + + synchronousEdges + Synchronous edges + NONE + + + + + emif_usr_clk + + + + + + + + clk + + + emif_usr_clk + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 300000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + ctrl_ecc_user_interrupt_0 + + + + + + + + ctrl_ecc_user_interrupt + + + ctrl_ecc_user_interrupt_0 + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + ctrl_amm_0 + + + + + + + + waitrequest_n + + + amm_ready_0 + + + + + read + + + amm_read_0 + + + + + write + + + amm_write_0 + + + + + address + + + amm_address_0 + + + + + readdata + + + amm_readdata_0 + + + + + writedata + + + amm_writedata_0 + + + + + burstcount + + + amm_burstcount_0 + + + + + byteenable + + + amm_byteenable_0 + + + + + readdatavalid + + + amm_readdatavalid_0 + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 8589934592 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + emif_usr_clk + + + associatedReset + Associated reset + emif_usr_reset_n + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + true + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 64 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 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dfhFeatureMajorVersion + Feature major version + 0 + + + dfhFeatureMinorVersion + Feature minor version + 0 + + + dfhFeatureId + Feature ID + 35 + + + dfhFeatureType + Feature Type + 3 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_emif_fm + + QUARTUS_SYNTH + + + + + + local_reset_req + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + local_reset_done + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_ref_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + oct_rzqin + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + mem_ck + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_ck_n + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + 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SYS_INFO_DEVICE_TEMPERATURE_GRADE + PARAM_SYS_INFO_DEVICE_TEMPERATURE_GRADE_NAME + EXTENDED + + + SYS_INFO_DEVICE_POWER_MODEL + PARAM_SYS_INFO_DEVICE_POWER_MODEL_NAME + STANDARD_POWER + + + SYS_INFO_DEVICE_DIE_REVISIONS + PARAM_SYS_INFO_DEVICE_DIE_REVISIONS_NAME + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + + + TRAIT_SUPPORTS_VID + PARAM_TRAIT_SUPPORTS_VID_NAME + 1 + + + TRAIT_IOBANK_REVISION + PARAM_TRAIT_IOBANK_REVISION_NAME + IO96A_REVB2 + + + PROTOCOL_ENUM + Protocol + PROTOCOL_DDR4 + + + IS_ED_SLAVE + PARAM_IS_ED_SLAVE_NAME + false + + + INTERNAL_TESTING_MODE + PARAM_INTERNAL_TESTING_MODE_NAME + false + + + CAL_DEBUG_CLOCK_FREQUENCY + PARAM_CAL_DEBUG_CLOCK_FREQUENCY_NAME + 50000000 + + + SYS_INFO_UNIQUE_ID + PARAM_SYS_INFO_UNIQUE_ID_NAME + ed_synth_emif_fm_0_emif_fm_0 + + + PLL_ADD_EXTRA_CLKS + Specify additional core clocks based on existing PLL + false + + + PLL_USER_NUM_OF_EXTRA_CLKS + Number of additional core clocks + 0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8_NAME + 50.0 + + + PHY_DDR3_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDR3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDR3_IO_VOLTAGE + Voltage + 1.5 + + + PHY_DDR3_DEFAULT_IO + Use default I/O settings + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_DDR3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDR3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDR3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_DDR3_CAL_ADDR0 + PARAM_PHY_DDR3_CAL_ADDR0_NAME + 0 + + + PHY_DDR3_CAL_ADDR1 + PARAM_PHY_DDR3_CAL_ADDR1_NAME + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + PARAM_PHY_DDR3_CAL_ENABLE_NON_DES_NAME + false + + + PHY_DDR4_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDR4_USER_CLAMSHELL_EN + Use clamshell layout + false + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1200.0 + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + false + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + 33.333 + + + PHY_DDR4_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDR4_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDR4_IO_VOLTAGE + Voltage + 1.2 + + + PHY_DDR4_DEFAULT_IO + Use default I/O settings + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDR4_ALLOW_72_DQ_WIDTH + Allow DQ Widths of 72 + false + + + PHY_DDR4_USER_AC_IO_STD_ENUM + I/O standard + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + I/O standard + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + I/O standard + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + Input mode + IN_OCT_60_CAL + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDR4_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + IO_STD_CMOS_12 + + + PHY_QDR2_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + Memory clock frequency + 633.333 + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_QDR2_RATE_ENUM + Clock rate of user logic + RATE_HALF + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_QDR2_IO_VOLTAGE + Voltage + 1.5 + + + PHY_QDR2_DEFAULT_IO + Use default I/O settings + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_QDR2_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_QDR2_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_QDR2_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_QDR4_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_QDR4_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_QDR4_IO_VOLTAGE + Voltage + 1.2 + + + PHY_QDR4_DEFAULT_IO + Use default I/O settings + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_QDR4_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_QDR4_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_QDR4_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_RLD2_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + Memory clock frequency + 533.333 + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_RLD2_RATE_ENUM + Clock rate of user logic + RATE_HALF + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_RLD2_IO_VOLTAGE + Voltage + 1.8 + + + PHY_RLD2_DEFAULT_IO + Use default I/O settings + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_RLD2_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_RLD2_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_RLD2_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_RLD3_CONFIG_ENUM + Configuration + CONFIG_PHY_ONLY + + + PHY_RLD3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_RLD3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_RLD3_IO_VOLTAGE + Voltage + 1.2 + + + PHY_RLD3_DEFAULT_IO + Use default I/O settings + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_RLD3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_RLD3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_RLD3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_LPDDR3_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 800.0 + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_LPDDR3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_LPDDR3_IO_VOLTAGE + Voltage + 1.2 + + + PHY_LPDDR3_DEFAULT_IO + Use default I/O settings + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_LPDDR3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_LPDDR3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_DDRT_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1200.0 + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDRT_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDRT_IO_VOLTAGE + Voltage + 1.2 + + + PHY_DDRT_DEFAULT_IO + Use default I/O settings + true + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDRT_IC_EN + Enable I2C Master + true + + + PHY_DDRT_2CH_EN + Enable 2 Channel + false + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + Enable I2C Multicolumn + false + + + PHY_DDRT_EXPORT_CLK_STP_IF + Export Clock Stop Interface + false + + + PHY_DDRT_I2C_USE_SMC + PARAM_PHY_I2C_USE_SMC_NAME + false + + + PHY_DDRT_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + Input mode + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDRT_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + MEM_DDR3_FORMAT_ENUM + Memory format + MEM_FORMAT_UDIMM + + + MEM_DDR3_DQ_WIDTH + DQ width + 72 + + + MEM_DDR3_DQ_PER_DQS + DQ pins per DQS group + 8 + + + MEM_DDR3_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDR3_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDR3_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDR3_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDR3_CK_WIDTH + Number of clocks + 1 + + + MEM_DDR3_ROW_ADDR_WIDTH + Row address width + 15 + + + MEM_DDR3_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDR3_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_DDR3_DM_EN + Enable DM pins + true + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDR3_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDR3_RDIMM_CONFIG + DDR3 RDIMM/LRDIMM control words + 0000000000000000 + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + DDR3 LRDIMM additional control words + 000000000000000000 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDR3_BL_ENUM + Burst Length + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + Read Burst Type + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_ASR_ENUM + Auto self-refresh method + DDR3_ASR_MANUAL + + + MEM_DDR3_SRT_ENUM + Self-refresh temperature + DDR3_SRT_NORMAL + + + MEM_DDR3_PD_ENUM + DLL precharge power down + DDR3_PD_OFF + + + MEM_DDR3_DRV_STR_ENUM + Output drive strength setting + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDR3_RTT_NOM_ENUM + ODT Rtt nominal value + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_WTCL + Memory write CAS latency setting + 10 + + + MEM_DDR3_ATCL_ENUM + Memory additive CAS latency setting + DDR3_ATCL_DISABLED + + + MEM_DDR3_TCL + Memory CAS latency setting + 14 + + + MEM_DDR3_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDR3_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDR3_R_ODT0_1X1 + ODT0 + off + + + MEM_DDR3_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDR3_W_ODT0_1X1 + ODT0 + on + + + MEM_DDR3_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDR3_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDR3_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDR3_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDR3_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDR3_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDR3_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR3_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR3_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR3_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR3_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODT0_4X4 + ODT0 + off,off,on,off + + + MEM_DDR3_R_ODT1_4X4 + ODT1 + off,off,off,on + + + MEM_DDR3_R_ODT2_4X4 + ODT2 + on,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + ODT3 + off,on,off,off + + + MEM_DDR3_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODT0_4X4 + ODT0 + on,off,on,off + + + MEM_DDR3_W_ODT1_4X4 + ODT1 + off,on,off,on + + + MEM_DDR3_W_ODT2_4X4 + ODT2 + on,off,on,off + + + MEM_DDR3_W_ODT3_4X4 + ODT3 + off,on,off,on + + + MEM_DDR3_SPEEDBIN_ENUM + Speed bin + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_TIS_PS + tIS (base) + 60 + + + MEM_DDR3_TIS_AC_MV + tIS (base) AC level + 135 + + + MEM_DDR3_TIH_PS + tIH (base) + 95 + + + MEM_DDR3_TIH_DC_MV + tIH (base) DC level + 100 + + + MEM_DDR3_TDS_PS + tDS (base) + 53 + + + MEM_DDR3_TDS_AC_MV + tDS (base) AC level + 135 + + + MEM_DDR3_TDH_PS + tDH (base) + 55 + + + MEM_DDR3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_DDR3_TDQSQ_PS + tDQSQ + 75 + + + MEM_DDR3_TQH_CYC + tQH + 0.38 + + + MEM_DDR3_TDQSCK_PS + tDQSCK + 180 + + + MEM_DDR3_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDR3_TQSH_CYC + tQSH + 0.4 + + + MEM_DDR3_TDSH_CYC + tDSH + 0.18 + + + MEM_DDR3_TWLS_PS + tWLS + 125.0 + + + MEM_DDR3_TWLH_PS + tWLH + 125.0 + + + MEM_DDR3_TDSS_CYC + tDSS + 0.18 + + + MEM_DDR3_TINIT_US + tINIT + 500 + + + MEM_DDR3_TMRD_CK_CYC + tMRD + 4 + + + MEM_DDR3_TRAS_NS + tRAS + 33.0 + + + MEM_DDR3_TRCD_NS + tRCD + 13.09 + + + MEM_DDR3_TRP_NS + tRP + 13.09 + + + MEM_DDR3_TREFI_US + tREFI + 7.8 + + + MEM_DDR3_TRFC_NS + tRFC + 160.0 + + + MEM_DDR3_TWR_NS + tWR + 15.0 + + + MEM_DDR3_TWTR_CYC + tWTR + 8 + + + MEM_DDR3_TFAW_NS + tFAW + 25.0 + + + MEM_DDR3_TRRD_CYC + tRRD + 6 + + + MEM_DDR3_TRTP_CYC + tRTP + 8 + + + MEM_DDR3_CFG_GEN_SBE + PARAM_MEM_DDR3_CFG_GEN_SBE_NAME + false + + + MEM_DDR3_CFG_GEN_DBE + PARAM_MEM_DDR3_CFG_GEN_DBE_NAME + false + + + MEM_DDR4_FORMAT_ENUM + Memory format + MEM_FORMAT_RDIMM + + + MEM_DDR4_DQ_WIDTH + DQ width + 72 + + + MEM_DDR4_DQ_PER_DQS + DQ pins per DQS group + 8 + + + MEM_DDR4_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDR4_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDR4_CHIP_ID_WIDTH + Chip ID width + 0 + + + MEM_DDR4_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDR4_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDR4_CK_WIDTH + Number of clocks + 1 + + + MEM_DDR4_ROW_ADDR_WIDTH + Row address width + 16 + + + MEM_DDR4_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDR4_BANK_ADDR_WIDTH + Bank address width + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + Bank group width + 2 + + + MEM_DDR4_DM_EN + Data mask + true + + + MEM_DDR4_ALERT_PAR_EN + Enable ALERT#/PAR pins + true + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + + + MEM_DDR4_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDR4_ALERT_N_AC_LANE + Address/command I/O lane of ALERT# + 3 + + + MEM_DDR4_ALERT_N_AC_PIN + Pin index of ALERT# + 8 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDR4_INTEL_DEFAULT_TERM + Use Default Memory I/O Settings + true + + + MEM_DDR4_BL_ENUM + Burst Length + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + Read Burst Type + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_TCL + Memory CAS latency setting + 21 + + + MEM_DDR4_RTT_NOM_ENUM + ODT Rtt nominal value + DDR4_RTT_NOM_RZQ_4 + + + MEM_DDR4_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDR4_ATCL_ENUM + Memory additive CAS latency setting + DDR4_ATCL_DISABLED + + + MEM_DDR4_DRV_STR_ENUM + Output drive strength setting + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_ASR_ENUM + Auto self-refresh method + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_WTCL + Memory write CAS latency setting + 16 + + + MEM_DDR4_WRITE_CRC + Write CRC enable + false + + + MEM_DDR4_GEARDOWN + DDR4 geardown mode + DDR4_GEARDOWN_HR + + + MEM_DDR4_PER_DRAM_ADDR + Per-DRAM addressability + false + + + MEM_DDR4_TEMP_SENSOR_READOUT + Temperature sensor readout + false + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + Fine granularity refresh + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_MPR_READ_FORMAT + MPR read format + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MAX_POWERDOWN + Maximum power down mode + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + Temperature controlled refresh range + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + Temperature controlled refresh enable + false + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + Internal VrefDQ monitor + false + + + MEM_DDR4_CAL_MODE + CS to Addr/CMD Latency + 0 + + + MEM_DDR4_SELF_RFSH_ABORT + Self refresh abort + false + + + MEM_DDR4_READ_PREAMBLE_TRAINING + Read preamble training mode enable + false + + + MEM_DDR4_READ_PREAMBLE + Read preamble + 2 + + + MEM_DDR4_WRITE_PREAMBLE + Write preamble + 1 + + + MEM_DDR4_AC_PARITY_LATENCY + Addr/CMD parity latency + DDR4_AC_PARITY_LATENCY_DISABLE + + + MEM_DDR4_ODT_IN_POWERDOWN + ODT input buffer during powerdown mode + true + + + MEM_DDR4_RTT_PARK + RTT PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_AC_PERSISTENT_ERROR + Addr/CMD persistent error + false + + + MEM_DDR4_WRITE_DBI + Write DBI + false + + + MEM_DDR4_READ_DBI + Read DBI + true + + + MEM_DDR4_DEFAULT_VREFOUT + Use recommended initial VrefDQ value + true + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + VrefDQ training value + 56.0 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + VrefDQ training range + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + RCD CA Input Bus Termination + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CS_IBT_ENUM + RCD DCS[3:0]_n Input Bus Termination + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + RCD DCKE Input Bus Termination + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + RCD DODT Input Bus Termination + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DB Host Interface DQ RTT_NOM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DB Host Interface DQ RTT_WR + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DB_RTT_PARK_ENUM + DB Host Interface DQ RTT_PARK + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_DQ_DRV_ENUM + DB Host Interface DQ Driver + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + SPD Byte 137 - RCD Drive Strength for Command/Address + 101 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + SPD Byte 138 - RCD Drive Strength for CK + 5 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + SPD Byte 140 - DRAM VrefDQ for Package Rank 0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + SPD Byte 141 - DRAM VrefDQ for Package Rank 1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + SPD Byte 142 - DRAM VrefDQ for Package Rank 2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + SPD Byte 143 - DRAM VrefDQ for Package Rank 3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + SPD Byte 144 - DB VrefDQ for DRAM Interface + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + SPD Byte 145-147 - DB MDQ Drive Strength and RTT + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + SPD Byte 148 - DRAM Drive Strength + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + SPD Byte 152-154 - DRAM ODT (RTT_PARK) + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + SPD Byte 155 - DB VrefDQ for DRAM Interface Range + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + RCD and DB Manufacturer (LSB) + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + RCD and DB Manufacturer (MSB) + 0 + + + MEM_DDR4_SPD_135_RCD_REV + RCD Revision Number + 0 + + + MEM_DDR4_SPD_139_DB_REV + DB Revision Number + 0 + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + PARAM_MEM_DDR4_LRDIMM_ODT_LESS_BS_NAME + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + PARAM_MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM_NAME + 240 + + + MEM_DDR4_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDR4_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDR4_R_ODT0_1X1 + ODT0 + off + + + MEM_DDR4_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDR4_W_ODT0_1X1 + ODT0 + on + + + MEM_DDR4_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDR4_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDR4_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDR4_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDR4_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDR4_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDR4_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR4_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR4_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR4_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR4_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODT0_4X4 + ODT0 + off,off,on,off + + + MEM_DDR4_R_ODT1_4X4 + ODT1 + off,off,off,on + + + MEM_DDR4_R_ODT2_4X4 + ODT2 + on,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + ODT3 + off,on,off,off + + + MEM_DDR4_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODT0_4X4 + ODT0 + on,off,on,off + + + MEM_DDR4_W_ODT1_4X4 + ODT1 + off,on,off,on + + + MEM_DDR4_W_ODT2_4X4 + ODT2 + on,off,on,off + + + MEM_DDR4_W_ODT3_4X4 + ODT3 + off,on,off,on + + + MEM_DDR4_SPEEDBIN_ENUM + Speed bin + DDR4_SPEEDBIN_2666 + + + MEM_DDR4_TIS_PS + tIS (base) + 62 + + + MEM_DDR4_TIS_AC_MV + tIS (base) AC level + 100 + + + MEM_DDR4_TIH_PS + tIH (base) + 87 + + + MEM_DDR4_TIH_DC_MV + tIH (base) DC level + 75 + + + MEM_DDR4_TDIVW_TOTAL_UI + TdiVW_total + 0.2 + + + MEM_DDR4_VDIVW_TOTAL + VdiVW_total + 130 + + + MEM_DDR4_TDQSQ_UI + tDQSQ + 0.14 + + + MEM_DDR4_TQH_UI + tQH + 0.74 + + + MEM_DDR4_TDVWP_UI + tDVWp + 0.72 + + + MEM_DDR4_TDQSCK_PS + tDQSCK + 175 + + + MEM_DDR4_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDR4_TQSH_CYC + tQSH + 0.4 + + + MEM_DDR4_TDSH_CYC + tDSH + 0.18 + + + MEM_DDR4_TDSS_CYC + tDSS + 0.18 + + + MEM_DDR4_TWLS_CYC + tWLS + 0.13 + + + MEM_DDR4_TWLH_CYC + tWLH + 0.13 + + + MEM_DDR4_TINIT_US + tINIT + 500 + + + MEM_DDR4_TMRD_CK_CYC + tMRD + 8 + + + MEM_DDR4_TRAS_NS + tRAS + 32.0 + + + MEM_DDR4_TRCD_NS + tRCD + 14.16 + + + MEM_DDR4_TRP_NS + tRP + 14.16 + + + MEM_DDR4_TREFI_US + tREFI + 7.8 + + + MEM_DDR4_TRFC_NS + tRFC + 350.0 + + + MEM_DDR4_TWR_NS + tWR + 15.0 + + + MEM_DDR4_TWTR_L_CYC + tWTR_L + 9 + + + MEM_DDR4_TWTR_S_CYC + tWTR_S + 3 + + + MEM_DDR4_TFAW_NS + tFAW + 21.0 + + + MEM_DDR4_TRRD_L_CYC + tRRD_L + 6 + + + MEM_DDR4_TRRD_S_CYC + tRRD_S + 4 + + + MEM_DDR4_TCCD_L_CYC + tCCD_L + 6 + + + MEM_DDR4_TCCD_S_CYC + tCCD_S + 4 + + + MEM_DDR4_TRFC_DLR_NS + tRFC_dlr + 90.0 + + + MEM_DDR4_TFAW_DLR_CYC + tFAW_dlr + 16 + + + MEM_DDR4_TRRD_DLR_CYC + tRRD_dlr + 4 + + + MEM_DDR4_TDIVW_DJ_CYC + PARAM_MEM_DDR4_TDIVW_DJ_CYC_NAME + 0.1 + + + MEM_DDR4_TDQSQ_PS + PARAM_MEM_DDR4_TDQSQ_PS_NAME + 66 + + + MEM_DDR4_TQH_CYC + PARAM_MEM_DDR4_TQH_CYC_NAME + 0.38 + + + MEM_DDR4_CFG_GEN_SBE + PARAM_MEM_DDR4_CFG_GEN_SBE_NAME + false + + + MEM_DDR4_CFG_GEN_DBE + PARAM_MEM_DDR4_CFG_GEN_DBE_NAME + false + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + PARAM_MEM_DDR4_LRDIMM_VREFDQ_VALUE_NAME + + + + MEM_DDR4_TWLS_PS + PARAM_MEM_DDR4_TWLS_PS_NAME + 0.0 + + + MEM_DDR4_TWLH_PS + PARAM_MEM_DDR4_TWLH_PS_NAME + 0.0 + + + MEM_QDR2_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_QDR2_DATA_PER_DEVICE + Data width per device + 36 + + + MEM_QDR2_ADDR_WIDTH + Address width + 19 + + + MEM_QDR2_BWS_EN + Enable BWS# pins + true + + + MEM_QDR2_BL + Burst length + 4 + + + MEM_QDR2_SPEEDBIN_ENUM + Speed bin + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TRL_CYC + tRL + 2.5 + + + MEM_QDR2_TSA_NS + tSA + 0.23 + + + MEM_QDR2_THA_NS + tHA + 0.18 + + + MEM_QDR2_TSD_NS + tSD + 0.23 + + + MEM_QDR2_THD_NS + tHD + 0.18 + + + MEM_QDR2_TCQD_NS + tCQD + 0.09 + + + MEM_QDR2_TCQDOH_NS + tCQDOH + -0.09 + + + MEM_QDR2_INTERNAL_JITTER_NS + Internal Jitter + 0.08 + + + MEM_QDR2_TCQH_NS + tCQH + 0.71 + + + MEM_QDR2_TCCQO_NS + tCCQO + 0.45 + + + MEM_QDR4_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + DQ width per device + 36 + + + MEM_QDR4_ADDR_WIDTH + Address width + 21 + + + MEM_QDR4_SKIP_ODT_SWEEPING + Skip automatic optimization of Clock and Address/Command ODT setting during calibration + true + + + MEM_QDR4_CK_ODT_MODE_ENUM + ODT (Clock) + QDR4_ODT_25_PCT + + + MEM_QDR4_AC_ODT_MODE_ENUM + ODT (Address/Command) + QDR4_ODT_25_PCT + + + MEM_QDR4_DATA_ODT_MODE_ENUM + ODT (Data) + QDR4_ODT_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + Output drive (pull-up) + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + Output drive (pull-down) + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_MEM_TYPE_ENUM + Memory Type + MEM_XP + + + MEM_QDR4_DATA_INV_ENA + Data bus inversion + true + + + MEM_QDR4_ADDR_INV_ENA + Address bus inversion + false + + + MEM_QDR4_USE_ADDR_PARITY + Use address parity bit + false + + + MEM_QDR4_SPEEDBIN_ENUM + Speed bin + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TISH_PS + tISH + 150 + + + MEM_QDR4_TQKQ_MAX_PS + tQKQ_max + 75 + + + MEM_QDR4_TQH_CYC + tQH + 0.4 + + + MEM_QDR4_TCKDK_MAX_PS + tCKDK_max + 150 + + + MEM_QDR4_TCKDK_MIN_PS + tCKDK_min + -150 + + + MEM_QDR4_TCKQK_MAX_PS + tCKQK_max + 225 + + + MEM_QDR4_TASH_PS + tASH + 170 + + + MEM_QDR4_TCSH_PS + tCSH + 170 + + + MEM_RLD2_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_RLD2_DQ_PER_DEVICE + DQ width per device + 9 + + + MEM_RLD2_ADDR_WIDTH + Address width + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_RLD2_DM_EN + Enable DM pins + true + + + MEM_RLD2_BL + Burst length + 4 + + + MEM_RLD2_CONFIG_ENUM + Configuration + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + Drive Impedance + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_ODT_MODE_ENUM + On-Die Termination + RLD2_ODT_ON + + + MEM_RLD2_SPEEDBIN_ENUM + Speed bin + RLD2_SPEEDBIN_18 + + + MEM_RLD2_REFRESH_INTERVAL_US + Refresh Interval + 0.24 + + + MEM_RLD2_TCKH_CYC + tCKH + 0.45 + + + MEM_RLD2_TQKH_HCYC + tQKH + 0.9 + + + MEM_RLD2_TAS_NS + tAS + 0.3 + + + MEM_RLD2_TAH_NS + tAH + 0.3 + + + MEM_RLD2_TDS_NS + tDS + 0.17 + + + MEM_RLD2_TDH_NS + tDH + 0.17 + + + MEM_RLD2_TQKQ_MAX_NS + tQKQ_max + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + tQKQ_min + -0.12 + + + MEM_RLD2_TCKDK_MAX_NS + tCKDK_max + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + tCKDK_min + -0.3 + + + MEM_RLD2_TCKQK_MAX_NS + tCKQK_max + 0.2 + + + MEM_RLD3_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_RLD3_DEPTH_EXPANDED + Enable depth expansion using twin die package + false + + + MEM_RLD3_DQ_PER_DEVICE + DQ width per device + 36 + + + MEM_RLD3_ADDR_WIDTH + Address width + 20 + + + MEM_RLD3_BANK_ADDR_WIDTH + Bank address width + 4 + + + MEM_RLD3_DM_EN + Enable DM pins + true + + + MEM_RLD3_BL + Burst length + 2 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + Data Latency + RLD3_DL_RL16_WL17 + + + MEM_RLD3_T_RC_MODE_ENUM + tRC + RLD3_TRC_9 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + Output drive + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_ODT_MODE_ENUM + ODT + RLD3_ODT_40 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + AREF protocol + RLD3_AREF_BAC + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + Write protocol + RLD3_WRITE_1BANK + + + MEM_RLD3_SPEEDBIN_ENUM + Speed bin + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TDS_PS + tDS (base) + -30 + + + MEM_RLD3_TDS_AC_MV + tDS (base) AC level + 150 + + + MEM_RLD3_TDH_PS + tDH (base) + 5 + + + MEM_RLD3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_RLD3_TQKQ_MAX_PS + tQKQ_max + 75 + + + MEM_RLD3_TQH_CYC + tQH + 0.38 + + + MEM_RLD3_TCKDK_MAX_CYC + tCKDK_max + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + tCKDK_min + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + tCKQK_max + 135 + + + MEM_RLD3_TIS_PS + tIS (base) + 85 + + + MEM_RLD3_TIS_AC_MV + tIS (base) AC level + 150 + + + MEM_RLD3_TIH_PS + tIH (base) + 65 + + + MEM_RLD3_TIH_DC_MV + tIH (base) DC level + 100 + + + MEM_LPDDR3_DQ_WIDTH + DQ width + 32 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_LPDDR3_CK_WIDTH + Number of clocks + 1 + + + MEM_LPDDR3_DM_EN + Enable DM pins + true + + + MEM_LPDDR3_ROW_ADDR_WIDTH + Row address width + 15 + + + MEM_LPDDR3_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_LPDDR3_BL + Burst length + LPDDR3_BL_BL8 + + + MEM_LPDDR3_DATA_LATENCY + Data latency + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DRV_STR + Output drive strength setting + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_DQODT + DQ ODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_PDODT + Power down ODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_LPDDR3_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_LPDDR3_R_ODT0_1X1 + ODT0 + off + + + MEM_LPDDR3_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_LPDDR3_W_ODT0_1X1 + ODT0 + on + + + MEM_LPDDR3_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODT0_2X2 + ODT0 + off,off + + + MEM_LPDDR3_R_ODT1_2X2 + ODT1 + off,off + + + MEM_LPDDR3_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODT0_2X2 + ODT0 + on,on + + + MEM_LPDDR3_W_ODT1_2X2 + ODT1 + off,off + + + MEM_LPDDR3_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_4X4 + ODT1 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + ODT3 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_W_ODT0_4X4 + ODT0 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_4X4 + ODT1 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + ODT3 + off,off,off,off + + + MEM_LPDDR3_SPEEDBIN_ENUM + Speed bin + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TIS_PS + tISCA (base) + 75 + + + MEM_LPDDR3_TIS_AC_MV + tISCA (base) AC level + 150 + + + MEM_LPDDR3_TIH_PS + tIHCA (base) + 100 + + + MEM_LPDDR3_TIH_DC_MV + tIHCA (base) DC level + 100 + + + MEM_LPDDR3_TDS_PS + tDS (base) + 75 + + + MEM_LPDDR3_TDS_AC_MV + tDS (base) AC level + 150 + + + MEM_LPDDR3_TDH_PS + tDH (base) + 100 + + + MEM_LPDDR3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_LPDDR3_TDQSQ_PS + tDQSQ + 135 + + + MEM_LPDDR3_TQH_CYC + tQH + 0.38 + + + MEM_LPDDR3_TDQSCKDL + tDQSCKDL + 614 + + + MEM_LPDDR3_TDQSS_CYC + tDQSS (max) + 1.25 + + + MEM_LPDDR3_TQSH_CYC + tQSH + 0.38 + + + MEM_LPDDR3_TDSH_CYC + tDSH + 0.2 + + + MEM_LPDDR3_TWLS_PS + tWLS + 175.0 + + + MEM_LPDDR3_TWLH_PS + tWLH + 175.0 + + + MEM_LPDDR3_TDSS_CYC + tDSS + 0.2 + + + MEM_LPDDR3_TINIT_US + tINIT + 500 + + + MEM_LPDDR3_TMRR_CK_CYC + tMRR + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + tMRW + 10 + + + MEM_LPDDR3_TRAS_NS + tRAS + 42.5 + + + MEM_LPDDR3_TRCD_NS + tRCD + 18.0 + + + MEM_LPDDR3_TRP_NS + tRPpb + 18.0 + + + MEM_LPDDR3_TREFI_US + tREFI + 3.9 + + + MEM_LPDDR3_TRFC_NS + tRFCab + 210.0 + + + MEM_LPDDR3_TWR_NS + tWR + 15.0 + + + MEM_LPDDR3_TWTR_CYC + tWTR + 6 + + + MEM_LPDDR3_TFAW_NS + tFAW + 50.0 + + + MEM_LPDDR3_TRRD_CYC + tRRD + 8 + + + MEM_LPDDR3_TRTP_CYC + tRTP + 6 + + + MEM_DDRT_FORMAT_ENUM + Memory format + MEM_FORMAT_LRDIMM + + + MEM_DDRT_DQ_WIDTH + DQ width + 72 + + + MEM_DDRT_DQ_PER_DQS + DQ pins per DQS group + 4 + + + MEM_DDRT_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDRT_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDRT_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDRT_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDRT_ROW_ADDR_WIDTH + Row address width + 18 + + + MEM_DDRT_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDRT_BANK_ADDR_WIDTH + Bank address width + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + Bank group width + 2 + + + MEM_DDRT_DM_EN + Data mask + false + + + MEM_DDRT_ALERT_PAR_EN + Enable ALERT#/PAR pins + true + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDRT_ALERT_N_AC_LANE + Address/command I/O lane of ALERT# + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + Pin index of ALERT# + 0 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + Hide advanced latency settings + true + + + MEM_DDRT_PWR_MODE + DIMM Power Mode + DDRT_PWR_MODE_12W + + + MEM_DDRT_BL_ENUM + Burst Length + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + Read Burst Type + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_TCL + Memory CAS latency setting + 15 + + + MEM_DDRT_RTT_NOM_ENUM + ODT Rtt nominal value + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDRT_ATCL_ENUM + Memory additive CAS latency setting + DDRT_ATCL_DISABLED + + + MEM_DDRT_DRV_STR_ENUM + Output drive strength setting + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ASR_ENUM + Auto self-refresh method + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_WTCL + Memory write CAS latency setting + 18 + + + MEM_DDRT_WRITE_CRC + Write CRC enable + false + + + MEM_DDRT_GEARDOWN + DDRT geardown mode + DDRT_GEARDOWN_HR + + + MEM_DDRT_PER_DRAM_ADDR + Per-DRAM addressability + false + + + MEM_DDRT_TEMP_SENSOR_READOUT + Temperature sensor readout + false + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + Fine granularity refresh + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_MPR_READ_FORMAT + MPR read format + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MAX_POWERDOWN + Maximum power down mode + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + Temperature controlled refresh range + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + Temperature controlled refresh enable + false + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + Internal VrefDQ monitor + false + + + MEM_DDRT_CAL_MODE + CS to Addr/CMD Latency + 0 + + + MEM_DDRT_SELF_RFSH_ABORT + Self refresh abort + false + + + MEM_DDRT_READ_PREAMBLE_TRAINING + Read preamble training mode enable + false + + + MEM_DDRT_DEFAULT_PREAMBLE + Use recommended preamble settings + true + + + MEM_DDRT_USER_READ_PREAMBLE + Read preamble + 1 + + + MEM_DDRT_USER_WRITE_PREAMBLE + Write preamble + 1 + + + MEM_DDRT_AC_PARITY_LATENCY + Addr/CMD parity latency + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_ODT_IN_POWERDOWN + ODT input buffer during powerdown mode + true + + + MEM_DDRT_RTT_PARK + CTT PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_AC_PERSISTENT_ERROR + Addr/CMD persistent error + false + + + MEM_DDRT_WRITE_DBI + Write DBI + false + + + MEM_DDRT_READ_DBI + Read DBI + false + + + MEM_DDRT_PARTIAL_WRITES + Partial Writes + false + + + MEM_DDRT_DEFAULT_VREFOUT + Use recommended initial VrefDQ value + true + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + VrefDQ training value + 56.0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + VrefDQ training range + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + Use recommended additional latency settings + true + + + MEM_DDRT_USER_TCL_ADDED + Additional CAS latency at PHY + 0 + + + MEM_DDRT_USER_WTCL_ADDED + Additional write CAS latency at PHY + 6 + + + MEM_DDRT_RCD_CA_IBT_ENUM + RCD CA Input Bus Termination + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CS_IBT_ENUM + RCD DCS[3:0]_n Input Bus Termination + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + RCD DCKE Input Bus Termination + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + RCD DODT Input Bus Termination + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DB Host Interface DQ RTT_NOM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DB Host Interface DQ RTT_WR + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DB_RTT_PARK_ENUM + DB Host Interface DQ RTT_PARK + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_DQ_DRV_ENUM + DB Host Interface DQ Driver + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + SPD Byte 137 - RCD Drive Strength for Command/Address + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + SPD Byte 138 - RCD Drive Strength for CK + 5 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + SPD Byte 140 - DRAM VrefDQ for Package Rank 0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + SPD Byte 141 - DRAM VrefDQ for Package Rank 1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + SPD Byte 142 - DRAM VrefDQ for Package Rank 2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + SPD Byte 143 - DRAM VrefDQ for Package Rank 3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + SPD Byte 144 - DB VrefDQ for DRAM Interface + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + SPD Byte 145-147 - DB MDQ Drive Strength and RTT + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + SPD Byte 148 - DRAM Drive Strength + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + SPD Byte 152-154 - DRAM ODT (RTT_PARK) + 39 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + RCD and DB Manufacturer (LSB) + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + RCD and DB Manufacturer (MSB) + 0 + + + MEM_DDRT_SPD_135_RCD_REV + RCD Revision Number + 0 + + + MEM_DDRT_SPD_139_DB_REV + DB Revision Number + 0 + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + PARAM_MEM_DDRT_LRDIMM_ODT_LESS_BS_NAME + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + PARAM_MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM_NAME + 240 + + + MEM_DDRT_I2C_DIMM_0_SA + I2C SA Value for DIMM 0 + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + I2C SA Value for DIMM 1 + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + I2C SA Value for DIMM 2 + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + I2C SA Value for DIMM 3 + 3 + + + MEM_DDRT_PERSISTENT_MODE + Persistent Mode + 1 + + + MEM_DDRT_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDRT_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDRT_R_ODT0_1X1 + ODT0 + off + + + MEM_DDRT_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDRT_W_ODT0_1X1 + ODT0 + on + + + MEM_DDRT_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDRT_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDRT_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDRT_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDRT_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDRT_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDRT_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDRT_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDRT_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDRT_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDRT_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDRT_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDRT_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDRT_SPEEDBIN_ENUM + Speed bin + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TIS_PS + tIS (base) + 60 + + + MEM_DDRT_TIS_AC_MV + tIS (base) AC level + 100 + + + MEM_DDRT_TIH_PS + tIH (base) + 95 + + + MEM_DDRT_TIH_DC_MV + tIH (base) DC level + 75 + + + MEM_DDRT_TDIVW_TOTAL_UI + TdiVW_total + 0.2 + + + MEM_DDRT_VDIVW_TOTAL + VdiVW_total + 136 + + + MEM_DDRT_TDQSQ_UI + tDQSQ + 0.16 + + + MEM_DDRT_TQH_UI + tQH + 0.76 + + + MEM_DDRT_TDVWP_UI + tDVWp + 0.72 + + + MEM_DDRT_TDQSCK_PS + tDQSCK + 165 + + + MEM_DDRT_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDRT_TQSH_CYC + tQSH + 0.38 + + + MEM_DDRT_TDSH_CYC + tDSH + 0.18 + + + MEM_DDRT_TDSS_CYC + tDSS + 0.18 + + + MEM_DDRT_TWLS_CYC + tWLS + 0.13 + + + MEM_DDRT_TWLH_CYC + tWLH + 0.13 + + + MEM_DDRT_TINIT_US + tINIT + 500 + + + MEM_DDRT_TMRD_CK_CYC + tMRD + 8 + + + MEM_DDRT_TRAS_NS + tRAS + 32.0 + + + MEM_DDRT_TRCD_NS + tRCD + 15.0 + + + MEM_DDRT_TRP_NS + tRP + 15.0 + + + MEM_DDRT_TREFI_US + tREFI + 7.8 + + + MEM_DDRT_TRFC_NS + tRFC + 260.0 + + + MEM_DDRT_TWR_NS + tWR + 15.0 + + + MEM_DDRT_TWTR_L_CYC + tWTR_L + 9 + + + MEM_DDRT_TWTR_S_CYC + tWTR_S + 3 + + + MEM_DDRT_TFAW_NS + tFAW + 21.0 + + + MEM_DDRT_TRRD_L_CYC + tRRD_L + 6 + + + MEM_DDRT_TRRD_S_CYC + tRRD_S + 4 + + + MEM_DDRT_TCCD_L_CYC + tCCD_L + 6 + + + MEM_DDRT_TCCD_S_CYC + tCCD_S + 4 + + + MEM_DDRT_TRFC_DLR_NS + tRFC_dlr + 90.0 + + + MEM_DDRT_TFAW_DLR_CYC + tFAW_dlr + 16 + + + MEM_DDRT_TRRD_DLR_CYC + tRRD_dlr + 4 + + + MEM_DDRT_TDIVW_DJ_CYC + PARAM_MEM_DDRT_TDIVW_DJ_CYC_NAME + 0.1 + + + MEM_DDRT_TDQSQ_PS + PARAM_MEM_DDRT_TDQSQ_PS_NAME + 66 + + + MEM_DDRT_TQH_CYC + PARAM_MEM_DDRT_TQH_CYC_NAME + 0.38 + + + MEM_DDRT_CFG_GEN_SBE + PARAM_MEM_DDRT_CFG_GEN_SBE_NAME + false + + + MEM_DDRT_CFG_GEN_DBE + PARAM_MEM_DDRT_CFG_GEN_DBE_NAME + false + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + PARAM_MEM_DDRT_LRDIMM_VREFDQ_VALUE_NAME + + + + MEM_DDRT_TWLS_PS + PARAM_MEM_DDRT_TWLS_PS_NAME + 0.0 + + + MEM_DDRT_TWLH_PS + PARAM_MEM_DDRT_TWLH_PS_NAME + 0.0 + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDR3_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 5.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + Read DQ slew rate + 2.5 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDR3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + false + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDR3_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDR4_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 8.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + Read DQ slew rate + 4.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDR4_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + true + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + false + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDR4_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_QDR2_USER_K_SLEW_RATE + K/K# slew rate (Differential) + 4.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + CQ/CQ# slew rate (Complementary) + 4.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + Read Q slew rate + 2.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + Write D slew rate + 2.0 + + + BOARD_QDR2_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + CQ/CQ# ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + K/K# ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + Read Q ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + Write D ISI/crosstalk + 0.0 + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + Package deskewed with board layout (Q group) + false + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + Package deskewed with board layout (D group) + false + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + Maximum board skew within Q group + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + Maximum board skew within D group + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + Maximum system skew within Q group + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + Maximum system skew within D group + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + Average delay difference between address/command and K + 0.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + Maximum K delay to device + 0.6 + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_QDR4_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + QK/QK# slew rate (Differential) + 5.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + DK/DK# slew rate (Differential) + 4.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + Read DQ slew rate + 2.5 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_QDR4_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + QK/QK# ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_WCLK_ISI_NS + DK/DK# ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + Package deskewed with board layout (QK group) + true + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + Maximum board skew within QK group + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + Maximum system skew within QK group + 0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + Average delay difference between DK and CK + -0.02 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + Maximum skew between DK groups + 0.02 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_QDR4_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + Maximum DK delay to device + 0.6 + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_RLD3_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + QK/QK# slew rate (Differential) + 7.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + DK/DK# slew rate (Differential) + 4.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + Read DQ slew rate + 3.5 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_RLD3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + QK/QK# ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_WCLK_ISI_NS + DK/DK# ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + Package deskewed with board layout (QK group) + false + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + Maximum board skew within QK group + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + Maximum system skew within QK group + 0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + Average delay difference between DK and CK + -0.02 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + Maximum skew between DK groups + 0.02 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_RLD3_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + Maximum DK delay to device + 0.6 + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + PARAM_BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES_NAME + true + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_CK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_AC_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_RCLK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_WCLK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_RDATA_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_WDATA_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + false + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + Maximum DQS delay to device + 0.6 + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDRT_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 8.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + Read DQ slew rate + 4.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDRT_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + true + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + false + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDRT_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDR3_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDR3_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + Address Ordering + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + true + + + CTRL_DDR3_ECC_STATUS_EN + Export error-correction code (ECC) status ports + false + + + CTRL_DDR3_REORDER_EN + Enable Reordering + true + + + CTRL_DDR3_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDR3_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDR4_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDR4_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDR4_ADDR_ORDER_ENUM + Address Ordering + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_ECC_EN + Enable Error Detection and Correction Logic with ECC + true + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDR4_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + false + + + CTRL_DDR4_ECC_STATUS_EN + Export error-correction code (ECC) status ports + false + + + CTRL_DDR4_REORDER_EN + Enable Reordering + true + + + CTRL_DDR4_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDR4_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDR4_MAJOR_MODE_EN + Enable controller major mode + false + + + CTRL_DDR4_POST_REFRESH_EN + Enable controller post-pay refresh + true + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + Post-pay refresh lower limit + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + Post-pay refresh upper limit + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + Enable controller pre-pay refresh + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + Refresh pre-pay upper limit + 1 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + Maximum Avalon-MM burst length + 4 + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + Generate power-of-2 data bus widths for Qsys + false + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + Maximum Avalon-MM burst length + 4 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + Generate power-of-2 data bus widths for Qsys + false + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + Additional read-after-write turnaround time + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + Additional write-after-read turnaround time + 0 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + PARAM_CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC_NAME + 4 + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + Address Ordering + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_LPDDR3_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_LPDDR3_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + Address Ordering + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_REORDER_EN + Enable Reordering + true + + + CTRL_LPDDR3_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_LPDDR3_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDRT_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDRT_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDRT_ADDR_ORDER_ENUM + PARAM_CTRL_DDRT_ADDR_ORDER_ENUM_NAME + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + true + + + CTRL_DDRT_ECC_STATUS_EN + Export error-correction code (ECC) status ports + true + + + CTRL_DDRT_REORDER_EN + Enable Reordering + true + + + CTRL_DDRT_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDRT_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_DIMM_DENSITY + Capacity of Optane DIMM + 128 + + + CTRL_DDRT_NUM_OF_AXIS_ID + Number of AXI masters + 1 + + + CTRL_DDRT_WR_ACK_POLICY + Write Acknowldgement Policy + POSTED + + + CTRL_DDRT_ERR_REPLAY_EN + Replay on Error + false + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + Host Error Viral + false + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + DIMM Error Viral + false + + + CTRL_DDRT_POISON_DETECTION_EN + Error Poison + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + PMM ADR Flow + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + PMM WPQ Flush + false + + + CTRL_DDRT_UPI_EN + UPI EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + PARAM_CTRL_DDRT_UPI_ID_WIDTH_NAME + 8 + + + CTRL_DDRT_PARITY_CMD_EN + CMD Parity EN + false + + + CTRL_DDRT_ADDR_INTERLEAVING + Address Interleaving + COARSE + + + CTRL_DDRT_PORT_AFI_C_WIDTH + PARAM_CTRL_DDRT_PORT_AFI_C_WIDTH_NAME + 2 + + + CTRL_DDRT_ZQ_INTERVAL_MS + ZQCS command interval + 3 + + + CTRL_DDRT_ERR_INJECT_EN + Error Inject EN + false + + + CTRL_DDRT_EXT_ERR_INJECT_EN + Ext Error Inject EN + false + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + Additional grant to write turnaround time (same DIMM) + 1 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + Additional write to grant turnaround time (same DIMM) + 0 + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + Additional grant to grant turnaround time (different DIMM) + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional grant to write turnaround time (different DIMM) + 1 + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + Additional write to grant turnaround time (different DIMM) + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write to write turnaround time (different DIMM) + 0 + + + DIAG_SIM_REGTEST_MODE + Simulation regtest mode + false + + + DIAG_TIMING_REGTEST_MODE + Timing regtest mode + false + + + DIAG_SYNTH_FOR_SIM + Synthesize for simulation + false + + + DIAG_FAST_SIM_OVERRIDE + Fast simulation override + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_SEQ_RESET_AUTO_RELEASE + PARAM_DIAG_SEQ_RESET_AUTO_RELEASE_NAME + avl + + + DIAG_DB_RESET_AUTO_RELEASE + PARAM_DIAG_DB_RESET_AUTO_RELEASE_NAME + avl_release + + + DIAG_ADD_READY_PIPELINE + Add additional pipeline on the ready/WaitRequest path. + true + + + DIAG_EXPOSE_EARLY_READY + Expose Early Ready + false + + + DIAG_EXPOSE_RD_TYPE + Expose Read Type + false + + + DIAG_VERBOSE_IOAUX + Show verbose IOAUX debug messages + false + + + DIAG_ECLIPSE_DEBUG + Enable Eclipse debugging + false + + + DIAG_EXPORT_VJI + Export Virtual JTAG Interface (VJI) + false + + + DIAG_ENABLE_JTAG_UART + Enable JTAG UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + Enable JTAG UART hexfiles + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + Enable UART for HPS EMIF Debug + false + + + DIAG_SOFT_NIOS_MODE + Use Soft NIOS Processor for On-Chip Debug + SOFT_NIOS_MODE_DISABLED + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + Calibration Processor External Clock Frequency + 100 + + + DIAG_USE_RS232_UART + Use an RS232 UART for Soft NIOS Calibration Processor debug output (requires code change) + false + + + DIAG_RS232_UART_BAUDRATE + RS232 UART Speed + 57600 + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + Add extra EMIFs to example design + + + + DIAG_EX_DESIGN_SEPARATE_RESETS + Use a separate global reset signal for every interface + false + + + DIAG_EXPOSE_DFT_SIGNALS + Expose test and debug signals + false + + + DIAG_EXTRA_CONFIGS + Extra configuration + + + + DIAG_USE_BOARD_DELAY_MODEL + Use board delay model during simulation + false + + + DIAG_BOARD_DELAY_CONFIG_STR + Board delay model configuration + + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + Number of Traffic Generator 2.0 configuration interfaces + 0 + + + DIAG_EXPORT_PLL_REF_CLK_OUT + PARAM_DIAG_EXPORT_PLL_REF_CLK_OUT_NAME + false + + + DIAG_EXPORT_PLL_LOCKED + Export PLL lock signal + true + + + DIAG_HMC_HRC + PARAM_DIAG_HMC_HRC_NAME + auto + + + SHORT_QSYS_INTERFACE_NAMES + Use short Qsys interface names + true + + + DIAG_EXT_DOCS + PARAM_DIAG_EXT_DOCS_NAME + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_DDR3_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDR3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDR3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_DDR3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDR3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDR3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDR3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDR3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDR3_CA_LEVEL_EN + Enable address/command leveling calibration + true + + + DIAG_DDR3_CA_DESKEW_EN + Enable address/command deskew calibration + true + + + DIAG_DDR3_CAL_ADDR0 + Calibration address 0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + Calibration address 1 + 8 + + + DIAG_DDR3_CAL_ENABLE_NON_DES + Enable refreshes during calibration + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + Enable automatic calibration after reset + true + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + Enable Micron Automata Calibration + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_DDR4_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDR4_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDR4_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_DDR4_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDR4_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDR4_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR4_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDR4_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDR4_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDR4_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_DDR4_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDR4_SKIP_VREF_CAL + Skip VREF calibration + false + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + Skip address/command parity check during calibration + false + + + DIAG_DDR4_CAL_ADDR0 + Calibration address 0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + Calibration address 1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + Enable refreshes during calibration + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + Enable automatic calibration after reset + true + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_QDR2_INTERFACE_ID + Interface ID + 0 + + + DIAG_QDR2_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_QDR2_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_QDR2_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_QDR2_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_QDR2_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR2_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_QDR2_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_QDR2_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_QDR4_INTERFACE_ID + Interface ID + 0 + + + DIAG_QDR4_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_QDR4_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_QDR4_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_QDR4_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_QDR4_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR4_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_QDR4_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_QDR4_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_QDR4_SKIP_VREF_CAL + Skip VREF_in calibration + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_RLD2_INTERFACE_ID + Interface ID + 0 + + + DIAG_RLD2_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_RLD2_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_RLD2_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_RLD2_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_RLD2_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD2_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_RLD2_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_RLD2_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_RLD3_INTERFACE_ID + Interface ID + 0 + + + DIAG_RLD3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_RLD3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_RLD3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_RLD3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_RLD3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_RLD3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_RLD3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_RLD3_CA_LEVEL_EN + Enable address/command leveling calibration + true + + + DIAG_RLD3_CA_DESKEW_EN + Enable address/command deskew calibration + true + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_LPDDR3_INTERFACE_ID + Interface ID + 0 + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_LPDDR3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_LPDDR3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_LPDDR3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_LPDDR3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_LPDDR3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_LPDDR3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_LPDDR3_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_LPDDR3_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + true + + + DIAG_DDRT_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDRT_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDRT_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + true + + + DIAG_DDRT_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDRT_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDRT_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDRT_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDRT_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDRT_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_DDRT_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDRT_SKIP_VREF_CAL + Skip VREF calibration + false + + + DIAG_DDRT_CAL_ADDR0 + PARAM_DIAG_DDRT_CAL_ADDR0_NAME + 0 + + + DIAG_DDRT_CAL_ADDR1 + PARAM_DIAG_DDRT_CAL_ADDR1_NAME + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + PARAM_DIAG_DDRT_CAL_ENABLE_NON_DES_NAME + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + PARAM_DIAG_DDRT_CAL_FULL_CAL_ON_RESET_NAME + true + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + Enable enhanced testing + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + Enable driver margining for DDR-T + false + + + DIAG_DDRT_EFF_TEST + PARAM_DIAG_DDRT_EFF_TEST_NAME + false + + + NUM_IPS + Number of IPs + 1 + + + EMIF_0_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_0_STORED_PARAM + PARAM_EMIF_0_STORED_PARAM_NAME + + + + EMIF_0_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_1_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_1_STORED_PARAM + PARAM_EMIF_1_STORED_PARAM_NAME + + + + EMIF_1_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_2_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_2_STORED_PARAM + PARAM_EMIF_2_STORED_PARAM_NAME + + + + EMIF_2_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_3_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_3_STORED_PARAM + PARAM_EMIF_3_STORED_PARAM_NAME + + + + EMIF_3_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_4_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_4_STORED_PARAM + PARAM_EMIF_4_STORED_PARAM_NAME + + + + EMIF_4_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_5_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_5_STORED_PARAM + PARAM_EMIF_5_STORED_PARAM_NAME + + + + EMIF_5_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_6_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_6_STORED_PARAM + PARAM_EMIF_6_STORED_PARAM_NAME + + + + EMIF_6_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_7_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_7_STORED_PARAM + PARAM_EMIF_7_STORED_PARAM_NAME + + + + EMIF_7_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_8_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_8_STORED_PARAM + PARAM_EMIF_8_STORED_PARAM_NAME + + + + EMIF_8_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_9_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_9_STORED_PARAM + PARAM_EMIF_9_STORED_PARAM_NAME + + + + EMIF_9_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_10_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_10_STORED_PARAM + PARAM_EMIF_10_STORED_PARAM_NAME + + + + EMIF_10_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_11_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_11_STORED_PARAM + PARAM_EMIF_11_STORED_PARAM_NAME + + + + EMIF_11_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_12_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_12_STORED_PARAM + PARAM_EMIF_12_STORED_PARAM_NAME + + + + EMIF_12_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_13_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_13_STORED_PARAM + PARAM_EMIF_13_STORED_PARAM_NAME + + + + EMIF_13_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_14_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_14_STORED_PARAM + PARAM_EMIF_14_STORED_PARAM_NAME + + + + EMIF_14_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_15_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_15_STORED_PARAM + PARAM_EMIF_15_STORED_PARAM_NAME + + + + EMIF_15_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDR3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDR4_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_QDR2_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_QDR4_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_RLD2_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_RLD3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDRT_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + AUTO_BOARD + Auto BOARD + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + + + + + + + board + Board + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + + + device + Device + AGFB014R24B2E2V + + + deviceFamily + Device family + Agilex 7 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element emif_fm_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>local_reset_req</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_req</name> + <role>local_reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>local_reset_status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_done</name> + <role>local_reset_done</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_ref_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_ref_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_locked</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_locked</name> + <role>pll_locked</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>oct</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>oct_rzqin</name> + <role>oct_rzqin</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>mem_ck</name> + <role>mem_ck</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ck_n</name> + <role>mem_ck_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_a</name> + <role>mem_a</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_act_n</name> + <role>mem_act_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_ba</name> + <role>mem_ba</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_bg</name> + <role>mem_bg</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cke</name> + <role>mem_cke</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_cs_n</name> + <role>mem_cs_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_odt</name> + <role>mem_odt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_reset_n</name> + <role>mem_reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_par</name> + <role>mem_par</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_alert_n</name> + <role>mem_alert_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs</name> + <role>mem_dqs</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dqs_n</name> + <role>mem_dqs_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dq</name> + <role>mem_dq</role> + <direction>Bidir</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_dbi_n</name> + <role>mem_dbi_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_cal_success</name> + <role>local_cal_success</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>local_cal_fail</name> + <role>local_cal_fail</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_calbus</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>calbus_read</name> + <role>calbus_read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_write</name> + <role>calbus_write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_address</name> + <role>calbus_address</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_wdata</name> + <role>calbus_wdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_rdata</name> + <role>calbus_rdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_seq_param_tbl</name> + <role>calbus_seq_param_tbl</role> + <direction>Output</direction> + <width>4096</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>emif_calbus_clk</value> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_calbus_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>calbus_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_reset_n</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>300000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_ecc_user_interrupt_0</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>ctrl_ecc_user_interrupt_0</name> + <role>ctrl_ecc_user_interrupt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>ctrl_amm_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>amm_ready_0</name> + <role>waitrequest_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_read_0</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_write_0</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_address_0</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdata_0</name> + <role>readdata</role> + <direction>Output</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_writedata_0</name> + <role>writedata</role> + <direction>Input</direction> + <width>512</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_burstcount_0</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_byteenable_0</name> + <role>byteenable</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>amm_readdatavalid_0</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8589934592</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>emif_usr_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>emif_usr_reset_n</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureGuid</key> + <value>0</value> + </entry> + <entry> + <key>dfhGroupId</key> + <value>0</value> + </entry> + <entry> + <key>dfhParameterId</key> + </entry> + <entry> + <key>dfhParameterName</key> + </entry> + <entry> + <key>dfhParameterVersion</key> + </entry> + <entry> + <key>dfhParameterData</key> + </entry> + <entry> + <key>dfhParameterDataLength</key> + </entry> + <entry> + <key>dfhFeatureMajorVersion</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureMinorVersion</key> + <value>0</value> + </entry> + <entry> + <key>dfhFeatureId</key> + <value>35</value> + </entry> + <entry> + <key>dfhFeatureType</key> + <value>3</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>ctrl_amm_0</key> + <value> + <connectionPointName>ctrl_amm_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_0' start='0x0' end='0x200000000' datawidth='512' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>33</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>512</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>emif_usr_clk</key> + <value> + <connectionPointName>emif_usr_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>300000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + <cpuInfoDefinition> + <version>1</version> + <cpuGroups/> + <exportedModules> + <entry> + <key>ecc_core</key> + <value> + <moduleInfo> + <name>ecc_core</name> + <kind>altera_emif_ecc</kind> + <version>19.1</version> + <path>ecc_core</path> + <assignments/> + <irqReceiverNames/> + <masterNames/> + </moduleInfo> + <slaveInterfaceInfos> + <slaveInterfaceInfo> + <interfaceName>ctrl_amm_0</interfaceName> + <connectedInterfaceName>ctrl_amm_0</connectedInterfaceName> + <baseAddress>0</baseAddress> + <span>8589934592</span> + <addressGroup>0</addressGroup> + <isBigEndian>false</isBigEndian> + <assignments> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignments> + </slaveInterfaceInfo> + </slaveInterfaceInfos> + </value> + </entry> + </exportedModules> + <systemInformation> + <name>emif_fm_0</name> + <deviceFamily>Agilex 7</deviceFamily> + <generateLegacySim>false</generateLegacySim> + </systemInformation> +</cpuInfoDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressAndMemoryMap + addressAndMemoryMap + 1.0 + + + ecc_core.ctrl_amm_0 + + + + + + + + + false + false + + \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_afi_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_afi_if.sv new file mode 100644 index 0000000000..562208ebda --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_afi_if.sv @@ -0,0 +1,1048 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the AFI interface through which +// a soft controller interacts with the memory interface PHY inside the tile. +// +/////////////////////////////////////////////////////////////////////////////// + + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _get_lane_usage(_tile_i, _lane_i) ( LANES_USAGE[(_tile_i * LANES_PER_TILE + _lane_i) * 3 +: 3] ) + +// are core-driven OEs required for any lane in {(DQ_ON,X), (DQ_ON,X), (DQ_ON,X), (DQ_ON,X) } +`define _use_dq_lane_oe(_tile_i, _oe_req) ( _oe_req[_tile_i][1] | _oe_req[_tile_i][3] | _oe_req[_tile_i][5] | _oe_req[_tile_i][7] ) +// are AC tie-offs required for any lane {(X, TIE_OFF), (X, TIE_OFF), (X, TIE_OFF), (X, TIE_OFF) } +`define _use_ac_lane_oe(_tile_i, _oe_req) ( _oe_req[_tile_i][0] | _oe_req[_tile_i][2] | _oe_req[_tile_i][4] | _oe_req[_tile_i][6] ) + +`define _get_db_pin_proc_mode(_pin_i) ( DB_PINS_PROC_MODE[_pin_i * 5 +: 5] ) + +`define _core2l_afi(_loc, _port_i, _phase_i) core2l_data\ + [`_get_tile(_loc, _port_i)]\ + [`_get_lane(_loc, _port_i)]\ + [(`_get_pin(_loc, _port_i) * 8) + _phase_i] + +`define _l2core_afi(_loc, _port_i, _phase_i) l2core_data\ + [`_get_tile(_loc, _port_i)]\ + [`_get_lane(_loc, _port_i)]\ + [(`_get_pin(_loc, _port_i) * 8) + _phase_i] + +`define _unused_core2l_afi(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +// +`define _connect_out(_loc, _mem_port_width, _afi_port_width, _afi_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : oport \ + for (phase_i = 0; phase_i < 8; ++phase_i) begin : data_phase \ + if (phase_i < _afi_port_width / _mem_port_width) begin \ + assign `_core2l_afi(_loc, port_i, phase_i) = _afi_port[_mem_port_width * phase_i + port_i]; \ + end else begin \ + assign `_core2l_afi(_loc, port_i, phase_i) = 1'b0; \ + end \ + end \ + end + +`define _connect_out_with_regs(_loc, _mem_port_width, _afi_port_width, _afi_port) \ + logic [_afi_port_width-1:0] sr_o; \ + altera_emif_arch_fm_regs # ( \ + .REGISTER (REGISTER_AFI_C2P), \ + .WIDTH (_afi_port_width) \ + ) afi_regs_o ( \ + .clk (afi_clk), \ + .reset_n (1'b1), \ + .data_in (_afi_port), \ + .data_out (sr_o) \ + ); \ + `_connect_out(_loc, _mem_port_width, _afi_port_width, sr_o) + +`define _connect_in(_loc, _mem_port_width, _afi_port_width, _afi_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : iport \ + for (phase_i = 0; phase_i < _afi_port_width / _mem_port_width; ++phase_i) begin : data_phase \ + assign _afi_port[_mem_port_width * phase_i + port_i] = `_l2core_afi(_loc, port_i, phase_i); \ + end \ + end + +`define _connect_in_with_regs(_loc, _mem_port_width, _afi_port_width, _afi_port) \ + logic [_afi_port_width-1:0] sr_i; \ + `_connect_in(_loc, _mem_port_width, _afi_port_width, sr_i) \ + altera_emif_arch_fm_regs # ( \ + .REGISTER (REGISTER_AFI_P2C), \ + .WIDTH (_afi_port_width) \ + ) afi_regs_i ( \ + .clk (afi_clk), \ + .reset_n (1'b1), \ + .data_in (sr_i), \ + .data_out (_afi_port) \ + ); + +module altera_emif_arch_fm_afi_if #( + + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + parameter REGISTER_AFI_C2P = 0, + parameter REGISTER_AFI_P2C = 0, + parameter PORT_AFI_ADDR_WIDTH = 1, + parameter PORT_AFI_BA_WIDTH = 1, + parameter PORT_AFI_BG_WIDTH = 1, + parameter PORT_AFI_C_WIDTH = 1, + parameter PORT_AFI_CKE_WIDTH = 1, + parameter PORT_AFI_CS_N_WIDTH = 1, + parameter PORT_AFI_RM_WIDTH = 1, + parameter PORT_AFI_ODT_WIDTH = 1, + parameter PORT_AFI_GNT_N_WIDTH = 1, + parameter PORT_AFI_REQ_N_WIDTH = 1, + parameter PORT_AFI_ERR_N_WIDTH = 1, + parameter PORT_AFI_RAS_N_WIDTH = 1, + parameter PORT_AFI_CAS_N_WIDTH = 1, + parameter PORT_AFI_WE_N_WIDTH = 1, + parameter PORT_AFI_RST_N_WIDTH = 1, + parameter PORT_AFI_ACT_N_WIDTH = 1, + parameter PORT_AFI_PAR_WIDTH = 1, + parameter PORT_AFI_CA_WIDTH = 1, + parameter PORT_AFI_REF_N_WIDTH = 1, + parameter PORT_AFI_WPS_N_WIDTH = 1, + parameter PORT_AFI_RPS_N_WIDTH = 1, + parameter PORT_AFI_DOFF_N_WIDTH = 1, + parameter PORT_AFI_LD_N_WIDTH = 1, + parameter PORT_AFI_RW_N_WIDTH = 1, + parameter PORT_AFI_LBK0_N_WIDTH = 1, + parameter PORT_AFI_LBK1_N_WIDTH = 1, + parameter PORT_AFI_CFG_N_WIDTH = 1, + parameter PORT_AFI_AP_WIDTH = 1, + parameter PORT_AFI_AINV_WIDTH = 1, + parameter PORT_AFI_DM_WIDTH = 1, + parameter PORT_AFI_DM_N_WIDTH = 1, + parameter PORT_AFI_BWS_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DINV_WIDTH = 1, + parameter PORT_AFI_WDATA_DINV_WIDTH = 1, + parameter PORT_AFI_DQS_BURST_WIDTH = 1, + parameter PORT_AFI_WDATA_VALID_WIDTH = 1, + parameter PORT_AFI_WDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 1, + parameter PORT_AFI_RDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_VALID_WIDTH = 1, + parameter PORT_AFI_RRANK_WIDTH = 1, + parameter PORT_AFI_WRANK_WIDTH = 1, + parameter PORT_AFI_ALERT_N_WIDTH = 1, + parameter PORT_AFI_PE_N_WIDTH = 1, + + // Definition of port widths for "mem" interface (auto-generated) + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_GNT_N_WIDTH = 1, + parameter PORT_MEM_REQ_N_WIDTH = 1, + parameter PORT_MEM_ERR_N_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + parameter PORT_MEM_CK_PINLOC = 10'b0000000000, + parameter PORT_MEM_CK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_A_PINLOC = 10'b0000000000, + parameter PORT_MEM_BA_PINLOC = 10'b0000000000, + parameter PORT_MEM_BG_PINLOC = 10'b0000000000, + parameter PORT_MEM_C_PINLOC = 10'b0000000000, + parameter PORT_MEM_CKE_PINLOC = 10'b0000000000, + parameter PORT_MEM_CS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RM_PINLOC = 10'b0000000000, + parameter PORT_MEM_ODT_PINLOC = 10'b0000000000, + parameter PORT_MEM_RAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WE_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RESET_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ACT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PAR_PINLOC = 10'b0000000000, + parameter PORT_MEM_CA_PINLOC = 10'b0000000000, + parameter PORT_MEM_REF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DOFF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK0_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK1_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CFG_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_AP_PINLOC = 10'b0000000000, + parameter PORT_MEM_AINV_PINLOC = 10'b0000000000, + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVB_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ALERT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PE_N_PINLOC = 10'b0000000000, + + parameter DQS_BUS_MODE_ENUM = "", + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter LANES_USAGE = 1'b0, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0, + parameter DB_PINS_PROC_MODE = 1'b0, + + parameter MEM_DATA_MASK_EN = 1, + parameter PHY_HMC_CLK_RATIO = 1 + +) ( + input logic afi_clk, + input logic afi_reset_n, + + input logic [PORT_AFI_ADDR_WIDTH-1:0] afi_addr, + input logic [PORT_AFI_BA_WIDTH-1:0] afi_ba, + input logic [PORT_AFI_BG_WIDTH-1:0] afi_bg, + input logic [PORT_AFI_C_WIDTH-1:0] afi_c, + input logic [PORT_AFI_CKE_WIDTH-1:0] afi_cke, + input logic [PORT_AFI_CS_N_WIDTH-1:0] afi_cs_n, + input logic [PORT_AFI_RM_WIDTH-1:0] afi_rm, + input logic [PORT_AFI_ODT_WIDTH-1:0] afi_odt, + input logic [PORT_AFI_GNT_N_WIDTH-1:0] afi_gnt_n, + output logic [PORT_AFI_REQ_N_WIDTH-1:0] afi_req_n, + output logic [PORT_AFI_ERR_N_WIDTH-1:0] afi_err_n, + input logic [PORT_AFI_RAS_N_WIDTH-1:0] afi_ras_n, + input logic [PORT_AFI_CAS_N_WIDTH-1:0] afi_cas_n, + input logic [PORT_AFI_WE_N_WIDTH-1:0] afi_we_n, + input logic [PORT_AFI_RST_N_WIDTH-1:0] afi_rst_n, + input logic [PORT_AFI_ACT_N_WIDTH-1:0] afi_act_n, + input logic [PORT_AFI_PAR_WIDTH-1:0] afi_par, + input logic [PORT_AFI_CA_WIDTH-1:0] afi_ca, + input logic [PORT_AFI_REF_N_WIDTH-1:0] afi_ref_n, + input logic [PORT_AFI_WPS_N_WIDTH-1:0] afi_wps_n, + input logic [PORT_AFI_RPS_N_WIDTH-1:0] afi_rps_n, + input logic [PORT_AFI_DOFF_N_WIDTH-1:0] afi_doff_n, + input logic [PORT_AFI_LD_N_WIDTH-1:0] afi_ld_n, + input logic [PORT_AFI_RW_N_WIDTH-1:0] afi_rw_n, + input logic [PORT_AFI_LBK0_N_WIDTH-1:0] afi_lbk0_n, + input logic [PORT_AFI_LBK1_N_WIDTH-1:0] afi_lbk1_n, + input logic [PORT_AFI_CFG_N_WIDTH-1:0] afi_cfg_n, + input logic [PORT_AFI_AP_WIDTH-1:0] afi_ap, + input logic [PORT_AFI_AINV_WIDTH-1:0] afi_ainv, + input logic [PORT_AFI_DM_WIDTH-1:0] afi_dm, + input logic [PORT_AFI_DM_N_WIDTH-1:0] afi_dm_n, + input logic [PORT_AFI_BWS_N_WIDTH-1:0] afi_bws_n, + output logic [PORT_AFI_RDATA_DBI_N_WIDTH-1:0] afi_rdata_dbi_n, + input logic [PORT_AFI_WDATA_DBI_N_WIDTH-1:0] afi_wdata_dbi_n, + output logic [PORT_AFI_RDATA_DINV_WIDTH-1:0] afi_rdata_dinv, + input logic [PORT_AFI_WDATA_DINV_WIDTH-1:0] afi_wdata_dinv, + input logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst, + input logic [PORT_AFI_WDATA_VALID_WIDTH-1:0] afi_wdata_valid, + input logic [PORT_AFI_WDATA_WIDTH-1:0] afi_wdata, + input logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full, + output logic [PORT_AFI_RDATA_WIDTH-1:0] afi_rdata, + output logic [PORT_AFI_RDATA_VALID_WIDTH-1:0] afi_rdata_valid, + input logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank, + input logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank, + output logic [PORT_AFI_ALERT_N_WIDTH-1:0] afi_alert_n, + output logic [PORT_AFI_PE_N_WIDTH-1:0] afi_pe_n, + + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + + // These signals fans out to each lane in an IO48 tile + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_read, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_write, + input logic [3:0] l2core_rdata_valid_pri, + input logic [3:0] l2core_rdata_valid_sec +); + timeunit 1ns; + timeprecision 1ps; + + // Enum that defines whether a lane is used or not, and in what mode. + // This enum type is used to encode the LANES_USAGE_MODE parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + LANE_USAGE_UNUSED = 3'b000, + LANE_USAGE_AC_HMC = 3'b001, + LANE_USAGE_AC_CORE = 3'b010, + LANE_USAGE_RDATA = 3'b011, + LANE_USAGE_WDATA = 3'b100, + LANE_USAGE_WRDATA = 3'b101 + } LANE_USAGE; + + + typedef enum bit [1:0] { + LANE_OE_REQ_OFF = 2'b00, + LANE_OE_REQ_ON = 2'b01, + LANE_OE_REQ_DQ = 2'b10 + } LANE_OE_REQ; + + // Enum that defines the write data buffer procedural mode of an EMIF pin. + // This enum type is used to encode the DB_PINS_PROC_MODE parameter + // passed into the io_tiles module. + typedef enum bit [4:0] { + DB_PIN_PROC_MODE_AC_CORE = 5'b00000, + DB_PIN_PROC_MODE_WDB_AC = 5'b00001, + DB_PIN_PROC_MODE_WDB_DQ = 5'b00010, + DB_PIN_PROC_MODE_WDB_DM = 5'b00011, + DB_PIN_PROC_MODE_WDB_CLK = 5'b00100, + DB_PIN_PROC_MODE_WDB_CLKB = 5'b00101, + DB_PIN_PROC_MODE_WDB_DQS = 5'b00110, + DB_PIN_PROC_MODE_WDB_DQSB = 5'b00111, + DB_PIN_PROC_MODE_DQS = 5'b01000, + DB_PIN_PROC_MODE_DQSB = 5'b01001, + DB_PIN_PROC_MODE_DQ = 5'b01010, + DB_PIN_PROC_MODE_DM = 5'b01011, + DB_PIN_PROC_MODE_DBI = 5'b01100, + DB_PIN_PROC_MODE_CLK = 5'b01101, + DB_PIN_PROC_MODE_CLKB = 5'b01110, + DB_PIN_PROC_MODE_DQS_DDR4 = 5'b01111, + DB_PIN_PROC_MODE_DQSB_DDR4 = 5'b10000, + DB_PIN_PROC_MODE_RDQ = 5'b10001, + DB_PIN_PROC_MODE_RDQS = 5'b10010, + DB_PIN_PROC_MODE_GPIO = 5'b11111 + } DB_PIN_PROC_MODE; + + localparam SDR_RATIO = PHY_HMC_CLK_RATIO; + localparam DDR_RATIO = SDR_RATIO * 2; + + localparam NUM_OF_LOGICAL_RANKS = PORT_AFI_RRANK_WIDTH / SDR_RATIO; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE*2-1:0] tile_oe_req; + logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst_r; + logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank_r; + logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank_r; + logic [7:0] afi_rrank_r_padded; + logic [7:0] afi_wrank_r_padded; + + logic [NUM_OF_RTL_TILES-1:0][3:0] dq_lane_oe_data; + logic [3:0] dq_lane_oe_strobe; + + logic [NUM_OF_RTL_TILES-1:0][7:0] int_core2l_oe; + logic [NUM_OF_RTL_TILES-1:0][3:0] int_core2l_rdata_en_full; + logic [NUM_OF_RTL_TILES-1:0][7:0] int_core2l_mrnk_read; + logic [NUM_OF_RTL_TILES-1:0][7:0] int_core2l_mrnk_write; + + function automatic logic [1:0] onehot_2_bin (input [NUM_OF_LOGICAL_RANKS-1:0] in); + onehot_2_bin = 2'b00; + for (int i=0; i data-pin OE, int_core2l_oe[7:4] => DQS OE + if ( DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ) begin + assign core2l_oe[tile_i][lane_i] = {{4{int_core2l_oe[tile_i][3:0]}},{4{int_core2l_oe[tile_i][7:4]}},{4{int_core2l_oe[tile_i][3:0]}}}; + end else begin + assign core2l_oe[tile_i][lane_i] = {{6{int_core2l_oe[tile_i][3:0]}},{2{int_core2l_oe[tile_i][7:4]}},{4{int_core2l_oe[tile_i][3:0]}}}; + end + end + end + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (PORT_AFI_RRANK_WIDTH) + ) afi_rrank_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_rrank), + .data_out (afi_rrank_r) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (PORT_AFI_WRANK_WIDTH) + ) afi_wrank_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_wrank), + .data_out (afi_wrank_r) + ); + + // FM mrnk_(rd|wr) encoding has changed from one-hot to binary + for (t = 0; t < 4; ++t) begin: timeslot + if (t >= SDR_RATIO) begin + assign afi_rrank_r_padded[2*t+1:2*t] = 2'b00; + assign afi_wrank_r_padded[2*t+1:2*t] = 2'b00; + end else begin + assign afi_rrank_r_padded[2*t+1:2*t] = onehot_2_bin(afi_rrank_r[NUM_OF_LOGICAL_RANKS*(t+1)-1:NUM_OF_LOGICAL_RANKS*t]); + assign afi_wrank_r_padded[2*t+1:2*t] = onehot_2_bin(afi_wrank_r[NUM_OF_LOGICAL_RANKS*(t+1)-1:NUM_OF_LOGICAL_RANKS*t]); + end + end + + assign int_core2l_mrnk_read = {(NUM_OF_RTL_TILES){afi_rrank_r_padded}}; + assign int_core2l_mrnk_write = {(NUM_OF_RTL_TILES){afi_wrank_r_padded}}; + + //////////////////////////////////////////////////////////////////////////// + // Connection for read control signals afi_rdata_en_full and afi_rdata_valid + //////////////////////////////////////////////////////////////////////////// + + // Register and duplicate the afi_rdata_en_full signal for timing closure + logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full_r; + logic [PORT_AFI_WDATA_VALID_WIDTH-1:0] afi_wdata_valid_r; + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH) + ) afi_rdata_en_full_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_rdata_en_full), + .data_out (afi_rdata_en_full_r) + ); + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (PORT_AFI_WDATA_VALID_WIDTH) + ) afi_wdata_valid_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_wdata_valid), + .data_out (afi_wdata_valid_r) + ); + + // External memory has dual data ports (i.e. DQA and DQB, as in QDR-IV) + // Split afi_rdata_en_full based on which port the signal belongs to. + // This special code path relies on the location of QKA/QKB pins to identify + // the read lanes for each data port. + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : dual_port + logic [3:0] afi_rdata_en_full_r_padded_a, afi_rdata_en_full_r_padded_b; + + if (SDR_RATIO < 4) begin + assign afi_rdata_en_full_r_padded_a = {'0, afi_rdata_en_full_r[SDR_RATIO-1:0]}; + assign afi_rdata_en_full_r_padded_b = {'0, afi_rdata_en_full_r[PORT_AFI_RDATA_EN_FULL_WIDTH-1:SDR_RATIO]}; + end else begin + assign afi_rdata_en_full_r_padded_a = afi_rdata_en_full_r[SDR_RATIO-1:0]; + assign afi_rdata_en_full_r_padded_b = afi_rdata_en_full_r[PORT_AFI_RDATA_EN_FULL_WIDTH-1:SDR_RATIO]; + end + + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) begin : rdata_en_full + if (tile_i == (`_get_tile(PORT_MEM_QKA_PINLOC, 0)) ) begin + assign int_core2l_rdata_en_full[tile_i] = afi_rdata_en_full_r_padded_a; + end else if ( tile_i == (`_get_tile(PORT_MEM_QKB_PINLOC, 0))) begin + assign int_core2l_rdata_en_full[tile_i] = afi_rdata_en_full_r_padded_b; + end else begin + assign int_core2l_rdata_en_full[tile_i] = '0; + end + end + /* + // afi_rdata_en_full for port A + for (port_i = 0; port_i < PORT_MEM_QKA_WIDTH; ++port_i) begin : port_a + assign int_core2l_rdata_en_full[`_get_tile(PORT_MEM_QKA_PINLOC, port_i)] = afi_rdata_en_full_r_padded_a; + if (MEM_TTL_DATA_WIDTH / MEM_TTL_NUM_OF_READ_GROUPS == 18) begin + if (`_get_lane(PORT_MEM_QKA_PINLOC, port_i) % 2 == 0) begin + assign int_core2l_rdata_en_full[`_get_tile(PORT_MEM_QKA_PINLOC, port_i)] = afi_rdata_en_full_r_padded_a; + end else begin + assign int_core2l_rdata_en_full[`_get_tile(PORT_MEM_QKA_PINLOC, port_i)] = afi_rdata_en_full_r_padded_a; + end + end + end + + // afi_rdata_en_full for port B + for (port_i = 0; port_i < PORT_MEM_QKB_WIDTH; ++port_i) begin : port_b + assign int_core2l_rdata_en_full[`_get_tile(PORT_MEM_QKB_PINLOC, port_i)] = afi_rdata_en_full_r_padded_b; + if (MEM_TTL_DATA_WIDTH / MEM_TTL_NUM_OF_READ_GROUPS == 18) begin + if (`_get_lane(PORT_MEM_QKA_PINLOC, port_i) % 2 == 0) begin + assign int_core2l_rdata_en_full[`_get_tile(PORT_MEM_QKB_PINLOC, port_i)] = afi_rdata_en_full_r_padded_b; + end else begin + assign int_core2l_rdata_en_full[`_get_tile(PORT_MEM_QKB_PINLOC, port_i)] = afi_rdata_en_full_r_padded_b; + end + end + end + */ + + // Connection for afi_rdata_valid + logic [PORT_AFI_RDATA_VALID_WIDTH/2-1:0] afi_rdata_valid_a, afi_rdata_valid_b; + + assign afi_rdata_valid_a = l2core_rdata_valid_pri[PORT_AFI_RDATA_VALID_WIDTH/2-1:0]; + assign afi_rdata_valid_b = l2core_rdata_valid_sec[PORT_AFI_RDATA_VALID_WIDTH/2-1:0]; + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_P2C), + .WIDTH (PORT_AFI_RDATA_VALID_WIDTH) + ) afi_rdata_valid_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in ({afi_rdata_valid_b, afi_rdata_valid_a}), + .data_out (afi_rdata_valid) + ); + + end else begin : single_port + logic [3:0] afi_rdata_en_full_r_padded; + + assign afi_rdata_en_full_r_padded = (PORT_AFI_RDATA_EN_FULL_WIDTH < 4) ? {'0, afi_rdata_en_full_r} : afi_rdata_en_full_r; + assign int_core2l_rdata_en_full = {(NUM_OF_RTL_TILES){afi_rdata_en_full_r_padded}}; + + // Connection for afi_rdata_valid + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_P2C), + .WIDTH (PORT_AFI_RDATA_VALID_WIDTH) + ) afi_rdata_valid_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (l2core_rdata_valid_pri[PORT_AFI_RDATA_VALID_WIDTH-1:0]), + .data_out (afi_rdata_valid) + ); + end : single_port + + + // Connection for tile OEs + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) begin : tile_oe_loop + for (lane_i=0; lane_i < LANES_PER_TILE; ++lane_i) begin : lane_oe_loop + if (`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_WDATA || `_get_lane_usage(tile_i, lane_i) == LANE_USAGE_WRDATA) begin + assign tile_oe_req[tile_i][2*(lane_i+1)-1:2*lane_i] = LANE_OE_REQ_DQ; + end else if (`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_AC_HMC || `_get_lane_usage(tile_i, lane_i) == LANE_USAGE_AC_CORE) begin + assign tile_oe_req[tile_i][2*(lane_i+1)-1:2*lane_i] = LANE_OE_REQ_ON; + end else begin + assign tile_oe_req[tile_i][2*(lane_i+1)-1:2*lane_i]= LANE_OE_REQ_OFF; + end + end : lane_oe_loop + + always_comb begin : tile_oe_gen + int_core2l_oe[tile_i] = '0; + if (`_use_dq_lane_oe(tile_i, tile_oe_req)) begin + int_core2l_oe[tile_i] = {dq_lane_oe_strobe, dq_lane_oe_data[tile_i]}; + end else if (`_use_ac_lane_oe(tile_i, tile_oe_req)) begin + int_core2l_oe[tile_i] = '1; + end + end : tile_oe_gen + + end : tile_oe_loop + + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to output-only pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_A_PINLOC) != 0) begin : mem_a + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_A_PINLOC, PORT_MEM_A_WIDTH, PORT_AFI_ADDR_WIDTH, afi_addr) + end + + if (`_get_pin_count(PORT_MEM_BA_PINLOC) != 0) begin : mem_ba + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_BA_PINLOC, PORT_MEM_BA_WIDTH, PORT_AFI_BA_WIDTH, afi_ba) + end + + if (`_get_pin_count(PORT_MEM_BG_PINLOC) != 0) begin : mem_bg + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_BG_PINLOC, PORT_MEM_BG_WIDTH, PORT_AFI_BG_WIDTH, afi_bg) + end + + if (`_get_pin_count(PORT_MEM_C_PINLOC) != 0) begin : mem_c + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_C_PINLOC, PORT_MEM_C_WIDTH, PORT_AFI_C_WIDTH, afi_c) + end + + if (`_get_pin_count(PORT_MEM_CKE_PINLOC) != 0) begin : mem_cke + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_CKE_PINLOC, PORT_MEM_CKE_WIDTH, PORT_AFI_CKE_WIDTH, afi_cke) + end + + if (`_get_pin_count(PORT_MEM_CS_N_PINLOC) != 0) begin : mem_cs_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_CS_N_PINLOC, PORT_MEM_CS_N_WIDTH, PORT_AFI_CS_N_WIDTH, afi_cs_n) + end + + if (`_get_pin_count(PORT_MEM_RM_PINLOC) != 0) begin : mem_rm + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_RM_PINLOC, PORT_MEM_RM_WIDTH, PORT_AFI_RM_WIDTH, afi_rm) + end + + if (`_get_pin_count(PORT_MEM_ODT_PINLOC) != 0) begin : mem_odt + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_ODT_PINLOC, PORT_MEM_ODT_WIDTH, PORT_AFI_ODT_WIDTH, afi_odt) + end + + if (`_get_pin_count(PORT_MEM_RAS_N_PINLOC) != 0) begin : mem_ras_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_RAS_N_PINLOC, PORT_MEM_RAS_N_WIDTH, PORT_AFI_RAS_N_WIDTH, afi_ras_n) + end + + if (`_get_pin_count(PORT_MEM_CAS_N_PINLOC) != 0) begin : mem_cas_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_CAS_N_PINLOC, PORT_MEM_CAS_N_WIDTH, PORT_AFI_CAS_N_WIDTH, afi_cas_n) + end + + if (`_get_pin_count(PORT_MEM_WE_N_PINLOC) != 0) begin : mem_we_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_WE_N_PINLOC, PORT_MEM_WE_N_WIDTH, PORT_AFI_WE_N_WIDTH, afi_we_n) + end + + if (`_get_pin_count(PORT_MEM_RESET_N_PINLOC) != 0) begin : mem_reset_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_RESET_N_PINLOC, PORT_MEM_RESET_N_WIDTH, PORT_AFI_RST_N_WIDTH, afi_rst_n) + end + + if (`_get_pin_count(PORT_MEM_ACT_N_PINLOC) != 0) begin : mem_act_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_ACT_N_PINLOC, PORT_MEM_ACT_N_WIDTH, PORT_AFI_ACT_N_WIDTH, afi_act_n) + end + + if (`_get_pin_count(PORT_MEM_PAR_PINLOC) != 0) begin : mem_par + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_PAR_PINLOC, PORT_MEM_PAR_WIDTH, PORT_AFI_PAR_WIDTH, afi_par) + end + + if (`_get_pin_count(PORT_MEM_CA_PINLOC) != 0) begin : mem_ca + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_CA_PINLOC, PORT_MEM_CA_WIDTH, PORT_AFI_CA_WIDTH, afi_ca) + end + + if (`_get_pin_count(PORT_MEM_REF_N_PINLOC) != 0) begin : mem_ref_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_REF_N_PINLOC, PORT_MEM_REF_N_WIDTH, PORT_AFI_REF_N_WIDTH, afi_ref_n) + end + + if (`_get_pin_count(PORT_MEM_WPS_N_PINLOC) != 0) begin : mem_wps_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_WPS_N_PINLOC, PORT_MEM_WPS_N_WIDTH, PORT_AFI_WPS_N_WIDTH, afi_wps_n) + end + + if (`_get_pin_count(PORT_MEM_RPS_N_PINLOC) != 0) begin : mem_rps_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_RPS_N_PINLOC, PORT_MEM_RPS_N_WIDTH, PORT_AFI_RPS_N_WIDTH, afi_rps_n) + end + + if (`_get_pin_count(PORT_MEM_DOFF_N_PINLOC) != 0) begin : mem_doff_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_DOFF_N_PINLOC, PORT_MEM_DOFF_N_WIDTH, PORT_AFI_DOFF_N_WIDTH, afi_doff_n) + end + + if (`_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0 && `_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : mem_ldab_n + logic [PORT_AFI_LD_N_WIDTH/2-1:0] afi_lda_n, afi_ldb_n; + assign afi_lda_n = afi_ld_n[0 +: PORT_AFI_LD_N_WIDTH / 2]; + assign afi_ldb_n = afi_ld_n[PORT_AFI_LD_N_WIDTH / 2 +: PORT_AFI_LD_N_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0) begin : a + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_LDA_N_PINLOC, PORT_MEM_LDA_N_WIDTH, (PORT_AFI_LD_N_WIDTH / 2), afi_lda_n) + end + if (`_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : b + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_LDB_N_PINLOC, PORT_MEM_LDB_N_WIDTH, (PORT_AFI_LD_N_WIDTH / 2), afi_ldb_n) + end + end + + if (`_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0 && `_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : mem_rwab_n + logic [PORT_AFI_RW_N_WIDTH/2-1:0] afi_rwa_n, afi_rwb_n; + + assign afi_rwa_n = afi_rw_n[0 +: PORT_AFI_RW_N_WIDTH / 2]; + assign afi_rwb_n = afi_rw_n[PORT_AFI_RW_N_WIDTH / 2 +: PORT_AFI_RW_N_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0) begin : a + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_RWA_N_PINLOC, PORT_MEM_RWA_N_WIDTH, (PORT_AFI_RW_N_WIDTH / 2), afi_rwa_n) + end + if (`_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : b + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_RWB_N_PINLOC, PORT_MEM_RWB_N_WIDTH, (PORT_AFI_RW_N_WIDTH / 2), afi_rwb_n) + end + end + + if (`_get_pin_count(PORT_MEM_LBK0_N_PINLOC) != 0) begin : mem_lbk0_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_LBK0_N_PINLOC, PORT_MEM_LBK0_N_WIDTH, PORT_AFI_LBK0_N_WIDTH, afi_lbk0_n) + end + + if (`_get_pin_count(PORT_MEM_LBK1_N_PINLOC) != 0) begin : mem_lbk1_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_LBK1_N_PINLOC, PORT_MEM_LBK1_N_WIDTH, PORT_AFI_LBK1_N_WIDTH, afi_lbk1_n) + end + + if (`_get_pin_count(PORT_MEM_CFG_N_PINLOC) != 0) begin : mem_cfg_n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_CFG_N_PINLOC, PORT_MEM_CFG_N_WIDTH, PORT_AFI_CFG_N_WIDTH, afi_cfg_n) + end + + if (`_get_pin_count(PORT_MEM_AP_PINLOC) != 0) begin : mem_ap + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_AP_PINLOC, PORT_MEM_AP_WIDTH, PORT_AFI_AP_WIDTH, afi_ap) + end + + if (`_get_pin_count(PORT_MEM_AINV_PINLOC) != 0) begin : mem_ainv + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_AINV_PINLOC, PORT_MEM_AINV_WIDTH, PORT_AFI_AINV_WIDTH, afi_ainv) + end + + if (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0) begin : mem_dm + //: AC_TIE_OE_HIGH + //inversion is required because sequencer requires WR_INVERT to be true inside I/O buffer + `_connect_out_with_regs(PORT_MEM_DM_PINLOC, PORT_MEM_DM_WIDTH, PORT_AFI_DM_WIDTH, ~afi_dm) + end + + if (`_get_pin_count(PORT_MEM_BWS_N_PINLOC) != 0) begin : mem_bws_n + //: AC_TIE_OE_HIGH + //inversion is required because sequencer requires WR_INVERT to be true inside I/O buffer + `_connect_out_with_regs(PORT_MEM_BWS_N_PINLOC, PORT_MEM_BWS_N_WIDTH, PORT_AFI_BWS_N_WIDTH, ~afi_bws_n) + end + + if (`_get_pin_count(PORT_MEM_D_PINLOC) != 0) begin : mem_d + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_D_PINLOC, PORT_MEM_D_WIDTH, PORT_AFI_WDATA_WIDTH, afi_wdata) + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to input-only pins + // tie off unused core-2-lane connections + //////////////////////////////////////////////////////////////////////////// + + if (`_get_pin_count(PORT_MEM_ALERT_N_PINLOC) != 0) begin : mem_alert_n + logic [PORT_MEM_ALERT_N_WIDTH-1:0] zeros; + assign zeros = '0; + `_connect_out(PORT_MEM_ALERT_N_PINLOC, PORT_MEM_ALERT_N_WIDTH, PORT_MEM_ALERT_N_WIDTH, zeros) + end + + if (`_get_pin_count(PORT_MEM_PE_N_PINLOC) != 0) begin : mem_pe_n + logic [PORT_MEM_PE_N_WIDTH-1:0] zeros; + assign zeros = '0; + `_connect_out(PORT_MEM_PE_N_PINLOC, PORT_MEM_PE_N_WIDTH, PORT_MEM_PE_N_WIDTH, zeros) + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to bidirectional pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 || `_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0) begin : mem_sp_bidir_data + logic [3:0] c2p_dq_oe; + + assign c2p_dq_oe = (PORT_AFI_WDATA_VALID_WIDTH < 4) ? {'0, afi_wdata_valid_r} : afi_wdata_valid_r; + assign dq_lane_oe_data = {(NUM_OF_RTL_TILES){c2p_dq_oe}}; + + + if (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0) begin : mem_dq + `_connect_out_with_regs(PORT_MEM_DQ_PINLOC, PORT_MEM_DQ_WIDTH, PORT_AFI_WDATA_WIDTH, afi_wdata) + `_connect_in_with_regs(PORT_MEM_DQ_PINLOC, PORT_MEM_DQ_WIDTH, PORT_AFI_RDATA_WIDTH, afi_rdata) + end + + if (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0) begin : mem_dbi_n + if (MEM_DATA_MASK_EN) begin : dm + `_connect_out_with_regs(PORT_MEM_DBI_N_PINLOC, PORT_MEM_DBI_N_WIDTH, PORT_AFI_DM_N_WIDTH, afi_dm_n) + end else begin : wdbi + logic [PORT_MEM_DBI_N_WIDTH-1:0] zeros; + assign zeros = '0; + `_connect_out(PORT_MEM_DBI_N_PINLOC, PORT_MEM_DBI_N_WIDTH, PORT_MEM_DBI_N_WIDTH, zeros) + end + end + + end + + assign afi_rdata_dbi_n = '1; + + // Double channel protocol - DDR4, RLDRAM3 + if ((`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) || (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0)) begin : mem_dp_bidir_data + + localparam MEM_NUM_OF_WRITE_GROUPS_PER_PORT = MEM_TTL_NUM_OF_WRITE_GROUPS / 2; + localparam PORT_AFI_WDATA_VALID_PER_PORT_WIDTH = PORT_AFI_WDATA_VALID_WIDTH / 2; + localparam PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH = PORT_AFI_WDATA_VALID_PER_PORT_WIDTH * MEM_NUM_OF_WRITE_GROUPS_PER_PORT; + + logic [PORT_AFI_WDATA_VALID_PER_PORT_WIDTH-1:0] afi_wdata_valid_a, afi_wdata_valid_b; + logic [3:0] c2p_dqa_oe, c2p_dqb_oe; + + assign afi_wdata_valid_a = afi_wdata_valid_r[0 +: PORT_AFI_WDATA_VALID_PER_PORT_WIDTH]; + assign afi_wdata_valid_b = afi_wdata_valid_r[PORT_AFI_WDATA_VALID_PER_PORT_WIDTH +: PORT_AFI_WDATA_VALID_PER_PORT_WIDTH]; + + assign c2p_dqa_oe = (PORT_AFI_WDATA_VALID_PER_PORT_WIDTH < 4) ? {'0, afi_wdata_valid_a} : afi_wdata_valid_a; + assign c2p_dqb_oe = (PORT_AFI_WDATA_VALID_PER_PORT_WIDTH < 4) ? {'0, afi_wdata_valid_b} : afi_wdata_valid_b; + + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) begin : dqa_dqb_oe_sel + if (tile_i == (`_get_tile(PORT_MEM_QKA_PINLOC, 0)) ) begin + assign dq_lane_oe_data[tile_i] = c2p_dqa_oe; + end else if ( tile_i == (`_get_tile(PORT_MEM_QKB_PINLOC, 0))) begin + assign dq_lane_oe_data[tile_i] = c2p_dqb_oe; + end else begin + assign dq_lane_oe_data[tile_i] = '0; + end + end + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : mem_dqab + logic [PORT_AFI_RDATA_WIDTH/2-1:0] afi_rdata_a , afi_rdata_b; + logic [PORT_AFI_WDATA_WIDTH/2-1:0] afi_wdata_a , afi_wdata_b; + + assign afi_rdata[0 +: PORT_AFI_RDATA_WIDTH / 2] = afi_rdata_a; + assign afi_wdata_a = afi_wdata[0 +: PORT_AFI_WDATA_WIDTH / 2]; + + assign afi_rdata[PORT_AFI_RDATA_WIDTH / 2 +: PORT_AFI_RDATA_WIDTH / 2] = afi_rdata_b; + assign afi_wdata_b = afi_wdata[PORT_AFI_RDATA_WIDTH / 2 +: PORT_AFI_WDATA_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0) begin : a + `_connect_out_with_regs(PORT_MEM_DQA_PINLOC, PORT_MEM_DQA_WIDTH, (PORT_AFI_WDATA_WIDTH / 2), afi_wdata_a) + `_connect_in_with_regs(PORT_MEM_DQA_PINLOC, PORT_MEM_DQA_WIDTH, (PORT_AFI_RDATA_WIDTH / 2), afi_rdata_a) + end + + if (`_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : b + `_connect_out_with_regs(PORT_MEM_DQB_PINLOC, PORT_MEM_DQB_WIDTH, (PORT_AFI_WDATA_WIDTH / 2), afi_wdata_b) + `_connect_in_with_regs(PORT_MEM_DQB_PINLOC, PORT_MEM_DQB_WIDTH, (PORT_AFI_RDATA_WIDTH / 2), afi_rdata_b) + end + end + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0) begin : mem_dinvab + + logic [PORT_AFI_RDATA_DINV_WIDTH/2-1:0] afi_rdata_dinv_a , afi_rdata_dinv_b; + logic [PORT_AFI_WDATA_DINV_WIDTH/2-1:0] afi_wdata_dinv_a , afi_wdata_dinv_b; + + assign afi_rdata_dinv[0 +: PORT_AFI_RDATA_DINV_WIDTH / 2] = afi_rdata_dinv_a; + assign afi_wdata_dinv_a = afi_wdata_dinv[0 +: PORT_AFI_RDATA_DINV_WIDTH / 2]; + + assign afi_rdata_dinv[PORT_AFI_RDATA_DINV_WIDTH / 2 +: PORT_AFI_RDATA_DINV_WIDTH / 2] = afi_rdata_dinv_b; + assign afi_wdata_dinv_b = afi_wdata_dinv[PORT_AFI_RDATA_DINV_WIDTH / 2 +: PORT_AFI_RDATA_DINV_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : a + `_connect_out_with_regs(PORT_MEM_DINVA_PINLOC, PORT_MEM_DINVA_WIDTH, (PORT_AFI_WDATA_DINV_WIDTH / 2), afi_wdata_dinv_a) + `_connect_in_with_regs(PORT_MEM_DINVA_PINLOC, PORT_MEM_DINVA_WIDTH, (PORT_AFI_RDATA_DINV_WIDTH / 2), afi_rdata_dinv_a) + end + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : b + `_connect_out_with_regs(PORT_MEM_DINVB_PINLOC, PORT_MEM_DINVB_WIDTH, (PORT_AFI_WDATA_DINV_WIDTH / 2), afi_wdata_dinv_b) + `_connect_in_with_regs(PORT_MEM_DINVB_PINLOC, PORT_MEM_DINVB_WIDTH, (PORT_AFI_RDATA_DINV_WIDTH / 2), afi_rdata_dinv_b) + end + end else begin : no_mem_dinvab + assign afi_rdata_dinv = '0; + end + end else begin : no_mem_dp_bidir_data + assign afi_rdata_dinv = '0; + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to bidir strobe pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_DQS_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQS_N_PINLOC) != 0) begin : mem_dqs_pair + logic [(PORT_MEM_DQS_WIDTH * DDR_RATIO)-1:0] disable_dqs; + + assign disable_dqs = '0; + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (PORT_AFI_DQS_BURST_WIDTH) + ) afi_dqs_burst_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_dqs_burst), + .data_out (afi_dqs_burst_r) + ); + assign dq_lane_oe_strobe = (PORT_AFI_DQS_BURST_WIDTH < 4) ? {'0, afi_dqs_burst_r} : afi_dqs_burst_r; + + end else begin + // RLDRAM3 & QDR-IV require OE tie-offs for its QKx(RCLK) & DKx(WCLK) + // DKx pins will have its OE inverted within DATA BUFFER through RDQS attribute + // For more details, study FB# 579260 + assign dq_lane_oe_strobe = '1; + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to output-only clock pins + //////////////////////////////////////////////////////////////////////////// + + if (`_get_pin_count(PORT_MEM_CK_PINLOC) != 0 && `_get_pin_count(PORT_MEM_CK_N_PINLOC) != 0) begin : mem_ck_pair + logic [(PORT_MEM_CK_WIDTH * DDR_RATIO)-1:0] disable_ck; + assign disable_ck = '0; + + if (`_get_pin_count(PORT_MEM_CK_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DKA_PINLOC) == 0) begin : p + //: AC_TIE_OE_HIGH + //mem_ck requires a 0 tie-off @ data_buffer to generate clock pattern + `_connect_out_with_regs(PORT_MEM_CK_PINLOC, PORT_MEM_CK_WIDTH, (PORT_MEM_CK_WIDTH * DDR_RATIO), disable_ck) + end + + if (`_get_pin_count(PORT_MEM_CK_N_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DKA_PINLOC) == 0) begin : n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_CK_N_PINLOC, PORT_MEM_CK_N_WIDTH, (PORT_MEM_CK_N_WIDTH * DDR_RATIO), disable_ck) + end + end + + if (`_get_pin_count(PORT_MEM_DK_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DK_N_PINLOC) != 0) begin : mem_dk_pair + logic [(PORT_MEM_DK_WIDTH * DDR_RATIO)-1:0] disable_dk; + assign disable_dk = '0; + + if (`_get_pin_count(PORT_MEM_DK_PINLOC) != 0) begin : p + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_DK_PINLOC, PORT_MEM_DK_WIDTH, (PORT_MEM_DK_WIDTH * DDR_RATIO), disable_dk) + end + + if (`_get_pin_count(PORT_MEM_DK_N_PINLOC) != 0) begin : n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_DK_N_PINLOC, PORT_MEM_DK_N_WIDTH, (PORT_MEM_DK_N_WIDTH * DDR_RATIO), disable_dk) + end + end + + if (`_get_pin_count(PORT_MEM_DKA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DKA_N_PINLOC) != 0) begin : mem_dka_pair + logic [(PORT_MEM_DKA_WIDTH * DDR_RATIO)-1:0] disable_dka; + assign disable_dka = '0; + + if (`_get_pin_count(PORT_MEM_DKA_PINLOC) != 0) begin : p + //: AC_TIE_OE_HIGH + //DKA and DKB of QDRIV is tie-off in the unused pin session using the C2L_DRIVEN parameter + end + + if (`_get_pin_count(PORT_MEM_DKA_N_PINLOC) != 0) begin : n + //: AC_TIE_OE_HIGH + //`_connect_out_with_regs(PORT_MEM_DKA_N_PINLOC, PORT_MEM_DKA_N_WIDTH, (PORT_MEM_DKA_N_WIDTH * DDR_RATIO), disable_dka) + end + end + + if (`_get_pin_count(PORT_MEM_DKB_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DKB_N_PINLOC) != 0) begin : mem_dkb_pair + logic [(PORT_MEM_DKB_WIDTH * DDR_RATIO)-1:0] disable_dkb; + assign disable_dkb = '0; + + if (`_get_pin_count(PORT_MEM_DKB_PINLOC) != 0) begin : p + //: AC_TIE_OE_HIGH + //DKA and DKB of QDRIV is tie-off in the unused pin session using the C2L_DRIVEN parameter + end + + if (`_get_pin_count(PORT_MEM_DKB_N_PINLOC) != 0) begin : n + //: AC_TIE_OE_HIGH + //`_connect_out_with_regs(PORT_MEM_DKB_N_PINLOC, PORT_MEM_DKB_N_WIDTH, (PORT_MEM_DKB_N_WIDTH * DDR_RATIO), disable_dkb) + end + end + + if (`_get_pin_count(PORT_MEM_K_PINLOC) != 0 && `_get_pin_count(PORT_MEM_K_N_PINLOC) != 0) begin : mem_k_pair + logic [(PORT_MEM_K_WIDTH * DDR_RATIO)-1:0] disable_k; + assign disable_k = '0; + + if (`_get_pin_count(PORT_MEM_K_PINLOC) != 0) begin : p + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_K_PINLOC, PORT_MEM_K_WIDTH, (PORT_MEM_K_WIDTH * DDR_RATIO), disable_k) + end + + if (`_get_pin_count(PORT_MEM_K_N_PINLOC) != 0) begin : n + //: AC_TIE_OE_HIGH + `_connect_out_with_regs(PORT_MEM_K_N_PINLOC, PORT_MEM_K_N_WIDTH, (PORT_MEM_K_N_WIDTH * DDR_RATIO), disable_k) + end + end + + //////////////////////////////////////////////////////////////////////////// + // Tie off core2l_data for unused connections + ////////////////////////////////////////////////////////////////////////////// + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) begin + assign `_unused_core2l_afi(pin_i) = '0; + end + end + endgenerate +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "O/UL8p4fjkdiniiI1fb4ptOFsAdF7Y3Hxp7T6jxKv0MGrEyaXaFTwgtlHVroTr2ly77oTzeBnz/H2ugF2Lm64wLDISiNxLkGwFrph7cf8l5oezq71gySptz6a1i1+sH+uTBP/IhfWlKmvqzXkENOz1PT/J8+EwAOHl+z3hJ5W8p9iA7X2pLUvopxcSXzYyZFe7Y+SdxGDVeHq8Bixu/tMkSijiUVBAWYj9rL+Bb7bFHiGYRY3a1pkV73DpmsHfYc0tms3raraTxvZT5GHHOWGGA0jwdXmk2nYMzZ0yXAPbxKBvamSYhkQ9iCYMbXyXZvJ2CampGvcdzTSqwpsh6XuEuj7ekqkq8vCcQAYjZWDuG2bbyZb8tFBXYAj2TP1WRqmi2D0PFoFRN6I/B6avkCJf/sB5rQvX+LqvUVTrDifTKZlZMp1wunKDbKYXn8OlIK7YKw6PYqbiVArkSfKRr0QIZf5nUFCZdBW5S31m4UyzmgoMlrMv9F7pjlLycoQe253dA2V0H/Mya0MkYPFRtCVFOr0eHvyOyfw/ZjhYihWNx6k2X10671d57bVgfldt0Wz7xlfTCQ71nxgWAugeYC5h6dpP7l/wYJJpyY36d9WgWKPKM0Kb2DUvTwIvQ8wNXB5jxIxesmwOUAMhBWnXZ/HHyMsIcqLdeLxzxe2sSNBTeItESEn5IBjA/gOoGB9m5vmdrUQwoJ2tpT/Rdr7f3EbtXndWR0zZkubN5nakiwlBU0J3B2yebbk6WYJcNdSTbVk0kvnQ4waWfXaQsL9RvRZwf1Lt8xoDlWYDny3eBotf0xL9FcWAT1PC86RExIT/TDIE04KC6cYE2sI/DhpBJGXcvatQlIJ6i0AvYXue4JJBdRFEc039ncDEbAIhN2VnKEjR6nuLbrdPZNmOY8GAwtsJ86bgfeOCh1oLisc5Y8jMAPfKpA4tQSIs/i4Va+iRQ8+p3oa9zNCZpcaIX59FOshTyqxtL9mbH7qegrP4OQBmfuLSUvnctyc3okFXSm1G2x" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_df.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_df.sv new file mode 100644 index 0000000000..a6591b91ee --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_df.sv @@ -0,0 +1,168 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_bdir_df #( + parameter OCT_CONTROL_WIDTH = 1, + parameter HPRX_CTLE_EN = "off", + parameter HPRX_OFFSET_CAL = "false", + parameter CALIBRATED_OCT = 1 +) ( + inout tri io, + inout tri iobar, + output logic ibuf_o, + input logic obuf_i, + input logic obuf_ibar, + input logic obuf_oe, + input logic obuf_oebar, + input logic obuf_dtc, + input logic obuf_dtcbar, + input logic oct_termin +); + timeunit 1ns; + timeprecision 1ps; + + localparam DCCEN = "true"; + + logic pdiff_out_o; + logic pdiff_out_obar; + logic pdiff_out_oe; + logic pdiff_out_oebar; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + logic pdiff_out_dtc; + logic pdiff_out_dtcbar; + + tennm_io_ibuf # ( + .hprx_ctle_en (HPRX_CTLE_EN), + .hprx_offset_cal (HPRX_OFFSET_CAL), + .differential_mode ("true") + ) ibuf ( + .i(io), + .ibar(iobar), + .o(ibuf_o), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + + tennm_pseudo_diff_out # ( + .feedthrough ("true") + ) pdiff_out ( + .i(obuf_i), + .ibar(obuf_ibar), + .oein(obuf_oe), + .oebin(obuf_oebar), + .dtcin(obuf_dtc), + .dtcbarin(obuf_dtcbar), + .o(pdiff_out_o), + .obar(pdiff_out_obar), + .oeout(pdiff_out_oe), + .oebout(pdiff_out_oebar), + .dtc(pdiff_out_dtc), + .dtcbar(pdiff_out_dtcbar) + ); + + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf ( + .i(pdiff_out_o), + .o(io), + .oe(pdiff_out_oe), + .term_in(oct_termin), + .dynamicterminationcontrol(pdiff_out_dtc), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf_bar ( + .i(pdiff_out_obar), + .o(iobar), + .oe(pdiff_out_oebar), + .term_in(oct_termin), + .dynamicterminationcontrol(pdiff_out_dtcbar), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + end else + begin : no_oct + tennm_io_ibuf # ( + .hprx_ctle_en (HPRX_CTLE_EN), + .hprx_offset_cal (HPRX_OFFSET_CAL), + .differential_mode ("true") + ) ibuf ( + .i(io), + .ibar(iobar), + .o(ibuf_o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + + tennm_pseudo_diff_out # ( + .feedthrough ("true") + ) pdiff_out ( + .i(obuf_i), + .ibar(obuf_ibar), + .oein(obuf_oe), + .oebin(obuf_oebar), + .dtcin(), + .dtcbarin(), + .o(pdiff_out_o), + .obar(pdiff_out_obar), + .oeout(pdiff_out_oe), + .oebout(pdiff_out_oebar), + .dtc(), + .dtcbar() + ); + + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf ( + .i(pdiff_out_o), + .o(io), + .oe(pdiff_out_oe), + .dynamicterminationcontrol(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf_bar ( + .i(pdiff_out_obar), + .o(iobar), + .oe(pdiff_out_oebar), + .dynamicterminationcontrol(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "O/UL8p4fjkdiniiI1fb4ptOFsAdF7Y3Hxp7T6jxKv0MGrEyaXaFTwgtlHVroTr2ly77oTzeBnz/H2ugF2Lm64wLDISiNxLkGwFrph7cf8l5oezq71gySptz6a1i1+sH+uTBP/IhfWlKmvqzXkENOz1PT/J8+EwAOHl+z3hJ5W8p9iA7X2pLUvopxcSXzYyZFe7Y+SdxGDVeHq8Bixu/tMkSijiUVBAWYj9rL+Bb7bFHCmB0sCqqsnMVFChPrUH5R8EpM6Zx+JOZ6248VFZUbCNO7XXIO9mZeTEsSWO1Avir8RJF+rwsAscUTICvdjlBTd7ZMHqhAZ6tQajgtqIu4hDhK2Vk9qJ/piLrVRPpa9TnX7OoOJ5AK0cylLXJyIOCVVNZgJBW1Jp96UeZa3jkuOzPgop1+clHCPDl0gsCz7U/qIFZuQGRPzrPKqjPP+vJeRrelykSdehrKA4glctDerNMikn5usw8wIY+8fJLivYTwcVZvfzRsbzNoOrWz1ynswV47pl3HwpuQGLgT2xnkYGTQofpQKCj9zvo5NHpO2NY7BHk25pJ4Fy94t9/CItofR8P3sVu8d7S37Bo1NaaVG/OBpmFiIuaybAXviGp1tZw4VPZl9dGRzSWOvIRMbz+kSHVZCQEzylZvkEl+XWo88jHVLo3mn4r8pWZe96yRrUm5KyGRDJewk7Au/1NkEHC72IMgBctCWV7t5GbHmMiEKObk8bshp8zmSEBehl+t5AOjlQGPt5VCN0jyWPZkmmIpHtWvGVKull3+FwFCD9avO7Fe9Ff7h+LOSFZUp8ur0EyL+FUPK04u8RHWrvSIUAcHEgNWnjkjFK2KCELCSrvwKo+V6LX8ucjlDuir3zdkwJy15SpZ7N+nmlXJ+iygufhadnKPYfQ6UiFOA1i7NwCXvmfbwhWgUTYdrX+MqoGrYTuLDrnwXRTntqqlXkNE6ZCbtGZz8NcLIQuwN+MbpnisjX7uQ8k4tKYb3jiy/zKLQxd6ntWWW/GuXT6sCIxmO+Pz" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_se.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_se.sv new file mode 100644 index 0000000000..a0719c0bfb --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_se.sv @@ -0,0 +1,87 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_bdir_se #( + parameter OCT_CONTROL_WIDTH = 1, + parameter HPRX_CTLE_EN = "off", + parameter HPRX_OFFSET_CAL = "false", + parameter CALIBRATED_OCT = 1 +) ( + inout tri io, + output logic ibuf_o, + input logic obuf_i, + input logic obuf_oe, + input logic obuf_dtc, + input logic oct_termin +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + tennm_io_ibuf # ( + .hprx_ctle_en (HPRX_CTLE_EN), + .hprx_offset_cal (HPRX_OFFSET_CAL) + ) ibuf ( + .i(io), + .o(ibuf_o), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .ibar() + ); + + tennm_io_obuf obuf ( + .i(obuf_i), + .o(io), + .oe(obuf_oe), + .term_in(oct_termin), + .dynamicterminationcontrol(obuf_dtc), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + end else + begin : no_oct + tennm_io_ibuf # ( + .hprx_ctle_en (HPRX_CTLE_EN), + .hprx_offset_cal (HPRX_OFFSET_CAL) + ) ibuf ( + .i(io), + .o(ibuf_o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .ibar() + ); + + tennm_io_obuf obuf ( + .i(obuf_i), + .o(io), + .oe(obuf_oe), + .dynamicterminationcontrol(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "O/UL8p4fjkdiniiI1fb4ptOFsAdF7Y3Hxp7T6jxKv0MGrEyaXaFTwgtlHVroTr2ly77oTzeBnz/H2ugF2Lm64wLDISiNxLkGwFrph7cf8l5oezq71gySptz6a1i1+sH+uTBP/IhfWlKmvqzXkENOz1PT/J8+EwAOHl+z3hJ5W8p9iA7X2pLUvopxcSXzYyZFe7Y+SdxGDVeHq8Bixu/tMkSijiUVBAWYj9rL+Bb7bFHJ77jCjl2qih2EzD3gNKqiwaKup7hP2dRq7UROjsDVZ30rRw4diZ+JZGo3VQ3SwX32eBGN93oxDhZ9E79D4qG+AQw9gHDwoKNDrqCpWGUxEj85vZi7kHpE9ztbJabjcqANFKeKgPHo0ahI0s/L+M5+udKVtBmpqz9NiTc3hM78+Z6/O3q/BxuPF5LmPb8DOJB9s6qL3tpA2W4elHPBhCuHzjlkTEYMxlgzaIbgujGLt0kpVGAOGtc1ZD2b7MK1O5E6PuWRHY2M374JF0DBXiXnJupJyMYTdPRAErVQR0avuytHspGunfLeH/KYDzKropWFqYpAlx3yNDRSfl9JCgLUWV338UJtMdev92TuRV9MLDpKGbhUhNXoikvoxQOxoWBtLfIFd1wAy3WrAplZbr3C0Aoj0JuMKhkAoeNuTfHePlTuWbM73wbtcw5/CIaHDunIklgZZ23DRMjn0gHwZJjZ5lcf6b+/78rAPQBknj+chUO+LZQtyshQ5FbeU/INwQxMdsvBZllPg99X//GePjzgQX8TUtHirjMGoLWJmz0GzroxxUEgyy3Wx8DhBGYmkDKCbekLC2/bC9yNi/VvLykACv8y/tjgKQQnElEU2/KKgqovLJiTTjmKGYvczr851zigocF71cYz6omqtl2uTQ2OFlNnLgSz7KDJePy6W6g4ifRd0gsC/Njy8f/H/TpmMzoO4asAlEp5QWF99P5OtYfmlmcADEZM0mxGyOooRfpkDIkAQI/vnbzAntjbCWEMW6NoNxKilPtXSLJ+WGj1U1ts" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_cp_i.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_cp_i.sv new file mode 100644 index 0000000000..23eef08d88 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_cp_i.sv @@ -0,0 +1,74 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_udir_cp_i # ( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic ibar, + output logic o, + output logic obar, + input logic oct_termin +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + tennm_io_ibuf ibuf( + .i(i), + .o(o), + .term_in(oct_termin), + .ibar(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + + tennm_io_ibuf ibuf_bar( + .i(ibar), + .o(obar), + .term_in(oct_termin), + .ibar(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + end else + begin : no_oct + tennm_io_ibuf ibuf( + .i(i), + .o(o), + .ibar(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + + tennm_io_ibuf ibuf_bar( + .i(ibar), + .o(obar), + .ibar(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "O/UL8p4fjkdiniiI1fb4ptOFsAdF7Y3Hxp7T6jxKv0MGrEyaXaFTwgtlHVroTr2ly77oTzeBnz/H2ugF2Lm64wLDISiNxLkGwFrph7cf8l5oezq71gySptz6a1i1+sH+uTBP/IhfWlKmvqzXkENOz1PT/J8+EwAOHl+z3hJ5W8p9iA7X2pLUvopxcSXzYyZFe7Y+SdxGDVeHq8Bixu/tMkSijiUVBAWYj9rL+Bb7bFGrrtD9+q4PfGdZLc+RGofgiqNMaJtMWNavu7kldkyWpKcD2mO1ggSWLmbB2Z2SOdGgMOj9yjWYSsdNPCQqsQ/C5ewFThFBZ9nwtD8qIFcYxxd9rhvY58KkEe0mZyJ4vsFxzICJMjVrR/CgutXHe4YSBzeLYanptnEehaODS0H1Ycqkl5ul7IuuhEwfEiZi+A9qm8LcAUVYIb34HgIdEcNZPr/r6BylNP1Nk+eFXiUluOWHYvjTBtvcSDTGHH8Oz8tyvC0AGL8SLHz1GVKojopKJ8vXMHAf0XudIhfGUBlnuzd02KhHizurdKgVIRpY03t7M4CY/qYcqm51Ov/wfApTiosoXE/9zT9UDD6z+nDY0ROqZly+RUDh767KxFWiSGMyORJ+Ll75TLIfVyWNOHUk/iFj2h2Z+wIzJ+/Le8QXOQXPK+6Vh4OO0jwS0thyG2ibFupvzHEtJnlMjN69LTN5b154KDBdwgXKkwvHFwjkuJ/XkKMHlTWGy/6jg2uuRfmb0w3AwQNIBSkELL3kSie5Txocz7rhakkPBTvtOXVOkXLDZ89VZhVN31VQArOe+3CXdJpew5o60w0aVe3Dc/ZgaPNw4XevXHvW43u2tIHhE7fzCql9aqM+ErlvA6horhD72KssjrOlCJb1zUqtNaK8eSyVLvLseaPI9GW+waE1/wh35200ZoEb9CRO5bAluWQtlyDS65trX0Rc9XDuY54OdCJKHpzv6tc9MnBzQ9qNzyODm34LTGqZfAsQN5wcMGgI+CM3nCmUwwwEsmoU88sU" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_i.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_i.sv new file mode 100644 index 0000000000..37ce33e329 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_i.sv @@ -0,0 +1,58 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_udir_df_i # ( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic ibar, + output logic o, + input logic oct_termin +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + tennm_io_ibuf # ( + .differential_mode ("true") + ) ibuf ( + .i(i), + .ibar(ibar), + .o(o), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + end else + begin : no_oct + tennm_io_ibuf # ( + .differential_mode ("true") + ) ibuf ( + .i(i), + .ibar(ibar), + .o(o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2SUhvjw++wGb07D+cuKvWVU+o2EWQJ70nDOdTTx9xPz4E2lZBeYmAYpWQi2sRSoicAukT+2yLYNmPgSyDisR0jYO7W+L/nGmGGzAY8qPic6n+wwsdWnlxDCwCL3+rKM0LonRdNSrbVc5+zCMKVA+dawIhT8tGueE19yDaqo2avP8vIAzDPMLtmKJWo9DrlZ+NQbwQsZNPy7aZByBlOwTW9egnw4wyOA5REBYZog3zmAykF5rZQ4kO+hf8+E3YmzEbZyAnxpZUQBYpUuCunt/G5s/vBRz5lfuBh1FTkcKRM4rp6xVwrJOouNDeP24a5ka/Sj45l+Evd1raiohhEwSJ2DVkrQczZO/QU3r840v+8m+elqGrMYLajz8jLrB6wMwbzUR4Ut9gzIB1fcBMOqW7oA1AdGeabEAwUYeBcqcqB8GC26lcGzbpHHPYLrIDykv0OyhDnmYKVK5Op+2ncVNd3zzbssD29v8UnohAYtwKXDEgM252o+GFHyVX9U8T3wsqRQRWOOShrHnxjRINvdFe4Vs+Ww1MzEAu7NIBhdKDV9MTBQg6CWnZBWqbHpedZq4ZajmfK+GMSaO0E8c0WbJFowdPXinBNDdW0ltR0jxOw4dneXEwEhGvJDZr1bxYI2UCFlkJOHY6fDvQL/vAvw/iHt1uZuWplT3gNPrN0Nd51JwzLfMoxtSPIMTU+eDQBmpPxWSyyqufG/zccEuTq4yxWDqvG3e7MA/IlDgTxNlmWxNfHvYgEoZ4UxS+bvh4M4zYiFyd4tsvC0UqkGm7gqy3x" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_o.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_o.sv new file mode 100644 index 0000000000..06938b0935 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_o.sv @@ -0,0 +1,117 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_udir_df_o #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic ibar, + output logic o, + output logic obar, + input logic oein, + input logic oeinb, + input logic oct_termin +); + timeunit 1ns; + timeprecision 1ps; + + localparam DCCEN = "true"; + + logic pdiff_out_o; + logic pdiff_out_obar; + + logic pdiff_out_oe; + logic pdiff_out_oebar; + + tennm_pseudo_diff_out # ( + .feedthrough("true") + ) pdiff_out ( + .i(i), + .ibar(ibar), + .o(pdiff_out_o), + .obar(pdiff_out_obar), + .oein(oein), + .oebin(oeinb), + .oeout(pdiff_out_oe), + .oebout(pdiff_out_oebar), + .dtcin(), + .dtcbarin(), + .dtc(), + .dtcbar() + ); + + generate + if (CALIBRATED_OCT) + begin : cal_oct + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf ( + .i(pdiff_out_o), + .o(o), + .oe(pdiff_out_oe), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf_bar ( + .i(pdiff_out_obar), + .o(obar), + .oe(pdiff_out_oebar), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + end else + begin : no_oct + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf ( + .i(pdiff_out_o), + .o(o), + .oe(pdiff_out_oe), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + + tennm_io_obuf # ( + .dccen(DCCEN) + ) obuf_bar ( + .i(pdiff_out_obar), + .o(obar), + .oe(pdiff_out_oebar), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2iyaudw3CXs5bnDhNz55tBPhJE7/EqCIrx3CP+FC5DOSLzcm6keCWrcljkpG5uNx9t3CMiivc9hetJr2FTBnGDixn7EhRAngy0TjjXTaT68INZnZ+9yqAjCBzqyMb4pyxK053BpRPfcJwP3pKBrQ/AoyqdQ/XTdT/AqBfXk0yCfVV7Za8TIP3rEBF34QkBbkRVLcNNvVwOzsVVkdY0IT8LdqLKYMX45sgszZwX0gK5OCKS5dSliUyRAyqoeNMiuBoHxFeMGMtJ2csCzwBeGA3LaqZRdIhl/WairZm36kh8Zm8H0vNKhnPGbNxUqPd0old/nTVudZVad11PmuRA8aFK+M4kIYDAQNLrMGMliBVds4fPvDqk0mljaRTR5f24GNho5q1VTDJhQcocxhoWQ3j1Q71DZZqtu7BC8+QFj/UVlmDloq+Z/9/GQ0xBm41bpxFuElY9CORWIpd7j+i5fWFgU83O04pa7oy/hmtejYQgjkAg2LEPxPxd43ohTPMYhmzl2zot1TvbWsQ2uYLYpAUy0f5Ui4lutq+6PHCSJ+NWR8UgzmYfazy+heBMB59tKmZAikE4eWGyjaihWivyBy4+6Ez4InrAIm7xsKRJPmUfSB1akTdHuV0x+Z+C2YYUYdSxnmjH+I6dcQc7Ha/8BJvwTt81VY6bTkFvmZU8a7I+edRnniRcMfLDiR2QmjuGicyhpvq5ZkjAAToYSkSIYKKOYSl1iUyG8wNgC/0AF/t8+OYVnzr6askUBZDqY8v0xbTDemoEyiB0Gs9Q0GoVJAL4" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_i.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_i.sv new file mode 100644 index 0000000000..b01e9e09b8 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_i.sv @@ -0,0 +1,53 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_udir_se_i #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic oct_termin, + output logic o +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + tennm_io_ibuf ibuf( + .i(i), + .o(o), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .ibar(), + .dynamicterminationcontrol() + ); + end else + begin : no_oct + tennm_io_ibuf ibuf( + .i(i), + .o(o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .ibar(), + .dynamicterminationcontrol() + ); + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2FmthPOs++Dvdswo7+h08zwz/9gADvK/6sUMDX7whuEsL9NVEK2plHS/Y6vm2eNMDNCJt2UBZPXA6a5NSlJIh7gHcRInIyrMxFfupxD3mc10hF6Kbm2Gxn3/wIVV3ZMg20NVk9oe8XY6oKn7dl7eZ2KcITCYhCEU6PQp4jjZ02aNXBYrEocXu0/jX247tso6eX/j1Mbuv4a4dnrsv9qO5YETYsIrvgHW2lWD8Wt2oJn8owmXX7TP0SCURrFg+42GVvhx+BdHCAGQpxrcZNU9YuMKmnvZELmnpcFRhhfne3T3Tmz5bacI+qsB8eQJWFLQTmPAo2LOOWAZYTz+vD5Dk7Jg2IBeUgbf2z70wXkgQIuurhtWBWTIiYkqbyHoYrrhLqQ4cCr/MHNtrfYR1BrOaMvpFmQL4WBF/9wr+dvO5BfhO+nqX+hDdRcXyZHkP3+8Ngp3OrcghpyEgb0j54J2iROHwbZgWUc3iPZiv5ifgfo+CguNWfyQh8fneY2SqKXCA6ra7M9UHmFd4pcEhjeEXIAEVKOS9oDbele+0BG3HYVZs/LpjLxI2BLbhWJawaGo8tPRTzk/fBoWf/5kUff4sLPqZnn1PoubkJ0ungaleVHQYuihAVhmVW6D/Bp0pUgM3kJZd5W4sd6UNyyGA/s+rK8OtsuMEIMMBJICe5XKCWbsZ3a9Sg2tkhJjm/5OHsoOY6HoFhPedykVA5O1d8pGiQuWtC+GsRlK8Z3UeOzNnL/f5BWXabOU6VfVuMbzPZ7tDjGILH47m18xtD6c5E5J3Q" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_o.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_o.sv new file mode 100644 index 0000000000..dab39071cf --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_o.sv @@ -0,0 +1,58 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_udir_se_o #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + output logic o, + input logic oe, + input logic oct_termin +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + tennm_io_obuf obuf ( + .i(i), + .o(o), + .term_in(oct_termin), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .oe(oe), + .dynamicterminationcontrol(), + .devoe() + ); + end else + begin : no_oct + tennm_io_obuf obuf ( + .i(i), + .o(o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .oe(oe), + .dynamicterminationcontrol(), + .devoe() + ); + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm0tDDu14dsl4TOuKMl087O8gOU7F660uXBhz5+pbY9/eMzX4u3w+gtxPLCnxFqRDACfsgc8ZIJ5YgseD0Rfaj2UEVy6N1dIoQhXCYVMzK6NUTR1AyxTLIOwwNSYVmfPjfxkpm2eleyU9kZEQcYWQ457Ww/TaQlo552Eqzbp+y6PAo8kLS9R13ZI+01b2nNKBRXVGGtXbFjS1OuPH1RPyg3GEOvV5w3XAHVSMPqM8o3hzzhw9USZ/FA+VgVGV2b/QTQBfsmr9tK8eOUav8mwUALFeDEgxeewKwjYBaj9ywmk1C4IuLrJFPUnmHJ4emonoKtvA8Tt9mZ+xh14Kvg+RXfJkgP+TM4Fd6YjYZelWVRmI9jDnrDY6/KfbHCZvsrkVXulso6obQaBz6qPQ0vQ2ac0hgKa0Zkst+4N6i9ANrvO6koZp9g6wuvl2o50IP8eQDRr6m9mOQ+otZa0OrlaZEY7/9vOD83qCFNfVR3jjQ8o256sLF6WrpdbyzsZ6Ph0hjKkX7pGRkjc/+qJVVKnRiPJSPHbWM++ikwEKIHeOhqwtxXRbrkdCRNmsdKxlv2ZPGM3OKY9Mm8jJWly6A9/TkkZGDATi7TpvJLxHQKSxdSfGJWx4NRWwMVohKigBFHuwvU1RhW9DiGMLB4Qvk3kL9Bs90MqgbIU4rKdKH7Y108LvcjGNzI92qIWrw/pwCzJ3id88Ahwm5Rbke8ZuVvMCR85rSlFM1rOAFP32hws9wmbj3RZAa7rc5z0uzg2/IZMQZOsweCxE8a4IoctwgMU394t" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_unused.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_unused.sv new file mode 100644 index 0000000000..af51a847ab --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_unused.sv @@ -0,0 +1,25 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module altera_emif_arch_fm_buf_unused ( + output logic o +); + timeunit 1ns; + timeprecision 1ps; + + assign o = 1'b0; +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm21Y3h4ZwmeCDLBi13DER8P/hE/05XIB+MP/tekkMHRc9fTpd07EtcbE+kKx+HhUC4VAUpq+6rJcdeYx9KymU9PVChpn2OMmtAq2PDxwE2Pvtf74Ig29FfLOCq2BK/7k7HjfqtVr/sqRiw8Jc6131zcHfbOam2soohRXzrz1NAn1zeypc7b7sPbSAvEk7ndfpjwLMeZSspCCFzSoSyQ6dvzYtlDVmeteHOTh3ATroJrmeUBFxGPDC4IXy9KLm5A4yB6uUEOJGrPudw4+X7AIJo92wAbvg8mNUEnR6E0UyBBQ4MSphh3wViQ3rdc1N3QZWufydLLwkiGprss+uAfxBrvUAv6DF+N/JyY1VVQ+4dN4Txi+O2SIDk1Ts9qPlMnsRpS5Y3LPbPd3V/oKm73IQwdObN2otvOzAc73VDTZmrJZO8bqL0E0IikLpCuP7TjjALgBOPWKxXNtL0GzyNtwjoObtBzoaB1SizhMC5vq1uqYX9qYDoJrHeGK12KwKNGPLpCWgi0quSmkfqJMWPhzdCTy8eXAWsYCc1mRLycDX3gekhOqjQkJtz92W/5FGw/wkxWpXmKL5u1ufs0H87Yb61u1RrO/whVOSRqhdMJJrwkGgVTcsnq2Po/NNJ1NaNKyWlEqZzxQgG+zk14hgBdxa+sdDOSp+o+lz2y1FdSWJJVQ1DCp8UwyypZd2boAAIoj9/nogzfp3Rq/mEg7CUdOfzwbkbb9SrYIG28ncvJWvoxDgoHiqmszxVN2hgV+0IMD8NfcteSZrbk1L+SKRfGGpgk" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_bufs.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_bufs.sv new file mode 100644 index 0000000000..fe63e7c796 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_bufs.sv @@ -0,0 +1,1288 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +module altera_emif_arch_fm_bufs #( + parameter PROTOCOL_ENUM = "", + parameter PINS_PER_LANE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter LANES_IN_RTL_TILES = 1, + parameter OCT_CONTROL_WIDTH = 1, + parameter DQS_BUS_MODE_ENUM = "", + parameter UNUSED_MEM_PINS_PINLOC = 10'b0000000000, + parameter UNUSED_DQS_BUSES_LANELOC = 10'b0000000000, + + // Definition of port widths for "mem" interface (auto-generated) + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_GNT_N_WIDTH = 1, + parameter PORT_MEM_REQ_N_WIDTH = 1, + parameter PORT_MEM_ERR_N_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + // Definition of parameters describing logical pin allocation + //AUTOGEN_BEGIN: Definition of memory port pinlocs + parameter PORT_MEM_CK_PINLOC = 10'b0000000000, + parameter PORT_MEM_CK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_A_PINLOC = 10'b0000000000, + parameter PORT_MEM_BA_PINLOC = 10'b0000000000, + parameter PORT_MEM_BG_PINLOC = 10'b0000000000, + parameter PORT_MEM_C_PINLOC = 10'b0000000000, + parameter PORT_MEM_CKE_PINLOC = 10'b0000000000, + parameter PORT_MEM_CS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RM_PINLOC = 10'b0000000000, + parameter PORT_MEM_ODT_PINLOC = 10'b0000000000, + parameter PORT_MEM_RAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WE_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RESET_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ACT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PAR_PINLOC = 10'b0000000000, + parameter PORT_MEM_CA_PINLOC = 10'b0000000000, + parameter PORT_MEM_REF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DOFF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK0_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK1_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CFG_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_AP_PINLOC = 10'b0000000000, + parameter PORT_MEM_AINV_PINLOC = 10'b0000000000, + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVB_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ALERT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PE_N_PINLOC = 10'b0000000000, + + parameter HPRX_CTLE_EN = "on", + parameter HPRX_OFFSET_CAL = "true", + + parameter PHY_CALIBRATED_OCT = 1, + parameter PHY_AC_CALIBRATED_OCT = 1, + parameter PHY_CK_CALIBRATED_OCT = 1, + parameter PHY_DATA_CALIBRATED_OCT = 1 +) ( + input logic [PINS_IN_RTL_TILES-1:0] l2b_data, + input logic [PINS_IN_RTL_TILES-1:0] l2b_oe, + input logic [PINS_IN_RTL_TILES-1:0] l2b_dtc, + output logic [PINS_IN_RTL_TILES-1:0] b2l_data, + output logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, + output logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, + + // Ports for "mem" interface + //AUTOGEN_BEGIN: Definition of memory ports + output logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + output logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + output logic [PORT_MEM_DK_WIDTH-1:0] mem_dk, + output logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n, + output logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka, + output logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n, + output logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb, + output logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n, + output logic [PORT_MEM_K_WIDTH-1:0] mem_k, + output logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n, + output logic [PORT_MEM_A_WIDTH-1:0] mem_a, + output logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + output logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + output logic [PORT_MEM_C_WIDTH-1:0] mem_c, + output logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke, + output logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n, + output logic [PORT_MEM_RM_WIDTH-1:0] mem_rm, + output logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + output logic [PORT_MEM_GNT_N_WIDTH-1:0] mem_gnt_n, + input logic [PORT_MEM_REQ_N_WIDTH-1:0] mem_req_n, + input logic [PORT_MEM_ERR_N_WIDTH-1:0] mem_err_n, + output logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n, + output logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n, + output logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n, + output logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n, + output logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n, + output logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + output logic [PORT_MEM_CA_WIDTH-1:0] mem_ca, + output logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n, + output logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n, + output logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n, + output logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n, + output logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n, + output logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n, + output logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n, + output logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n, + output logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n, + output logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n, + output logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n, + output logic [PORT_MEM_AP_WIDTH-1:0] mem_ap, + output logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv, + output logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + output logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n, + output logic [PORT_MEM_D_WIDTH-1:0] mem_d, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa, + inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb, + inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva, + inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb, + input logic [PORT_MEM_Q_WIDTH-1:0] mem_q, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n, + input logic [PORT_MEM_QK_WIDTH-1:0] mem_qk, + input logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n, + input logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka, + input logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n, + input logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb, + input logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n, + input logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq, + input logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n, + input logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n, + + input logic oct_rzqin, + input logic oct_termin, + output logic oct_rzqin2ter +); + timeunit 1ns; + timeprecision 1ps; + + assign mem_gnt_n = '1; + + assign {mem_ck_bidir, mem_ck_bidir_n} = '0; + + generate + genvar port_i; + + for (port_i = 0; port_i < `_get_pin_count(UNUSED_MEM_PINS_PINLOC); ++port_i) + begin : unused_pin + altera_emif_arch_fm_buf_unused ub (.o(b2l_data[`_get_pin_index(UNUSED_MEM_PINS_PINLOC, port_i)])); + end + + for (port_i = 0; port_i < `_get_pin_count(UNUSED_DQS_BUSES_LANELOC); ++port_i) + begin : unused_dqs_bus + altera_emif_arch_fm_buf_unused ub0 (.o(b2t_dqs[`_get_pin_index(UNUSED_DQS_BUSES_LANELOC, port_i)])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2t_dqsb[`_get_pin_index(UNUSED_DQS_BUSES_LANELOC, port_i)])); + end + + if (`_get_pin_count(PORT_MEM_CK_PINLOC) != 0) begin : gen_mem_ck + for (port_i = 0; port_i < PORT_MEM_CK_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_CK_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CK_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_CK_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ck[port_i]), + .obar(mem_ck_n[port_i]), + .oein(l2b_oe[`_get_pin_index(PORT_MEM_CK_PINLOC, port_i)]), + .oeinb(l2b_oe[`_get_pin_index(PORT_MEM_CK_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_CK_PINLOC, port_i)])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_CK_N_PINLOC, port_i)])); + end + end else begin : no_mem_ck + assign {mem_ck, mem_ck_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_DK_PINLOC) != 0) begin : gen_mem_dk + for (port_i = 0; port_i < PORT_MEM_DK_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DK_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_DK_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_dk[port_i]), + .obar(mem_dk_n[port_i]), + .oein(l2b_oe[`_get_pin_index(PORT_MEM_DK_PINLOC, port_i)]), + .oeinb(l2b_oe[`_get_pin_index(PORT_MEM_DK_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_DK_PINLOC, port_i)])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DK_N_PINLOC, port_i)])); + end + end else begin : no_mem_dk + assign {mem_dk, mem_dk_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_DKA_PINLOC) != 0) begin : gen_mem_dka + for (port_i = 0; port_i < PORT_MEM_DKA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DKA_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_DKA_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_dka[port_i]), + .obar(mem_dka_n[port_i]), + .oein(l2b_oe[`_get_pin_index(PORT_MEM_DKA_PINLOC, port_i)]), + .oeinb(l2b_oe[`_get_pin_index(PORT_MEM_DKA_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKA_PINLOC, port_i)])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKA_N_PINLOC, port_i)])); + end + end else begin : no_mem_dka + assign {mem_dka, mem_dka_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_DKB_PINLOC) != 0) begin : gen_mem_dkb + for (port_i = 0; port_i < PORT_MEM_DKB_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DKB_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_DKB_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_dkb[port_i]), + .obar(mem_dkb_n[port_i]), + .oein(l2b_oe[`_get_pin_index(PORT_MEM_DKB_PINLOC, port_i)]), + .oeinb(l2b_oe[`_get_pin_index(PORT_MEM_DKB_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKB_PINLOC, port_i)])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKB_N_PINLOC, port_i)])); + end + end else begin : no_mem_dkb + assign {mem_dkb, mem_dkb_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_K_PINLOC) != 0) begin : gen_mem_k + for (port_i = 0; port_i < PORT_MEM_K_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_CK_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_K_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_K_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_k[port_i]), + .obar(mem_k_n[port_i]), + .oein(l2b_oe[`_get_pin_index(PORT_MEM_K_PINLOC, port_i)]), + .oeinb(l2b_oe[`_get_pin_index(PORT_MEM_K_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_K_PINLOC, port_i)])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_K_N_PINLOC, port_i)])); + end + end else begin : no_mem_k + assign {mem_k, mem_k_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_A_PINLOC) != 0) begin : gen_mem_a + for (port_i = 0; port_i < PORT_MEM_A_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_A_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_a[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_A_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_A_PINLOC, port_i)])); + end + end else begin : no_mem_a + assign mem_a = '0; + end + + if (`_get_pin_count(PORT_MEM_BA_PINLOC) != 0) begin : gen_mem_ba + for (port_i = 0; port_i < PORT_MEM_BA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_BA_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ba[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_BA_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_BA_PINLOC, port_i)])); + end + end else begin : no_mem_ba + assign mem_ba = '0; + end + + if (`_get_pin_count(PORT_MEM_BG_PINLOC) != 0) begin : gen_mem_bg + for (port_i = 0; port_i < PORT_MEM_BG_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_BG_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_bg[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_BG_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_BG_PINLOC, port_i)])); + end + end else begin : no_mem_bg + assign mem_bg = '0; + end + + if (`_get_pin_count(PORT_MEM_C_PINLOC) != 0) begin : gen_mem_c + for (port_i = 0; port_i < PORT_MEM_C_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_C_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_c[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_C_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_C_PINLOC, port_i)])); + end + end else begin : no_mem_c + assign mem_c = '0; + end + + if (`_get_pin_count(PORT_MEM_CKE_PINLOC) != 0) begin : gen_mem_cke + for (port_i = 0; port_i < PORT_MEM_CKE_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CKE_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_cke[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_CKE_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CKE_PINLOC, port_i)])); + end + end else begin : no_mem_cke + assign mem_cke = '0; + end + + if (`_get_pin_count(PORT_MEM_CS_N_PINLOC) != 0) begin : gen_mem_cs_n + for (port_i = 0; port_i < PORT_MEM_CS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CS_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_cs_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_CS_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CS_N_PINLOC, port_i)])); + end + end else begin : no_mem_cs_n + assign mem_cs_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RM_PINLOC) != 0) begin : gen_mem_rm + for (port_i = 0; port_i < PORT_MEM_RM_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RM_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_rm[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_RM_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RM_PINLOC, port_i)])); + end + end else begin : no_mem_rm + assign mem_rm = '1; + end + + if (`_get_pin_count(PORT_MEM_ODT_PINLOC) != 0) begin : gen_mem_odt + for (port_i = 0; port_i < PORT_MEM_ODT_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_ODT_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_odt[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_ODT_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_ODT_PINLOC, port_i)])); + end + end else begin : no_mem_odt + assign mem_odt = '0; + end + + if (`_get_pin_count(PORT_MEM_RAS_N_PINLOC) != 0) begin : gen_mem_ras_n + for (port_i = 0; port_i < PORT_MEM_RAS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RAS_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ras_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_RAS_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RAS_N_PINLOC, port_i)])); + end + end else begin : no_mem_ras_n + assign mem_ras_n = '1; + end + + if (`_get_pin_count(PORT_MEM_CAS_N_PINLOC) != 0) begin : gen_mem_cas_n + for (port_i = 0; port_i < PORT_MEM_CAS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CAS_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_cas_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_CAS_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CAS_N_PINLOC, port_i)])); + end + end else begin : no_mem_cas_n + assign mem_cas_n = '1; + end + + if (`_get_pin_count(PORT_MEM_WE_N_PINLOC) != 0) begin : gen_mem_we_n + for (port_i = 0; port_i < PORT_MEM_WE_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_WE_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_we_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_WE_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_WE_N_PINLOC, port_i)])); + end + end else begin : no_mem_we_n + assign mem_we_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RESET_N_PINLOC) != 0) begin : gen_mem_reset_n + for (port_i = 0; port_i < PORT_MEM_RESET_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(0) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RESET_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_reset_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_RESET_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RESET_N_PINLOC, port_i)])); + end + end else begin : no_mem_reset_n + assign mem_reset_n = '1; + end + + if (`_get_pin_count(PORT_MEM_ACT_N_PINLOC) != 0) begin : gen_mem_act_n + for (port_i = 0; port_i < PORT_MEM_ACT_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_ACT_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_act_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_ACT_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_ACT_N_PINLOC, port_i)])); + end + end else begin : no_mem_act_n + assign mem_act_n = '1; + end + + if (`_get_pin_count(PORT_MEM_PAR_PINLOC) != 0) begin : gen_mem_par + for (port_i = 0; port_i < PORT_MEM_PAR_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_PAR_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_par[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_PAR_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_PAR_PINLOC, port_i)])); + end + end else begin : no_mem_par + assign mem_par = '0; + end + + if (`_get_pin_count(PORT_MEM_CA_PINLOC) != 0) begin : gen_mem_ca + for (port_i = 0; port_i < PORT_MEM_CA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CA_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ca[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_CA_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CA_PINLOC, port_i)])); + end + end else begin : no_mem_ca + assign mem_ca = '0; + end + + if (`_get_pin_count(PORT_MEM_REF_N_PINLOC) != 0) begin : gen_mem_ref_n + for (port_i = 0; port_i < PORT_MEM_REF_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_REF_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ref_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_REF_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_REF_N_PINLOC, port_i)])); + end + end else begin : no_mem_ref_n + assign mem_ref_n = '1; + end + + if (`_get_pin_count(PORT_MEM_WPS_N_PINLOC) != 0) begin : gen_mem_wps_n + for (port_i = 0; port_i < PORT_MEM_WPS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_WPS_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_wps_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_WPS_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_WPS_N_PINLOC, port_i)])); + end + end else begin : no_mem_wps_n + assign mem_wps_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RPS_N_PINLOC) != 0) begin : gen_mem_rps_n + for (port_i = 0; port_i < PORT_MEM_RPS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RPS_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_rps_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_RPS_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RPS_N_PINLOC, port_i)])); + end + end else begin : no_mem_rps_n + assign mem_rps_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0) begin : gen_mem_lda_n + for (port_i = 0; port_i < PORT_MEM_LDA_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LDA_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_lda_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_LDA_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LDA_N_PINLOC, port_i)])); + end + end else begin : no_mem_lda_n + assign mem_lda_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : gen_mem_ldb_n + for (port_i = 0; port_i < PORT_MEM_LDB_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LDB_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ldb_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_LDB_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LDB_N_PINLOC, port_i)])); + end + end else begin : no_mem_ldb_n + assign mem_ldb_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0) begin : gen_mem_rwa_n + for (port_i = 0; port_i < PORT_MEM_RWA_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RWA_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_rwa_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_RWA_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RWA_N_PINLOC, port_i)])); + end + end else begin : no_mem_rwa_n + assign mem_rwa_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : gen_mem_rwb_n + for (port_i = 0; port_i < PORT_MEM_RWB_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RWB_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_rwb_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_RWB_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RWB_N_PINLOC, port_i)])); + end + end else begin : no_mem_rwb_n + assign mem_rwb_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LBK0_N_PINLOC) != 0) begin : gen_mem_lbk0_n + for (port_i = 0; port_i < PORT_MEM_LBK0_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LBK0_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_lbk0_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_LBK0_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LBK0_N_PINLOC, port_i)])); + end + end else begin : no_mem_lbk0_n + assign mem_lbk0_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LBK1_N_PINLOC) != 0) begin : gen_mem_lbk1_n + for (port_i = 0; port_i < PORT_MEM_LBK1_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LBK1_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_lbk1_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_LBK1_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LBK1_N_PINLOC, port_i)])); + end + end else begin : no_mem_lbk1_n + assign mem_lbk1_n = '1; + end + + if (`_get_pin_count(PORT_MEM_AP_PINLOC) != 0) begin : gen_mem_ap + for (port_i = 0; port_i < PORT_MEM_AP_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_AP_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ap[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_AP_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_AP_PINLOC, port_i)])); + end + end else begin : no_mem_ap + assign mem_ap = '1; + end + + if (`_get_pin_count(PORT_MEM_AINV_PINLOC) != 0) begin : gen_mem_ainv + for (port_i = 0; port_i < PORT_MEM_AINV_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_AINV_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_ainv[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_AINV_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_AINV_PINLOC, port_i)])); + end + end else begin : no_mem_ainv + assign mem_ainv = '1; + end + + if (`_get_pin_count(PORT_MEM_CFG_N_PINLOC) != 0) begin : gen_mem_cfg_n + for (port_i = 0; port_i < PORT_MEM_CFG_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CFG_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_cfg_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_CFG_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CFG_N_PINLOC, port_i)])); + end + end else begin : no_mem_cfg_n + assign mem_cfg_n = '1; + end + + if (`_get_pin_count(PORT_MEM_DOFF_N_PINLOC) != 0) begin : gen_mem_doff_n + for (port_i = 0; port_i < PORT_MEM_DOFF_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DOFF_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_doff_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_DOFF_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_DOFF_N_PINLOC, port_i)])); + end + end else begin : no_mem_doff_n + assign mem_doff_n = '1; + end + + if (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0) begin : gen_mem_dm + for (port_i = 0; port_i < PORT_MEM_DM_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DM_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_dm[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_DM_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_DM_PINLOC, port_i)])); + end + end else begin : no_mem_dm + assign mem_dm = '0; + end + + if (`_get_pin_count(PORT_MEM_BWS_N_PINLOC) != 0) begin : gen_mem_bws_n + for (port_i = 0; port_i < PORT_MEM_BWS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_BWS_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_bws_n[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_BWS_N_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_BWS_N_PINLOC, port_i)])); + end + end else begin : no_mem_bws_n + assign mem_bws_n = '1; + end + + if (`_get_pin_count(PORT_MEM_D_PINLOC) != 0) begin : gen_mem_d + for (port_i = 0; port_i < PORT_MEM_D_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_D_PINLOC, port_i)]), + .oct_termin(oct_termin), + .o(mem_d[port_i]), + .oe(l2b_oe[`_get_pin_index(PORT_MEM_D_PINLOC, port_i)]) + ); + + altera_emif_arch_fm_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_D_PINLOC, port_i)])); + end + end else begin : no_mem_d + assign mem_d = '0; + end + + if (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0) begin : gen_mem_dq + for (port_i = 0; port_i < PORT_MEM_DQ_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dq[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]) + ); + end + end else begin : no_mem_dq + assign mem_dq = '0; + end + + if (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0) begin : gen_mem_dbi_n + for (port_i = 0; port_i < PORT_MEM_DBI_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dbi_n[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]) + ); + end + end else begin : no_mem_dbi_n + assign mem_dbi_n = '0; + end + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0) begin : gen_mem_dqa + for (port_i = 0; port_i < PORT_MEM_DQA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dqa[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]) + ); + end + end else begin : no_mem_dqa + assign mem_dqa = '0; + end + + if (`_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : gen_mem_dqb + for (port_i = 0; port_i < PORT_MEM_DQB_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dqb[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]) + ); + end + end else begin : no_mem_dqb + assign mem_dqb = '0; + end + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : gen_mem_dinva + for (port_i = 0; port_i < PORT_MEM_DINVA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dinva[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]) + ); + end + end else begin : no_mem_dinva + assign mem_dinva = '0; + end + + if (`_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0) begin : gen_mem_dinvb + for (port_i = 0; port_i < PORT_MEM_DINVB_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dinvb[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]) + ); + end + end else begin : no_mem_dinvb + assign mem_dinvb = '0; + end + + if (`_get_pin_count(PORT_MEM_Q_PINLOC) != 0) begin : gen_mem_q + for (port_i = 0; port_i < PORT_MEM_Q_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_q[port_i]), + .oct_termin(oct_termin), + .o(b2l_data[`_get_pin_index(PORT_MEM_Q_PINLOC, port_i)]) + ); + end + end + + if (`_get_pin_count(PORT_MEM_ALERT_N_PINLOC) != 0) begin : gen_mem_alert_n + for (port_i = 0; port_i < PORT_MEM_ALERT_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT((PROTOCOL_ENUM == "PROTOCOL_DDR4") ? 0 : PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_alert_n[port_i]), + .oct_termin(oct_termin), + .o(b2l_data[`_get_pin_index(PORT_MEM_ALERT_N_PINLOC, port_i)]) + ); + end + end + + if (`_get_pin_count(PORT_MEM_PE_N_PINLOC) != 0) begin : gen_mem_pe_n + for (port_i = 0; port_i < PORT_MEM_PE_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_fm_buf_udir_se_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_pe_n[port_i]), + .oct_termin(oct_termin), + .o(b2l_data[`_get_pin_index(PORT_MEM_PE_N_PINLOC, port_i)]) + ); + end + end + + if (PHY_CALIBRATED_OCT == 1) begin : gen_rzqin + tennm_io_ibuf ibuf( + .i(oct_rzqin), + .o(oct_rzqin2ter), + .term_in(/*open*/), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .ibar(), + .dynamicterminationcontrol() + ); + end + + + if (`_get_pin_count(PORT_MEM_DQS_PINLOC) != 0) begin : gen_mem_dqs + for (port_i = 0; port_i < PORT_MEM_DQS_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_fm_buf_bdir_df # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .HPRX_CTLE_EN(HPRX_CTLE_EN), + .HPRX_OFFSET_CAL(HPRX_OFFSET_CAL), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dqs[port_i]), + .iobar(mem_dqs_n[port_i]), + .ibuf_o(sig), + .oct_termin(oct_termin), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)]), + .obuf_ibar(l2b_data[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)]), + .obuf_oebar(l2b_oe[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)]), + .obuf_dtcbar(l2b_dtc[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)]) + ); + + if (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") begin : gen_x4 + if ((`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) % PINS_PER_LANE) < (PINS_PER_LANE / 2)) begin : a + assign b2t_dqs[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) / PINS_PER_LANE] = sig; + end else begin : b + assign b2t_dqsb[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) / PINS_PER_LANE] = sig; + end + end else begin : gen_x8 + assign b2t_dqs[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) / PINS_PER_LANE] = sig; + altera_emif_arch_fm_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i) / PINS_PER_LANE])); + end + + assign b2l_data[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)] = sig; + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)])); + end + end else begin : no_mem_dqs + assign {mem_dqs, mem_dqs_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_QK_PINLOC) != 0) begin : gen_mem_qk + for (port_i = 0; port_i < PORT_MEM_QK_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_fm_buf_udir_df_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_qk[port_i]), + .ibar(mem_qk_n[port_i]), + .oct_termin(oct_termin), + .o(sig) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_QK_PINLOC, port_i) / PINS_PER_LANE] = sig; + assign b2l_data[`_get_pin_index(PORT_MEM_QK_PINLOC, port_i)] = sig; + + altera_emif_arch_fm_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_QK_N_PINLOC, port_i) / PINS_PER_LANE])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_QK_N_PINLOC, port_i)])); + end + end + + if (`_get_pin_count(PORT_MEM_QKA_PINLOC) != 0) begin : gen_mem_qka + for (port_i = 0; port_i < PORT_MEM_QKA_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_fm_buf_udir_df_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_qka[port_i]), + .ibar(mem_qka_n[port_i]), + .oct_termin(oct_termin), + .o(sig) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_QKA_PINLOC, port_i) / PINS_PER_LANE] = sig; + assign b2l_data[`_get_pin_index(PORT_MEM_QKA_PINLOC, port_i)] = sig; + + altera_emif_arch_fm_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_QKA_N_PINLOC, port_i) / PINS_PER_LANE])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_QKA_N_PINLOC, port_i)])); + end + end + + if (`_get_pin_count(PORT_MEM_QKB_PINLOC) != 0) begin : gen_mem_qkb + for (port_i = 0; port_i < PORT_MEM_QKB_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_fm_buf_udir_df_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_qkb_n[port_i]), + .ibar(mem_qkb[port_i]), + .oct_termin(oct_termin), + .o(sig) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_QKB_PINLOC, port_i) / PINS_PER_LANE] = sig; + assign b2l_data[`_get_pin_index(PORT_MEM_QKB_PINLOC, port_i)] = sig; + + altera_emif_arch_fm_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_QKB_N_PINLOC, port_i) / PINS_PER_LANE])); + altera_emif_arch_fm_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_QKB_N_PINLOC, port_i)])); + end + end + + if (`_get_pin_count(PORT_MEM_CQ_PINLOC) != 0) begin : gen_mem_cq + for (port_i = 0; port_i < PORT_MEM_CQ_WIDTH; ++port_i) + begin : inst + logic sig_p; + logic sig_n; + + altera_emif_arch_fm_buf_udir_cp_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_cq[port_i]), + .ibar(mem_cq_n[port_i]), + .oct_termin(oct_termin), + .o(sig_p), + .obar(sig_n) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_CQ_PINLOC, port_i) / PINS_PER_LANE] = sig_p; + assign b2t_dqsb[`_get_pin_index(PORT_MEM_CQ_N_PINLOC, port_i) / PINS_PER_LANE] = sig_n; + + assign b2l_data[`_get_pin_index(PORT_MEM_CQ_PINLOC, port_i)] = sig_p; + assign b2l_data[`_get_pin_index(PORT_MEM_CQ_N_PINLOC, port_i)] = sig_n; + end + end + endgenerate +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm3P/V/ksQ1NvMZ8DoAgDBoSWkaCKzF+3NC5CldVhK4x1C9Cj91JjpW5k3SFrFtP3B5QM3leEAFr7oJ4Tsoy8OURvKdW5eXC/9FsmeI75gZquuuxG+oK+wsk5puPVqlFAdwL/lQs2Kh1Et/ylUSc0yvtDZknRe0k5yC8Vt3i/Y4rK//WPoRCntkL1v9rhqa/fIstBoWrZZLiFx2UlTLxIXGfjEijxFooPYO5JV+GwoksCCT9VbVC9INF2AYVzGc434zbcw8vDflX7UKDiu7oRYtuq1ziAeHvLZbXIc5Rc0NthlZDPtr0qR+6naQnWoAmWIX/yBfY4Gqckv5+QtTLGeT5AZgo02tFEyvq1MwVxML6A02aZH5h94aPj3CqWerpuHOUXYvF9ekyA/PypcKFd6A/ahslf+fjsFZ6V4S6m3zZdEi6DSEKX5pGI5+wjQFwWxJtkEq+tNCwcSu5P3KMfPDg0Qmmb9oLMhU9Nksyfm4uWNM0JjIuPUnb34fX7mDAc2VM4Ri1eGuv4KCvYQue7Scd8HI+8PzW5utz5tBk7j6KNA9K6+URiS4vNxquxRvxecpcsrsJIL1R3TtCVhOVl8oAg9UtOiORtEtK2FehgLVesH17ruoiwSx2qE+CDf1Tea95iT1Za+18aKI6RhqAExFCTg5DK4YAS4vHPAdi6C/7dgxsxPzT58Db87fcVde49aNZtULF2K3qgGu6uttLLXZs+59PiKKCGC6DSUsmizfnPMdX5pi4cG0E6riE/E6J4sW3TctEmP3KmjCYLqSet75q" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_cal_counter.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_cal_counter.sv new file mode 100644 index 0000000000..17ef6ada3e --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_cal_counter.sv @@ -0,0 +1,126 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +module altera_emif_arch_fm_cal_counter # ( + parameter IS_HPS = 0 +) ( + input logic pll_ref_clk_int, + input logic local_reset_req_int, + input logic afi_cal_in_progress +); + timeunit 1ps; + timeprecision 1ps; + + typedef enum { + INIT, + IDLE, + COUNT_CAL, + STOP + } counter_state_t; + + logic done; + logic [31:0] clk_counter; + + generate + if (IS_HPS == 0) begin : non_hps + logic cal_done; + logic reset_req_sync; + logic cal_in_progress_sync; + + altera_std_synchronizer_nocut + inst_sync_reset_n ( + .clk (pll_ref_clk_int), + .reset_n (1'b1), + .din (local_reset_req_int), + .dout (reset_req_sync) + ); + + altera_std_synchronizer_nocut + inst_sync_cal_in_progress ( + .clk (pll_ref_clk_int), + .reset_n (1'b1), + .din (afi_cal_in_progress), + .dout (cal_in_progress_sync) + ); + + counter_state_t counter_state /* synthesis ignore_power_up */; + + assign done = ((counter_state == STOP) ? 1'b1 : 1'b0); + + always_ff @(posedge pll_ref_clk_int) begin + if(reset_req_sync == 1'b1) begin + counter_state <= INIT; + end + else begin + case(counter_state) + INIT: + begin + clk_counter <= 32'h0; + counter_state <= IDLE; + end + + IDLE: + begin + if (cal_in_progress_sync == 1'b1) + begin + counter_state <= COUNT_CAL; + end + end + + COUNT_CAL: + begin + clk_counter[31:0] <= clk_counter[31:0] + 32'h0000_0001; + + if (cal_in_progress_sync == 1'b0) + begin + counter_state <= STOP; + end + end + + STOP: + begin + counter_state <= STOP; + end + + default: + begin + counter_state <= INIT; + end + endcase + end + end + end else begin : hps + assign done = 1'b1; + assign clk_counter = '0; + end + endgenerate + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALC"), + .probe_width (33), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_counter_issp ( + .probe ({done, clk_counter[31:0]}) + ); +`endif + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm3ajnRlCoTycdS5rLOAtZ6M6huxrgTizglD8CjFQHox2DR3mB7yrrtaKHIjqDW2jh+v84NRIUDYBdKhTW51/7O2DZsh64KUeoDc53EsrQLtn2yLnMIoCa9vcO9HjOLLTJBkJZAwMWlCwM6ei3SJGHwjp1fMp8oGysL/awCnW1Mpi+mWbH4Mr/HvaRj5xN29UVZCCwSlV4hyIdsy3K7ag/iO6ljXQEHSyRPjq0ofMN2NFNLDRFKZT4eE+3k+5pKTbSmSRZGgpAUnbw6sWJ2Fa3NpXHdRnvr4uq9ylg4Pz0RJ5+C7yu4kJBrQm2Vt8h5rmMVGp9cGn9Ub17Odi9OZLJfyAB5u+SkBp6JPOSO/KZrARP1hkWsUPqGyu7WX0YGkVGDOX34vNFFyd5E0wZCI9gkCLYieq7t5SzhXbvIKKALvlMcOxpWDPv48I7Q50qRl7LbKmM5C+Bopp4TT/UDW/3woKHg3EK9QbeqUBaAzlqPHo6r8Fbd3cgLXBuYytFja6jlPohYMJUNR1xilbJZOCE1Mj+IqYKX5UpSAZtKSsgDvsTYihdrKVj74NEExrgYleQ4t+Q2zOb7YSGRC3CML0xFA9H6wuCB+R6s1uAt83gYKVBIDcRJ6ZeAtygjgh9DDa9XrYejBayHUmqn6IB0dpltElm/nD+x7XRI6JFKetcLKOgMTxykFiWFDCLY20NopPEdPKj8cL+kGrEQAGk8JvHDraqlwCerSMeTnmOy595DvdgK3hJS221B/oP9xAPlBTBfsl9pQsmaPhhdzUD1t4FYI" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_core_clks_rsts.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_core_clks_rsts.sv new file mode 100644 index 0000000000..2c2bf8f2b0 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_core_clks_rsts.sv @@ -0,0 +1,631 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module handles the creation and wiring of the core clock/reset signals. +// +/////////////////////////////////////////////////////////////////////////////// + +// altera message_off 10036 + + module altera_emif_arch_fm_core_clks_rsts #( + parameter PHY_CONFIG_ENUM = "", + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter C2P_P2C_CLK_RATIO = 1, + parameter USER_CLK_RATIO = 1, + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 32, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 32, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 1, + parameter DIAG_SYNTH_FOR_SIM = 1, + parameter PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH = 1 +) ( + // For a master interface, the PLL ref clock and the global reset signal + // come from an external source from user logic, via the following ports. + // For slave interfaces, they come from the master via the sharing interface. + // The connectivity ensures that all interfaces in a master/slave + // configuration share the same ref clock and global reset, which is + // one of the requirements for core-clock sharing. + // pll_ref_clk_int is the actual PLL ref clock signal that will be used by the + // reset of the IP. For a master interface it is equivalent to pll_ref_clk. + // For a slave interface it is equivalent to the pll_ref_clk signal of the master. + input logic pll_ref_clk, + output logic pll_ref_clk_int, + + // For a master interface, core clocks come from the clock phase alignment + // block of the current interface, via the following ports. Note that the + // CPA block also expects feedback signals after the clock signals have + // propagated through core clock networks. + // For slave interfaces, the core clock signals come from the master + // via the sharing interface. + input logic [1:0] core_clks_from_cpa_pri, + input logic [1:0] core_clks_locked_cpa_pri, + output logic [1:0] core_clks_fb_to_cpa_pri, + + input logic [1:0] core_clks_from_cpa_sec, + input logic [1:0] core_clks_locked_cpa_sec, + output logic [1:0] core_clks_fb_to_cpa_sec, + + // Async reset_n signal from sequencer to force core clock domain to be in reset. + // This is needed by local_reset_req as well as by DCD calibration (which can + // destabilize the CPA output clocks. + input logic seq2core_reset_n, + + // PLL lock signal + input logic pll_locked, + + // PLL c-counters + input logic [8:0] pll_c_counters, + + // Reset request signal. + // local_reset_req_int is the actual reset request signal that will be + // used internally by the rest of the IP. For a master interface it + // is equivalent to local_reset_req. For a slave interface it is + // equivalent to the local_reset_req signal of the master. + input logic local_reset_req, + output logic local_reset_req_int, + + // The following is the master/slave sharing interfaces. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // The following are all the possible core clock/reset signals. + // afi_* only exists in PHY-only mode (or if soft controller is used). + // emif_usr_* only exists if hard memory controller is used. + output logic afi_clk, + output logic afi_half_clk, + output logic afi_reset_n, + + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n, + + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic emif_usr_reset_n_sec, + + // DFT + output logic [PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + // This is the length of the core reset synchronizer chain. At a high-level, + // we de-assert reset whenever the core clock is stable (as indicated by signals such + // as CPA lock and DCC stable). + // The chain actually has two purposes: reset synchronization (which typically requires + // no more than 3 FFs for reasonable MTBF), and delaying reset deassertion enough to + // satisfy the following two requirements: + // 1) It is set higher than the length of the reset chain + // in the periphery (5+), to avoid the core from getting out of reset + // earlier than the hard PHY/sequencer/controller. + // This is for extra safety, but isn't strictly necessary, because + // soft logic must either wait for the hard controller's assertion of + // the ready signal, or, if the hard controller is bypassed, + // for the sequencer to assert the afi_cal_success, prior to accessing + // the hard circuitries. + // 2) It is set high enough for the reset state to propagate to all Hyper-register + // stages in the IP. Since Hyper-registers can't be reset asynchronously, + // they are carefully designed such that they'll naturally reach the reset + // state with enough number of clock cycles, prior to system reset + // deassertion occurs. For this purpose we reserve 16 FFs. + // 3) The async reset to the reset synchronizer has MCP setup=7, hold=6 to + // relax timing. This means the async reset arrival time has a max variance + // of 7 cycles, which means the output of synchronizer FF 0..6 can all be + // metastable. For this purpose we reserve 7 FFs + localparam CPA_RESET_SYNC_LENGTH = 27; + + // Reset synchronizer chain length for PLL-based core clocks + // The async reset to the reset synchronizer has MCP setup=7, hold=6 to + // relax timing. This means the async reset arrival time has a max variance + // of 7 cycles, which means the output of synchronizer FF 0..6 can all be + // metastable. For safety set sychronzier length to be 7+3=10. + localparam PLL_RESET_SYNC_LENGTH = 10; + + // Data synchronizer chain length for local_reset_req + localparam LOCAL_RESET_REQ_SYNC_LENGTH = 3; + + ///////////////////////////////////////////////////////////// + // Get signals to/from the master/slave sharing interface. + logic local_reset_req_sync; + logic pll_locked_int; + logic seq2core_reset_n_int; + logic counter_lock; + logic cpa_lock_pri; + logic cpa_lock_sec; + logic async_reset_n_pri; + logic async_reset_n_sec; + logic issp_reset_n; + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("TGR"), + .probe_width (0), + .source_width (1), + .source_initial_value ("1"), + .enable_metastability ("NO") + ) core_reset_n_issp ( + .source (issp_reset_n) + ); +`else + assign issp_reset_n = 1'b1; +`endif + + assign async_reset_n_pri = (DIAG_USE_CPA_LOCK ? cpa_lock_pri : counter_lock) & seq2core_reset_n_int & issp_reset_n; + assign async_reset_n_sec = (DIAG_USE_CPA_LOCK ? cpa_lock_sec : counter_lock) & seq2core_reset_n_int & issp_reset_n; + + logic pll_ref_clk_slave_in; + logic pll_locked_slave_in; + logic cpa_lock_pri_slave_in; + logic cpa_lock_sec_slave_in; + logic local_reset_req_slave_in; + logic seq2core_reset_n_slave_in; + logic afi_clk_slave_in; + logic afi_half_clk_slave_in; + logic afi_reset_n_pre_reg_slave_in; + logic afi_reset_n_pre_reg; + logic counter_lock_slave_in; + logic emif_usr_clk_slave_in; + logic emif_usr_half_clk_slave_in; + logic emif_usr_reset_n_pri_pre_reg_slave_in; + logic emif_usr_reset_n_pri_pre_reg; + logic emif_usr_clk_sec_slave_in; + logic emif_usr_half_clk_sec_slave_in; + logic emif_usr_reset_n_sec_pre_reg_slave_in; + logic emif_usr_reset_n_sec_pre_reg; + + + ///////////////////////////////////////////////////////////// + // Generate connectivity for PLL ref clk and reset. + generate + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : slave + assign pll_ref_clk_int = pll_ref_clk_slave_in; + assign pll_locked_int = pll_locked_slave_in; + assign local_reset_req_int = local_reset_req_slave_in; + assign seq2core_reset_n_int = seq2core_reset_n_slave_in; + + assign pll_ref_clk_slave_in = clks_sharing_slave_in[0]; + assign pll_locked_slave_in = clks_sharing_slave_in[1]; + assign seq2core_reset_n_slave_in = clks_sharing_slave_in[2]; + assign local_reset_req_slave_in = clks_sharing_slave_in[3]; + assign cpa_lock_pri_slave_in = clks_sharing_slave_in[4]; + assign cpa_lock_sec_slave_in = clks_sharing_slave_in[5]; + assign counter_lock_slave_in = clks_sharing_slave_in[6]; + assign afi_clk_slave_in = clks_sharing_slave_in[7]; + assign afi_half_clk_slave_in = clks_sharing_slave_in[8]; + assign afi_reset_n_pre_reg_slave_in = clks_sharing_slave_in[9]; + assign emif_usr_clk_slave_in = clks_sharing_slave_in[10]; + assign emif_usr_half_clk_slave_in = clks_sharing_slave_in[11]; + assign emif_usr_reset_n_pri_pre_reg_slave_in = clks_sharing_slave_in[12]; + assign emif_usr_clk_sec_slave_in = clks_sharing_slave_in[13]; + assign emif_usr_half_clk_sec_slave_in = clks_sharing_slave_in[14]; + assign emif_usr_reset_n_sec_pre_reg_slave_in = clks_sharing_slave_in[15]; + + assign clks_sharing_master_out = '0; + end else + begin : master + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PALP"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cpa_lock_pri_issp ( + .probe (cpa_lock_pri) + ); + + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PALS"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cpa_lock_sec_issp ( + .probe (cpa_lock_sec) + ); +`endif + + assign local_reset_req_int = local_reset_req_sync; + assign pll_ref_clk_int = pll_ref_clk; + assign pll_locked_int = pll_locked; + assign seq2core_reset_n_int = seq2core_reset_n; + + assign clks_sharing_master_out[0] = pll_ref_clk_int; + assign clks_sharing_master_out[1] = pll_locked_int; + assign clks_sharing_master_out[2] = seq2core_reset_n_int; + assign clks_sharing_master_out[3] = local_reset_req_int; + assign clks_sharing_master_out[4] = cpa_lock_pri; + assign clks_sharing_master_out[5] = cpa_lock_sec; + assign clks_sharing_master_out[6] = counter_lock; + assign clks_sharing_master_out[7] = afi_clk; + assign clks_sharing_master_out[8] = afi_half_clk; + assign clks_sharing_master_out[9] = afi_reset_n_pre_reg; + assign clks_sharing_master_out[10] = emif_usr_clk; + assign clks_sharing_master_out[11] = emif_usr_half_clk; + assign clks_sharing_master_out[12] = emif_usr_reset_n_pri_pre_reg; + assign clks_sharing_master_out[13] = emif_usr_clk_sec; + assign clks_sharing_master_out[14] = emif_usr_half_clk_sec; + assign clks_sharing_master_out[15] = emif_usr_reset_n_sec_pre_reg; + + assign clks_sharing_master_out[PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:16] = '0; + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate core clock lock signal if CPA lock isn't used + generate + if (DIAG_USE_CPA_LOCK) + begin : use_cpa_lock + assign counter_lock = 1'b0; + end + else + begin : use_counter_lock + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : counter_lock_gen_slave + assign counter_lock = counter_lock_slave_in; + end else + begin : counter_lock_gen_master + + // Synchronize PLL lock signal to PLL ref clock domain. + // This may not be necessary but we do it for extra safety. + logic pll_ref_clk_reset_n; + logic pll_ref_clk_reset_n_sync_r; + logic pll_ref_clk_reset_n_sync_rr; + logic pll_ref_clk_reset_n_sync_rrr; + + assign pll_ref_clk_reset_n = pll_ref_clk_reset_n_sync_rrr; + + always_ff @(posedge pll_ref_clk_int or negedge pll_locked_int) begin + if (~pll_locked_int) begin + pll_ref_clk_reset_n_sync_r <= 1'b0; + pll_ref_clk_reset_n_sync_rr <= 1'b0; + pll_ref_clk_reset_n_sync_rrr <= 1'b0; + end else begin + pll_ref_clk_reset_n_sync_r <= 1'b1; + pll_ref_clk_reset_n_sync_rr <= pll_ref_clk_reset_n_sync_r; + pll_ref_clk_reset_n_sync_rrr <= pll_ref_clk_reset_n_sync_rr; + end + end + + // CPA takes ~50k core clock cycles to lock. Obviously we can't use a potentially + // unstable core clock to clock the counter. We need to use the ref clock instead. + // The fastest legal ref clock can run at the same rate as core clock, so we simply + // count 64k PLL ref clock cycles. + logic [16:0] cpa_count_to_lock; + + // The following is evaluated for simulation. Don't wait too long during simulation. + // synthesis translate_off + `define USE_SIM_COUNTER_LOCK_EXP TRUE + // synthesis translate_on + + `ifdef USE_SIM_COUNTER_LOCK_EXP + localparam COUNTER_LOCK_EXP = 9; + `else + localparam COUNTER_LOCK_EXP = DIAG_SYNTH_FOR_SIM ? 9 : 16; + `endif + + always_ff @(posedge pll_ref_clk_int or negedge pll_ref_clk_reset_n) begin + if (~pll_ref_clk_reset_n) begin + cpa_count_to_lock <= '0; + counter_lock <= 1'b0; + end else begin + if (~cpa_count_to_lock[COUNTER_LOCK_EXP]) begin + cpa_count_to_lock <= cpa_count_to_lock + 1'b1; + end + counter_lock <= cpa_count_to_lock[COUNTER_LOCK_EXP]; + end + end + end + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate CPA-based core clock signals + logic [1:0] core_clks_from_cpa_pri_buffered; + logic [1:0] core_clks_from_cpa_sec_buffered; + + ///////////////////////////////////////////////////////////// + // Assign signals for DFT + assign dft_core_clk_locked = DIAG_USE_CPA_LOCK ? core_clks_locked_cpa_pri : {2{counter_lock}}; + assign dft_core_clk_buf_out = core_clks_from_cpa_pri_buffered; + + generate + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") + begin : clk_gen_hmc + + // If HMC is used, there's no AFI clock + assign afi_half_clk = 1'b0; + assign afi_clk = 1'b0; + + if (USER_CLK_RATIO == 2 && C2P_P2C_CLK_RATIO == 4) + begin : bridge_2x + // For 2x-bridge mode, expose two core clocks: + // 0) A half-rate clock (i.e. emif_usr_clk) + // 1) A quarter-rate clock (i.e. emif_usr_half_clk) + + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : clk_gen_slave + assign core_clks_from_cpa_pri_buffered = {emif_usr_half_clk_slave_in, emif_usr_clk_slave_in}; + assign core_clks_from_cpa_sec_buffered = {emif_usr_half_clk_sec_slave_in, emif_usr_clk_sec_slave_in}; + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = cpa_lock_pri_slave_in; + assign cpa_lock_sec = cpa_lock_sec_slave_in; + end else + begin : clk_gen_master + + // Fitter can automatically insert clock buffers as needed + assign core_clks_from_cpa_pri_buffered[0] = core_clks_from_cpa_pri[0]; + assign core_clks_from_cpa_pri_buffered[1] = core_clks_from_cpa_pri[1]; + + assign cpa_lock_pri = core_clks_locked_cpa_pri[0]; + assign core_clks_fb_to_cpa_pri = core_clks_from_cpa_pri_buffered; + if (PHY_PING_PONG_EN) begin : gen_sec_clk + // Fitter can automatically insert clock buffers as needed + assign core_clks_from_cpa_sec_buffered[0] = core_clks_from_cpa_sec[0]; + assign core_clks_from_cpa_sec_buffered[1] = core_clks_from_cpa_sec[1]; + + assign cpa_lock_sec = core_clks_locked_cpa_sec[0] & core_clks_locked_cpa_sec[1]; + assign core_clks_fb_to_cpa_sec = core_clks_from_cpa_sec_buffered; + + end else begin : non_pp + assign cpa_lock_sec = 1'b0; + assign core_clks_fb_to_cpa_sec = '0; + assign core_clks_from_cpa_sec_buffered = '0; + end + end + + assign emif_usr_clk = core_clks_from_cpa_pri_buffered[0]; + assign emif_usr_half_clk = core_clks_from_cpa_pri_buffered[1]; + assign emif_usr_clk_sec = core_clks_from_cpa_sec_buffered[0]; + assign emif_usr_half_clk_sec = core_clks_from_cpa_sec_buffered[1]; + + end else + begin : hr_qr + + // For half/quarter-rate, expose one core clock (i.e. emif_usr_clk) + // running at the user-requested rate + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : clk_gen_slave + assign core_clks_from_cpa_pri_buffered = {emif_usr_half_clk_slave_in, emif_usr_clk_slave_in}; + assign core_clks_from_cpa_sec_buffered = {emif_usr_half_clk_sec_slave_in, emif_usr_clk_sec_slave_in}; + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = cpa_lock_pri_slave_in; + assign cpa_lock_sec = cpa_lock_sec_slave_in; + end else + begin : clk_gen_master + + // Fitter can automatically insert clock buffers as needed + assign core_clks_from_cpa_pri_buffered[0] = core_clks_from_cpa_pri[0]; + + if (DIAG_CPA_OUT_1_EN) + begin : force_cpa_out_1_en + assign core_clks_from_cpa_pri_buffered[1] = core_clks_from_cpa_pri[1]; + assign cpa_lock_pri = core_clks_locked_cpa_pri[0] & core_clks_locked_cpa_pri[1]; + + end else begin : normal + assign core_clks_from_cpa_pri_buffered[1] = core_clks_from_cpa_pri_buffered[0]; + assign cpa_lock_pri = core_clks_locked_cpa_pri[0]; + end + + assign core_clks_fb_to_cpa_pri = core_clks_from_cpa_pri_buffered; + + if (PHY_PING_PONG_EN) begin : gen_sec_clk + // Fitter can automatically insert clock buffers as needed + assign core_clks_from_cpa_sec_buffered[0] = core_clks_from_cpa_sec[0]; + + assign cpa_lock_sec = core_clks_locked_cpa_sec[0]; + assign core_clks_fb_to_cpa_sec = core_clks_from_cpa_sec_buffered; + assign core_clks_from_cpa_sec_buffered[1] = core_clks_from_cpa_sec_buffered[0]; + + end else begin : non_pp + assign cpa_lock_sec = 1'b0; + assign core_clks_fb_to_cpa_sec = '0; + assign core_clks_from_cpa_sec_buffered = '0; + end + end + + assign emif_usr_clk = core_clks_from_cpa_pri_buffered[0]; + assign emif_usr_half_clk = core_clks_from_cpa_pri_buffered[1]; + assign emif_usr_clk_sec = core_clks_from_cpa_sec_buffered[0]; + assign emif_usr_half_clk_sec = core_clks_from_cpa_sec_buffered[1]; + + end + end else + begin : clk_gen_non_hmc + + // If HMC isn't used, there's no emif_usr_* clocks + assign emif_usr_clk = 1'b0; + assign emif_usr_half_clk = 1'b0; + assign emif_usr_clk_sec = 1'b0; + assign emif_usr_half_clk_sec = 1'b0; + + // Always expose both afi_clk and afi_half_clk + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : clk_gen_slave + assign core_clks_from_cpa_pri_buffered = {afi_clk_slave_in, afi_half_clk_slave_in}; + assign core_clks_from_cpa_sec_buffered = '0; + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = cpa_lock_pri_slave_in; + assign cpa_lock_sec = cpa_lock_sec_slave_in; + end else + begin : clk_gen_master + // Fitter can automatically insert clock buffers as needed + assign core_clks_from_cpa_pri_buffered[0] = core_clks_from_cpa_pri[0]; + assign core_clks_from_cpa_pri_buffered[1] = core_clks_from_cpa_pri[1]; + + assign core_clks_fb_to_cpa_pri = core_clks_from_cpa_pri_buffered; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = core_clks_locked_cpa_pri[0]; + assign cpa_lock_sec = 1'b0; + end + + assign afi_clk = core_clks_from_cpa_pri_buffered[0]; + assign afi_half_clk = 1'b0; + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate core reset signals for CPA-based core clocks + logic sync_clk_pri; + logic sync_clk_sec; + logic reset_sync_pri_pre_reg; + logic reset_sync_sec_pre_reg; + + // Every interface flops the synchronized reset signal locally. + // We do this so every interface has an anchor point that our SDC can use + // as starting point to traverse the clock topology. + // The flop is marked to prevent from being optimized away. + (* altera_attribute = {"-name GLOBAL_SIGNAL ON"}*) logic reset_sync_pri_sdc_anchor /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin + if (~async_reset_n_pri) begin + reset_sync_pri_sdc_anchor <= '0; + end else begin + reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg; + end + end + + logic reset_sync_sec_sdc_anchor_ext; + generate + if (PHY_PING_PONG_EN) begin : pp + (* altera_attribute = {"-name GLOBAL_SIGNAL ON"}*) logic reset_sync_sec_sdc_anchor /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + always_ff @(posedge sync_clk_sec or negedge async_reset_n_sec) begin + if (~async_reset_n_sec) begin + reset_sync_sec_sdc_anchor <= '0; + end else begin + reset_sync_sec_sdc_anchor <= reset_sync_sec_pre_reg; + end + end + assign reset_sync_sec_sdc_anchor_ext = reset_sync_sec_sdc_anchor; + end else begin : no_pp + assign reset_sync_sec_sdc_anchor_ext = 1'b0; + end + endgenerate + + generate + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") + begin : reset_gen_hmc + assign sync_clk_pri = emif_usr_clk; + assign sync_clk_sec = emif_usr_clk_sec; + assign emif_usr_reset_n_pri_pre_reg = reset_sync_pri_pre_reg; + assign emif_usr_reset_n_sec_pre_reg = reset_sync_sec_pre_reg; + assign emif_usr_reset_n = reset_sync_pri_sdc_anchor; + assign emif_usr_reset_n_sec = reset_sync_sec_sdc_anchor_ext; + assign afi_reset_n_pre_reg = 1'b0; + assign afi_reset_n = 1'b0; + end else + begin: reset_gen_non_hmc + assign sync_clk_pri = afi_clk; + assign sync_clk_sec = 1'b0; + assign afi_reset_n_pre_reg = reset_sync_pri_pre_reg; + assign afi_reset_n = reset_sync_pri_sdc_anchor; + assign emif_usr_reset_n_pri_pre_reg = 1'b0; + assign emif_usr_reset_n = 1'b0; + assign emif_usr_reset_n_sec_pre_reg = 1'b0; + assign emif_usr_reset_n_sec = 1'b0; + end + + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : reset_gen_slave + // The master exposes a synchronized reset signal for the slaves + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") begin + assign reset_sync_pri_pre_reg = emif_usr_reset_n_pri_pre_reg_slave_in; + assign reset_sync_sec_pre_reg = emif_usr_reset_n_sec_pre_reg_slave_in; + end else begin + assign reset_sync_pri_pre_reg = afi_reset_n_pre_reg_slave_in; + assign reset_sync_sec_pre_reg = 1'b0; + end + end else + begin : reset_gen_master + + // Synchronize reset deassertion to core clock + logic [CPA_RESET_SYNC_LENGTH-1:0] reset_sync_pri; + always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin + if (~async_reset_n_pri) begin + reset_sync_pri <= '0; + end else begin + reset_sync_pri[0] <= 1'b1; + reset_sync_pri[CPA_RESET_SYNC_LENGTH-1:1] <= reset_sync_pri[CPA_RESET_SYNC_LENGTH-2:0]; + end + end + assign reset_sync_pri_pre_reg = reset_sync_pri[CPA_RESET_SYNC_LENGTH-1]; + + if (PHY_PING_PONG_EN) begin : gen_sec_rst_sync + logic [CPA_RESET_SYNC_LENGTH-1:0] reset_sync_sec; + always_ff @(posedge sync_clk_sec or negedge async_reset_n_sec) begin + if (~async_reset_n_sec) begin + reset_sync_sec <= '0; + end else begin + reset_sync_sec[0] <= 1'b1; + reset_sync_sec[CPA_RESET_SYNC_LENGTH-1:1] <= reset_sync_sec[CPA_RESET_SYNC_LENGTH-2:0]; + end + end + assign reset_sync_sec_pre_reg = reset_sync_sec[CPA_RESET_SYNC_LENGTH-1]; + end else begin : no_pp + assign reset_sync_sec_pre_reg = 1'b0; + end + end + endgenerate + + /////////////////////////////////////////////////////////////////// + // Synchronize local_reset_req to core clock domain. This gives + // users freedom to use an asynchonrous source for local_reset_req, + // but with the extra requirement that the request pulse must be + // at least 2 core clock cycles long. + // Instantiate synchronizer at the master only and use the output + // of the synchronizer to drive all slaves, to make sure that + // the request gets to the sequencer at the exact same cycle for + // all masters and slaves. + generate + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : local_reset_req_sync_gen_slave + assign local_reset_req_sync = 1'b0; + end else + begin : local_reset_req_sync_gen_master + logic sync_clk; + logic sync_reset_n; + + assign sync_clk = (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") ? emif_usr_clk : afi_clk; + assign sync_reset_n = (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") ? emif_usr_reset_n : afi_reset_n; + + altera_std_synchronizer_nocut # ( + .depth (LOCAL_RESET_REQ_SYNC_LENGTH), + .rst_value (0) + ) local_reset_req_sync_inst ( + .clk (sync_clk), + .reset_n (sync_reset_n), + .din (local_reset_req), + .dout (local_reset_req_sync) + ); + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2gdRxeoq7YMd09J0Ox2d/MTEgLDbJ+E/3atnQdXbskMZMHQcqp+8mGKfqevapAP2IgQ+qIFxbK+YkgPvlocVbVuyZ9pe7XFS2l3zfsGznlSFOtxGDinGuQdWWREYMp7BJewXAOBa/csqcSb5Huo94qc0TuDmAaen0VgIPgnK7peyZnMWQVDb9uJYGkbg0nL6alMBr8S7yzVX7NlwvesdKqpXEsOh2zar4CTw1MEpW2UYbjJpQgNeFwrfBcvllGXlYSSCfUWbeXDc2MEuBYpW7cGljz+93O3fX5k9I4R6kM4BNrbAFl9GjyFYTEE6A5IKkUAWFAjEwa8vCMtuv//BKWyd4CZU5SDopV2XE9w1VFHcaAETfktskD0f4X7ARtdZUo8T+rtSFwTd0ePlpcJx88dq9knVDD0vs4Gh4+mQ+o2iy2B0v00/6ua9HYCoOgvvtjxBS2ZZeI75GOWRWA1fjjMWSk9QGi07g/qYZf3ouCaXt4br+GDf+b0hoVxkZbSBKSQv+l2z5R5hSEQwTKE4wdfVZ155ttLjSuWFObZGReDJWHfimwOH//LX8eGWlPcQZ8w7WtK1sQ8Rqc3uem43Lo5y/Q3CdGV2gx+i+lfIMfFa9/ruhzY9E4RjphYQqNkyqVPWiKc4CeOmGai0KnvtTKHZ1okAOVXov8P++VzhXrcaaMz+kiCDtylPGkm7AaX+TZWnVGIqqEYjDNXKO+8gcRHZOGM9cyCgAdmFCGG0wcIEyQiGm/tilN3Idf0WbyqMc14ZqNed/uW6gUOl5+jGAT" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_amm_data_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_amm_data_if.sv new file mode 100644 index 0000000000..34cfa3c3ea --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_amm_data_if.sv @@ -0,0 +1,248 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the data interfaces through which +// soft logic interacts with the Avalon MM port of the HMC +// +/////////////////////////////////////////////////////////////////////////////// + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _core2l_data(_port_i, _phase_i) core2l_data\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)]\ + [(`_get_pin(WD_PINLOC, _port_i) * 8) + _phase_i] + +`define _core2l_datamask(_port_i, _phase_i) core2l_data\ + [`_get_tile(WM_PINLOC, _port_i)]\ + [`_get_lane(WM_PINLOC, _port_i)]\ + [(`_get_pin(WM_PINLOC, _port_i) * 8) + _phase_i] + +`define _l2core_data(_port_i, _phase_i) l2core_data\ + [`_get_tile(RD_PINLOC, _port_i)]\ + [`_get_lane(RD_PINLOC, _port_i)]\ + [(`_get_pin(RD_PINLOC, _port_i) * 8) + _phase_i] + +`define _unused_core2l_data(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +module altera_emif_arch_fm_hmc_amm_data_if #( + parameter HMC_READY_LATENCY = 0, + parameter REGISTER_AMM_C2P = 0, + parameter REGISTER_AMM_P2C = 0, + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + + // Parameters describing HMC front-end ports + parameter NUM_OF_HMC_PORTS = 1, + + // Definition of port widths for "ctrl_amm" interface (auto-generated) + parameter PORT_CTRL_AMM_RDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 1, + + // Pin indexes of data signals + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + + // Pin indexes of write data mask signals + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0 +) ( + input emif_usr_clk, + input emif_usr_clk_sec, + + // Signals between core and data lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + + // FM IOSS C2P restrictions requires C2P OEs to be 8 bits per tile + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe, + + // AMM data signals between core and data lanes when HMC is used + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_0, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0, + + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_1, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1 +); + timeunit 1ns; + timeprecision 1ps; + + localparam RD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_Q_PINLOC); + localparam WD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_D_PINLOC); + localparam WM_PINLOC = (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0 ? PORT_MEM_DM_PINLOC : (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0 ? PORT_MEM_DBI_N_PINLOC : PORT_MEM_BWS_N_PINLOC)); + + localparam NUM_RD_PINS = `_get_pin_count(RD_PINLOC); + localparam NUM_WD_PINS = `_get_pin_count(WD_PINLOC); + localparam NUM_WM_PINS = `_get_pin_count(WM_PINLOC); + + localparam NUM_RD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_RD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WM_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WM_PINS / NUM_OF_HMC_PORTS) : 0; + + localparam NUM_OF_RD_PHASES_PER_HMC_PORT = PORT_CTRL_AMM_RDATA_WIDTH / NUM_RD_PINS_PER_HMC_PORT; + localparam NUM_OF_WD_PHASES_PER_HMC_PORT = PORT_CTRL_AMM_WDATA_WIDTH / NUM_WD_PINS_PER_HMC_PORT; + localparam NUM_OF_WM_PHASES_PER_HMC_PORT = (NUM_WM_PINS == 0) ? 0 : (PORT_CTRL_AMM_BYTEEN_WIDTH / NUM_WM_PINS_PER_HMC_PORT); + + assign core2l_oe = '1; + + generate + genvar port_i; + genvar phase_i; + genvar pin_i; + + logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0_final; + logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0_final; + logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1_final; + logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1_final; + + if (NUM_OF_HMC_PORTS == 0) begin + assign amm_writedata_0_final = amm_writedata_0; + assign amm_byteenable_0_final = amm_byteenable_0; + assign amm_writedata_1_final = amm_writedata_1; + assign amm_byteenable_1_final = amm_byteenable_1; + end else begin + logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0_r [1:0]; + logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0_r [1:0]; + logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1_r [1:0]; + logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1_r [1:0]; + + assign amm_writedata_0_final = amm_writedata_0_r [REGISTER_AMM_C2P > 1 ? 1 : 0]; + assign amm_byteenable_0_final = amm_byteenable_0_r[REGISTER_AMM_C2P > 1 ? 1 : 0]; + assign amm_writedata_1_final = amm_writedata_1_r [REGISTER_AMM_C2P > 1 ? 1 : 0]; + assign amm_byteenable_1_final = amm_byteenable_1_r[REGISTER_AMM_C2P > 1 ? 1 : 0]; + + always_ff @(posedge emif_usr_clk) begin + amm_writedata_0_r[0] <= amm_writedata_0; + amm_byteenable_0_r[0] <= amm_byteenable_0; + amm_writedata_0_r[1] <= amm_writedata_0_r[0]; + amm_byteenable_0_r[1] <= amm_byteenable_0_r[0]; + end + always_ff @(posedge emif_usr_clk_sec) begin + amm_writedata_1_r[0] <= amm_writedata_1; + amm_byteenable_1_r[0] <= amm_byteenable_1; + amm_writedata_1_r[1] <= amm_writedata_1_r[0]; + amm_byteenable_1_r[1] <= amm_byteenable_1_r[0]; + end + end + + // Map Avalon-MM writedata signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port + for (phase_i = 0; phase_i < NUM_OF_WD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WD_PINS_PER_HMC_PORT) begin + assign `_core2l_data(port_i, phase_i) = amm_writedata_0_final[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i]; + end else begin + assign `_core2l_data(port_i, phase_i) = amm_writedata_1_final[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i - NUM_WD_PINS_PER_HMC_PORT]; + end + end + end + + // Map Avalon-MM byte-enable signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port + for (phase_i = 0; phase_i < NUM_OF_WM_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WM_PINS_PER_HMC_PORT) begin + assign `_core2l_datamask(port_i, phase_i) = amm_byteenable_0_final[phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i]; + end else begin + assign `_core2l_datamask(port_i, phase_i) = amm_byteenable_1_final[phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i - NUM_WM_PINS_PER_HMC_PORT]; + end + end + end + + logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_0_int; + logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_1_int; + + // Map lanes' read data bus to Avalon-MM readdata signal + for (port_i = 0; port_i < NUM_RD_PINS; ++port_i) + begin : rd_port + for (phase_i = 0; phase_i < NUM_OF_RD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_RD_PINS_PER_HMC_PORT) begin + assign amm_readdata_0_int[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i] = `_l2core_data(port_i, phase_i); + end else begin + assign amm_readdata_1_int[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i - NUM_RD_PINS_PER_HMC_PORT] = `_l2core_data(port_i, phase_i); + end + end + end + + if (REGISTER_AMM_P2C >= 1) begin + always_ff @(posedge emif_usr_clk) begin + amm_readdata_0 <= amm_readdata_0_int; + end + always_ff @(posedge emif_usr_clk_sec) begin + amm_readdata_1 <= amm_readdata_1_int; + end + end else begin + assign amm_readdata_0 = amm_readdata_0_int; + assign amm_readdata_1 = amm_readdata_1_int; + end + + // Tie off unused phases for core2l_data for the write data pins + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port_unused + for (phase_i = NUM_OF_WD_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_data(port_i, phase_i) = 1'b0; + end + end + + // Tie off unused phases for core2l_data for the write data mask pins + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port_unused + for (phase_i = NUM_OF_WM_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_datamask(port_i, phase_i) = 1'b0; + end + end + + // Tie off core2l_data for unused connections + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) + assign `_unused_core2l_data(pin_i) = '0; + end + + // Tie off the read data ports if they're not used + if (NUM_OF_HMC_PORTS < 1) begin + assign amm_readdata_0_int = '0; + end + + if (NUM_OF_HMC_PORTS < 2) begin + assign amm_readdata_1_int = '0; + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm02m6ttNb6xchRuC7VKb5RwoOkRce+DWo1otWUycjAsAHJcT9TXSj69Bf/M81tWt3BFb9Rfo+Ftb7Tt+J+DtN2DUwMbE9xDzrnMJe8CV+gL4golMAau/IXUAJfA2yqjdpWujP2gxrzlPI5H+DNUDVdz6sdcD6tqI9/Jxpi5tWBXxDBSLjb4D0vdWhAcYFRvJaVmx3SaYVxOjqLdvFFOtdc58WjSAINVUz95MGiWtxhgklbQ99qhM0IGIwkw6K20wBjZ9M9a6ZlTRLZ3v7NRfgOoNPzEWkk2Ih+aNIcG0GcmxpjahOLrsFtTpg2HAUDGjIi0J+IG1NRsPV4I8FmxR3nbwIeQd89o4+EOdkqWxzvDQabpIW64t0i/Pm68YAHvEWgL+mvNFX1V+0nVUZR95vSSRWOOEXrIDypXLk6UopY7DdiOvSwNhi/VHlsJbmtN5rrsCNfVuCerVcRJNbYWhjy/hCeTpBWMyE5/VYh6B9xmElfMoniBLr9klN45K/upjWy5WG1gdYAooWzYzMGe0/KAQLI1NhPvJOVbYYrYhIiVq3kPY8YUtFPqknxnd0ofc/ZADYyogTUkl3Q96xe5UONYZaHhcb7hMPDvY5FtkYDOXQ9WYjcVkqy7f9bqDl05tb+9neonMKaYcUZAkQqlJgjfd+74CALYzACZnHDruyn+dTML3dPNoVzup3x72SDW+GOrGJUxQWXySEOh7b5udXJCXMQQfwrR4Aim60ZL2IFXqR0swsZw+h1R8jM0xQXLsQK7PWc42V7DXg4Wr4Ic+6JQ" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_ast_data_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_ast_data_if.sv new file mode 100644 index 0000000000..a44696daca --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_ast_data_if.sv @@ -0,0 +1,196 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the data interfaces through which +// soft logic interacts with the Avalon ST port of the HMC +// +/////////////////////////////////////////////////////////////////////////////// + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _core2l_data(_port_i, _phase_i) core2l_data\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)]\ + [(`_get_pin(WD_PINLOC, _port_i) * 8) + _phase_i] + +`define _core2l_datamask(_port_i, _phase_i) core2l_data\ + [`_get_tile(WM_PINLOC, _port_i)]\ + [`_get_lane(WM_PINLOC, _port_i)]\ + [(`_get_pin(WM_PINLOC, _port_i) * 8) + _phase_i] + +`define _l2core_data(_port_i, _phase_i) l2core_data\ + [`_get_tile(RD_PINLOC, _port_i)]\ + [`_get_lane(RD_PINLOC, _port_i)]\ + [(`_get_pin(RD_PINLOC, _port_i) * 8) + _phase_i] + +`define _unused_core2l_data(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +module altera_emif_arch_fm_hmc_ast_data_if #( + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + + // Parameters describing HMC front-end ports + parameter NUM_OF_HMC_PORTS = 1, + + // Definition of port widths for "ctrl_ast_wr" interface (auto-generated) + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_rd" interface (auto-generated) + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 1, + + // Pin indexes of data signals + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + + // Pin indexes of write data mask signals + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0 +) ( + // Signals between core and data lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + + // FM IOSS C2P restrictions requires C2P OEs to be 8 bits per lane + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe, + + // AST data signals between core and data lanes when HMC is used + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_0, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_0, + + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_1, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_1 +); + timeunit 1ns; + timeprecision 1ps; + + localparam RD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_Q_PINLOC); + localparam WD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_D_PINLOC); + localparam WM_PINLOC = (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0 ? PORT_MEM_DM_PINLOC : (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0 ? PORT_MEM_DBI_N_PINLOC : PORT_MEM_BWS_N_PINLOC)); + + localparam NUM_RD_PINS = `_get_pin_count(RD_PINLOC); + localparam NUM_WD_PINS = `_get_pin_count(WD_PINLOC); + localparam NUM_WM_PINS = `_get_pin_count(WM_PINLOC); + + // The write data bus includes both data (LSBs) and data mask (MSBs). Here we calculate the width of both. + localparam NUM_OF_AST_REAL_WR_DATA_WIDTH = PORT_CTRL_AST_RD_DATA_WIDTH; + localparam NUM_OF_AST_BYTE_EN_WIDTH = PORT_CTRL_AST_WR_DATA_WIDTH - NUM_OF_AST_REAL_WR_DATA_WIDTH; + + localparam NUM_RD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_RD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WM_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WM_PINS / NUM_OF_HMC_PORTS) : 0; + + localparam NUM_OF_RD_PHASES_PER_HMC_PORT = PORT_CTRL_AST_RD_DATA_WIDTH / NUM_RD_PINS_PER_HMC_PORT; + localparam NUM_OF_WD_PHASES_PER_HMC_PORT = NUM_OF_AST_REAL_WR_DATA_WIDTH / NUM_WD_PINS_PER_HMC_PORT; + localparam NUM_OF_WM_PHASES_PER_HMC_PORT = (NUM_WM_PINS == 0) ? 0 : (NUM_OF_AST_BYTE_EN_WIDTH / NUM_WM_PINS_PER_HMC_PORT); + + assign core2l_oe = '1; + + generate + genvar port_i; + genvar phase_i; + genvar pin_i; + + // Map Avalon-ST writedata signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port + for (phase_i = 0; phase_i < NUM_OF_WD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WD_PINS_PER_HMC_PORT) begin + assign `_core2l_data(port_i, phase_i) = ast_wr_data_0[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i]; + end else begin + assign `_core2l_data(port_i, phase_i) = ast_wr_data_1[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i - NUM_WD_PINS_PER_HMC_PORT]; + end + end + end + + // Map Avalon-ST byte-enable signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port + for (phase_i = 0; phase_i < NUM_OF_WM_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WM_PINS_PER_HMC_PORT) begin + assign `_core2l_datamask(port_i, phase_i) = ast_wr_data_0[(NUM_OF_WD_PHASES_PER_HMC_PORT * NUM_WD_PINS_PER_HMC_PORT) + (phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i)]; + end else begin + assign `_core2l_datamask(port_i, phase_i) = ast_wr_data_1[(NUM_OF_WD_PHASES_PER_HMC_PORT * NUM_WD_PINS_PER_HMC_PORT) + (phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i - NUM_WM_PINS_PER_HMC_PORT)]; + end + end + end + + // Map lanes' read data bus to Avalon-ST readdata signal + for (port_i = 0; port_i < NUM_RD_PINS; ++port_i) + begin : rd_port + for (phase_i = 0; phase_i < NUM_OF_RD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_RD_PINS_PER_HMC_PORT) begin + assign ast_rd_data_0[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i] = `_l2core_data(port_i, phase_i); + end else begin + assign ast_rd_data_1[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i - NUM_RD_PINS_PER_HMC_PORT] = `_l2core_data(port_i, phase_i); + end + end + end + + // Tie off unused phases for core2l_data for the write data pins + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port_unused + for (phase_i = NUM_OF_WD_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_data(port_i, phase_i) = 1'b0; + end + end + + // Tie off unused phases for core2l_data for the write data mask pins + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port_unused + for (phase_i = NUM_OF_WM_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_datamask(port_i, phase_i) = 1'b0; + end + end + + // Tie off core2l_data for unused connections + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) + assign `_unused_core2l_data(pin_i) = '0; + end + + // Tie off the read data ports if they're not used + if (NUM_OF_HMC_PORTS < 1) begin + assign ast_rd_data_0 = '0; + end + + if (NUM_OF_HMC_PORTS < 2) begin + assign ast_rd_data_1 = '0; + end + endgenerate +endmodule + + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm0XkvqozUSoPu/dpPG/oqhMfpedxct7ldg1ZwJbEixblVCvcTEk9ES/Mr6twVic02FgL0h0P37Lb2dfmLe7DKNXtqavYPEm4QhXOMpBmcwl6idM43mzhKs7q1dGozpIslSQ1F5IxpMiiqfXv2mvaYcWtvC6GFlRELjOeiiGnQq2BnPp7ebAyYUGPX9vW6WE2SH7c5UgmpyUqKFIh5Ye1rTK6HVjzPgQjEY2Oxu/ykp43PbYbDri2XWC41b5rcUMpJ/eqPBBNKnEdvfP2UB9q6LvSZ3laA0SNC4ApWDZIGp9kFN3eQiuKvTHJRf74H/YRT9tV5kI6X40dwqG7KEjVFSuLd5rRE7k5mp/26W3vf9sboe7KbLdy78bC5A9y55rxnEROw63ZiB+4Wx6w/x0W2mxk1MHV+0c9S+Dxa3m+iPw2oFSY7M4dw3muCyFk7IFblA9o7bNaKw9OIbbAkcatHhfdVoHSHtI29o+nxVdi+3FKKPKCBSDh7ZYQys4WqV6zJNX8RMRyetESuA6PqXWwY9EcCHMzRCDq3f1lnY8u866EIGM1f0jOF/zGu2wD0xOTSUNjDHlutW8Cfv5e4goieOBH65/V9439QQPXBojL6G9A+SqiWKEJ3PhaEaPf5oLz3WjVE+kSU0l9ippoJv/dIqlAI4eZnHJg99lLPDB3PGflg0j3lYnjOiCY8BHO4O8ohYPL2CPg4tyKoiFxHLYTEp/9C7b5yGQSq/s5gCZM26rXelBTup99IuNLrn34Rt6dq2FV7XSFmJ++8fYJSoRqeGZ" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_avl_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_avl_if.sv new file mode 100644 index 0000000000..08f06d54cb --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_avl_if.sv @@ -0,0 +1,375 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the Avalon interfaces through which +// soft logic interacts with the Hard Memory Controller inside the tile. +// The tile WYSIWYG blocks collapse the individual Avalon signals into big +// buses. This module re-wires the big buses into proper Avalon interfaces. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_fm_hmc_avl_if #( + // Parameters describing HMC front-end ports + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_READY_LATENCY = 0, + parameter REGISTER_AMM_P2C = 0, + parameter REGISTER_AMM_C2P = 0, + + // Parameters describing lanes/tiles + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + + // Definition of port widths for "ctrl_ast_cmd" interface (auto-generated) + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_amm" interface (auto-generated) + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 1 + +) ( + // User reset going to core (for PHY + hard controller interfaces) + input logic emif_usr_reset_n, + input logic emif_usr_reset_n_sec, + + // User clock going to core (for PHY + hard controller interfaces) + input logic emif_usr_clk, + input logic emif_usr_clk_sec, + + // Collapsed Avalon signals going into/out of tiles + output logic [62:0] core2ctl_avl_0, + output core2ctl_avl_rd_data_ready_0, + input logic ctl2core_avl_cmd_ready_0, + + output logic core2l_wr_data_vld_ast, + output logic core2l_rd_data_rdy_ast, + + output logic [62:0] core2ctl_avl_1, + output core2ctl_avl_rd_data_ready_1, + input logic ctl2core_avl_cmd_ready_1, + + + // Avalon interfaces between core and lanes + input logic l2core_rd_data_vld_avl, + input logic l2core_wr_data_rdy_ast, + input logic l2core_rd_type, + + // Ports for "ctrl_user_priority" interface + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + + // Controller auto-precharge request signals + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + + // Ports for "ctrl_ast_cmd" interfaces (auto-generated) + output logic ast_cmd_ready_0, + input logic ast_cmd_valid_0, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_0, + + output logic ast_cmd_ready_1, + input logic ast_cmd_valid_1, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_1, + + // Ports for "ctrl_ast_wr" interfaces (auto-generated) + output logic ast_wr_ready_0, + input logic ast_wr_valid_0, + + output logic ast_wr_ready_1, + input logic ast_wr_valid_1, + + // Ports for "ctrl_ast_rd" interfaces (auto-generated) + input logic ast_rd_ready_0, + output logic ast_rd_valid_0, + + input logic ast_rd_ready_1, + output logic ast_rd_valid_1, + + // Ports for "ctrl_amm" interfaces (auto-generated) + input logic amm_write_0, + input logic amm_read_0, + output logic amm_ready_0, + output logic amm_early_ready_0, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_0, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + output logic amm_rd_type_0, + + input logic amm_write_1, + input logic amm_read_1, + output logic amm_ready_1, + output logic amm_early_ready_1, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_1, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + output logic amm_rd_type_1 +); + timeunit 1ns; + timeprecision 1ps; + + localparam NUM_C2L_FANOUT = 1; + + generate + if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM") begin : amm + logic [34:0] amm_address_padded_0; + logic [34:0] amm_address_padded_1; + logic [7:0] amm_burstcount_padded_0; + logic [7:0] amm_burstcount_padded_1; + + if (PORT_CTRL_AMM_ADDRESS_WIDTH >= 35) begin + assign amm_address_padded_0 = amm_address_0; + assign amm_address_padded_1 = amm_address_1; + end else begin + assign amm_address_padded_0 = {'0, amm_address_0}; + assign amm_address_padded_1 = {'0, amm_address_1}; + end + + if (PORT_CTRL_AMM_BCOUNT_WIDTH >= 8) begin + assign amm_burstcount_padded_0 = amm_burstcount_0; + assign amm_burstcount_padded_1 = amm_burstcount_1; + end else begin + assign amm_burstcount_padded_0 = {'0, amm_burstcount_0}; + assign amm_burstcount_padded_1 = {'0, amm_burstcount_1}; + end + + logic [34:0] amm_address_padded_0_final; + logic [34:0] amm_address_padded_1_final; + logic [7:0] amm_burstcount_padded_0_final; + logic [7:0] amm_burstcount_padded_1_final; + logic ctrl_user_priority_hi_0_final; + logic ctrl_user_priority_hi_1_final; + logic ctrl_auto_precharge_req_0_final; + logic ctrl_auto_precharge_req_1_final; + logic amm_read_0_final; + logic amm_read_1_final; + logic amm_write_0_final; + logic amm_write_1_final; + + if (REGISTER_AMM_C2P == 0) begin + assign amm_address_padded_0_final = amm_address_padded_0; + assign amm_address_padded_1_final = amm_address_padded_1; + assign amm_burstcount_padded_0_final = amm_burstcount_padded_0; + assign amm_burstcount_padded_1_final = amm_burstcount_padded_1; + assign ctrl_user_priority_hi_0_final = ctrl_user_priority_hi_0; + assign ctrl_user_priority_hi_1_final = ctrl_user_priority_hi_1; + assign ctrl_auto_precharge_req_0_final = ctrl_auto_precharge_req_0; + assign ctrl_auto_precharge_req_1_final = ctrl_auto_precharge_req_1; + assign amm_read_0_final = (NUM_OF_HMC_PORTS == 0) ? amm_read_0 : amm_read_0 & amm_ready_0; + assign amm_read_1_final = (NUM_OF_HMC_PORTS == 0) ? amm_read_1 : amm_read_1 & amm_ready_1; + assign amm_write_0_final = (NUM_OF_HMC_PORTS == 0) ? amm_write_0 : amm_write_0 & amm_ready_0; + assign amm_write_1_final = (NUM_OF_HMC_PORTS == 0) ? amm_write_1 : amm_write_1 & amm_ready_1; + end else begin + logic [1:0][34:0] amm_address_padded_0_r; + logic [1:0][34:0] amm_address_padded_1_r; + logic [1:0][7:0] amm_burstcount_padded_0_r; + logic [1:0][7:0] amm_burstcount_padded_1_r; + logic [1:0] ctrl_user_priority_hi_0_r; + logic [1:0] ctrl_user_priority_hi_1_r; + logic [1:0] ctrl_auto_precharge_req_0_r; + logic [1:0] ctrl_auto_precharge_req_1_r; + logic [1:0] amm_read_0_r; + logic [1:0] amm_read_1_r; + logic [1:0] amm_write_0_r; + logic [1:0] amm_write_1_r; + + assign amm_address_padded_0_final = amm_address_padded_0_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_address_padded_1_final = amm_address_padded_1_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_burstcount_padded_0_final = amm_burstcount_padded_0_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_burstcount_padded_1_final = amm_burstcount_padded_1_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign ctrl_user_priority_hi_0_final = ctrl_user_priority_hi_0_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign ctrl_user_priority_hi_1_final = ctrl_user_priority_hi_1_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign ctrl_auto_precharge_req_0_final = ctrl_auto_precharge_req_0_r[(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign ctrl_auto_precharge_req_1_final = ctrl_auto_precharge_req_1_r[(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_read_0_final = amm_read_0_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_read_1_final = amm_read_1_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_write_0_final = amm_write_0_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + assign amm_write_1_final = amm_write_1_r [(REGISTER_AMM_C2P > 1) ? 1 : 0]; + + + always_ff @(posedge emif_usr_clk) begin + amm_read_0_r <= {amm_read_0_r[0], amm_read_0 & amm_ready_0}; + amm_write_0_r <= {amm_write_0_r[0], amm_write_0 & amm_ready_0}; + + amm_address_padded_0_r <= {amm_address_padded_0_r[0], amm_address_padded_0}; + amm_burstcount_padded_0_r <= {amm_burstcount_padded_0_r[0], amm_burstcount_padded_0}; + ctrl_user_priority_hi_0_r <= {ctrl_user_priority_hi_0_r[0], ctrl_user_priority_hi_0}; + ctrl_auto_precharge_req_0_r <= {ctrl_auto_precharge_req_0_r[0], ctrl_auto_precharge_req_0}; + end + + always_ff @(posedge emif_usr_clk_sec) begin + amm_read_1_r <= {amm_read_1_r[0], amm_read_1 & amm_ready_1}; + amm_write_1_r <= {amm_write_1_r[0], amm_write_1 & amm_ready_1}; + + amm_address_padded_1_r <= {amm_address_padded_1_r[0], amm_address_padded_1}; + amm_burstcount_padded_1_r <= {amm_burstcount_padded_1_r[0], amm_burstcount_padded_1}; + ctrl_user_priority_hi_1_r <= {ctrl_user_priority_hi_1_r[0], ctrl_user_priority_hi_1}; + ctrl_auto_precharge_req_1_r <= {ctrl_auto_precharge_req_1_r[0], ctrl_auto_precharge_req_1}; + end + end + + + if (REGISTER_AMM_P2C >= 1) begin + always_ff @(posedge emif_usr_clk) begin + amm_rd_type_0 <= l2core_rd_type; + amm_readdatavalid_0 <= l2core_rd_data_vld_avl; + end + always_ff @(posedge emif_usr_clk_sec) begin + amm_rd_type_1 <= l2core_rd_type; + amm_readdatavalid_1 <= l2core_rd_data_vld_avl; + end + end else begin + assign amm_rd_type_0 = l2core_rd_type; + assign amm_rd_type_1 = l2core_rd_type; + assign amm_readdatavalid_0 = l2core_rd_data_vld_avl; + assign amm_readdatavalid_1 = l2core_rd_data_vld_avl; + end + + if (NUM_OF_HMC_PORTS == 0) begin : ready_wire + assign amm_ready_0 = ctl2core_avl_cmd_ready_0; + assign amm_ready_1 = ctl2core_avl_cmd_ready_1; + assign amm_early_ready_0 = '0; + assign amm_early_ready_1 = '0; + end else begin: ready_hyper_regs + logic amm_ready_0_r0; + logic amm_ready_1_r0; + logic amm_ready_0_r1; + logic amm_ready_1_r1; + always_ff @(posedge emif_usr_clk) begin + amm_ready_0_r0 <= ctl2core_avl_cmd_ready_0; + amm_ready_0_r1 <= amm_ready_0_r0; + end + assign amm_ready_0 = (REGISTER_AMM_P2C == 0 ? ctl2core_avl_cmd_ready_0 : + REGISTER_AMM_P2C > 1 ? amm_ready_0_r1 : amm_ready_0_r0); + assign amm_early_ready_0 = (REGISTER_AMM_P2C == 0 ? 1'b0 : + REGISTER_AMM_P2C > 1 ? amm_ready_0_r0 : ctl2core_avl_cmd_ready_0); + + always_ff @(posedge emif_usr_clk_sec) begin + amm_ready_1_r0 <= ctl2core_avl_cmd_ready_1; + amm_ready_1_r1 <= amm_ready_1_r0; + end + assign amm_ready_1 = (REGISTER_AMM_P2C == 0 ? ctl2core_avl_cmd_ready_1 : + REGISTER_AMM_P2C > 1 ? amm_ready_1_r1 : amm_ready_1_r0); + assign amm_early_ready_1 = (REGISTER_AMM_P2C == 0 ? 1'b0 : + REGISTER_AMM_P2C > 1 ? amm_ready_1_r0 : ctl2core_avl_cmd_ready_1); + end + + // Port 0 + assign core2ctl_avl_0[0] = amm_read_0_final; + assign core2ctl_avl_0[1] = amm_write_0_final; + assign core2ctl_avl_0[36:2] = amm_address_padded_0_final; + assign core2ctl_avl_0[44:37] = amm_burstcount_padded_0_final; + assign core2ctl_avl_0[45] = ctrl_user_priority_hi_0_final; + assign core2ctl_avl_0[46] = ctrl_auto_precharge_req_0_final; + assign core2ctl_avl_0[47] = '0; + assign core2ctl_avl_0[60:48] = '0; + assign core2ctl_avl_0[61] = '0; + assign core2ctl_avl_0[62] = '0; + + // Port 1 + assign core2ctl_avl_1[0] = amm_read_1_final; + assign core2ctl_avl_1[1] = amm_write_1_final; + assign core2ctl_avl_1[36:2] = amm_address_padded_1_final; + assign core2ctl_avl_1[44:37] = amm_burstcount_padded_1_final; + assign core2ctl_avl_1[45] = ctrl_user_priority_hi_1_final; + assign core2ctl_avl_1[46] = ctrl_auto_precharge_req_1_final; + assign core2ctl_avl_1[47] = '0; + assign core2ctl_avl_1[60:48] = '0; + assign core2ctl_avl_1[61] = '0; + assign core2ctl_avl_1[62] = '0; + + // Tie-off unused signals + assign ast_cmd_ready_0 = '0; + assign ast_wr_ready_0 = '0; + assign ast_rd_valid_0 = '0; + assign core2ctl_avl_rd_data_ready_0 = '1; + assign core2l_wr_data_vld_ast = '0; + assign core2l_rd_data_rdy_ast = '1; + assign ast_cmd_ready_1 = '0; + assign ast_wr_ready_1 = '0; + assign ast_rd_valid_1 = '0; + assign core2ctl_avl_rd_data_ready_1 = '1; + + end else if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_ST") begin : ast + // Port 0 + assign core2ctl_avl_0[60:0] = ast_cmd_data_0; + assign core2ctl_avl_0[61] = ast_cmd_valid_0; + assign core2ctl_avl_0[62] = ast_wr_valid_0; + assign ast_cmd_ready_0 = ctl2core_avl_cmd_ready_0; + + assign ast_wr_ready_0 = l2core_wr_data_rdy_ast; + assign ast_rd_valid_0 = l2core_rd_data_vld_avl; + + assign core2ctl_avl_rd_data_ready_0 = ast_rd_ready_0; + assign amm_ready_0 = '0; + assign amm_early_ready_0 = '0; + assign amm_readdatavalid_0 = '0; + assign amm_rd_type_0 = '0; + assign core2l_wr_data_vld_ast = ast_wr_valid_0; + assign core2l_rd_data_rdy_ast = ast_rd_ready_0; + + // Port 1 + assign core2ctl_avl_1[60:0] = ast_cmd_data_1; + assign core2ctl_avl_1[61] = ast_cmd_valid_1; + assign core2ctl_avl_1[62] = ast_wr_valid_1; + assign ast_cmd_ready_1 = ctl2core_avl_cmd_ready_1; + assign ast_wr_ready_1 = l2core_wr_data_rdy_ast; + assign ast_rd_valid_1 = l2core_rd_data_vld_avl; + assign core2ctl_avl_rd_data_ready_1 = ast_rd_ready_1; + assign amm_ready_1 = '0; + assign amm_early_ready_1 = '0; + assign amm_readdatavalid_1 = '0; + assign amm_rd_type_1 = '0; + end else begin : no_hmc + // Port 0 + assign core2ctl_avl_0 = '0; + assign ast_cmd_ready_0 = '0; + assign ast_wr_ready_0 = '0; + assign ast_rd_valid_0 = '0; + assign core2ctl_avl_rd_data_ready_0 = '1; + assign amm_ready_0 = '0; + assign amm_early_ready_0 = '0; + assign amm_readdatavalid_0 = '0; + assign core2l_wr_data_vld_ast = '0; + assign core2l_rd_data_rdy_ast = '1; + assign amm_rd_type_0 = '0; + + // Port 1 + assign core2ctl_avl_1 = '0; + assign ast_cmd_ready_1 = '0; + assign ast_wr_ready_1 = '0; + assign ast_rd_valid_1 = '0; + assign core2ctl_avl_rd_data_ready_1 = '1; + assign amm_ready_1 = '0; + assign amm_early_ready_1 = '0; + assign amm_readdatavalid_1 = '0; + assign amm_rd_type_1 = '0; + end + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm1IFi0lYVUwsvLFhY6JYpGiaThUsiJ++0jhiwcH96eHRcC2IhihvdtVSwv0xf37ynA05f7FUFymP9zU5RmwVb4zk8WcR10/u5EsWF4ljG27gxCqC0BPogMVkM6yP2fkBWsJEoDtf6PpYqUf7oKyc9+SAWrHCSA96OVtuEJZHcL4ikiNzy8VVf0LkmDArCazFVWEPdb0XFVOFO0l6xVMICLNFWgd2DWLKQFi6/Adrx4LO3zIKGAoddblt4EunwCKF54lVl+TZTaW+RwdYEMT2gXTR8ilobZz39zSqo7SYkJNhXWoBxvn8cA22/pDZ1+64mN88BMwiMUUf/r3kUuGsj40p/jnDNG6YM40IoQQ9VmcA3M+SwBmthACzDLsW6+MuU+j5U5BPFH1HFkDDFinT9QkRYXCMuAaFgKKFJQB8d9s7iIxQDTmdf/QDSQF2RCNoF5VShl+XXvLS9OdqS2Im1Ka7B7i1x+plcOzVNJxEjyqnR8X0F6oBmJ34GkmzHqLabdx8+Q263dIX7effOH5deuNuclQJOKtrBjWyrVh28zGacAvrSfMBC3JKEp2OrQdF7aWKaqb6HPB9Fxn+bCU3F/RtwZztqlM0xwlO0rx+YsDmqiCVJQrO8TbluhKMe5QSBKLaF54ma/5TkrOnn5tvZXMHHNZeAp1Dwjbo7m4mLfbBjyBgSysvA5PY3F3M2pMhKRY+7lGpPYEyLANScZwRyYPEa1f7/i4tn71pysa1xKu3TjsoUMY1y60Qeqrdf2phdkhcaASm753I4Pz70n/3xrn" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_mmr_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_mmr_if.sv new file mode 100644 index 0000000000..a089da1f61 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_mmr_if.sv @@ -0,0 +1,84 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + +module altera_emif_arch_fm_hmc_mmr_if #( + + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 1 +) ( + input logic [33:0] ctl2core_mmr_0, + output logic [50:0] core2ctl_mmr_0, + input logic [33:0] ctl2core_mmr_1, + output logic [50:0] core2ctl_mmr_1, + + input logic emif_usr_clk, + + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_0, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_0, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_0, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_1, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_1, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_1, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1 +); + timeunit 1ns; + timeprecision 1ps; + + assign core2ctl_mmr_1[13:10] = 'b0; + assign core2ctl_mmr_0[13:10] = 'b0; + + always_ff @(posedge emif_usr_clk) begin + core2ctl_mmr_0[9:0] <= mmr_slave_address_0; + core2ctl_mmr_0[45:14] <= mmr_slave_writedata_0; + core2ctl_mmr_0[46] <= mmr_slave_write_0; + core2ctl_mmr_0[47] <= mmr_slave_read_0; + core2ctl_mmr_0[49:48] <= mmr_slave_burstcount_0; + core2ctl_mmr_0[50] <= mmr_slave_beginbursttransfer_0; + + mmr_slave_readdata_0 <= ctl2core_mmr_0[31:0]; + mmr_slave_readdatavalid_0 <= ctl2core_mmr_0[32]; + mmr_slave_waitrequest_0 <= ctl2core_mmr_0[33]; + + core2ctl_mmr_1[9:0] <= mmr_slave_address_1; + core2ctl_mmr_1[45:14] <= mmr_slave_writedata_1; + core2ctl_mmr_1[46] <= mmr_slave_write_1; + core2ctl_mmr_1[47] <= mmr_slave_read_1; + core2ctl_mmr_1[49:48] <= mmr_slave_burstcount_1; + core2ctl_mmr_1[50] <= mmr_slave_beginbursttransfer_1; + + mmr_slave_readdata_1 <= ctl2core_mmr_1[31:0]; + mmr_slave_readdatavalid_1 <= ctl2core_mmr_1[32]; + mmr_slave_waitrequest_1 <= ctl2core_mmr_1[33]; + end + +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2zTfIUIGJoZH5DYU9hegJoUhSoB9M+V9SheV2Iit6Wtucb91DV9bw4WeqcRbqpf1olkZRBqaRzLIXMWwNC1V4x/fxciUj6QtrpgSNybY7tJyX3ksHuwDdun3hpwxubpi9CHm/Ugg5UVRXK3HlKG04ISwnsLX1dP8836ZwO2vej08xxxb1v6qZBgrdXsNgb1ErxwGFLb6+BLN0zoSUgiX92rJTRiRM1ce7/9fLEMEzXSoTxPLgCaZ8W3E68tQuuJawst0W/nN1gfaAFHOBUeU4DTLiNVcCzSFbMb4+1IVayv0EW0xZuenNGnvO29mPBdjD1hp/dgdKNFGTd9mpBAXH5M9JYPBgPhuaJJIeADvEeW4sfiPGbJeW8gA6l9LixrxstXsuEBGZPJ73HOMvaXDHkVZr0WeFYZtSLiiFX9BRh4/JjxR1eMkS9cH3uVhIf1eZNIRzJinyrXUK0J9/OpKc1am0Ebh7twp9AepnWc/mm05IXmkYVFbmnwSecYhe4GjD6XcV9nCX/hEHBReDULdf1HaYunTUjKslyOKZ+ciAQtxtxXLxWjHluYJYZBGEgisnfYqOEf3KNCAI2H3DSzdIqJu96EtXFtGSbTYrCUxWVx/lcTPXD2i3di+wjjiRoyXk6GdWgHKtqIqt82xBFy6y4wLsPVxXyvyAwnMdZhRaoXyJz2pL0JIRCSxP5GIyA3ZiLI5qVrU53abXPay/x3fRLABePWXxMd00X2I6eNtidXz8Pgiu334BVTsekAAPjz9zOxfrcbW6IYE10X+slbvTC" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_sideband_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_sideband_if.sv new file mode 100644 index 0000000000..152537cf0b --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_sideband_if.sv @@ -0,0 +1,160 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the controller sideband interfaces +// through which soft logic interacts with the Hard Memory Controller. +// The tile WYSIWYG blocks collapse the individual sideband signals into big +// buses. This module re-logics the big buses into proper interfaces. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_fm_hmc_sideband_if #( + + // Parameters describing lanes/tiles + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter PRI_AC_TILE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + + // Definition of port widths for "ctrl_user_refresh" interface + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 1, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 1, + + // Definition of port widths for "ctrl_self_refresh" interface + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 1, + + // Definition describing ECC + parameter PRI_HMC_CFG_ENABLE_ECC = "disable", + parameter SEC_HMC_CFG_ENABLE_ECC = "disable", + + // Definition of port widths for "ctrl_ecc" interface + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 1, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 1 + +) ( + // Collapsed sideband signals going into/out of tiles + output logic [41:0] core2ctl_sideband_0, + input logic [13:0] ctl2core_sideband_0, + output logic [41:0] core2ctl_sideband_1, + input logic [13:0] ctl2core_sideband_1, + + // Additional ECC signals going into/out of lanes + input logic [12:0] ctl2core_avl_rdata_id_0, + input logic [12:0] ctl2core_avl_rdata_id_1, + output logic [12:0] core2l_wr_ecc_info, + input logic [11:0] l2core_wb_pointer_for_ecc, + + // Ports for "ctrl_user_refresh" interface + input logic [PORT_CTRL_USER_REFRESH_REQ_WIDTH-1:0] ctrl_user_refresh_req, + input logic [PORT_CTRL_USER_REFRESH_BANK_WIDTH-1:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + + // Ports for "ctrl_self_refresh" interface + input logic [PORT_CTRL_SELF_REFRESH_REQ_WIDTH-1:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + + // Ports for "ctrl_will_refresh" interface + output logic ctrl_will_refresh, + + // Ports for "ctrl_deep_power_down" interface + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + + // Ports for "ctrl_power_down" interface + output logic ctrl_power_down_ack, + + // Ports for "ctrl_zq_cal" interface + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_0, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_0, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_0, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_0, + + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_1, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_1, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_1, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_1 + +); + timeunit 1ns; + timeprecision 1ps; + + localparam NUM_C2L_FANOUT = NUM_OF_RTL_TILES * LANES_PER_TILE; + + assign core2ctl_sideband_0[3:0] = ctrl_user_refresh_req; + assign core2ctl_sideband_0[19:4] = ctrl_user_refresh_bank; + assign core2ctl_sideband_0[20] = ctrl_deep_power_down_req; + assign core2ctl_sideband_0[24:21] = ctrl_self_refresh_req; + assign core2ctl_sideband_0[25] = ctrl_zq_cal_long_req; + assign core2ctl_sideband_0[26] = ctrl_zq_cal_short_req; + + assign ctrl_user_refresh_ack = ctl2core_sideband_0[6]; + assign ctrl_deep_power_down_ack = ctl2core_sideband_0[7]; + assign ctrl_power_down_ack = ctl2core_sideband_0[8]; + assign ctrl_self_refresh_ack = ctl2core_sideband_0[9]; + assign ctrl_zq_cal_ack = ctl2core_sideband_0[10]; + assign ctrl_will_refresh = ctl2core_sideband_0[13]; + + + + assign ctrl_ecc_read_info_0 = ctl2core_sideband_0[2:0]; + assign ctrl_ecc_cmd_info_0 = ctl2core_sideband_0[5:3]; + assign ctrl_ecc_idle_0 = ctl2core_sideband_0[12]; + assign ctrl_ecc_rdata_id_0 = ctl2core_avl_rdata_id_0; + + assign ctrl_ecc_wr_pointer_info_0 = l2core_wb_pointer_for_ecc[11:0]; + assign core2ctl_sideband_0[41:27] = ctrl_ecc_write_info_0; + + assign core2l_wr_ecc_info = (NUM_OF_HMC_PORTS>0 && HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_ST")? ctrl_ecc_write_info_0[14:2] : 13'b0; + + assign ctrl_ecc_read_info_1 = 3'd0; + assign ctrl_ecc_cmd_info_1 = 3'd0; + assign ctrl_ecc_idle_1 = 1'b0; + assign ctrl_ecc_rdata_id_1 = 13'd0; + assign ctrl_ecc_wr_pointer_info_1 = 12'd0; + assign core2ctl_sideband_1[3:0] = '0; + assign core2ctl_sideband_1[19:4] = '0; + assign core2ctl_sideband_1[20] = '0; + assign core2ctl_sideband_1[24:21] = '0; + assign core2ctl_sideband_1[25] = '0; + assign core2ctl_sideband_1[26] = '0; + assign core2ctl_sideband_1[41:27] = 15'd0; + +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm068zWwN3Gvd0+vLqYte5gk4gZkrjWWs1hpN2l14WFBOFeogFzjmiiGGXXF0EMoDlVbsIxIzy6sSaUeNxCoMZzzFjCmflWQ6s1Mxw/bSbxNbVgtwhjL2LZyGP0+uhhZP3WYMIZhiBfMhHgivq9DwUkWiN9ghMQxa9QXqO7n77/fyf2eejvESKZ/sxUA/1WrXQsrLwqaTKngFtIDCcp+/eLLL7QH8xLciwvq2vocL6WObkVY4GX+tXm5kzbr3AW7Ko8nxPARVLyN23T+hcZ8dXWAgbpIopm8ilC59Tffp6hsiZ4Oomjr6aVemOcnlsdLua6SwleTEmsW6fHvx2tpISBSHS8YreekzhW5aCxDCXmDPCALpSKPmac5GUpr7NqCCXknZPD+4FaRiDvyiA3+XsuYwxaRDTO+g1hW56HHdTpPi7f4qEKhUhn0VGRQlTHil2PCjtSd854yBmQu4fnM2Cyb+awa91+stRaCHQEcNn+LWHziCYhvUzHF3BqSnENdTlqSh4SH3gDgFAanvKq54sD2KNghJcPAwSrIStEoI/VAAYSBNt1cU1MCKMlDFsu7SiYnwNoP6vmFfiCYLcHRaRhtlyQ4ixrv1VmnApNTgoQQqTbwYMyf9BoT+YXWaP2sOabcYOWhd8FmU6wMBq3BdMKdcfWRouSo0cI8/2PNCcZa6ru6BBjeBIh7ongdpBWQXmsnHFm8Q5V9Oi6cJxZL+ThbjdsTOdZx5xplLH/JHmTMvyPtvo6ikTYQnLaxiCR73GchMIry7vkja9AmDyVRjFYP" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hps_clks_rsts.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hps_clks_rsts.sv new file mode 100644 index 0000000000..d275699be1 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hps_clks_rsts.sv @@ -0,0 +1,109 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module handles the creation and wiring of the HPS clock/reset signals. +// +/////////////////////////////////////////////////////////////////////////////// + +// altera message_off 10036 + + module altera_emif_arch_fm_hps_clks_rsts #( + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 32, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 32, + parameter PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 1 +) ( + // For a master interface, the PLL ref clock and the global reset signal + // come from an external source from user logic, via the following ports. + // For slave interfaces, they come from the master via the sharing interface. + // The connectivity ensures that all interfaces in a master/slave + // configuration share the same ref clock and global reset, which is + // one of the requirements for core-clock sharing. + // pll_ref_clk_int is the actual PLL ref clock signal that will be used by the + // reset of the IP. For a master interface it is equivalent to pll_ref_clk. + // For a slave interface it is equivalent to the pll_ref_clk signal of the master. + input logic pll_ref_clk, + output logic pll_ref_clk_int, + + // Feedback signals to CPA via the core + output logic [1:0] core_clks_fb_to_cpa_pri, + output logic [1:0] core_clks_fb_to_cpa_sec, + + // Reset request signal. + // local_reset_req_int is the actual reset request signal that will be + // used internally by the rest of the IP. For a master interface it + // is equivalent to local_reset_req. For a slave interface it is + // equivalent to the local_reset_req signal of the master. + input logic local_reset_req, + output logic local_reset_req_int, + + // The following is the master/slave sharing interfaces. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // The following are all the possible core clock/reset signals. + // afi_* only exists in PHY-only mode (or if soft controller is used). + // emif_usr_* only exists if hard memory controller is used. + output logic afi_clk, + output logic afi_half_clk, + output logic afi_reset_n, + + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n, + + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic emif_usr_reset_n_sec, + + // DFT + output logic [PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + // HPS clocks are not modeled for simulation. + // Also in HPS mode we do not generate clocks that are visible to user logic. + assign pll_ref_clk_int = pll_ref_clk; + + // Reset request is not supported by HPS EMIF. + // HPS EMIF has its own way of reset request mechanism. + assign local_reset_req_int = 1'b0; + + assign afi_clk = 1'b0; + assign afi_half_clk = 1'b0; + assign afi_reset_n = 1'b1; + + assign emif_usr_clk = 1'b0; + assign emif_usr_half_clk = 1'b0; + assign emif_usr_reset_n = 1'b1; + + assign emif_usr_clk_sec = 1'b0; + assign emif_usr_half_clk_sec = 1'b0; + assign emif_usr_reset_n_sec = 1'b1; + + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign clks_sharing_master_out = '0; + + assign dft_core_clk_locked = '0; + assign dft_core_clk_buf_out = '0; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2VJ/YUEn9R/ugUoGv9EVWxH2feQCRBXZZFQaUR7HxitpOWsPBGtN9tbo3ts1HWl/3/p/hfRgTvK3To+uNM1OSBeMLQ9IUr7hM//ghYu5SaAKQ7CTeOveiHpxUm8dG+ZJ7Pl4XvhfvC4/uneZ6vAWQSDVB5RKTPrtAtF2+dqdUoYcKOPZLA2UG71oa2MUAEhhpqwvG829Z0T2BMnXTY9w2/4v+Yb7cPxCkKuAfD0aeHpoEYCDJdv/r1nYjpFVzWYYGOhsm/h2nMmihZBBpGAFpvF7uo0obDwCYv5xra53EHt/hfIhPLXCWQTc5iR/F5YcgZ6KMGvvpFCJwbOIoNHM2wm6VlSxtYmfoQnxoSQN47Xtw3VyPudSziivVu0HFALaXbh9KCFqFP4ThEU8PbkWXSBwZijFL2f5WgcjD6LZmHhiIZIEWAVUa1NauPlL+uxFbisLejCRb7qDAU5fy9i60iba/riaUz1obOAt5F9XbqVkbHK5NPhfkswQV7ERsB88PqsRhfkB61RCcdPJ/WJJoyyL2cEYTdtlK1V+9PfNebeGJXxPRnndnNOmpAmMM0JXR0z8KDxB8N9/i/EoqLNfiTqJ9p9b3KS+WxYIlDVKKFMCqlbmGgIyEycix0IgfYyA72gofzIF5rLlloSCLq99pLWtL8R7MP8+Z4sQkrMuJIegphhK9XQlKmWWTeRonWRoTaCwquZ0v9fH2P6hAk7deaO3dgK9dBBmc7Ht6rgoWveg6/0DNCx9sZT2cW303qcokHAY9qS+yAZH8H01IpS1GV" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_lane_remap.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_lane_remap.sv new file mode 100644 index 0000000000..8c9d3bf631 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_lane_remap.sv @@ -0,0 +1,696 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module instantiates one lane withina a tile +// This file remaps the parameter to uniquify the names for easy reading +// at the top level +// +/////////////////////////////////////////////////////////////////////////////// + +`define TO_STRING(S) `"S`" + +`define _map_pin_octrt(X) ( pin``X``_oct_rt == "static_oct_on" ? `TO_STRING(pin``X``_static_oct_on) : ( \ + `TO_STRING(pin``X``_static_oct_off) )) + +`define _map_pin_initial_out(X) ( pin``X``_initial_out == "initial_out_z" ? `TO_STRING(pin``X``_initial_out_z) : ( \ + pin``X``_initial_out == "initial_out_0" ? `TO_STRING(pin``X``_initial_out_0) : ( \ + pin``X``_initial_out == "initial_out_1" ? `TO_STRING(pin``X``_initial_out_1) : ( \ + `TO_STRING(pin``X``_initial_out_x) )))) + +`define _map_lane_pin_mode(X) ( lane_pin``X``_mode == "pin_ddr" ? `TO_STRING(lane_pin``X``_ddr) : ( \ + `TO_STRING(lane_pin``X``_unused) )) + +`define _map_pin_dynoct(X) ( pin``X``_dyn_oct == "dyn_oct_on" ? `TO_STRING(pin``X``_dyn_oct_on) : ( \ + `TO_STRING(pin``X``_dyn_oct_off) )) + +`define _map_db_pin_mode(X) ( \ + db_pin``X``_mode == "ac_hmc" ? `TO_STRING(pin``X``_ac_wdb_ddr4_hmc) : ( \ + db_pin``X``_mode == "dq_wdb_mode" ? `TO_STRING(pin``X``_dq_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "dm_wdb_mode" ? `TO_STRING(pin``X``_dm_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "dbi_wdb_mode" ? `TO_STRING(pin``X``_dbi_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "clk_wdb_mode" ? `TO_STRING(pin``X``_clk_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "clkb_wdb_mode" ? `TO_STRING(pin``X``_clkb_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "dqs_wdb_mode" ? `TO_STRING(pin``X``_dqs_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "dqsb_wdb_mode" ? `TO_STRING(pin``X``_dqsb_wdb_ddr4_mode) : ( \ + db_pin``X``_mode == "ac_in_core" ? `TO_STRING(pin``X``_ac_in_core) : ( \ + db_pin``X``_mode == "ac_core" ? `TO_STRING(pin``X``_ac_core) : ( \ + db_pin``X``_mode == "dq_mode" ? `TO_STRING(pin``X``_dq_mode) : ( \ + db_pin``X``_mode == "dm_mode" ? `TO_STRING(pin``X``_dm_mode) : ( \ + db_pin``X``_mode == "dbi_mode" ? `TO_STRING(pin``X``_dbi_mode) : ( \ + db_pin``X``_mode == "clk_mode" ? `TO_STRING(pin``X``_clk_mode) : ( \ + db_pin``X``_mode == "clkb_mode" ? `TO_STRING(pin``X``_clkb_mode) : ( \ + db_pin``X``_mode == "dqs_mode" ? `TO_STRING(pin``X``_dqs_mode) : ( \ + db_pin``X``_mode == "dqsb_mode" ? `TO_STRING(pin``X``_dqsb_mode) : ( \ + db_pin``X``_mode == "dqs_ddr4_mode" ? `TO_STRING(pin``X``_dqs_ddr4_mode) : ( \ + db_pin``X``_mode == "dqsb_ddr4_mode" ? `TO_STRING(pin``X``_dqsb_ddr4_mode) : ( \ + db_pin``X``_mode == "rdq_mode" ? `TO_STRING(pin``X``_rdq_mode) : ( \ + db_pin``X``_mode == "rdqs_mode" ? `TO_STRING(pin``X``_rdqs_mode) : ( \ + db_pin``X``_mode == "gpio_mode" ? `TO_STRING(pin``X``_gpio_mode) : ( \ + "UNMATCHED_DB_PIN_MODE" ))))))))))))))))))))))) + +`define _map_pin_mode_ddr(X) ( pin``X``_mode_ddr == "mode_sdr" ? `TO_STRING(pin``X``_mode_sdr) : ( \ + `TO_STRING(pin``X``_mode_ddr) )) + +`define _map_pin_dqs_mode(X) ( pin``X``_dqs_mode == "dqs_sampler_a" ? `TO_STRING(pin``X``_dqs_sampler_a) : ( \ + pin``X``_dqs_mode == "dqs_sampler_b" ? `TO_STRING(pin``X``_dqs_sampler_b) : ( \ + `TO_STRING(pin``X``_dqs_sampler_b_a_rise) ))) + +`define _map_pin_data_in_mode(X) ( pin``X``_data_in_mode == "ca" ? `TO_STRING(pin``X``_ca) : ( \ + pin``X``_data_in_mode == "clock" ? `TO_STRING(pin``X``_clock) : ( \ + pin``X``_data_in_mode == "dq" ? `TO_STRING(pin``X``_dq) : ( \ + pin``X``_data_in_mode == "dqs" ? `TO_STRING(pin``X``_dqs) : ( \ + pin``X``_data_in_mode == "dpa_slave" ? `TO_STRING(pin``X``_dpa_slave) : ( \ + pin``X``_data_in_mode == "dpa_master" ? `TO_STRING(pin``X``_dpa_master) : ( \ + pin``X``_data_in_mode == "dq_xor_a_loopback" ? `TO_STRING(pin``X``_dq_xor_a_loopback) : ( \ + pin``X``_data_in_mode == "dq_xor_b_loopback" ? `TO_STRING(pin``X``_dq_xor_b_loopback) : ( \ + `TO_STRING(pin``X``_dqs_xor_loopback) ))))))))) + +`define _map_pin_gpio_differential(X) ( pin``X``_gpio_differential == "gpio_single_ended" ? `TO_STRING(pin``X``_gpio_single_ended) : ( \ + `TO_STRING(pin``X``_gpio_differential) )) + +`define _map_pin_dq_in_select(X) ( pin``X``_dq_in_select == "dq_sstl_in" ? `TO_STRING(pin``X``_dq_sstl_in) : ( \ + pin``X``_dq_in_select == "dq_loopback_in" ? `TO_STRING(pin``X``_dq_loopback_in) : ( \ + pin``X``_dq_in_select == "dq_xor_loopback_in" ? `TO_STRING(pin``X``_dq_xor_loopback_in) : ( \ + pin``X``_dq_in_select == "dq_differential_in" ? `TO_STRING(pin``X``_dq_differential_in) : ( \ + `TO_STRING(pin``X``_dq_disabled) ))))) + +`define _map_lane_pin_ddr_mode(X) ( lane_pin``X``_ddr_mode == "ddr_notddr" ? `TO_STRING(lane_pin``X``_ddr_notddr) : ( \ + lane_pin``X``_ddr_mode == "ddr_dq" ? `TO_STRING(lane_pin``X``_ddr_dq) : ( \ + lane_pin``X``_ddr_mode == "ddr_dqs" ? `TO_STRING(lane_pin``X``_ddr_dqs) : ( \ + lane_pin``X``_ddr_mode == "ddr_dqsb" ? `TO_STRING(lane_pin``X``_ddr_dqsb) : ( \ + lane_pin``X``_ddr_mode == "ddr_dm" ? `TO_STRING(lane_pin``X``_ddr_dm) : ( \ + lane_pin``X``_ddr_mode == "ddr_ca_ddr" ? `TO_STRING(lane_pin``X``_ddr_ca_ddr) : ( \ + lane_pin``X``_ddr_mode == "ddr_ca_sdr" ? `TO_STRING(lane_pin``X``_ddr_ca_sdr) : ( \ + lane_pin``X``_ddr_mode == "ddr_phylite_data_qr" ? `TO_STRING(lane_pin``X``_ddr_phylite_data_qr) : ( \ + `TO_STRING(lane_pin``X``_ddr_phylite_data_hr) ))))))))) + +module altera_emif_arch_fm_io_lane_remap ( + input [1:0] phy_clk, + input [1:0] phy_clk_local_early, + input [1:0] phy_clk_local_late, + input [7:0] phy_clk_phs, + + input reset_n, + input pll_locked, + input dll_ref_clk, + output [5:0] ioereg_locked, + + input [47:0] oe_from_core, + input [95:0] data_from_core, + output [95:0] data_to_core, + input [15:0] mrnk_read_core, + input [15:0] mrnk_write_core, + input [3:0] rdata_en_full_core, + output [3:0] rdata_valid_core, + + input core2dbc_rd_data_rdy, + input core2dbc_wr_data_vld0, + input [12:0] core2dbc_wr_ecc_info, + output dbc2core_rd_data_vld0, + output dbc2core_rd_type, + output [11:0] dbc2core_wb_pointer, + output dbc2core_wr_data_rdy, + + input [95:0] ac_hmc, + output [5:0] afi_rlat_core, + output [5:0] afi_wlat_core, + input [17:0] cfg_dbc, + input [50:0] ctl2dbc0, + input [50:0] ctl2dbc1, + output [22:0] dbc2ctl, + + input [54:0] cal_avl_in, + output [31:0] cal_avl_readdata_out, + output [54:0] cal_avl_out, + input [31:0] cal_avl_readdata_in, + + input [1:0] dqs_in, + input [1:0] broadcast_in_bot, + input [1:0] broadcast_in_top, + output [1:0] broadcast_out_bot, + output [1:0] broadcast_out_top, + + input [11:0] data_in, + output [11:0] data_out, + output [11:0] data_oe, + output [11:0] oct_enable, + + input [2:0] core_dll, + output [12:0] dll_core, + + input sync_clk_bot_in, + output sync_clk_bot_out, + input sync_clk_top_in, + output sync_clk_top_out, + input sync_data_bot_in, + output sync_data_bot_out, + input sync_data_top_in, + output sync_data_top_out, + + output [1:0] dft_phy_clk +); +timeunit 1ps; +timeprecision 1ps; + + +parameter memory_controller = "smc"; +parameter memory_standard = "ddr4"; +parameter memory_burst_length = "bl8"; +parameter memory_width = "x8"; +parameter phy_clk_sel = 0; +parameter lane_mode = "lane_unused"; +parameter lane_ddr_mode = "lane_ddr_notddr"; +parameter logic [15:0] clock_period_ps = 'd0; + +parameter dqs_enable_delay = 6'd0; +parameter dqs_phase_shift_b = 13'd0; +parameter dqs_phase_shift_a = 13'd0; +parameter oct_size = 4'd0; +parameter rd_valid_delay = 7'd0; + +parameter mode_rate_in = "in_rate_1_4"; +parameter mode_rate_out = "out_rate_full"; +parameter logic [2:0] lock_speed = 3'h6; +parameter calibration = "skip"; + +parameter lane_pin0_mode = "lane_pin_unused"; +parameter lane_pin1_mode = "lane_pin_unused"; +parameter lane_pin2_mode = "lane_pin_unused"; +parameter lane_pin3_mode = "lane_pin_unused"; +parameter lane_pin4_mode = "lane_pin_unused"; +parameter lane_pin5_mode = "lane_pin_unused"; +parameter lane_pin6_mode = "lane_pin_unused"; +parameter lane_pin7_mode = "lane_pin_unused"; +parameter lane_pin8_mode = "lane_pin_unused"; +parameter lane_pin9_mode = "lane_pin_unused"; +parameter lane_pin10_mode = "lane_pin_unused"; +parameter lane_pin11_mode = "lane_pin_unused"; + +parameter lane_pin0_ddr_mode = "lane_pin_unused"; +parameter lane_pin1_ddr_mode = "lane_pin_unused"; +parameter lane_pin2_ddr_mode = "lane_pin_unused"; +parameter lane_pin3_ddr_mode = "lane_pin_unused"; +parameter lane_pin4_ddr_mode = "lane_pin_unused"; +parameter lane_pin5_ddr_mode = "lane_pin_unused"; +parameter lane_pin6_ddr_mode = "lane_pin_unused"; +parameter lane_pin7_ddr_mode = "lane_pin_unused"; +parameter lane_pin8_ddr_mode = "lane_pin_unused"; +parameter lane_pin9_ddr_mode = "lane_pin_unused"; +parameter lane_pin10_ddr_mode = "lane_pin_unused"; +parameter lane_pin11_ddr_mode = "lane_pin_unused"; + +parameter pin0_oct_rt = "static_oct_off"; +parameter pin1_oct_rt = "static_oct_off"; +parameter pin2_oct_rt = "static_oct_off"; +parameter pin3_oct_rt = "static_oct_off"; +parameter pin4_oct_rt = "static_oct_off"; +parameter pin5_oct_rt = "static_oct_off"; +parameter pin6_oct_rt = "static_oct_off"; +parameter pin7_oct_rt = "static_oct_off"; +parameter pin8_oct_rt = "static_oct_off"; +parameter pin9_oct_rt = "static_oct_off"; +parameter pin10_oct_rt = "static_oct_off"; +parameter pin11_oct_rt = "static_oct_off"; + +parameter pin0_initial_out = "initial_out_z"; +parameter pin1_initial_out = "initial_out_z"; +parameter pin2_initial_out = "initial_out_z"; +parameter pin3_initial_out = "initial_out_z"; +parameter pin4_initial_out = "initial_out_z"; +parameter pin5_initial_out = "initial_out_z"; +parameter pin6_initial_out = "initial_out_z"; +parameter pin7_initial_out = "initial_out_z"; +parameter pin8_initial_out = "initial_out_z"; +parameter pin9_initial_out = "initial_out_z"; +parameter pin10_initial_out = "initial_out_z"; +parameter pin11_initial_out = "initial_out_z"; + +parameter pin0_dyn_oct = "dyn_oct_off"; +parameter pin1_dyn_oct = "dyn_oct_off"; +parameter pin2_dyn_oct = "dyn_oct_off"; +parameter pin3_dyn_oct = "dyn_oct_off"; +parameter pin4_dyn_oct = "dyn_oct_off"; +parameter pin5_dyn_oct = "dyn_oct_off"; +parameter pin6_dyn_oct = "dyn_oct_off"; +parameter pin7_dyn_oct = "dyn_oct_off"; +parameter pin8_dyn_oct = "dyn_oct_off"; +parameter pin9_dyn_oct = "dyn_oct_off"; +parameter pin10_dyn_oct = "dyn_oct_off"; +parameter pin11_dyn_oct = "dyn_oct_off"; + +parameter pin0_dq_in_select = "dq_disabled"; +parameter pin1_dq_in_select = "dq_disabled"; +parameter pin2_dq_in_select = "dq_disabled"; +parameter pin3_dq_in_select = "dq_disabled"; +parameter pin4_dq_in_select = "dq_disabled"; +parameter pin5_dq_in_select = "dq_disabled"; +parameter pin6_dq_in_select = "dq_disabled"; +parameter pin7_dq_in_select = "dq_disabled"; +parameter pin8_dq_in_select = "dq_disabled"; +parameter pin9_dq_in_select = "dq_disabled"; +parameter pin10_dq_in_select = "dq_disabled"; +parameter pin11_dq_in_select = "dq_disabled"; + +parameter pin0_mode_ddr = "mode_ddr"; +parameter pin1_mode_ddr = "mode_ddr"; +parameter pin2_mode_ddr = "mode_ddr"; +parameter pin3_mode_ddr = "mode_ddr"; +parameter pin4_mode_ddr = "mode_ddr"; +parameter pin5_mode_ddr = "mode_ddr"; +parameter pin6_mode_ddr = "mode_ddr"; +parameter pin7_mode_ddr = "mode_ddr"; +parameter pin8_mode_ddr = "mode_ddr"; +parameter pin9_mode_ddr = "mode_ddr"; +parameter pin10_mode_ddr = "mode_ddr"; +parameter pin11_mode_ddr = "mode_ddr"; + +parameter pin0_dqs_mode = "dqs_sampler_a"; +parameter pin1_dqs_mode = "dqs_sampler_a"; +parameter pin2_dqs_mode = "dqs_sampler_a"; +parameter pin3_dqs_mode = "dqs_sampler_a"; +parameter pin4_dqs_mode = "dqs_sampler_a"; +parameter pin5_dqs_mode = "dqs_sampler_a"; +parameter pin6_dqs_mode = "dqs_sampler_a"; +parameter pin7_dqs_mode = "dqs_sampler_a"; +parameter pin8_dqs_mode = "dqs_sampler_a"; +parameter pin9_dqs_mode = "dqs_sampler_a"; +parameter pin10_dqs_mode = "dqs_sampler_a"; +parameter pin11_dqs_mode = "dqs_sampler_a"; + +parameter pin0_data_in_mode = "ca"; +parameter pin1_data_in_mode = "ca"; +parameter pin2_data_in_mode = "ca"; +parameter pin3_data_in_mode = "ca"; +parameter pin4_data_in_mode = "ca"; +parameter pin5_data_in_mode = "ca"; +parameter pin6_data_in_mode = "ca"; +parameter pin7_data_in_mode = "ca"; +parameter pin8_data_in_mode = "ca"; +parameter pin9_data_in_mode = "ca"; +parameter pin10_data_in_mode = "ca"; +parameter pin11_data_in_mode = "ca"; + +parameter db_pin0_mode = "pin_gpio_mode"; +parameter db_pin1_mode = "pin_gpio_mode"; +parameter db_pin2_mode = "pin_gpio_mode"; +parameter db_pin3_mode = "pin_gpio_mode"; +parameter db_pin4_mode = "pin_gpio_mode"; +parameter db_pin5_mode = "pin_gpio_mode"; +parameter db_pin6_mode = "pin_gpio_mode"; +parameter db_pin7_mode = "pin_gpio_mode"; +parameter db_pin8_mode = "pin_gpio_mode"; +parameter db_pin9_mode = "pin_gpio_mode"; +parameter db_pin10_mode = "pin_gpio_mode"; +parameter db_pin11_mode = "pin_gpio_mode"; + +parameter pin0_gpio_differential = "gpio_single_ended"; +parameter pin1_gpio_differential = "gpio_single_ended"; +parameter pin2_gpio_differential = "gpio_single_ended"; +parameter pin3_gpio_differential = "gpio_single_ended"; +parameter pin4_gpio_differential = "gpio_single_ended"; +parameter pin5_gpio_differential = "gpio_single_ended"; +parameter pin6_gpio_differential = "gpio_single_ended"; +parameter pin7_gpio_differential = "gpio_single_ended"; +parameter pin8_gpio_differential = "gpio_single_ended"; +parameter pin9_gpio_differential = "gpio_single_ended"; +parameter pin10_gpio_differential = "gpio_single_ended"; +parameter pin11_gpio_differential = "gpio_single_ended"; + +parameter db_hmc_or_core = "core"; +parameter db_dbi_sel = "dbi_dq0"; +parameter db_dbi_wr_en = "dbi_wr_dis"; +parameter db_dbi_rd_en = "dbi_rd_dis"; + +parameter db_avl_ena = "avl_disable"; +parameter db_avl_base_addr = 9'd0; +parameter db_avl_broadcast_en = "bc_disable"; + +parameter db_sel_core_clk = "phy_clk0"; + +parameter db_rwlat_mode = "avl_vlu"; +parameter db_ptr_pipeline_depth = "db_ptr_pipeline_depth_0"; +parameter db_preamble_mode = "preamble_one_cycle"; +parameter db_data_alignment_mode = "align_disable"; +parameter db_db2core_registered = "registered"; +parameter db_seq_rd_en_full_pipeline = "db_seq_rd_en_full_pipeline_0"; +parameter dll_rst_en = "dll_rst_dis"; +parameter dll_core_updnen = "core_updn_en"; +parameter dll_ctlsel = "ctl_static"; +parameter enable_toggler = "preamble_track_dqs_enable"; + +parameter dqs_select_a = "dqs_diff_in_1_a"; +parameter dqs_select_b = "dqs_diff_in_1_b"; + +parameter db_afi_wlat_vlu = 6'd0; +parameter db_afi_rlat_vlu = 6'd0; +parameter dbc_wb_reserved_entry = 5'd0; +parameter dll_ctl_static = 11'd0; +parameter db_mrnk_write_mode = "mrnk_write_enable"; + +parameter db_dbc_rb_readylat_en = "dbc_rb_readylat_disable"; +parameter db_dbc_wb_readylat_en = "dbc_wb_readylat_disable"; +parameter db_dbc_ctrl_rc_en_scalar = "dbc_rc_scalar_disable"; + +localparam l_phy_clk_sel = (phy_clk_sel == 0) ? "phy_clk_0" : "phy_clk_1"; + +localparam [15:0] clock_period_remap = clock_period_ps * 10; + +`define a_db_seq_rd_en_full_pipeline_remap(a_db_seq_rd_en_full_pipeline) \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_0") ? "db_seq_rd_en_full_pipeline_1": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_1") ? "db_seq_rd_en_full_pipeline_2": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_2") ? "db_seq_rd_en_full_pipeline_3": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_3") ? "db_seq_rd_en_full_pipeline_4": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_4") ? "db_seq_rd_en_full_pipeline_5": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_5") ? "db_seq_rd_en_full_pipeline_6": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_6") ? "db_seq_rd_en_full_pipeline_7": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_7") ? "db_seq_rd_en_full_pipeline_8": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_8") ? "db_seq_rd_en_full_pipeline_9": \ + (a_db_seq_rd_en_full_pipeline == "db_seq_rd_en_full_pipeline_9") ? "db_seq_rd_en_full_pipeline_10": \ + "db_seq_rd_en_full_pipeline_2" + + tennm_io_12_lane #( + .a_memory_standard (memory_standard), + .a_memory_burst_length (memory_burst_length), + .a_memory_controller (memory_controller), + .a_memory_width (memory_width), + + .a_mode_rate_in (mode_rate_in), + .a_mode_rate_out (mode_rate_out), + .a_clock_period (clock_period_remap), + .a_phy_clk_mode (l_phy_clk_sel), + .a_calibration (calibration), + .a_lock_speed (lock_speed), + .a_db_dbc_ctrl_rc_en_scalar (db_dbc_ctrl_rc_en_scalar), + .a_db_avl_base_addr (db_avl_base_addr), + .a_db_avl_broadcast_en (db_avl_broadcast_en), + .a_db_avl_ena (db_avl_ena), + .a_dqs_select_a (dqs_select_a), + .a_dqs_select_b (dqs_select_b), + + .a_memory_rank_size ("rank1"), + .a_output_phase (0), + .a_io_out_delay (0), + .a_board_delay (0), + .a_io_in_delay (0), + .a_pipe_latency (0), + .a_cas_latency (0), + .a_wl_latency (0), + .a_al_latency (0), + .a_register_latency (0), + .a_parity_latency (0), + .a_phy_wlat (0), + .a_dq_wl_remainder (0), + .a_ck_cmd (0), + .a_dqss (12'h40), + .a_dq_read_latency (0), + .a_dq_write_latency (0), + .a_cmd_core_to_codin (0), + .a_dq_min_core_to_codin (0), + .a_dq_rem_core_to_codin (0), + .a_struct_gate_delay (8'h0b), + .a_cmd_pipe_latency (0), + .a_cmd_add_phy_delay (0), + .a_mode_output ("oct_delayed"), + .a_dq_min_output_phase (0), + .a_cmd_min_output_phase (0), + + .a_lane_ddr_mode (lane_ddr_mode), + .a_lane_pin0_ddr_mode (`_map_lane_pin_ddr_mode(0)), + .a_lane_pin1_ddr_mode (`_map_lane_pin_ddr_mode(1)), + .a_lane_pin2_ddr_mode (`_map_lane_pin_ddr_mode(2)), + .a_lane_pin3_ddr_mode (`_map_lane_pin_ddr_mode(3)), + .a_lane_pin4_ddr_mode (`_map_lane_pin_ddr_mode(4)), + .a_lane_pin5_ddr_mode (`_map_lane_pin_ddr_mode(5)), + .a_lane_pin6_ddr_mode (`_map_lane_pin_ddr_mode(6)), + .a_lane_pin7_ddr_mode (`_map_lane_pin_ddr_mode(7)), + .a_lane_pin8_ddr_mode (`_map_lane_pin_ddr_mode(8)), + .a_lane_pin9_ddr_mode (`_map_lane_pin_ddr_mode(9)), + .a_lane_pin10_ddr_mode (`_map_lane_pin_ddr_mode(10)), + .a_lane_pin11_ddr_mode (`_map_lane_pin_ddr_mode(11)), + + .a_lane_mode (lane_mode), + .a_lane_pin0_mode (`_map_lane_pin_mode(0)), + .a_lane_pin1_mode (`_map_lane_pin_mode(1)), + .a_lane_pin2_mode (`_map_lane_pin_mode(2)), + .a_lane_pin3_mode (`_map_lane_pin_mode(3)), + .a_lane_pin4_mode (`_map_lane_pin_mode(4)), + .a_lane_pin5_mode (`_map_lane_pin_mode(5)), + .a_lane_pin6_mode (`_map_lane_pin_mode(6)), + .a_lane_pin7_mode (`_map_lane_pin_mode(7)), + .a_lane_pin8_mode (`_map_lane_pin_mode(8)), + .a_lane_pin9_mode (`_map_lane_pin_mode(9)), + .a_lane_pin10_mode (`_map_lane_pin_mode(10)), + .a_lane_pin11_mode (`_map_lane_pin_mode(11)), + + .a_lane_lvds0_mode ("lane_lvds0_notlvds"), + .a_lane_lvds1_mode ("lane_lvds1_notlvds"), + .a_lane_lvds2_mode ("lane_lvds2_notlvds"), + .a_lane_lvds3_mode ("lane_lvds3_notlvds"), + .a_lane_lvds4_mode ("lane_lvds4_notlvds"), + .a_lane_lvds5_mode ("lane_lvds5_notlvds"), + + .a_db_hmc_or_core (db_hmc_or_core), + .a_db_db2core_registered (db_db2core_registered), + .a_db_preamble_mode (db_preamble_mode), + .a_db_data_alignment_mode (db_data_alignment_mode), + + .a_db_pin0_mode (`_map_db_pin_mode(0)), + .a_db_pin1_mode (`_map_db_pin_mode(1)), + .a_db_pin2_mode (`_map_db_pin_mode(2)), + .a_db_pin3_mode (`_map_db_pin_mode(3)), + .a_db_pin4_mode (`_map_db_pin_mode(4)), + .a_db_pin5_mode (`_map_db_pin_mode(5)), + .a_db_pin6_mode (`_map_db_pin_mode(6)), + .a_db_pin7_mode (`_map_db_pin_mode(7)), + .a_db_pin8_mode (`_map_db_pin_mode(8)), + .a_db_pin9_mode (`_map_db_pin_mode(9)), + .a_db_pin10_mode (`_map_db_pin_mode(10)), + .a_db_pin11_mode (`_map_db_pin_mode(11)), + + + .a_pin0_octrt (`_map_pin_octrt(0)), + .a_pin1_octrt (`_map_pin_octrt(1)), + .a_pin2_octrt (`_map_pin_octrt(2)), + .a_pin3_octrt (`_map_pin_octrt(3)), + .a_pin4_octrt (`_map_pin_octrt(4)), + .a_pin5_octrt (`_map_pin_octrt(5)), + .a_pin6_octrt (`_map_pin_octrt(6)), + .a_pin7_octrt (`_map_pin_octrt(7)), + .a_pin8_octrt (`_map_pin_octrt(8)), + .a_pin9_octrt (`_map_pin_octrt(9)), + .a_pin10_octrt (`_map_pin_octrt(10)), + .a_pin11_octrt (`_map_pin_octrt(11)), + + .a_pin0_initial_out (`_map_pin_initial_out(0)), + .a_pin1_initial_out (`_map_pin_initial_out(1)), + .a_pin2_initial_out (`_map_pin_initial_out(2)), + .a_pin3_initial_out (`_map_pin_initial_out(3)), + .a_pin4_initial_out (`_map_pin_initial_out(4)), + .a_pin5_initial_out (`_map_pin_initial_out(5)), + .a_pin6_initial_out (`_map_pin_initial_out(6)), + .a_pin7_initial_out (`_map_pin_initial_out(7)), + .a_pin8_initial_out (`_map_pin_initial_out(8)), + .a_pin9_initial_out (`_map_pin_initial_out(9)), + .a_pin10_initial_out (`_map_pin_initial_out(10)), + .a_pin11_initial_out (`_map_pin_initial_out(11)), + + .a_pin0_dynoct (`_map_pin_dynoct(0)), + .a_pin1_dynoct (`_map_pin_dynoct(1)), + .a_pin2_dynoct (`_map_pin_dynoct(2)), + .a_pin3_dynoct (`_map_pin_dynoct(3)), + .a_pin4_dynoct (`_map_pin_dynoct(4)), + .a_pin5_dynoct (`_map_pin_dynoct(5)), + .a_pin6_dynoct (`_map_pin_dynoct(6)), + .a_pin7_dynoct (`_map_pin_dynoct(7)), + .a_pin8_dynoct (`_map_pin_dynoct(8)), + .a_pin9_dynoct (`_map_pin_dynoct(9)), + .a_pin10_dynoct (`_map_pin_dynoct(10)), + .a_pin11_dynoct (`_map_pin_dynoct(11)), + + .a_pin0_mode_ddr (`_map_pin_mode_ddr(0)), + .a_pin1_mode_ddr (`_map_pin_mode_ddr(1)), + .a_pin2_mode_ddr (`_map_pin_mode_ddr(2)), + .a_pin3_mode_ddr (`_map_pin_mode_ddr(3)), + .a_pin4_mode_ddr (`_map_pin_mode_ddr(4)), + .a_pin5_mode_ddr (`_map_pin_mode_ddr(5)), + .a_pin6_mode_ddr (`_map_pin_mode_ddr(6)), + .a_pin7_mode_ddr (`_map_pin_mode_ddr(7)), + .a_pin8_mode_ddr (`_map_pin_mode_ddr(8)), + .a_pin9_mode_ddr (`_map_pin_mode_ddr(9)), + .a_pin10_mode_ddr (`_map_pin_mode_ddr(10)), + .a_pin11_mode_ddr (`_map_pin_mode_ddr(11)), + + .a_pin0_dqs_mode (`_map_pin_dqs_mode(0)), + .a_pin1_dqs_mode (`_map_pin_dqs_mode(1)), + .a_pin2_dqs_mode (`_map_pin_dqs_mode(2)), + .a_pin3_dqs_mode (`_map_pin_dqs_mode(3)), + .a_pin4_dqs_mode (`_map_pin_dqs_mode(4)), + .a_pin5_dqs_mode (`_map_pin_dqs_mode(5)), + .a_pin6_dqs_mode (`_map_pin_dqs_mode(6)), + .a_pin7_dqs_mode (`_map_pin_dqs_mode(7)), + .a_pin8_dqs_mode (`_map_pin_dqs_mode(8)), + .a_pin9_dqs_mode (`_map_pin_dqs_mode(9)), + .a_pin10_dqs_mode (`_map_pin_dqs_mode(10)), + .a_pin11_dqs_mode (`_map_pin_dqs_mode(11)), + + .a_pin0_data_in_mode (`_map_pin_data_in_mode(0)), + .a_pin1_data_in_mode (`_map_pin_data_in_mode(1)), + .a_pin2_data_in_mode (`_map_pin_data_in_mode(2)), + .a_pin3_data_in_mode (`_map_pin_data_in_mode(3)), + .a_pin4_data_in_mode (`_map_pin_data_in_mode(4)), + .a_pin5_data_in_mode (`_map_pin_data_in_mode(5)), + .a_pin6_data_in_mode (`_map_pin_data_in_mode(6)), + .a_pin7_data_in_mode (`_map_pin_data_in_mode(7)), + .a_pin8_data_in_mode (`_map_pin_data_in_mode(8)), + .a_pin9_data_in_mode (`_map_pin_data_in_mode(9)), + .a_pin10_data_in_mode (`_map_pin_data_in_mode(10)), + .a_pin11_data_in_mode (`_map_pin_data_in_mode(11)), + + .a_pin0_gpio_differential ("pin0_gpio_single_ended"), + .a_pin1_gpio_differential ("pin1_gpio_single_ended"), + .a_pin2_gpio_differential ("pin2_gpio_single_ended"), + .a_pin3_gpio_differential ("pin3_gpio_single_ended"), + .a_pin4_gpio_differential ("pin4_gpio_single_ended"), + .a_pin5_gpio_differential ("pin5_gpio_single_ended"), + .a_pin6_gpio_differential ("pin6_gpio_single_ended"), + .a_pin7_gpio_differential ("pin7_gpio_single_ended"), + .a_pin8_gpio_differential ("pin8_gpio_single_ended"), + .a_pin9_gpio_differential ("pin9_gpio_single_ended"), + .a_pin10_gpio_differential ("pin10_gpio_single_ended"), + .a_pin11_gpio_differential ("pin11_gpio_single_ended"), + + .a_pin0_dq_in_select (`_map_pin_dq_in_select(0)), + .a_pin1_dq_in_select (`_map_pin_dq_in_select(1)), + .a_pin2_dq_in_select (`_map_pin_dq_in_select(2)), + .a_pin3_dq_in_select (`_map_pin_dq_in_select(3)), + .a_pin4_dq_in_select (`_map_pin_dq_in_select(4)), + .a_pin5_dq_in_select (`_map_pin_dq_in_select(5)), + .a_pin6_dq_in_select (`_map_pin_dq_in_select(6)), + .a_pin7_dq_in_select (`_map_pin_dq_in_select(7)), + .a_pin8_dq_in_select (`_map_pin_dq_in_select(8)), + .a_pin9_dq_in_select (`_map_pin_dq_in_select(9)), + .a_pin10_dq_in_select (`_map_pin_dq_in_select(10)), + .a_pin11_dq_in_select (`_map_pin_dq_in_select(11)), + + .a_db_afi_rlat_vlu (db_afi_rlat_vlu), + .a_db_afi_wlat_vlu (db_afi_wlat_vlu), + .a_db_sel_core_clk (db_sel_core_clk), + + .a_db_dbi_wr_en (db_dbi_wr_en), + .a_db_dbi_rd_en (db_dbi_rd_en), + .a_db_dbi_sel (db_dbi_sel), + .a_db_ptr_pipeline_depth (db_ptr_pipeline_depth), + .a_db_seq_rd_en_full_pipeline (`a_db_seq_rd_en_full_pipeline_remap(db_seq_rd_en_full_pipeline)), + + .a_pin0_output_phase (13'd0), + .a_pin1_output_phase (13'd0), + .a_pin2_output_phase (13'd0), + .a_pin3_output_phase (13'd0), + .a_pin4_output_phase (13'd0), + .a_pin5_output_phase (13'd0), + .a_pin6_output_phase (13'd0), + .a_pin7_output_phase (13'd0), + .a_pin8_output_phase (13'd0), + .a_pin9_output_phase (13'd0), + .a_pin10_output_phase (13'd0), + .a_pin11_output_phase (13'd0), + + .a_db_mrnk_write_mode (db_mrnk_write_mode), + .a_db_dbc_wb_reserved_entry (dbc_wb_reserved_entry), + + .a_db_dbc_rb_readylat_en (db_dbc_rb_readylat_en), + .a_db_dbc_wb_readylat_en (db_dbc_wb_readylat_en), + + .a_oct_size (oct_size), + .a_rd_valid_delay (rd_valid_delay), + + .a_dqs_enable_delay (dqs_enable_delay), + .a_dqs_phase_shift_b (dqs_phase_shift_b), + .a_dqs_phase_shift_a (dqs_phase_shift_a), + + .a_dll_rst_en (dll_rst_en), + .a_dll_core_updnen (dll_core_updnen), + .a_dll_ctlsel (dll_ctlsel), + .a_dll_ctl_static (dll_ctl_static) + ) lane_inst ( + .phy_clk (phy_clk), + .phy_clk_phs (phy_clk_phs), + + .phy_clk_local_early (phy_clk_local_early), + .phy_clk_local_late (phy_clk_local_late), + + .reset_n (reset_n), + .pll_locked (pll_locked), + .dll_ref_clk (dll_ref_clk), + .ioereg_locked (ioereg_locked), + + .oe_from_core (oe_from_core), + .data_from_core (data_from_core), + .data_to_core (data_to_core), + .mrnk_read_core (mrnk_read_core), + .mrnk_write_core (mrnk_write_core), + .rdata_en_full_core (rdata_en_full_core), + .rdata_valid_core (rdata_valid_core), + + .core2dbc_rd_data_rdy (core2dbc_rd_data_rdy), + .core2dbc_wr_data_vld0 (core2dbc_wr_data_vld0), + .core2dbc_wr_ecc_info (core2dbc_wr_ecc_info), + .dbc2core_rd_data_vld0 (dbc2core_rd_data_vld0), + + .dbc2core_rd_type (dbc2core_rd_type), + .dbc2core_wb_pointer (dbc2core_wb_pointer), + .dbc2core_wr_data_rdy (dbc2core_wr_data_rdy), + + .ac_hmc (ac_hmc), + .afi_rlat_core (afi_rlat_core), + .afi_wlat_core (afi_wlat_core), + .cfg_dbc (cfg_dbc), + .ctl2dbc0 (ctl2dbc0), + .ctl2dbc1 (ctl2dbc1), + .dbc2ctl (dbc2ctl), + + .cal_avl_in (cal_avl_in), + .cal_avl_readdata_out (cal_avl_readdata_out), + .cal_avl_out (cal_avl_out), + .cal_avl_readdata_in (cal_avl_readdata_in), + + .dqs_in (dqs_in), + .broadcast_in_bot (broadcast_in_bot), + .broadcast_in_top (broadcast_in_top), + .broadcast_out_bot (broadcast_out_bot), + .broadcast_out_top (broadcast_out_top), + + .data_in (data_in), + .data_out (data_out), + .data_oe (data_oe), + .oct_enable (oct_enable), + + .core_dll (core_dll), + .dll_core (dll_core), + + .sync_clk_bot_in (sync_clk_bot_in), + .sync_clk_bot_out (sync_clk_bot_out), + .sync_clk_top_in (sync_clk_top_in), + .sync_clk_top_out (sync_clk_top_out), + .sync_data_bot_in (sync_data_bot_in), + .sync_data_bot_out (sync_data_bot_out), + .sync_data_top_in (sync_data_top_in), + .sync_data_top_out (sync_data_top_out), + + .dft_phy_clk (dft_phy_clk) + ); +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm3g0SiPR8kcBjSVqQUz5PhpyZlwQ0KE7yFCmS6UWWe6bYAtJe7R/CNCtXSfgRYjdyzTvn3hpT6XEuKJxVexm4sgKWi4fEBb2SYQcUMoty4NUzeyiKLKqJ8JoSO1tLz5y7YNTd/tTEX9XPflI5Wj1IJ7bRKo1Igi9hwG5VEL7LxXmlzfFkmP7zA3z8zQRgNkPrYvcYKwqA+8Ir5j64R8nZEsTD7DJFwlvvBGjSin5gFoAOZYEi/nJbQCW3M0s71wazi5WBL0QZrhIDyzhN5aQh2lDClozFaDCfCzdtcl/CZjKZ/hm+epLPKEj0pE4upDXeYPPbScqgzLrtj8IaZUobImsxrYFUccYOmEkIcAtykXuJGdPp1VhuzdbQZzSUORxUxHoD2bF/R8VW9rZFmcAV4WJ4WHJdFjPeZgNjTSn27d+p8V8SzLJ79XgNtCt5aBPfexMu5fQE9p/2aVBS4PvNVkF004IuXR3gmU8aQNq7qbz6WkU4XOEakacu3Bw4ZYWcJhpFhcCGUVg2VaQdT4VlIvwAHKudsJj93MfUZwuLR5mI7VWk37xQ/+QNrwgsc3k+WCnOUHJ52JlsHkKF5KoiT6JrmjOvsOYmV5nwCr94QJ2bRjKmnk4HD0M8b5gXy+IIfTkq7n1tGzd2smxz0rKOI1EiWucV+wrjDZyrUFUugUSyGTFcv8XOIJbf+JZ2Irjf0apfAQ2Q4qn1Th3aHCPVFn3f956kDnZG9UgERbQCBBF5C9/URKfU9CkAoxChlK1lkBnGGRBBJ5ZeJgEl96Nl9P" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles.sv new file mode 100644 index 0000000000..e674293226 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles.sv @@ -0,0 +1,2110 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module instantiates one or more x48 I/O tiles (along with +// the necessary x12 I/O lanes) that are required to build as single EMIF. +// +/////////////////////////////////////////////////////////////////////////////// + +// Index to signal buses used to implement a daisy chain of +// (L0->L1->T0->L2->L3)->(L0->L1->T1->L2->L3)->... +`define _get_chain_index_for_tile(_tile_i) ( _tile_i * (LANES_PER_TILE + 1) + 2 ) + +`define _get_chain_index_for_lane(_tile_i, _lane_i) ( (_lane_i < 2) ? (_tile_i * (LANES_PER_TILE + 1) + _lane_i) : ( \ + (_tile_i * (LANES_PER_TILE + 1) + _lane_i + 1 )) ) + +// Index to signal buses used to implement a daisy chain of +// (L0->L1->L2->L3)->(L0->L1->L2->L3)->... +`define _get_broadcast_chain_index(_tile_i, _lane_i) ( _tile_i * LANES_PER_TILE + _lane_i ) + +`define _get_lane_usage(_tile_i, _lane_i) ( LANES_USAGE[(_tile_i * LANES_PER_TILE + _lane_i) * 3 +: 3] ) + +`define _get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) ( PINS_OCT_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i)] ) + +`define _get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) ( PINS_RATE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ) +`define _get_pin_ddr_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) == PIN_RATE_DDR ? "mode_ddr" : "mode_sdr" ) + +`define _get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) ( LANE_PIN_USAGE[((_tile_i * LANES_PER_TILE * PINS_PER_LANE) + (_lane_i * PINS_PER_LANE) + _pin_i) * 4 +: 4] ) + +`define _get_lane_ddr_mode_str(_tile_i, _lane_i) ( `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_UNUSED ? "lane_ddr_notddr" : ( \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_HMC ? "lane_ddr_ca_sdr" : ( \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_CORE ? ((PROTOCOL_ENUM == "PROTOCOL_QDR4") ? "lane_ddr_ca_ddr" : "lane_ddr_ca_sdr") : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? "lane_ddr_ddr2x4" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV" ? "lane_ddr_qdrx10" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X18_DINV" ? "lane_ddr_qdrx10" : ( \ + "lane_ddr_ddrx8" ))))))) + +`define _get_dqs_group_width ( DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? "x4" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? "x8" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV" ? "x8" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" ? "x16" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X18_DINV" ? "x16" : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X32_X36" ? "x32" : ( \ + "x8" ))))))) + +`define _get_lane_pin_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_UNUSED ? "pin_unused" : "pin_ddr" ) +`define _get_lane_pin_ddr_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_UNUSED ? "ddr_notddr" : ( \ + `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_DQ ? "ddr_dq" : ( \ + `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_DQS ? "ddr_dqs" : ( \ + `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_DQSB ? "ddr_dqsb" : ( \ + `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_CA_SDR ? "ddr_ca_sdr" : ( \ + `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_CA_DDR ? "ddr_ca_ddr" : ( \ + `_get_lane_pin_usage_raw(_tile_i, _lane_i, _pin_i) == LANE_PIN_USAGE_MODE_DM ? "ddr_dm" : ( \ + "ddr_notddr" )))))))) + + +`define _get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) ( DB_PINS_PROC_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 5 +: 5] ) +`define _get_db_pin_proc_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_AC_CORE ? "ac_core" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_AC_IN_CORE ? "ac_in_core" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_AC ? "ac_hmc" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_DQ ? "dq_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_DBI ? "dbi_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_DM ? "dm_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_CLK ? "clk_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_CLKB ? "clkb_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_DQS ? "dqs_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_WDB_DQSB ? "dqsb_wdb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DQS ? "dqs_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DQSB ? "dqsb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DQ ? "dq_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DM ? "dm_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DBI ? "dbi_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_CLK ? "clk_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_CLKB ? "clkb_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DQS_DDR4 ? "dqs_ddr4_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_DQSB_DDR4 ? "dqsb_ddr4_mode": ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_RDQ ? "rdq_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_RDQS ? "rdqs_mode" : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_GPIO ? "gpio_mode" : ( \ + "dq_mode" ))))))))))))))))))))))) + +`define _get_pin_oct_rt_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_STATIC_OFF ? "static_oct_off" : ( \ + `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_DYNAMIC ? "static_oct_off" : ( \ + "static_oct_on" ))) + +`define _get_pin_dyn_oct_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_DYNAMIC ? "dyn_oct_on" : ( \ + "dyn_oct_off" )) + +`define _get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) ( PINS_DATA_IN_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 3 +: 3] ) + +`define _get_pin_data_in_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DISABLED ? "dq" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_SSTL_IN ? "dq" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_LOOPBACK_IN ? "dq" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_XOR_LOOPBACK_IN ? "dq" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN ? "dq" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN_AVL_OUT ? "dq" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN_X12_OUT ? "dq" : ( \ + "dqs" )))))))) + +`define _get_pin_dqs_mode_str(_tile_i, _lane_i, _pin_i) ( (PROTOCOL_ENUM == "PROTOCOL_QDR2") ? "dqs_sampler_b_a_rise" : ( \ + (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") && (_pin_i > 5) ? "dqs_sampler_b" : ( \ + "dqs_sampler_a" ))) + +// Given the tile and lane index of a lane, returns the index of the AC tile controlling +// this lane. For non-ping-pong, return value is always PRI_AC_TILE_INDEX. +// For ping-pong, return SEC_AC_TILE_INDEX for all tiles below tile at SEC_AC_TILE_INDEX, +// and for lane 2 and 3 of tile SEC_AC_TILE_INDEX; return PRI_AC_TILE_INDEX otherwise. +// This assumption must be consistent with the logical pin placement strategy in hwtcl. +`define _get_ac_tile_index(_tile_i, _lane_i) ( (PHY_PING_PONG_EN && (_tile_i < SEC_AC_TILE_INDEX || (_tile_i == SEC_AC_TILE_INDEX && _lane_i < 2))) ? SEC_AC_TILE_INDEX : PRI_AC_TILE_INDEX ) + +// The following account for latency incurred when cross tile boundaries +`define _get_dbc_pipe_lat(_tile_i, _lane_i) ( DBC_PIPE_LATS[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] ) +`define _get_db_ptr_pipe_depth_str(_tile_i, _lane_i) ( DB_PTR_PIPELINE_DEPTHS[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] == 4'b0000 ? "db_ptr_pipeline_depth_0" : \ + DB_PTR_PIPELINE_DEPTHS[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] == 4'b0001 ? "db_ptr_pipeline_depth_1" : \ + DB_PTR_PIPELINE_DEPTHS[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] == 4'b0010 ? "db_ptr_pipeline_depth_2" : \ + DB_PTR_PIPELINE_DEPTHS[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] == 4'b0011 ? "db_ptr_pipeline_depth_3" : \ + DB_PTR_PIPELINE_DEPTHS[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] == 4'b0100 ? "db_ptr_pipeline_depth_4" : \ + "db_ptr_pipeline_depth_0") + +`define _get_db_seq_rd_en_full_pipeline_raw(_tile_i, _lane_i) ( DB_SEQ_RD_EN_FULL_PIPELINES[(_tile_i * LANES_PER_TILE + _lane_i) * 4 +: 4] ) +`define _get_db_seq_rd_en_full_pipeline_str(_tile_i, _lane_i) ( `_get_db_seq_rd_en_full_pipeline_raw(_tile_i, _lane_i) == 4'b0001 ? "db_seq_rd_en_full_pipeline_1" : \ + `_get_db_seq_rd_en_full_pipeline_raw(_tile_i, _lane_i) == 4'b0010 ? "db_seq_rd_en_full_pipeline_2" : \ + `_get_db_seq_rd_en_full_pipeline_raw(_tile_i, _lane_i) == 4'b0011 ? "db_seq_rd_en_full_pipeline_3" : \ + `_get_db_seq_rd_en_full_pipeline_raw(_tile_i, _lane_i) == 4'b0100 ? "db_seq_rd_en_full_pipeline_4" : \ + `_get_db_seq_rd_en_full_pipeline_raw(_tile_i, _lane_i) == 4'b0000 ? "db_seq_rd_en_full_pipeline_0" : \ + "db_seq_rd_en_full_pipeline_1") + +`define _get_db_data_alignment_mode ( (NUM_OF_HMC_PORTS > 0) ? "align_ena" : "align_disable" ) + +`define _get_memory_standard ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "ddr4" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "qdriv" : ( \ + "rldram3" ))) + +`define _get_lane_mode_rate_in ( PHY_HMC_CLK_RATIO == 4 ? "in_rate_1_4" : ( \ + PHY_HMC_CLK_RATIO == 2 ? "in_rate_1_2" : ( \ + "in_rate_full" ))) + +`define _get_lane_mode_rate_out ( PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 8 ? "out_rate_1_8" : ( \ + PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 4 ? "out_rate_1_4" : ( \ + PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 2 ? "out_rate_1_2" : ( \ + "out_rate_full" )))) + +`define _get_hmc_ctrl_mem_type ( PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "mem_type_ddr3" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "mem_type_ddr4" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "mem_type_default" : ( \ + "mem_type_lpddr3" )))) + +`define _get_hmc_or_smc ( NUM_OF_HMC_PORTS == 0 ? "smc" : "hmc" ) +`define _get_hmc_or_core ( NUM_OF_HMC_PORTS == 0 ? "db_core" : "db_hmc" ) +`define _get_hmc_or_core_physeq ( NUM_OF_HMC_PORTS == 0 ? "core" : "hmc" ) + +`define _get_hmc_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "ctrl_cfg_cmd_rate_qr" : "ctrl_cfg_cmd_rate_hr" ) +`define _get_dbc0_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "dbc0_cfg_cmd_rate_qr" : "dbc0_cfg_cmd_rate_hr" ) +`define _get_dbc1_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "dbc1_cfg_cmd_rate_qr" : "dbc1_cfg_cmd_rate_hr" ) +`define _get_dbc2_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "dbc2_cfg_cmd_rate_qr" : "dbc2_cfg_cmd_rate_hr" ) +`define _get_dbc3_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "dbc3_cfg_cmd_rate_qr" : "dbc3_cfg_cmd_rate_hr" ) + +`define _get_hmc_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "ctrl_amm" : "ctrl_ast" ) +`define _get_dbc0_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "dbc0_amm" : "dbc0_ast" ) +`define _get_dbc1_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "dbc1_amm" : "dbc1_ast" ) +`define _get_dbc2_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "dbc2_amm" : "dbc2_ast" ) +`define _get_dbc3_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "dbc3_amm" : "dbc3_ast" ) + +`define _get_memory_burst_length ( PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "bl2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "bl2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "bl2" : ( \ + MEM_BURST_LENGTH == 2 ? "bl2" : ( \ + MEM_BURST_LENGTH == 4 ? "bl4" : ( \ + MEM_BURST_LENGTH == 8 ? "bl8" : ( \ + "" ))))))) + +`define _get_cpa_0_clk_divider ( (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 1 ? "core_clk0_div1" : ( \ + (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 2 ? "core_clk0_div2" : ( \ + (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 4 ? "core_clk0_div4" : ( \ + (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 8 ? "core_clk0_div8" : ( \ + (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 16 ? "core_clk0_div16" : ( \ + (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 32 ? "core_clk0_div32" : ( \ + (USER_CLK_RATIO * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 64 ? "core_clk0_div64" : ( \ + "core_clk0_div1" )))))))) + +// CPA output 0 - in HMC mode, matches emif_usr_clk; in non-HMC mode, since afi_half_clk is no longer used in FM, use the same clock ratio +`define _get_cpa_0_clk_ratio ( NUM_OF_HMC_PORTS > 0 ? USER_CLK_RATIO : (USER_CLK_RATIO) ) + +// CPA output 1 - always matches the C2P/P2C rate +`define _get_cpa_1_clk_ratio ( C2P_P2C_CLK_RATIO ) +`define _get_pa_exponent_1 ( (`_get_pa_exponent(`_get_cpa_1_clk_ratio)) ) + +// CPA output 0 - clock divider on PHY clock feedback. +// Enable divide-by-2 whenever the core clock needs to run at half the speed of the feedback clock +`define _get_pa_feedback_divider_p0 ( (`_get_cpa_0_clk_ratio == C2P_P2C_CLK_RATIO * 2) ? "fb_clk0_div2" : "fb_clk0_div1" ) + +// CPA output 0 - clock divider on core clock feedback. +// Enable divide-by-2 whenever the core clock needs to run at 2x the speed of the feedback clock +`define _get_pa_feedback_divider_c0 ( (`_get_cpa_0_clk_ratio * 2 == C2P_P2C_CLK_RATIO) ? "core_clk0_div2" : "core_clk0_div1" ) + +`define _get_dqsin(_tile_i, _lane_i) ( (`_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_RDATA && `_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_WDATA && `_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_WRDATA) ? 2'b0 : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? t2l_dqsbus_x4[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? t2l_dqsbus_x8[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV" ? t2l_dqsbus_x8[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" ? t2l_dqsbus_x18[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X18_DINV" ? t2l_dqsbus_x18[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X32_X36" ? t2l_dqsbus_x36[_lane_i] : ( \ + 2'b0 )))))))) + +`define _get_hmc_burst_length ( MEM_BURST_LENGTH == 2 ? 5'b00010 : ( \ + MEM_BURST_LENGTH == 4 ? 5'b00100 : ( \ + MEM_BURST_LENGTH == 8 ? 5'b01000 : ( \ + 5'b00000 )))) + +// DBC Mux Scheme (non-ping-pong): +// +// Tiles above : switch0 = don't-care dbc*_sel = switch1 (lower mux) +// switch1 = from lower +// +// AC Tile : switch0 = local dbc*_sel = switch0 (upper mux) +// switch1 = local +// +// Tiles below : switch0 = from upper dbc*_sel = switch0 (upper mux) +// switch1 = don't-care +// +`define _get_ctrl2dbc_switch_0_non_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_tile_dbc0" : ( \ + "lower_tile_dbc0" ))) + +`define _get_ctrl2dbc_switch_1_non_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc1" : ( \ + (_tile_i > PRI_AC_TILE_INDEX) ? "lower_tile_dbc1" : ( \ + "upper_tile_dbc1" ))) + +`define _get_ctrl2dbc_sel_0_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc0" : "lower_mux_dbc0" ) +`define _get_ctrl2dbc_sel_1_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc1" : "lower_mux_dbc1" ) +`define _get_ctrl2dbc_sel_2_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc2" : "lower_mux_dbc2" ) +`define _get_ctrl2dbc_sel_3_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc3" : "lower_mux_dbc3" ) + +// DBC Mux Scheme (ping-pong): +// +// Tiles above : switch0 = don't-care dbc*_sel = switch1 (lower mux) +// switch1 = from lower +// +// Primary AC Tile : switch0 = local dbc*_sel = switch1 (lower mux) +// switch1 = local +// +// Secondary AC Tile: switch0 = local dbc2_sel, dbc3_sel = switch0 (upper mux) +// switch1 = from upper dbc0_sel, dbc1_sel = switch1 (lower mux) +// +// Tiles below : switch0 = from upper dbc*_sel = switch0 (upper mux) +// switch1 = don't-care +// +`define _get_ctrl2dbc_switch_0_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i == SEC_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i < SEC_AC_TILE_INDEX) ? "upper_tile_dbc0" : ( \ + "lower_tile_dbc0" )))) + +`define _get_ctrl2dbc_switch_1_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc1" : ( \ + (_tile_i == SEC_AC_TILE_INDEX) ? "upper_tile_dbc1" : ( \ + (_tile_i > PRI_AC_TILE_INDEX) ? "lower_tile_dbc1" : ( \ + "upper_tile_dbc1" )))) + +`define _get_ctrl2dbc_sel_0_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc0" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc0" : (`_get_ac_tile_index(_tile_i, 0) == PRI_AC_TILE_INDEX ? "lower_mux_dbc0" : "upper_mux_dbc0")) ) +`define _get_ctrl2dbc_sel_1_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc1" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc1" : (`_get_ac_tile_index(_tile_i, 1) == PRI_AC_TILE_INDEX ? "lower_mux_dbc1" : "upper_mux_dbc1")) ) +`define _get_ctrl2dbc_sel_2_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc2" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc2" : (`_get_ac_tile_index(_tile_i, 2) == PRI_AC_TILE_INDEX ? "lower_mux_dbc2" : "upper_mux_dbc2")) ) +`define _get_ctrl2dbc_sel_3_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc3" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc3" : (`_get_ac_tile_index(_tile_i, 3) == PRI_AC_TILE_INDEX ? "lower_mux_dbc3" : "upper_mux_dbc3")) ) + +// DBC Mux Scheme (ping-pong and non-ping-pong) +`define _get_ctrl2dbc_switch_0(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_switch_0_pp(_tile_i) : `_get_ctrl2dbc_switch_0_non_pp(_tile_i) ) +`define _get_ctrl2dbc_switch_1(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_switch_1_pp(_tile_i) : `_get_ctrl2dbc_switch_1_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_0(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_0_pp(_tile_i) : `_get_ctrl2dbc_sel_0_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_1(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_1_pp(_tile_i) : `_get_ctrl2dbc_sel_1_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_2(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_2_pp(_tile_i) : `_get_ctrl2dbc_sel_2_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_3(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_3_pp(_tile_i) : `_get_ctrl2dbc_sel_3_non_pp(_tile_i) ) + +// Select which DBC to use as shadow. +// For the primary HMC tile or non-Ping-Pong HMC tile, pick "dbc1_to_local" as it's guaranteed to be used by the interface (as an A/C lane). +// For the secondary HMC tile, which one we pick depends on which data lane in the tile belongs to the secondary interface. +`define _get_hmc_dbc2ctrl_sel_non_pp(_tile_i) ( PRI_HMC_DBC_SHADOW_LANE_INDEX == 0 ? "dbc0_to_local" : ( \ + PRI_HMC_DBC_SHADOW_LANE_INDEX == 1 ? "dbc1_to_local" : ( \ + PRI_HMC_DBC_SHADOW_LANE_INDEX == 2 ? "dbc2_to_local" : ( \ + "dbc3_to_local" )))) + +`define _get_hmc_dbc2ctrl_sel_pp(_tile_i) ( (_tile_i != SEC_AC_TILE_INDEX) ? `_get_hmc_dbc2ctrl_sel_non_pp(_tile_i) : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 0) == SEC_AC_TILE_INDEX) ? "dbc0_to_local" : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 1) == SEC_AC_TILE_INDEX) ? "dbc1_to_local" : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 2) == SEC_AC_TILE_INDEX) ? "dbc2_to_local" : ( \ + "dbc3_to_local" ))))) +`define _get_hmc_dbc2ctrl_sel(_tile_i) ( PHY_PING_PONG_EN ? `_get_hmc_dbc2ctrl_sel_pp(_tile_i) : `_get_hmc_dbc2ctrl_sel_non_pp(_tile_i) ) + +// ac_hmc is hard connectivity between HMC and A/C lanes +// The Fitter uses ac_hmc as a special connection to locate the A/C tile and lanes, regardless of whether HMC is used. +// Normally, we only connect these to lanes that are used as A/C, regardless of HMC or SMC. +`define _get_ac_hmc(_tile_i, _lane_i) ( (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_HMC || \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_CORE) ? \ + t2l_ac_hmc[lane_i] : 96'b0 ) + +// The following is evaluated for simulation. Don't wait too long during simulation. +`define _get_core2dbc_wr_data_vld(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + core2l_wr_data_vld_ast[_tile_i][_lane_i] : 1'b0 ) + +`define _get_core2dbc_wr_ecc_info(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + core2l_wr_ecc_info[_tile_i][_lane_i] : 13'b0 ) + +`define _get_core2dbc_rd_data_rdy(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + core2l_rd_data_rdy_ast[_tile_i][_lane_i] : 1'b1 ) + +// core2dbc_rd_data_rdy needs to fanout to every data lane and also the lane denoted as shadow by _get_hmc_dbc2ctrl_sel +`define _get_center_tid(_tile_i) ( CENTER_TIDS[_tile_i * 9 +: 9] ) +`define _get_hmc_tid(_tile_i) ( HMC_TIDS[_tile_i * 9 +: 9] ) +`define _get_lane_tid(_tile_i, _lane_i) ( LANE_TIDS[(_tile_i * LANES_PER_TILE + _lane_i) * 9 +: 9] ) + +`define _get_preamble_track_dqs_enable_mode ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "preamble_track_toggler" : ( \ + "" ))))))) + +`define _get_pst_preamble_mode ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "ddr4_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "ddr3_preamble" : ( \ + "" ))))))) +`define _get_pst_en_shrink ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "shrink_1_0" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "shrink_1_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "shrink_1_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "shrink_0_1" : ( \ + "" ))))))) + +`define _get_pa_filter_code ( "freq_1600" ) + +`define _get_a_filter_code ( "freq_16ghz" ) + +`define _get_pa_track_speed ( 5'h0c ) + +// Enable the per-lane hard DBI circuitry. Only intended to be used by DDR4 data lanes. +`define _get_dbi_wr_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? DBI_WR_ENABLE : "dbi_wr_dis") +`define _get_dbi_rd_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? DBI_RD_ENABLE : "dbi_rd_dis") + +// Set it to enabled to data lanes (or multi-rank shadow would not work). +// Set it to disabled for address/command lanes. +`define _get_data_lane(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WDATA) || \ + (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_RDATA)) ? 1 : 0 ) + +`define _get_mrnk_write_mode(_tile_i, _lane_i) ( (`_get_data_lane(_tile_i, _lane_i) == 1) ? "mrnk_write_enable" : "mrnk_write_disable" ) + +// Controls how early/late to enable Rt termination. +// Decimal to binary conversion required by Quartus. +`define _get_oct_size ( (OCT_SIZE == 0 ) ? 4'b0000 : ( \ + (OCT_SIZE == 1 ) ? 4'b0001 : ( \ + (OCT_SIZE == 2 ) ? 4'b0010 : ( \ + (OCT_SIZE == 3 ) ? 4'b0011 : ( \ + (OCT_SIZE == 4 ) ? 4'b0100 : ( \ + (OCT_SIZE == 5 ) ? 4'b0101 : ( \ + (OCT_SIZE == 6 ) ? 4'b0110 : ( \ + (OCT_SIZE == 7 ) ? 4'b0111 : ( \ + (OCT_SIZE == 8 ) ? 4'b1000 : ( \ + (OCT_SIZE == 9 ) ? 4'b1001 : ( \ + (OCT_SIZE == 10) ? 4'b1010 : ( \ + (OCT_SIZE == 11) ? 4'b1011 : ( \ + (OCT_SIZE == 12) ? 4'b1100 : ( \ + (OCT_SIZE == 13) ? 4'b1101 : ( \ + (OCT_SIZE == 14) ? 4'b1110 : ( \ + 4'b1111 )))))))))))))))) + +`define _get_hmc_cb_tbp_reload_fix_en_n ((PRI_HMC_3DS_EN == "enable") ? "disable" : "enable") + +// Select primary or secondary HMC config +// For non-ping-pong and primary HMC of ping-pong, select primary +// For secondary HMC of ping-pong, select secondary +// For everything else, select primary +`define _sel_hmc_tile(_tile_i, _pri, _sec) ( PHY_PING_PONG_EN ? (_tile_i <= SEC_AC_TILE_INDEX ? _sec : _pri) : _pri ) + +// Select primary/secondary/default HMC config +// For non-ping-pong and primary HMC of ping-pong, select primary +// For secondary HMC of ping-pong, select secondary +// For everything else, select default +`define _sel_hmc_default(_tile_i, _pri, _sec, _def) (_tile_i == SEC_AC_TILE_INDEX) ? _sec : ((_tile_i == PRI_AC_TILE_INDEX) ? _pri : _def) + +// Select primary or secondary HMC config, with lane dependence +// For non-ping-pong and primary HMC of ping-pong, select primary +// For secondary HMC of ping-pong, select primary or secondary based on lane affiliation +`define _sel_hmc_lane(_tile_i, _lane_i, _pri, _sec) ( (PHY_PING_PONG_EN && (_tile_i < SEC_AC_TILE_INDEX || (_tile_i == SEC_AC_TILE_INDEX && _lane_i < 2))) ? _sec : _pri ) + +module altera_emif_arch_fm_io_tiles #( + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_SEQ_RESET_AUTO_RELEASE = "avl", + parameter DIAG_DB_RESET_AUTO_RELEASE = "avl_release", + parameter IS_HPS = 0, + parameter SILICON_REV = "", + parameter PROTOCOL_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_MEM_CLK_FREQ_PS = 0, + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter LANES_IN_RTL_TILES = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + parameter PHY_MIMIC_HPS_EMIF = 0, + parameter CPA_FB_MUX_1_SEL = "", + + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter PRI_HMC_CFG_CS_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_COL_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_RC = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter [ 1: 0] PRI_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter [ 31: 0] PRI_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 31: 0] PRI_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter PRI_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 7: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter [ 31: 0] PRI_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter PRI_HMC_CFG_DQSTRK_EN = "", + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 31: 0] PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter [ 31: 0] PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter [ 31: 0] PRI_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 7: 0] PRI_HMC_MEMCLKGATE_SETTING = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_AL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCCD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCCD_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCKESR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCKSRX = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCWL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TDQSCKMAX = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TFAW = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TMOD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TPL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRAS = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRCD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TREFI = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRFC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRRD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRRD_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRTP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXPDLL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXSR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TZQCS = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TZQOPER = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_WR_CRC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 9: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter [ 1: 0] PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter [ 31: 0] PRI_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter [ 31: 0] PRI_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter PRI_HMC_CFG_MAJOR_MODE_EN = "", + parameter [ 1: 0] PRI_HMC_CFG_REFRESH_TYPE = 0, + parameter PRI_HMC_CFG_POST_REFRESH_EN = "", + parameter [ 4: 0] PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter [ 4: 0] PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter PRI_HMC_CFG_PRE_REFRESH_EN = "", + parameter [ 3: 0] PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter [ 8: 0] PRI_HMC_CHIP_ID = 0, + parameter [ 1: 0] PRI_HMC_CID_ADDR_WIDTH = 0, + parameter PRI_HMC_3DS_EN = "", + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM0 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM1 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM2 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM3 = 0, + parameter PRI_HMC_3DS_PR_STAG_ENABLE = "", + parameter [ 6: 0] PRI_HMC_3DS_REF2REF_DLR = 0, + parameter PRI_HMC_3DSREF_ACK_ON_DONE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter SEC_HMC_CFG_CS_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_COL_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_RC = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter [ 1: 0] SEC_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter [ 31: 0] SEC_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 31: 0] SEC_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter SEC_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 7: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter [ 31: 0] SEC_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter SEC_HMC_CFG_DQSTRK_EN = "", + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 31: 0] SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter [ 31: 0] SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter [ 31: 0] SEC_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 7: 0] SEC_HMC_MEMCLKGATE_SETTING = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_AL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCCD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCCD_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCKESR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCKSRX = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCWL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TDQSCKMAX = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TFAW = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TMOD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TPL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRAS = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRCD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TREFI = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRFC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRRD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRRD_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRTP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXPDLL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXSR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TZQCS = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TZQOPER = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_WR_CRC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 9: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter [ 1: 0] SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter [ 31: 0] SEC_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter [ 31: 0] SEC_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter SEC_HMC_CFG_MAJOR_MODE_EN = "", + parameter [ 1: 0] SEC_HMC_CFG_REFRESH_TYPE = 0, + parameter SEC_HMC_CFG_POST_REFRESH_EN = "", + parameter [ 4: 0] SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter [ 4: 0] SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter SEC_HMC_CFG_PRE_REFRESH_EN = "", + parameter [ 3: 0] SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter [ 8: 0] SEC_HMC_CHIP_ID = 0, + parameter [ 1: 0] SEC_HMC_CID_ADDR_WIDTH = 0, + parameter SEC_HMC_3DS_EN = "", + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM0 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM1 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM2 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM3 = 0, + parameter SEC_HMC_3DS_PR_STAG_ENABLE = "", + parameter [ 6: 0] SEC_HMC_3DS_REF2REF_DLR = 0, + parameter SEC_HMC_3DSREF_ACK_ON_DONE = "", + + parameter PORT_CALBUS_ADDRESS_WIDTH = 1, + parameter PORT_CALBUS_RDATA_WIDTH = 1, + parameter PORT_CALBUS_WDATA_WIDTH = 1, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 1, + + parameter SEQ_PT_CONTENT = "", + parameter LANES_USAGE = 0, + parameter PINS_USAGE = 0, + parameter LANE_PIN_USAGE = 0, + parameter PINS_RATE = 0, + parameter DB_PINS_PROC_MODE = 0, + parameter PINS_DATA_IN_MODE = 0, + parameter PINS_OCT_MODE = 0, + parameter PINS_DCC_SPLIT = 0, + parameter CENTER_TIDS = 0, + parameter HMC_TIDS = 0, + parameter LANE_TIDS = 0, + parameter DBC_EXTRA_PIPE_STAGE_EN = "", + parameter DBC_PIPE_LATS = 0, + parameter DB_PTR_PIPELINE_DEPTHS = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES = 0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = "", + parameter DQSA_LGC_MODE = "", + parameter DQSB_LGC_MODE = "", + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter [10:0] DLL_CODEWORD = 0, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH = 1, + + parameter DIAG_USE_ABSTRACT_PHY = 0 +) ( + // Reset related + input logic core2seq_reset_req, // For abstract phy support + + // Signals for various signals from PLL + input logic pll_locked, // Indicates PLL lock status + input logic pll_dll_clk, // PLL -> DLL output clock + input logic [7:0] phy_clk_phs, // FR PHY clock signals (8 phases, 45-deg apart) + input logic [1:0] phy_clk, // {phy_clk[1], phy_clk[0]} + input logic phy_fb_clk_to_tile, // PHY feedback clock (to tile) + output logic phy_fb_clk_to_pll_nonabphy, // PHY feedback clock (to PLL) + + output logic [1:0] global_phy_clk, // {phy_clk[1], phy_clk[0]} + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + output logic [1:0] core_clks_from_cpa_pri_nonabphy, // Core clock signals from the CPA of primary interface + output logic [1:0] core_clks_locked_cpa_pri_nonabphy, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_fb_to_cpa_pri, // Core clock feedback signals to the CPA of primary interface + output logic [1:0] core_clks_from_cpa_sec_nonabphy, // Core clock signals from the CPA of secondary interface (ping-pong only) + output logic [1:0] core_clks_locked_cpa_sec_nonabphy, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_fb_to_cpa_sec, // Core clock feedback signals to the CPA of secondary interface (ping-pong only) + + // Avalon interfaces between core and HMC + input logic [62:0] core2ctl_avl_0, + input logic [62:0] core2ctl_avl_1, + input logic core2ctl_avl_rd_data_ready_0, + input logic core2ctl_avl_rd_data_ready_1, + output logic ctl2core_avl_cmd_ready_0_nonabphy, + output logic ctl2core_avl_cmd_ready_1_nonabphy, + output logic [12:0] ctl2core_avl_rdata_id_0_nonabphy, + output logic [12:0] ctl2core_avl_rdata_id_1_nonabphy, + + // ECC signals between core and lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] core2l_wr_data_vld_ast, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] core2l_rd_data_rdy_ast, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][12:0] core2l_wr_ecc_info, + + output logic l2core_rd_type_nonabphy, + output logic l2core_rd_data_vld_avl_nonabphy, + output logic l2core_wr_data_rdy_ast_nonabphy, + output logic [11:0] l2core_wb_pointer_for_ecc_nonabphy, + + // Signals between core and data lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_nonabphy, + + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_write, + + output logic [3:0] l2core_rdata_valid_nonabphy_pri, + output logic [3:0] l2core_rdata_valid_nonabphy_sec, + output logic [5:0] l2core_afi_rlat_nonabphy, + output logic [5:0] l2core_afi_wlat_nonabphy, + + // AFI signals between tile and core + input logic [17:0] c2t_afi, + output logic [26:0] t2c_afi_nonabphy, + + // Side-band signals between core and HMC + input logic [41:0] core2ctl_sideband_0, + output logic [13:0] ctl2core_sideband_0_nonabphy, + input logic [41:0] core2ctl_sideband_1, + output logic [13:0] ctl2core_sideband_1_nonabphy, + + // MMR signals between core and HMC + output logic [33:0] ctl2core_mmr_0_nonabphy, + input logic [50:0] core2ctl_mmr_0, + output logic [33:0] ctl2core_mmr_1_nonabphy, + input logic [50:0] core2ctl_mmr_1, + + // Signals between I/O buffers and lanes/tiles + output logic [PINS_IN_RTL_TILES-1:0] l2b_data_nonabphy, // lane-to-buffer data + output logic [PINS_IN_RTL_TILES-1:0] l2b_oe_nonabphy, // lane-to-buffer output-enable + output logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_nonabphy, // lane-to-buffer dynamic-termination-control + input logic [PINS_IN_RTL_TILES-1:0] b2l_data, // buffer-to-lane data + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, // buffer-to-tile DQS + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, // buffer-to-tile DQSb + + // Avalon-MM bus for the calibration commands between IOSSM and tiles + input logic cal_bus_clk, + input logic cal_bus_avl_read, + input logic cal_bus_avl_write, + input logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] cal_bus_avl_address, + output logic [PORT_CALBUS_RDATA_WIDTH-1:0] cal_bus_avl_read_data, + input logic [PORT_CALBUS_WDATA_WIDTH-1:0] cal_bus_avl_write_data, + output logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] cal_bus_seq_param_tbl, + + // Ports for internal test and debug + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select_nonabphy, + output logic [PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_nonabphy +); + timeunit 1ns; + timeprecision 1ps; + + // Enum that defines whether a lane is used or not, and in what mode. + // This enum type is used to encode the LANES_USAGE_MODE parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + LANE_USAGE_UNUSED = 3'b000, + LANE_USAGE_AC_HMC = 3'b001, + LANE_USAGE_AC_CORE = 3'b010, + LANE_USAGE_RDATA = 3'b011, + LANE_USAGE_WDATA = 3'b100, + LANE_USAGE_WRDATA = 3'b101 + } LANE_USAGE; + + // Enum that defines whether a pin is used by EMIF + // This enum type is used to encode the PINS_USAGE parameter + // passed into the io_tiles module. + typedef enum bit [0:0] { + PIN_USAGE_UNUSED = 1'b0, + PIN_USAGE_USED = 1'b1 + } PIN_USAGE; + + // Enum that defines whether an EMIF pin operates at SDR or DDR. + // This enum type is used to encode the PINS_RATE parameter + // passed into the io_tiles module. + typedef enum bit [0:0] { + PIN_RATE_DDR = 1'b0, + PIN_RATE_SDR = 1'b1 + } PIN_RATE; + + // Enum that defines the direction of an EMIF pin. + typedef enum bit [0:0] { + PIN_OCT_STATIC_OFF = 1'b0, + PIN_OCT_DYNAMIC = 1'b1 + } PIN_OCT_MODE; + + // Enum that defines the pin usage within a lane + typedef enum bit [3:0] { + LANE_PIN_USAGE_MODE_UNUSED = 4'b0000, + LANE_PIN_USAGE_MODE_DQ = 4'b0001, + LANE_PIN_USAGE_MODE_DQS = 4'b0010, + LANE_PIN_USAGE_MODE_DQSB = 4'b0011, + LANE_PIN_USAGE_MODE_CA_SDR = 4'b0100, + LANE_PIN_USAGE_MODE_CA_DDR = 4'b0101, + LANE_PIN_USAGE_MODE_DM = 4'b1000, + LANE_PIN_USAGE_MODE_DBI = 4'b1001 + } LANE_PIN_USAGE_MODE; + + // Enum that defines the write data buffer procedural mode of an EMIF pin. + // This enum type is used to encode the DB_PINS_PROC_MODE parameter + // passed into the io_tiles module. + typedef enum bit [4:0] { + DB_PIN_PROC_MODE_AC_CORE = 5'b00000, + DB_PIN_PROC_MODE_AC_IN_CORE = 5'b10100, + DB_PIN_PROC_MODE_WDB_AC = 5'b00001, + DB_PIN_PROC_MODE_WDB_DQ = 5'b00010, + DB_PIN_PROC_MODE_WDB_DBI = 5'b00011, + DB_PIN_PROC_MODE_WDB_DM = 5'b00100, + DB_PIN_PROC_MODE_WDB_CLK = 5'b00101, + DB_PIN_PROC_MODE_WDB_CLKB = 5'b00110, + DB_PIN_PROC_MODE_WDB_DQS = 5'b00111, + DB_PIN_PROC_MODE_WDB_DQSB = 5'b01000, + DB_PIN_PROC_MODE_DQS = 5'b01001, + DB_PIN_PROC_MODE_DQSB = 5'b01010, + DB_PIN_PROC_MODE_DQ = 5'b01011, + DB_PIN_PROC_MODE_DM = 5'b01100, + DB_PIN_PROC_MODE_DBI = 5'b01101, + DB_PIN_PROC_MODE_CLK = 5'b01110, + DB_PIN_PROC_MODE_CLKB = 5'b01111, + DB_PIN_PROC_MODE_DQS_DDR4 = 5'b10000, + DB_PIN_PROC_MODE_DQSB_DDR4 = 5'b10001, + DB_PIN_PROC_MODE_RDQ = 5'b10010, + DB_PIN_PROC_MODE_RDQS = 5'b10011, + DB_PIN_PROC_MODE_GPIO = 5'b11111 + } DB_PIN_PROC_MODE; + + // Enum that defines the pin data in mode of an EMIF pin. + // This enum type is used to encode the PINS_DATA_IN_MODE parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + PIN_DATA_IN_MODE_DISABLED = 3'b000, + PIN_DATA_IN_MODE_SSTL_IN = 3'b001, + PIN_DATA_IN_MODE_LOOPBACK_IN = 3'b010, + PIN_DATA_IN_MODE_XOR_LOOPBACK_IN = 3'b011, + PIN_DATA_IN_MODE_DIFF_IN = 3'b100, + PIN_DATA_IN_MODE_DIFF_IN_AVL_OUT = 3'b101, + PIN_DATA_IN_MODE_DIFF_IN_X12_OUT = 3'b110, + PIN_DATA_IN_MODE_DIFF_IN_AVL_X12_OUT = 3'b111 + } PIN_DATA_IN_MODE; + + // Is HMC rate converter or dual-port feature turned on? + // This can be inferred from the clock rates at core/periphery boundary and in HMC. + localparam USE_HMC_RC_OR_DP = (C2P_P2C_CLK_RATIO == PHY_HMC_CLK_RATIO) ? 0 : 1; + localparam LANE_DB_CLK_SEL = USE_HMC_RC_OR_DP ? "phy_clk1" : "phy_clk0"; + + // The phase alignment blocks have synchronization signals between them + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_data_up_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_data_dn_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_clk_up_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_clk_dn_chain; + assign pa_sync_data_dn_chain[NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 1'b1; + assign pa_sync_clk_dn_chain [NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 1'b1; + assign pa_sync_data_up_chain[0] = 1'b1; + assign pa_sync_clk_up_chain [0] = 1'b1; + + // The Avalon command bus signal daisy-chains one tile to another + // from bottom-to-top starting from the I/O aux. + logic [NUM_OF_RTL_TILES-1:0][PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] tile_param_tables; + + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0][54:0] cal_bus_avl_up_chain; + assign cal_bus_avl_up_chain[0][19:0] = cal_bus_avl_address; + assign cal_bus_avl_up_chain[0][51:20] = cal_bus_avl_write_data; + assign cal_bus_avl_up_chain[0][52] = cal_bus_avl_write; + assign cal_bus_avl_up_chain[0][53] = cal_bus_avl_read; + assign cal_bus_avl_up_chain[0][54] = cal_bus_clk; + + // The Avalon read data signal daisy-chains one tile to another + // from top-to-bottom ending at the I/O aux. + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0][31:0] cal_bus_avl_read_data_dn_chain; + assign cal_bus_avl_read_data = cal_bus_avl_read_data_dn_chain[0]; + assign cal_bus_avl_read_data_dn_chain[NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 32'b0; + + // Broadcast signals that daisy-chain all lanes in upward and downward directions. + logic [(NUM_OF_RTL_TILES * LANES_PER_TILE):0][1:0] broadcast_up_chain; + logic [(NUM_OF_RTL_TILES * LANES_PER_TILE):0][1:0] broadcast_dn_chain; + assign broadcast_dn_chain[NUM_OF_RTL_TILES * LANES_PER_TILE] = 2'b11; + assign broadcast_up_chain[0] = 2'b11; + + // HMC-to-DBC signals going from tiles to lanes and between tiles + logic [NUM_OF_RTL_TILES:0][50:0] all_tiles_ctl2dbc0_dn_chain; + logic [NUM_OF_RTL_TILES:0][50:0] all_tiles_ctl2dbc1_up_chain; + assign all_tiles_ctl2dbc0_dn_chain[NUM_OF_RTL_TILES] = {51{1'b1}}; + assign all_tiles_ctl2dbc1_up_chain[0] = {51{1'b1}}; + + // Ping-Pong signals going up the column + logic [NUM_OF_RTL_TILES:0][101:0] all_tiles_ping_pong_up_chain; + assign all_tiles_ping_pong_up_chain[0] = {102{1'b1}}; + + // PHY clock signals going from tiles to lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] all_tiles_t2l_phy_clk_phs; + + logic [LANES_PER_TILE-1:0][4:0] all_tiles_t2l_phy_clk; + + // DLL clock from tile_ctrl to lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] all_tiles_dll_clk_out; + + // Outputs from the CPA inside each tile + // In the following arrays, only elements at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + // In ping-pong configuration, the CPA inside the primary HMC tile is used, hence no need to account for secondary tile + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_out; + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_fb_in; + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_locked; + + assign core_clks_from_cpa_pri_nonabphy = {1'b0, all_tiles_core_clks_out[PRI_AC_TILE_INDEX][0]}; + assign core_clks_locked_cpa_pri_nonabphy = all_tiles_core_clks_locked[PRI_AC_TILE_INDEX]; + assign all_tiles_core_clks_fb_in[PRI_AC_TILE_INDEX] = core_clks_fb_to_cpa_pri; + + assign core_clks_from_cpa_sec_nonabphy = PHY_PING_PONG_EN ? {1'b0,all_tiles_core_clks_out[SEC_AC_TILE_INDEX][0]} : '0; + assign core_clks_locked_cpa_sec_nonabphy = PHY_PING_PONG_EN ? all_tiles_core_clks_locked[SEC_AC_TILE_INDEX] : '0; + generate + if (PHY_PING_PONG_EN) begin + assign all_tiles_core_clks_fb_in[SEC_AC_TILE_INDEX] = core_clks_fb_to_cpa_sec; + end + endgenerate + + // Outputs from PHY clock tree back to PLL + // Physically, this connection needs to happen in every tile but + // in RTL we only make this connection for the A/C tile (since we + // only have one logical PLL) + + // Avalon signals between HMC and core + // In the following arrays, only elements at tile index *_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0] all_tiles_ctl2core_avl_cmd_ready; + logic [NUM_OF_RTL_TILES-1:0][12:0] all_tiles_ctl2core_avl_rdata_id; + + assign ctl2core_avl_cmd_ready_0_nonabphy = all_tiles_ctl2core_avl_cmd_ready[PRI_AC_TILE_INDEX]; + assign ctl2core_avl_rdata_id_0_nonabphy = all_tiles_ctl2core_avl_rdata_id[PRI_AC_TILE_INDEX]; + + assign ctl2core_avl_cmd_ready_1_nonabphy = all_tiles_ctl2core_avl_cmd_ready[SEC_AC_TILE_INDEX]; + assign ctl2core_avl_rdata_id_1_nonabphy = all_tiles_ctl2core_avl_rdata_id[SEC_AC_TILE_INDEX]; + + // AFI signals between tile and core + // In the following arrays, only elements at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + // Ping-Pong PHY doesn't support AFI interface so there's no need to account for SEC_AC_TILE_INDEX + logic [NUM_OF_RTL_TILES-1:0][17:0] all_tiles_c2t_afi; + logic [NUM_OF_RTL_TILES-1:0][26:0] all_tiles_t2c_afi; + + assign all_tiles_c2t_afi[PRI_AC_TILE_INDEX] = c2t_afi; + assign t2c_afi_nonabphy = all_tiles_t2c_afi[PRI_AC_TILE_INDEX]; + + // Sideband signals between HMC and core + // In the following arrays, only elements at tile index *_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0][13:0] all_tiles_ctl2core_sideband; + + assign ctl2core_sideband_0_nonabphy = all_tiles_ctl2core_sideband[PRI_AC_TILE_INDEX]; + assign ctl2core_sideband_1_nonabphy = all_tiles_ctl2core_sideband[SEC_AC_TILE_INDEX]; + + // MMR signals between HMC and core + // In the following arrays, only elements at tile index *_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0][33:0] all_tiles_ctl2core_mmr; + + assign ctl2core_mmr_0_nonabphy = all_tiles_ctl2core_mmr[PRI_AC_TILE_INDEX]; + assign ctl2core_mmr_1_nonabphy = all_tiles_ctl2core_mmr[SEC_AC_TILE_INDEX]; + + // CPA DPRIO signals (for internal debug) + // In the following arrays, only elements at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0] all_tiles_pa_dprio_block_select; + logic [NUM_OF_RTL_TILES-1:0][PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH-1:0] all_tiles_pa_dprio_readdata; + + assign pa_dprio_readdata_nonabphy = all_tiles_pa_dprio_readdata[PRI_AC_TILE_INDEX]; + assign pa_dprio_block_select_nonabphy = all_tiles_pa_dprio_block_select[PRI_AC_TILE_INDEX]; + + // FM Tile PHYCLK Atom + logic [2:0] phy_fbclk_pa; + logic [1:0] phy_clk_hmc; + + // CPA DPRIO signals (for internal debug) + logic [LANES_PER_TILE-1:0][1:0] phy_clk_local_early; + logic [LANES_PER_TILE-1:0][1:0] phy_clk_local_late; + + logic phy_rxloaden_tp_loopback, phy_rxloaden_btm_loopback; + logic phy_rxclk_tp_loopback, phy_rxclk_btm_loopback; + logic phy_fb_tp_loopback, phy_fb_btm_loopback; + logic phy_txloaden_tp_loopback, phy_txloaden_btm_loopback; + logic phy_txclk_tp_loopback, phy_txclk_btm_loopback; + + + localparam VCO_FREQ_HZ_INT = PLL_VCO_FREQ_MHZ_INT * 1000000; + + `define cpa_clock_1_div_factor(vco_freq_mhz) \ + (vco_freq_mhz >= 600 && vco_freq_mhz < 800) ? "core_clk1_div2": \ + (vco_freq_mhz >= 800 && vco_freq_mhz < 1000) ? "core_clk1_div2p5": \ + (vco_freq_mhz >= 1000 && vco_freq_mhz < 1200) ? "core_clk1_div3": \ + "core_clk1_div4" + + tennm_io48_phyclk phyclk_inst ( + .loaden_0 (phy_clk[0]), // PHYCLK from the logical IOPLL + .lvds_clk_0 (phy_clk[1]), // PHYCLK from the logical IOPLL + .fblvds (phy_fb_clk_to_tile), // PLL signal going into PHY feedback clock; replaces tile_ctrl.pa_fbclk_in + .loaden_1 (1'b0), // Unused PHYCLK in an EMIF + .lvds_clk_1 (1'b0), // Unused PHYCLK in an EMIF + + // PHYCLK loopback timing paths + .phy_fb_match_btm (phy_fb_btm_loopback), + .phy_fb_match_tp (phy_fb_tp_loopback), + .phy_rxclk_from_btm (1'b0), + .phy_rxclk_from_left (1'b0), + .phy_rxclk_from_right (1'b0), + .phy_rxclk_from_tp (1'b0), + .phy_rxclk_match_btm (phy_rxclk_btm_loopback), + .phy_rxclk_match_tp (phy_rxclk_tp_loopback), + .phy_rxloaden_from_btm (1'b0), + .phy_rxloaden_from_left (1'b0), + .phy_rxloaden_from_right(1'b0), + .phy_rxloaden_from_tp (1'b0), + .phy_rxloaden_match_btm (phy_rxloaden_btm_loopback), + .phy_rxloaden_match_tp (phy_rxloaden_tp_loopback), + .phy_txclk_from_btm (1'b0), + .phy_txclk_from_left (1'b0), + .phy_txclk_from_right (1'b0), + .phy_txclk_from_tp (1'b0), + .phy_txclk_match_btm (phy_txclk_btm_loopback), + .phy_txclk_match_tp (phy_txclk_tp_loopback), + .phy_txloaden_from_btm (1'b0), + .phy_txloaden_from_left (1'b0), + .phy_txloaden_from_right(1'b0), + .phy_txloaden_from_tp (1'b0), + .phy_txloaden_match_btm (phy_txloaden_btm_loopback), + .phy_txloaden_match_tp (phy_txloaden_tp_loopback), + + .phy_clk_hmc (phy_clk_hmc), + .fbclk_pa (phy_fbclk_pa), + .fbclk_pll (phy_fb_clk_to_pll_nonabphy), // to IOPLL feedback; we have one logical PLL + + .phy_clk_local_early0 (phy_clk_local_early[0]), + .phy_clk_local_early1 (phy_clk_local_early[1]), + .phy_clk_local_early2 (phy_clk_local_early[2]), + .phy_clk_local_early3 (phy_clk_local_early[3]), + .phy_clk_local_late0 (phy_clk_local_late[0]), + .phy_clk_local_late1 (phy_clk_local_late[1]), + .phy_clk_local_late2 (phy_clk_local_late[2]), + .phy_clk_local_late3 (phy_clk_local_late[3]), + + .phy_clk_out_0 (all_tiles_t2l_phy_clk[0]), + .phy_clk_out_1 (all_tiles_t2l_phy_clk[1]), + .phy_clk_out_2 (all_tiles_t2l_phy_clk[2]), + .phy_clk_out_3 (all_tiles_t2l_phy_clk[3]), + + .phy_clk_ufi_0 (global_phy_clk[0]), // Global PHYCLK0 for C2P/P2C crossings + .phy_clk_ufi_1 (global_phy_clk[1]), // Global PHYCLK1 for C2P/P2C crossings + .phy_clk_ufi_3 (/*open*/), // Not used by EMIF (review NF EMIF Clock Topologies by Jimmy) + + // PHYCLK loopback timing paths + .phy_fb_to_btm (phy_fb_btm_loopback), + .phy_fb_to_tp (phy_fb_tp_loopback), + .phy_rxclk_to_left (/*open*/), + .phy_rxclk_to_right (/*open*/), + .phy_rxclk_to_tp (phy_rxclk_tp_loopback), + .phy_rxclk_to_btm (phy_rxclk_btm_loopback), + .phy_rxloaden_to_left (/*open*/), + .phy_rxloaden_to_right(/*open*/), + .phy_rxloaden_to_tp (phy_rxloaden_tp_loopback), + .phy_rxloaden_to_btm (phy_rxloaden_btm_loopback), + .phy_txclk_to_left (/*open*/), + .phy_txclk_to_right (/*open*/), + .phy_txclk_to_tp (phy_txclk_tp_loopback), + .phy_txclk_to_btm (phy_txclk_btm_loopback), + .phy_txloaden_to_left (/*open*/), + .phy_txloaden_to_right(/*open*/), + .phy_txloaden_to_tp (phy_txloaden_tp_loopback), + .phy_txloaden_to_btm (phy_txloaden_btm_loopback) + ); + + + //////////////////////////////////////////////////////////////////////////// + // Generate tiles and lanes. + //////////////////////////////////////////////////////////////////////////// + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2vio_afi_rlat; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2vio_afi_wlat; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2vio_rdata_valid; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2vio_rd_type; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2vio_rd_data_vld_avl; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2vio_wr_data_rdy_ast; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2vio_wb_pointer_for_ecc; + + + + localparam L2CORE_P2C_PER_IF_SIGS_TILE_INDEX = IS_HPS ? PRI_AC_TILE_INDEX : PRI_RDATA_TILE_INDEX; + localparam L2CORE_P2C_PER_IF_SIGS_LANE_INDEX = IS_HPS ? PRI_HMC_DBC_SHADOW_LANE_INDEX : PRI_RDATA_LANE_INDEX; + + assign l2core_afi_rlat_nonabphy = l2vio_afi_rlat[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + assign l2core_afi_wlat_nonabphy = l2vio_afi_wlat[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + + assign l2core_rdata_valid_nonabphy_pri = l2vio_rdata_valid[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + assign l2core_rdata_valid_nonabphy_sec = l2vio_rdata_valid[SEC_RDATA_TILE_INDEX][SEC_RDATA_LANE_INDEX]; + assign l2core_rd_data_vld_avl_nonabphy = l2vio_rd_data_vld_avl[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + assign l2core_rd_type_nonabphy = l2vio_rd_type[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + + assign l2core_wr_data_rdy_ast_nonabphy = l2vio_wr_data_rdy_ast[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + assign l2core_wb_pointer_for_ecc_nonabphy = l2vio_wb_pointer_for_ecc[L2CORE_P2C_PER_IF_SIGS_TILE_INDEX][L2CORE_P2C_PER_IF_SIGS_LANE_INDEX]; + + localparam PRI_HMC_CFG_NO_OF_REF_FOR_SELF_RFSH = (PRI_HMC_CFG_REFRESH_TYPE == 2'b01 ? 4'h2 : ( + PRI_HMC_CFG_REFRESH_TYPE == 2'b10 ? 4'h4 : ( + 4'h1 ))); + localparam SEC_HMC_CFG_NO_OF_REF_FOR_SELF_RFSH = (SEC_HMC_CFG_REFRESH_TYPE == 2'b01 ? 4'h2 : ( + SEC_HMC_CFG_REFRESH_TYPE == 2'b10 ? 4'h4 : ( + 4'h1 ))); + + // Select the param table data of the primary A/C tile + assign cal_bus_seq_param_tbl = tile_param_tables[PRI_AC_TILE_INDEX]; + generate + genvar tile_i, lane_i; + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) + begin: tile_gen + // DQS bus from tile to lanes + logic [1:0] t2l_dqsbus_x4 [LANES_PER_TILE-1:0]; + logic [1:0] t2l_dqsbus_x8 [LANES_PER_TILE-1:0]; + logic [1:0] t2l_dqsbus_x18 [LANES_PER_TILE-1:0]; + logic [1:0] t2l_dqsbus_x36 [LANES_PER_TILE-1:0]; + + // HMC AFI signals going to lanes. + logic [3:0][95:0] t2l_ac_hmc; + + // HMC to Data buffer control blocks in the lanes + logic [17:0] t2l_cfg_dbc [LANES_PER_TILE-1:0]; + + tennm_tile_ctrl # ( + .a_fmio96_hps_used (IS_HPS ? "A_FMIO96_HPS_USED" : "A_FMIO96_HPS_UNUSED"), + .mimic_hps (PHY_MIMIC_HPS_EMIF ? "true" : "false"), + .ioaux_param_table(SEQ_PT_CONTENT), + .param_table_valid((tile_i == PRI_AC_TILE_INDEX) ? "true" : "false"), + + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_wdata_driver_sel_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_prbs_ctrl_sel_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_loopback_en_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cmd_driver_sel_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbg_mode (4'b0000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbg_ctrl (32'b00000000000000000000000000000000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_bist_cmd0_u (32'b00000000000000000000000000000000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_bist_cmd0_l (32'b00000000000000000000000000000000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_bist_cmd1_u (32'b00000000000000000000000000000000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_bist_cmd1_l (32'b00000000000000000000000000000000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbg_out_sel (16'b0000000000000000), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_mem_type (`_get_hmc_ctrl_mem_type), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dimm_type (HMC_CTRL_DIMM_TYPE), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ac_pos (AC_PIN_MAP_SCHEME), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_addr_order (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ADDR_ORDER , SEC_HMC_CFG_ADDR_ORDER )), // (hmc_addr_order V) Mapping of Avalon address to physical address of the memory device + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl_enable_ecc_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CTRL_ENABLE_ECC , SEC_HMC_CFG_CTRL_ENABLE_ECC )), // Enable ECC + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_enable_ecc_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC0_ENABLE_ECC , SEC_HMC_CFG_DBC0_ENABLE_ECC )), // Enable ECC + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_enable_ecc_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC1_ENABLE_ECC , SEC_HMC_CFG_DBC1_ENABLE_ECC )), // Enable ECC + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_enable_ecc_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC2_ENABLE_ECC , SEC_HMC_CFG_DBC2_ENABLE_ECC )), // Enable ECC + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_enable_ecc_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC3_ENABLE_ECC , SEC_HMC_CFG_DBC3_ENABLE_ECC )), // Enable ECC + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_reorder_data_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_REORDER_DATA , SEC_HMC_CFG_REORDER_DATA )), // Enable command reodering + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl_reorder_rdata_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CTRL_REORDER_RDATA , SEC_HMC_CFG_CTRL_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_reorder_rdata_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC0_REORDER_RDATA , SEC_HMC_CFG_DBC0_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_reorder_rdata_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC1_REORDER_RDATA , SEC_HMC_CFG_DBC1_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_reorder_rdata_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC2_REORDER_RDATA , SEC_HMC_CFG_DBC2_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_reorder_rdata_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC3_REORDER_RDATA , SEC_HMC_CFG_DBC3_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_reorder_read_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_REORDER_READ , SEC_HMC_CFG_REORDER_READ )), // Enable read command reordering if command reordering is enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_starve_limit (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_STARVE_LIMIT , SEC_HMC_CFG_STARVE_LIMIT )), // When command reordering is enabled, specifies the number of commands that can be served before a starved command is starved. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dqstrk_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DQSTRK_EN , SEC_HMC_CFG_DQSTRK_EN )), // Enable DQS tracking + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl_enable_dm_scalar (MEM_DATA_MASK_EN ? "enable" : "disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_enable_dm_scalar (MEM_DATA_MASK_EN ? "enable" : "disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_enable_dm_scalar (MEM_DATA_MASK_EN ? "enable" : "disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_enable_dm_scalar (MEM_DATA_MASK_EN ? "enable" : "disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_enable_dm_scalar (MEM_DATA_MASK_EN ? "enable" : "disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl2dbc_switch0 (`_get_ctrl2dbc_switch_0(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl2dbc_switch1 (`_get_ctrl2dbc_switch_1(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_ctrl_sel_scalar (`_get_ctrl2dbc_sel_0(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_ctrl_sel_scalar (`_get_ctrl2dbc_sel_1(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_ctrl_sel_scalar (`_get_ctrl2dbc_sel_2(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_ctrl_sel_scalar (`_get_ctrl2dbc_sel_3(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2ctrl_sel (`_get_hmc_dbc2ctrl_sel(tile_i)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 0))), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 1))), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 2))), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 3))), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl_cmd_rate (`_get_hmc_cmd_rate), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_cmd_rate (`_get_dbc0_cmd_rate), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_cmd_rate (`_get_dbc1_cmd_rate), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_cmd_rate (`_get_dbc2_cmd_rate), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_cmd_rate (`_get_dbc3_cmd_rate), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl_in_protocol_scalar (`_get_hmc_protocol), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_in_protocol_scalar (`_get_dbc0_protocol), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_in_protocol_scalar (`_get_dbc1_protocol), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_in_protocol_scalar (`_get_dbc2_protocol), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_in_protocol_scalar (`_get_dbc3_protocol), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_geardn_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_GEAR_DOWN_EN , SEC_HMC_CFG_GEAR_DOWN_EN )), // Gear-down (DDR4) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3dsref_ack_on_done_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_3DSREF_ACK_ON_DONE , SEC_HMC_3DSREF_ACK_ON_DONE )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cb_tbp_reload_fix_en_n_scalar (`_get_hmc_cb_tbp_reload_fix_en_n), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_tile_id (tile_i[4:0]), // HMC ID (0 for T0, 1 for T1, etc) - actual value set by Fitter based on placement + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_pingpong_mode ((tile_i == PRI_AC_TILE_INDEX) ? PRI_HMC_CFG_PING_PONG_MODE : ((tile_i == SEC_AC_TILE_INDEX ) ? SEC_HMC_CFG_PING_PONG_MODE : "pingpong_off")), // Ping-Pong PHY mode + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_slot_rotate_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN , SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN )), // Command slot rotation + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_slot_rotate_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN , SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN )), // Command slot rotation + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_slot_rotate_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN , SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN )), // Command slot rotation + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_slot_rotate_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN , SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN )), // Command slot rotation + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_slot_offset (`_sel_hmc_lane(tile_i, 0, PRI_HMC_CFG_DBC0_SLOT_OFFSET , SEC_HMC_CFG_DBC0_SLOT_OFFSET )), // Command slot offset + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_slot_offset (`_sel_hmc_lane(tile_i, 1, PRI_HMC_CFG_DBC1_SLOT_OFFSET , SEC_HMC_CFG_DBC1_SLOT_OFFSET )), // Command slot offset + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_slot_offset (`_sel_hmc_lane(tile_i, 2, PRI_HMC_CFG_DBC2_SLOT_OFFSET , SEC_HMC_CFG_DBC2_SLOT_OFFSET )), // Command slot offset + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_slot_offset (`_sel_hmc_lane(tile_i, 3, PRI_HMC_CFG_DBC3_SLOT_OFFSET , SEC_HMC_CFG_DBC3_SLOT_OFFSET )), // Command slot offset + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctrl_rc_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CTRL_ENABLE_RC , SEC_HMC_CFG_CTRL_ENABLE_RC )), // Enable rate-conversion feature + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc0_rc_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC0_ENABLE_RC , SEC_HMC_CFG_DBC0_ENABLE_RC )), // Enable rate-conversion feature + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc1_rc_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC1_ENABLE_RC , SEC_HMC_CFG_DBC1_ENABLE_RC )), // Enable rate-conversion feature + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc2_rc_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC2_ENABLE_RC , SEC_HMC_CFG_DBC2_ENABLE_RC )), // Enable rate-conversion feature + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dbc3_rc_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DBC3_ENABLE_RC , SEC_HMC_CFG_DBC3_ENABLE_RC )), // Enable rate-conversion feature + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cs_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CS_TO_CHIP_MAPPING , SEC_HMC_CFG_CS_TO_CHIP_MAPPING )), // Chip select mapping scheme + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rb_reserved_entry (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RB_RESERVED_ENTRY , SEC_HMC_CFG_RB_RESERVED_ENTRY )), // Number of entries reserved in read buffer before almost full is asserted. Should be set to 4 + 2 * user_pipe_stages + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_wb_reserved_entry (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WB_RESERVED_ENTRY , SEC_HMC_CFG_WB_RESERVED_ENTRY )), // Number of entries reserved in write buffer before almost full is asserted. Should be set to 4 + 2 * user_pipe_stages + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_EN , SEC_HMC_3DS_EN )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ck_inv_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dfx_bypass_en_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_tcl (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_TCL , SEC_HMC_CFG_TCL )), // Memory CAS latency + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tcl (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_TCL , SEC_HMC_CFG_TCL )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_power_saving_exit_cycles (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_POWER_SAVING_EXIT_CYC , SEC_HMC_CFG_POWER_SAVING_EXIT_CYC )), // The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_mem_clk_disable_entry_cycles (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC, SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC )), // Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_write_odt_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WRITE_ODT_CHIP , SEC_HMC_CFG_WRITE_ODT_CHIP )), // ODT scheme setting for write command + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_read_odt_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_READ_ODT_CHIP , SEC_HMC_CFG_READ_ODT_CHIP )), // ODT scheme setting for read command + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rd_odt_on (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_ODT_ON , SEC_HMC_CFG_RD_ODT_ON )), // Indicates number of memory clock cycle gap between read command and ODT signal rising edge + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_wr_odt_period (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_ODT_PERIOD , SEC_HMC_CFG_WR_ODT_PERIOD )), // Indicates number of memory clock cycle write ODT signal should stay asserted after rising edge + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rd_odt_period (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_ODT_PERIOD , SEC_HMC_CFG_RD_ODT_PERIOD )), // Indicates number of memory clock cycle read ODT signal should stay asserted after rising edge + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_exit_pdn_for_dqstrk_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cb_revert_ref_qual_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_self_rfsh_dqstrk_en_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_srf_zqcal_disable_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SRF_ZQCAL_DISABLE , SEC_HMC_CFG_SRF_ZQCAL_DISABLE )), // Setting to disable ZQ Calibration after self refresh + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_mps_zqcal_disable_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MPS_ZQCAL_DISABLE , SEC_HMC_CFG_MPS_ZQCAL_DISABLE )), // Setting to disable ZQ Calibration after Maximum Power Saving exit + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_mps_dqstrk_disable_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MPS_DQSTRK_DISABLE , SEC_HMC_CFG_MPS_DQSTRK_DISABLE )), // Setting to disable DQS Tracking after Maximum Power Saving exit + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_sb_cg_disable_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SB_CG_DISABLE , SEC_HMC_CFG_SB_CG_DISABLE )), // Setting to disable mem_ck gating during self refresh and deep power down + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_user_rfsh_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_USER_RFSH_EN , SEC_HMC_CFG_USER_RFSH_EN )), // Setting to enable user refresh + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_srf_autoexit_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SRF_AUTOEXIT_EN , SEC_HMC_CFG_SRF_AUTOEXIT_EN )), // Setting to enable controller to exit Self Refresh when new command is detected + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_srf_entry_exit_block (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK , SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK )), // Blocking arbiter from issuing commands + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_sb_ddr4_mr3 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SB_DDR4_MR3 , SEC_HMC_CFG_SB_DDR4_MR3 )), // DDR4 MR3 + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_sb_ddr4_mr4 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SB_DDR4_MR4 , SEC_HMC_CFG_SB_DDR4_MR4 )), // DDR4 MR4 + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_short_dqstrk_ctrl_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN , SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_period_dqstrk_ctrl_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN , SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_period_dqstrk_interval (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL , SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_dqstrk_to_valid_last (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DQSTRK_TO_VALID_LAST , SEC_HMC_CFG_DQSTRK_TO_VALID_LAST )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_dqstrk_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DQSTRK_TO_VALID , SEC_HMC_CFG_DQSTRK_TO_VALID )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rfsh_warn_threshold (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RFSH_WARN_THRESHOLD , SEC_HMC_CFG_RFSH_WARN_THRESHOLD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_act_to_rdwr (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ACT_TO_RDWR , SEC_HMC_CFG_ACT_TO_RDWR )), // Activate to Read/write command timing (e.g. tRCD) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_act_to_pch (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ACT_TO_PCH , SEC_HMC_CFG_ACT_TO_PCH )), // Active to precharge (e.g. tRAS) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_act_to_act (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ACT_TO_ACT , SEC_HMC_CFG_ACT_TO_ACT )), // Active to activate timing on same bank (e.g. tRC) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_act_to_act_diff_bank (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK , SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK )), // Active to activate timing on different banks, for DDR4 same bank group (e.g. tRRD) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_act_to_act_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG , SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG )), // Active to activate timing on different bank groups, DDR4 only + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_rd (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_RD , SEC_HMC_CFG_RD_TO_RD )), // Read to read command timing on same bank (e.g. tCCD) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_rd_diff_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP , SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP )), // Read to read command timing on different chips + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_rd_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_RD_DIFF_BG , SEC_HMC_CFG_RD_TO_RD_DIFF_BG )), // Read to read command timing on different chips + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_wr (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_WR , SEC_HMC_CFG_RD_TO_WR )), // Read to write command timing on same bank + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_wr_diff_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP , SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP )), // Read to write command timing on different chips + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_wr_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_WR_DIFF_BG , SEC_HMC_CFG_RD_TO_WR_DIFF_BG )), // Read to write command timing on different bank groups + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_to_pch (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_TO_PCH , SEC_HMC_CFG_RD_TO_PCH )), // Read to precharge command timing (e.g. tRTP) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_rd_ap_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RD_AP_TO_VALID , SEC_HMC_CFG_RD_AP_TO_VALID )), // Read command with autoprecharge to data valid timing + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_wr (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_WR , SEC_HMC_CFG_WR_TO_WR )), // Write to write command timing on same bank. (e.g. tCCD) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_wr_diff_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP , SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP )), // Write to write command timing on different chips. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_wr_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_WR_DIFF_BG , SEC_HMC_CFG_WR_TO_WR_DIFF_BG )), // Write to write command timing on different bank groups. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_rd (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_RD , SEC_HMC_CFG_WR_TO_RD )), // Write to read command timing. (e.g. tWTR) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_rd_diff_chip (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP , SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP )), // Write to read command timing on different chips. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_rd_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_RD_DIFF_BG , SEC_HMC_CFG_WR_TO_RD_DIFF_BG )), // Write to read command timing on different bank groups + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_to_pch (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_TO_PCH , SEC_HMC_CFG_WR_TO_PCH )), // Write to precharge command timing. (e.g. tWR) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_wr_ap_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_AP_TO_VALID , SEC_HMC_CFG_WR_AP_TO_VALID )), // Write with autoprecharge to valid command timing. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_pch_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PCH_TO_VALID , SEC_HMC_CFG_PCH_TO_VALID )), // Precharge to valid command timing. (e.g. tRP) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_pch_all_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PCH_ALL_TO_VALID , SEC_HMC_CFG_PCH_ALL_TO_VALID )), // Precharge all to banks being ready for bank activation command. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_arf_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ARF_TO_VALID , SEC_HMC_CFG_ARF_TO_VALID )), // Auto Refresh to valid DRAM command window. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_pdn_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PDN_TO_VALID , SEC_HMC_CFG_PDN_TO_VALID )), // Power down to valid bank command window. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_srf_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SRF_TO_VALID , SEC_HMC_CFG_SRF_TO_VALID )), // Self-refresh to valid bank command window. (e.g. tRFC) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_srf_to_zq_cal (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SRF_TO_ZQ_CAL , SEC_HMC_CFG_SRF_TO_ZQ_CAL )), // Self refresh to ZQ calibration window + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_arf_period (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ARF_PERIOD , SEC_HMC_CFG_ARF_PERIOD )), // Auto-refresh period (e.g. tREFI) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_pdn_period (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PDN_PERIOD , SEC_HMC_CFG_PDN_PERIOD )), // Number of controller cycles before automatic power down. + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_zqcl_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ZQCL_TO_VALID , SEC_HMC_CFG_ZQCL_TO_VALID )), // Long ZQ calibration to valid + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_zqcs_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ZQCS_TO_VALID , SEC_HMC_CFG_ZQCS_TO_VALID )), // Short ZQ calibration to valid + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mrs_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MRS_TO_VALID , SEC_HMC_CFG_MRS_TO_VALID )), // Mode Register Setting to valid (e.g. tMRD) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mps_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MPS_TO_VALID , SEC_HMC_CFG_MPS_TO_VALID )), // Max Power Saving to Valid + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mrr_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MRR_TO_VALID , SEC_HMC_CFG_MRR_TO_VALID )), // Mode Register Read to Valid + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mpr_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MPR_TO_VALID , SEC_HMC_CFG_MPR_TO_VALID )), // Multi Purpose Register Read to Valid + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mps_exit_cs_to_cke (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE , SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE )), // Max Power Saving CS to CKE + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mps_exit_cke_to_cs (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS , SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS )), // Max Power Saving CKE to CS + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_mmr_cmd_to_valid (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MMR_CMD_TO_VALID , SEC_HMC_CFG_MMR_CMD_TO_VALID )), // MMR cmd to valid delay + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_t_param_4_act_to_act (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_4_ACT_TO_ACT , SEC_HMC_CFG_4_ACT_TO_ACT )), // The four-activate window timing parameter. (e.g. tFAW) + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_col_addr_width (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_COL_ADDR_WIDTH , SEC_HMC_CFG_COL_ADDR_WIDTH )), // Column address width + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_row_addr_width (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ROW_ADDR_WIDTH , SEC_HMC_CFG_ROW_ADDR_WIDTH )), // Row address width + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_bank_addr_width (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_BANK_ADDR_WIDTH , SEC_HMC_CFG_BANK_ADDR_WIDTH )), // Bank address width + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_bank_group_addr_width (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH , SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH )), // Bank group address width + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cs_addr_width (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CS_ADDR_WIDTH , SEC_HMC_CFG_CS_ADDR_WIDTH )), // Address width in bits required to access every CS in interface + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_sb_ddr4_mr5 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_SB_DDR4_MR5 , SEC_HMC_CFG_SB_DDR4_MR5 )), // DDR4 MR5 + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ddr4_mps_addrmirror_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR , SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR )), // DDR4 MPS Address Mirror + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_lr_num0 (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_LR_NUM0 , SEC_HMC_3DS_LR_NUM0 )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_lr_num1 (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_LR_NUM1 , SEC_HMC_3DS_LR_NUM1 )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_lr_num2 (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_LR_NUM2 , SEC_HMC_3DS_LR_NUM2 )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_lr_num3 (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_LR_NUM3 , SEC_HMC_3DS_LR_NUM3 )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cid_addr_width (`_sel_hmc_tile(tile_i, PRI_HMC_CID_ADDR_WIDTH , SEC_HMC_CID_ADDR_WIDTH )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_pr_stag_enable_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_PR_STAG_ENABLE , SEC_HMC_3DS_PR_STAG_ENABLE )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_3ds_ref2ref_dlr (`_sel_hmc_tile(tile_i, PRI_HMC_3DS_REF2REF_DLR , SEC_HMC_3DS_REF2REF_DLR )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_chip_id (`_sel_hmc_tile(tile_i, PRI_HMC_CHIP_ID , SEC_HMC_CHIP_ID )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_arbiter_reg_ena_scalar ("disable"), // Unused + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_wb_ptr_reg_ena_scalar ("disable"), // Intended for hard circuitry timing closure, but currently not necessary + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rb_ptr_reg_ena_scalar ("disable"), // Intended for hard circuitry timing closure, but currently not necessary + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctl2dbc_reg_ena_scalar ("enable"), // Unused + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctl2dbc_tile_reg_ena_scalar ("enable"), // Intended for hard circuitry timing closure, but currently not necessary + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ac_tile_reg_ena_scalar ("disable"), // Intended for hard circuitry timing closure, but currently not necessary + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tcwl (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TCWL , SEC_HMC_MEM_IF_TCWL )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_al (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_AL , SEC_HMC_MEM_IF_AL )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tpl (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TPL , SEC_HMC_MEM_IF_TPL )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trcd (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRCD , SEC_HMC_MEM_IF_TRCD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tras (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRAS , SEC_HMC_MEM_IF_TRAS )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trp (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRP , SEC_HMC_MEM_IF_TRP )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trp_ab (32'd0), // DON'T CARE; drive to default + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trc (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRC , SEC_HMC_MEM_IF_TRC )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trrd (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRRD , SEC_HMC_MEM_IF_TRRD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tfaw (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TFAW , SEC_HMC_MEM_IF_TFAW )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trfc (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRFC , SEC_HMC_MEM_IF_TRFC )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_3ds_trfc_dlr (32'd0), // DON'T CARE; drive to default + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_txpdll (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TXPDLL , SEC_HMC_MEM_IF_TXPDLL )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_txsr (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TXSR , SEC_HMC_MEM_IF_TXSR )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tckesr (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TCKESR , SEC_HMC_MEM_IF_TCKESR )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tcksrx (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TCKSRX , SEC_HMC_MEM_IF_TCKSRX )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tccd (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TCCD , SEC_HMC_MEM_IF_TCCD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_twr (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TWR , SEC_HMC_MEM_IF_TWR )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tzqcs (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TZQCS , SEC_HMC_MEM_IF_TZQCS )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tzqoper (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TZQOPER , SEC_HMC_MEM_IF_TZQOPER )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tmod (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TMOD , SEC_HMC_MEM_IF_TMOD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trefi (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TREFI , SEC_HMC_MEM_IF_TREFI )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_auto_pd_cycles (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MEM_AUTO_PD_CYCLES , SEC_HMC_CFG_MEM_AUTO_PD_CYCLES )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trtp (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRTP , SEC_HMC_MEM_IF_TRTP )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_twtr (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TWTR , SEC_HMC_MEM_IF_TWTR )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_trrd_s (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TRRD_S , SEC_HMC_MEM_IF_TRRD_S )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tccd_s (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TCCD_S , SEC_HMC_MEM_IF_TCCD_S )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_wr_preamble (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_WR_PREAMBLE , SEC_HMC_MEM_IF_WR_PREAMBLE )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_rd_preamble (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_RD_PREAMBLE , SEC_HMC_MEM_IF_RD_PREAMBLE )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_wr_crc (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_WR_CRC , SEC_HMC_MEM_IF_WR_CRC )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_twtr_l_crc_dm (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TWTR_L_CRC_DM , SEC_HMC_MEM_IF_TWTR_L_CRC_DM )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_twtr_s_crc_dm (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TWTR_S_CRC_DM , SEC_HMC_MEM_IF_TWTR_S_CRC_DM )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_twr_crc_dm (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TWR_CRC_DM , SEC_HMC_MEM_IF_TWR_CRC_DM )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_twtr_s (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TWTR_S , SEC_HMC_MEM_IF_TWTR_S )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_txp (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TXP , SEC_HMC_MEM_IF_TXP )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_tdqsckmax (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_TDQSCKMAX , SEC_HMC_MEM_IF_TDQSCKMAX )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_ctl_odt_enabled (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CTL_ODT_ENABLED , SEC_HMC_CFG_CTL_ODT_ENABLED )), // ODT enabled + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_cs_per_dimm (`_sel_hmc_tile(tile_i, PRI_HMC_MEM_IF_CS_PER_DIMM , SEC_HMC_MEM_IF_CS_PER_DIMM )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_enable_fast_exit_ppd (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD , SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_ctl_short_dqstrk_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN , SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_hmc_phy_delay_mismatch (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PHY_DELAY_MISMATCH , SEC_HMC_CFG_PHY_DELAY_MISMATCH )), + + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_va_cfg_hmc_mode ("prod"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cmd_fifo_reserve_entry (0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_ctl2dbc_io_pipeline_en_scalar (DBC_EXTRA_PIPE_STAGE_EN), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_livelock_breaker_en_scalar ("enable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_memclkgate_setting (0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_opportunistic_rfsh_en_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rfsh_idle_threshold (0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_core_wr_pipeline_wdata (0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_mem_if_lpasr (0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_ufi_pipeline_wdata (0), + + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_col_cmd_slot (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_COL_CMD_SLOT , SEC_HMC_CFG_COL_CMD_SLOT )), // Command slot for column commands + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_row_cmd_slot (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ROW_CMD_SLOT , SEC_HMC_CFG_ROW_CMD_SLOT )), // Command slot for row commands + .iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_col_to_row_offset (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_COL_TO_ROW_OFFSET , SEC_HMC_CFG_COL_TO_ROW_OFFSET )), // Command slot offset from col to row command + .iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_row_to_col_offset (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ROW_TO_COL_OFFSET , SEC_HMC_CFG_ROW_TO_COL_OFFSET )), // Command slot offset from row to col command + .iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_col_to_col_offset (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_COL_TO_COL_OFFSET , SEC_HMC_CFG_COL_TO_COL_OFFSET )), // Command slot offset from col to col command + .iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_col_to_diff_col_offset (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET , SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET )), // Command slot offset from col to col command (different columns) + .iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_row_to_row_offset (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ROW_TO_ROW_OFFSET , SEC_HMC_CFG_ROW_TO_ROW_OFFSET )), // Command slot offset from row to row commandr + .iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_ctl_width_ratio (PHY_HMC_CLK_RATIO == 2 ? 32'd4 : 32'd8), // Virtual setting. Unused + + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_temp_cfg_t_param_wr_to_rd (`_sel_hmc_tile(tile_i, PRI_HMC_TEMP_WR_TO_RD , SEC_HMC_TEMP_WR_TO_RD )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_temp_cfg_t_param_wr_to_rd_diff_chip (`_sel_hmc_tile(tile_i, PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP , SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_temp_cfg_t_param_wr_to_rd_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_TEMP_WR_TO_RD_DIFF_BG , SEC_HMC_TEMP_WR_TO_RD_DIFF_BG )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_temp_cfg_t_param_wr_to_wr_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_TEMP_WR_TO_WR_DIFF_BG , SEC_HMC_TEMP_WR_TO_WR_DIFF_BG )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_temp_cfg_t_param_rd_to_rd_diff_bg (`_sel_hmc_tile(tile_i, PRI_HMC_TEMP_RD_TO_RD_DIFF_BG , SEC_HMC_TEMP_RD_TO_RD_DIFF_BG )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_temp_cfg_t_param_4_act_to_act (`_sel_hmc_tile(tile_i, PRI_HMC_TEMP_4_ACT_TO_ACT , SEC_HMC_TEMP_4_ACT_TO_ACT )), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_pipeline_wdata_path ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_pipeline_rdata_path ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_rd_to_rd_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_wr_to_wr_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_rd_to_wr_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_wr_to_rd_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_rd_to_rd_diff_chip_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_wr_to_wr_diff_chip_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_rd_to_wr_diff_chip_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_wr_to_rd_diff_chip_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_rd_to_rd_diff_bg_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_wr_to_wr_diff_bg_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_rd_to_wr_diff_bg_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_wr_to_rd_diff_bg_extra (32'd0), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_num_of_mem_clk_pair (32'd1), + + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_periodic_refresh_type (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_REFRESH_TYPE , SEC_HMC_CFG_REFRESH_TYPE)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_no_of_ref_for_self_rfsh (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_NO_OF_REF_FOR_SELF_RFSH , SEC_HMC_CFG_NO_OF_REF_FOR_SELF_RFSH)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_major_mode_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_MAJOR_MODE_EN , SEC_HMC_CFG_MAJOR_MODE_EN)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_post_rfsh_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_POST_REFRESH_EN , SEC_HMC_CFG_POST_REFRESH_EN)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rfsh_post_upper_limit (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT , SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rfsh_post_lower_limit (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT , SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_pre_rfsh_en_scalar (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PRE_REFRESH_EN , SEC_HMC_CFG_PRE_REFRESH_EN)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_rfsh_pre_upper_limit (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT , SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT)), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_cb_3ds_pdown_exit_for_ref_scalar ("disable"), + .u4_0_x0_iohmc_ctrl_inst_iohmc_ctrl_mmr_top_inst_cfg_dual_ping_pong_en_scalar ("disable"), + + .u4_0_x0_iophyseq_inst_a_rb_tile_id (`_get_center_tid(tile_i)), + .u4_0_x0_iophyseq_inst_a_rb_avl_ena ("avl_enable"), + .u4_0_x0_iophyseq_inst_a_rb_hmc_or_core (`_get_hmc_or_core_physeq), + .u4_0_x0_iophyseq_inst_a_rb_trk_mgr_mrnk_mode ("one_rank"), + .u4_0_x0_iophyseq_inst_a_rb_trk_mgr_read_monitor_ena ("disable"), // Must be disabled to avoid an issue with tracking manager (ICD) + .u4_0_x0_iophyseq_inst_a_rb_hmc_id (`_get_hmc_tid(tile_i)), // HMC tile ID - actual value is set by fitter based on placement + .u4_0_x0_iophyseq_inst_a_rb_reset_auto_release (DIAG_SEQ_RESET_AUTO_RELEASE), // Reset sequencer controlled via Avalon by Nios + .u4_0_x0_iophyseq_inst_a_rb_rwlat_mode ("avl_vlu"), // wlat/rlat set dynamically via Avalon by Nios (instead of through CSR) + .u4_0_x0_iophyseq_inst_a_rb_afi_rlat_vlu (6'b000000), // Unused - wlat set dynamically via Avalon by Nios + .u4_0_x0_iophyseq_inst_a_rb_afi_wlat_vlu (6'b000000), // Unused - rlat set dynamically via Avalon by Nios + .u4_0_x0_iophyseq_inst_a_rb_core_clk_sel (USE_HMC_RC_OR_DP ? "clk1" : "clk0"), // Use clk1 in rate-converter or dual-port mode, and clk0 otherwise + .u4_0_x0_iophyseq_inst_a_afi_seq_busy_extend ("extend_8cycles"), + .u4_0_x0_powermode_ac (tile_i == PRI_AC_TILE_INDEX ? "ac_tile" : "data_tile"), // + .u4_0_x0_powermode_dc ("powerup"), // Power-up this HMC + + .u1_0_x0_powermode_dc ("powerup"), + + .powermode_freq_hz_phs_clk (VCO_FREQ_HZ_INT), + + .u1_0_x0_xio_phase_align_pnr_a_rbpa_phase_offset_0 (12'b0), // Output clock phase degree = phase_offset / 128 * 360 + .u1_0_x0_xio_phase_align_pnr_a_rbpa_phase_offset_1 (12'b0), // Output clock phase degree = phase_offset / 128 * 360 + .u1_0_x0_xio_phase_align_pnr_a_rbpa_core_control_en_0 ("core_disable_0"), + .u1_0_x0_xio_phase_align_pnr_a_rbpa_core_control_en_1 ("core_disable_1"), + .u1_0_x0_xio_phase_align_pnr_a_rbpa_pa_reset_enable ("pa_reset_en"), + .u1_0_x0_xio_phase_align_pnr_a_dprio_base_addr (9'b000000000), + .u1_0_x0_xio_phase_align_pnr_a_rbpa_filter_code (`_get_pa_filter_code), + .u1_0_x0_xio_phase_align_pnr_a_support_dpa ("not_support_dpa"), // VALID only for LVDS + + .u1_0_x0_xio_phase_align_pnr_a_core_clk0_pll_vco_freq_divide (`_get_cpa_0_clk_divider), + .u1_0_x0_xio_phase_adjust_xio_pa_peri_fb_mux_0_a_rbpa_feedback_mux_sel ((PRI_HMC_CFG_CTRL_ENABLE_RC == "enable") ? "fb1_p_clk" : "fb0_p_clk"), + + .u1_0_x0_xio_phase_align_pnr_a_core_clk1_pll_vco_freq_divide (`cpa_clock_1_div_factor(PLL_VCO_FREQ_MHZ_INT)), + .u1_0_x0_xio_phase_align_pnr_a_dpa_clk_pll_vco_freq_divide ("dpa_clk_div1"), + .u1_0_x0_xio_phase_align_pnr_a_fb_core_clk0_phy_clk0_freq_divide (`_get_pa_feedback_divider_p0), + .u1_0_x0_xio_phase_adjust_xio_pa_peri_fb_mux_1_a_rbpa_feedback_mux_sel (CPA_FB_MUX_1_SEL), + .u1_0_x0_xio_phase_adjust_xio_pa_feedback_path_1_a_rbpa_feedback_path ("feedback_path_0"), + .u1_0_x0_xio_phase_adjust_xio_pa_feedback_gate_1_a_rbpa_feedback_gate_sel ("gate_skew_periphery"), + .u1_0_x0_xio_phase_adjust_xio_pa_feedback_gate_1_a_rbpa_feedback_gate ("feedback_gate_dly_0") + +/* +* Untouched ND params +* .hmc_dbc0_burst_length (`_get_hmc_burst_length), +* .hmc_dbc1_burst_length (`_get_hmc_burst_length), +* .hmc_dbc2_burst_length (`_get_hmc_burst_length), +* .hmc_dbc3_burst_length (`_get_hmc_burst_length), +* .hmc_wr_odt_on (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_WR_ODT_ON , SEC_HMC_CFG_WR_ODT_ON )), // Indicates number of memory clock cycle gap between write command and ODT signal rising edge +* .silicon_rev (SILICON_REV), +* .hps_ctrl_en (IS_HPS ? "hps_ctrl_en" : "hps_ctrl_dis"), +* .pa_exponent_0 (`_get_pa_exponent_0), // Output clock freq = VCO Freq / 2^exponent +* .pa_exponent_1 (`_get_pa_exponent_1), // Output clock freq = VCO Freq / 2^exponent +* .pa_feedback_divider_c0 (`_get_pa_feedback_divider_c0), // Core clock 0 divider (either 1 or 2) +* .pa_feedback_divider_c1 ("div_by_1"), // Core clock 1 divider (always 1) +* .pa_feedback_divider_p0 (`_get_pa_feedback_divider_p0), // PHY clock 0 divider (either 1 or 2) +* .pa_feedback_divider_p1 ("div_by_1"), // PHY clock 1 divider (always 1) +* .pa_feedback_mux_sel_0 ("fb2_p_clk"), // Use phy_clk[2] as feedback +* .pa_feedback_mux_sel_1 (DIAG_CPA_OUT_1_EN ? "fb0_p_clk" : "fb2_p_clk"), // Use phy_clk[2] as feedback, unless in dual-CPA characterization mode +* .pa_freq_track_speed (4'hd), +* .pa_track_speed (`_get_pa_track_speed), +* .pa_sync_control ("no_sync"), +* .pa_sync_latency (4'b0000), +* .pa_coreclk_override ("non_override"), // Override mechanism to use test clock as input +* .pa_couple_enable ("couple_en"), +* .pa_hps_clk_en (IS_HPS ? "fb_clk_hps" : "fb_clk_core"), // HPS or not? +* .physeq_bc_id_ena ("bc_enable"), // Enable broadcast mechanism +* .physeq_seq_feature (21'b000000000000000000000), +* .hmc_ac_pos (AC_PIN_MAP_SCHEME), +* .hmc_ctrl_output_regd ("disable"), // Engineering option. Unused. +* .hmc_dbc0_output_regd ("disable"), // Engineering option. Unused. +* .hmc_dbc1_output_regd ("disable"), // Engineering option. Unused. +* .hmc_dbc2_output_regd ("disable"), // Engineering option. Unused. +* .hmc_dbc3_output_regd ("disable"), // Engineering option. Unused. +* .hmc_ctrl_dualport_en ("disable"), // No dual-port mode support +* .hmc_dbc0_dualport_en ("disable"), // No dual-port mode support +* .hmc_dbc1_dualport_en ("disable"), // No dual-port mode support +* .hmc_dbc2_dualport_en ("disable"), // No dual-port mode support +* .hmc_dbc3_dualport_en ("disable"), // No dual-port mode support +* .hmc_avl_scg_en ("disable"), // Static clock gating +* .hmc_dbc_sw_scg_en ("disable"), // Static clock gating +* .hmc_core_scg_en ("disable"), // Static clock gating +* .hmc_dbg_scg_en ("disable"), // Static clock gating +* .hmc_scg_en ("disable"), // Static clock gating +* .hmc_mmr_scg_en ("disable"), // Static clock gating +* .hmc_pipe_scg_en ("disable"), // Static clock gating +* .hmc_seq_scg_en ("disable"), // Static clock gating +* +* .cfg_cb_3ds_mixed_height_ref_ack_disable ("disable"), // Set to 0 (same as "disable") to enable fix (case:384958) +* .cfg_cb_3ds_mixed_height_req_fix ("disable"), // Set to 0 (same as "disable") to enable fix (case:384958) +* .hmc_cb_seq_en_fix_en_n ("enable"), // Set to 0 (same as "enable") to enable fix (case:384958) +* .cfg_cb_memclk_gate_default ("disable"), // Set to 0 (same as "disable") to enable fix (case:384958) +* .cfg_cb_en_cmd_valid_ungate_fix ("enable"), // Set to 1 (same as "enable") to enable fix (case:384958) +* .cfg_cb_en_mrnk_rd_fix ("enable"), // Set to 1 (same as "enable") to enable fix (case:384958) +* .cfg_cb_pdqs_perf_fix_disable ("disable"), // Set to 0 (same as "disable") to enable fix (case:384958) +* +* +* .hmc_arbiter_type (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_ARBITER_TYPE , SEC_HMC_CFG_ARBITER_TYPE )), // Arbiter Type +* .hmc_open_page_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_OPEN_PAGE_EN , SEC_HMC_CFG_OPEN_PAGE_EN )), // Unused +* .hmc_ctrl_slot_rotate_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN , SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN )), // Command slot rotation +* .hmc_cmd_fifo_reserve_en (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_CMD_FIFO_RESERVE_EN , SEC_HMC_CFG_CMD_FIFO_RESERVE_EN )), // Command FIFO reserve enable +* .hmc_memclkgate_setting (`_sel_hmc_tile(tile_i, PRI_HMC_MEMCLKGATE_SETTING , SEC_HMC_MEMCLKGATE_SETTING )), +* .hmc_16_act_to_act (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_16_ACT_TO_ACT , SEC_HMC_CFG_16_ACT_TO_ACT )), // The 16-activate window timing parameter (RLD3) (e.g. tSAW) +* .hmc_rld3_multibank_ref_delay (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY , SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY )), // RLD3 multi-bank ref delay +* .hmc_rld3_refresh_seq0 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ0 , SEC_HMC_CFG_RLD3_REFRESH_SEQ0 )), // Banks to refresh for RLD3 in sequence 0. Must not be more than 4 banks +* .hmc_rld3_refresh_seq1 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ1 , SEC_HMC_CFG_RLD3_REFRESH_SEQ1 )), // Banks to refresh for RLD3 in sequence 1. Must not be more than 4 banks +* .hmc_rld3_refresh_seq2 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ2 , SEC_HMC_CFG_RLD3_REFRESH_SEQ2 )), // Banks to refresh for RLD3 in sequence 2. Must not be more than 4 banks +* .hmc_rld3_refresh_seq3 (`_sel_hmc_tile(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ3 , SEC_HMC_CFG_RLD3_REFRESH_SEQ3 )), // Banks to refresh for RLD3 in sequence 3. Must not be more than 4 banks +* .mode ("tile_ddr") +*/ + ) tile_ctrl_inst ( + // Reset + .global_reset_n (DIAG_USE_ABSTRACT_PHY == 1 ? (~core2seq_reset_req) : 1'b1), + + // PLL -> Tiles + .pll_locked_in (pll_locked), + .pll_vco_in (phy_clk_phs), // FR clocks routed on PHY clock tree + .phy_clk_in (phy_clk_hmc), // PHY clock tree inputs + + // Clock Phase Alignment + .pa_core_clk_in ({1'b0,all_tiles_core_clks_fb_in[tile_i][0]}), // Input to CPA through feedback path + .pa_core_clk_out (all_tiles_core_clks_out[tile_i]), // Output from CPA to core clock networks + .pa_locked (all_tiles_core_clks_locked[tile_i]), // Lock signal from CPA to core + .pa_reset_n (DIAG_USE_ABSTRACT_PHY == 1 ? (~core2seq_reset_req) : 1'b1), // Connected to global reset from core in non-HPS mode + .pa_core_in (12'b000000000000), // Control code word + + // ND_2_FM delta => PA feedback port expanded to 3 bits + .pa_fbclk_in (phy_fbclk_pa), // PLL signal going into PHY feedback clock + + .pa_sync_data_bot_in (pa_sync_data_up_chain[`_get_chain_index_for_tile(tile_i)]), + .pa_sync_data_top_out (pa_sync_data_up_chain[`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_data_top_in (pa_sync_data_dn_chain[`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_data_bot_out (pa_sync_data_dn_chain[`_get_chain_index_for_tile(tile_i)]), + .pa_sync_clk_bot_in (pa_sync_clk_up_chain [`_get_chain_index_for_tile(tile_i)]), + .pa_sync_clk_top_out (pa_sync_clk_up_chain [`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_clk_top_in (pa_sync_clk_dn_chain [`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_clk_bot_out (pa_sync_clk_dn_chain [`_get_chain_index_for_tile(tile_i)]), + .pa_dprio_rst_n ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_rst_n : 1'b0)), + .pa_dprio_clk ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_clk : 1'b0)), + .pa_dprio_read ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_read : 1'b0)), + .pa_dprio_reg_addr ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_reg_addr : 9'b0)), + .pa_dprio_write ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_write : 1'b0)), + .pa_dprio_writedata ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_writedata : 8'b0)), + .pa_dprio_block_select (all_tiles_pa_dprio_block_select[tile_i]), + .pa_dprio_readdata (all_tiles_pa_dprio_readdata[tile_i]), + + // PHY clock signals going from tiles to lanes + .phy_clk_phs_out0 (all_tiles_t2l_phy_clk_phs[tile_i][0]), // PHY vco clocks to lane 0 + .phy_clk_phs_out1 (all_tiles_t2l_phy_clk_phs[tile_i][1]), // PHY vco clocks to lane 1 + .phy_clk_phs_out2 (all_tiles_t2l_phy_clk_phs[tile_i][2]), // PHY vco clocks to lane 2 + .phy_clk_phs_out3 (all_tiles_t2l_phy_clk_phs[tile_i][3]), // PHY vco clocks to lane 3 + + // DLL Interface + .dll_clk_in (pll_dll_clk), // PLL clock feeding to DLL + .dll_clk_out0 (all_tiles_dll_clk_out[tile_i][0]), // DLL clock to lane 0 + .dll_clk_out1 (all_tiles_dll_clk_out[tile_i][1]), // DLL clock to lane 1 + .dll_clk_out2 (all_tiles_dll_clk_out[tile_i][2]), // DLL clock to lane 2 + .dll_clk_out3 (all_tiles_dll_clk_out[tile_i][3]), // DLL clock to lane 3 + + // Calibration bus between Nios and sequencer (a.k.a slow Avalon-MM bus) + .param_table_data (tile_param_tables[tile_i]), + .cal_avl_in (cal_bus_avl_up_chain [`_get_chain_index_for_tile(tile_i)]), + .cal_avl_out (cal_bus_avl_up_chain [`_get_chain_index_for_tile(tile_i) + 1]), + .cal_avl_rdata_in (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_tile(tile_i) + 1]), + .cal_avl_rdata_out (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_tile(tile_i)]), + + .core2ctl_avl ((tile_i == PRI_AC_TILE_INDEX) ? core2ctl_avl_0 : ((tile_i == SEC_AC_TILE_INDEX ) ? core2ctl_avl_1 : 63'd0)), + .core2ctl_avl_rd_data_ready ((tile_i == PRI_AC_TILE_INDEX) ? core2ctl_avl_rd_data_ready_0 : ((tile_i == SEC_AC_TILE_INDEX ) ? core2ctl_avl_rd_data_ready_1 : 1'b0)), + .ctl2core_avl_cmd_ready (all_tiles_ctl2core_avl_cmd_ready[tile_i]), + .ctl2core_avl_rdata_id (all_tiles_ctl2core_avl_rdata_id[tile_i]), + + .core2ctl_sideband ((tile_i == PRI_AC_TILE_INDEX) ? core2ctl_sideband_0 : ((tile_i == SEC_AC_TILE_INDEX ) ? core2ctl_sideband_1 : 42'd0)), + .ctl2core_sideband (all_tiles_ctl2core_sideband[tile_i]), + + // Interface between HMC and lanes + .afi_cmd_bus (t2l_ac_hmc), + + // DQS buses + // There are 8 x4 DQS buses per tile, with two pairs of input DQS per lane. + .dqs_in_x4_a_0 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 0] : 1'b0), + .dqs_in_x4_a_1 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 1] : 1'b0), + .dqs_in_x4_a_2 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 2] : 1'b0), + .dqs_in_x4_a_3 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 3] : 1'b0), + .dqs_in_x4_b_0 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 0] : 1'b0), + .dqs_in_x4_b_1 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 1] : 1'b0), + .dqs_in_x4_b_2 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 2] : 1'b0), + .dqs_in_x4_b_3 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 3] : 1'b0), + .dqs_out_x4_a_lane0 (t2l_dqsbus_x4[0][0]), + .dqs_out_x4_b_lane0 (t2l_dqsbus_x4[0][1]), + .dqs_out_x4_a_lane1 (t2l_dqsbus_x4[1][0]), + .dqs_out_x4_b_lane1 (t2l_dqsbus_x4[1][1]), + .dqs_out_x4_a_lane2 (t2l_dqsbus_x4[2][0]), + .dqs_out_x4_b_lane2 (t2l_dqsbus_x4[2][1]), + .dqs_out_x4_a_lane3 (t2l_dqsbus_x4[3][0]), + .dqs_out_x4_b_lane3 (t2l_dqsbus_x4[3][1]), + + // There are 4 x8/x9 DQS buses per tile, with one pair of input DQS per lane. + .dqs_in_x8_0 ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" || DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV")? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 0], b2t_dqs[(tile_i * LANES_PER_TILE) + 0]} : 2'b0), + .dqs_in_x8_1 ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" || DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV")? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 1], b2t_dqs[(tile_i * LANES_PER_TILE) + 1]} : 2'b0), + .dqs_in_x8_2 ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" || DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV")? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 2], b2t_dqs[(tile_i * LANES_PER_TILE) + 2]} : 2'b0), + .dqs_in_x8_3 ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" || DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X9_DINV")? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 3], b2t_dqs[(tile_i * LANES_PER_TILE) + 3]} : 2'b0), + .dqs_out_x8_lane0 (t2l_dqsbus_x8[0]), + .dqs_out_x8_lane1 (t2l_dqsbus_x8[1]), + .dqs_out_x8_lane2 (t2l_dqsbus_x8[2]), + .dqs_out_x8_lane3 (t2l_dqsbus_x8[3]), + + // There are 2 x16/x18 DQS buses per tile, and the input DQS must originate from lane 0 and 2 (Follow-on) + .dqs_in_x18_0 ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" || DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X18_DINV")? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 0], b2t_dqs[(tile_i * LANES_PER_TILE) + 0]} : 2'b0), + .dqs_in_x18_1 ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" || DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X18_DINV")? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 2], b2t_dqs[(tile_i * LANES_PER_TILE) + 2]} : 2'b0), + .dqs_out_x18_lane0 (t2l_dqsbus_x18[0]), + .dqs_out_x18_lane1 (t2l_dqsbus_x18[1]), + .dqs_out_x18_lane2 (t2l_dqsbus_x18[2]), + .dqs_out_x18_lane3 (t2l_dqsbus_x18[3]), + + // There is 1 x32/x36 DQS bus per tile, and the input DQS must originate from lane 1 + .dqs_in_x36 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X32_X36" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 1], b2t_dqs[(tile_i * LANES_PER_TILE) + 1]} : 2'b0), + .dqs_out_x36_lane0 (t2l_dqsbus_x36[0]), + .dqs_out_x36_lane1 (t2l_dqsbus_x36[1]), + .dqs_out_x36_lane2 (t2l_dqsbus_x36[2]), + .dqs_out_x36_lane3 (t2l_dqsbus_x36[3]), + + // Data buffer control signals + .ctl2dbc0 (all_tiles_ctl2dbc0_dn_chain[tile_i]), + .ctl2dbc1 (all_tiles_ctl2dbc1_up_chain[tile_i + 1]), + .ctl2dbc_in_up (all_tiles_ctl2dbc0_dn_chain[tile_i + 1]), + .ctl2dbc_in_down (all_tiles_ctl2dbc1_up_chain[tile_i]), + .cfg_dbc0 (t2l_cfg_dbc[0]), + .cfg_dbc1 (t2l_cfg_dbc[1]), + .cfg_dbc2 (t2l_cfg_dbc[2]), + .cfg_dbc3 (t2l_cfg_dbc[3]), + + // Ping-Pong PHY related signals + .ping_pong_in (all_tiles_ping_pong_up_chain[tile_i]), + .ping_pong_out (all_tiles_ping_pong_up_chain[tile_i + 1]), + + // MMR-related signals + .mmr_in ((tile_i == PRI_AC_TILE_INDEX) ? core2ctl_mmr_0 : ((tile_i == SEC_AC_TILE_INDEX ) ? core2ctl_mmr_1 : 51'b0)), + .mmr_out (all_tiles_ctl2core_mmr[tile_i]), + + // Miscellaneous signals + .afi_core2ctl (all_tiles_c2t_afi[tile_i]), + .afi_ctl2core (all_tiles_t2c_afi[tile_i]), + .seq2core_reset_n (), + .ctl_mem_clk_disable (), + .rdata_en_full_core (4'b0), + .mrnk_read_core (16'b0), + .test_dbg_in (48'b000000000000000000000000000000000000000000000000), + .test_dbg_out () + ); + + + for (lane_i = 0; lane_i < LANES_PER_TILE; ++lane_i) + begin: lane_gen + (* altera_attribute = "-name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 1; -name MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER 1" *) + altera_emif_arch_fm_io_lane_remap #( + .memory_standard (`_get_memory_standard), + .memory_controller (`_get_hmc_or_smc), + .mode_rate_in (`_get_lane_mode_rate_in), + .mode_rate_out (`_get_lane_mode_rate_out), + .memory_burst_length (`_get_memory_burst_length), + .memory_width (`_get_dqs_group_width), + + .clock_period_ps ((`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_UNUSED) ? 16'd0 : PLL_MEM_CLK_FREQ_PS), + .phy_clk_sel (0), + .calibration ("run"), + .lock_speed (3'h7), + + .db_dbc_ctrl_rc_en_scalar ((PRI_HMC_CFG_CTRL_ENABLE_RC == "enable") ? "dbc_rc_scalar_enable" : "dbc_rc_scalar_disable"), + .db_avl_base_addr (`_get_lane_tid(tile_i, lane_i)), + .db_avl_broadcast_en ("bc_enable"), + .db_avl_ena ("avl_enable"), + .dqs_select_a (DQSA_LGC_MODE), + .dqs_select_b (DQSB_LGC_MODE), + + .lane_ddr_mode (`_get_lane_ddr_mode_str(tile_i, lane_i)), + + .lane_pin0_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 0) ), + .lane_pin1_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 1) ), + .lane_pin2_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 2) ), + .lane_pin3_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 3) ), + .lane_pin4_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 4) ), + .lane_pin5_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 5) ), + .lane_pin6_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 6) ), + .lane_pin7_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 7) ), + .lane_pin8_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 8) ), + .lane_pin9_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 9) ), + .lane_pin10_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 10)), + .lane_pin11_ddr_mode (`_get_lane_pin_ddr_mode_str(tile_i, lane_i, 11)), + + .lane_mode ((`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_UNUSED) ? "lane_unused" : "lane_ddr"), + .lane_pin0_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 0) ), + .lane_pin1_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 1) ), + .lane_pin2_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 2) ), + .lane_pin3_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 3) ), + .lane_pin4_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 4) ), + .lane_pin5_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 5) ), + .lane_pin6_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 6) ), + .lane_pin7_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 7) ), + .lane_pin8_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 8) ), + .lane_pin9_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 9) ), + .lane_pin10_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 10)), + .lane_pin11_mode (`_get_lane_pin_mode_str(tile_i, lane_i, 11)), + + + .db_hmc_or_core (`_get_hmc_or_core), + .db_db2core_registered ("registered"), + .db_preamble_mode (PREAMBLE_MODE), + .db_data_alignment_mode (`_get_db_data_alignment_mode), // Data alignment mode (enabled IFF HMC) + + .db_pin0_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 0) ), + .db_pin1_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 1) ), + .db_pin2_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 2) ), + .db_pin3_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 3) ), + .db_pin4_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 4) ), + .db_pin5_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 5) ), + .db_pin6_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 6) ), + .db_pin7_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 7) ), + .db_pin8_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 8) ), + .db_pin9_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 9) ), + .db_pin10_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 10)), + .db_pin11_mode (`_get_db_pin_proc_mode_str(tile_i, lane_i, 11)), + + .pin0_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 0) ), + .pin1_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 1) ), + .pin2_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 2) ), + .pin3_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 3) ), + .pin4_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 4) ), + .pin5_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 5) ), + .pin6_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 6) ), + .pin7_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 7) ), + .pin8_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 8) ), + .pin9_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 9) ), + .pin10_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 10)), + .pin11_oct_rt (`_get_pin_oct_rt_str(tile_i, lane_i, 11)), + + .pin0_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 0) ), + .pin1_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 1) ), + .pin2_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 2) ), + .pin3_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 3) ), + .pin4_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 4) ), + .pin5_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 5) ), + .pin6_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 6) ), + .pin7_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 7) ), + .pin8_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 8) ), + .pin9_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 9) ), + .pin10_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 10)), + .pin11_dyn_oct (`_get_pin_dyn_oct_str(tile_i, lane_i, 11)), + + .pin0_initial_out ("initial_out_z"), + .pin1_initial_out ("initial_out_z"), + .pin2_initial_out ("initial_out_z"), + .pin3_initial_out ("initial_out_z"), + .pin4_initial_out ("initial_out_z"), + .pin5_initial_out ("initial_out_z"), + .pin6_initial_out ("initial_out_z"), + .pin7_initial_out ("initial_out_z"), + .pin8_initial_out ("initial_out_z"), + .pin9_initial_out ("initial_out_z"), + .pin10_initial_out ("initial_out_z"), + .pin11_initial_out ("initial_out_z"), + + .pin0_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 0) ), + .pin1_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 1) ), + .pin2_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 2) ), + .pin3_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 3) ), + .pin4_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 4) ), + .pin5_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 5) ), + .pin6_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 6) ), + .pin7_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 7) ), + .pin8_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 8) ), + .pin9_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 9) ), + .pin10_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 10)), + .pin11_mode_ddr (`_get_pin_ddr_str(tile_i, lane_i, 11)), + + .pin0_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 0) ), + .pin1_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 1) ), + .pin2_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 2) ), + .pin3_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 3) ), + .pin4_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 4) ), + .pin5_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 5) ), + .pin6_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 6) ), + .pin7_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 7) ), + .pin8_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 8) ), + .pin9_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 9) ), + .pin10_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 10)), + .pin11_dqs_mode (`_get_pin_dqs_mode_str(tile_i, lane_i, 11)), + + .pin0_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 0) ), + .pin1_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 1) ), + .pin2_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 2) ), + .pin3_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 3) ), + .pin4_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 4) ), + .pin5_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 5) ), + .pin6_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 6) ), + .pin7_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 7) ), + .pin8_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 8) ), + .pin9_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 9) ), + .pin10_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 10)), + .pin11_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 11)), + + .db_afi_rlat_vlu (6'b000000), // Unused - rlat set dynamically via Avalon by Nios + .db_afi_wlat_vlu (6'b000000), // Unused - wlat set dynamically via Avalon by Nios + + // Use phy_clk1 if HMC dual-port or rate-converter is used, use phy_clk0 otherwise + .db_sel_core_clk ((`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_UNUSED) ? "core_clk_disable" : LANE_DB_CLK_SEL ), + .db_dbi_wr_en (`_get_dbi_wr_en(tile_i, lane_i)), + .db_dbi_rd_en (`_get_dbi_rd_en(tile_i, lane_i)), + .db_dbi_sel ("dbi_dq6"), + .db_ptr_pipeline_depth (`_get_db_ptr_pipe_depth_str(tile_i, lane_i)), // Additional latency to compensate for distance from HMC + .db_seq_rd_en_full_pipeline (`_get_db_seq_rd_en_full_pipeline_str(tile_i, lane_i)), // Additional latency to compensate for distance from sequencer + .db_mrnk_write_mode (`_get_mrnk_write_mode(tile_i, lane_i)), + .dbc_wb_reserved_entry (DBC_WB_RESERVED_ENTRY[4:0]), + .db_dbc_rb_readylat_en (DBC_WB_RESERVED_ENTRY[6] ? "dbc_rb_readylat_enable" : "dbc_rb_readylat_disable"), + .db_dbc_wb_readylat_en (DBC_WB_RESERVED_ENTRY[5] ? "dbc_wb_readylat_enable" : "dbc_wb_readylat_disable"), + .oct_size (`_get_oct_size), + .rd_valid_delay (7'b0000000), // Don't-care - always set by calibration software + .dqs_enable_delay (6'b000000), // Don't-care - always set by calibration software + .dqs_phase_shift_b (13'b00000_0000_0000), // Delay to read clock/strobe gating signal. Overriden by Nios during calibration. + .dqs_phase_shift_a (13'b00000_0000_0000), // Delay to read clock/strobe gating signal. Overriden by Nios during calibration. + .dll_rst_en (IS_HPS ? "dll_rst_dis" : "dll_rst_en"), + .dll_core_updnen ("dll_core_updn_dis"), + .dll_ctlsel (DLL_MODE), + .dll_ctl_static (DLL_CODEWORD), + .enable_toggler (`_get_preamble_track_dqs_enable_mode) // Tracking Mode + ) lane_inst ( + + // PLL/DLL/PVT interface + .pll_locked (pll_locked), + .dll_ref_clk (all_tiles_dll_clk_out[tile_i][lane_i]), + .core_dll (3'b100), + .dll_core (), + .ioereg_locked (), + + // Clocks + .phy_clk (all_tiles_t2l_phy_clk[lane_i][1:0]), + .phy_clk_phs (all_tiles_t2l_phy_clk_phs[tile_i][lane_i]), + .phy_clk_local_early (phy_clk_local_early[lane_i]), + .phy_clk_local_late (phy_clk_local_late[lane_i]), + + // Clock Phase Alignment + .sync_data_bot_in (pa_sync_data_up_chain[`_get_chain_index_for_lane(tile_i, lane_i)]), + .sync_data_top_out (pa_sync_data_up_chain[`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_data_top_in (pa_sync_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_data_bot_out (pa_sync_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i)]), + .sync_clk_bot_in (pa_sync_clk_up_chain [`_get_chain_index_for_lane(tile_i, lane_i)]), + .sync_clk_top_out (pa_sync_clk_up_chain [`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_clk_top_in (pa_sync_clk_dn_chain [`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_clk_bot_out (pa_sync_clk_dn_chain [`_get_chain_index_for_lane(tile_i, lane_i)]), + + // DQS bus from tile. Connections are only made for the data lanes (as captured by the macro) + .dqs_in (`_get_dqsin(tile_i, lane_i)), + + // Interface to I/O bufers + .oct_enable (l2b_dtc_nonabphy [tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + .data_oe (l2b_oe_nonabphy [tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + .data_in (b2l_data[tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + .data_out (l2b_data_nonabphy[tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + + // Interface to core + .data_from_core (core2l_data[tile_i][lane_i]), + .data_to_core (l2core_data_nonabphy[tile_i][lane_i]), + + // core2l_oe is inverted before feeding into the lane because + // oe_invert is always set to true as required by HMC and sequencer + .oe_from_core (core2l_oe[tile_i][lane_i]), + .rdata_en_full_core (core2l_rdata_en_full[tile_i][lane_i]), + + // mrnk_(read|write) + .mrnk_read_core ((`_get_data_lane(tile_i,lane_i) == 1'b1 || PROTOCOL_ENUM == "PROTOCOL_QDR4" ) ? {8'd0, core2l_mrnk_read[tile_i][lane_i]} : 16'b0), + .mrnk_write_core ((`_get_data_lane(tile_i,lane_i) == 1'b1 || PROTOCOL_ENUM == "PROTOCOL_QDR4" ) ? {8'd0, core2l_mrnk_write[tile_i][lane_i]} : 16'b0), + + .rdata_valid_core (l2vio_rdata_valid[tile_i][lane_i]), + .afi_wlat_core (l2vio_afi_wlat[tile_i][lane_i]), + .afi_rlat_core (l2vio_afi_rlat[tile_i][lane_i]), + + // ECC signals between core and lanes + .dbc2core_rd_data_vld0 (l2vio_rd_data_vld_avl[tile_i][lane_i]), + .core2dbc_wr_data_vld0 (`_get_core2dbc_wr_data_vld(tile_i, lane_i)), + .dbc2core_wr_data_rdy (l2vio_wr_data_rdy_ast[tile_i][lane_i]), + .core2dbc_rd_data_rdy (`_get_core2dbc_rd_data_rdy(tile_i, lane_i)), + .dbc2core_wb_pointer (l2vio_wb_pointer_for_ecc[tile_i][lane_i]), + .core2dbc_wr_ecc_info (`_get_core2dbc_wr_ecc_info(tile_i, lane_i)), + .dbc2core_rd_type (l2vio_rd_type[tile_i][lane_i]), + + // Calibration bus between Nios and sequencer (a.k.a slow Avalon-MM bus) + .reset_n (DIAG_USE_ABSTRACT_PHY == 1 ? (~core2seq_reset_req) : 1'b1), + .cal_avl_in (cal_bus_avl_up_chain [`_get_chain_index_for_lane(tile_i, lane_i)]), + .cal_avl_out (cal_bus_avl_up_chain [`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .cal_avl_readdata_in (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .cal_avl_readdata_out (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i)]), + + // HMC interface + .ac_hmc (`_get_ac_hmc(tile_i, lane_i)), + .ctl2dbc0 (all_tiles_ctl2dbc0_dn_chain[tile_i]), + .ctl2dbc1 (all_tiles_ctl2dbc1_up_chain[tile_i + 1]), + .cfg_dbc (t2l_cfg_dbc[lane_i]), + + // Broadcast signals + .broadcast_in_bot (broadcast_up_chain[`_get_broadcast_chain_index(tile_i, lane_i)]), + .broadcast_out_top (broadcast_up_chain[`_get_broadcast_chain_index(tile_i, lane_i) + 1]), + .broadcast_in_top (broadcast_dn_chain[`_get_broadcast_chain_index(tile_i, lane_i) + 1]), + .broadcast_out_bot (broadcast_dn_chain[`_get_broadcast_chain_index(tile_i, lane_i)]), + + // Unused signals + .dft_phy_clk (/*open*/) + ); + + end + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm17Ies0Vsl/kcZ66hCa0cxXw4w0Fyjibd+1pmoa3KnGaTBErSNL1IdeYka0p/TnGQ4ny7EFj5kJWtiwMSWR77bb4RT4tneNfK8718tMGMCEFpnRfZt30Yov386tAL2EAtTvraGyRSnxswOaEM0Euq2RjTsYuUbDi3aIVMuM42NLmideJE3+qwxDbdlSsMKgL3mo3Gi0GC4+gK9WlKm83RIfmGU05QKXIW2H1WIAZGopr4HOg7vHShQgncu77Se1cRmI3JaQNNcZRcLkaCjGITBoBw1QHhDKcdePaqSYxf00G+4yT/HdROXWNd3pP1UNh8nfhvohVcHuVO5tydrpfWP1TP227pkZ+bkHe+aLHtx1qIbTg3KDF/48Jg4ZWRcWTC/Uoo1AqviAeOBrNH+zCoqQaUgZB9x0Clma48SPv3I3ZCDDD2JBxC+Cf+QXyVgX8obb27SRlxyIYMwUH88ohSg2RnlEM2xJDs1NXtIr1m/PhYPGFmI0pNQLApemuSi3bi5RTpa78Kpz4R3xmpJf8qiH57IBA9Yd1MDe4YOLbNZ9SPU2C2PbIYUHD4aHjPNDo4dz7JgZ+VUwSNUs0tZDTEyITg4TcEEFrzcDFBRlYeZzj0rGfa7ypkHecOfkGuiLkkKT2uYbr+RcJ2mqLYhj43BAZ0PwrUvIIYuiSDmGALWnPBp7xv/hO4ApUDCZEhAIm4pWFGmafrlADKhOnmxxBQv4cRN7Mk5RiPPDGpyCsmyU/X71RgZoYGMTEeNWwsZFyLcaQuWBzWu5R2O+ds7khwfU" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles_wrap.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles_wrap.sv new file mode 100644 index 0000000000..20f666945c --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles_wrap.sv @@ -0,0 +1,1864 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// +// Wrapper module for IO tiles +// +/////////////////////////////////////////////////////////////////////////////// + +module altera_emif_arch_fm_io_tiles_wrap #( + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_SIM_VERBOSE_LEVEL = 2, + parameter DIAG_SEQ_RESET_AUTO_RELEASE = "avl", + parameter DIAG_DB_RESET_AUTO_RELEASE = "avl_release", + parameter IS_HPS = 0, + parameter SILICON_REV = "", + parameter PROTOCOL_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_MEM_CLK_FREQ_PS = 0, + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter LANES_IN_RTL_TILES = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter PHY_MIMIC_HPS_EMIF = 0, + parameter CPA_FB_MUX_1_SEL = "", + + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter PRI_HMC_CFG_CS_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_COL_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_RC = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter [ 1: 0] PRI_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter [ 31: 0] PRI_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 31: 0] PRI_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter PRI_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 7: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter [ 31: 0] PRI_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter PRI_HMC_CFG_DQSTRK_EN = "", + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 31: 0] PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter [ 31: 0] PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter [ 31: 0] PRI_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 7: 0] PRI_HMC_MEMCLKGATE_SETTING = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_AL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCCD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCCD_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCKESR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCKSRX = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCWL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TDQSCKMAX = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TFAW = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TMOD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TPL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRAS = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRCD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TREFI = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRFC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRRD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRRD_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRTP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXPDLL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXSR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TZQCS = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TZQOPER = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_WR_CRC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 9: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter [ 1: 0] PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter [ 31: 0] PRI_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter [ 31: 0] PRI_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter PRI_HMC_CFG_MAJOR_MODE_EN = "", + parameter [ 1: 0] PRI_HMC_CFG_REFRESH_TYPE = 0, + parameter PRI_HMC_CFG_POST_REFRESH_EN = "", + parameter [ 4: 0] PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter [ 4: 0] PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter PRI_HMC_CFG_PRE_REFRESH_EN = "", + parameter [ 3: 0] PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter [ 8: 0] PRI_HMC_CHIP_ID = 0, + parameter [ 1: 0] PRI_HMC_CID_ADDR_WIDTH = 0, + parameter PRI_HMC_3DS_EN = "", + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM0 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM1 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM2 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM3 = 0, + parameter PRI_HMC_3DS_PR_STAG_ENABLE = "", + parameter [ 6: 0] PRI_HMC_3DS_REF2REF_DLR = 0, + parameter PRI_HMC_3DSREF_ACK_ON_DONE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter SEC_HMC_CFG_CS_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_COL_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_RC = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter [ 1: 0] SEC_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter [ 31: 0] SEC_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 31: 0] SEC_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter SEC_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 7: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter [ 31: 0] SEC_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter SEC_HMC_CFG_DQSTRK_EN = "", + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 31: 0] SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter [ 31: 0] SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter [ 31: 0] SEC_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 7: 0] SEC_HMC_MEMCLKGATE_SETTING = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_AL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCCD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCCD_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCKESR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCKSRX = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCWL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TDQSCKMAX = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TFAW = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TMOD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TPL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRAS = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRCD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TREFI = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRFC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRRD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRRD_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRTP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXPDLL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXSR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TZQCS = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TZQOPER = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_WR_CRC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 9: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter [ 1: 0] SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter [ 31: 0] SEC_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter [ 31: 0] SEC_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter SEC_HMC_CFG_MAJOR_MODE_EN = "", + parameter [ 1: 0] SEC_HMC_CFG_REFRESH_TYPE = 0, + parameter SEC_HMC_CFG_POST_REFRESH_EN = "", + parameter [ 4: 0] SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter [ 4: 0] SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter SEC_HMC_CFG_PRE_REFRESH_EN = "", + parameter [ 3: 0] SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter [ 8: 0] SEC_HMC_CHIP_ID = 0, + parameter [ 1: 0] SEC_HMC_CID_ADDR_WIDTH = 0, + parameter SEC_HMC_3DS_EN = "", + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM0 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM1 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM2 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM3 = 0, + parameter SEC_HMC_3DS_PR_STAG_ENABLE = "", + parameter [ 6: 0] SEC_HMC_3DS_REF2REF_DLR = 0, + parameter SEC_HMC_3DSREF_ACK_ON_DONE = "", + + parameter SEQ_PT_CONTENT = "", + parameter LANES_USAGE = 0, + parameter LANE_PIN_USAGE = 0, + parameter PINS_USAGE = 0, + parameter PINS_RATE = 0, + parameter DB_PINS_PROC_MODE = 0, + parameter PINS_DATA_IN_MODE = 0, + parameter PINS_OCT_MODE = 0, + parameter PINS_DCC_SPLIT = 0, + parameter CENTER_TIDS = 0, + parameter HMC_TIDS = 0, + parameter LANE_TIDS = 0, + parameter DBC_EXTRA_PIPE_STAGE_EN = "", + parameter DBC_PIPE_LATS = 0, + parameter DB_PTR_PIPELINE_DEPTHS = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES = 0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = "", + parameter DQSA_LGC_MODE = "", + parameter DQSB_LGC_MODE = "", + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter [10:0] DLL_CODEWORD = 0, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH = 1, + + parameter PORT_CALBUS_ADDRESS_WIDTH = 1, + parameter PORT_CALBUS_RDATA_WIDTH = 1, + parameter PORT_CALBUS_WDATA_WIDTH = 1, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 1, + + + parameter PORT_MEM_A_PINLOC = 0, + parameter PORT_MEM_BA_PINLOC = 0, + parameter PORT_MEM_BG_PINLOC = 0, + parameter PORT_MEM_CS_N_PINLOC = 0, + parameter PORT_MEM_ACT_N_PINLOC = 0, + parameter PORT_MEM_DQ_PINLOC = 0, + parameter PORT_MEM_DM_PINLOC = 0, + parameter PORT_MEM_DBI_N_PINLOC = 0, + parameter PORT_MEM_RAS_N_PINLOC = 0, + parameter PORT_MEM_CAS_N_PINLOC = 0, + parameter PORT_MEM_WE_N_PINLOC = 0, + parameter PORT_MEM_REF_N_PINLOC = 0, + + parameter PORT_MEM_WPS_N_PINLOC = 0, + parameter PORT_MEM_RPS_N_PINLOC = 0, + parameter PORT_MEM_BWS_N_PINLOC = 0, + parameter PORT_MEM_DQA_PINLOC = 0, + parameter PORT_MEM_DQB_PINLOC = 0, + parameter PORT_MEM_Q_PINLOC = 0, + parameter PORT_MEM_D_PINLOC = 0, + parameter PORT_MEM_RWA_N_PINLOC = 0, + parameter PORT_MEM_RWB_N_PINLOC = 0, + parameter PORT_MEM_QKA_PINLOC = 0, + parameter PORT_MEM_QKB_PINLOC = 0, + parameter PORT_MEM_LDA_N_PINLOC = 0, + parameter PORT_MEM_LDB_N_PINLOC = 0, + parameter PORT_MEM_CK_PINLOC = 0, + parameter PORT_MEM_DINVA_PINLOC = 0, + parameter PORT_MEM_DINVB_PINLOC = 0, + parameter PORT_MEM_AINV_PINLOC = 0, + parameter PORT_MEM_DQS_PINLOC = 0, + parameter PORT_MEM_QK_PINLOC = 0, + parameter PORT_MEM_CQ_PINLOC = 0, + + parameter PORT_MEM_A_WIDTH = 0, + parameter PORT_MEM_BA_WIDTH = 0, + parameter PORT_MEM_BG_WIDTH = 0, + parameter PORT_MEM_CS_N_WIDTH = 0, + parameter PORT_MEM_ACT_N_WIDTH = 0, + parameter PORT_MEM_DBI_N_WIDTH = 0, + parameter PORT_MEM_RAS_N_WIDTH = 0, + parameter PORT_MEM_CAS_N_WIDTH = 0, + parameter PORT_MEM_WE_N_WIDTH = 0, + parameter PORT_MEM_DM_WIDTH = 0, + parameter PORT_MEM_REF_N_WIDTH = 0, + parameter PORT_MEM_WPS_N_WIDTH = 0, + parameter PORT_MEM_RPS_N_WIDTH = 0, + parameter PORT_MEM_BWS_N_WIDTH = 0, + parameter PORT_MEM_DQA_WIDTH = 0, + parameter PORT_MEM_DQB_WIDTH = 0, + parameter PORT_MEM_Q_WIDTH = 0, + parameter PORT_MEM_D_WIDTH = 0, + parameter PORT_MEM_RWA_N_WIDTH = 0, + parameter PORT_MEM_RWB_N_WIDTH = 0, + parameter PORT_MEM_QKA_WIDTH = 0, + parameter PORT_MEM_QKB_WIDTH = 0, + parameter PORT_MEM_LDA_N_WIDTH = 0, + parameter PORT_MEM_LDB_N_WIDTH = 0, + parameter PORT_MEM_CK_WIDTH = 0, + parameter PORT_MEM_DINVA_WIDTH = 0, + parameter PORT_MEM_DINVB_WIDTH = 0, + parameter PORT_MEM_AINV_WIDTH = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 0, + parameter DIAG_ABSTRACT_PHY_RLAT = 0, + parameter ABPHY_WRITE_PROTOCOL = 1 +) ( + // Reset related + input logic core2seq_reset_req, // For abstract phy support + + // Signals for various signals from PLL + input logic pll_locked, // Indicates PLL lock status + input logic pll_dll_clk, // PLL -> DLL output clock + input logic [7:0] phy_clk_phs, // FR PHY clock signals (8 phases, 45-deg apart) + input logic [1:0] phy_clk, // {phy_clk[1], phy_clk[0]} + output logic [1:0] global_phy_clk, // {phy_clk[1], phy_clk[0]} + input logic phy_fb_clk_to_tile, // PHY feedback clock (to tile) + output logic phy_fb_clk_to_pll, // PHY feedback clock (to PLL) + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + output logic [1:0] core_clks_from_cpa_pri, // Core clock signals from the CPA of primary interface + output logic [1:0] core_clks_locked_cpa_pri, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_fb_to_cpa_pri, // Core clock feedback signals to the CPA of primary interface + output logic [1:0] core_clks_from_cpa_sec, // Core clock signals from the CPA of secondary interface (ping-pong only) + output logic [1:0] core_clks_locked_cpa_sec, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_fb_to_cpa_sec, // Core clock feedback signals to the CPA of secondary interface (ping-pong only) + + // Avalon interfaces between core and HMC + input logic [62:0] core2ctl_avl_0, + input logic [62:0] core2ctl_avl_1, + input logic core2ctl_avl_rd_data_ready_0, + input logic core2ctl_avl_rd_data_ready_1, + output logic ctl2core_avl_cmd_ready_0, + output logic ctl2core_avl_cmd_ready_1, + output logic [12:0] ctl2core_avl_rdata_id_0, + output logic [12:0] ctl2core_avl_rdata_id_1, + + // ECC signals between core and lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] core2l_wr_data_vld_ast, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] core2l_rd_data_rdy_ast, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][12:0] core2l_wr_ecc_info, + + output logic [11:0] l2core_wb_pointer_for_ecc, + output logic l2core_rd_data_vld_avl, + output logic l2core_wr_data_rdy_ast, + + // Signals between core and data lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_write, + output logic [3:0] l2core_rdata_valid_pri, + output logic [3:0] l2core_rdata_valid_sec, + output logic [5:0] l2core_afi_rlat, + output logic [5:0] l2core_afi_wlat, + + // AFI signals between tile and core + input [17:0] c2t_afi, + output [26:0] t2c_afi, + + // Side-band signals between core and HMC + input logic [41:0] core2ctl_sideband_0, + output logic [13:0] ctl2core_sideband_0, + input logic [41:0] core2ctl_sideband_1, + output logic [13:0] ctl2core_sideband_1, + + // MMR signals between core and HMC + output logic [33:0] ctl2core_mmr_0, + input logic [50:0] core2ctl_mmr_0, + output logic [33:0] ctl2core_mmr_1, + input logic [50:0] core2ctl_mmr_1, + output logic l2core_rd_type, + + // Signals between I/O buffers and lanes/tiles + output logic [PINS_IN_RTL_TILES-1:0] l2b_data, // lane-to-buffer data + output logic [PINS_IN_RTL_TILES-1:0] l2b_oe, // lane-to-buffer output-enable + output logic [PINS_IN_RTL_TILES-1:0] l2b_dtc, // lane-to-buffer dynamic-termination-control + input logic [PINS_IN_RTL_TILES-1:0] b2l_data, // buffer-to-lane data + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, // buffer-to-tile DQS + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, // buffer-to-tile DQSb + + // Avalon-MM bus for the calibration commands between IOSSM and tiles + input logic cal_bus_clk, + input logic cal_bus_avl_read, + input logic cal_bus_avl_write, + input logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] cal_bus_avl_address, + output logic [PORT_CALBUS_RDATA_WIDTH-1:0] cal_bus_avl_read_data, + input logic [PORT_CALBUS_WDATA_WIDTH-1:0] cal_bus_avl_write_data, + output logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] cal_bus_seq_param_tbl, + + + // Ports for internal test and debug + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata, + + input logic afi_cal_success, + output logic runAbstractPhySim +); + timeunit 1ns; + timeprecision 1ps; + + logic phy_fb_clk_to_pll_abphy; + logic [1:0] core_clks_from_cpa_pri_abphy; + logic [1:0] core_clks_locked_cpa_pri_abphy; + logic [1:0] core_clks_from_cpa_sec_abphy; + logic [1:0] core_clks_locked_cpa_sec_abphy; + logic ctl2core_avl_cmd_ready_0_abphy; + logic ctl2core_avl_cmd_ready_1_abphy; + logic [12:0] ctl2core_avl_rdata_id_0_abphy; + logic [12:0] ctl2core_avl_rdata_id_1_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_abphy; + logic [26:0] t2c_afi_abphy; + logic [13:0] ctl2core_sideband_0_abphy; + logic [13:0] ctl2core_sideband_1_abphy; + logic [33:0] ctl2core_mmr_0_abphy; + logic [33:0] ctl2core_mmr_1_abphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_data_abphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_oe_abphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_abphy; + logic pa_dprio_block_select_abphy; + logic [PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_abphy; + + logic phy_fb_clk_to_pll_nonabphy; + logic [1:0] core_clks_from_cpa_pri_nonabphy; + logic [1:0] core_clks_locked_cpa_pri_nonabphy; + logic [1:0] core_clks_from_cpa_sec_nonabphy; + logic [1:0] core_clks_locked_cpa_sec_nonabphy; + logic ctl2core_avl_cmd_ready_0_nonabphy; + logic ctl2core_avl_cmd_ready_1_nonabphy; + logic [12:0] ctl2core_avl_rdata_id_0_nonabphy; + logic [12:0] ctl2core_avl_rdata_id_1_nonabphy; + + logic [11:0] l2core_wb_pointer_for_ecc_nonabphy; + logic l2core_rd_data_vld_avl_nonabphy; + logic l2core_wr_data_rdy_ast_nonabphy; + logic l2core_rd_type_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_nonabphy; + logic [3:0] l2core_rdata_valid_nonabphy_pri; + logic [3:0] l2core_rdata_valid_nonabphy_sec; + logic [5:0] l2core_afi_rlat_nonabphy; + logic [5:0] l2core_afi_wlat_nonabphy; + + logic [26:0] t2c_afi_nonabphy; + logic [13:0] ctl2core_sideband_0_nonabphy; + logic [13:0] ctl2core_sideband_1_nonabphy; + logic [33:0] ctl2core_mmr_0_nonabphy; + logic [33:0] ctl2core_mmr_1_nonabphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_data_nonabphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_oe_nonabphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_nonabphy; + logic pa_dprio_block_select_nonabphy; + logic [PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_nonabphy; + + logic core2seq_reset_req_iotile_in; + logic pll_locked_iotile_in; + logic pll_dll_clk_iotile_in; + logic [7:0] phy_clk_phs_iotile_in; + logic [1:0] phy_clk_iotile_in; + logic phy_fb_clk_to_tile_iotile_in; + logic [1:0] core_clks_fb_to_cpa_pri_iotile_in; + logic [1:0] core_clks_fb_to_cpa_sec_iotile_in; + logic [62:0] core2ctl_avl_0_iotile_in; + logic [62:0] core2ctl_avl_1_iotile_in; + logic core2ctl_avl_rd_data_ready_0_iotile_in; + logic core2ctl_avl_rd_data_ready_1_iotile_in; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] core2l_wr_data_vld_ast_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] core2l_rd_data_rdy_ast_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][12:0] core2l_wr_ecc_info_iotile_in; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_read_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_write_iotile_in; + + logic [17:0] c2t_afi_iotile_in; + logic [41:0] core2ctl_sideband_0_iotile_in; + logic [41:0] core2ctl_sideband_1_iotile_in; + logic [50:0] core2ctl_mmr_0_iotile_in; + logic [50:0] core2ctl_mmr_1_iotile_in; + logic [PINS_IN_RTL_TILES-1:0] b2l_data_iotile_in; + logic [LANES_IN_RTL_TILES-1:0] b2t_dqs_iotile_in; + logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb_iotile_in; + logic cal_bus_clk_iotile_in; + logic cal_bus_avl_read_iotile_in; + logic cal_bus_avl_write_iotile_in; + logic [19:0] cal_bus_avl_address_iotile_in; + logic [31:0] cal_bus_avl_write_data_iotile_in; + logic pa_dprio_clk_iotile_in; + logic pa_dprio_read_iotile_in; + logic [PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr_iotile_in; + logic pa_dprio_rst_n_iotile_in; + logic pa_dprio_write_iotile_in; + logic [PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata_iotile_in; + + + altera_emif_arch_fm_io_tiles #( + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .DIAG_SEQ_RESET_AUTO_RELEASE (DIAG_SEQ_RESET_AUTO_RELEASE), + .DIAG_DB_RESET_AUTO_RELEASE (DIAG_DB_RESET_AUTO_RELEASE), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .PLL_MEM_CLK_FREQ_PS (PLL_MEM_CLK_FREQ_PS), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .PHY_MIMIC_HPS_EMIF (PHY_MIMIC_HPS_EMIF), + .CPA_FB_MUX_1_SEL (CPA_FB_MUX_1_SEL), + + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_CS_ADDR_WIDTH (PRI_HMC_CFG_CS_ADDR_WIDTH), + .PRI_HMC_CFG_COL_ADDR_WIDTH (PRI_HMC_CFG_COL_ADDR_WIDTH), + .PRI_HMC_CFG_ROW_ADDR_WIDTH (PRI_HMC_CFG_ROW_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_ADDR_WIDTH (PRI_HMC_CFG_BANK_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH (PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_CTRL_ENABLE_RC (PRI_HMC_CFG_CTRL_ENABLE_RC), + .PRI_HMC_CFG_DBC0_ENABLE_RC (PRI_HMC_CFG_DBC0_ENABLE_RC), + .PRI_HMC_CFG_DBC1_ENABLE_RC (PRI_HMC_CFG_DBC1_ENABLE_RC), + .PRI_HMC_CFG_DBC2_ENABLE_RC (PRI_HMC_CFG_DBC2_ENABLE_RC), + .PRI_HMC_CFG_DBC3_ENABLE_RC (PRI_HMC_CFG_DBC3_ENABLE_RC), + .PRI_HMC_CFG_CTRL_ENABLE_ECC (PRI_HMC_CFG_CTRL_ENABLE_ECC), + .PRI_HMC_CFG_DBC0_ENABLE_ECC (PRI_HMC_CFG_DBC0_ENABLE_ECC), + .PRI_HMC_CFG_DBC1_ENABLE_ECC (PRI_HMC_CFG_DBC1_ENABLE_ECC), + .PRI_HMC_CFG_DBC2_ENABLE_ECC (PRI_HMC_CFG_DBC2_ENABLE_ECC), + .PRI_HMC_CFG_DBC3_ENABLE_ECC (PRI_HMC_CFG_DBC3_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_CTRL_REORDER_RDATA (PRI_HMC_CFG_CTRL_REORDER_RDATA), + .PRI_HMC_CFG_DBC0_REORDER_RDATA (PRI_HMC_CFG_DBC0_REORDER_RDATA), + .PRI_HMC_CFG_DBC1_REORDER_RDATA (PRI_HMC_CFG_DBC1_REORDER_RDATA), + .PRI_HMC_CFG_DBC2_REORDER_RDATA (PRI_HMC_CFG_DBC2_REORDER_RDATA), + .PRI_HMC_CFG_DBC3_REORDER_RDATA (PRI_HMC_CFG_DBC3_REORDER_RDATA), + .PRI_HMC_CFG_CTRL_SLOT_OFFSET (PRI_HMC_CFG_CTRL_SLOT_OFFSET), + .PRI_HMC_CFG_DBC0_SLOT_OFFSET (PRI_HMC_CFG_DBC0_SLOT_OFFSET), + .PRI_HMC_CFG_DBC1_SLOT_OFFSET (PRI_HMC_CFG_DBC1_SLOT_OFFSET), + .PRI_HMC_CFG_DBC2_SLOT_OFFSET (PRI_HMC_CFG_DBC2_SLOT_OFFSET), + .PRI_HMC_CFG_DBC3_SLOT_OFFSET (PRI_HMC_CFG_DBC3_SLOT_OFFSET), + .PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN (PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ROW_TO_COL_OFFSET (PRI_HMC_CFG_ROW_TO_COL_OFFSET), + .PRI_HMC_CFG_ROW_TO_ROW_OFFSET (PRI_HMC_CFG_ROW_TO_ROW_OFFSET), + .PRI_HMC_CFG_COL_TO_COL_OFFSET (PRI_HMC_CFG_COL_TO_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET (PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_ROW_OFFSET (PRI_HMC_CFG_COL_TO_ROW_OFFSET), + .PRI_HMC_CFG_SIDEBAND_OFFSET (PRI_HMC_CFG_SIDEBAND_OFFSET), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_CTL_ODT_ENABLED (PRI_HMC_CFG_CTL_ODT_ENABLED), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_CMD_FIFO_RESERVE_EN (PRI_HMC_CFG_CMD_FIFO_RESERVE_EN), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_PHY_DELAY_MISMATCH (PRI_HMC_CFG_PHY_DELAY_MISMATCH), + .PRI_HMC_CFG_DQSTRK_EN (PRI_HMC_CFG_DQSTRK_EN), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN (PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD (PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_MEM_AUTO_PD_CYCLES (PRI_HMC_CFG_MEM_AUTO_PD_CYCLES), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_MEMCLKGATE_SETTING (PRI_HMC_MEMCLKGATE_SETTING), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_MEM_IF_AL (PRI_HMC_MEM_IF_AL), + .PRI_HMC_MEM_IF_CS_PER_DIMM (PRI_HMC_MEM_IF_CS_PER_DIMM), + .PRI_HMC_MEM_IF_RD_PREAMBLE (PRI_HMC_MEM_IF_RD_PREAMBLE), + .PRI_HMC_MEM_IF_TCCD (PRI_HMC_MEM_IF_TCCD), + .PRI_HMC_MEM_IF_TCCD_S (PRI_HMC_MEM_IF_TCCD_S), + .PRI_HMC_MEM_IF_TCKESR (PRI_HMC_MEM_IF_TCKESR), + .PRI_HMC_MEM_IF_TCKSRX (PRI_HMC_MEM_IF_TCKSRX), + .PRI_HMC_MEM_IF_TCL (PRI_HMC_MEM_IF_TCL), + .PRI_HMC_MEM_IF_TCWL (PRI_HMC_MEM_IF_TCWL), + .PRI_HMC_MEM_IF_TDQSCKMAX (PRI_HMC_MEM_IF_TDQSCKMAX), + .PRI_HMC_MEM_IF_TFAW (PRI_HMC_MEM_IF_TFAW), + .PRI_HMC_MEM_IF_TMOD (PRI_HMC_MEM_IF_TMOD), + .PRI_HMC_MEM_IF_TPL (PRI_HMC_MEM_IF_TPL), + .PRI_HMC_MEM_IF_TRAS (PRI_HMC_MEM_IF_TRAS), + .PRI_HMC_MEM_IF_TRC (PRI_HMC_MEM_IF_TRC), + .PRI_HMC_MEM_IF_TRCD (PRI_HMC_MEM_IF_TRCD), + .PRI_HMC_MEM_IF_TREFI (PRI_HMC_MEM_IF_TREFI), + .PRI_HMC_MEM_IF_TRFC (PRI_HMC_MEM_IF_TRFC), + .PRI_HMC_MEM_IF_TRP (PRI_HMC_MEM_IF_TRP), + .PRI_HMC_MEM_IF_TRRD (PRI_HMC_MEM_IF_TRRD), + .PRI_HMC_MEM_IF_TRRD_S (PRI_HMC_MEM_IF_TRRD_S), + .PRI_HMC_MEM_IF_TRTP (PRI_HMC_MEM_IF_TRTP), + .PRI_HMC_MEM_IF_TWR (PRI_HMC_MEM_IF_TWR), + .PRI_HMC_MEM_IF_TWR_CRC_DM (PRI_HMC_MEM_IF_TWR_CRC_DM), + .PRI_HMC_MEM_IF_TWTR (PRI_HMC_MEM_IF_TWTR), + .PRI_HMC_MEM_IF_TWTR_L_CRC_DM (PRI_HMC_MEM_IF_TWTR_L_CRC_DM), + .PRI_HMC_MEM_IF_TWTR_S (PRI_HMC_MEM_IF_TWTR_S), + .PRI_HMC_MEM_IF_TWTR_S_CRC_DM (PRI_HMC_MEM_IF_TWTR_S_CRC_DM), + .PRI_HMC_MEM_IF_TXP (PRI_HMC_MEM_IF_TXP), + .PRI_HMC_MEM_IF_TXPDLL (PRI_HMC_MEM_IF_TXPDLL), + .PRI_HMC_MEM_IF_TXSR (PRI_HMC_MEM_IF_TXSR), + .PRI_HMC_MEM_IF_TZQCS (PRI_HMC_MEM_IF_TZQCS), + .PRI_HMC_MEM_IF_TZQOPER (PRI_HMC_MEM_IF_TZQOPER), + .PRI_HMC_MEM_IF_WR_CRC (PRI_HMC_MEM_IF_WR_CRC), + .PRI_HMC_MEM_IF_WR_PREAMBLE (PRI_HMC_MEM_IF_WR_PREAMBLE), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR (PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_TEMP_4_ACT_TO_ACT (PRI_HMC_TEMP_4_ACT_TO_ACT), + .PRI_HMC_TEMP_RD_TO_RD_DIFF_BG (PRI_HMC_TEMP_RD_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD (PRI_HMC_TEMP_WR_TO_RD), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_BG (PRI_HMC_TEMP_WR_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP (PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_TEMP_WR_TO_WR_DIFF_BG (PRI_HMC_TEMP_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MAJOR_MODE_EN (PRI_HMC_CFG_MAJOR_MODE_EN), + .PRI_HMC_CFG_REFRESH_TYPE (PRI_HMC_CFG_REFRESH_TYPE), + .PRI_HMC_CFG_POST_REFRESH_EN (PRI_HMC_CFG_POST_REFRESH_EN), + .PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT (PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT), + .PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT (PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT), + .PRI_HMC_CFG_PRE_REFRESH_EN (PRI_HMC_CFG_PRE_REFRESH_EN), + .PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT), + .PRI_HMC_CHIP_ID (PRI_HMC_CHIP_ID), + .PRI_HMC_CID_ADDR_WIDTH (PRI_HMC_CID_ADDR_WIDTH), + .PRI_HMC_3DS_EN (PRI_HMC_3DS_EN), + .PRI_HMC_3DS_LR_NUM0 (PRI_HMC_3DS_LR_NUM0), + .PRI_HMC_3DS_LR_NUM1 (PRI_HMC_3DS_LR_NUM1), + .PRI_HMC_3DS_LR_NUM2 (PRI_HMC_3DS_LR_NUM2), + .PRI_HMC_3DS_LR_NUM3 (PRI_HMC_3DS_LR_NUM3), + .PRI_HMC_3DS_PR_STAG_ENABLE (PRI_HMC_3DS_PR_STAG_ENABLE), + .PRI_HMC_3DS_REF2REF_DLR (PRI_HMC_3DS_REF2REF_DLR), + .PRI_HMC_3DSREF_ACK_ON_DONE (PRI_HMC_3DSREF_ACK_ON_DONE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_CS_ADDR_WIDTH (SEC_HMC_CFG_CS_ADDR_WIDTH), + .SEC_HMC_CFG_COL_ADDR_WIDTH (SEC_HMC_CFG_COL_ADDR_WIDTH), + .SEC_HMC_CFG_ROW_ADDR_WIDTH (SEC_HMC_CFG_ROW_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_ADDR_WIDTH (SEC_HMC_CFG_BANK_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH (SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_CTRL_ENABLE_RC (SEC_HMC_CFG_CTRL_ENABLE_RC), + .SEC_HMC_CFG_DBC0_ENABLE_RC (SEC_HMC_CFG_DBC0_ENABLE_RC), + .SEC_HMC_CFG_DBC1_ENABLE_RC (SEC_HMC_CFG_DBC1_ENABLE_RC), + .SEC_HMC_CFG_DBC2_ENABLE_RC (SEC_HMC_CFG_DBC2_ENABLE_RC), + .SEC_HMC_CFG_DBC3_ENABLE_RC (SEC_HMC_CFG_DBC3_ENABLE_RC), + .SEC_HMC_CFG_CTRL_ENABLE_ECC (SEC_HMC_CFG_CTRL_ENABLE_ECC), + .SEC_HMC_CFG_DBC0_ENABLE_ECC (SEC_HMC_CFG_DBC0_ENABLE_ECC), + .SEC_HMC_CFG_DBC1_ENABLE_ECC (SEC_HMC_CFG_DBC1_ENABLE_ECC), + .SEC_HMC_CFG_DBC2_ENABLE_ECC (SEC_HMC_CFG_DBC2_ENABLE_ECC), + .SEC_HMC_CFG_DBC3_ENABLE_ECC (SEC_HMC_CFG_DBC3_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_CTRL_REORDER_RDATA (SEC_HMC_CFG_CTRL_REORDER_RDATA), + .SEC_HMC_CFG_DBC0_REORDER_RDATA (SEC_HMC_CFG_DBC0_REORDER_RDATA), + .SEC_HMC_CFG_DBC1_REORDER_RDATA (SEC_HMC_CFG_DBC1_REORDER_RDATA), + .SEC_HMC_CFG_DBC2_REORDER_RDATA (SEC_HMC_CFG_DBC2_REORDER_RDATA), + .SEC_HMC_CFG_DBC3_REORDER_RDATA (SEC_HMC_CFG_DBC3_REORDER_RDATA), + .SEC_HMC_CFG_CTRL_SLOT_OFFSET (SEC_HMC_CFG_CTRL_SLOT_OFFSET), + .SEC_HMC_CFG_DBC0_SLOT_OFFSET (SEC_HMC_CFG_DBC0_SLOT_OFFSET), + .SEC_HMC_CFG_DBC1_SLOT_OFFSET (SEC_HMC_CFG_DBC1_SLOT_OFFSET), + .SEC_HMC_CFG_DBC2_SLOT_OFFSET (SEC_HMC_CFG_DBC2_SLOT_OFFSET), + .SEC_HMC_CFG_DBC3_SLOT_OFFSET (SEC_HMC_CFG_DBC3_SLOT_OFFSET), + .SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN (SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ROW_TO_COL_OFFSET (SEC_HMC_CFG_ROW_TO_COL_OFFSET), + .SEC_HMC_CFG_ROW_TO_ROW_OFFSET (SEC_HMC_CFG_ROW_TO_ROW_OFFSET), + .SEC_HMC_CFG_COL_TO_COL_OFFSET (SEC_HMC_CFG_COL_TO_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET (SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_ROW_OFFSET (SEC_HMC_CFG_COL_TO_ROW_OFFSET), + .SEC_HMC_CFG_SIDEBAND_OFFSET (SEC_HMC_CFG_SIDEBAND_OFFSET), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_CTL_ODT_ENABLED (SEC_HMC_CFG_CTL_ODT_ENABLED), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_CMD_FIFO_RESERVE_EN (SEC_HMC_CFG_CMD_FIFO_RESERVE_EN), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_PHY_DELAY_MISMATCH (SEC_HMC_CFG_PHY_DELAY_MISMATCH), + .SEC_HMC_CFG_DQSTRK_EN (SEC_HMC_CFG_DQSTRK_EN), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN (SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD (SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_MEM_AUTO_PD_CYCLES (SEC_HMC_CFG_MEM_AUTO_PD_CYCLES), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_MEMCLKGATE_SETTING (SEC_HMC_MEMCLKGATE_SETTING), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_MEM_IF_AL (SEC_HMC_MEM_IF_AL), + .SEC_HMC_MEM_IF_CS_PER_DIMM (SEC_HMC_MEM_IF_CS_PER_DIMM), + .SEC_HMC_MEM_IF_RD_PREAMBLE (SEC_HMC_MEM_IF_RD_PREAMBLE), + .SEC_HMC_MEM_IF_TCCD (SEC_HMC_MEM_IF_TCCD), + .SEC_HMC_MEM_IF_TCCD_S (SEC_HMC_MEM_IF_TCCD_S), + .SEC_HMC_MEM_IF_TCKESR (SEC_HMC_MEM_IF_TCKESR), + .SEC_HMC_MEM_IF_TCKSRX (SEC_HMC_MEM_IF_TCKSRX), + .SEC_HMC_MEM_IF_TCL (SEC_HMC_MEM_IF_TCL), + .SEC_HMC_MEM_IF_TCWL (SEC_HMC_MEM_IF_TCWL), + .SEC_HMC_MEM_IF_TDQSCKMAX (SEC_HMC_MEM_IF_TDQSCKMAX), + .SEC_HMC_MEM_IF_TFAW (SEC_HMC_MEM_IF_TFAW), + .SEC_HMC_MEM_IF_TMOD (SEC_HMC_MEM_IF_TMOD), + .SEC_HMC_MEM_IF_TPL (SEC_HMC_MEM_IF_TPL), + .SEC_HMC_MEM_IF_TRAS (SEC_HMC_MEM_IF_TRAS), + .SEC_HMC_MEM_IF_TRC (SEC_HMC_MEM_IF_TRC), + .SEC_HMC_MEM_IF_TRCD (SEC_HMC_MEM_IF_TRCD), + .SEC_HMC_MEM_IF_TREFI (SEC_HMC_MEM_IF_TREFI), + .SEC_HMC_MEM_IF_TRFC (SEC_HMC_MEM_IF_TRFC), + .SEC_HMC_MEM_IF_TRP (SEC_HMC_MEM_IF_TRP), + .SEC_HMC_MEM_IF_TRRD (SEC_HMC_MEM_IF_TRRD), + .SEC_HMC_MEM_IF_TRRD_S (SEC_HMC_MEM_IF_TRRD_S), + .SEC_HMC_MEM_IF_TRTP (SEC_HMC_MEM_IF_TRTP), + .SEC_HMC_MEM_IF_TWR (SEC_HMC_MEM_IF_TWR), + .SEC_HMC_MEM_IF_TWR_CRC_DM (SEC_HMC_MEM_IF_TWR_CRC_DM), + .SEC_HMC_MEM_IF_TWTR (SEC_HMC_MEM_IF_TWTR), + .SEC_HMC_MEM_IF_TWTR_L_CRC_DM (SEC_HMC_MEM_IF_TWTR_L_CRC_DM), + .SEC_HMC_MEM_IF_TWTR_S (SEC_HMC_MEM_IF_TWTR_S), + .SEC_HMC_MEM_IF_TWTR_S_CRC_DM (SEC_HMC_MEM_IF_TWTR_S_CRC_DM), + .SEC_HMC_MEM_IF_TXP (SEC_HMC_MEM_IF_TXP), + .SEC_HMC_MEM_IF_TXPDLL (SEC_HMC_MEM_IF_TXPDLL), + .SEC_HMC_MEM_IF_TXSR (SEC_HMC_MEM_IF_TXSR), + .SEC_HMC_MEM_IF_TZQCS (SEC_HMC_MEM_IF_TZQCS), + .SEC_HMC_MEM_IF_TZQOPER (SEC_HMC_MEM_IF_TZQOPER), + .SEC_HMC_MEM_IF_WR_CRC (SEC_HMC_MEM_IF_WR_CRC), + .SEC_HMC_MEM_IF_WR_PREAMBLE (SEC_HMC_MEM_IF_WR_PREAMBLE), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR (SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_TEMP_4_ACT_TO_ACT (SEC_HMC_TEMP_4_ACT_TO_ACT), + .SEC_HMC_TEMP_RD_TO_RD_DIFF_BG (SEC_HMC_TEMP_RD_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD (SEC_HMC_TEMP_WR_TO_RD), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_BG (SEC_HMC_TEMP_WR_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP (SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_TEMP_WR_TO_WR_DIFF_BG (SEC_HMC_TEMP_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MAJOR_MODE_EN (SEC_HMC_CFG_MAJOR_MODE_EN), + .SEC_HMC_CFG_REFRESH_TYPE (SEC_HMC_CFG_REFRESH_TYPE), + .SEC_HMC_CFG_POST_REFRESH_EN (SEC_HMC_CFG_POST_REFRESH_EN), + .SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT (SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT), + .SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT (SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT), + .SEC_HMC_CFG_PRE_REFRESH_EN (SEC_HMC_CFG_PRE_REFRESH_EN), + .SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT), + .SEC_HMC_CHIP_ID (SEC_HMC_CHIP_ID), + .SEC_HMC_CID_ADDR_WIDTH (SEC_HMC_CID_ADDR_WIDTH), + .SEC_HMC_3DS_EN (SEC_HMC_3DS_EN), + .SEC_HMC_3DS_LR_NUM0 (SEC_HMC_3DS_LR_NUM0), + .SEC_HMC_3DS_LR_NUM1 (SEC_HMC_3DS_LR_NUM1), + .SEC_HMC_3DS_LR_NUM2 (SEC_HMC_3DS_LR_NUM2), + .SEC_HMC_3DS_LR_NUM3 (SEC_HMC_3DS_LR_NUM3), + .SEC_HMC_3DS_PR_STAG_ENABLE (SEC_HMC_3DS_PR_STAG_ENABLE), + .SEC_HMC_3DS_REF2REF_DLR (SEC_HMC_3DS_REF2REF_DLR), + .SEC_HMC_3DSREF_ACK_ON_DONE (SEC_HMC_3DSREF_ACK_ON_DONE), + + .SEQ_PT_CONTENT (SEQ_PT_CONTENT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .LANE_PIN_USAGE (LANE_PIN_USAGE), + .PINS_USAGE (PINS_USAGE), + .PINS_RATE (PINS_RATE), + .DB_PINS_PROC_MODE (DB_PINS_PROC_MODE), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_DCC_SPLIT (PINS_DCC_SPLIT), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .DBC_EXTRA_PIPE_STAGE_EN (DBC_EXTRA_PIPE_STAGE_EN), + .DBC_PIPE_LATS (DBC_PIPE_LATS), + .DB_PTR_PIPELINE_DEPTHS (DB_PTR_PIPELINE_DEPTHS), + .DB_SEQ_RD_EN_FULL_PIPELINES (DB_SEQ_RD_EN_FULL_PIPELINES), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DQSA_LGC_MODE (DQSA_LGC_MODE), + .DQSB_LGC_MODE (DQSB_LGC_MODE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH), + .PORT_CALBUS_ADDRESS_WIDTH (PORT_CALBUS_ADDRESS_WIDTH), + .PORT_CALBUS_RDATA_WIDTH (PORT_CALBUS_RDATA_WIDTH), + .PORT_CALBUS_WDATA_WIDTH (PORT_CALBUS_WDATA_WIDTH), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (PORT_CALBUS_SEQ_PARAM_TBL_WIDTH), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY) + ) io_tiles_inst ( + .core2seq_reset_req (core2seq_reset_req_iotile_in), + .pll_locked (pll_locked_iotile_in), + .pll_dll_clk (pll_dll_clk_iotile_in), + .phy_clk_phs (phy_clk_phs_iotile_in), + .phy_clk (phy_clk_iotile_in), + .global_phy_clk (global_phy_clk), + .phy_fb_clk_to_tile (phy_fb_clk_to_tile_iotile_in), + .core_clks_fb_to_cpa_pri (core_clks_fb_to_cpa_pri_iotile_in), + .core_clks_fb_to_cpa_sec (core_clks_fb_to_cpa_sec_iotile_in), + .core2ctl_avl_0 (core2ctl_avl_0_iotile_in), + .core2ctl_avl_1 (core2ctl_avl_1_iotile_in), + .core2ctl_avl_rd_data_ready_0 (core2ctl_avl_rd_data_ready_0_iotile_in), + .core2ctl_avl_rd_data_ready_1 (core2ctl_avl_rd_data_ready_1_iotile_in), + + .core2l_wr_data_vld_ast (core2l_wr_data_vld_ast_iotile_in), + .core2l_rd_data_rdy_ast (core2l_rd_data_rdy_ast_iotile_in), + .core2l_wr_ecc_info (core2l_wr_ecc_info_iotile_in), + + .core2l_data (core2l_data_iotile_in), + .core2l_oe (core2l_oe_iotile_in), + .core2l_rdata_en_full (core2l_rdata_en_full_iotile_in), + .core2l_mrnk_read (core2l_mrnk_read_iotile_in), + .core2l_mrnk_write (core2l_mrnk_write_iotile_in), + .c2t_afi (c2t_afi_iotile_in), + .core2ctl_sideband_0 (core2ctl_sideband_0_iotile_in), + .core2ctl_sideband_1 (core2ctl_sideband_1_iotile_in), + .core2ctl_mmr_0 (core2ctl_mmr_0_iotile_in), + .core2ctl_mmr_1 (core2ctl_mmr_1_iotile_in), + .b2l_data (b2l_data_iotile_in), + .b2t_dqs (b2t_dqs_iotile_in), + .b2t_dqsb (b2t_dqsb_iotile_in), + .cal_bus_clk (cal_bus_clk_iotile_in), + .cal_bus_avl_read (cal_bus_avl_read_iotile_in), + .cal_bus_avl_write (cal_bus_avl_write_iotile_in), + .cal_bus_avl_address (cal_bus_avl_address_iotile_in), + .cal_bus_avl_write_data (cal_bus_avl_write_data_iotile_in), + .pa_dprio_clk (pa_dprio_clk_iotile_in), + .pa_dprio_read (pa_dprio_read_iotile_in), + .pa_dprio_reg_addr (pa_dprio_reg_addr_iotile_in), + .pa_dprio_rst_n (pa_dprio_rst_n_iotile_in), + .pa_dprio_write (pa_dprio_write_iotile_in), + .pa_dprio_writedata (pa_dprio_writedata_iotile_in), + .* + ); + + generate + if ( DIAG_USE_ABSTRACT_PHY==1 ) begin : abphy_tiles + altera_emif_arch_fm_io_tiles_abphy # ( + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .MEM_ABPHY_VERBOSE (DIAG_SIM_VERBOSE_LEVEL >= 2), + .DIAG_SEQ_RESET_AUTO_RELEASE (DIAG_SEQ_RESET_AUTO_RELEASE), + .DIAG_DB_RESET_AUTO_RELEASE (DIAG_DB_RESET_AUTO_RELEASE), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_CS_ADDR_WIDTH (PRI_HMC_CFG_CS_ADDR_WIDTH), + .PRI_HMC_CFG_COL_ADDR_WIDTH (PRI_HMC_CFG_COL_ADDR_WIDTH), + .PRI_HMC_CFG_ROW_ADDR_WIDTH (PRI_HMC_CFG_ROW_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_ADDR_WIDTH (PRI_HMC_CFG_BANK_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH (PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_CTRL_ENABLE_RC (PRI_HMC_CFG_CTRL_ENABLE_RC), + .PRI_HMC_CFG_DBC0_ENABLE_RC (PRI_HMC_CFG_DBC0_ENABLE_RC), + .PRI_HMC_CFG_DBC1_ENABLE_RC (PRI_HMC_CFG_DBC1_ENABLE_RC), + .PRI_HMC_CFG_DBC2_ENABLE_RC (PRI_HMC_CFG_DBC2_ENABLE_RC), + .PRI_HMC_CFG_DBC3_ENABLE_RC (PRI_HMC_CFG_DBC3_ENABLE_RC), + .PRI_HMC_CFG_CTRL_ENABLE_ECC (PRI_HMC_CFG_CTRL_ENABLE_ECC), + .PRI_HMC_CFG_DBC0_ENABLE_ECC (PRI_HMC_CFG_DBC0_ENABLE_ECC), + .PRI_HMC_CFG_DBC1_ENABLE_ECC (PRI_HMC_CFG_DBC1_ENABLE_ECC), + .PRI_HMC_CFG_DBC2_ENABLE_ECC (PRI_HMC_CFG_DBC2_ENABLE_ECC), + .PRI_HMC_CFG_DBC3_ENABLE_ECC (PRI_HMC_CFG_DBC3_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_CTRL_REORDER_RDATA (PRI_HMC_CFG_CTRL_REORDER_RDATA), + .PRI_HMC_CFG_DBC0_REORDER_RDATA (PRI_HMC_CFG_DBC0_REORDER_RDATA), + .PRI_HMC_CFG_DBC1_REORDER_RDATA (PRI_HMC_CFG_DBC1_REORDER_RDATA), + .PRI_HMC_CFG_DBC2_REORDER_RDATA (PRI_HMC_CFG_DBC2_REORDER_RDATA), + .PRI_HMC_CFG_DBC3_REORDER_RDATA (PRI_HMC_CFG_DBC3_REORDER_RDATA), + .PRI_HMC_CFG_CTRL_SLOT_OFFSET (PRI_HMC_CFG_CTRL_SLOT_OFFSET), + .PRI_HMC_CFG_DBC0_SLOT_OFFSET (PRI_HMC_CFG_DBC0_SLOT_OFFSET), + .PRI_HMC_CFG_DBC1_SLOT_OFFSET (PRI_HMC_CFG_DBC1_SLOT_OFFSET), + .PRI_HMC_CFG_DBC2_SLOT_OFFSET (PRI_HMC_CFG_DBC2_SLOT_OFFSET), + .PRI_HMC_CFG_DBC3_SLOT_OFFSET (PRI_HMC_CFG_DBC3_SLOT_OFFSET), + .PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN (PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ROW_TO_COL_OFFSET (PRI_HMC_CFG_ROW_TO_COL_OFFSET), + .PRI_HMC_CFG_ROW_TO_ROW_OFFSET (PRI_HMC_CFG_ROW_TO_ROW_OFFSET), + .PRI_HMC_CFG_COL_TO_COL_OFFSET (PRI_HMC_CFG_COL_TO_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET (PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_ROW_OFFSET (PRI_HMC_CFG_COL_TO_ROW_OFFSET), + .PRI_HMC_CFG_SIDEBAND_OFFSET (PRI_HMC_CFG_SIDEBAND_OFFSET), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_CTL_ODT_ENABLED (PRI_HMC_CFG_CTL_ODT_ENABLED), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_CMD_FIFO_RESERVE_EN (PRI_HMC_CFG_CMD_FIFO_RESERVE_EN), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_PHY_DELAY_MISMATCH (PRI_HMC_CFG_PHY_DELAY_MISMATCH), + .PRI_HMC_CFG_DQSTRK_EN (PRI_HMC_CFG_DQSTRK_EN), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN (PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD (PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_MEM_AUTO_PD_CYCLES (PRI_HMC_CFG_MEM_AUTO_PD_CYCLES), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_MEMCLKGATE_SETTING (PRI_HMC_MEMCLKGATE_SETTING), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_MEM_IF_AL (PRI_HMC_MEM_IF_AL), + .PRI_HMC_MEM_IF_CS_PER_DIMM (PRI_HMC_MEM_IF_CS_PER_DIMM), + .PRI_HMC_MEM_IF_RD_PREAMBLE (PRI_HMC_MEM_IF_RD_PREAMBLE), + .PRI_HMC_MEM_IF_TCCD (PRI_HMC_MEM_IF_TCCD), + .PRI_HMC_MEM_IF_TCCD_S (PRI_HMC_MEM_IF_TCCD_S), + .PRI_HMC_MEM_IF_TCKESR (PRI_HMC_MEM_IF_TCKESR), + .PRI_HMC_MEM_IF_TCKSRX (PRI_HMC_MEM_IF_TCKSRX), + .PRI_HMC_MEM_IF_TCL (PRI_HMC_MEM_IF_TCL), + .PRI_HMC_MEM_IF_TCWL (PRI_HMC_MEM_IF_TCWL), + .PRI_HMC_MEM_IF_TDQSCKMAX (PRI_HMC_MEM_IF_TDQSCKMAX), + .PRI_HMC_MEM_IF_TFAW (PRI_HMC_MEM_IF_TFAW), + .PRI_HMC_MEM_IF_TMOD (PRI_HMC_MEM_IF_TMOD), + .PRI_HMC_MEM_IF_TPL (PRI_HMC_MEM_IF_TPL), + .PRI_HMC_MEM_IF_TRAS (PRI_HMC_MEM_IF_TRAS), + .PRI_HMC_MEM_IF_TRC (PRI_HMC_MEM_IF_TRC), + .PRI_HMC_MEM_IF_TRCD (PRI_HMC_MEM_IF_TRCD), + .PRI_HMC_MEM_IF_TREFI (PRI_HMC_MEM_IF_TREFI), + .PRI_HMC_MEM_IF_TRFC (PRI_HMC_MEM_IF_TRFC), + .PRI_HMC_MEM_IF_TRP (PRI_HMC_MEM_IF_TRP), + .PRI_HMC_MEM_IF_TRRD (PRI_HMC_MEM_IF_TRRD), + .PRI_HMC_MEM_IF_TRRD_S (PRI_HMC_MEM_IF_TRRD_S), + .PRI_HMC_MEM_IF_TRTP (PRI_HMC_MEM_IF_TRTP), + .PRI_HMC_MEM_IF_TWR (PRI_HMC_MEM_IF_TWR), + .PRI_HMC_MEM_IF_TWR_CRC_DM (PRI_HMC_MEM_IF_TWR_CRC_DM), + .PRI_HMC_MEM_IF_TWTR (PRI_HMC_MEM_IF_TWTR), + .PRI_HMC_MEM_IF_TWTR_L_CRC_DM (PRI_HMC_MEM_IF_TWTR_L_CRC_DM), + .PRI_HMC_MEM_IF_TWTR_S (PRI_HMC_MEM_IF_TWTR_S), + .PRI_HMC_MEM_IF_TWTR_S_CRC_DM (PRI_HMC_MEM_IF_TWTR_S_CRC_DM), + .PRI_HMC_MEM_IF_TXP (PRI_HMC_MEM_IF_TXP), + .PRI_HMC_MEM_IF_TXPDLL (PRI_HMC_MEM_IF_TXPDLL), + .PRI_HMC_MEM_IF_TXSR (PRI_HMC_MEM_IF_TXSR), + .PRI_HMC_MEM_IF_TZQCS (PRI_HMC_MEM_IF_TZQCS), + .PRI_HMC_MEM_IF_TZQOPER (PRI_HMC_MEM_IF_TZQOPER), + .PRI_HMC_MEM_IF_WR_CRC (PRI_HMC_MEM_IF_WR_CRC), + .PRI_HMC_MEM_IF_WR_PREAMBLE (PRI_HMC_MEM_IF_WR_PREAMBLE), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR (PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_TEMP_4_ACT_TO_ACT (PRI_HMC_TEMP_4_ACT_TO_ACT), + .PRI_HMC_TEMP_RD_TO_RD_DIFF_BG (PRI_HMC_TEMP_RD_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD (PRI_HMC_TEMP_WR_TO_RD), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_BG (PRI_HMC_TEMP_WR_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP (PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_TEMP_WR_TO_WR_DIFF_BG (PRI_HMC_TEMP_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CHIP_ID (PRI_HMC_CHIP_ID), + .PRI_HMC_CID_ADDR_WIDTH (PRI_HMC_CID_ADDR_WIDTH), + .PRI_HMC_3DS_EN (PRI_HMC_3DS_EN), + .PRI_HMC_3DS_LR_NUM0 (PRI_HMC_3DS_LR_NUM0), + .PRI_HMC_3DS_LR_NUM1 (PRI_HMC_3DS_LR_NUM1), + .PRI_HMC_3DS_LR_NUM2 (PRI_HMC_3DS_LR_NUM2), + .PRI_HMC_3DS_LR_NUM3 (PRI_HMC_3DS_LR_NUM3), + .PRI_HMC_3DS_PR_STAG_ENABLE (PRI_HMC_3DS_PR_STAG_ENABLE), + .PRI_HMC_3DS_REF2REF_DLR (PRI_HMC_3DS_REF2REF_DLR), + .PRI_HMC_3DSREF_ACK_ON_DONE (PRI_HMC_3DSREF_ACK_ON_DONE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_CS_ADDR_WIDTH (SEC_HMC_CFG_CS_ADDR_WIDTH), + .SEC_HMC_CFG_COL_ADDR_WIDTH (SEC_HMC_CFG_COL_ADDR_WIDTH), + .SEC_HMC_CFG_ROW_ADDR_WIDTH (SEC_HMC_CFG_ROW_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_ADDR_WIDTH (SEC_HMC_CFG_BANK_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH (SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_CTRL_ENABLE_RC (SEC_HMC_CFG_CTRL_ENABLE_RC), + .SEC_HMC_CFG_DBC0_ENABLE_RC (SEC_HMC_CFG_DBC0_ENABLE_RC), + .SEC_HMC_CFG_DBC1_ENABLE_RC (SEC_HMC_CFG_DBC1_ENABLE_RC), + .SEC_HMC_CFG_DBC2_ENABLE_RC (SEC_HMC_CFG_DBC2_ENABLE_RC), + .SEC_HMC_CFG_DBC3_ENABLE_RC (SEC_HMC_CFG_DBC3_ENABLE_RC), + .SEC_HMC_CFG_CTRL_ENABLE_ECC (SEC_HMC_CFG_CTRL_ENABLE_ECC), + .SEC_HMC_CFG_DBC0_ENABLE_ECC (SEC_HMC_CFG_DBC0_ENABLE_ECC), + .SEC_HMC_CFG_DBC1_ENABLE_ECC (SEC_HMC_CFG_DBC1_ENABLE_ECC), + .SEC_HMC_CFG_DBC2_ENABLE_ECC (SEC_HMC_CFG_DBC2_ENABLE_ECC), + .SEC_HMC_CFG_DBC3_ENABLE_ECC (SEC_HMC_CFG_DBC3_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_CTRL_REORDER_RDATA (SEC_HMC_CFG_CTRL_REORDER_RDATA), + .SEC_HMC_CFG_DBC0_REORDER_RDATA (SEC_HMC_CFG_DBC0_REORDER_RDATA), + .SEC_HMC_CFG_DBC1_REORDER_RDATA (SEC_HMC_CFG_DBC1_REORDER_RDATA), + .SEC_HMC_CFG_DBC2_REORDER_RDATA (SEC_HMC_CFG_DBC2_REORDER_RDATA), + .SEC_HMC_CFG_DBC3_REORDER_RDATA (SEC_HMC_CFG_DBC3_REORDER_RDATA), + .SEC_HMC_CFG_CTRL_SLOT_OFFSET (SEC_HMC_CFG_CTRL_SLOT_OFFSET), + .SEC_HMC_CFG_DBC0_SLOT_OFFSET (SEC_HMC_CFG_DBC0_SLOT_OFFSET), + .SEC_HMC_CFG_DBC1_SLOT_OFFSET (SEC_HMC_CFG_DBC1_SLOT_OFFSET), + .SEC_HMC_CFG_DBC2_SLOT_OFFSET (SEC_HMC_CFG_DBC2_SLOT_OFFSET), + .SEC_HMC_CFG_DBC3_SLOT_OFFSET (SEC_HMC_CFG_DBC3_SLOT_OFFSET), + .SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN (SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ROW_TO_COL_OFFSET (SEC_HMC_CFG_ROW_TO_COL_OFFSET), + .SEC_HMC_CFG_ROW_TO_ROW_OFFSET (SEC_HMC_CFG_ROW_TO_ROW_OFFSET), + .SEC_HMC_CFG_COL_TO_COL_OFFSET (SEC_HMC_CFG_COL_TO_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET (SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_ROW_OFFSET (SEC_HMC_CFG_COL_TO_ROW_OFFSET), + .SEC_HMC_CFG_SIDEBAND_OFFSET (SEC_HMC_CFG_SIDEBAND_OFFSET), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_CTL_ODT_ENABLED (SEC_HMC_CFG_CTL_ODT_ENABLED), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_CMD_FIFO_RESERVE_EN (SEC_HMC_CFG_CMD_FIFO_RESERVE_EN), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_PHY_DELAY_MISMATCH (SEC_HMC_CFG_PHY_DELAY_MISMATCH), + .SEC_HMC_CFG_DQSTRK_EN (SEC_HMC_CFG_DQSTRK_EN), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN (SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD (SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_MEM_AUTO_PD_CYCLES (SEC_HMC_CFG_MEM_AUTO_PD_CYCLES), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_MEMCLKGATE_SETTING (SEC_HMC_MEMCLKGATE_SETTING), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_MEM_IF_AL (SEC_HMC_MEM_IF_AL), + .SEC_HMC_MEM_IF_CS_PER_DIMM (SEC_HMC_MEM_IF_CS_PER_DIMM), + .SEC_HMC_MEM_IF_RD_PREAMBLE (SEC_HMC_MEM_IF_RD_PREAMBLE), + .SEC_HMC_MEM_IF_TCCD (SEC_HMC_MEM_IF_TCCD), + .SEC_HMC_MEM_IF_TCCD_S (SEC_HMC_MEM_IF_TCCD_S), + .SEC_HMC_MEM_IF_TCKESR (SEC_HMC_MEM_IF_TCKESR), + .SEC_HMC_MEM_IF_TCKSRX (SEC_HMC_MEM_IF_TCKSRX), + .SEC_HMC_MEM_IF_TCL (SEC_HMC_MEM_IF_TCL), + .SEC_HMC_MEM_IF_TCWL (SEC_HMC_MEM_IF_TCWL), + .SEC_HMC_MEM_IF_TDQSCKMAX (SEC_HMC_MEM_IF_TDQSCKMAX), + .SEC_HMC_MEM_IF_TFAW (SEC_HMC_MEM_IF_TFAW), + .SEC_HMC_MEM_IF_TMOD (SEC_HMC_MEM_IF_TMOD), + .SEC_HMC_MEM_IF_TPL (SEC_HMC_MEM_IF_TPL), + .SEC_HMC_MEM_IF_TRAS (SEC_HMC_MEM_IF_TRAS), + .SEC_HMC_MEM_IF_TRC (SEC_HMC_MEM_IF_TRC), + .SEC_HMC_MEM_IF_TRCD (SEC_HMC_MEM_IF_TRCD), + .SEC_HMC_MEM_IF_TREFI (SEC_HMC_MEM_IF_TREFI), + .SEC_HMC_MEM_IF_TRFC (SEC_HMC_MEM_IF_TRFC), + .SEC_HMC_MEM_IF_TRP (SEC_HMC_MEM_IF_TRP), + .SEC_HMC_MEM_IF_TRRD (SEC_HMC_MEM_IF_TRRD), + .SEC_HMC_MEM_IF_TRRD_S (SEC_HMC_MEM_IF_TRRD_S), + .SEC_HMC_MEM_IF_TRTP (SEC_HMC_MEM_IF_TRTP), + .SEC_HMC_MEM_IF_TWR (SEC_HMC_MEM_IF_TWR), + .SEC_HMC_MEM_IF_TWR_CRC_DM (SEC_HMC_MEM_IF_TWR_CRC_DM), + .SEC_HMC_MEM_IF_TWTR (SEC_HMC_MEM_IF_TWTR), + .SEC_HMC_MEM_IF_TWTR_L_CRC_DM (SEC_HMC_MEM_IF_TWTR_L_CRC_DM), + .SEC_HMC_MEM_IF_TWTR_S (SEC_HMC_MEM_IF_TWTR_S), + .SEC_HMC_MEM_IF_TWTR_S_CRC_DM (SEC_HMC_MEM_IF_TWTR_S_CRC_DM), + .SEC_HMC_MEM_IF_TXP (SEC_HMC_MEM_IF_TXP), + .SEC_HMC_MEM_IF_TXPDLL (SEC_HMC_MEM_IF_TXPDLL), + .SEC_HMC_MEM_IF_TXSR (SEC_HMC_MEM_IF_TXSR), + .SEC_HMC_MEM_IF_TZQCS (SEC_HMC_MEM_IF_TZQCS), + .SEC_HMC_MEM_IF_TZQOPER (SEC_HMC_MEM_IF_TZQOPER), + .SEC_HMC_MEM_IF_WR_CRC (SEC_HMC_MEM_IF_WR_CRC), + .SEC_HMC_MEM_IF_WR_PREAMBLE (SEC_HMC_MEM_IF_WR_PREAMBLE), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR (SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_TEMP_4_ACT_TO_ACT (SEC_HMC_TEMP_4_ACT_TO_ACT), + .SEC_HMC_TEMP_RD_TO_RD_DIFF_BG (SEC_HMC_TEMP_RD_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD (SEC_HMC_TEMP_WR_TO_RD), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_BG (SEC_HMC_TEMP_WR_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP (SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_TEMP_WR_TO_WR_DIFF_BG (SEC_HMC_TEMP_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CHIP_ID (SEC_HMC_CHIP_ID), + .SEC_HMC_CID_ADDR_WIDTH (SEC_HMC_CID_ADDR_WIDTH), + .SEC_HMC_3DS_EN (SEC_HMC_3DS_EN), + .SEC_HMC_3DS_LR_NUM0 (SEC_HMC_3DS_LR_NUM0), + .SEC_HMC_3DS_LR_NUM1 (SEC_HMC_3DS_LR_NUM1), + .SEC_HMC_3DS_LR_NUM2 (SEC_HMC_3DS_LR_NUM2), + .SEC_HMC_3DS_LR_NUM3 (SEC_HMC_3DS_LR_NUM3), + .SEC_HMC_3DS_PR_STAG_ENABLE (SEC_HMC_3DS_PR_STAG_ENABLE), + .SEC_HMC_3DS_REF2REF_DLR (SEC_HMC_3DS_REF2REF_DLR), + .SEC_HMC_3DSREF_ACK_ON_DONE (SEC_HMC_3DSREF_ACK_ON_DONE), + + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .PINS_USAGE (PINS_USAGE), + .PINS_RATE (PINS_RATE), + .DB_PINS_PROC_MODE (DB_PINS_PROC_MODE), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_DCC_SPLIT (PINS_DCC_SPLIT), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .DBC_PIPE_LATS (DBC_PIPE_LATS), + .DB_PTR_PIPELINE_DEPTHS (DB_PTR_PIPELINE_DEPTHS), + .DB_SEQ_RD_EN_FULL_PIPELINES (DB_SEQ_RD_EN_FULL_PIPELINES), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DQSA_LGC_MODE (DQSA_LGC_MODE), + .DQSB_LGC_MODE (DQSB_LGC_MODE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH), + + .PORT_CALBUS_ADDRESS_WIDTH (PORT_CALBUS_ADDRESS_WIDTH), + .PORT_CALBUS_RDATA_WIDTH (PORT_CALBUS_RDATA_WIDTH), + .PORT_CALBUS_WDATA_WIDTH (PORT_CALBUS_WDATA_WIDTH), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (PORT_CALBUS_SEQ_PARAM_TBL_WIDTH), + + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL) + ) io_tiles_abphy_inst ( + .* + ); + end + else begin : nonabphy_setoutputs + assign phy_fb_clk_to_pll_abphy = 'd0; + assign core_clks_from_cpa_pri_abphy = 'd0; + assign core_clks_locked_cpa_pri_abphy = 'd0; + assign core_clks_from_cpa_sec_abphy = 'd0; + assign core_clks_locked_cpa_sec_abphy = 'd0; + assign ctl2core_avl_cmd_ready_0_abphy = 'd0; + assign ctl2core_avl_cmd_ready_1_abphy = 'd0; + assign ctl2core_avl_rdata_id_0_abphy = 'd0; + assign ctl2core_avl_rdata_id_1_abphy = 'd0; + assign l2core_rd_data_vld_avl_abphy = 'd0; + assign l2core_wr_data_rdy_ast_abphy = 'd0; + assign l2core_wb_pointer_for_ecc_abphy = 'd0; + assign l2core_data_abphy = 'd0; + assign l2core_rdata_valid_abphy = 'd0; + assign l2core_afi_rlat_abphy = 'd0; + assign l2core_afi_wlat_abphy = 'd0; + assign t2c_afi_abphy = 'd0; + assign ctl2core_sideband_0_abphy = 'd0; + assign ctl2core_sideband_1_abphy = 'd0; + assign ctl2core_mmr_0_abphy = 'd0; + assign ctl2core_mmr_1_abphy = 'd0; + assign l2b_data_abphy = 'd0; + assign l2b_oe_abphy = 'd0; + assign l2b_dtc_abphy = 'd0; + assign pa_dprio_block_select_abphy = 'd0; + assign pa_dprio_readdata_abphy = 'd0; + assign runAbstractPhySim = 'd0; + end + endgenerate + +/* + altera_emif_arch_fm_abphy_mux #( + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH), + .PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES) + ) altera_emif_arch_fm_abphy_mux_inst ( + .* + ); +*/ + integer i, j; + + assign phy_fb_clk_to_pll = phy_fb_clk_to_pll_nonabphy; + assign core_clks_from_cpa_pri = core_clks_from_cpa_pri_nonabphy; + assign core_clks_locked_cpa_pri = core_clks_locked_cpa_pri_nonabphy; + assign core_clks_from_cpa_sec = core_clks_from_cpa_sec_nonabphy; + assign core_clks_locked_cpa_sec = core_clks_locked_cpa_sec_nonabphy; + assign ctl2core_avl_cmd_ready_0 = ctl2core_avl_cmd_ready_0_nonabphy; + assign ctl2core_avl_cmd_ready_1 = ctl2core_avl_cmd_ready_1_nonabphy; + assign ctl2core_avl_rdata_id_0 = ctl2core_avl_rdata_id_0_nonabphy; + assign ctl2core_avl_rdata_id_1 = ctl2core_avl_rdata_id_1_nonabphy; + assign l2core_rd_type = l2core_rd_type_nonabphy; + assign l2core_rd_data_vld_avl = l2core_rd_data_vld_avl_nonabphy; + assign l2core_wr_data_rdy_ast = l2core_wr_data_rdy_ast_nonabphy; + assign l2core_wb_pointer_for_ecc = l2core_wb_pointer_for_ecc_nonabphy; + assign l2core_data = l2core_data_nonabphy; + assign l2core_rdata_valid_pri = l2core_rdata_valid_nonabphy_pri; + assign l2core_rdata_valid_sec = l2core_rdata_valid_nonabphy_sec; + assign l2core_afi_rlat = l2core_afi_rlat_nonabphy; + assign l2core_afi_wlat = l2core_afi_wlat_nonabphy; + assign t2c_afi = t2c_afi_nonabphy; + assign ctl2core_sideband_0 = ctl2core_sideband_0_nonabphy; + assign ctl2core_sideband_1 = ctl2core_sideband_1_nonabphy; + assign ctl2core_mmr_0 = ctl2core_mmr_0_nonabphy; + assign ctl2core_mmr_1 = ctl2core_mmr_1_nonabphy; + assign l2b_data = l2b_data_nonabphy; + assign l2b_oe = l2b_oe_nonabphy; + assign l2b_dtc = l2b_dtc_nonabphy; + assign pa_dprio_block_select = pa_dprio_block_select_nonabphy; + assign pa_dprio_readdata = pa_dprio_readdata_nonabphy; + + assign core2seq_reset_req_iotile_in = core2seq_reset_req; + assign pll_locked_iotile_in = pll_locked; + assign pll_dll_clk_iotile_in = pll_dll_clk; + assign phy_clk_phs_iotile_in = phy_clk_phs; + assign phy_clk_iotile_in = phy_clk; + assign phy_fb_clk_to_tile_iotile_in = phy_fb_clk_to_tile; + assign core_clks_fb_to_cpa_pri_iotile_in = core_clks_fb_to_cpa_pri; + assign core_clks_fb_to_cpa_sec_iotile_in = core_clks_fb_to_cpa_sec; + assign core2ctl_avl_0_iotile_in = core2ctl_avl_0; + assign core2ctl_avl_1_iotile_in = core2ctl_avl_1; + assign core2ctl_avl_rd_data_ready_0_iotile_in = core2ctl_avl_rd_data_ready_0; + assign core2ctl_avl_rd_data_ready_1_iotile_in = core2ctl_avl_rd_data_ready_1; + assign core2l_wr_data_vld_ast_iotile_in = core2l_wr_data_vld_ast; + assign core2l_rd_data_rdy_ast_iotile_in = core2l_rd_data_rdy_ast; + + assign core2l_wr_ecc_info_iotile_in = core2l_wr_ecc_info; + + assign core2l_data_iotile_in = core2l_data; + assign core2l_oe_iotile_in = core2l_oe; + assign core2l_rdata_en_full_iotile_in = core2l_rdata_en_full; + assign core2l_mrnk_read_iotile_in = core2l_mrnk_read; + assign core2l_mrnk_write_iotile_in = core2l_mrnk_write; + assign c2t_afi_iotile_in = c2t_afi; + assign core2ctl_sideband_0_iotile_in = core2ctl_sideband_0; + assign core2ctl_sideband_1_iotile_in = core2ctl_sideband_1; + assign core2ctl_mmr_0_iotile_in = core2ctl_mmr_0; + assign core2ctl_mmr_1_iotile_in = core2ctl_mmr_1; + assign b2l_data_iotile_in = b2l_data; + assign b2t_dqs_iotile_in = b2t_dqs; + assign b2t_dqsb_iotile_in = b2t_dqsb; + assign cal_bus_clk_iotile_in = cal_bus_clk; + assign cal_bus_avl_read_iotile_in = cal_bus_avl_read; + assign cal_bus_avl_write_iotile_in = cal_bus_avl_write; + assign cal_bus_avl_address_iotile_in = cal_bus_avl_address; + assign cal_bus_avl_write_data_iotile_in = cal_bus_avl_write_data; + assign pa_dprio_clk_iotile_in = pa_dprio_clk; + assign pa_dprio_read_iotile_in = pa_dprio_read; + assign pa_dprio_reg_addr_iotile_in = pa_dprio_reg_addr; + assign pa_dprio_rst_n_iotile_in = pa_dprio_rst_n; + assign pa_dprio_write_iotile_in = pa_dprio_write; + assign pa_dprio_writedata_iotile_in = pa_dprio_writedata; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2/39q+AmDu8QJxXn7LyuCABXcorJ3Lyxu8VEEQLtH3S33YEzTsMstzJheypEkpInhXf0oEr5v4zdu23PCpjuwkKBG08tc5gKJR8RP2Pa+PDZeBPzWTHmPJjg45HpXlBwqsuFZu3CeWI7qaNyIAxriTgXWZ4x1+u59EYY7yOU40y7H5XC3dylKauTaR+LOTaJTNIBo0H0THmrcV10fKJdjujFviDoo+arc7eA/Z6jy6e6TSVSFSF28Kj82oPKJ+l7XdnXc31ojN3vjdjVtFflEr1J2kP6M3eAg3x3V4E/9w5X7A6+Lj1njPqCcYbBr9twy4ksR/pmpfYOi+SHlqKWtYhR2fYUhj6dNWOVeHJjbX2Lw/2PueiAgdBCLUwNNF973Zx3g5D7SsUmoxclHciXaoSAu7xZgqWQvrHYJ1DbutxRJBz9UO5/wvFII+n1ZvfI4s6l6jDripref1i1eoCcKRyyiXl4CMroWaNvh1mwe5vgPTB4UsFNfQYs72auRyuHm1X6zEQ2VEdUtVsr11+CdI98Eq1yLoxm3Csc6YuQndm+VrLvgJmFPuNQQtO/PIdQExPjZNbaZkdCthNOnzEWu1+2Xeerj6yz5zUz5q98gf4wlKO0/980xjxY/+Q+KJbPk7NDGs9KDB29tw8IpnJJW/WVENXpMphVBDykpqSP83CfDRO8T0sqIU2pRQakJA+WGu+4vu4RojNWe8/oG7fnhJHuYf6oxsRFar33ielWjVwaYfeqQAxsjoevbhg0kLatmSJZNdCb19t5anRcztLLhb" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_local_reset.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_local_reset.sv new file mode 100644 index 0000000000..9d20d6f358 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_local_reset.sv @@ -0,0 +1,167 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// Reset request sequencing state machine. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_fm_local_reset # ( + parameter PHY_CONFIG_ENUM = "", + parameter IS_HPS = 0 +) ( + input logic afi_clk, + input logic afi_reset_n, + input logic emif_usr_clk, + input logic emif_usr_reset_n, + + input logic local_reset_req_int, + output logic core2seq_reset_req, + + output logic local_reset_done, + input logic seq2core_reset_done +); + timeunit 1ns; + timeprecision 1ps; + + typedef enum { + WAIT_RESET_DONE, + WAIT_USER_RESET_REQ_1ST_DEASSERT, + WAIT_USER_RESET_REQ_ASSERT, + WAIT_USER_RESET_REQ_2ND_DEASSERT, + ASSERT_CORE2SEQ_RESET_REQ + } state_t; + + generate + if (IS_HPS) begin: hps + assign core2seq_reset_req = 1'b0; + assign local_reset_done = 1'b0; + end else begin : non_hps + logic clk; + logic reset_n; + + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") begin : hmc + assign clk = emif_usr_clk; + assign reset_n = emif_usr_reset_n; + end else begin : non_hmc + assign clk = afi_clk; + assign reset_n = afi_reset_n; + end + + //////////////////////////////////////////////////////////////////// + // State machine + //////////////////////////////////////////////////////////////////// + state_t state /* synthesis ignore_power_up */; + logic core2seq_reset_req_r /* synthesis ignore_power_up dont_merge syn_noprune syn_preserve = 1 */; + logic local_reset_done_r /* synthesis ignore_power_up dont_merge syn_noprune syn_preserve = 1 */; + + always_ff @(posedge clk, negedge reset_n) + begin + if (!reset_n) begin + state <= WAIT_RESET_DONE; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b0; + end else begin + case (state) + WAIT_RESET_DONE: + begin + // Wait until sequencer signals it's ready to accept a reset request. + if (seq2core_reset_done) begin + if (local_reset_req_int == 1'b1) begin + state <= WAIT_USER_RESET_REQ_1ST_DEASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end else begin + state <= WAIT_USER_RESET_REQ_ASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end + end + else + begin + state <= WAIT_RESET_DONE; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b0; + end + end + + WAIT_USER_RESET_REQ_1ST_DEASSERT: + begin + if (~local_reset_req_int) begin + state <= WAIT_USER_RESET_REQ_ASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end else begin + state <= WAIT_USER_RESET_REQ_1ST_DEASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end + end + + WAIT_USER_RESET_REQ_ASSERT: + begin + if (local_reset_req_int) begin + state <= WAIT_USER_RESET_REQ_2ND_DEASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end else begin + state <= WAIT_USER_RESET_REQ_ASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end + + end + + WAIT_USER_RESET_REQ_2ND_DEASSERT: + begin + if (~local_reset_req_int) begin + state <= ASSERT_CORE2SEQ_RESET_REQ; + core2seq_reset_req_r <= 1'b1; + local_reset_done_r <= 1'b0; + end else begin + state <= WAIT_USER_RESET_REQ_2ND_DEASSERT; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b1; + end + end + + ASSERT_CORE2SEQ_RESET_REQ: + begin + state <= ASSERT_CORE2SEQ_RESET_REQ; + core2seq_reset_req_r <= 1'b1; + local_reset_done_r <= 1'b0; + end + default: + begin + state <= WAIT_RESET_DONE; + core2seq_reset_req_r <= 1'b0; + local_reset_done_r <= 1'b0; + end + endcase + end + end + + //////////////////////////////////////////////////////////////////// + // Output generation + //////////////////////////////////////////////////////////////////// + assign core2seq_reset_req = core2seq_reset_req_r; + + // Instead of passing seq2core_reset_done directly to user, we have the ability + // to acknowledge the reset request earlier, as soon as a local_reset_req pulse + // is detected. + assign local_reset_done = local_reset_done_r; + end + endgenerate +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm17Lw9A+Y1qL6DKmZb6gNVp9ibcm6scere9epDXTC/2vzfNVlWzB7JrJDsxI4z+NLDxVyeb/fRVHzbHATHTA+3LN523uM+Wv4CQEwz9JO1ReHQQBFMj9RERCsr65s4/Zk0DERrPpuIEeJVFGBx/Iqvp6YtXZNnQo8DTvrdTmC2geBEMESzW5fZ//rcOboyFXIWtfNWiy+OQwrLypjC4gUWVwvEpq/iP422FqxX09YuKbuoWpi6POlvLNJdhu5F6KT8u0vIL9+zxUCK/GUxoVl7QzvG5dYjDskh5DZ8yuSbEfnZZTvFPD3MauEbN7jnpgA8kXniSqCOpQjg83tp8Dmx0/AHba1qxSE6/ZmL8Oe0liDqw0b/zpJacWiNzXM0+ZLW+jL5iVbPRqXd7eq1E+e6s0TfSDeBFgHIwfusfMMTcsQt913WtGFxfK/e8Z2f86iM2RRSLJ3dJ6dBmrO/jj9v1B8skKwgnqZ0cncrNsd4FkHlu5/qNEXg8WjCeW3d7yHWUAreteELxypgp6N8D5qIHgdVrOU9bjt0zRGvfkMalGGC+Ic1bhQ/VekVN90ky6fSI74OJopRZBoYk7XFyjm/aB6v6Gd/iWTd0F8jjBHHPv0WgEGFCMTU2T3SUgu8Zx1AfEfxDiWqsjg3z3Bjag0vY45foDi55s22f2GjjgkrrxXmGALi4fbxAeF7vxUh+Ur8C9TjWBlU4CNO/yKX49Huugt6l728z9s18vUX8McJdSZnFPS2/fHF4CO/oKHMc8EV6RmeO7sEP36yoSAkymiIo" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_oct.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_oct.sv new file mode 100644 index 0000000000..cfaec4ffb7 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_oct.sv @@ -0,0 +1,36 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +module altera_emif_arch_fm_oct #( + parameter PHY_CALIBRATED_OCT = 0 +) ( + input logic oct_rzqin, + output logic oct_termin +); + localparam OCT_USER_OCT = "A_OCT_USER_OCT_OFF"; + + generate if (PHY_CALIBRATED_OCT == 1) begin + tennm_termination term_inst ( + .req_recal (1'b0), + .ack_recal (/*open*/), + .rzqin (oct_rzqin), + .serdataout(oct_termin) + ); + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm2RWhySuBXlG9AbE3HbTHwOJAj6ZCPGmwbYNUTcab+qWf8xi+J0WWjcXplRVhwNUN9uVKKovhRPcZFCZT0p4VJ+i7pZKiELwJm6gNtgjQYnKp27fN+/E3cPfzN++cxiL69ksN/50jhgNKTiyEWUDrgPUhyWHpocRzWJadcswBIgkDTLdfcoV5gprIoxRa7wjqc8juq1fzbDR+m63skC30xpYUENbeo1YO5W6FEh+vkiVOxEWEbS3LNxoGRAVYxzZyhnNH3tO+hgyIUBoERkTYUWIiMO2ZAibAveq0BO+aABmKflXAy4sWPAEya6W7BgtTc9zc5iHEndNqMzjdkB2U4ocnC4SHcaDorMptul7FS2h50DEnltLdli0p0Jz81ELdFLVt6J4faxiRwwIZe9o9c6ocykEqGeDESxpygDZ+UBwbwwa+lPRjesXc3SKg1Ev6udMGQfRQoRn35Hb+URaxUr0OWnWV/3wvpSJ2BRdTnBQ1PAkWbZKx82NSUg+mM+zwXNGXP0PZFEAykXbaDqKMK1xFjv5lLT0CCSWf8OwV6pSvIMBPMFGA+jIuYsYwBTNT+NR/+wbnZzVFecIcYYHoGqvwoAUemL0XvbhHH/zFo5+lSOBlbtG9AWnxPnS9mC1SM8QmAmVgBJoSEkuep9xwdgybpDJKNjYQHopTV8Zqh28fP7o5rTS7iBpE9SCaSeozSEtvq6laSHsWSIdyl05C5M4LcLPMAluCiVziuVK4ODvzm8ddEHqX4zl+TKPjzxptuCApz1L1cIWMFxnxEJEb0i" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_phylite_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_phylite_if.sv new file mode 100644 index 0000000000..a763d06199 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_phylite_if.sv @@ -0,0 +1,221 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the data interfaces through which +// soft logic interacts with the Avalon MM port of the HMC +// +/////////////////////////////////////////////////////////////////////////////// + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _core2l_data(_port_i, _phase_i) core2l_data\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)]\ + [(`_get_pin(WD_PINLOC, _port_i) * 8) + _phase_i] + +`define _core2l_oe(_port_i, _phase_i) core2l_oe\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)]\ + [(`_get_pin(WD_PINLOC, _port_i) * 4) + _phase_i] + +`define _l2core_data(_port_i, _phase_i) l2core_data\ + [`_get_tile(RD_PINLOC, _port_i)]\ + [`_get_lane(RD_PINLOC, _port_i)]\ + [(`_get_pin(RD_PINLOC, _port_i) * 8) + _phase_i] + +`define _l2core_rdata_valid(_port_i) l2core_rdata_valid\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)] + +`define _unused_core2l_data(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +`define _unused_oe(_pin_i) core2l_oe\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 4) +: 4] + +module altera_emif_arch_fm_phylite_if #( + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter UFI_LATENCY = 2, + + // Pin indexes of data signals + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_N_PINLOC = 10'b0000000000, + + // Pin indexes of write data mask signals + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0, + + // Definition of port widths for "phylite" interface (auto-generated) + parameter PORT_CTRL_DATA_OUT_WIDTH = 1, + parameter PORT_CTRL_DATA_IN_WIDTH = 1, + parameter PORT_CTRL_DATA_OE_WIDTH = 1, + parameter PORT_CTRL_STROBE_OE_WIDTH = 1, + parameter PORT_CTRL_STROBE_WIDTH = 1, + parameter PORT_CTRL_RDATA_VALID_WIDTH = 1, + parameter PORT_CTRL_RDATA_ENABLE_WIDTH = 1 +) ( + input logic pll_locked, + input logic emif_usr_clk, + input logic emif_usr_clk_sec, + input logic ufi_phy_clk, + + // Signals between core and data lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + input logic [3:0] l2core_rdata_valid, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [1:0] core_clks_locked_cpa_pri, + + // PHYLite interface + input logic [PORT_CTRL_STROBE_WIDTH-1:0] phylite_strobe, + input logic [PORT_CTRL_DATA_OE_WIDTH-1:0] phylite_data_oe, + input logic [PORT_CTRL_STROBE_OE_WIDTH-1:0] phylite_strobe_oe, + input logic [PORT_CTRL_DATA_OUT_WIDTH-1:0] phylite_data_from_core, + output logic [PORT_CTRL_DATA_IN_WIDTH-1:0] phylite_data_to_core, + output logic [PORT_CTRL_RDATA_VALID_WIDTH-1:0] phylite_rdata_valid, + input logic [PORT_CTRL_RDATA_ENABLE_WIDTH-1:0] phylite_rdata_en, + output logic phylite_interface_locked +); + timeunit 1ns; + timeprecision 1ps; + + localparam RD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_Q_PINLOC); + localparam WD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_D_PINLOC); + + localparam NUM_RD_PINS = `_get_pin_count(RD_PINLOC); + localparam NUM_WD_PINS = `_get_pin_count(WD_PINLOC); + localparam NUM_DQS_PINS = `_get_pin_count(PORT_MEM_DQS_PINLOC); + localparam NUM_DQS_N_PINS = `_get_pin_count(PORT_MEM_DQS_N_PINLOC); + + localparam NUM_OF_RD_PHASES = PORT_CTRL_DATA_OUT_WIDTH / NUM_RD_PINS; + localparam NUM_OF_WD_PHASES = PORT_CTRL_DATA_IN_WIDTH / NUM_WD_PINS; + localparam NUM_OF_OE_PHASES = NUM_OF_WD_PHASES / 2; + + + logic [NUM_WD_PINS-1:0][NUM_OF_OE_PHASES-1:0] ufi_core2l_oe; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] ufi_core2l_rdata_en_full; + localparam UFI_MODE = (UFI_LATENCY == 2) ? "pin_ufi_use_delay_fifo_out_reg" : + (UFI_LATENCY == 1) ? "pin_ufi_use_in_direct_out_reg" : "pin_ufi_use_in_direct_out_direct"; + localparam P2C_UFI_MODE = (UFI_LATENCY == 2) ? "pin_ufi_use_fast_fifo_out_reg" : + (UFI_LATENCY == 1) ? "pin_ufi_use_in_direct_out_reg" : "pin_ufi_use_in_direct_out_direct"; + generate + genvar port_i, data_i, oe_i, phase_i, pin_i; + genvar tile_i, lane_i, sig_i; + + + // phylite_interface locked signal + assign phylite_interface_locked= pll_locked ; + + // phylite_data_from_core to lanes' write data bus + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) begin : wd_port + + for (data_i = 0; data_i < 8; ++data_i) + begin : data_phase + if (data_i < NUM_OF_WD_PHASES) begin + assign `_core2l_data(port_i, data_i) = phylite_data_from_core[data_i * NUM_WD_PINS + port_i]; + end else begin + assign `_core2l_data(port_i, data_i) = 1'b0; + end + end + + for (oe_i = 0; oe_i < 4; ++oe_i) + begin : oe_phase + if (oe_i < NUM_OF_OE_PHASES) begin + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 225"} *) + tennm_ufi # ( + .mode (UFI_MODE), + .datapath("c2p")) ufi_inst ( + .srcclk (emif_usr_clk), + .destclk(ufi_phy_clk), + .d (phylite_data_oe[oe_i]), + .dout (ufi_core2l_oe[port_i][oe_i]) + ); + assign `_core2l_oe(port_i, oe_i) = ufi_core2l_oe[port_i][oe_i]; + end else begin + assign `_core2l_oe(port_i, oe_i) = 1'b0; + end + end + end + + // Map lanes' read data bus to phylite_data_to_core + for (port_i = 0; port_i < NUM_RD_PINS; ++port_i) + begin : rd_port + for (phase_i = 0; phase_i < NUM_OF_RD_PHASES; ++phase_i) + begin : phase + assign phylite_data_to_core[phase_i * NUM_RD_PINS + port_i] = `_l2core_data(port_i, phase_i); + end + end + + // Map lanes' read_valid to phylite_rdata_valid + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 225"} *) + tennm_ufi # ( + .mode (P2C_UFI_MODE), + .datapath("p2c")) rdata_valid_ufi_inst [PORT_CTRL_RDATA_VALID_WIDTH - 1:0] ( + .srcclk (ufi_phy_clk), + .destclk(emif_usr_clk), + .d (l2core_rdata_valid[PORT_CTRL_RDATA_VALID_WIDTH - 1:0]), + .dout (phylite_rdata_valid[PORT_CTRL_RDATA_VALID_WIDTH - 1:0]) + ); + + // Map lanes' rdata_en + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) begin : tile_loop + for (lane_i = 0; lane_i < LANES_PER_TILE; ++lane_i) begin : lane_loop + for (sig_i = 0; sig_i < 4; ++sig_i) begin : sig_loop + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 225"} *) + tennm_ufi # ( + .mode (UFI_MODE), + .datapath("c2p")) ufi_inst ( + .srcclk (emif_usr_clk), + .destclk(ufi_phy_clk), + .d (phylite_rdata_en[sig_i]), + .dout (ufi_core2l_rdata_en_full[tile_i][lane_i][sig_i]) + ); + end + assign core2l_rdata_en_full[tile_i][lane_i] = {{(4 - PORT_CTRL_RDATA_ENABLE_WIDTH){1'b0}}, ufi_core2l_rdata_en_full[tile_i][lane_i]}; + end + end + + // Tie off core2l_data for unused connections + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) begin + assign `_unused_core2l_data(pin_i) = '0; + end + end + + endgenerate +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm17yDrEN5tN07/Ds5pM+c3mBk5k3/Lfm7OY8/PIK6tH8hCR1xx1LkZA5p5wr8GzWkhPjRqvFihOZsLCY2SSYu6dfDGX+NXNCvLPPzpk+UL/uyf0ZIhnc3u+v8Crd6t6w3bZWD7Lrt6E3meMlk8hPaaVS3NmzUOeKSnl8WhrTC0fFZ5L2rIXo3+VJSGckDSSuP+DHLQPfw9wz9LInvjy2bc4sjPMW3fo5/0Z1AKvV8SFi6hQgrXoxgyoq3EswUDaBqT8M9dcYzMPzpigsnGjayLg1R/L/ICLWoeLBl85aSP2o9LIx4iaZj0yXP4OJNgI05WgCi8jJ4JADLsD9pei8sVjuiRI8TSXomklraO35J0ZsPqq2YrBgWwTv2hfcGB4Y3GkjteBkw3hdBzvr8DPkZCF/aA1Rm/3Hgs4NWD2dmNOzCn+A+31PVMiIV2pQw3ohHwPzNSEmKlsTba02DpNPkJYrg46ysmllSTBLycV6RQjPfMQkQ3e68wieu4S6dmG031mZBy1ksFLu4nZzJ7NOglMtWtXOUHsurL1Nc/qqVnaTrBUQ1PIbpIT/ND7jI2sdIPEZT3Xgq0RC1EX66AMluedfLwa2kVXV3/TnrRRXbVAEhp3z5nts2RzwVCAPNtFctAenf5tN6QnNbfu3+pFz9LvIy6vowx2Q64tbv5qIm0aHzDAh5BZBfhQ3aI2ImqlG8eovH/ByB4xqjmcAgMPIScVBaZUCjr4MEdYoYH9c/MR9Sd1dmjpSo6RrTiki0GF709rkn+6aoKYRYRbenZkvit+" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll.sv new file mode 100644 index 0000000000..dab7ff4436 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll.sv @@ -0,0 +1,474 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +// EMIF IOPLL instantiation for 20nm families +// +// The following table describes the usage of IOPLL by EMIF. +// +// PLL Counter Fanouts Usage +// ===================================================================================== +// VCO Outputs vcoph[7:0] -> phy_clk_phs[7:0] FR clocks, 8 phases (45-deg apart) +// vcoph[0] -> DLL FR clock to DLL +// C-counter 0 lvds_clk[0] -> phy_clk[1] Secondary PHY clock tree (C2P/P2C rate) +// C-counter 1 loaden[0] -> phy_clk[0] Primary PHY clock tree (PHY/HMC rate) +// C-counter 2 phy_clk[2] Feedback PHY clock tree (slowest phy clock in system) +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////////// + +module altera_emif_arch_fm_pll #( + parameter PORT_DFT_ND_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH = 1, + parameter PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH = 1, + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_OUT_EN_8 = "", + + parameter PLL_REF_CLK_FREQ_MHZ_STR = "", + parameter PLL_VCO_FREQ_MHZ_STR = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_0 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_1 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_2 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_3 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_4 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_5 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_6 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_7 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_8 = "", + parameter IS_HPS = 0 + +) ( + input logic pll_ref_clk_int, + output logic pll_locked, + output logic pll_dll_clk, + output logic [7:0] phy_clk_phs, + output logic [1:0] phy_clk, + output logic phy_fb_clk_to_tile, + input logic phy_fb_clk_to_pll, + output logic [8:0] pll_c_counters, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_ND_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done, + input logic [PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH-1:0] pll_core_refclk +); + timeunit 1ns; + timeprecision 1ps; + + logic [7:0] pll_vcoph; + logic [1:0] pll_loaden; + logic [1:0] pll_lvds_clk; + + assign phy_clk_phs = pll_vcoph; + + assign phy_clk[0] = pll_loaden[0]; // C-cnt 1 drives phy_clk 0 through a delay chain (swapping is intentional) + assign phy_clk[1] = pll_lvds_clk[0]; // C-cnt 0 drives phy_clk 1 through a delay chain (swapping is intentional) + +`ifdef ALTERA_EMIF_ENABLE_ISSP + generate + if (IS_HPS == 0) begin : non_hps + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PLLL"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) pll_lock_issp ( + .probe (pll_locked) + ); + end + endgenerate +`endif + + tennm_iopll # ( + + //////////////////////////////////// + // VCO and Ref clock + // fVCO = fRefClk * M * CCnt2 / N + //////////////////////////////////// + .prot_mode ("emif_mode"), + .refclk_time (PLL_REF_CLK_FREQ_PS_STR), + .vco (PLL_VCO_FREQ_PS_STR), + + // : N_CNT_BYPASS_EN is always on which means pfd_freq == ref_clk_freq / 1 + .pfd (PLL_REF_CLK_FREQ_PS_STR), + + //////////////////////////////////// + // M Counter + //////////////////////////////////// + .m_counter_bypass_en (PLL_M_CNT_BYPASS_EN), + .m_counter_even_duty_en (PLL_M_CNT_EVEN_DUTY_EN), + .m_counter_high (PLL_M_CNT_HIGH), + .m_counter_low (PLL_M_CNT_LOW), + .m_counter_coarse_dly ("0 ps"), + .m_counter_fine_dly ("0 ps"), + + //////////////////////////////////// + // N Counter (bypassed) + //////////////////////////////////// + .n_counter_bypass_en (PLL_N_CNT_BYPASS_EN), + .n_counter_odd_div_duty_en (PLL_N_CNT_EVEN_DUTY_EN), + .n_counter_high (PLL_N_CNT_HIGH), + .n_counter_low (PLL_N_CNT_LOW), + .n_counter_coarse_dly ("0 ps"), + .n_counter_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 0 (phy_clk[1]) + //////////////////////////////////// + .c0_out_en (PLL_C_CNT_OUT_EN_0), // C-counter driving phy_clk[1] + .outclk0 (PLL_C_CNT_FREQ_PS_STR_0), + .phase_shift_0 (PLL_C_CNT_PHASE_PS_STR_0), + .duty_cycle_0 (PLL_C_CNT_DUTY_CYCLE_0), + .c0_bypass_en (PLL_C_CNT_BYPASS_EN_0), + .c0_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_0), + .c0_high (PLL_C_CNT_HIGH_0), + .c0_low (PLL_C_CNT_LOW_0), + .c0_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_0), + .c0_prst (PLL_C_CNT_PRST_0), + .c0_coarse_dly ("0 ps"), + .c0_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 1 (phy_clk[0]) + //////////////////////////////////// + .c1_out_en (PLL_C_CNT_OUT_EN_1), // C-counter driving phy_clk[0] + .outclk1 (PLL_C_CNT_FREQ_PS_STR_1), + .phase_shift_1 (PLL_C_CNT_PHASE_PS_STR_1), + .duty_cycle_1 (PLL_C_CNT_DUTY_CYCLE_1), + .c1_bypass_en (PLL_C_CNT_BYPASS_EN_1), + .c1_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_1), + .c1_high (PLL_C_CNT_HIGH_1), + .c1_low (PLL_C_CNT_LOW_1), + .c1_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_1), + .c1_prst (PLL_C_CNT_PRST_1), + .c1_coarse_dly ("0 ps"), + .c1_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 2 (phy_clk[2]) + //////////////////////////////////// + .c2_out_en (PLL_C_CNT_OUT_EN_2), // C-counter driving phy_clk[2] + .outclk2 (PLL_C_CNT_FREQ_PS_STR_2), + .phase_shift_2 (PLL_C_CNT_PHASE_PS_STR_2), + .duty_cycle_2 (PLL_C_CNT_DUTY_CYCLE_2), + .c2_bypass_en (PLL_C_CNT_BYPASS_EN_2), + .c2_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_2), + .c2_high (PLL_C_CNT_HIGH_2), + .c2_low (PLL_C_CNT_LOW_2), + .c2_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_2), + .c2_prst (PLL_C_CNT_PRST_2), + .c2_coarse_dly ("0 ps"), + .c2_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 3 (unused) + //////////////////////////////////// + .c3_out_en (PLL_C_CNT_OUT_EN_3), // Not used by EMIF + .outclk3 (PLL_C_CNT_FREQ_PS_STR_3), + .phase_shift_3 (PLL_C_CNT_PHASE_PS_STR_3), + .duty_cycle_3 (PLL_C_CNT_DUTY_CYCLE_3), + .c3_bypass_en (PLL_C_CNT_BYPASS_EN_3), + .c3_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_3), + .c3_high (PLL_C_CNT_HIGH_3), + .c3_low (PLL_C_CNT_LOW_3), + .c3_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_3), + .c3_prst (PLL_C_CNT_PRST_3), + .c3_coarse_dly ("0 ps"), + .c3_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 4 (unused) + //////////////////////////////////// + .c4_out_en (PLL_C_CNT_OUT_EN_4), // Not used by EMIF + .outclk4 (PLL_C_CNT_FREQ_PS_STR_4), + .phase_shift_4 (PLL_C_CNT_PHASE_PS_STR_4), + .duty_cycle_4 (PLL_C_CNT_DUTY_CYCLE_4), + .c4_bypass_en (PLL_C_CNT_BYPASS_EN_4), + .c4_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_4), + .c4_high (PLL_C_CNT_HIGH_4), + .c4_low (PLL_C_CNT_LOW_4), + .c4_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_4), + .c4_prst (PLL_C_CNT_PRST_4), + .c4_coarse_dly ("0 ps"), + .c4_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 5 (unused) + //////////////////////////////////// + .c5_out_en (PLL_C_CNT_OUT_EN_5), // Not used by EMIF + .outclk5 (PLL_C_CNT_FREQ_PS_STR_5), + .phase_shift_5 (PLL_C_CNT_PHASE_PS_STR_5), // Don't care (unused c-counter) + .duty_cycle_5 (PLL_C_CNT_DUTY_CYCLE_5), // Don't care (unused c-counter) + .c5_bypass_en (PLL_C_CNT_BYPASS_EN_5), // Don't care (unused c-counter) + .c5_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_5), // Don't care (unused c-counter) + .c5_high (PLL_C_CNT_HIGH_5), // Don't care (unused c-counter) + .c5_low (PLL_C_CNT_LOW_5), // Don't care (unused c-counter) + .c5_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_5), // Don't care (unused c-counter) + .c5_prst (PLL_C_CNT_PRST_5), // Don't care (unused c-counter) + .c5_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .c5_fine_dly ("0 ps"), // Don't care (unused c-counter) + + //////////////////////////////////// + // C Counter 6 (unused) + //////////////////////////////////// + .c6_out_en (PLL_C_CNT_OUT_EN_6), // Not used by EMIF + .outclk6 (PLL_C_CNT_FREQ_PS_STR_6), + .phase_shift_6 (PLL_C_CNT_PHASE_PS_STR_6), // Don't care (unused c-counter) + .duty_cycle_6 (PLL_C_CNT_DUTY_CYCLE_6), // Don't care (unused c-counter) + .c6_bypass_en (PLL_C_CNT_BYPASS_EN_6), // Don't care (unused c-counter) + .c6_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_6), // Don't care (unused c-counter) + .c6_high (PLL_C_CNT_HIGH_6), // Don't care (unused c-counter) + .c6_low (PLL_C_CNT_LOW_6), // Don't care (unused c-counter) + .c6_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_6), // Don't care (unused c-counter) + .c6_prst (PLL_C_CNT_PRST_6), // Don't care (unused c-counter) + .c6_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .c6_fine_dly ("0 ps"), // Don't care (unused c-counter) + + //////////////////////////////////// + // C Counter 7 (unused) + //////////////////////////////////// + .c7_out_en (PLL_C_CNT_OUT_EN_7), // Not used by EMIF + .outclk7 (PLL_C_CNT_FREQ_PS_STR_7), + .phase_shift_7 (PLL_C_CNT_PHASE_PS_STR_7), // Don't care (unused c-counter) + .duty_cycle_7 (PLL_C_CNT_DUTY_CYCLE_7), // Don't care (unused c-counter) + .c7_bypass_en (PLL_C_CNT_BYPASS_EN_7), // Don't care (unused c-counter) + .c7_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_7), // Don't care (unused c-counter) + .c7_high (PLL_C_CNT_HIGH_7), // Don't care (unused c-counter) + .c7_low (PLL_C_CNT_LOW_7), // Don't care (unused c-counter) + .c7_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_7), // Don't care (unused c-counter) + .c7_prst (PLL_C_CNT_PRST_7), // Don't care (unused c-counter) + .c7_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .c7_fine_dly ("0 ps"), // Don't care (unused c-counter) + + //////////////////////////////////// + // C Counter 8 (unused) + //////////////////////////////////// + .c8_out_en (PLL_C_CNT_OUT_EN_8), // Not used by EMIF + .outclk8 (PLL_C_CNT_FREQ_PS_STR_8), + .phase_shift_8 (PLL_C_CNT_PHASE_PS_STR_8), // Don't care (unused c-counter) + .duty_cycle_8 (PLL_C_CNT_DUTY_CYCLE_8), // Don't care (unused c-counter) + .c8_bypass_en (PLL_C_CNT_BYPASS_EN_8), // Don't care (unused c-counter) + .c8_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_8), // Don't care (unused c-counter) + .c8_high (PLL_C_CNT_HIGH_8), // Don't care (unused c-counter) + .c8_low (PLL_C_CNT_LOW_8), // Don't care (unused c-counter) + .c8_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_8), // Don't care (unused c-counter) + .c8_prst (PLL_C_CNT_PRST_8), // Don't care (unused c-counter) + .c8_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .c8_fine_dly ("0 ps"), // Don't care (unused c-counter) + + //////////////////////////////////// + // Misc Delay Chains + //////////////////////////////////// + .ref_buf_dly ("0 ps"), + .cmp_buf_dly ("0 ps"), + + .lvdsclk_0_coarse_dly ("0 ps"), // Fine delay chain to skew phyclk[0] + .loaden_0_coarse_dly ("0 ps"), // Fine delay chain to skew phyclk[1] + .lvdsclk_1_coarse_dly ("0 ps"), // Fine delay chain to skew phyclk[2] + .loaden_1_coarse_dly ("0 ps"), // Fine delay chain to skew phyclk[3] + + .lvdsclk_0_fine_dly ("0 ps"), // Fine delay chain to skew phyclk[0] + .loaden_0_fine_dly ("0 ps"), // Fine delay chain to skew phyclk[1] + .lvdsclk_1_fine_dly ("0 ps"), // Fine delay chain to skew phyclk[2] + .loaden_1_fine_dly ("0 ps"), // Fine delay chain to skew phyclk[3] + + //////////////////////////////////// + // Misc PLL Modes and Features + //////////////////////////////////// + .feedback ("direct"), // EMIF doesn't need PLL compensation. Alignment of core clocks and PHY clocks is handled by CPA + + .extclk_0_enable ("false"), // EMIF PLL does not need to drive output clock pin + .extclk_1_enable ("false"), // EMIF PLL does not need to drive output clock pin + + .clkin_0_src ("refclkin"), // + .clkin_1_src ("refclkin"), // + .refclk_src_mux ("clk_0"), // + .auto_clk_sw_en ("false"), // EMIF PLL does not use the automatic clock switch-over feature + .manu_clk_sw_en ("false"), // EMIF PLL does not use the automatic clock switch-over feature + .merging_permitted ("true"), + + .bw_mode ("hi_bw"), // Bandwidth select + .lock_mode ("low_lock_time"), //__ACDS_USER_COMMNET__ lock_fltr_cfg 100 => "low_lock_time" + + //////////////////////////////////// + // To enable PLL calibration + //////////////////////////////////// + .uc_channel_base_addr(16'h0) + + ) pll_inst ( + + .refclk (pll_core_refclk), + .rst_n (1'b1), + .loaden (pll_loaden), + .lvds_clk (pll_lvds_clk), + .vcoph (pll_vcoph), + .fblvds_in (), + .fblvds_out (phy_fb_clk_to_tile), + .dll_output (pll_dll_clk), + .lock (pll_locked), + .outclk (pll_c_counters), + .fbclk_in (1'b0), + .fbclk_out (), + .zdb_in (1'b0), + .phase_done (pll_phase_done), + .pll_cascade_in (pll_ref_clk_int), + .pll_cascade_out (), + .extclk_output (), + .core_refclk (1'b0), + .dps_rst_n (1'b1), + .mdio_dis (1'b0), + .pfden (1'b1), + .phase_en (pll_phase_en), + .pma_csr_test_dis (1'b1), + .up_dn (pll_up_dn), + .extswitch (1'b0), + .clken (2'b00), // Don't care (extclk) + .cnt_sel (pll_cnt_sel), + .num_phase_shifts (pll_num_phase_shifts), + .clk0_bad (), + .clk1_bad (), + .clksel (), + .csr_clk (1'b1), + .csr_en (1'b1), + .csr_in (1'b1), + .csr_out (), + .dprio_clk (1'b0), + .dprio_rst_n (1'b1), + .dprio_address (9'b000000000), + .scan_mode_n (1'b1), + .scan_shift_n (1'b1), + .write (1'b0), + .read (1'b0), + .readdata (), + .writedata (8'b00000000), + .extclk_dft (), + .block_select (), + .lf_reset (), + .pipeline_global_en_n (), + .pll_pd (), + .vcop_en (), + .user_mode (1'b1) + ); + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm03/adeGfDnFvYrNFWP5b8KM0itmRZy+oB2JIV75ZMQZ1Tl7D0v4ikMe4xrpBpHUqXrV6jfjk0S7/nPE5IHNjYoNf5avFRpXLhXEFEv7vQrKo+Mg8KSKPQpX69tC7xEBelATHHx1TnRmQ7hA4jq+ThXSOxg+zToL8I3CnGhM2YYNGzaMUCxRuCSuPYVnP8mQlOdwf6mpNtx5deyV0S3rgLyGKrwhT+BRQ/pSvTyAI8dRjGQtzTTS0reTJp1Rt12sA/dAgr4SQA6V2iVzPqSg7JbGr01eXiFQIxI7nRp1wpeJVPdodOTFPj/3qBh/Un6qYhIlJcEyrd+fWcsEHoMK0zgSk5DHZ3tMEdtISaBSi3KGNe9EiVnV9KXHKQzL9aPv5Xego52m5YfN4AEuhrMNf2Th8GG1d7V8yEjpaclbedNfQlyIX87xgH7xhj9GBflSSzleMgrdzwa6Ogxs1Y8oA4O+lv6r/K1QxoCVTKS2PQ2GTmm0UXLGrDiTRNzv8CtcMahM+awrFJLuVfySUj5KXpwapBlvYJvtBqeZPWfPG7kBxfCd2Uv6l8b9Po6GnlQR9fheSvE4gmTPgCeh0Y7PC7hDzF/2bHQkBKGVvnwHgtdDBUtwQZPr6YzHpiy9IWyDakBxfABq9NhwMvwGVgikZxV5u6hIto8+qdIh/orxu1MA/fIcshm67Bae9cOn6VZE1dloaYHyBrYM9maLMMimc3tdPyWxt8KHSg/IYwaayAznD5bJQNAdVJrhPTyJTOSNUJqNjfd26wXn/XtyTu5xFxv" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_extra_clks.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_extra_clks.sv new file mode 100644 index 0000000000..8bccbbdeac --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_extra_clks.sv @@ -0,0 +1,79 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Expose extra core clocks from IOPLL +// +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_fm_pll_extra_clks #( + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter DIAG_SIM_REGTEST_MODE = 0 +) ( + input logic pll_locked, + input logic [8:0] pll_c_counters, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + output logic pll_extra_clk_diag_ok +); + timeunit 1ns; + timeprecision 1ps; + + logic [3:0] pll_extra_clks; + + // Extra core clocks to user logic. + // These clocks are unrelated to EMIF core clock domains. The feature is intended as a + // way to reuse EMIF PLL to generate core clocks for designs in which physical PLLs are scarce. + assign pll_extra_clks = pll_c_counters[8:5]; + assign pll_extra_clk_0 = pll_extra_clks[0]; + assign pll_extra_clk_1 = pll_extra_clks[1]; + assign pll_extra_clk_2 = pll_extra_clks[2]; + assign pll_extra_clk_3 = pll_extra_clks[3]; + + // In internal test mode, generate additional counters clocked by the extra clocks + generate + genvar i; + + if (DIAG_SIM_REGTEST_MODE && PLL_NUM_OF_EXTRA_CLKS > 0) begin: test_mode + logic [PLL_NUM_OF_EXTRA_CLKS-1:0] pll_extra_clk_diag_done; + + for (i = 0; i < PLL_NUM_OF_EXTRA_CLKS; ++i) + begin : extra_clk + logic [9:0] counter; + + always_ff @(posedge pll_extra_clks[i] or negedge pll_locked) begin + if (~pll_locked) begin + counter <= '0; + pll_extra_clk_diag_done[i] <= 1'b0; + end else begin + if (~counter[9]) begin + counter <= counter + 1'b1; + end + pll_extra_clk_diag_done[i] <= counter[9]; + end + end + end + + assign pll_extra_clk_diag_ok = &pll_extra_clk_diag_done; + + end else begin : normal_mode + assign pll_extra_clk_diag_ok = 1'b1; + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm3HRP669h4e40UGyQSmTgYw2cfdljNSKWm+e85+uUmrYb7ks40d95f32V/kNHxQ60Z2sgrLbN82EuwqRNCnBLceiw2KyJp1V6lFQfCeK/+4j5xx0J+YaCdrqWJaoHweHsGm1MzuNdJ29PzLVC1Daiwk0FO/SxEe43FbBCtor/DUhyOHcPWY5GviHXJTLOT/VvziOsd1mVPMCv2shs73BPOB2W7hlv5vI6tpIbpnRMaoAFmDABM9d3oZLnAzha5IqtSsZ+lOKd0z3kX4PbxyoIRj0TuF9/KOAP+ZO1/syjlZqM+haNQcO3RhdIeb7khdaeO0vau2e5t91/FAsb6JZBVnNaml890Rcqia/Maoz2YKSqPxjuyi5JEyc0bgMJEHf4Ao5UROTOu7apgZOTV7S1oqaveZuMv15cB8dv03AJlgE3J+okELao3UnDK7Eo3n5h7xGJ7HxJ2CpHRDKxyzTCugfXaZ7K+yJcv8bM4+HYAz3Ed8Kgc6IB4U0QDoBJKTrDsDkY9SJA1l9URiPs7v8ncr52BH1BMfztBPbLXsFXcwcjrxw4HkvPRkanirjX5XD4t9+FWAK/eE/VGbrxaSl4kx3XJ31VWosJDrAv5d8U2KCqhP4iHC2VA6jvDnT7tX8cKt/P6IJJ2DacCM/erNjsXsI5Vqle9G18OP9EEa/BSQ8DRfET6j6UMCn5XnwQ1S4JvtI6RZsw2lTMWlY1p9IwrEzX6tlPCgnunBFgagOC+5f17EInvqWYTEslTZhGwBtz1fUvNW1DxOsHTJVYIoUgwE" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_fast_sim.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_fast_sim.sv new file mode 100644 index 0000000000..4a776e2ec2 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_fast_sim.sv @@ -0,0 +1,118 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +// EMIF IOPLL instantiation for 20nm families +// +// The following table describes the usage of IOPLL by EMIF. +// +// PLL Counter Fanouts Usage +// ===================================================================================== +// VCO Outputs vcoph[7:0] -> phy_clk_phs[7:0] FR clocks, 8 phases (45-deg apart) +// vcoph[0] -> DLL FR clock to DLL +// C-counter 0 lvds_clk[0] -> phy_clk[1] Secondary PHY clock tree (C2P/P2C rate) +// C-counter 1 loaden[0] -> phy_clk[0] Primary PHY clock tree (PHY/HMC rate) +// C-counter 2 phy_clk[2] Feedback PHY clock tree (slowest phy clock in system) +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_fm_pll_fast_sim #( + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PORT_DFT_ND_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH = 1, + parameter PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH = 1 + +) ( + input logic pll_ref_clk_int, + output logic pll_locked, + output logic pll_dll_clk, + output logic [7:0] phy_clk_phs, + output logic [1:0] phy_clk, + output logic phy_fb_clk_to_tile, + input logic phy_fb_clk_to_pll, + output logic [8:0] pll_c_counters, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_ND_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done, + input logic [PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH-1:0] pll_core_refclk +); + timeunit 1ps; + timeprecision 1ps; + + localparam VCO_PHASES = 8; + + reg vco_out, phyclk0_out, phyclk1_out, fbclk_out; + reg [4:0] pll_lock_count; + // synthesis translate_off + initial begin + vco_out <= 1'b1; + forever #(PLL_SIM_VCO_FREQ_PS/2) vco_out <= ~vco_out; + end + initial begin + phyclk0_out <= 1'b1; + #(PLL_SIM_VCO_FREQ_PS*PLL_SIM_PHY_CLK_VCO_PHASE_PS/VCO_PHASES); + forever #(PLL_SIM_PHYCLK_0_FREQ_PS/2) phyclk0_out <= ~phyclk0_out; + end + initial begin + phyclk1_out <= 1'b1; + #(PLL_SIM_VCO_FREQ_PS*PLL_SIM_PHY_CLK_VCO_PHASE_PS/VCO_PHASES); + forever #(PLL_SIM_PHYCLK_1_FREQ_PS/2) phyclk1_out <= ~phyclk1_out; + end + initial begin + fbclk_out <= 1'b1; + #(PLL_SIM_VCO_FREQ_PS*PLL_SIM_PHY_CLK_VCO_PHASE_PS/VCO_PHASES); + forever #(PLL_SIM_PHYCLK_FB_FREQ_PS/2) fbclk_out <= ~fbclk_out; + end + + initial begin + pll_lock_count <= 5'b0; + end + // synthesis translate_on + + always @ (posedge vco_out) begin + if (pll_lock_count != 5'b11111) begin + pll_lock_count <= pll_lock_count + 1; + end + end + + assign pll_locked = (pll_lock_count == 5'b11111); + assign pll_dll_clk = pll_locked & vco_out; + assign phy_clk_phs[0] = pll_locked & vco_out; + always @ (*) begin + phy_clk_phs[1] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[0]; + phy_clk_phs[2] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[1]; + phy_clk_phs[3] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[2]; + phy_clk_phs[4] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[3]; + phy_clk_phs[5] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[4]; + phy_clk_phs[6] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[5]; + phy_clk_phs[7] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[6]; + end + assign phy_clk = {pll_locked & phyclk1_out, pll_locked & phyclk0_out}; + assign phy_fb_clk_to_tile = pll_locked & fbclk_out; + assign pll_c_counters[0] = pll_locked & phyclk1_out; + assign pll_c_counters[1] = pll_locked & phyclk0_out; + assign pll_c_counters[2] = pll_locked & fbclk_out; + assign pll_c_counters[8:3] = 6'd0; + assign pll_phase_done = 1'b1; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm3BGXk9lUcm5RF8HkFXhW2IR5/x+h8T5PbKTqwuwhus1/PoXI0qiAFflw54MC3ilxDPX80k62rh2cYxlerC4ZmDfBW+AOOM6AeHpIuZZWUvyPWYWXWrivxWPneu9rYZ2WrnHdZaQJpueIIQKhFVanmu0CdggAbNdVWGkffyupL0hJ2ZXdoiMn7ro+63lDA0Y1cE0pkahmZa2BD94Ih3FeHJSDmTmUnprODmyptruZuWjNzca0WZ99JaABDaU1De7O00OrFojm2rNW9D8FMfoeiVrsoGXOQiq6nF+rCQCPXvCRVjRQL2WR7SwJuFTMfCkxYt/p3gamgN1pQi6e4v1BU5cVfe895AiYHwmu+of3gtCzhVtHwvvsbJcU+iHZID4Oy8skadjkfj5VfopXg+q4WThbsBpevH2svYAJtqw735zAaP3yr8xTqf+B5y4mkbJM+Va2uyMLbKNfYyT6WVIH37gp7W6IZOVRfO0d+EAX3viymgSnc04cUmChs22J67SKR3NB4goS/+wvbMA8AfbDrtFNucsatvj+D4PK0jydwxQSwduLOlv/WWy8tMh55u9zpYYqrP883sUN+sO2NsQTEYNfCqDU0gOFl7HYK8Gc1t9M/4kmKPKXbvurDkVKAAS/oZfXZ+PZ0GqQgsbRm02JxXAq+hWuHwbIOJuSphyNSs65rF3/8E5JROZ53Ezii4rvOlHVWeDdBnkPjJlHnhS1UVrNVW8bQfEhgp1rS9u1YAZ041Tnh+zHgS/Jf/+XKkklzfi+7HnyYffrIKaVhJ4NSt" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_regs.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_regs.sv new file mode 100644 index 0000000000..9340eac3dc --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_regs.sv @@ -0,0 +1,63 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module handles the creation of a conditional register stage. +// This module may be used to implement a synchronizer (with properly selected +// REGISTER value) +/////////////////////////////////////////////////////////////////////////////// + +// The following ensures that the register stage isn't synthesized into +// RAM-based shift-regs (especially if customer logic implements another follow-on +// pipeline stage). RAM-based shift-regs can degrade timing for C2P/P2C transfers. +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) + + module altera_emif_arch_fm_regs #( + parameter REGISTER = 0, + parameter WIDTH = 0 +) ( + input logic clk, + input logic reset_n, + input logic [WIDTH-1:0] data_in, + output logic [WIDTH-1:0] data_out +) /* synthesis dont_merge */; + timeunit 1ns; + timeprecision 1ps; + + generate + genvar stage; + + if (REGISTER == 0) begin : no_reg + assign data_out = data_in; + end else begin : regs + logic [WIDTH-1:0] sr_out [(REGISTER > 0 ? REGISTER-1 : 0):0]; + + assign data_out = sr_out[REGISTER-1]; + + for (stage = 0; stage < REGISTER; stage = stage + 1) + begin : stage_gen + always_ff @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + sr_out[stage] <= '0; + end else begin + sr_out[stage] <= (stage == 0) ? data_in : sr_out[stage-1]; + end + end + end + end + endgenerate +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm3tozkeL1uA0g6U2EUSXAyXVQSjpOKAZHctS0q08TSgBla5+tUOYiiDPSAb9bcqW8CStRlmK7HGvMwv9069DY1wUGZ0y07cixAGitu/K30eRibQpiV8iWJOIl7HtulD0SZbbsYF4CeOunjnp9tXrYEVMUG47w3LW0kccnee89uKQJPJn9ADtaqFPPGB7TwznwzJwUcoFZeLyAO94/WpewMNi2B30PWwBloh/zN9faAvH65NZU6lHEiMc+sGO2ngnIJvaoldVHvgyUDysucNk/o22crj3iWw6cRxRVauERE2To393Ivq2mpvI26hroo/pTqrE2AzpOI/4rVRmGQpoVEjmhraaJ1HuacA1lyOKf82oAhBKgVYwiX7MyfRYWiQn2sCtWSuZtgfSXXXDl5AVctMxRH0sA8UOjT3joWiY8F2YwG7xVC/BEjkNEeofaXqSBKcf0Fod6iNzCrVuYpG8J737B1PHgjVOR6Du6Pwl63RCgYc6QaJHH7R6DSd5IBJwPMpDZi9csIWAXHAxr6DIqDQFn00SEhKPqU3BWOZWjkztjQx5ik+m6hJGI7HUyMI5htPfFVfzwT6ZqEOn9FEU+i7gBSu4PYelN2HhfAPsn43lfngh6JnTjWrOXPqkckUU0uYQ09MRNQEq6b7DJHKuZdjCss0pc8acC4AWHdw46U2MXH38Xz2AVejtf8hRQSL32G4OsTq8uqVp+MDESDawj8M5b5tz+S7vTjdnXO/9TF3BajMmRKqcFi5uFJUy1ijWQUF2aVW9RM+mEbv4mLJXmdv" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_seq_if.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_seq_if.sv new file mode 100644 index 0000000000..70b49e98b3 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_seq_if.sv @@ -0,0 +1,248 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing control signals from/to the +// sequencer. +// +/////////////////////////////////////////////////////////////////////////////// + +module altera_emif_arch_fm_seq_if #( + parameter PHY_CONFIG_ENUM = "", + parameter USER_CLK_RATIO = 1, + parameter REGISTER_AFI_C2P = 0, + parameter REGISTER_AFI_P2C = 0, + parameter PHY_USERMODE_OCT = 0, + parameter PORT_AFI_RLAT_WIDTH = 1, + parameter PORT_AFI_WLAT_WIDTH = 1, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 1, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 1, + parameter PHY_PERIODIC_OCT_RECAL = 1, + parameter IS_HPS = 0 +) ( + input logic core2seq_reset_req, + output logic seq2core_reset_done, + input logic [1:0] core_clks_locked_cpa_pri, + + input logic afi_clk, + input logic afi_reset_n, + input logic emif_usr_clk, + input logic emif_usr_reset_n, + output logic afi_cal_success, + output logic afi_cal_fail, + output logic afi_cal_in_progress, + input logic afi_cal_req, + output logic [PORT_AFI_RLAT_WIDTH-1:0] afi_rlat, + output logic [PORT_AFI_WLAT_WIDTH-1:0] afi_wlat, + output logic afi_mps_ack, + output logic [PORT_AFI_SEQ_BUSY_WIDTH-1:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic [17:0] c2t_afi, + input logic [26:0] t2c_afi, + input logic [PORT_HPS_EMIF_H2E_GP_WIDTH-1:0] hps_to_emif_gp, + output logic [PORT_HPS_EMIF_E2H_GP_WIDTH-1:0] emif_to_hps_gp, + output logic seq2core_reset_n, + output logic ac_parity_err +); + timeunit 1ns; + timeprecision 1ps; + + logic clk; + logic reset_n; + + generate + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") begin : hmc + assign clk = emif_usr_clk; + assign reset_n = emif_usr_reset_n; + end else begin : non_hmc + assign clk = afi_clk; + assign reset_n = afi_reset_n; + end + endgenerate + + assign c2t_afi[4:0] = '0; + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (1) + ) core2seq_reset_req_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (core2seq_reset_req), + .data_out (c2t_afi[6]) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (1) + ) afi_cal_req_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (afi_cal_req), + .data_out (c2t_afi[8]) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (4) + ) afi_ctl_refresh_done_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in ({4{afi_ctl_refresh_done}}), + .data_out (c2t_afi[12:9]) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (4) + ) afi_ctl_long_idle_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in ({4{afi_ctl_long_idle}}), + .data_out (c2t_afi[16:13]) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_C2P), + .WIDTH (1) + ) afi_mps_reg_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (afi_mps_req), + .data_out (c2t_afi[17]) + ); + assign c2t_afi[7] = 1'b0; + assign c2t_afi[5] = 1'b0; + + + + logic [PORT_AFI_RLAT_WIDTH-1:0] pre_adjusted_afi_rlat; + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_P2C), + .WIDTH (6) + ) afi_rlat_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[5:0]), + .data_out (pre_adjusted_afi_rlat) + ); + + assign afi_rlat = pre_adjusted_afi_rlat + REGISTER_AFI_P2C[PORT_AFI_RLAT_WIDTH-2:0] + REGISTER_AFI_C2P[PORT_AFI_RLAT_WIDTH-2:0]; + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_P2C), + .WIDTH (6) + ) afi_wlat_regs ( + .clk (clk), + .reset_n (1'b1), + .data_in (t2c_afi[11:6]), + .data_out (afi_wlat) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_P2C), + .WIDTH (4) + ) afi_seq_busy_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[23:20]), + .data_out (afi_seq_busy) + ); + + altera_emif_arch_fm_regs # ( + .REGISTER (REGISTER_AFI_P2C), + .WIDTH (1) + ) afi_mps_ack_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[26]), + .data_out (afi_mps_ack) + ); + + localparam SYNC_LENGTH = 3; + + generate + if (IS_HPS == 0) begin : non_hps + altera_std_synchronizer_nocut # ( + .depth (SYNC_LENGTH), + .rst_value (0) + ) afi_cal_success_sync_inst ( + .clk (clk), + .reset_n (reset_n), + .din (t2c_afi[24]), + .dout (afi_cal_success) + ); + + altera_std_synchronizer_nocut # ( + .depth (SYNC_LENGTH), + .rst_value (0) + ) afi_cal_fail_sync_inst ( + .clk (clk), + .reset_n (reset_n), + .din (t2c_afi[25]), + .dout (afi_cal_fail) + ); + + altera_std_synchronizer_nocut # ( + .depth (SYNC_LENGTH), + .rst_value (0) + ) seq2core_reset_done_sync_inst ( + .clk (clk), + .reset_n (reset_n), + .din (t2c_afi[17]), + .dout (seq2core_reset_done) + ); + + altera_std_synchronizer_nocut # ( + .depth (SYNC_LENGTH), + .rst_value (0) + ) afi_cal_in_progress_sync_inst ( + .clk (clk), + .reset_n (reset_n), + .din (t2c_afi[16]), + .dout (afi_cal_in_progress) + ); + + // Connects the parity error flag (t2c_afi[19]) to a register (ac_parity_err) + altera_std_synchronizer_nocut # ( + .depth (SYNC_LENGTH), + .rst_value (0) + ) seq2core_ac_parity_sync_inst ( + .clk (clk), + .reset_n (reset_n), + .din (t2c_afi[19]), + .dout (ac_parity_err) + ); + + assign seq2core_reset_n = t2c_afi[18]; + + end else begin : hps + assign afi_cal_success = 1'b0; + assign afi_cal_fail = 1'b0; + assign seq2core_reset_done= 1'b0; + assign afi_cal_in_progress= 1'b0; + assign ac_parity_err = 1'b0; + + assign seq2core_reset_n = 1'b1; + end + endgenerate + + assign emif_to_hps_gp = '0; +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm1xPg+0kVofVsQ0ajf7CL9sQuuXrLkzrYinBapdQUeX+zasYblbZBzzxN8Prs0KgkQiF40wIEqlZ5bt1k0xFkmNDG3GVlPBQao9X6CIeu9/DGSWi2Sa/sBOAlxDQhqLA6FJZlLE88e43fWMj21jVN0xAqFbw4AKkT/SJCqvotMe5HvaF+Y/5CahLNlZih/nR1VL3Ppx2WuBUUTQjJYB0YklEPqmJ5U3ihFAKsTOwBqMA07fi4/fDhrycEfjUg3quKIGhN0s71iSSrclarapOZJHtK5r42O73ta6MNvCGNc3JrEL05sS3NnIENyt6UDVoeIoGy3S7+BpPqQ6bNmbuKdpdAz98yrC4Z8nOxqOzZ/npf1XyWogDioIcDJxj/Zx6bnXm7ChVvkH0rHvzrY09XPiDSA8ni9mwo4JCmBEF5xjD7nb7CsrHKo43sqPGbXLOkQAQz1ZGpoF89UbROZLvYz3Cvc1+aEXJTY/zeIsPCyGPRF2x95vsqeHTF+efAMrs97ha276vWnjHCsYwm8hi9Wg2tBW/P0QJY0m1rhKhIdC5o/hU6+dC6aA6i9iceCiJusPMAEBtQzAimiWCJ/3NsRZBxTA3oSyBuUL1gllSJ7MyGfZTn9FvsxKuwEODOIrTOB/hmKzLmSZCgwpnixrhtQqIuBo0FVbhFVHc/CjU6kXX1U3sD/410DyEw1JEi41bYcK3qu/67QCsIuHYdvQ2S3qSpifdEHDjc+YEJ+ycD6vpRxVWbwpnwkzLN+P8x/mMnxCmoTwinHCzeWH1cuvTAcn" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufi_wrapper.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufi_wrapper.sv new file mode 100644 index 0000000000..cc41d3c365 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufi_wrapper.sv @@ -0,0 +1,102 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// UFI wrapper for FalconMesa EMIFs +/////////////////////////////////////////////////////////////////////////////// + +module altera_emif_arch_fm_ufi_wrapper #( + parameter MODE = "pin_ufi_use_in_direct_out_direct", + parameter IS_HPS = 1, + parameter IS_C2P = 1, + parameter HIPI_DELAY= 225, + parameter TIEOFF = 0 +) ( + input logic i_src_clk, + input logic i_dst_clk, + + input logic i_din, + output logic o_dout +); + generate + if (TIEOFF) begin + assign o_dout = i_din; + end else begin + if (IS_HPS && !IS_C2P) begin : hps_p2c_ufi + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_PERIPHERY_CORE_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 225; -name PRESERVE_FANOUT_FREE_WYSIWYG ON"} *) + tennm_ufi #( + .mode (MODE), + .datapath("p2c") + ) preserved_ufi_inst ( + .srcclk (i_src_clk), + .destclk(i_dst_clk), + .d (i_din), + .dout (o_dout) + ); + end else begin + if (!IS_C2P) begin : p2c_ufi + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_PERIPHERY_CORE_TRANSFER ON"} *) + tennm_ufi #( + .mode (MODE), + .datapath("p2c") + ) ufi_inst ( + .srcclk (i_src_clk), + .destclk(i_dst_clk), + .d (i_din), + .dout (o_dout) + ); + end else if (HIPI_DELAY == 350) begin : c2p_350_ufi + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 350"} *) + tennm_ufi #( + .mode (MODE), + .datapath("c2p") + ) ufi_inst ( + .srcclk (i_src_clk), + .destclk(i_dst_clk), + .d (i_din), + .dout (o_dout) + ); + end else if (HIPI_DELAY == 100) begin: c2p_100_ufi + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 100"} *) + tennm_ufi #( + .mode (MODE), + .datapath("c2p") + ) ufi_inst ( + .srcclk (i_src_clk), + .destclk(i_dst_clk), + .d (i_din), + .dout (o_dout) + ); + end else begin: c2p_225_ufi + (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 225"} *) + tennm_ufi #( + .mode (MODE), + .datapath("c2p") + ) ufi_inst ( + .srcclk (i_src_clk), + .destclk(i_dst_clk), + .d (i_din), + .dout (o_dout) + ); + end + + end + end + + endgenerate + + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm0lPb2rA9npgCsuUKWkVR8buKodsngmuaYUcPPhMbOy4jRLTU1fIhnf1XXGli+YcScsOTcDGnFg0QgpO1ZjPEQMROpWryoaCLxudrqQrP37YLNQ/2YNvnECYoVJJIknk8AWCKHsMT9mc9zLslnf3cVH31IdDO5oJNgTOVi6yzBMZP/RAHCYjtub/ZqEARvXmdZZhTCu67yxofqbfZ1bL8w/ohFyaVONGyYkpoHkGtwlOVCrlhjiV7TyUM5Cs5lf6g4zFVpIzNTxqkaAEZ9tjd8bQZfBh1NV5zxx45BOrjqZwnXhSE7Gv/FLJTPGLpF9Sr85EFvD4GCoKkbfKaP/flBh6Ets/BoHBUYCzraApBw4RV4NkvhQEyBMScP3UoCTEKaXYI1d9Bp+8ylaBFUnZ+zERTTuWvyUcBmhg96sZfE/kUEc8aVQGQvk/M9FY5ov/4i0D93djxvqQtRbQBRT710rFkCyHUIyJW5WNmdojB1ksSYSB1LAngcKswWZoiO92YkFrkUWrVl32H9ZNzuTm+7KxuXlWwwABXrKp4/1I0pur1ST4cHbXlO6thmj5CyozOJNHEa574S0wK3qyzNyTunkGkOL6r3dskvATLIy3Ki6QE9J5DZ8Xj/goIV6sXbPP0+DPLOlU+FfnQBuJsERlBrnO9I/EWxBzXLYgNFX9y7+Vr6hTaJWPVfGXhFsUKaaMA/CgSa/9GhKq5N3Aervm0DNR2Ev/UQEIb+0Sw254ikRpkElobm/IYV83iAsDXeDNUwoESDvt+QwOCjlt9gVfK13" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufis.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufis.sv new file mode 100644 index 0000000000..81ad823559 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufis.sv @@ -0,0 +1,784 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// Wrapper module for C2P/P2C UFIs +/////////////////////////////////////////////////////////////////////////////// + +`define _get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) ( DB_PINS_PROC_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 5 +: 5] ) +`define _get_pin_usage(_tile_i, _lane_i, _pin_i) ( LANE_PIN_USAGE[((_tile_i * LANES_PER_TILE * PINS_PER_LANE) + (_lane_i * PINS_PER_LANE) + _pin_i) * 4 +: 4] ) +`define _get_lane_usage(_tile_i, _lane_i) ( LANES_USAGE[(_tile_i * LANES_PER_TILE + _lane_i) * 3 +: 3] ) +`define _is_lane_ac_or_empty(_tile_i, _lane_i) ( `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_UNUSED ? 1 : ( \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_HMC ? 1 : ( \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_CORE ? 1 : ( \ + 0 )))) +`define _is_clk_pin(_tile_i, _lane_i, _pin_i) ( `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_CLK ? 1 : ( \ + `_get_db_pin_proc_mode_raw(_tile_i, _lane_i, _pin_i) == DB_PIN_PROC_MODE_CLKB ? 1 : ( \ + 0 ))) +module altera_emif_arch_fm_ufis #( + parameter NUM_OF_RTL_TILES = 1, + parameter LANES_PER_TILE = 1, + parameter PINS_PER_LANE = 1, + + parameter PROTOCOL_ENUM = "", + parameter AMM_C2P_UFI_MODE = "", + parameter AMM_P2C_UFI_MODE = "", + parameter MMR_C2P_UFI_MODE = "", + parameter MMR_P2C_UFI_MODE = "", + parameter SIDEBAND_C2P_UFI_MODE = "", + parameter SIDEBAND_P2C_UFI_MODE = "", + parameter SEQ_C2P_UFI_MODE = "", + parameter SEQ_P2C_UFI_MODE = "", + parameter ECC_C2P_UFI_MODE = "", + parameter ECC_P2C_UFI_MODE = "", + parameter LANE_C2P_UFI_MODE = "", + parameter LANE_P2C_UFI_MODE = "", + parameter LANE_PIN_USAGE = 0, + parameter LANES_USAGE = 0, + parameter DB_PINS_PROC_MODE = 0, + + parameter AMM_HIPI_DELAY = 225, + parameter MMR_HIPI_DELAY = 225, + parameter SIDEBAND_HIPI_DELAY = 225, + parameter SEQ_HIPI_DELAY = 225, + parameter ECC_HIPI_DELAY = 225, + parameter LANE_HIPI_DELAY = 225, + + parameter ENABLE_RD_TYPE = 0, + parameter PHY_PING_PONG_EN = 0, + parameter NUM_OF_HMC_PORTS = 1, + parameter PINS_C2L_DRIVEN = 0, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter IS_HPS = 0, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + parameter PRI_AC_TILE_INDEX = -1 +) ( + input logic ufi_phy_clk, + input logic ufi_core_clk, + + // Avalon interfaces between core and HMC + input logic [62:0] i_core2ctl_avl_0, + input logic [62:0] i_core2ctl_avl_1, + input logic i_core2ctl_avl_rd_data_ready_0, + input logic i_core2ctl_avl_rd_data_ready_1, + input logic i_ctl2core_avl_cmd_ready_0, + input logic i_ctl2core_avl_cmd_ready_1, + input logic [12:0] i_ctl2core_avl_rdata_id_0, + input logic [12:0] i_ctl2core_avl_rdata_id_1, + output logic [62:0] actual_core2ctl_avl_0, + output logic actual_core2ctl_avl_rd_data_ready_0, + output logic [62:0] actual_core2ctl_avl_1, + output logic actual_core2ctl_avl_rd_data_ready_1, + output logic actual_ctl2core_avl_cmd_ready_0, + output logic actual_ctl2core_avl_cmd_ready_1, + output logic [12:0] actual_ctl2core_avl_rdata_id_0, + output logic [12:0] actual_ctl2core_avl_rdata_id_1, + + // MMR signals between core and HMC + input logic [33:0] i_ctl2core_mmr_0, + input logic [50:0] i_core2ctl_mmr_0, + input logic [33:0] i_ctl2core_mmr_1, + input logic [50:0] i_core2ctl_mmr_1, + output logic [33:0] actual_ctl2core_mmr_0, + output logic [50:0] actual_core2ctl_mmr_0, + output logic [33:0] actual_ctl2core_mmr_1, + output logic [50:0] actual_core2ctl_mmr_1, + + // Side-band signals between core and HMC + input logic [41:0] i_core2ctl_sideband_0, + input logic [13:0] i_ctl2core_sideband_0, + input logic [41:0] i_core2ctl_sideband_1, + input logic [13:0] i_ctl2core_sideband_1, + output logic [41:0] actual_core2ctl_sideband_0, + output logic [13:0] actual_ctl2core_sideband_0, + output logic [41:0] actual_core2ctl_sideband_1, + output logic [13:0] actual_ctl2core_sideband_1, + + // sequencer signals between tile and core + input logic [17:0] i_c2t_afi, + input logic [26:0] i_t2c_afi, + output logic [17:0] actual_c2t_afi, + output logic [26:0] actual_t2c_afi, + + // Signals between core and data lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] i_core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] i_l2core_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] i_core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] i_core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] i_core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] i_core2l_mrnk_write, + input logic i_l2core_rd_type, + input logic [3:0] i_l2core_rdata_valid_pri, + input logic [3:0] i_l2core_rdata_valid_sec, + + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] actual_l2core_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] actual_core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] actual_core2l_oe, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] actual_core2l_rdata_en_full, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] actual_core2l_mrnk_read, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] actual_core2l_mrnk_write, + output logic actual_l2core_rd_type, + output logic [3:0] actual_l2core_rdata_valid_pri, + output logic [3:0] actual_l2core_rdata_valid_sec, + + // ECC signals between core and lanes + input logic i_core2l_wr_data_vld_ast, + input logic i_core2l_rd_data_rdy_ast, + input logic [12:0] i_core2l_wr_ecc_info, + input logic i_l2core_wr_data_rdy_ast, + input logic i_l2core_rd_data_vld_avl, + input logic [11:0] i_l2core_wb_pointer_for_ecc, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] actual_core2l_wr_data_vld_ast, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] actual_core2l_rd_data_rdy_ast, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][12:0] actual_core2l_wr_ecc_info, + output logic [11:0] actual_l2core_wb_pointer_for_ecc, + output logic actual_l2core_wr_data_rdy_ast, + output logic actual_l2core_rd_data_vld_avl + +); + + localparam UFI_IN_OUT_DIRECT_L0 = "pin_ufi_use_in_direct_out_direct"; + localparam UFI_C2P_FIFO_OREG_L2 = "pin_ufi_use_delay_fifo_out_reg"; + localparam UFI_P2C_FIFO_OREG_L2 = "pin_ufi_use_fast_fifo_out_reg"; + + typedef enum bit [2:0] { + LANE_USAGE_UNUSED = 3'b000, + LANE_USAGE_AC_HMC = 3'b001, + LANE_USAGE_AC_CORE = 3'b010, + LANE_USAGE_RDATA = 3'b011, + LANE_USAGE_WDATA = 3'b100, + LANE_USAGE_WRDATA = 3'b101 + } LANE_USAGE; + + // Enum that defines the pin usage within a lane + typedef enum bit [3:0] { + LANE_PIN_USAGE_MODE_UNUSED = 4'b0000, + LANE_PIN_USAGE_MODE_DQ = 4'b0001, + LANE_PIN_USAGE_MODE_DQS = 4'b0010, + LANE_PIN_USAGE_MODE_DQSB = 4'b0011, + LANE_PIN_USAGE_MODE_CA_SDR = 4'b0100, + LANE_PIN_USAGE_MODE_CA_DDR = 4'b0101, + LANE_PIN_USAGE_MODE_DM = 4'b1000, + LANE_PIN_USAGE_MODE_DBI = 4'b1001 + } LANE_PIN_USAGE_MODE; + + typedef enum bit [4:0] { + DB_PIN_PROC_MODE_AC_CORE = 5'b00000, + DB_PIN_PROC_MODE_AC_IN_CORE = 5'b10100, + DB_PIN_PROC_MODE_WDB_AC = 5'b00001, + DB_PIN_PROC_MODE_WDB_DQ = 5'b00010, + DB_PIN_PROC_MODE_WDB_DBI = 5'b00011, + DB_PIN_PROC_MODE_WDB_DM = 5'b00100, + DB_PIN_PROC_MODE_WDB_CLK = 5'b00101, + DB_PIN_PROC_MODE_WDB_CLKB = 5'b00110, + DB_PIN_PROC_MODE_WDB_DQS = 5'b00111, + DB_PIN_PROC_MODE_WDB_DQSB = 5'b01000, + DB_PIN_PROC_MODE_DQS = 5'b01001, + DB_PIN_PROC_MODE_DQSB = 5'b01010, + DB_PIN_PROC_MODE_DQ = 5'b01011, + DB_PIN_PROC_MODE_DM = 5'b01100, + DB_PIN_PROC_MODE_DBI = 5'b01101, + DB_PIN_PROC_MODE_CLK = 5'b01110, + DB_PIN_PROC_MODE_CLKB = 5'b01111, + DB_PIN_PROC_MODE_DQS_DDR4 = 5'b10000, + DB_PIN_PROC_MODE_DQSB_DDR4 = 5'b10001, + DB_PIN_PROC_MODE_RDQ = 5'b10010, + DB_PIN_PROC_MODE_RDQS = 5'b10011, + DB_PIN_PROC_MODE_GPIO = 5'b11111 + } DB_PIN_PROC_MODE; + + + generate + genvar tile_i, lane_i, pin_i, phase_i, sig_i; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] ufi_core2l_data /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] ufi_core2l_oe /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] ufi_core2l_rdata_en_full /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] ufi_core2l_mrnk_read /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] ufi_core2l_mrnk_write /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] ufi_l2core_data /*synthesis dont_merge*/; + + logic [3:0] ufi_l2core_rdata_valid_pri /*synthesis dont_merge*/; + logic [3:0] ufi_l2core_rdata_valid_sec /*synthesis dont_merge*/; + logic ufi_l2core_rd_data_vld_avl /*synthesis dont_merge*/; + logic ufi_l2core_rd_type /*synthesis dont_merge*/; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] ufi_core2l_rd_data_rdy_ast /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] ufi_core2l_wr_data_vld_ast /* synthesis dont_merge*/; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] [12:0] ufi_core2l_wr_ecc_info /* synthesis dont_merge*/; + logic ufi_l2core_wr_data_rdy_ast /*synthesis dont_merge*/; + logic [11:0] ufi_l2core_wb_pointer_for_ecc /* synthesis dont_merge*/; + + logic [62:0] ufi_core2ctl_avl_0 /*synthesis dont_merge*/; + logic ufi_core2ctl_avl_rd_data_ready_0 /*synthesis dont_merge*/; + logic ufi_ctl2core_avl_cmd_ready_0 /*synthesis dont_merge*/; + logic [12:0] ufi_ctl2core_avl_rdata_id_0 /*synthesis dont_merge*/; + + logic [62:0] ufi_core2ctl_avl_1 /*synthesis dont_merge*/; + logic ufi_core2ctl_avl_rd_data_ready_1 /* synthesis dont_merge*/; + logic ufi_ctl2core_avl_cmd_ready_1 /*synthesis dont_merge*/; + logic [12:0] ufi_ctl2core_avl_rdata_id_1 /*synthesis dont_merge*/; + + logic [33:0] ufi_ctl2core_mmr_0 /*synthesis dont_merge*/; + logic [50:0] ufi_core2ctl_mmr_0 /*synthesis dont_merge*/; + logic [33:0] ufi_ctl2core_mmr_1 /*synthesis dont_merge*/; + logic [50:0] ufi_core2ctl_mmr_1 /*synthesis dont_merge*/; + + logic [41:0] ufi_core2ctl_sideband_0 /*synthesis dont_merge*/; + logic [13:0] ufi_ctl2core_sideband_0 /*synthesis dont_merge*/; + logic [41:0] ufi_core2ctl_sideband_1 /*synthesis dont_merge*/; + logic [13:0] ufi_ctl2core_sideband_1 /*synthesis dont_merge*/; + + logic [17:0] ufi_seq_core2ctl /*synthesis dont_merge*/; + logic [26:0] ufi_seq_ctl2core /*synthesis dont_merge*/; + + + for (sig_i = 0; sig_i < 18; ++sig_i) begin: sequencer_c2p_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((PROTOCOL_ENUM == "PROTOCOL_QDR4") ? "pin_ufi_use_in_direct_out_direct" : SEQ_C2P_UFI_MODE), + .HIPI_DELAY (SEQ_HIPI_DELAY), + .IS_C2P (1), + .IS_HPS (IS_HPS), + .TIEOFF (NUM_OF_HMC_PORTS > 0 && sig_i > 7) + ) core2ctl_seq_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk (ufi_phy_clk), + .i_din (i_c2t_afi[sig_i]), + .o_dout (ufi_seq_core2ctl[sig_i]) + ); + end + + for (sig_i = 0; sig_i < 27; ++sig_i) begin: sequencer_p2c_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (SEQ_P2C_UFI_MODE), + .IS_HPS (IS_HPS), + .IS_C2P (0) + ) ctl2core_seq_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk (ufi_core_clk), + .i_din (i_t2c_afi[sig_i]), + .o_dout (ufi_seq_ctl2core[sig_i]) + ); + end + + if (NUM_OF_HMC_PORTS == 0) begin: tie_off_hmc_ufis + assign ufi_core2ctl_avl_0 = '0; + assign ufi_core2ctl_avl_1 = '0; + assign ufi_core2ctl_avl_rd_data_ready_0 = '1; + assign ufi_ctl2core_avl_cmd_ready_0 = '1; + assign ufi_ctl2core_avl_rdata_id_0 = '0; + assign ufi_core2ctl_avl_rd_data_ready_1 = '1; + assign ufi_ctl2core_avl_cmd_ready_1 = '1; + assign ufi_ctl2core_avl_rdata_id_1 = '0; + + assign ufi_ctl2core_mmr_0 = '0; + assign ufi_ctl2core_mmr_1 = '0; + assign ufi_core2ctl_mmr_0 = '0; + assign ufi_core2ctl_mmr_1 = '0; + assign ufi_core2ctl_sideband_0 = '0; + assign ufi_core2ctl_sideband_1 = '0; + assign ufi_ctl2core_sideband_0 = '0; + assign ufi_ctl2core_sideband_1 = '0; + end else begin : generate_hmc_ufis + for (sig_i = 0; sig_i < 63; ++sig_i) begin: avl_ctl_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_C2P_UFI_MODE), + .HIPI_DELAY(AMM_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) avl0_amm_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk (ufi_phy_clk), + .i_din (i_core2ctl_avl_0[sig_i]), + .o_dout (ufi_core2ctl_avl_0[sig_i]) + ); + + if (PHY_PING_PONG_EN) begin : sec_avl_ctl_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_C2P_UFI_MODE), + .HIPI_DELAY(AMM_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) avl1_amm_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk (ufi_phy_clk), + .i_din (i_core2ctl_avl_1[sig_i]), + .o_dout (ufi_core2ctl_avl_1[sig_i]) + ); + end + end + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_C2P_UFI_MODE), + .HIPI_DELAY(AMM_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) avl_rd_data_ready_0_amm_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk (ufi_phy_clk), + .i_din (i_core2ctl_avl_rd_data_ready_0), + .o_dout (ufi_core2ctl_avl_rd_data_ready_0) + ); + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) avl_cmd_ready_0_amm_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk (ufi_core_clk), + .i_din (i_ctl2core_avl_cmd_ready_0), + .o_dout (ufi_ctl2core_avl_cmd_ready_0) + ); + + for (sig_i = 0; sig_i < 13; ++sig_i) begin : ctl2core_avl_rdata_id_0_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) rdata_id_amm_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk (ufi_core_clk), + .i_din (i_ctl2core_avl_rdata_id_0[sig_i]), + .o_dout (ufi_ctl2core_avl_rdata_id_0[sig_i]) + ); + end + + if (PHY_PING_PONG_EN) begin : sec_avl_cmd_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_C2P_UFI_MODE), + .HIPI_DELAY(AMM_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) avl_rd_data_ready_1_amm_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk (ufi_phy_clk), + .i_din (i_core2ctl_avl_rd_data_ready_1), + .o_dout (ufi_core2ctl_avl_rd_data_ready_1) + ); + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) avl_cmd_ready_1_amm_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk (ufi_core_clk), + .i_din (i_ctl2core_avl_cmd_ready_1), + .o_dout (ufi_ctl2core_avl_cmd_ready_1) + ); + + for (sig_i = 0; sig_i < 13; ++sig_i) begin : ctl2core_avl_rdata_id_1_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (AMM_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) rdata_id_amm_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_ctl2core_avl_rdata_id_1[sig_i]), + .o_dout (ufi_ctl2core_avl_rdata_id_1[sig_i]) + ); + end + end + + for (sig_i = 0; sig_i < 34; ++sig_i) begin: ctl2core_mmr_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (MMR_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) mmr_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_ctl2core_mmr_0[sig_i]), + .o_dout (ufi_ctl2core_mmr_0[sig_i]) + ); + + if (PHY_PING_PONG_EN) begin : sec_ctl2core_mmr_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (MMR_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) mmr_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_ctl2core_mmr_1[sig_i]), + .o_dout (ufi_ctl2core_mmr_1[sig_i]) + ); + end + end + + for (sig_i = 0; sig_i < 51; ++sig_i) begin: core2ctl_mmr_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (MMR_C2P_UFI_MODE), + .HIPI_DELAY(MMR_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) mmr_c2p_ufi_i( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2ctl_mmr_0[sig_i]), + .o_dout (ufi_core2ctl_mmr_0[sig_i]) + ); + + if (PHY_PING_PONG_EN) begin : sec_core2ctl_mmr_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (MMR_C2P_UFI_MODE), + .HIPI_DELAY(MMR_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) mmr_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2ctl_mmr_1[sig_i]), + .o_dout (ufi_core2ctl_mmr_1[sig_i]) + ); + end + end + + for (sig_i = 0; sig_i < 42; ++sig_i) begin: core2ctl_sideband_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((sig_i < 27) ? (sig_i == 20) ? UFI_IN_OUT_DIRECT_L0 : SIDEBAND_C2P_UFI_MODE : ECC_C2P_UFI_MODE), + .HIPI_DELAY((sig_i < 27) ? SIDEBAND_HIPI_DELAY : ECC_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) sideband_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2ctl_sideband_0[sig_i]), + .o_dout (ufi_core2ctl_sideband_0[sig_i]) + ); + + if (PHY_PING_PONG_EN) begin : sec_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((sig_i < 27) ? SIDEBAND_C2P_UFI_MODE : ECC_C2P_UFI_MODE), + .HIPI_DELAY((sig_i < 27) ? SIDEBAND_HIPI_DELAY : ECC_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) sideband_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2ctl_sideband_1[sig_i]), + .o_dout (ufi_core2ctl_sideband_1[sig_i]) + ); + end + end + + for (sig_i = 0; sig_i < 14; ++sig_i) begin: ctl2core_sideband_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((sig_i < 6 || sig_i == 12) ? ECC_P2C_UFI_MODE : SIDEBAND_P2C_UFI_MODE), + .IS_HPS (IS_HPS), + .IS_C2P (0) + ) sideband_p2c_ufi_i ( + .i_src_clk(ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_ctl2core_sideband_0[sig_i]), + .o_dout (ufi_ctl2core_sideband_0[sig_i]) + ); + if (PHY_PING_PONG_EN) begin : sec_ctl2core_sideband_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((sig_i < 6 || sig_i == 12) ? ECC_P2C_UFI_MODE : SIDEBAND_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) sideband_p2c_ufi_i ( + .i_src_clk(ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_ctl2core_sideband_1[sig_i]), + .o_dout (ufi_ctl2core_sideband_1[sig_i]) + ); + end + end + end + + + assign actual_core2ctl_avl_0 = ufi_core2ctl_avl_0; + assign actual_ctl2core_avl_cmd_ready_0 = ufi_ctl2core_avl_cmd_ready_0; + assign actual_ctl2core_avl_rdata_id_0 = ufi_ctl2core_avl_rdata_id_0; + assign actual_core2ctl_avl_rd_data_ready_0 = ufi_core2ctl_avl_rd_data_ready_0 ; + + assign actual_ctl2core_mmr_0 = ufi_ctl2core_mmr_0; + assign actual_core2ctl_mmr_0 = ufi_core2ctl_mmr_0; + assign actual_core2ctl_sideband_0 = ufi_core2ctl_sideband_0; + assign actual_ctl2core_sideband_0 = ufi_ctl2core_sideband_0; + + assign actual_c2t_afi = ufi_seq_core2ctl; + assign actual_t2c_afi = ufi_seq_ctl2core; + + if (PHY_PING_PONG_EN) begin : sec_tie_offs + assign actual_ctl2core_mmr_1 = ufi_ctl2core_mmr_1; + assign actual_core2ctl_mmr_1 = ufi_core2ctl_mmr_1; + assign actual_core2ctl_sideband_1 = ufi_core2ctl_sideband_1; + assign actual_ctl2core_sideband_1 = ufi_ctl2core_sideband_1; + assign actual_core2ctl_avl_1 = ufi_core2ctl_avl_1; + assign actual_ctl2core_avl_cmd_ready_1 = ufi_ctl2core_avl_cmd_ready_1; + assign actual_ctl2core_avl_rdata_id_1 = ufi_ctl2core_avl_rdata_id_1; + assign actual_core2ctl_avl_rd_data_ready_1 = ufi_core2ctl_avl_rd_data_ready_1; + end else begin : no_ufis + assign actual_ctl2core_mmr_1 = i_ctl2core_mmr_1; + assign actual_core2ctl_mmr_1 = i_core2ctl_mmr_1; + assign actual_core2ctl_sideband_1 = i_core2ctl_sideband_1; + assign actual_ctl2core_sideband_1 = i_ctl2core_sideband_1; + assign actual_core2ctl_avl_1 = i_core2ctl_avl_1; + assign actual_ctl2core_avl_cmd_ready_1 = i_ctl2core_avl_cmd_ready_1; + assign actual_ctl2core_avl_rdata_id_1 = i_ctl2core_avl_rdata_id_1; + assign actual_core2ctl_avl_rd_data_ready_1 = i_core2ctl_avl_rd_data_ready_1; + end + + if (NUM_OF_HMC_PORTS > 0) begin : p2c_per_if_hmc_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) rd_data_vld_avl_lane_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_l2core_rd_data_vld_avl), + .o_dout (ufi_l2core_rd_data_vld_avl) + ); + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0), + .TIEOFF(ENABLE_RD_TYPE) + ) rd_type_avl_lane_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk (ufi_core_clk), + .i_din (i_l2core_rd_type), + .o_dout (ufi_l2core_rd_type) + ); + + if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_ST") begin : p2c_ecc_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (ECC_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) wr_data_rdy_ast_ecc_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_l2core_wr_data_rdy_ast), + .o_dout (ufi_l2core_wr_data_rdy_ast) + ); + for (sig_i = 0; sig_i < 12; ++sig_i) begin : ecc_wb_ptr_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (ECC_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) wb_ptr_ecc_p2c_ufi_i( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_l2core_wb_pointer_for_ecc[sig_i]), + .o_dout (ufi_l2core_wb_pointer_for_ecc[sig_i]) + ); + end + end else begin : p2c_ecc_tie_off + assign ufi_l2core_wr_data_rdy_ast = i_l2core_wr_data_rdy_ast; + assign ufi_l2core_wb_pointer_for_ecc = 12'b0; + end + + assign ufi_l2core_rdata_valid_pri = '0; + assign ufi_l2core_rdata_valid_sec = '0; + + end else begin : p2c_per_if_smc + for (sig_i = 0; sig_i < 4; ++sig_i) begin: rvalid_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) pri_rvalid_lane_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_l2core_rdata_valid_pri[sig_i]), + .o_dout (ufi_l2core_rdata_valid_pri[sig_i]) + ); + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_P2C_UFI_MODE), + .IS_HPS(IS_HPS), + .IS_C2P(0) + ) sec_rvalid_lane_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_l2core_rdata_valid_sec[sig_i]), + .o_dout (ufi_l2core_rdata_valid_sec[sig_i]) + ); + end + + assign ufi_l2core_wb_pointer_for_ecc = '0; + assign ufi_l2core_wr_data_rdy_ast = '0; + assign ufi_l2core_rd_data_vld_avl = '0; + assign ufi_l2core_rd_type = '0; + end + + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) begin: tile_gen + for (lane_i = 0; lane_i < LANES_PER_TILE; ++lane_i) begin: lane_gen + localparam AC_TIE_OFF = `_is_lane_ac_or_empty(tile_i, lane_i) || (NUM_OF_HMC_PORTS != 0); + + for (sig_i = 0; sig_i < 48; ++sig_i) begin: oe_ufi_gen + altera_emif_arch_fm_ufi_wrapper # ( + .MODE (LANE_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1), + .TIEOFF (AC_TIE_OFF) + ) oe_lane_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_oe[tile_i][lane_i][sig_i]), + .o_dout (ufi_core2l_oe[tile_i][lane_i][sig_i]) + ); + end + for (sig_i = 0; sig_i < 4; ++sig_i) begin: rdata_en_full_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1), + .TIEOFF (AC_TIE_OFF) + ) rdata_en_lane_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_rdata_en_full[tile_i][lane_i][sig_i]), + .o_dout (ufi_core2l_rdata_en_full[tile_i][lane_i][sig_i]) + ); + end + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (ECC_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1), + .TIEOFF (HMC_AVL_PROTOCOL_ENUM != "CTRL_AVL_PROTOCOL_ST") + ) wr_data_vld_ast_ecc_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_wr_data_vld_ast), + .o_dout (ufi_core2l_wr_data_vld_ast[tile_i][lane_i]) + ); + altera_emif_arch_fm_ufi_wrapper #( + .MODE (ECC_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1), + .TIEOFF (HMC_AVL_PROTOCOL_ENUM != "CTRL_AVL_PROTOCOL_ST") + ) rd_data_rdy_ast_ecc_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_rd_data_rdy_ast), + .o_dout (ufi_core2l_rd_data_rdy_ast[tile_i][lane_i]) + ); + + for (sig_i = 0; sig_i < 8; ++sig_i) begin: mrnk_ufi_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((PROTOCOL_ENUM == "PROTOCOL_QDR4") ? "pin_ufi_use_in_direct_out_direct" : LANE_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1), + .TIEOFF (NUM_OF_HMC_PORTS != 0) + ) mrnk_read_lane_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_mrnk_read[tile_i][lane_i][sig_i]), + .o_dout (ufi_core2l_mrnk_read[tile_i][lane_i][sig_i]) + ); + + altera_emif_arch_fm_ufi_wrapper #( + .MODE ((PROTOCOL_ENUM == "PROTOCOL_QDR4") ? "pin_ufi_use_in_direct_out_direct" : LANE_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1), + .TIEOFF (NUM_OF_HMC_PORTS != 0) + ) mrnk_write_lane_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_mrnk_write[tile_i][lane_i][sig_i]), + .o_dout (ufi_core2l_mrnk_write[tile_i][lane_i][sig_i]) + ); + end + + for (sig_i = 0; sig_i < 13; ++sig_i) begin: ecc_info_gen + altera_emif_arch_fm_ufi_wrapper #( + .MODE (ECC_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) info_ecc_c2p_ufi_i( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_wr_ecc_info[sig_i]), + .o_dout (ufi_core2l_wr_ecc_info[tile_i][lane_i][sig_i]) + ); + end + + for (pin_i = 0; pin_i < PINS_PER_LANE; ++pin_i) begin : pin_gen + localparam phase_size = ((`_get_pin_usage(tile_i, lane_i, pin_i) == LANE_PIN_USAGE_MODE_CA_SDR) || `_is_clk_pin(tile_i, lane_i, pin_i)) ? 4 : 8; + + for (phase_i = 0; phase_i < 8; ++phase_i) begin : phase_gen + if ( (phase_i < phase_size) && PINS_C2L_DRIVEN[(LANES_PER_TILE * PINS_PER_LANE) * tile_i + PINS_PER_LANE * lane_i + pin_i] ) begin + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_C2P_UFI_MODE), + .HIPI_DELAY(LANE_HIPI_DELAY), + .IS_HPS (IS_HPS), + .IS_C2P (1) + ) data_lane_c2p_ufi_i ( + .i_src_clk (ufi_core_clk), + .i_dst_clk(ufi_phy_clk), + .i_din (i_core2l_data[tile_i][lane_i][8 * pin_i + phase_i]), + .o_dout (ufi_core2l_data[tile_i][lane_i][8 * pin_i + phase_i]) + ); + + altera_emif_arch_fm_ufi_wrapper #( + .MODE (LANE_P2C_UFI_MODE), + .IS_HPS (IS_HPS), + .IS_C2P (0), + .TIEOFF (NUM_OF_HMC_PORTS != 0 && pin_i==6) + ) data_lane_p2c_ufi_i ( + .i_src_clk (ufi_phy_clk), + .i_dst_clk(ufi_core_clk), + .i_din (i_l2core_data[tile_i][lane_i][8 * pin_i + phase_i]), + .o_dout (ufi_l2core_data[tile_i][lane_i][8 * pin_i + phase_i]) + ); + assign actual_core2l_data[tile_i][lane_i][8 * pin_i + phase_i] = ufi_core2l_data[tile_i][lane_i][8 * pin_i + phase_i]; + assign actual_l2core_data[tile_i][lane_i][8 * pin_i + phase_i] = ufi_l2core_data[tile_i][lane_i][8 * pin_i + phase_i]; + end else begin + assign actual_core2l_data[tile_i][lane_i][8 * pin_i + phase_i] = i_core2l_data[tile_i][lane_i][8 * pin_i + phase_i]; + assign actual_l2core_data[tile_i][lane_i][8 * pin_i + phase_i] = i_l2core_data[tile_i][lane_i][8 * pin_i + phase_i]; + end + end + end + end + end + + assign actual_l2core_rd_type = ufi_l2core_rd_type; + assign actual_l2core_rd_data_vld_avl = ufi_l2core_rd_data_vld_avl; + assign actual_l2core_wr_data_rdy_ast = ufi_l2core_wr_data_rdy_ast; + assign actual_l2core_rdata_valid_pri = ufi_l2core_rdata_valid_pri; + assign actual_l2core_rdata_valid_sec = ufi_l2core_rdata_valid_sec; + + assign actual_core2l_oe = ufi_core2l_oe; + assign actual_core2l_rdata_en_full = ufi_core2l_rdata_en_full; + + assign actual_core2l_mrnk_read = ufi_core2l_mrnk_read; + assign actual_core2l_mrnk_write = ufi_core2l_mrnk_write; + + assign actual_l2core_wb_pointer_for_ecc = ufi_l2core_wb_pointer_for_ecc; + assign actual_core2l_wr_ecc_info = ufi_core2l_wr_ecc_info; + assign actual_core2l_wr_data_vld_ast = ufi_core2l_wr_data_vld_ast; + assign actual_core2l_rd_data_rdy_ast = ufi_core2l_rd_data_rdy_ast; + + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm1oKyPZcd5kjMwa4n0A4xOKz9qUQXFQ2gsapiCXVq166BU40pq//T1QzfJs0GctI4nj1Erpj72AJVYt0W8FNaE2gvqBYaEuLSKK/cLcX1Tn+Fb0zPvgXEferiTC0FmH7ol0/9R49qrKwsilR8ei8imZrClUbsh3B4IPMQtYL7e7CfVgbKutVRXtalZ8kdfT68CAGOHXQ5V4it1DsH/6Kf7AvcsrY62eBO/AlP2Q3JeGdm2BHTnE36CCYvoDW3yQ793/di9qQUSqqrTpormr8eaRUqjEe6rtm/qR1N6a17IoxQlTL+ZoDMM6LakoRclnHpoM60IF68B/0p/4hNI7TwOp5GOzYyDLU9pnj8Mx2DPfT5eFNFelCqHahy7A5P2UTufFNCgAjYu8SFcPTf0czESrnO+5zk9XWi9ZZLIodOsXF6cwXwLWeCQmFQq/JhnUI07M7ayhRgJ+7ZwHsLwCUeHgOGs2eSzzVhK4NLLcJq//nKVDUHgFVZiH7Pnh8ySAok5iYHp0J5JTaOj88VaARTKkxJ2DnSSbUzf/3XOQdo5++Y8fBmyvdD35EVRaCxGT2IJxALaRV26PDlFvyV7sMQ/YOarJBF8g1hpXFT2hWwNclFhG797zReIWGNubwKALfQ/bpf+JIg/X0IDSzVrKxT8J8A5t4XYReZTPnaK2DPRutkzLiUT5aFULtAn3KXV50b4rH/Ewgzsuvmaxyxd6faq71tgfcEwaEGMk8IB6KbbMZUWMEr/TDuxy7etlpm7LhEV44rbyhJ+IoePTiEccCIQ1" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_std_synchronizer_nocut.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_std_synchronizer_nocut.v new file mode 100644 index 0000000000..6193835c5b --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/altera_std_synchronizer_nocut.v @@ -0,0 +1,267 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $ +// $Revision: #8 $ +// $Date: 2009/02/18 $ +// $Author: pscheidt $ +//----------------------------------------------------------------------------- +// +// File: altera_std_synchronizer_nocut.v +// +// Abstract: Single bit clock domain crossing synchronizer. Exactly the same +// as altera_std_synchronizer.v, except that the embedded false +// path constraint is removed in this module. If you use this +// module, you will have to apply the appropriate timing +// constraints. +// +// We expect to make this a standard Quartus atom eventually. +// +// Composed of two or more flip flops connected in series. +// Random metastable condition is simulated when the +// __ALTERA_STD__METASTABLE_SIM macro is defined. +// Use +define+__ALTERA_STD__METASTABLE_SIM argument +// on the Verilog simulator compiler command line to +// enable this mode. In addition, define the macro +// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output +// with every metastable event generated in the synchronizer. +// +// Copyright (C) Altera Corporation 2009, All Rights Reserved +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_std_synchronizer_nocut ( + clk, + reset_n, + din, + dout + ); + + parameter depth = 3; // This value must be >= 2 ! + parameter rst_value = 0; + + //when enabled, this will allow retiming for the sync depth >3. + parameter retiming_reg_en = 0; + + input clk; + input reset_n; + input din; + output dout; + + // QuartusII synthesis directives: + // 1. Preserve all registers ie. do not touch them. + // 2. Do not merge other flip-flops with synchronizer flip-flops. + // QuartusII TimeQuest directives: + // 1. Identify all flip-flops in this module as members of the synchronizer + // to enable automatic metastability MTBF analysis. + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1; + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; + + //synthesis translate_off + `ifndef QUARTUS_CDC + initial begin + if (retiming_reg_en == 0 ) begin + if (depth <2) begin + $display("%m: Error: synchronizer length: %0d less than 2.", depth); + end + end + else begin + if (depth <4) begin + $display("%m: Error: synchronizer length: %0d less than 4 with retiming enabled.", depth); + end + end + end + `endif + + // the first synchronizer register is either a simple D flop for synthesis + // and non-metastable simulation or a D flop with a method to inject random + // metastable events resulting in random delay of [0,1] cycles + +`ifdef __ALTERA_STD__METASTABLE_SIM + + reg[31:0] RANDOM_SEED = 123456; + wire next_din_s1; + wire dout; + reg din_last; + reg random; + event metastable_event; // hook for debug monitoring + + initial begin + $display("%m: Info: Metastable event injection simulation mode enabled"); + random = $random; + end + + always @(posedge clk) begin + if (reset_n == 0) + random <= $random(RANDOM_SEED); + else + random <= $random; + end + + assign next_din_s1 = (din_last ^ din) ? random : din; + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_last <= (rst_value == 0)? 1'b0 : 1'b1; + else + din_last <= din; + end + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= (rst_value == 0)? 1'b0 : 1'b1; + else + din_s1 <= next_din_s1; + end + +`else + + //synthesis translate_on + generate if (rst_value == 0) + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b0; + else + din_s1 <= din; + end + endgenerate + + generate if (rst_value == 1) + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b1; + else + din_s1 <= din; + end + endgenerate + //synthesis translate_off + +`endif + +`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE + always @(*) begin + if (reset_n && (din_last != din) && (random != din)) begin + $display("%m: Verbose Info: metastable event @ time %t", $time); + ->metastable_event; + end + end +`endif + + //synthesis translate_on + + // the remaining synchronizer registers form a simple shift register + // of length depth-1 + generate if (rst_value == 0) begin + if (retiming_reg_en == 0) begin + if (depth < 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= din_s1; + end + end else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= {dreg[depth-3:0], din_s1}; + end + end + + assign dout = dreg[depth-2]; + end + + else begin //This part is enabled when we set retiming_reg_en =1 + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1; + reg [depth-4:0] dreg2; + wire [depth-2:0] dreg3; + + assign dreg3 = {dreg2,dreg1}; + + if (depth <= 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg1 <= {depth-1{1'b0}}; + else + dreg1 <= din_s1; + end + end + else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + {dreg2,dreg1} <= {depth-1{1'b0}}; + else + {dreg2,dreg1} <= {dreg3[depth-3:0], din_s1}; + end + end + assign dout = dreg3[depth-2]; + end + end + + + else begin + if (retiming_reg_en == 0) begin + if (depth < 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b1}}; + else + dreg <= din_s1; + end + end else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b1}}; + else + dreg <= {dreg[depth-3:0], din_s1}; + end + end + assign dout = dreg[depth-2]; + end + + else begin + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1; + reg [depth-4:0] dreg2; + wire [depth-2:0] dreg3; + + assign dreg3 = {dreg2,dreg1}; + + if (depth <= 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg1 <= {depth-1{1'b1}}; + else + dreg1 <= din_s1; + end + end + else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + {dreg2,dreg1} <= {depth-1{1'b1}}; + else + {dreg2,dreg1} <= {dreg3[depth-3:0], din_s1}; + end + end + assign dout = dreg3[depth-2]; + end + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "aBtvkOB0rVavpqYSnxGbfcYBNx6OkCwAi2K9gh9Y53caqg+VfzD4if1Wx+NybTLcpY+PnuQz6pp9KScOY4ye64zeX7CBjYAFsecofqjfk4a1c+382xda6/OF2dJrJri51Uq3eJPH2tWhlL9RydkIvKPJDVVgsS6+mu9Mhzg00gJFu3PHFz80h2m0h/O4E8aAn998tC3clvatEJIWGp/WDkQ+DABTXAmgzljq9l00wHHlQKp4dZWIzdPxUtrHxAa3x1dtnlScSyYYyx2fXHeg/nh3nZxYZ4QbQ7MBw0OMADXU0N8CpFFQljG99TZjQBJdLBLJRYSY71DTm85eCDqeM1MOSgf3F47ZHihaaJgfOK5Qy1myN8Un9uiKFilNXwp8mpHadYS4Z582GkRuV6zlovrdby/xESUQf1/DWgC0CF/vlTsP8Jpw3vTPq2h1bILGPzTrQpJqQFSASl6pC69qTXRxUAh5vV7FgwSd7BcKB24KtZcsMlqlEZvLfurZLUo+yj86zGm/S0rFIVbBSCuY+J9OMaOEloV7WkDREZ6lR6KN97Ry3IsHnr03SMgkFAPTubk1EEO+6cOkjYaxemUs6vsbyan5i9VbF88m1X5ITFRfOCNB4p5eWppdirYruL+EkSudlEj7XjY08nJg3IDo/8DRr5yqp7t9WybAm5vHsd3rgb7ruVFAjP8KoedXf5gwhkslO8NcZqADGNh/3I21On06VBJ0Tmh7mOQjzUKdeMLzyzRegco5pWDphgD51Iej5wZOoJLzyZbJkRN+h+o74LNmZE22KRWx6bdS2eNx08/dmLBAY2JB6P7xAgfxalYQY5FyWXWVlw9DiHqRuGOtJRI0Rf8hudKDET6LnVXRYnjAM5x/Kxw3VW8e1lX8zKCnP42NZ+Cs7+SMc3xkDdndFQOErW1eGLxV4poLgtp2LYn58ff9E21ixrxe6l6n73D6INSQXyh+399nt2zmXfmZ/CluDKJOOSHBulbzntO6ctpcKUjU+bz6yYn+oddPmMzo" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sdc b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sdc new file mode 100644 index 0000000000..3789a10c4e --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sdc @@ -0,0 +1,1100 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file specifies the timing constraints of the memory device and +# of the memory interface + +# ------------------------------------------- # +# - - # +# --- Some useful functions and variables --- # +# - - # +# ------------------------------------------- # + +set script_dir [file dirname [info script]] +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl" + +#--------------------------------------------# +# - - # +# --- Determine when SDC is being loaded --- # +# - - # +#--------------------------------------------# + +set syn_flow 0 +set sta_flow 0 +set fit_flow 0 +set pow_flow 0 +if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" || $::TimeQuestInfo(nameofexecutable) == "quartus_syn" } { + set syn_flow 1 +} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_sta" } { + set sta_flow 1 +} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_fit" } { + set fit_flow 1 +} elseif { $::TimeQuestInfo(nameofexecutable) == "quartus_pow" } { + set pow_flow 1 +} +set ::io_only_analysis 0 + +# ------------------------ # +# - - # +# --- GENERAL SETTINGS --- # +# - - # +# ------------------------ # + +# This is a global setting and will apply to the whole design. +# This setting is required for the memory interface to be +# properly constrained. +derive_clock_uncertainty + +# Debug switch. Change to 1 to get more run-time debug information +set debug 0 + +# All timing requirements will be represented in nanoseconds with up to 3 decimal places of precision +set_time_format -unit ns -decimal_places 3 + +# Determine if entity names are on +set entity_names_on [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_are_entity_names_on ] + +# ---------------------- # +# - - # +# --- DERIVED TIMING --- # +# - - # +# ---------------------- # + +# PLL multiplier to mem clk +regexp {([0-9\.]+) ps} $var(PLL_REF_CLK_FREQ_PS_STR) match var(PHY_REF_CLK_FREQ_PS) +regexp {([0-9\.]+) ps} $var(PLL_VCO_FREQ_PS_STR) match var(PHY_VCO_FREQ_PS) +set pll_multiplier [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [expr $var(PHY_MEM_CLK_FREQ_MHZ)/$var(PHY_REF_CLK_FREQ_MHZ)] ] +set vco_multiplier [expr int($var(PHY_REF_CLK_FREQ_PS)/$var(PHY_VCO_FREQ_PS))] + +# Half of memory clock cycle +set half_period [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr $var(UI) / 2.0 ] ] + +# Half of reference clock +set ref_period [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr $var(PHY_REF_CLK_FREQ_PS)/1000.0] ] +set ref_half_period [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr $ref_period / 2.0 ] ] + +# Other clock periods +set tCK_AFI [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr 1000.0/$var(PHY_MEM_CLK_FREQ_MHZ)*$var(USER_CLK_RATIO) ] ] +set tCK_C2P_P2C [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr 1000.0/$var(PHY_MEM_CLK_FREQ_MHZ)*$var(C2P_P2C_CLK_RATIO) ] ] +set tCK_PHY [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr 1000.0/$var(PHY_MEM_CLK_FREQ_MHZ)*$var(PHY_HMC_CLK_RATIO) ] ] + +# Asymmetric uncertainties on address and command paths +set ac_min_delay [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr - $var(tIH) + $var(CA_TO_CK_BD_PKG_SKEW) ]] +set ac_max_delay [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [ expr $var(tIS) + $var(CA_TO_CK_BD_PKG_SKEW) ]] + +# ---------------------- # +# - - # +# --- INTERFACE RATE --- # +# - - # +# ---------------------- # + +# -------------------------------------------------------------------- # +# - - # +# --- This is the main call to the netlist traversal routines --- # +# --- that will automatically find all pins and registers required --- # +# --- to apply timing constraints. --- # +# --- During the fitter, the routines will be called only once --- # +# --- and cached data will be used in all subsequent calls. --- # +# - - # +# -------------------------------------------------------------------- # + +if { ! [ info exists ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sdc_cache ] } { + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_initialize_ddr_db ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ddr_db var + set ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sdc_cache 1 +} else { + if { $debug } { + post_message -type info "SDC: reusing cached DDR DB" + } +} + +# ------------------------------------------------------------- # +# - - # +# --- If multiple instances of this core are present in the --- # +# --- design they will all be constrained through the --- # +# --- following loop --- # +# - - # +# ------------------------------------------------------------- # + +set instances [ array names ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ddr_db ] +foreach { inst } $instances { + if { [ info exists pins ] } { + unset pins + } + array set pins $ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ddr_db($inst) + + # ----------------------- # + # - - # + # --- REFERENCE CLOCK --- # + # - - # + # ----------------------- # + + # First determine if a reference clock has already been created (i.e. Reference clock sharing) + set ref_clock_exists [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_does_ref_clk_exist $pins(pll_ref_clock) ] + if { $ref_clock_exists == 0 } { + # This is the reference clock used by the PLL to derive any other clock in the core + create_clock -period "$var(PHY_REF_CLK_FREQ_MHZ)MHz" -waveform [ list 0 $ref_half_period ] $pins(pll_ref_clock) -add -name ${inst}_ref_clock + } + set pins(ref_clock_name) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_name_from_pin_name $pins(pll_ref_clock)] + + # ------------------ # + # - - # + # --- PLL CLOCKS --- # + # - - # + # ------------------ # + + # VCO clock + #We also detect and save the index of the clocks that drive the CPAs + set is_master [expr {([string compare $inst $pins(master_instname)] == 0) ? 1 : 0}] + set i_vco_clock 0 + set i_cpa_clock_tile_pri -1 + set i_cpa_clock_tile_sec -1 + foreach { vco_clock } $pins(pll_vco_clock) { + + set suffix "_${i_vco_clock}" + if {$vco_clock == $pins(master_vco_clock)} { + set suffix "" + if {$is_master} { + set i_cpa_clock_tile_pri $i_vco_clock + } + } elseif {$vco_clock == $pins(master_vco_clock_sec)} { + if {$is_master} { + set i_cpa_clock_tile_sec $i_vco_clock + } + } + + set local_pll_vco_clk_${i_vco_clock} [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $vco_clock \ + -name "${inst}_vco_clk${suffix}" \ + -source $pins(pll_ref_clock) \ + -multiply_by [expr $vco_multiplier ] \ + -divide_by 1 \ + -phase 0 ] + incr i_vco_clock + } + + if {! $var(IS_HPS)} { + if {$is_master} { + if {$i_cpa_clock_tile_pri == -1} { + post_message -type critical_warning "Failed to find CPA clock index" + } + if {$i_cpa_clock_tile_sec == -1 && $var(PHY_PING_PONG_EN)} { + post_message -type critical_warning "Failed to find CPA clock index for secondary interface" + } + } + } + + # Core clocks + set core_clocks [list] + set core_clocks_local [list] + + # Skip if we're in HPS mode since there's no user accessible core clock + # and there's no transfers within core fabric to analyze + if {! $var(IS_HPS)} { + + set local_pll_master_vco_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $pins(master_vco_clock) \ + -name "${pins(master_instname)}_vco_clk" \ + -source $pins(pll_ref_clock) \ + -multiply_by [expr $vco_multiplier ] \ + -divide_by 1 \ + -phase 0 ] + + # emif_usr_clk + # Clock only exists when HMC is used. + set local_core_usr_clock "" + if {$pins(master_core_usr_clock) != ""} { + set name "core_usr_clk" + set master_core_clock $pins(master_core_usr_clock) + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO)}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_core_usr_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by\ + -phase $phase ] + + lappend core_clocks $pins(master_core_usr_clock) + lappend core_clocks_local $local_core_usr_clock + } + + # emif_usr_clk_sec + # Clock only exists when ping-pong HMC is used + set local_core_usr_clock_sec "" + if {$pins(master_core_usr_clock_sec) != ""} { + set name "core_usr_clk_sec" + set master_core_clock_sec $pins(master_core_usr_clock_sec) + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO)}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_core_usr_clock_sec [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock_sec \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock_sec) \ + -multiply_by 1 \ + -divide_by $divide_by\ + -phase $phase ] + + lappend core_clocks $pins(master_core_usr_clock_sec) + lappend core_clocks_local $local_core_usr_clock_sec + } + + # emif_usr_half_clk + # Clock only exists when HMC is used and in 2x bridge mode + set local_core_usr_half_clock "" + if {$pins(master_core_usr_half_clock) != ""} { + set name "core_usr_half_clk" + set master_core_clock $pins(master_core_usr_half_clock) + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO) * 2}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_core_usr_half_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by\ + -phase $phase ] + + lappend core_clocks $pins(master_core_usr_half_clock) + lappend core_clocks_local $local_core_usr_half_clock + } + + # emif_usr_half_clk + # Clock only exists when ping-pong HMC is used and in 2x bridge mode + set local_core_usr_half_clock_sec "" + if {$pins(master_core_usr_half_clock_sec) != ""} { + set name "core_usr_half_clk_sec" + set master_core_clock_sec $pins(master_core_usr_half_clock_sec) + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO) * 2}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_core_usr_half_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock_sec \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock_sec) \ + -multiply_by 1 \ + -divide_by $divide_by\ + -phase $phase ] + + lappend core_clocks $pins(master_core_usr_half_clock_sec) + lappend core_clocks_local $local_core_usr_half_clock + } + + # afi_clk + # Clock only exists when HMC isn't used. + set local_core_afi_clock "" + if {$pins(master_core_afi_clock) != ""} { + set name "core_afi_clk" + set master_core_clock $pins(master_core_afi_clock) + if {$var(USER_CLK_RATIO) == 8} { + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO) / 2}] + } else { + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO)}] + } + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_core_afi_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by\ + -phase $phase ] + + lappend core_clocks $pins(master_core_afi_clock) + lappend core_clocks_local $local_core_afi_clock + } + + # extra CPA output for PE test purpose. + set local_core_dft_cpa_1_clock "" + if {$pins(master_core_dft_cpa_1_clock) != ""} { + set name "core_dft_cpa_1_clk" + set master_core_clock $pins(master_core_dft_cpa_1_clock) + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(USER_CLK_RATIO)}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_core_dft_cpa_1_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by\ + -phase $phase ] + + lappend core_clocks $pins(master_core_dft_cpa_1_clock) + lappend core_clocks_local $local_core_dft_cpa_1_clock + } + + # Calibration master logic clock + if {$pins(master_cal_master_clk) != ""} { + set pll_cal_master_clk [get_pins -nowarn $pins(master_cal_master_clk)] + + if {[get_collection_size $pll_cal_master_clk] > 0} { + set name "core_cal_master_clk" + set master_core_clock $pins(master_cal_master_clk) + set divide_by $var(pll_c4_cnt) + set phase [expr { [lindex $var(PLL_C_CNT_PHASE_PS_STR_4) 0] * 360.0 / $var(PHY_VCO_FREQ_PS) / $var(pll_c4_cnt) } ] + set duty_cyc $var(PLL_C_CNT_DUTY_CYCLE_4) + + set local_cal_master_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cyc ] + + lappend core_clocks $pins(master_cal_master_clk) + lappend core_clocks_local $local_cal_master_clock + } + } + + # Calibration slave logic clock + if {$pins(master_cal_slave_clk) != ""} { + set pll_cal_slave_clk [get_pins -nowarn $pins(master_cal_slave_clk)] + + if {[get_collection_size $pll_cal_slave_clk] > 0} { + set name "core_cal_slave_clk" + set master_core_clock $pins(master_cal_slave_clk) + set divide_by $var(pll_c3_cnt) + set phase [expr { [lindex $var(PLL_C_CNT_PHASE_PS_STR_3) 0] * 360.0 / $var(PHY_VCO_FREQ_PS) / $var(pll_c3_cnt) } ] + set duty_cyc $var(PLL_C_CNT_DUTY_CYCLE_3) + + set local_cal_slave_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cyc ] + + lappend core_clocks $pins(master_cal_slave_clk) + lappend core_clocks_local $local_cal_slave_clock + } + } + + # Optional PLL Extra clocks + for {set i_extra_clk 0} {$i_extra_clk < $var(PLL_NUM_OF_EXTRA_CLKS)} {incr i_extra_clk} { + set pll_extra_clk [get_pins -nowarn $pins(pll_extra_clk_${i_extra_clk})] + + # PLL counter may not exist if clock isn't actually connected and used + if {[get_collection_size $pll_extra_clk] > 0} { + set i_clk_cnt_num [expr {$i_extra_clk + $var(pll_num_of_reserved_cnts)}] + set name "core_extra_clk_${i_extra_clk}" + set master_core_clock $pins(pll_extra_clk_${i_extra_clk}) + set divide_by $var(pll_c${i_clk_cnt_num}_cnt) + set phase [expr { [lindex $var(PLL_C_CNT_PHASE_PS_STR_${i_clk_cnt_num}) 0] * 360.0 / $var(PHY_VCO_FREQ_PS) / $var(pll_c${i_clk_cnt_num}_cnt) } ] + set duty_cyc $var(PLL_C_CNT_DUTY_CYCLE_${i_clk_cnt_num}) + + set local_pll_extra_clock [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $master_core_clock \ + -name "${pins(master_instname)}_${name}" \ + -source $pins(master_vco_clock) \ + -multiply_by 1 \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cyc ] + } + } + } + + # Periphery clocks + set periphery_clocks [list] + set i_phy_clock 0 + foreach { phy_clock } $pins(pll_phy_clock) { + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(PHY_HMC_CLK_RATIO)}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_phy_clk_${i_phy_clock} [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $phy_clock \ + -name "${inst}_phy_clk_${i_phy_clock}" \ + -source [lindex $pins(pll_vco_clock) $i_phy_clock] \ + -multiply_by 1 \ + -divide_by $divide_by \ + -phase $phase ] + lappend periphery_clocks [set local_phy_clk_${i_phy_clock}] + incr i_phy_clock + } + + set i_phy_clock_l 0 + foreach { phy_clock_l } $pins(pll_phy_clock_l) { + set divide_by [expr {$var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) * $var(C2P_P2C_CLK_RATIO)}] + set phase [expr {$var(PLL_PHY_CLK_VCO_PHASE) * 45.0 / $divide_by}] + + set local_phy_clk_l_${i_phy_clock_l} [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target $phy_clock_l \ + -name "${inst}_phy_clk_l_${i_phy_clock_l}" \ + -source [lindex $pins(pll_vco_clock) $i_phy_clock_l] \ + -multiply_by 1 \ + -divide_by $divide_by \ + -phase $phase ] + lappend periphery_clocks [set local_phy_clk_l_${i_phy_clock_l}] + incr i_phy_clock_l + } + + # ------------------------ # + # - - # + # --- WRITE FIFO CLOCK --- # + # - - # + # ------------------------ # + + set write_fifo_clk [get_keepers ${inst}*|tile_gen[*].lane_gen[*].lane_inst|lane_inst~out_phy_reg] + + set i_wf_clock 0 + foreach_in_collection wf_clock $write_fifo_clk { + set vco_clock_id [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_vco_clk_id $wf_clock var] + if {$vco_clock_id == -1} { + post_message -type critical_warning "Failed to find VCO clock" + } else { + set local_wf_clk_${i_wf_clock} [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock \ + -target [get_node_info -name $wf_clock] \ + -name "${inst}_wf_clk_${i_wf_clock}" \ + -source [get_node_info -name $vco_clock_id] \ + -multiply_by 1 \ + -divide_by [expr $var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO)] \ + -phase 0 ] + } + incr i_wf_clock + } + + # ---------------- # + # - - # + # --- A/C PATH --- # + # - - # + # ---------------- # + + # Only during the Fitter do we need to have constraints to allow for auto-delay chain code to + # pick appropirate good settings + # Also, only need it if address/command is not calibrated + if {($fit_flow == 1) && ($var(CA_DESKEW) == 0)} { + + # First, define CK and CK#clocks because A/C timing is defined w.r.t. to these. + set master_ck_clock "" + foreach ac_clk_pin $pins(ac_clk) ac_clk_pin_n $pins(ac_clk_n) { + set master_ck_clock [get_fanins $ac_clk_pin] + foreach_in_collection check_pin $master_ck_clock { + set check_pin_name [get_node_info -name $check_pin] + if {[regexp {out_phy_reg$} $check_pin_name]} { + set master_ck_clock $check_pin_name + break + } + } + create_generated_clock -multiply_by 1 -source $master_ck_clock $ac_clk_pin -name $ac_clk_pin + create_generated_clock -multiply_by 1 -invert -source $master_ck_clock $ac_clk_pin_n -name $ac_clk_pin_n + } + + foreach { ac_clk_pin } $pins(ac_clk) { + # ac_pins can contain input ports such as mem_err_out_n + # Loop through each ac pin to make sure we only apply set_output_delay to output ports + foreach { ac_pin } $pins(ac_sync) { + set ac_port [ get_ports $ac_pin ] + if {[get_collection_size $ac_port] > 0} { + if [ get_port_info -is_output_port $ac_port ] { + # Specifies the minimum delay difference between the DQS pin and the address/control pins: + set_output_delay -min $ac_min_delay -clock [get_clocks $ac_clk_pin] $ac_port -add_delay + + # Specifies the maximum delay difference between the DQS pin and the address/control pins: + set_output_delay -max $ac_max_delay -clock [get_clocks $ac_clk_pin] $ac_port -add_delay + } + } + } + } + } else { + set_false_path -to $pins(ac_sync) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_sync) + } + + + # ----------------- # + # - - # + # --- READ PATH --- # + # - - # + # ----------------- # + + foreach { read_clock } $pins(rclk) { + create_clock -period "$var(PHY_MEM_CLK_FREQ_MHZ)MHz" -waveform [ list 0 $half_period ] $read_clock -name ${read_clock}_IN -add + } + + # ------------------------------ # + # - - # + # --- MULTICYCLE CONSTRAINTS --- # + # - - # + # ------------------------------ # + + if {!$var(IS_HPS)} { + + # Relax timing to the input of the synchronizer for the local_reset_req signal + # setup=7 and hold=6 are somewhat arbitrary choices + if {$is_master} { + set tmp "${inst}|arch|arch_inst|non_hps.core_clks_rsts_inst|local_reset_req_sync_gen_master.local_reset_req_sync_inst|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # Soft reset synchronizers + # See RTL for the justification of setup=7 and hold=6 + set tmp "${inst}|arch|arch_inst|non_hps.core_clks_rsts_inst|*reset_sync*" + set tmp_pin [get_pins -nowarn ${inst}|arch|arch_inst|non_hps.core_clks_rsts_inst|*reset_sync*|clrn] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # seq2core_reset_done comes out of the PHY at up to 666MHz. Needs to be treated as async with synchronizer in the core. + # setup=7 and hold=6 are somewhat arbitrary choices + set tmp "${inst}|arch|arch_inst|seq_if_inst|non_hps.seq2core_reset_done_sync_inst|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # ac_parity_err + # setup=7 and hold=6 are somewhat arbitrary choices + set tmp "${inst}|arch|arch_inst|seq_if_inst|non_hps.seq2core_ac_parity_sync_inst|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # afi_cal_in_progress (used by cal_counter module) + # setup=7 and hold=6 are somewhat arbitrary choices + set tmp "${inst}|arch|arch_inst|seq_if_inst|non_hps.afi_cal_in_progress_sync_inst|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # afi_cal_success + # setup=7 and hold=6 are somewhat arbitrary choices + set tmp "${inst}|arch|arch_inst|seq_if_inst|non_hps.afi_cal_success_sync_inst|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # afi_cal_fail + # setup=7 and hold=6 are somewhat arbitrary choices + set tmp "${inst}|arch|arch_inst|seq_if_inst|non_hps.afi_cal_fail_sync_inst|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # cal_counter synchronizer for global_reset_n_int + set tmp "${inst}|arch|arch_inst|cal_counter_inst|non_hps.inst_sync_reset_n|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + # cal_counter synchronizer for afi_cal_in_progress + set tmp "${inst}|arch|arch_inst|cal_counter_inst|non_hps.inst_sync_cal_in_progress|din_s1" + set tmp_pin [get_pins -nowarn [list "${tmp}|d" "${tmp}|*data"]] + set tmp_reg [get_registers -nowarn $tmp] + if {[get_collection_size $tmp_pin] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through $tmp_pin -to $tmp -setup 7 -end + set_multicycle_path -through $tmp_pin -to $tmp -hold 6 -end + } else { + set_false_path -through $tmp_pin -to $tmp_reg + } + } + + set tmp [get_pins -nowarn ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_core2ctl[6]] + if {[get_collection_size $tmp] > 0} { + set_multicycle_path -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst~hmc_reg0 -through $tmp -from [get_keepers *reset*] -setup 3 -end + set_multicycle_path -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst~hmc_reg0 -through $tmp -from [get_keepers *reset*] -hold 2 -end + } + + if {$var(PHY_USERMODE_OCT)} { + set tmp [get_pins -nowarn ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_ctl2core[19]] + if {[get_collection_size $tmp] > 0} { + set_multicycle_path -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst~hmc_reg0 -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_ctl2core[19] -to *gen_oct_cal_req.gen_oct_cal_req_no_hps.oct_cal_req_regs* -setup 4 -start + set_multicycle_path -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst~hmc_reg0 -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_ctl2core[19] -to *gen_oct_cal_req.gen_oct_cal_req_no_hps.oct_cal_req_regs* -hold 3 -start + } + + set tmp [get_pins -nowarn ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_core2ctl[7]] + if {[get_collection_size $tmp] > 0} { + set_multicycle_path -from ${inst}|arch|arch_inst|seq_if_inst|gen_oct_cal_rdy.gen_oct_cal_rdy_no_hps.oct_cal_rdy_regs|regs.sr_out* -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst~hmc_reg0 -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_core2ctl[7] -setup 4 -start + set_multicycle_path -from ${inst}|arch|arch_inst|seq_if_inst|gen_oct_cal_rdy.gen_oct_cal_rdy_no_hps.oct_cal_rdy_regs|regs.sr_out* -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst~hmc_reg0 -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].tile_ctrl_inst|afi_core2ctl[7] -hold 3 -start + } + } + + set ufi_wr [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*ufi_write_reg] + set ufi_rd [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*ufi_read_reg] + + if {([get_collection_size $ufi_wr] > 0) && ([get_collection_size $ufi_rd] > 0)} { + set_multicycle_path -from $ufi_wr -to $ufi_rd -setup 1 -end + set_multicycle_path -from $ufi_wr -to $ufi_rd -hold 1 -end + } + } + + if {$var(AMM_C2P_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*amm_c2p_ufi_i|*ufi_read_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -from $ufi_reg -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(AMM_P2C_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*amm_p2c_ufi_i|*ufi_write_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -to $ufi_reg -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(MMR_C2P_UFI_MODE)!= "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*mmr_c2p_ufi_i|*ufi_read_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -from $ufi_reg -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(MMR_P2C_UFI_MODE)!= "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*mmr_p2c_ufi_i|*ufi_write_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -to $ufi_reg -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(SEQ_C2P_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*seq_c2p_ufi_i|*ufi_read_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -from $ufi_reg -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*hmc_reg* -0.200 + } + } + if {$var(SEQ_P2C_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*seq_p2c_ufi_i|*ufi_write_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -to $ufi_reg -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*hmc_reg* -0.200 + } + } + if {$var(ECC_C2P_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*ecc_c2p_ufi_i|*ufi_read_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -from $ufi_reg -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(ECC_P2C_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*ecc_p2c_ufi_i|*ufi_write_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -to $ufi_reg -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(LANE_C2P_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*lane_c2p_ufi_i|*ufi_read_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -from $ufi_reg -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(LANE_P2C_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*lane_p2c_ufi_i|*ufi_write_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -to $ufi_reg -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(SIDEBAND_C2P_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*sideband_c2p_ufi_i|*ufi_read_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -from $ufi_reg -to ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + if {$var(SIDEBAND_P2C_UFI_MODE) != "pin_ufi_use_in_direct_out_direct"} { + set ufi_reg [get_keepers -nowarn ${inst}|arch|arch_inst|fm_ufis|*sideband_p2c_ufi_i|*ufi_write_reg] + if {[get_collection_size $ufi_reg] > 0} { + set_min_delay -to $ufi_reg -from ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|*phy_reg* -0.200 + } + } + + foreach periphery_clock $periphery_clocks { + set_clock_uncertainty -10ps -add -enable_same_physical_edge -hold -from [get_clocks $periphery_clock] -to [get_clocks $periphery_clock] + } + + if {!$var(IS_HPS)} { + set dll_reset [get_pins -nowarn ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst|core_dll[2]] + if {[get_collection_size $dll_reset] > 0} { + if {$fit_flow == 1} { + set_multicycle_path -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst|core_dll[2] -setup 8 -end + set_multicycle_path -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst|core_dll[2] -hold 7 -end + } else { + set_false_path -through ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst|core_dll[2] + } + } + } + + # ------------------------------ # + # - - # + # --- FALSE PATH CONSTRAINTS --- # + # - - # + # ------------------------------ # + + if {$var(C2C_TG_FALSE_PATH)} { + set_false_path -from tg|tg|* -to tg|tg|* + } + + + foreach ac_buf_path [concat $var(PATTERNS_AC_CLK) $var(PATTERNS_AC_SYNC) $var(PATTERNS_AC_ASYNC)] { + set length [string length $ac_buf_path] + set last_char [string range $ac_buf_path [expr $length -1] [expr $length -1]] + + if {[string equal $last_char "o"] == 1} { + + set word_idx [string first "cal_oct" $ac_buf_path] + if {$word_idx == -1 } { + set word_idx [string first "no_oct" $ac_buf_path] + set suffix "no_oct.obuf" + } else { + set suffix "cal_oct.obuf" + } + set sub_path [string range $ac_buf_path 0 [expr {$word_idx - 1}]] + + set buf_path ${inst}|${sub_path}${suffix} + set oe_path "${buf_path}|oe" + + set_false_path -through $oe_path + set_disable_timing -from oe -to o $buf_path + } + } + + + foreach ac_n_buf_path $var(PATTERNS_AC_CLK_N) { + set length [string length $ac_n_buf_path] + set last_char [string range $ac_n_buf_path [expr $length -1] [expr $length -1]] + + if {[string equal $last_char "o"] == 1} { + + set word_idx [string first "cal_oct" $ac_n_buf_path] + if {$word_idx == -1 } { + set word_idx [string first "no_oct" $ac_n_buf_path] + set suffix "no_oct.obuf_bar" + } else { + set suffix "cal_oct.obuf_bar" + } + set sub_path [string range $ac_n_buf_path 0 [expr {$word_idx - 1}]] + + set buf_path ${inst}|${sub_path}${suffix} + set oe_path "${buf_path}|oe" + + set_false_path -through $oe_path + set_disable_timing -from oe -to o $buf_path + } + } + + + foreach dqdqs_buf_path [concat $var(PATTERNS_WCLK) $var(PATTERNS_WDATA) $var(PATTERNS_DBI) $var(PATTERNS_DM)] { + set length [string length $dqdqs_buf_path] + set last_char [string range $dqdqs_buf_path [expr $length -1] [expr $length -1]] + + if {[string equal $last_char "o"] == 1} { + set word_idx [string first "cal_oct" $dqdqs_buf_path] + set suffix "cal_oct.obuf" + + set sub_path [string range $dqdqs_buf_path 0 [expr {$word_idx - 1}]] + set buf_path ${inst}|${sub_path}${suffix} + set oe_path "${buf_path}|oe" + set_false_path -through $oe_path + set_disable_timing -from oe -to o $buf_path + } + } + + foreach dqdqs_buf_path $var(PATTERNS_WCLK_N) { + set length [string length $dqdqs_buf_path] + set last_char [string range $dqdqs_buf_path [expr $length -1] [expr $length -1]] + + if {[string equal $last_char "o"] == 1} { + set word_idx [string first "cal_oct" $dqdqs_buf_path] + set suffix "cal_oct.obuf_bar" + + set sub_path [string range $dqdqs_buf_path 0 [expr {$word_idx - 1}]] + set buf_path ${inst}|${sub_path}${suffix} + set oe_path "${buf_path}|oe" + set_false_path -through $oe_path + set_disable_timing -from oe -to o $buf_path + } + } + + # DQ/DQS pins are calibrated + set_false_path -to $pins(wdata) + set_false_path -from $pins(rdata) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(wdata) + set_input_delay -clock $pins(ref_clock_name) 0 $pins(rdata) + if {[llength $pins(dm)] > 0} { + set_false_path -to $pins(dm) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(dm) + } + if {[llength $pins(dbi)] > 0} { + set_false_path -to $pins(dbi) + set_false_path -from $pins(dbi) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(dbi) + set_input_delay -clock $pins(ref_clock_name) 0 $pins(dbi) + } + set_false_path -to $pins(wclk) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk) + if {[llength $pins(wclk_n)] > 0} { + set_false_path -to $pins(wclk_n) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk_n) + } + set_false_path -from $pins(rclk) + if {[llength $pins(rclk_n)] > 0} { + set_false_path -from $pins(rclk_n) + } + if {[llength $pins(ac_clk)] > 0} { + set_false_path -to $pins(ac_clk) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_clk) -add + } + if {[llength $pins(ac_clk_n)] > 0} { + set_false_path -to $pins(ac_clk_n) + set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_clk_n) -add + } + + if {[llength $pins(ac_async)] > 0} { + set_false_path -to $pins(ac_async) + set_false_path -from $pins(ac_async) + foreach ac_async $pins(ac_async) { + if {[get_port_info -is_input $ac_async] || [get_port_info -is_inout $ac_async]} { + set_input_delay -clock $pins(ref_clock_name) 0 $ac_async + } + if {[get_port_info -is_output $ac_async] || [get_port_info -is_inout $ac_async]} { + set_output_delay -clock $pins(ref_clock_name) 0 $ac_async + } + } + } + + if {!$var(IS_HPS)} { + set tmp_pins_0 [get_pins -nowarn ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst|core2dbc_rd_data_rdy] + set tmp_pins_1 [get_pins -nowarn ${inst}|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst|dbc2core_rd_data_vld0] + if {[get_collection_size $tmp_pins_0] > 0 && [get_collection_size $tmp_pins_1] > 0} { + set_false_path -through $tmp_pins_0 -through $tmp_pins_1 + } + } + + # ------------------------- # + # - - # + # --- CLOCK UNCERTAINTY --- # + # - - # + # ------------------------- # + + if {!$var(IS_HPS) && ($fit_flow == 1 || $sta_flow == 1)} { + + ################################# + # C2P/P2C transfers + ################################# + + # Get P2C / C2P Multi-tile clock uncertainty + set p2c_c2p_multi_tile_clock_uncertainty [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_p2c_c2p_clock_uncertainty $inst var] + + # Get extra periphery clock uncertainty + set periphery_clock_uncertainty [list] + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_periphery_clock_uncertainty periphery_clock_uncertainty var + + # Get Fitter overconstraints + if {$fit_flow == 1} { + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_periphery_overconstraints periphery_overconstraints_st periphery_overconstraints_mt var + } else { + set periphery_overconstraints_st [list 0.0 0.0 0.0 0.0] + set periphery_overconstraints_mt [list 0.0 0.0 0.0 0.0] + } + + # Now loop over core/periphery clocks and set clock uncertainty + set i_core_clock 0 + foreach core_clock $core_clocks { + if {$core_clock != ""} { + + set local_core_clock [lindex $core_clocks_local $i_core_clock] + + if {$core_clock == $pins(master_core_usr_clock_sec) || $core_clock == $pins(master_core_usr_half_clock_sec)} { + set same_tile_index $i_cpa_clock_tile_sec + } else { + set same_tile_index $i_cpa_clock_tile_pri + } + + set i_phy_clock 0 + foreach { phy_clock } $pins(pll_phy_clock_l) { + + if {$i_phy_clock != $same_tile_index} { + # C2P/P2C where the periphery tile != CPA tile. + # For these transfers the SDC explicitly overrides the clock uncertainty values. + # Therefore, when overconstraining we must not use the "-add" option. + set add_to_derived "" + set c2p_su [expr {$p2c_c2p_multi_tile_clock_uncertainty + [lindex $periphery_overconstraints_mt 0] + [lindex $periphery_clock_uncertainty 0]}] + set c2p_h [expr {$p2c_c2p_multi_tile_clock_uncertainty + [lindex $periphery_overconstraints_mt 1] + [lindex $periphery_clock_uncertainty 1]}] + set p2c_su [expr {$p2c_c2p_multi_tile_clock_uncertainty + [lindex $periphery_overconstraints_mt 2] + [lindex $periphery_clock_uncertainty 2]}] + set p2c_h [expr {$p2c_c2p_multi_tile_clock_uncertainty + [lindex $periphery_overconstraints_mt 3] + [lindex $periphery_clock_uncertainty 3]}] + } else { + # C2P/P2C where the periphery tile == CPA tile + # For these transfers it is safe to use the -add option since we rely on + # derive_clock_uncertainty for the base value. + set add_to_derived "-add" + set c2p_su [expr [lindex $periphery_overconstraints_st 0] + [lindex $periphery_clock_uncertainty 0]] + set c2p_h [expr [lindex $periphery_overconstraints_st 1] + [lindex $periphery_clock_uncertainty 1]] + set p2c_su [expr [lindex $periphery_overconstraints_st 2] + [lindex $periphery_clock_uncertainty 2]] + set p2c_h [expr [lindex $periphery_overconstraints_st 3] + [lindex $periphery_clock_uncertainty 3]] + } + + set catch_exception [catch {set local_phy_clk_l_${i_phy_clock}} result] + if {$catch_exception == 0} { + set_clock_uncertainty -from [get_clocks $local_core_clock] -to [get_clocks [set local_phy_clk_l_${i_phy_clock}]] -suppress_warnings -setup {*}$add_to_derived $c2p_su + set_clock_uncertainty -from [get_clocks $local_core_clock] -to [get_clocks [set local_phy_clk_l_${i_phy_clock}]] -suppress_warnings -hold {*}$add_to_derived $c2p_h + set_clock_uncertainty -to [get_clocks $local_core_clock] -from [get_clocks [set local_phy_clk_l_${i_phy_clock}]] -suppress_warnings -setup {*}$add_to_derived $p2c_su + set_clock_uncertainty -to [get_clocks $local_core_clock] -from [get_clocks [set local_phy_clk_l_${i_phy_clock}]] -suppress_warnings -hold {*}$add_to_derived $p2c_h + + if {$sta_flow == 1 && $var(CUT_C2P_P2C_PATHS)} { + set_false_path -to [get_clocks [set local_phy_clk_l_${i_phy_clock}]] + set_false_path -from [get_clocks [set local_phy_clk_l_${i_phy_clock}]] + } + } + + set catch_exception [catch {set local_phy_clk_${i_phy_clock}} result] + if {$catch_exception == 0} { + set_clock_uncertainty -from [get_clocks $local_core_clock] -to [get_clocks [set local_phy_clk_${i_phy_clock}]] -suppress_warnings -setup {*}$add_to_derived $c2p_su + set_clock_uncertainty -from [get_clocks $local_core_clock] -to [get_clocks [set local_phy_clk_${i_phy_clock}]] -suppress_warnings -hold {*}$add_to_derived $c2p_h + set_clock_uncertainty -to [get_clocks $local_core_clock] -from [get_clocks [set local_phy_clk_${i_phy_clock}]] -suppress_warnings -setup {*}$add_to_derived $p2c_su + set_clock_uncertainty -to [get_clocks $local_core_clock] -from [get_clocks [set local_phy_clk_${i_phy_clock}]] -suppress_warnings -hold {*}$add_to_derived $p2c_h + + if {$sta_flow == 1 && $var(CUT_C2P_P2C_PATHS) } { + set_false_path -to [get_clocks [set local_phy_clk_${i_phy_clock}]] + set_false_path -from [get_clocks [set local_phy_clk_${i_phy_clock}]] + } + + } + + incr i_phy_clock + } + } + incr i_core_clock + } + + ################################# + # Within-core transfers + ################################# + + # Get extra core clock uncertainty + set core_clock_uncertainty [list] + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_clock_uncertainty core_clock_uncertainty var + + # Get Fitter overconstraints + if {$fit_flow == 1} { + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_overconstraints core_overconstraints var + } else { + set core_overconstraints [list 0.0 0.0 0.0 0.0] + } + + set c2c_same_su [expr [lindex $core_overconstraints 0] + [lindex $core_clock_uncertainty 0]] + set c2c_same_h [expr [lindex $core_overconstraints 1] + [lindex $core_clock_uncertainty 1]] + set c2c_diff_su [expr [lindex $core_overconstraints 2] + [lindex $core_clock_uncertainty 2]] + set c2c_diff_h [expr [lindex $core_overconstraints 3] + [lindex $core_clock_uncertainty 3]] + + # For these transfers it is safe to use the -add option of set_clock_uncertainty since + # we rely on derive_clock_uncertainty for the base value. + foreach src_core_clock_local $core_clocks_local { + if {$src_core_clock_local != ""} { + foreach dst_core_clock_local $core_clocks_local { + if {$dst_core_clock_local != ""} { + if {$src_core_clock_local == $dst_core_clock_local} { + # Same clock network transfers + set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -setup -add $c2c_same_su + set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -hold -enable_same_physical_edge -add $c2c_same_h + } else { + # Transfers between different core clock networks + set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -setup -add $c2c_diff_su + set_clock_uncertainty -from $src_core_clock_local -to $dst_core_clock_local -hold -add $c2c_diff_h + } + } + } + } + } + + } + + # --------------------- # + # - - # + # --- ACTIVE CLOCKS --- # + # - - # + # --------------------- # + + if {(($::quartus(nameofexecutable) ne "quartus_fit") && ($::quartus(nameofexecutable) ne "quartus_map"))} { + + if {$var(C2P_P2C_PR) && [llength $periphery_clocks] > 0 && !$debug} { + post_sdc_message info "Setting periphery clocks as inactive; use Report DDR to timing analyze periphery clocks" + set_active_clocks [remove_from_collection [get_active_clocks] [get_clocks $periphery_clocks]] + } + } +} + +# -------------------------- # +# - - # +# --- REPORT DDR COMMAND --- # +# - - # +# -------------------------- # + +add_ddr_report_command "source [list [file join [file dirname [info script]] ${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename}_report_timing.tcl]]" + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sv new file mode 100644 index 0000000000..1292804d6e --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sv @@ -0,0 +1,4093 @@ +module ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy #( + parameter PROTOCOL_ENUM = "", + parameter PHY_TARGET_IS_ES = 0, + parameter PHY_TARGET_IS_ES2 = 0, + parameter PHY_TARGET_IS_PRODUCTION = 0, + parameter PHY_CONFIG_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter PHY_CALIBRATED_OCT = 0, + parameter PHY_AC_CALIBRATED_OCT = 0, + parameter PHY_CK_CALIBRATED_OCT = 0, + parameter PHY_DATA_CALIBRATED_OCT = 0, + parameter PHY_MIMIC_HPS_EMIF = 0, + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter MEM_FORMAT_ENUM = "", + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 0, + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + parameter DIAG_SIM_REGTEST_MODE = 0, + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_SEQ_RESET_AUTO_RELEASE = "", + parameter DIAG_DB_RESET_AUTO_RELEASE = "", + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_SIM_VERBOSE_LEVEL = 0, + parameter DIAG_FAST_SIM = 0, + parameter SILICON_REV = "", + parameter IS_HPS = 0, + parameter USER_CLK_RATIO = 0, + parameter C2P_P2C_CLK_RATIO = 0, + parameter PHY_HMC_CLK_RATIO = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 0, + parameter DIAG_ABSTRACT_PHY_RLAT = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter AC_PIN_MAP_SCHEME = "", + parameter NUM_OF_HMC_PORTS = 0, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_READY_LATENCY = 0, + parameter HMC_CTRL_DIMM_TYPE = "", + parameter SEQ_PT_SYN_CONTENT = "", + parameter SEQ_PT_SIM_CONTENT = "", + parameter REGISTER_AFI_C2P = 0, + parameter REGISTER_AFI_P2C = 0, + parameter REGISTER_AMM_P2C = 0, + parameter REGISTER_AMM_C2P = 0, + parameter NUM_OF_RTL_TILES = 0, + parameter PRI_RDATA_TILE_INDEX = 0, + parameter PRI_RDATA_LANE_INDEX = 0, + parameter PRI_WDATA_TILE_INDEX = 0, + parameter PRI_WDATA_LANE_INDEX = 0, + parameter PRI_AC_TILE_INDEX = 0, + parameter SEC_RDATA_TILE_INDEX = 0, + parameter SEC_RDATA_LANE_INDEX = 0, + parameter SEC_WDATA_TILE_INDEX = 0, + parameter SEC_WDATA_LANE_INDEX = 0, + parameter SEC_AC_TILE_INDEX = 0, + parameter LANES_USAGE_0 = 0, + parameter LANES_USAGE_1 = 0, + parameter LANES_USAGE_2 = 0, + parameter LANES_USAGE_3 = 0, + parameter LANES_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_USAGE_0 = 0, + parameter PINS_USAGE_1 = 0, + parameter PINS_USAGE_2 = 0, + parameter PINS_USAGE_3 = 0, + parameter PINS_USAGE_4 = 0, + parameter PINS_USAGE_5 = 0, + parameter PINS_USAGE_6 = 0, + parameter PINS_USAGE_7 = 0, + parameter PINS_USAGE_8 = 0, + parameter PINS_USAGE_9 = 0, + parameter PINS_USAGE_10 = 0, + parameter PINS_USAGE_11 = 0, + parameter PINS_USAGE_12 = 0, + parameter PINS_USAGE_AUTOGEN_WCNT = 0, + parameter LANE_PIN_USAGE_0 = 0, + parameter LANE_PIN_USAGE_1 = 0, + parameter LANE_PIN_USAGE_2 = 0, + parameter LANE_PIN_USAGE_3 = 0, + parameter LANE_PIN_USAGE_4 = 0, + parameter LANE_PIN_USAGE_5 = 0, + parameter LANE_PIN_USAGE_6 = 0, + parameter LANE_PIN_USAGE_7 = 0, + parameter LANE_PIN_USAGE_8 = 0, + parameter LANE_PIN_USAGE_9 = 0, + parameter LANE_PIN_USAGE_10 = 0, + parameter LANE_PIN_USAGE_11 = 0, + parameter LANE_PIN_USAGE_12 = 0, + parameter LANE_PIN_USAGE_13 = 0, + parameter LANE_PIN_USAGE_14 = 0, + parameter LANE_PIN_USAGE_15 = 0, + parameter LANE_PIN_USAGE_16 = 0, + parameter LANE_PIN_USAGE_17 = 0, + parameter LANE_PIN_USAGE_18 = 0, + parameter LANE_PIN_USAGE_19 = 0, + parameter LANE_PIN_USAGE_20 = 0, + parameter LANE_PIN_USAGE_21 = 0, + parameter LANE_PIN_USAGE_22 = 0, + parameter LANE_PIN_USAGE_23 = 0, + parameter LANE_PIN_USAGE_24 = 0, + parameter LANE_PIN_USAGE_25 = 0, + parameter LANE_PIN_USAGE_26 = 0, + parameter LANE_PIN_USAGE_27 = 0, + parameter LANE_PIN_USAGE_28 = 0, + parameter LANE_PIN_USAGE_29 = 0, + parameter LANE_PIN_USAGE_30 = 0, + parameter LANE_PIN_USAGE_31 = 0, + parameter LANE_PIN_USAGE_32 = 0, + parameter LANE_PIN_USAGE_33 = 0, + parameter LANE_PIN_USAGE_34 = 0, + parameter LANE_PIN_USAGE_35 = 0, + parameter LANE_PIN_USAGE_36 = 0, + parameter LANE_PIN_USAGE_37 = 0, + parameter LANE_PIN_USAGE_38 = 0, + parameter LANE_PIN_USAGE_39 = 0, + parameter LANE_PIN_USAGE_40 = 0, + parameter LANE_PIN_USAGE_41 = 0, + parameter LANE_PIN_USAGE_42 = 0, + parameter LANE_PIN_USAGE_43 = 0, + parameter LANE_PIN_USAGE_44 = 0, + parameter LANE_PIN_USAGE_45 = 0, + parameter LANE_PIN_USAGE_46 = 0, + parameter LANE_PIN_USAGE_47 = 0, + parameter LANE_PIN_USAGE_48 = 0, + parameter LANE_PIN_USAGE_49 = 0, + parameter LANE_PIN_USAGE_50 = 0, + parameter LANE_PIN_USAGE_51 = 0, + parameter LANE_PIN_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_RATE_0 = 0, + parameter PINS_RATE_1 = 0, + parameter PINS_RATE_2 = 0, + parameter PINS_RATE_3 = 0, + parameter PINS_RATE_4 = 0, + parameter PINS_RATE_5 = 0, + parameter PINS_RATE_6 = 0, + parameter PINS_RATE_7 = 0, + parameter PINS_RATE_8 = 0, + parameter PINS_RATE_9 = 0, + parameter PINS_RATE_10 = 0, + parameter PINS_RATE_11 = 0, + parameter PINS_RATE_12 = 0, + parameter PINS_RATE_AUTOGEN_WCNT = 0, + parameter DB_PINS_PROC_MODE_0 = 0, + parameter DB_PINS_PROC_MODE_1 = 0, + parameter DB_PINS_PROC_MODE_2 = 0, + parameter DB_PINS_PROC_MODE_3 = 0, + parameter DB_PINS_PROC_MODE_4 = 0, + parameter DB_PINS_PROC_MODE_5 = 0, + parameter DB_PINS_PROC_MODE_6 = 0, + parameter DB_PINS_PROC_MODE_7 = 0, + parameter DB_PINS_PROC_MODE_8 = 0, + parameter DB_PINS_PROC_MODE_9 = 0, + parameter DB_PINS_PROC_MODE_10 = 0, + parameter DB_PINS_PROC_MODE_11 = 0, + parameter DB_PINS_PROC_MODE_12 = 0, + parameter DB_PINS_PROC_MODE_13 = 0, + parameter DB_PINS_PROC_MODE_14 = 0, + parameter DB_PINS_PROC_MODE_15 = 0, + parameter DB_PINS_PROC_MODE_16 = 0, + parameter DB_PINS_PROC_MODE_17 = 0, + parameter DB_PINS_PROC_MODE_18 = 0, + parameter DB_PINS_PROC_MODE_19 = 0, + parameter DB_PINS_PROC_MODE_20 = 0, + parameter DB_PINS_PROC_MODE_21 = 0, + parameter DB_PINS_PROC_MODE_22 = 0, + parameter DB_PINS_PROC_MODE_23 = 0, + parameter DB_PINS_PROC_MODE_24 = 0, + parameter DB_PINS_PROC_MODE_25 = 0, + parameter DB_PINS_PROC_MODE_26 = 0, + parameter DB_PINS_PROC_MODE_27 = 0, + parameter DB_PINS_PROC_MODE_28 = 0, + parameter DB_PINS_PROC_MODE_29 = 0, + parameter DB_PINS_PROC_MODE_30 = 0, + parameter DB_PINS_PROC_MODE_31 = 0, + parameter DB_PINS_PROC_MODE_32 = 0, + parameter DB_PINS_PROC_MODE_33 = 0, + parameter DB_PINS_PROC_MODE_34 = 0, + parameter DB_PINS_PROC_MODE_35 = 0, + parameter DB_PINS_PROC_MODE_36 = 0, + parameter DB_PINS_PROC_MODE_37 = 0, + parameter DB_PINS_PROC_MODE_38 = 0, + parameter DB_PINS_PROC_MODE_39 = 0, + parameter DB_PINS_PROC_MODE_40 = 0, + parameter DB_PINS_PROC_MODE_41 = 0, + parameter DB_PINS_PROC_MODE_42 = 0, + parameter DB_PINS_PROC_MODE_43 = 0, + parameter DB_PINS_PROC_MODE_44 = 0, + parameter DB_PINS_PROC_MODE_45 = 0, + parameter DB_PINS_PROC_MODE_46 = 0, + parameter DB_PINS_PROC_MODE_47 = 0, + parameter DB_PINS_PROC_MODE_48 = 0, + parameter DB_PINS_PROC_MODE_49 = 0, + parameter DB_PINS_PROC_MODE_50 = 0, + parameter DB_PINS_PROC_MODE_51 = 0, + parameter DB_PINS_PROC_MODE_52 = 0, + parameter DB_PINS_PROC_MODE_53 = 0, + parameter DB_PINS_PROC_MODE_54 = 0, + parameter DB_PINS_PROC_MODE_55 = 0, + parameter DB_PINS_PROC_MODE_56 = 0, + parameter DB_PINS_PROC_MODE_57 = 0, + parameter DB_PINS_PROC_MODE_58 = 0, + parameter DB_PINS_PROC_MODE_59 = 0, + parameter DB_PINS_PROC_MODE_60 = 0, + parameter DB_PINS_PROC_MODE_61 = 0, + parameter DB_PINS_PROC_MODE_62 = 0, + parameter DB_PINS_PROC_MODE_63 = 0, + parameter DB_PINS_PROC_MODE_AUTOGEN_WCNT = 0, + parameter PINS_DATA_IN_MODE_0 = 0, + parameter PINS_DATA_IN_MODE_1 = 0, + parameter PINS_DATA_IN_MODE_2 = 0, + parameter PINS_DATA_IN_MODE_3 = 0, + parameter PINS_DATA_IN_MODE_4 = 0, + parameter PINS_DATA_IN_MODE_5 = 0, + parameter PINS_DATA_IN_MODE_6 = 0, + parameter PINS_DATA_IN_MODE_7 = 0, + parameter PINS_DATA_IN_MODE_8 = 0, + parameter PINS_DATA_IN_MODE_9 = 0, + parameter PINS_DATA_IN_MODE_10 = 0, + parameter PINS_DATA_IN_MODE_11 = 0, + parameter PINS_DATA_IN_MODE_12 = 0, + parameter PINS_DATA_IN_MODE_13 = 0, + parameter PINS_DATA_IN_MODE_14 = 0, + parameter PINS_DATA_IN_MODE_15 = 0, + parameter PINS_DATA_IN_MODE_16 = 0, + parameter PINS_DATA_IN_MODE_17 = 0, + parameter PINS_DATA_IN_MODE_18 = 0, + parameter PINS_DATA_IN_MODE_19 = 0, + parameter PINS_DATA_IN_MODE_20 = 0, + parameter PINS_DATA_IN_MODE_21 = 0, + parameter PINS_DATA_IN_MODE_22 = 0, + parameter PINS_DATA_IN_MODE_23 = 0, + parameter PINS_DATA_IN_MODE_24 = 0, + parameter PINS_DATA_IN_MODE_25 = 0, + parameter PINS_DATA_IN_MODE_26 = 0, + parameter PINS_DATA_IN_MODE_27 = 0, + parameter PINS_DATA_IN_MODE_28 = 0, + parameter PINS_DATA_IN_MODE_29 = 0, + parameter PINS_DATA_IN_MODE_30 = 0, + parameter PINS_DATA_IN_MODE_31 = 0, + parameter PINS_DATA_IN_MODE_32 = 0, + parameter PINS_DATA_IN_MODE_33 = 0, + parameter PINS_DATA_IN_MODE_34 = 0, + parameter PINS_DATA_IN_MODE_35 = 0, + parameter PINS_DATA_IN_MODE_36 = 0, + parameter PINS_DATA_IN_MODE_37 = 0, + parameter PINS_DATA_IN_MODE_38 = 0, + parameter PINS_DATA_IN_MODE_AUTOGEN_WCNT = 0, + parameter PINS_C2L_DRIVEN_0 = 0, + parameter PINS_C2L_DRIVEN_1 = 0, + parameter PINS_C2L_DRIVEN_2 = 0, + parameter PINS_C2L_DRIVEN_3 = 0, + parameter PINS_C2L_DRIVEN_4 = 0, + parameter PINS_C2L_DRIVEN_5 = 0, + parameter PINS_C2L_DRIVEN_6 = 0, + parameter PINS_C2L_DRIVEN_7 = 0, + parameter PINS_C2L_DRIVEN_8 = 0, + parameter PINS_C2L_DRIVEN_9 = 0, + parameter PINS_C2L_DRIVEN_10 = 0, + parameter PINS_C2L_DRIVEN_11 = 0, + parameter PINS_C2L_DRIVEN_12 = 0, + parameter PINS_C2L_DRIVEN_AUTOGEN_WCNT = 0, + parameter PINS_OCT_MODE_0 = 0, + parameter PINS_OCT_MODE_1 = 0, + parameter PINS_OCT_MODE_2 = 0, + parameter PINS_OCT_MODE_3 = 0, + parameter PINS_OCT_MODE_4 = 0, + parameter PINS_OCT_MODE_5 = 0, + parameter PINS_OCT_MODE_6 = 0, + parameter PINS_OCT_MODE_7 = 0, + parameter PINS_OCT_MODE_8 = 0, + parameter PINS_OCT_MODE_9 = 0, + parameter PINS_OCT_MODE_10 = 0, + parameter PINS_OCT_MODE_11 = 0, + parameter PINS_OCT_MODE_12 = 0, + parameter PINS_OCT_MODE_AUTOGEN_WCNT = 0, + parameter PINS_DCC_SPLIT_0 = 0, + parameter PINS_DCC_SPLIT_1 = 0, + parameter PINS_DCC_SPLIT_2 = 0, + parameter PINS_DCC_SPLIT_3 = 0, + parameter PINS_DCC_SPLIT_4 = 0, + parameter PINS_DCC_SPLIT_5 = 0, + parameter PINS_DCC_SPLIT_6 = 0, + parameter PINS_DCC_SPLIT_7 = 0, + parameter PINS_DCC_SPLIT_8 = 0, + parameter PINS_DCC_SPLIT_9 = 0, + parameter PINS_DCC_SPLIT_10 = 0, + parameter PINS_DCC_SPLIT_11 = 0, + parameter PINS_DCC_SPLIT_12 = 0, + parameter PINS_DCC_SPLIT_AUTOGEN_WCNT = 0, + parameter UNUSED_MEM_PINS_PINLOC_0 = 0, + parameter UNUSED_MEM_PINS_PINLOC_1 = 0, + parameter UNUSED_MEM_PINS_PINLOC_2 = 0, + parameter UNUSED_MEM_PINS_PINLOC_3 = 0, + parameter UNUSED_MEM_PINS_PINLOC_4 = 0, + parameter UNUSED_MEM_PINS_PINLOC_5 = 0, + parameter UNUSED_MEM_PINS_PINLOC_6 = 0, + parameter UNUSED_MEM_PINS_PINLOC_7 = 0, + parameter UNUSED_MEM_PINS_PINLOC_8 = 0, + parameter UNUSED_MEM_PINS_PINLOC_9 = 0, + parameter UNUSED_MEM_PINS_PINLOC_10 = 0, + parameter UNUSED_MEM_PINS_PINLOC_11 = 0, + parameter UNUSED_MEM_PINS_PINLOC_12 = 0, + parameter UNUSED_MEM_PINS_PINLOC_13 = 0, + parameter UNUSED_MEM_PINS_PINLOC_14 = 0, + parameter UNUSED_MEM_PINS_PINLOC_15 = 0, + parameter UNUSED_MEM_PINS_PINLOC_16 = 0, + parameter UNUSED_MEM_PINS_PINLOC_17 = 0, + parameter UNUSED_MEM_PINS_PINLOC_18 = 0, + parameter UNUSED_MEM_PINS_PINLOC_19 = 0, + parameter UNUSED_MEM_PINS_PINLOC_20 = 0, + parameter UNUSED_MEM_PINS_PINLOC_21 = 0, + parameter UNUSED_MEM_PINS_PINLOC_22 = 0, + parameter UNUSED_MEM_PINS_PINLOC_23 = 0, + parameter UNUSED_MEM_PINS_PINLOC_24 = 0, + parameter UNUSED_MEM_PINS_PINLOC_25 = 0, + parameter UNUSED_MEM_PINS_PINLOC_26 = 0, + parameter UNUSED_MEM_PINS_PINLOC_27 = 0, + parameter UNUSED_MEM_PINS_PINLOC_28 = 0, + parameter UNUSED_MEM_PINS_PINLOC_29 = 0, + parameter UNUSED_MEM_PINS_PINLOC_30 = 0, + parameter UNUSED_MEM_PINS_PINLOC_31 = 0, + parameter UNUSED_MEM_PINS_PINLOC_32 = 0, + parameter UNUSED_MEM_PINS_PINLOC_33 = 0, + parameter UNUSED_MEM_PINS_PINLOC_34 = 0, + parameter UNUSED_MEM_PINS_PINLOC_35 = 0, + parameter UNUSED_MEM_PINS_PINLOC_36 = 0, + parameter UNUSED_MEM_PINS_PINLOC_37 = 0, + parameter UNUSED_MEM_PINS_PINLOC_38 = 0, + parameter UNUSED_MEM_PINS_PINLOC_39 = 0, + parameter UNUSED_MEM_PINS_PINLOC_40 = 0, + parameter UNUSED_MEM_PINS_PINLOC_41 = 0, + parameter UNUSED_MEM_PINS_PINLOC_42 = 0, + parameter UNUSED_MEM_PINS_PINLOC_43 = 0, + parameter UNUSED_MEM_PINS_PINLOC_44 = 0, + parameter UNUSED_MEM_PINS_PINLOC_45 = 0, + parameter UNUSED_MEM_PINS_PINLOC_46 = 0, + parameter UNUSED_MEM_PINS_PINLOC_47 = 0, + parameter UNUSED_MEM_PINS_PINLOC_48 = 0, + parameter UNUSED_MEM_PINS_PINLOC_49 = 0, + parameter UNUSED_MEM_PINS_PINLOC_50 = 0, + parameter UNUSED_MEM_PINS_PINLOC_51 = 0, + parameter UNUSED_MEM_PINS_PINLOC_52 = 0, + parameter UNUSED_MEM_PINS_PINLOC_53 = 0, + parameter UNUSED_MEM_PINS_PINLOC_54 = 0, + parameter UNUSED_MEM_PINS_PINLOC_55 = 0, + parameter UNUSED_MEM_PINS_PINLOC_56 = 0, + parameter UNUSED_MEM_PINS_PINLOC_57 = 0, + parameter UNUSED_MEM_PINS_PINLOC_58 = 0, + parameter UNUSED_MEM_PINS_PINLOC_59 = 0, + parameter UNUSED_MEM_PINS_PINLOC_60 = 0, + parameter UNUSED_MEM_PINS_PINLOC_61 = 0, + parameter UNUSED_MEM_PINS_PINLOC_62 = 0, + parameter UNUSED_MEM_PINS_PINLOC_63 = 0, + parameter UNUSED_MEM_PINS_PINLOC_64 = 0, + parameter UNUSED_MEM_PINS_PINLOC_65 = 0, + parameter UNUSED_MEM_PINS_PINLOC_66 = 0, + parameter UNUSED_MEM_PINS_PINLOC_67 = 0, + parameter UNUSED_MEM_PINS_PINLOC_68 = 0, + parameter UNUSED_MEM_PINS_PINLOC_69 = 0, + parameter UNUSED_MEM_PINS_PINLOC_70 = 0, + parameter UNUSED_MEM_PINS_PINLOC_71 = 0, + parameter UNUSED_MEM_PINS_PINLOC_72 = 0, + parameter UNUSED_MEM_PINS_PINLOC_73 = 0, + parameter UNUSED_MEM_PINS_PINLOC_74 = 0, + parameter UNUSED_MEM_PINS_PINLOC_75 = 0, + parameter UNUSED_MEM_PINS_PINLOC_76 = 0, + parameter UNUSED_MEM_PINS_PINLOC_77 = 0, + parameter UNUSED_MEM_PINS_PINLOC_78 = 0, + parameter UNUSED_MEM_PINS_PINLOC_79 = 0, + parameter UNUSED_MEM_PINS_PINLOC_80 = 0, + parameter UNUSED_MEM_PINS_PINLOC_81 = 0, + parameter UNUSED_MEM_PINS_PINLOC_82 = 0, + parameter UNUSED_MEM_PINS_PINLOC_83 = 0, + parameter UNUSED_MEM_PINS_PINLOC_84 = 0, + parameter UNUSED_MEM_PINS_PINLOC_85 = 0, + parameter UNUSED_MEM_PINS_PINLOC_86 = 0, + parameter UNUSED_MEM_PINS_PINLOC_87 = 0, + parameter UNUSED_MEM_PINS_PINLOC_88 = 0, + parameter UNUSED_MEM_PINS_PINLOC_89 = 0, + parameter UNUSED_MEM_PINS_PINLOC_90 = 0, + parameter UNUSED_MEM_PINS_PINLOC_91 = 0, + parameter UNUSED_MEM_PINS_PINLOC_92 = 0, + parameter UNUSED_MEM_PINS_PINLOC_93 = 0, + parameter UNUSED_MEM_PINS_PINLOC_94 = 0, + parameter UNUSED_MEM_PINS_PINLOC_95 = 0, + parameter UNUSED_MEM_PINS_PINLOC_96 = 0, + parameter UNUSED_MEM_PINS_PINLOC_97 = 0, + parameter UNUSED_MEM_PINS_PINLOC_98 = 0, + parameter UNUSED_MEM_PINS_PINLOC_99 = 0, + parameter UNUSED_MEM_PINS_PINLOC_100 = 0, + parameter UNUSED_MEM_PINS_PINLOC_101 = 0, + parameter UNUSED_MEM_PINS_PINLOC_102 = 0, + parameter UNUSED_MEM_PINS_PINLOC_103 = 0, + parameter UNUSED_MEM_PINS_PINLOC_104 = 0, + parameter UNUSED_MEM_PINS_PINLOC_105 = 0, + parameter UNUSED_MEM_PINS_PINLOC_106 = 0, + parameter UNUSED_MEM_PINS_PINLOC_107 = 0, + parameter UNUSED_MEM_PINS_PINLOC_108 = 0, + parameter UNUSED_MEM_PINS_PINLOC_109 = 0, + parameter UNUSED_MEM_PINS_PINLOC_110 = 0, + parameter UNUSED_MEM_PINS_PINLOC_111 = 0, + parameter UNUSED_MEM_PINS_PINLOC_112 = 0, + parameter UNUSED_MEM_PINS_PINLOC_113 = 0, + parameter UNUSED_MEM_PINS_PINLOC_114 = 0, + parameter UNUSED_MEM_PINS_PINLOC_115 = 0, + parameter UNUSED_MEM_PINS_PINLOC_116 = 0, + parameter UNUSED_MEM_PINS_PINLOC_117 = 0, + parameter UNUSED_MEM_PINS_PINLOC_118 = 0, + parameter UNUSED_MEM_PINS_PINLOC_119 = 0, + parameter UNUSED_MEM_PINS_PINLOC_120 = 0, + parameter UNUSED_MEM_PINS_PINLOC_121 = 0, + parameter UNUSED_MEM_PINS_PINLOC_122 = 0, + parameter UNUSED_MEM_PINS_PINLOC_123 = 0, + parameter UNUSED_MEM_PINS_PINLOC_124 = 0, + parameter UNUSED_MEM_PINS_PINLOC_125 = 0, + parameter UNUSED_MEM_PINS_PINLOC_126 = 0, + parameter UNUSED_MEM_PINS_PINLOC_127 = 0, + parameter UNUSED_MEM_PINS_PINLOC_128 = 0, + parameter UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT = 0, + parameter UNUSED_DQS_BUSES_LANELOC_0 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_1 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_2 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_3 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_4 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_5 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_6 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_7 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_8 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_9 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_10 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT = 0, + parameter DBC_EXTRA_PIPE_STAGE_EN = "", + parameter DBC_PIPE_LATS_0 = 0, + parameter DBC_PIPE_LATS_1 = 0, + parameter DBC_PIPE_LATS_2 = 0, + parameter DBC_PIPE_LATS_3 = 0, + parameter DBC_PIPE_LATS_4 = 0, + parameter DBC_PIPE_LATS_AUTOGEN_WCNT = 0, + parameter DB_PTR_PIPELINE_DEPTHS_0 = 0, + parameter DB_PTR_PIPELINE_DEPTHS_1 = 0, + parameter DB_PTR_PIPELINE_DEPTHS_2 = 0, + parameter DB_PTR_PIPELINE_DEPTHS_3 = 0, + parameter DB_PTR_PIPELINE_DEPTHS_4 = 0, + parameter DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_0 = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_1 = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_2 = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_3 = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_4 = 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT = 0, + parameter CENTER_TIDS_0 = 0, + parameter CENTER_TIDS_1 = 0, + parameter CENTER_TIDS_2 = 0, + parameter CENTER_TIDS_AUTOGEN_WCNT = 0, + parameter HMC_TIDS_0 = 0, + parameter HMC_TIDS_1 = 0, + parameter HMC_TIDS_2 = 0, + parameter HMC_TIDS_AUTOGEN_WCNT = 0, + parameter LANE_TIDS_0 = 0, + parameter LANE_TIDS_1 = 0, + parameter LANE_TIDS_2 = 0, + parameter LANE_TIDS_3 = 0, + parameter LANE_TIDS_4 = 0, + parameter LANE_TIDS_5 = 0, + parameter LANE_TIDS_6 = 0, + parameter LANE_TIDS_7 = 0, + parameter LANE_TIDS_8 = 0, + parameter LANE_TIDS_9 = 0, + parameter LANE_TIDS_AUTOGEN_WCNT = 0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = 0, + parameter DQSA_LGC_MODE = "", + parameter DQSB_LGC_MODE = "", + parameter DBC_WB_RESERVED_ENTRY = 0, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + parameter ABPHY_WRITE_PROTOCOL = 0, + parameter PHY_USERMODE_OCT = 0, + parameter PHY_PERIODIC_OCT_RECAL = 0, + parameter GENERATE_PHYLITE = 0, + parameter HPRX_CTLE_EN = "", + parameter HPRX_OFFSET_CAL = "", + parameter CPA_FB_MUX_1_SEL = "", + parameter ENABLE_RD_TYPE = 0, + parameter AMM_C2P_UFI_MODE = "", + parameter AMM_P2C_UFI_MODE = "", + parameter MMR_C2P_UFI_MODE = "", + parameter MMR_P2C_UFI_MODE = "", + parameter SIDEBAND_C2P_UFI_MODE = "", + parameter SIDEBAND_P2C_UFI_MODE = "", + parameter SEQ_C2P_UFI_MODE = "", + parameter SEQ_P2C_UFI_MODE = "", + parameter ECC_C2P_UFI_MODE = "", + parameter ECC_P2C_UFI_MODE = "", + parameter LANE_C2P_UFI_MODE = "", + parameter LANE_P2C_UFI_MODE = "", + parameter AMM_HIPI_DELAY = 0, + parameter MMR_HIPI_DELAY = 0, + parameter SIDEBAND_HIPI_DELAY = 0, + parameter SEQ_HIPI_DELAY = 0, + parameter ECC_HIPI_DELAY = 0, + parameter LANE_HIPI_DELAY = 0, + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter PRI_HMC_CFG_CS_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_COL_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_RC = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter PRI_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter PRI_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter PRI_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter PRI_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter PRI_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter PRI_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter PRI_HMC_CFG_RD_ODT_ON = 0, + parameter PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter PRI_HMC_CFG_WR_ODT_ON = 0, + parameter PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter PRI_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter PRI_HMC_CFG_DQSTRK_EN = "", + parameter PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter PRI_HMC_MEMCLKGATE_SETTING = 0, + parameter PRI_HMC_CFG_TCL = 0, + parameter PRI_HMC_CFG_16_ACT_TO_ACT = 0, + parameter PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter PRI_HMC_MEM_IF_AL = 0, + parameter PRI_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter PRI_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter PRI_HMC_MEM_IF_TCCD = 0, + parameter PRI_HMC_MEM_IF_TCCD_S = 0, + parameter PRI_HMC_MEM_IF_TCKESR = 0, + parameter PRI_HMC_MEM_IF_TCKSRX = 0, + parameter PRI_HMC_MEM_IF_TCL = 0, + parameter PRI_HMC_MEM_IF_TCWL = 0, + parameter PRI_HMC_MEM_IF_TDQSCKMAX = 0, + parameter PRI_HMC_MEM_IF_TFAW = 0, + parameter PRI_HMC_MEM_IF_TMOD = 0, + parameter PRI_HMC_MEM_IF_TPL = 0, + parameter PRI_HMC_MEM_IF_TRAS = 0, + parameter PRI_HMC_MEM_IF_TRC = 0, + parameter PRI_HMC_MEM_IF_TRCD = 0, + parameter PRI_HMC_MEM_IF_TREFI = 0, + parameter PRI_HMC_MEM_IF_TRFC = 0, + parameter PRI_HMC_MEM_IF_TRP = 0, + parameter PRI_HMC_MEM_IF_TRRD = 0, + parameter PRI_HMC_MEM_IF_TRRD_S = 0, + parameter PRI_HMC_MEM_IF_TRTP = 0, + parameter PRI_HMC_MEM_IF_TWR = 0, + parameter PRI_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter PRI_HMC_MEM_IF_TWTR = 0, + parameter PRI_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter PRI_HMC_MEM_IF_TWTR_S = 0, + parameter PRI_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter PRI_HMC_MEM_IF_TXP = 0, + parameter PRI_HMC_MEM_IF_TXPDLL = 0, + parameter PRI_HMC_MEM_IF_TXSR = 0, + parameter PRI_HMC_MEM_IF_TZQCS = 0, + parameter PRI_HMC_MEM_IF_TZQOPER = 0, + parameter PRI_HMC_MEM_IF_WR_CRC = 0, + parameter PRI_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter PRI_HMC_CFG_ARF_PERIOD = 0, + parameter PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter PRI_HMC_CFG_PDN_PERIOD = 0, + parameter PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter PRI_HMC_CFG_RD_TO_PCH = 0, + parameter PRI_HMC_CFG_RD_TO_RD = 0, + parameter PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_RD_TO_WR = 0, + parameter PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter PRI_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_TEMP_WR_TO_RD = 0, + parameter PRI_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter PRI_HMC_CFG_WR_TO_PCH = 0, + parameter PRI_HMC_CFG_WR_TO_RD = 0, + parameter PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_WR_TO_WR = 0, + parameter PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter PRI_HMC_CHIP_ID = 0, + parameter PRI_HMC_CID_ADDR_WIDTH = 0, + parameter PRI_HMC_3DS_EN = "", + parameter PRI_HMC_3DS_LR_NUM0 = 0, + parameter PRI_HMC_3DS_LR_NUM1 = 0, + parameter PRI_HMC_3DS_LR_NUM2 = 0, + parameter PRI_HMC_3DS_LR_NUM3 = 0, + parameter PRI_HMC_3DS_PR_STAG_ENABLE = "", + parameter PRI_HMC_3DS_REF2REF_DLR = 0, + parameter PRI_HMC_3DSREF_ACK_ON_DONE = "", + parameter PRI_HMC_CFG_MAJOR_MODE_EN = "", + parameter PRI_HMC_CFG_REFRESH_TYPE = 0, + parameter PRI_HMC_CFG_PRE_REFRESH_EN = "", + parameter PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter PRI_HMC_CFG_POST_REFRESH_EN = "", + parameter PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter SEC_HMC_CFG_CS_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_COL_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_RC = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter SEC_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter SEC_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter SEC_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter SEC_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter SEC_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter SEC_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter SEC_HMC_CFG_RD_ODT_ON = 0, + parameter SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter SEC_HMC_CFG_WR_ODT_ON = 0, + parameter SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter SEC_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter SEC_HMC_CFG_DQSTRK_EN = "", + parameter SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter SEC_HMC_MEMCLKGATE_SETTING = 0, + parameter SEC_HMC_CFG_TCL = 0, + parameter SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter SEC_HMC_MEM_IF_AL = 0, + parameter SEC_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter SEC_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter SEC_HMC_MEM_IF_TCCD = 0, + parameter SEC_HMC_MEM_IF_TCCD_S = 0, + parameter SEC_HMC_MEM_IF_TCKESR = 0, + parameter SEC_HMC_MEM_IF_TCKSRX = 0, + parameter SEC_HMC_MEM_IF_TCL = 0, + parameter SEC_HMC_MEM_IF_TCWL = 0, + parameter SEC_HMC_MEM_IF_TDQSCKMAX = 0, + parameter SEC_HMC_MEM_IF_TFAW = 0, + parameter SEC_HMC_MEM_IF_TMOD = 0, + parameter SEC_HMC_MEM_IF_TPL = 0, + parameter SEC_HMC_MEM_IF_TRAS = 0, + parameter SEC_HMC_MEM_IF_TRC = 0, + parameter SEC_HMC_MEM_IF_TRCD = 0, + parameter SEC_HMC_MEM_IF_TREFI = 0, + parameter SEC_HMC_MEM_IF_TRFC = 0, + parameter SEC_HMC_MEM_IF_TRP = 0, + parameter SEC_HMC_MEM_IF_TRRD = 0, + parameter SEC_HMC_MEM_IF_TRRD_S = 0, + parameter SEC_HMC_MEM_IF_TRTP = 0, + parameter SEC_HMC_MEM_IF_TWR = 0, + parameter SEC_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter SEC_HMC_MEM_IF_TWTR = 0, + parameter SEC_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter SEC_HMC_MEM_IF_TWTR_S = 0, + parameter SEC_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter SEC_HMC_MEM_IF_TXP = 0, + parameter SEC_HMC_MEM_IF_TXPDLL = 0, + parameter SEC_HMC_MEM_IF_TXSR = 0, + parameter SEC_HMC_MEM_IF_TZQCS = 0, + parameter SEC_HMC_MEM_IF_TZQOPER = 0, + parameter SEC_HMC_MEM_IF_WR_CRC = 0, + parameter SEC_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter SEC_HMC_CFG_ARF_PERIOD = 0, + parameter SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter SEC_HMC_CFG_PDN_PERIOD = 0, + parameter SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter SEC_HMC_CFG_RD_TO_PCH = 0, + parameter SEC_HMC_CFG_RD_TO_RD = 0, + parameter SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_RD_TO_WR = 0, + parameter SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter SEC_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_TEMP_WR_TO_RD = 0, + parameter SEC_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter SEC_HMC_CFG_WR_TO_PCH = 0, + parameter SEC_HMC_CFG_WR_TO_RD = 0, + parameter SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_WR_TO_WR = 0, + parameter SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter SEC_HMC_CHIP_ID = 0, + parameter SEC_HMC_CID_ADDR_WIDTH = 0, + parameter SEC_HMC_3DS_EN = "", + parameter SEC_HMC_3DS_LR_NUM0 = 0, + parameter SEC_HMC_3DS_LR_NUM1 = 0, + parameter SEC_HMC_3DS_LR_NUM2 = 0, + parameter SEC_HMC_3DS_LR_NUM3 = 0, + parameter SEC_HMC_3DS_PR_STAG_ENABLE = "", + parameter SEC_HMC_3DS_REF2REF_DLR = 0, + parameter SEC_HMC_3DSREF_ACK_ON_DONE = "", + parameter SEC_HMC_CFG_MAJOR_MODE_EN = "", + parameter SEC_HMC_CFG_REFRESH_TYPE = 0, + parameter SEC_HMC_CFG_PRE_REFRESH_EN = "", + parameter SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter SEC_HMC_CFG_POST_REFRESH_EN = "", + parameter SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter PINS_PER_LANE = 0, + parameter LANES_PER_TILE = 0, + parameter OCT_CONTROL_WIDTH = 0, + parameter PORT_MEM_CK_WIDTH = 0, + parameter PORT_MEM_CK_PINLOC_0 = 0, + parameter PORT_MEM_CK_PINLOC_1 = 0, + parameter PORT_MEM_CK_PINLOC_2 = 0, + parameter PORT_MEM_CK_PINLOC_3 = 0, + parameter PORT_MEM_CK_PINLOC_4 = 0, + parameter PORT_MEM_CK_PINLOC_5 = 0, + parameter PORT_MEM_CK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_N_WIDTH = 0, + parameter PORT_MEM_CK_N_PINLOC_0 = 0, + parameter PORT_MEM_CK_N_PINLOC_1 = 0, + parameter PORT_MEM_CK_N_PINLOC_2 = 0, + parameter PORT_MEM_CK_N_PINLOC_3 = 0, + parameter PORT_MEM_CK_N_PINLOC_4 = 0, + parameter PORT_MEM_CK_N_PINLOC_5 = 0, + parameter PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_BIDIR_WIDTH = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_0 = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_1 = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_2 = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_3 = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_4 = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_5 = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_BIDIR_N_WIDTH = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_0 = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_1 = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_2 = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_3 = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_4 = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_5 = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_WIDTH = 0, + parameter PORT_MEM_DK_PINLOC_0 = 0, + parameter PORT_MEM_DK_PINLOC_1 = 0, + parameter PORT_MEM_DK_PINLOC_2 = 0, + parameter PORT_MEM_DK_PINLOC_3 = 0, + parameter PORT_MEM_DK_PINLOC_4 = 0, + parameter PORT_MEM_DK_PINLOC_5 = 0, + parameter PORT_MEM_DK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_N_WIDTH = 0, + parameter PORT_MEM_DK_N_PINLOC_0 = 0, + parameter PORT_MEM_DK_N_PINLOC_1 = 0, + parameter PORT_MEM_DK_N_PINLOC_2 = 0, + parameter PORT_MEM_DK_N_PINLOC_3 = 0, + parameter PORT_MEM_DK_N_PINLOC_4 = 0, + parameter PORT_MEM_DK_N_PINLOC_5 = 0, + parameter PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_WIDTH = 0, + parameter PORT_MEM_DKA_PINLOC_0 = 0, + parameter PORT_MEM_DKA_PINLOC_1 = 0, + parameter PORT_MEM_DKA_PINLOC_2 = 0, + parameter PORT_MEM_DKA_PINLOC_3 = 0, + parameter PORT_MEM_DKA_PINLOC_4 = 0, + parameter PORT_MEM_DKA_PINLOC_5 = 0, + parameter PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_N_WIDTH = 0, + parameter PORT_MEM_DKA_N_PINLOC_0 = 0, + parameter PORT_MEM_DKA_N_PINLOC_1 = 0, + parameter PORT_MEM_DKA_N_PINLOC_2 = 0, + parameter PORT_MEM_DKA_N_PINLOC_3 = 0, + parameter PORT_MEM_DKA_N_PINLOC_4 = 0, + parameter PORT_MEM_DKA_N_PINLOC_5 = 0, + parameter PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_WIDTH = 0, + parameter PORT_MEM_DKB_PINLOC_0 = 0, + parameter PORT_MEM_DKB_PINLOC_1 = 0, + parameter PORT_MEM_DKB_PINLOC_2 = 0, + parameter PORT_MEM_DKB_PINLOC_3 = 0, + parameter PORT_MEM_DKB_PINLOC_4 = 0, + parameter PORT_MEM_DKB_PINLOC_5 = 0, + parameter PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_N_WIDTH = 0, + parameter PORT_MEM_DKB_N_PINLOC_0 = 0, + parameter PORT_MEM_DKB_N_PINLOC_1 = 0, + parameter PORT_MEM_DKB_N_PINLOC_2 = 0, + parameter PORT_MEM_DKB_N_PINLOC_3 = 0, + parameter PORT_MEM_DKB_N_PINLOC_4 = 0, + parameter PORT_MEM_DKB_N_PINLOC_5 = 0, + parameter PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_WIDTH = 0, + parameter PORT_MEM_K_PINLOC_0 = 0, + parameter PORT_MEM_K_PINLOC_1 = 0, + parameter PORT_MEM_K_PINLOC_2 = 0, + parameter PORT_MEM_K_PINLOC_3 = 0, + parameter PORT_MEM_K_PINLOC_4 = 0, + parameter PORT_MEM_K_PINLOC_5 = 0, + parameter PORT_MEM_K_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_N_WIDTH = 0, + parameter PORT_MEM_K_N_PINLOC_0 = 0, + parameter PORT_MEM_K_N_PINLOC_1 = 0, + parameter PORT_MEM_K_N_PINLOC_2 = 0, + parameter PORT_MEM_K_N_PINLOC_3 = 0, + parameter PORT_MEM_K_N_PINLOC_4 = 0, + parameter PORT_MEM_K_N_PINLOC_5 = 0, + parameter PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_A_WIDTH = 0, + parameter PORT_MEM_A_PINLOC_0 = 0, + parameter PORT_MEM_A_PINLOC_1 = 0, + parameter PORT_MEM_A_PINLOC_2 = 0, + parameter PORT_MEM_A_PINLOC_3 = 0, + parameter PORT_MEM_A_PINLOC_4 = 0, + parameter PORT_MEM_A_PINLOC_5 = 0, + parameter PORT_MEM_A_PINLOC_6 = 0, + parameter PORT_MEM_A_PINLOC_7 = 0, + parameter PORT_MEM_A_PINLOC_8 = 0, + parameter PORT_MEM_A_PINLOC_9 = 0, + parameter PORT_MEM_A_PINLOC_10 = 0, + parameter PORT_MEM_A_PINLOC_11 = 0, + parameter PORT_MEM_A_PINLOC_12 = 0, + parameter PORT_MEM_A_PINLOC_13 = 0, + parameter PORT_MEM_A_PINLOC_14 = 0, + parameter PORT_MEM_A_PINLOC_15 = 0, + parameter PORT_MEM_A_PINLOC_16 = 0, + parameter PORT_MEM_A_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BA_WIDTH = 0, + parameter PORT_MEM_BA_PINLOC_0 = 0, + parameter PORT_MEM_BA_PINLOC_1 = 0, + parameter PORT_MEM_BA_PINLOC_2 = 0, + parameter PORT_MEM_BA_PINLOC_3 = 0, + parameter PORT_MEM_BA_PINLOC_4 = 0, + parameter PORT_MEM_BA_PINLOC_5 = 0, + parameter PORT_MEM_BA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BG_WIDTH = 0, + parameter PORT_MEM_BG_PINLOC_0 = 0, + parameter PORT_MEM_BG_PINLOC_1 = 0, + parameter PORT_MEM_BG_PINLOC_2 = 0, + parameter PORT_MEM_BG_PINLOC_3 = 0, + parameter PORT_MEM_BG_PINLOC_4 = 0, + parameter PORT_MEM_BG_PINLOC_5 = 0, + parameter PORT_MEM_BG_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_C_WIDTH = 0, + parameter PORT_MEM_C_PINLOC_0 = 0, + parameter PORT_MEM_C_PINLOC_1 = 0, + parameter PORT_MEM_C_PINLOC_2 = 0, + parameter PORT_MEM_C_PINLOC_3 = 0, + parameter PORT_MEM_C_PINLOC_4 = 0, + parameter PORT_MEM_C_PINLOC_5 = 0, + parameter PORT_MEM_C_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CKE_WIDTH = 0, + parameter PORT_MEM_CKE_PINLOC_0 = 0, + parameter PORT_MEM_CKE_PINLOC_1 = 0, + parameter PORT_MEM_CKE_PINLOC_2 = 0, + parameter PORT_MEM_CKE_PINLOC_3 = 0, + parameter PORT_MEM_CKE_PINLOC_4 = 0, + parameter PORT_MEM_CKE_PINLOC_5 = 0, + parameter PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CS_N_WIDTH = 0, + parameter PORT_MEM_CS_N_PINLOC_0 = 0, + parameter PORT_MEM_CS_N_PINLOC_1 = 0, + parameter PORT_MEM_CS_N_PINLOC_2 = 0, + parameter PORT_MEM_CS_N_PINLOC_3 = 0, + parameter PORT_MEM_CS_N_PINLOC_4 = 0, + parameter PORT_MEM_CS_N_PINLOC_5 = 0, + parameter PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RM_WIDTH = 0, + parameter PORT_MEM_RM_PINLOC_0 = 0, + parameter PORT_MEM_RM_PINLOC_1 = 0, + parameter PORT_MEM_RM_PINLOC_2 = 0, + parameter PORT_MEM_RM_PINLOC_3 = 0, + parameter PORT_MEM_RM_PINLOC_4 = 0, + parameter PORT_MEM_RM_PINLOC_5 = 0, + parameter PORT_MEM_RM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ODT_WIDTH = 0, + parameter PORT_MEM_ODT_PINLOC_0 = 0, + parameter PORT_MEM_ODT_PINLOC_1 = 0, + parameter PORT_MEM_ODT_PINLOC_2 = 0, + parameter PORT_MEM_ODT_PINLOC_3 = 0, + parameter PORT_MEM_ODT_PINLOC_4 = 0, + parameter PORT_MEM_ODT_PINLOC_5 = 0, + parameter PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REQ_N_WIDTH = 0, + parameter PORT_MEM_REQ_N_PINLOC_0 = 0, + parameter PORT_MEM_REQ_N_PINLOC_1 = 0, + parameter PORT_MEM_REQ_N_PINLOC_2 = 0, + parameter PORT_MEM_REQ_N_PINLOC_3 = 0, + parameter PORT_MEM_REQ_N_PINLOC_4 = 0, + parameter PORT_MEM_REQ_N_PINLOC_5 = 0, + parameter PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_GNT_N_WIDTH = 0, + parameter PORT_MEM_GNT_N_PINLOC_0 = 0, + parameter PORT_MEM_GNT_N_PINLOC_1 = 0, + parameter PORT_MEM_GNT_N_PINLOC_2 = 0, + parameter PORT_MEM_GNT_N_PINLOC_3 = 0, + parameter PORT_MEM_GNT_N_PINLOC_4 = 0, + parameter PORT_MEM_GNT_N_PINLOC_5 = 0, + parameter PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ERR_N_WIDTH = 0, + parameter PORT_MEM_ERR_N_PINLOC_0 = 0, + parameter PORT_MEM_ERR_N_PINLOC_1 = 0, + parameter PORT_MEM_ERR_N_PINLOC_2 = 0, + parameter PORT_MEM_ERR_N_PINLOC_3 = 0, + parameter PORT_MEM_ERR_N_PINLOC_4 = 0, + parameter PORT_MEM_ERR_N_PINLOC_5 = 0, + parameter PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RAS_N_WIDTH = 0, + parameter PORT_MEM_RAS_N_PINLOC_0 = 0, + parameter PORT_MEM_RAS_N_PINLOC_1 = 0, + parameter PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CAS_N_WIDTH = 0, + parameter PORT_MEM_CAS_N_PINLOC_0 = 0, + parameter PORT_MEM_CAS_N_PINLOC_1 = 0, + parameter PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WE_N_WIDTH = 0, + parameter PORT_MEM_WE_N_PINLOC_0 = 0, + parameter PORT_MEM_WE_N_PINLOC_1 = 0, + parameter PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RESET_N_WIDTH = 0, + parameter PORT_MEM_RESET_N_PINLOC_0 = 0, + parameter PORT_MEM_RESET_N_PINLOC_1 = 0, + parameter PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ACT_N_WIDTH = 0, + parameter PORT_MEM_ACT_N_PINLOC_0 = 0, + parameter PORT_MEM_ACT_N_PINLOC_1 = 0, + parameter PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PAR_WIDTH = 0, + parameter PORT_MEM_PAR_PINLOC_0 = 0, + parameter PORT_MEM_PAR_PINLOC_1 = 0, + parameter PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CA_WIDTH = 0, + parameter PORT_MEM_CA_PINLOC_0 = 0, + parameter PORT_MEM_CA_PINLOC_1 = 0, + parameter PORT_MEM_CA_PINLOC_2 = 0, + parameter PORT_MEM_CA_PINLOC_3 = 0, + parameter PORT_MEM_CA_PINLOC_4 = 0, + parameter PORT_MEM_CA_PINLOC_5 = 0, + parameter PORT_MEM_CA_PINLOC_6 = 0, + parameter PORT_MEM_CA_PINLOC_7 = 0, + parameter PORT_MEM_CA_PINLOC_8 = 0, + parameter PORT_MEM_CA_PINLOC_9 = 0, + parameter PORT_MEM_CA_PINLOC_10 = 0, + parameter PORT_MEM_CA_PINLOC_11 = 0, + parameter PORT_MEM_CA_PINLOC_12 = 0, + parameter PORT_MEM_CA_PINLOC_13 = 0, + parameter PORT_MEM_CA_PINLOC_14 = 0, + parameter PORT_MEM_CA_PINLOC_15 = 0, + parameter PORT_MEM_CA_PINLOC_16 = 0, + parameter PORT_MEM_CA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REF_N_WIDTH = 0, + parameter PORT_MEM_REF_N_PINLOC_0 = 0, + parameter PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WPS_N_WIDTH = 0, + parameter PORT_MEM_WPS_N_PINLOC_0 = 0, + parameter PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RPS_N_WIDTH = 0, + parameter PORT_MEM_RPS_N_PINLOC_0 = 0, + parameter PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DOFF_N_WIDTH = 0, + parameter PORT_MEM_DOFF_N_PINLOC_0 = 0, + parameter PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDA_N_WIDTH = 0, + parameter PORT_MEM_LDA_N_PINLOC_0 = 0, + parameter PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDB_N_WIDTH = 0, + parameter PORT_MEM_LDB_N_PINLOC_0 = 0, + parameter PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWA_N_WIDTH = 0, + parameter PORT_MEM_RWA_N_PINLOC_0 = 0, + parameter PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWB_N_WIDTH = 0, + parameter PORT_MEM_RWB_N_PINLOC_0 = 0, + parameter PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK0_N_WIDTH = 0, + parameter PORT_MEM_LBK0_N_PINLOC_0 = 0, + parameter PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK1_N_WIDTH = 0, + parameter PORT_MEM_LBK1_N_PINLOC_0 = 0, + parameter PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CFG_N_WIDTH = 0, + parameter PORT_MEM_CFG_N_PINLOC_0 = 0, + parameter PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AP_WIDTH = 0, + parameter PORT_MEM_AP_PINLOC_0 = 0, + parameter PORT_MEM_AP_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AINV_WIDTH = 0, + parameter PORT_MEM_AINV_PINLOC_0 = 0, + parameter PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DM_WIDTH = 0, + parameter PORT_MEM_DM_PINLOC_0 = 0, + parameter PORT_MEM_DM_PINLOC_1 = 0, + parameter PORT_MEM_DM_PINLOC_2 = 0, + parameter PORT_MEM_DM_PINLOC_3 = 0, + parameter PORT_MEM_DM_PINLOC_4 = 0, + parameter PORT_MEM_DM_PINLOC_5 = 0, + parameter PORT_MEM_DM_PINLOC_6 = 0, + parameter PORT_MEM_DM_PINLOC_7 = 0, + parameter PORT_MEM_DM_PINLOC_8 = 0, + parameter PORT_MEM_DM_PINLOC_9 = 0, + parameter PORT_MEM_DM_PINLOC_10 = 0, + parameter PORT_MEM_DM_PINLOC_11 = 0, + parameter PORT_MEM_DM_PINLOC_12 = 0, + parameter PORT_MEM_DM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BWS_N_WIDTH = 0, + parameter PORT_MEM_BWS_N_PINLOC_0 = 0, + parameter PORT_MEM_BWS_N_PINLOC_1 = 0, + parameter PORT_MEM_BWS_N_PINLOC_2 = 0, + parameter PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_D_WIDTH = 0, + parameter PORT_MEM_D_PINLOC_0 = 0, + parameter PORT_MEM_D_PINLOC_1 = 0, + parameter PORT_MEM_D_PINLOC_2 = 0, + parameter PORT_MEM_D_PINLOC_3 = 0, + parameter PORT_MEM_D_PINLOC_4 = 0, + parameter PORT_MEM_D_PINLOC_5 = 0, + parameter PORT_MEM_D_PINLOC_6 = 0, + parameter PORT_MEM_D_PINLOC_7 = 0, + parameter PORT_MEM_D_PINLOC_8 = 0, + parameter PORT_MEM_D_PINLOC_9 = 0, + parameter PORT_MEM_D_PINLOC_10 = 0, + parameter PORT_MEM_D_PINLOC_11 = 0, + parameter PORT_MEM_D_PINLOC_12 = 0, + parameter PORT_MEM_D_PINLOC_13 = 0, + parameter PORT_MEM_D_PINLOC_14 = 0, + parameter PORT_MEM_D_PINLOC_15 = 0, + parameter PORT_MEM_D_PINLOC_16 = 0, + parameter PORT_MEM_D_PINLOC_17 = 0, + parameter PORT_MEM_D_PINLOC_18 = 0, + parameter PORT_MEM_D_PINLOC_19 = 0, + parameter PORT_MEM_D_PINLOC_20 = 0, + parameter PORT_MEM_D_PINLOC_21 = 0, + parameter PORT_MEM_D_PINLOC_22 = 0, + parameter PORT_MEM_D_PINLOC_23 = 0, + parameter PORT_MEM_D_PINLOC_24 = 0, + parameter PORT_MEM_D_PINLOC_25 = 0, + parameter PORT_MEM_D_PINLOC_26 = 0, + parameter PORT_MEM_D_PINLOC_27 = 0, + parameter PORT_MEM_D_PINLOC_28 = 0, + parameter PORT_MEM_D_PINLOC_29 = 0, + parameter PORT_MEM_D_PINLOC_30 = 0, + parameter PORT_MEM_D_PINLOC_31 = 0, + parameter PORT_MEM_D_PINLOC_32 = 0, + parameter PORT_MEM_D_PINLOC_33 = 0, + parameter PORT_MEM_D_PINLOC_34 = 0, + parameter PORT_MEM_D_PINLOC_35 = 0, + parameter PORT_MEM_D_PINLOC_36 = 0, + parameter PORT_MEM_D_PINLOC_37 = 0, + parameter PORT_MEM_D_PINLOC_38 = 0, + parameter PORT_MEM_D_PINLOC_39 = 0, + parameter PORT_MEM_D_PINLOC_40 = 0, + parameter PORT_MEM_D_PINLOC_41 = 0, + parameter PORT_MEM_D_PINLOC_42 = 0, + parameter PORT_MEM_D_PINLOC_43 = 0, + parameter PORT_MEM_D_PINLOC_44 = 0, + parameter PORT_MEM_D_PINLOC_45 = 0, + parameter PORT_MEM_D_PINLOC_46 = 0, + parameter PORT_MEM_D_PINLOC_47 = 0, + parameter PORT_MEM_D_PINLOC_48 = 0, + parameter PORT_MEM_D_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQ_WIDTH = 0, + parameter PORT_MEM_DQ_PINLOC_0 = 0, + parameter PORT_MEM_DQ_PINLOC_1 = 0, + parameter PORT_MEM_DQ_PINLOC_2 = 0, + parameter PORT_MEM_DQ_PINLOC_3 = 0, + parameter PORT_MEM_DQ_PINLOC_4 = 0, + parameter PORT_MEM_DQ_PINLOC_5 = 0, + parameter PORT_MEM_DQ_PINLOC_6 = 0, + parameter PORT_MEM_DQ_PINLOC_7 = 0, + parameter PORT_MEM_DQ_PINLOC_8 = 0, + parameter PORT_MEM_DQ_PINLOC_9 = 0, + parameter PORT_MEM_DQ_PINLOC_10 = 0, + parameter PORT_MEM_DQ_PINLOC_11 = 0, + parameter PORT_MEM_DQ_PINLOC_12 = 0, + parameter PORT_MEM_DQ_PINLOC_13 = 0, + parameter PORT_MEM_DQ_PINLOC_14 = 0, + parameter PORT_MEM_DQ_PINLOC_15 = 0, + parameter PORT_MEM_DQ_PINLOC_16 = 0, + parameter PORT_MEM_DQ_PINLOC_17 = 0, + parameter PORT_MEM_DQ_PINLOC_18 = 0, + parameter PORT_MEM_DQ_PINLOC_19 = 0, + parameter PORT_MEM_DQ_PINLOC_20 = 0, + parameter PORT_MEM_DQ_PINLOC_21 = 0, + parameter PORT_MEM_DQ_PINLOC_22 = 0, + parameter PORT_MEM_DQ_PINLOC_23 = 0, + parameter PORT_MEM_DQ_PINLOC_24 = 0, + parameter PORT_MEM_DQ_PINLOC_25 = 0, + parameter PORT_MEM_DQ_PINLOC_26 = 0, + parameter PORT_MEM_DQ_PINLOC_27 = 0, + parameter PORT_MEM_DQ_PINLOC_28 = 0, + parameter PORT_MEM_DQ_PINLOC_29 = 0, + parameter PORT_MEM_DQ_PINLOC_30 = 0, + parameter PORT_MEM_DQ_PINLOC_31 = 0, + parameter PORT_MEM_DQ_PINLOC_32 = 0, + parameter PORT_MEM_DQ_PINLOC_33 = 0, + parameter PORT_MEM_DQ_PINLOC_34 = 0, + parameter PORT_MEM_DQ_PINLOC_35 = 0, + parameter PORT_MEM_DQ_PINLOC_36 = 0, + parameter PORT_MEM_DQ_PINLOC_37 = 0, + parameter PORT_MEM_DQ_PINLOC_38 = 0, + parameter PORT_MEM_DQ_PINLOC_39 = 0, + parameter PORT_MEM_DQ_PINLOC_40 = 0, + parameter PORT_MEM_DQ_PINLOC_41 = 0, + parameter PORT_MEM_DQ_PINLOC_42 = 0, + parameter PORT_MEM_DQ_PINLOC_43 = 0, + parameter PORT_MEM_DQ_PINLOC_44 = 0, + parameter PORT_MEM_DQ_PINLOC_45 = 0, + parameter PORT_MEM_DQ_PINLOC_46 = 0, + parameter PORT_MEM_DQ_PINLOC_47 = 0, + parameter PORT_MEM_DQ_PINLOC_48 = 0, + parameter PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DBI_N_WIDTH = 0, + parameter PORT_MEM_DBI_N_PINLOC_0 = 0, + parameter PORT_MEM_DBI_N_PINLOC_1 = 0, + parameter PORT_MEM_DBI_N_PINLOC_2 = 0, + parameter PORT_MEM_DBI_N_PINLOC_3 = 0, + parameter PORT_MEM_DBI_N_PINLOC_4 = 0, + parameter PORT_MEM_DBI_N_PINLOC_5 = 0, + parameter PORT_MEM_DBI_N_PINLOC_6 = 0, + parameter PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQA_WIDTH = 0, + parameter PORT_MEM_DQA_PINLOC_0 = 0, + parameter PORT_MEM_DQA_PINLOC_1 = 0, + parameter PORT_MEM_DQA_PINLOC_2 = 0, + parameter PORT_MEM_DQA_PINLOC_3 = 0, + parameter PORT_MEM_DQA_PINLOC_4 = 0, + parameter PORT_MEM_DQA_PINLOC_5 = 0, + parameter PORT_MEM_DQA_PINLOC_6 = 0, + parameter PORT_MEM_DQA_PINLOC_7 = 0, + parameter PORT_MEM_DQA_PINLOC_8 = 0, + parameter PORT_MEM_DQA_PINLOC_9 = 0, + parameter PORT_MEM_DQA_PINLOC_10 = 0, + parameter PORT_MEM_DQA_PINLOC_11 = 0, + parameter PORT_MEM_DQA_PINLOC_12 = 0, + parameter PORT_MEM_DQA_PINLOC_13 = 0, + parameter PORT_MEM_DQA_PINLOC_14 = 0, + parameter PORT_MEM_DQA_PINLOC_15 = 0, + parameter PORT_MEM_DQA_PINLOC_16 = 0, + parameter PORT_MEM_DQA_PINLOC_17 = 0, + parameter PORT_MEM_DQA_PINLOC_18 = 0, + parameter PORT_MEM_DQA_PINLOC_19 = 0, + parameter PORT_MEM_DQA_PINLOC_20 = 0, + parameter PORT_MEM_DQA_PINLOC_21 = 0, + parameter PORT_MEM_DQA_PINLOC_22 = 0, + parameter PORT_MEM_DQA_PINLOC_23 = 0, + parameter PORT_MEM_DQA_PINLOC_24 = 0, + parameter PORT_MEM_DQA_PINLOC_25 = 0, + parameter PORT_MEM_DQA_PINLOC_26 = 0, + parameter PORT_MEM_DQA_PINLOC_27 = 0, + parameter PORT_MEM_DQA_PINLOC_28 = 0, + parameter PORT_MEM_DQA_PINLOC_29 = 0, + parameter PORT_MEM_DQA_PINLOC_30 = 0, + parameter PORT_MEM_DQA_PINLOC_31 = 0, + parameter PORT_MEM_DQA_PINLOC_32 = 0, + parameter PORT_MEM_DQA_PINLOC_33 = 0, + parameter PORT_MEM_DQA_PINLOC_34 = 0, + parameter PORT_MEM_DQA_PINLOC_35 = 0, + parameter PORT_MEM_DQA_PINLOC_36 = 0, + parameter PORT_MEM_DQA_PINLOC_37 = 0, + parameter PORT_MEM_DQA_PINLOC_38 = 0, + parameter PORT_MEM_DQA_PINLOC_39 = 0, + parameter PORT_MEM_DQA_PINLOC_40 = 0, + parameter PORT_MEM_DQA_PINLOC_41 = 0, + parameter PORT_MEM_DQA_PINLOC_42 = 0, + parameter PORT_MEM_DQA_PINLOC_43 = 0, + parameter PORT_MEM_DQA_PINLOC_44 = 0, + parameter PORT_MEM_DQA_PINLOC_45 = 0, + parameter PORT_MEM_DQA_PINLOC_46 = 0, + parameter PORT_MEM_DQA_PINLOC_47 = 0, + parameter PORT_MEM_DQA_PINLOC_48 = 0, + parameter PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQB_WIDTH = 0, + parameter PORT_MEM_DQB_PINLOC_0 = 0, + parameter PORT_MEM_DQB_PINLOC_1 = 0, + parameter PORT_MEM_DQB_PINLOC_2 = 0, + parameter PORT_MEM_DQB_PINLOC_3 = 0, + parameter PORT_MEM_DQB_PINLOC_4 = 0, + parameter PORT_MEM_DQB_PINLOC_5 = 0, + parameter PORT_MEM_DQB_PINLOC_6 = 0, + parameter PORT_MEM_DQB_PINLOC_7 = 0, + parameter PORT_MEM_DQB_PINLOC_8 = 0, + parameter PORT_MEM_DQB_PINLOC_9 = 0, + parameter PORT_MEM_DQB_PINLOC_10 = 0, + parameter PORT_MEM_DQB_PINLOC_11 = 0, + parameter PORT_MEM_DQB_PINLOC_12 = 0, + parameter PORT_MEM_DQB_PINLOC_13 = 0, + parameter PORT_MEM_DQB_PINLOC_14 = 0, + parameter PORT_MEM_DQB_PINLOC_15 = 0, + parameter PORT_MEM_DQB_PINLOC_16 = 0, + parameter PORT_MEM_DQB_PINLOC_17 = 0, + parameter PORT_MEM_DQB_PINLOC_18 = 0, + parameter PORT_MEM_DQB_PINLOC_19 = 0, + parameter PORT_MEM_DQB_PINLOC_20 = 0, + parameter PORT_MEM_DQB_PINLOC_21 = 0, + parameter PORT_MEM_DQB_PINLOC_22 = 0, + parameter PORT_MEM_DQB_PINLOC_23 = 0, + parameter PORT_MEM_DQB_PINLOC_24 = 0, + parameter PORT_MEM_DQB_PINLOC_25 = 0, + parameter PORT_MEM_DQB_PINLOC_26 = 0, + parameter PORT_MEM_DQB_PINLOC_27 = 0, + parameter PORT_MEM_DQB_PINLOC_28 = 0, + parameter PORT_MEM_DQB_PINLOC_29 = 0, + parameter PORT_MEM_DQB_PINLOC_30 = 0, + parameter PORT_MEM_DQB_PINLOC_31 = 0, + parameter PORT_MEM_DQB_PINLOC_32 = 0, + parameter PORT_MEM_DQB_PINLOC_33 = 0, + parameter PORT_MEM_DQB_PINLOC_34 = 0, + parameter PORT_MEM_DQB_PINLOC_35 = 0, + parameter PORT_MEM_DQB_PINLOC_36 = 0, + parameter PORT_MEM_DQB_PINLOC_37 = 0, + parameter PORT_MEM_DQB_PINLOC_38 = 0, + parameter PORT_MEM_DQB_PINLOC_39 = 0, + parameter PORT_MEM_DQB_PINLOC_40 = 0, + parameter PORT_MEM_DQB_PINLOC_41 = 0, + parameter PORT_MEM_DQB_PINLOC_42 = 0, + parameter PORT_MEM_DQB_PINLOC_43 = 0, + parameter PORT_MEM_DQB_PINLOC_44 = 0, + parameter PORT_MEM_DQB_PINLOC_45 = 0, + parameter PORT_MEM_DQB_PINLOC_46 = 0, + parameter PORT_MEM_DQB_PINLOC_47 = 0, + parameter PORT_MEM_DQB_PINLOC_48 = 0, + parameter PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVA_WIDTH = 0, + parameter PORT_MEM_DINVA_PINLOC_0 = 0, + parameter PORT_MEM_DINVA_PINLOC_1 = 0, + parameter PORT_MEM_DINVA_PINLOC_2 = 0, + parameter PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVB_WIDTH = 0, + parameter PORT_MEM_DINVB_PINLOC_0 = 0, + parameter PORT_MEM_DINVB_PINLOC_1 = 0, + parameter PORT_MEM_DINVB_PINLOC_2 = 0, + parameter PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_Q_WIDTH = 0, + parameter PORT_MEM_Q_PINLOC_0 = 0, + parameter PORT_MEM_Q_PINLOC_1 = 0, + parameter PORT_MEM_Q_PINLOC_2 = 0, + parameter PORT_MEM_Q_PINLOC_3 = 0, + parameter PORT_MEM_Q_PINLOC_4 = 0, + parameter PORT_MEM_Q_PINLOC_5 = 0, + parameter PORT_MEM_Q_PINLOC_6 = 0, + parameter PORT_MEM_Q_PINLOC_7 = 0, + parameter PORT_MEM_Q_PINLOC_8 = 0, + parameter PORT_MEM_Q_PINLOC_9 = 0, + parameter PORT_MEM_Q_PINLOC_10 = 0, + parameter PORT_MEM_Q_PINLOC_11 = 0, + parameter PORT_MEM_Q_PINLOC_12 = 0, + parameter PORT_MEM_Q_PINLOC_13 = 0, + parameter PORT_MEM_Q_PINLOC_14 = 0, + parameter PORT_MEM_Q_PINLOC_15 = 0, + parameter PORT_MEM_Q_PINLOC_16 = 0, + parameter PORT_MEM_Q_PINLOC_17 = 0, + parameter PORT_MEM_Q_PINLOC_18 = 0, + parameter PORT_MEM_Q_PINLOC_19 = 0, + parameter PORT_MEM_Q_PINLOC_20 = 0, + parameter PORT_MEM_Q_PINLOC_21 = 0, + parameter PORT_MEM_Q_PINLOC_22 = 0, + parameter PORT_MEM_Q_PINLOC_23 = 0, + parameter PORT_MEM_Q_PINLOC_24 = 0, + parameter PORT_MEM_Q_PINLOC_25 = 0, + parameter PORT_MEM_Q_PINLOC_26 = 0, + parameter PORT_MEM_Q_PINLOC_27 = 0, + parameter PORT_MEM_Q_PINLOC_28 = 0, + parameter PORT_MEM_Q_PINLOC_29 = 0, + parameter PORT_MEM_Q_PINLOC_30 = 0, + parameter PORT_MEM_Q_PINLOC_31 = 0, + parameter PORT_MEM_Q_PINLOC_32 = 0, + parameter PORT_MEM_Q_PINLOC_33 = 0, + parameter PORT_MEM_Q_PINLOC_34 = 0, + parameter PORT_MEM_Q_PINLOC_35 = 0, + parameter PORT_MEM_Q_PINLOC_36 = 0, + parameter PORT_MEM_Q_PINLOC_37 = 0, + parameter PORT_MEM_Q_PINLOC_38 = 0, + parameter PORT_MEM_Q_PINLOC_39 = 0, + parameter PORT_MEM_Q_PINLOC_40 = 0, + parameter PORT_MEM_Q_PINLOC_41 = 0, + parameter PORT_MEM_Q_PINLOC_42 = 0, + parameter PORT_MEM_Q_PINLOC_43 = 0, + parameter PORT_MEM_Q_PINLOC_44 = 0, + parameter PORT_MEM_Q_PINLOC_45 = 0, + parameter PORT_MEM_Q_PINLOC_46 = 0, + parameter PORT_MEM_Q_PINLOC_47 = 0, + parameter PORT_MEM_Q_PINLOC_48 = 0, + parameter PORT_MEM_Q_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_WIDTH = 0, + parameter PORT_MEM_DQS_PINLOC_0 = 0, + parameter PORT_MEM_DQS_PINLOC_1 = 0, + parameter PORT_MEM_DQS_PINLOC_2 = 0, + parameter PORT_MEM_DQS_PINLOC_3 = 0, + parameter PORT_MEM_DQS_PINLOC_4 = 0, + parameter PORT_MEM_DQS_PINLOC_5 = 0, + parameter PORT_MEM_DQS_PINLOC_6 = 0, + parameter PORT_MEM_DQS_PINLOC_7 = 0, + parameter PORT_MEM_DQS_PINLOC_8 = 0, + parameter PORT_MEM_DQS_PINLOC_9 = 0, + parameter PORT_MEM_DQS_PINLOC_10 = 0, + parameter PORT_MEM_DQS_PINLOC_11 = 0, + parameter PORT_MEM_DQS_PINLOC_12 = 0, + parameter PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_N_WIDTH = 0, + parameter PORT_MEM_DQS_N_PINLOC_0 = 0, + parameter PORT_MEM_DQS_N_PINLOC_1 = 0, + parameter PORT_MEM_DQS_N_PINLOC_2 = 0, + parameter PORT_MEM_DQS_N_PINLOC_3 = 0, + parameter PORT_MEM_DQS_N_PINLOC_4 = 0, + parameter PORT_MEM_DQS_N_PINLOC_5 = 0, + parameter PORT_MEM_DQS_N_PINLOC_6 = 0, + parameter PORT_MEM_DQS_N_PINLOC_7 = 0, + parameter PORT_MEM_DQS_N_PINLOC_8 = 0, + parameter PORT_MEM_DQS_N_PINLOC_9 = 0, + parameter PORT_MEM_DQS_N_PINLOC_10 = 0, + parameter PORT_MEM_DQS_N_PINLOC_11 = 0, + parameter PORT_MEM_DQS_N_PINLOC_12 = 0, + parameter PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_WIDTH = 0, + parameter PORT_MEM_QK_PINLOC_0 = 0, + parameter PORT_MEM_QK_PINLOC_1 = 0, + parameter PORT_MEM_QK_PINLOC_2 = 0, + parameter PORT_MEM_QK_PINLOC_3 = 0, + parameter PORT_MEM_QK_PINLOC_4 = 0, + parameter PORT_MEM_QK_PINLOC_5 = 0, + parameter PORT_MEM_QK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_N_WIDTH = 0, + parameter PORT_MEM_QK_N_PINLOC_0 = 0, + parameter PORT_MEM_QK_N_PINLOC_1 = 0, + parameter PORT_MEM_QK_N_PINLOC_2 = 0, + parameter PORT_MEM_QK_N_PINLOC_3 = 0, + parameter PORT_MEM_QK_N_PINLOC_4 = 0, + parameter PORT_MEM_QK_N_PINLOC_5 = 0, + parameter PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_WIDTH = 0, + parameter PORT_MEM_QKA_PINLOC_0 = 0, + parameter PORT_MEM_QKA_PINLOC_1 = 0, + parameter PORT_MEM_QKA_PINLOC_2 = 0, + parameter PORT_MEM_QKA_PINLOC_3 = 0, + parameter PORT_MEM_QKA_PINLOC_4 = 0, + parameter PORT_MEM_QKA_PINLOC_5 = 0, + parameter PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_N_WIDTH = 0, + parameter PORT_MEM_QKA_N_PINLOC_0 = 0, + parameter PORT_MEM_QKA_N_PINLOC_1 = 0, + parameter PORT_MEM_QKA_N_PINLOC_2 = 0, + parameter PORT_MEM_QKA_N_PINLOC_3 = 0, + parameter PORT_MEM_QKA_N_PINLOC_4 = 0, + parameter PORT_MEM_QKA_N_PINLOC_5 = 0, + parameter PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_WIDTH = 0, + parameter PORT_MEM_QKB_PINLOC_0 = 0, + parameter PORT_MEM_QKB_PINLOC_1 = 0, + parameter PORT_MEM_QKB_PINLOC_2 = 0, + parameter PORT_MEM_QKB_PINLOC_3 = 0, + parameter PORT_MEM_QKB_PINLOC_4 = 0, + parameter PORT_MEM_QKB_PINLOC_5 = 0, + parameter PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_N_WIDTH = 0, + parameter PORT_MEM_QKB_N_PINLOC_0 = 0, + parameter PORT_MEM_QKB_N_PINLOC_1 = 0, + parameter PORT_MEM_QKB_N_PINLOC_2 = 0, + parameter PORT_MEM_QKB_N_PINLOC_3 = 0, + parameter PORT_MEM_QKB_N_PINLOC_4 = 0, + parameter PORT_MEM_QKB_N_PINLOC_5 = 0, + parameter PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_WIDTH = 0, + parameter PORT_MEM_CQ_PINLOC_0 = 0, + parameter PORT_MEM_CQ_PINLOC_1 = 0, + parameter PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_N_WIDTH = 0, + parameter PORT_MEM_CQ_N_PINLOC_0 = 0, + parameter PORT_MEM_CQ_N_PINLOC_1 = 0, + parameter PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ALERT_N_WIDTH = 0, + parameter PORT_MEM_ALERT_N_PINLOC_0 = 0, + parameter PORT_MEM_ALERT_N_PINLOC_1 = 0, + parameter PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PE_N_WIDTH = 0, + parameter PORT_MEM_PE_N_PINLOC_0 = 0, + parameter PORT_MEM_PE_N_PINLOC_1 = 0, + parameter PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 0, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 0, + parameter PORT_CLKS_SHARING_SLAVE_OUT_WIDTH = 0, + parameter PORT_AFI_RLAT_WIDTH = 0, + parameter PORT_AFI_WLAT_WIDTH = 0, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 0, + parameter PORT_AFI_ADDR_WIDTH = 0, + parameter PORT_AFI_BA_WIDTH = 0, + parameter PORT_AFI_BG_WIDTH = 0, + parameter PORT_AFI_C_WIDTH = 0, + parameter PORT_AFI_CKE_WIDTH = 0, + parameter PORT_AFI_CS_N_WIDTH = 0, + parameter PORT_AFI_RM_WIDTH = 0, + parameter PORT_AFI_ODT_WIDTH = 0, + parameter PORT_AFI_RAS_N_WIDTH = 0, + parameter PORT_AFI_CAS_N_WIDTH = 0, + parameter PORT_AFI_WE_N_WIDTH = 0, + parameter PORT_AFI_RST_N_WIDTH = 0, + parameter PORT_AFI_ACT_N_WIDTH = 0, + parameter PORT_AFI_REQ_N_WIDTH = 0, + parameter PORT_AFI_GNT_N_WIDTH = 0, + parameter PORT_AFI_ERR_N_WIDTH = 0, + parameter PORT_AFI_PAR_WIDTH = 0, + parameter PORT_AFI_CA_WIDTH = 0, + parameter PORT_AFI_REF_N_WIDTH = 0, + parameter PORT_AFI_WPS_N_WIDTH = 0, + parameter PORT_AFI_RPS_N_WIDTH = 0, + parameter PORT_AFI_DOFF_N_WIDTH = 0, + parameter PORT_AFI_LD_N_WIDTH = 0, + parameter PORT_AFI_RW_N_WIDTH = 0, + parameter PORT_AFI_LBK0_N_WIDTH = 0, + parameter PORT_AFI_LBK1_N_WIDTH = 0, + parameter PORT_AFI_CFG_N_WIDTH = 0, + parameter PORT_AFI_AP_WIDTH = 0, + parameter PORT_AFI_AINV_WIDTH = 0, + parameter PORT_AFI_DM_WIDTH = 0, + parameter PORT_AFI_DM_N_WIDTH = 0, + parameter PORT_AFI_BWS_N_WIDTH = 0, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 0, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 0, + parameter PORT_AFI_RDATA_DINV_WIDTH = 0, + parameter PORT_AFI_WDATA_DINV_WIDTH = 0, + parameter PORT_AFI_DQS_BURST_WIDTH = 0, + parameter PORT_AFI_WDATA_VALID_WIDTH = 0, + parameter PORT_AFI_WDATA_WIDTH = 0, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 0, + parameter PORT_AFI_RDATA_WIDTH = 0, + parameter PORT_AFI_RDATA_VALID_WIDTH = 0, + parameter PORT_AFI_RRANK_WIDTH = 0, + parameter PORT_AFI_WRANK_WIDTH = 0, + parameter PORT_AFI_ALERT_N_WIDTH = 0, + parameter PORT_AFI_PE_N_WIDTH = 0, + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 0, + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 0, + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 0, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 0, + parameter PORT_CTRL_AMM_RDATA_WIDTH = 0, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 0, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 0, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 0, + parameter PORT_CTRL_STROBE_WIDTH = 0, + parameter PORT_CTRL_STROBE_OE_WIDTH = 0, + parameter PORT_CTRL_DATA_OE_WIDTH = 0, + parameter PORT_CTRL_DATA_OUT_WIDTH = 0, + parameter PORT_CTRL_DATA_IN_WIDTH = 0, + parameter PORT_CTRL_RDATA_VALID_WIDTH = 0, + parameter PORT_CTRL_LOCKED_WIDTH = 0, + parameter PORT_CTRL_RDATA_ENABLE_WIDTH = 0, + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 0, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 0, + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 0, + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 0, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 0, + parameter PORT_HPS_EMIF_H2E_WIDTH = 0, + parameter PORT_HPS_EMIF_E2H_WIDTH = 0, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 0, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 0, + parameter PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH = 0, + parameter PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH = 0, + parameter PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH = 0, + parameter PORT_DFT_ND_PLL_CNTSEL_WIDTH = 0, + parameter PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH = 0, + parameter PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH = 0, + parameter PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH = 0, + parameter PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH = 0, + parameter PORT_CALBUS_ADDRESS_WIDTH = 0, + parameter PORT_CALBUS_WDATA_WIDTH = 0, + parameter PORT_CALBUS_RDATA_WIDTH = 0, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 0, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 0, + parameter PLL_MEM_CLK_FREQ_PS = 0, + parameter PLL_PHY_CLK_VCO_PHASE = 0, + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_VCO_FREQ_MHZ_STR = "", + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_REF_CLK_FREQ_MHZ_STR = "", + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_8 = "" +) ( + input logic local_reset_req, + output logic local_reset_done, + input logic pll_ref_clk, + output logic pll_ref_clk_out, + output logic pll_locked, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + output logic ac_parity_err, + input logic oct_rzqin, + output logic [0:0] mem_ck, + output logic [0:0] mem_ck_n, + output logic [16:0] mem_a, + output logic [0:0] mem_act_n, + output logic [1:0] mem_ba, + output logic [1:0] mem_bg, + output logic [0:0] mem_c, + output logic [0:0] mem_cke, + output logic [0:0] mem_cs_n, + output logic [0:0] mem_rm, + output logic [0:0] mem_odt, + output logic [0:0] mem_reset_n, + output logic [0:0] mem_par, + input logic [0:0] mem_alert_n, + inout tri [8:0] mem_dqs, + inout tri [8:0] mem_dqs_n, + inout tri [71:0] mem_dq, + inout tri [8:0] mem_dbi_n, + inout tri [0:0] mem_ck_bidir, + inout tri [0:0] mem_ck_bidir_n, + output logic [0:0] mem_dk, + output logic [0:0] mem_dk_n, + output logic [0:0] mem_dka, + output logic [0:0] mem_dka_n, + output logic [0:0] mem_dkb, + output logic [0:0] mem_dkb_n, + output logic [0:0] mem_k, + output logic [0:0] mem_k_n, + input logic [0:0] mem_req_n, + output logic [0:0] mem_gnt_n, + input logic [0:0] mem_err_n, + output logic [0:0] mem_ras_n, + output logic [0:0] mem_cas_n, + output logic [0:0] mem_we_n, + output logic [0:0] mem_ca, + output logic [0:0] mem_ref_n, + output logic [0:0] mem_wps_n, + output logic [0:0] mem_rps_n, + output logic [0:0] mem_doff_n, + output logic [0:0] mem_lda_n, + output logic [0:0] mem_ldb_n, + output logic [0:0] mem_rwa_n, + output logic [0:0] mem_rwb_n, + output logic [0:0] mem_lbk0_n, + output logic [0:0] mem_lbk1_n, + output logic [0:0] mem_cfg_n, + output logic [0:0] mem_ap, + output logic [0:0] mem_ainv, + output logic [0:0] mem_dm, + output logic [0:0] mem_bws_n, + output logic [0:0] mem_d, + inout tri [0:0] mem_dqa, + inout tri [0:0] mem_dqb, + inout tri [0:0] mem_dinva, + inout tri [0:0] mem_dinvb, + input logic [0:0] mem_q, + input logic [0:0] mem_qk, + input logic [0:0] mem_qk_n, + input logic [0:0] mem_qka, + input logic [0:0] mem_qka_n, + input logic [0:0] mem_qkb, + input logic [0:0] mem_qkb_n, + input logic [0:0] mem_cq, + input logic [0:0] mem_cq_n, + input logic [0:0] mem_pe_n, + output logic local_cal_success, + output logic local_cal_fail, + output logic afi_reset_n, + output logic afi_clk, + output logic afi_half_clk, + output logic emif_usr_reset_n, + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n_sec, + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic [31:0] clks_sharing_master_out, + input logic [31:0] clks_sharing_slave_in, + output logic [31:0] clks_sharing_slave_out, + output logic afi_cal_success, + output logic afi_cal_fail, + input logic afi_cal_req, + output logic [5:0] afi_rlat, + output logic [5:0] afi_wlat, + output logic [3:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic afi_mps_ack, + input logic [0:0] afi_addr, + input logic [0:0] afi_ba, + input logic [0:0] afi_bg, + input logic [0:0] afi_c, + input logic [0:0] afi_cke, + input logic [0:0] afi_cs_n, + input logic [0:0] afi_rm, + input logic [0:0] afi_odt, + input logic [0:0] afi_ras_n, + input logic [0:0] afi_cas_n, + input logic [0:0] afi_we_n, + input logic [0:0] afi_rst_n, + input logic [0:0] afi_act_n, + output logic [0:0] afi_req_n, + input logic [0:0] afi_gnt_n, + output logic [0:0] afi_err_n, + input logic [0:0] afi_par, + input logic [0:0] afi_ca, + input logic [0:0] afi_ref_n, + input logic [0:0] afi_wps_n, + input logic [0:0] afi_rps_n, + input logic [0:0] afi_doff_n, + input logic [0:0] afi_ld_n, + input logic [0:0] afi_rw_n, + input logic [0:0] afi_lbk0_n, + input logic [0:0] afi_lbk1_n, + input logic [0:0] afi_cfg_n, + input logic [0:0] afi_ap, + input logic [0:0] afi_ainv, + input logic [0:0] afi_dm, + input logic [0:0] afi_dm_n, + input logic [0:0] afi_bws_n, + output logic [0:0] afi_rdata_dbi_n, + input logic [0:0] afi_wdata_dbi_n, + output logic [0:0] afi_rdata_dinv, + input logic [0:0] afi_wdata_dinv, + input logic [0:0] afi_dqs_burst, + input logic [0:0] afi_wdata_valid, + input logic [0:0] afi_wdata, + input logic [0:0] afi_rdata_en_full, + output logic [0:0] afi_rdata, + output logic [0:0] afi_rdata_valid, + input logic [0:0] afi_rrank, + input logic [0:0] afi_wrank, + output logic [0:0] afi_alert_n, + output logic [0:0] afi_pe_n, + input logic ast_cmd_valid_0, + output logic ast_cmd_ready_0, + input logic [60:0] ast_cmd_data_0, + input logic ast_cmd_valid_1, + output logic ast_cmd_ready_1, + input logic [60:0] ast_cmd_data_1, + input logic ast_wr_valid_0, + output logic ast_wr_ready_0, + input logic [647:0] ast_wr_data_0, + input logic ast_wr_valid_1, + output logic ast_wr_ready_1, + input logic [647:0] ast_wr_data_1, + output logic ast_rd_valid_0, + input logic ast_rd_ready_0, + output logic [575:0] ast_rd_data_0, + output logic ast_rd_valid_1, + input logic ast_rd_ready_1, + output logic [575:0] ast_rd_data_1, + output logic amm_ready_0, + input logic amm_read_0, + input logic amm_write_0, + input logic [0:0] amm_address_0, + output logic [0:0] amm_readdata_0, + input logic [0:0] amm_writedata_0, + input logic [0:0] amm_burstcount_0, + input logic [0:0] amm_byteenable_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + output logic amm_ready_1, + input logic amm_read_1, + input logic amm_write_1, + input logic [0:0] amm_address_1, + output logic [0:0] amm_readdata_1, + input logic [0:0] amm_writedata_1, + input logic [0:0] amm_burstcount_1, + input logic [0:0] amm_byteenable_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + output logic amm_early_ready_0, + output logic amm_early_ready_1, + output logic amm_rd_type_0, + output logic amm_rd_type_1, + input logic [0:0] phylite_strobe, + input logic [0:0] phylite_strobe_oe, + input logic [0:0] phylite_data_oe, + input logic [0:0] phylite_data_from_core, + output logic [0:0] phylite_data_to_core, + output logic [0:0] phylite_rdata_valid, + output logic [0:0] phylite_interface_locked, + input logic [0:0] phylite_rdata_en, + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + input logic [3:0] ctrl_user_refresh_req, + input logic [15:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + input logic [3:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + output logic ctrl_will_refresh, + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + output logic ctrl_power_down_ack, + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + input logic [14:0] ctrl_ecc_write_info_0, + output logic [12:0] ctrl_ecc_rdata_id_0, + output logic [2:0] ctrl_ecc_read_info_0, + output logic [2:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + output logic [11:0] ctrl_ecc_wr_pointer_info_0, + input logic [14:0] ctrl_ecc_write_info_1, + output logic [12:0] ctrl_ecc_rdata_id_1, + output logic [2:0] ctrl_ecc_read_info_1, + output logic [2:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + output logic [11:0] ctrl_ecc_wr_pointer_info_1, + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [9:0] mmr_slave_address_0, + output logic [31:0] mmr_slave_readdata_0, + input logic [31:0] mmr_slave_writedata_0, + input logic [1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [9:0] mmr_slave_address_1, + output logic [31:0] mmr_slave_readdata_1, + input logic [31:0] mmr_slave_writedata_1, + input logic [1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1, + input logic [4095:0] hps_to_emif, + output logic [4095:0] emif_to_hps, + input logic [1:0] hps_to_emif_gp, + output logic [0:0] emif_to_hps_gp, + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [8:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [7:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [7:0] pa_dprio_readdata, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [3:0] pll_cnt_sel, + input logic [2:0] pll_num_phase_shifts, + output logic pll_phase_done, + input logic [3:0] pll_core_refclk, + output logic [1:0] dft_core_clk_buf_out, + output logic [1:0] dft_core_clk_locked, + input logic calbus_read, + input logic calbus_write, + input logic [19:0] calbus_address, + input logic [31:0] calbus_wdata, + output logic [31:0] calbus_rdata, + output logic [4095:0] calbus_seq_param_tbl, + input logic calbus_clk +); + timeunit 1ns; + timeprecision 1ps; + + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_top # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_TARGET_IS_ES (PHY_TARGET_IS_ES), + .PHY_TARGET_IS_ES2 (PHY_TARGET_IS_ES2), + .PHY_TARGET_IS_PRODUCTION (PHY_TARGET_IS_PRODUCTION), + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .PHY_CORE_CLKS_SHARING_ENUM (PHY_CORE_CLKS_SHARING_ENUM), + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_AC_CALIBRATED_OCT (PHY_AC_CALIBRATED_OCT), + .PHY_CK_CALIBRATED_OCT (PHY_CK_CALIBRATED_OCT), + .PHY_DATA_CALIBRATED_OCT (PHY_DATA_CALIBRATED_OCT), + .PHY_MIMIC_HPS_EMIF (PHY_MIMIC_HPS_EMIF), + .PLL_NUM_OF_EXTRA_CLKS (PLL_NUM_OF_EXTRA_CLKS), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .MEM_TTL_DATA_WIDTH (MEM_TTL_DATA_WIDTH), + .MEM_TTL_NUM_OF_READ_GROUPS (MEM_TTL_NUM_OF_READ_GROUPS), + .MEM_TTL_NUM_OF_WRITE_GROUPS (MEM_TTL_NUM_OF_WRITE_GROUPS), + .DIAG_SIM_REGTEST_MODE (DIAG_SIM_REGTEST_MODE), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_SEQ_RESET_AUTO_RELEASE (DIAG_SEQ_RESET_AUTO_RELEASE), + .DIAG_DB_RESET_AUTO_RELEASE (DIAG_DB_RESET_AUTO_RELEASE), + .DIAG_ECLIPSE_DEBUG (DIAG_ECLIPSE_DEBUG), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .DIAG_SIM_VERBOSE_LEVEL (DIAG_SIM_VERBOSE_LEVEL), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .SILICON_REV (SILICON_REV), + .IS_HPS (IS_HPS), + .USER_CLK_RATIO (USER_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_USE_CPA_LOCK (DIAG_USE_CPA_LOCK), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_READY_LATENCY (HMC_READY_LATENCY), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .SEQ_PT_SYN_CONTENT (SEQ_PT_SYN_CONTENT), + .SEQ_PT_SIM_CONTENT (SEQ_PT_SIM_CONTENT), + .REGISTER_AFI_C2P (REGISTER_AFI_C2P), + .REGISTER_AFI_P2C (REGISTER_AFI_P2C), + .REGISTER_AMM_P2C (REGISTER_AMM_P2C), + .REGISTER_AMM_C2P (REGISTER_AMM_C2P), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .LANES_USAGE_0 (LANES_USAGE_0), + .LANES_USAGE_1 (LANES_USAGE_1), + .LANES_USAGE_2 (LANES_USAGE_2), + .LANES_USAGE_3 (LANES_USAGE_3), + .LANES_USAGE_AUTOGEN_WCNT (LANES_USAGE_AUTOGEN_WCNT), + .PINS_USAGE_0 (PINS_USAGE_0), + .PINS_USAGE_1 (PINS_USAGE_1), + .PINS_USAGE_2 (PINS_USAGE_2), + .PINS_USAGE_3 (PINS_USAGE_3), + .PINS_USAGE_4 (PINS_USAGE_4), + .PINS_USAGE_5 (PINS_USAGE_5), + .PINS_USAGE_6 (PINS_USAGE_6), + .PINS_USAGE_7 (PINS_USAGE_7), + .PINS_USAGE_8 (PINS_USAGE_8), + .PINS_USAGE_9 (PINS_USAGE_9), + .PINS_USAGE_10 (PINS_USAGE_10), + .PINS_USAGE_11 (PINS_USAGE_11), + .PINS_USAGE_12 (PINS_USAGE_12), + .PINS_USAGE_AUTOGEN_WCNT (PINS_USAGE_AUTOGEN_WCNT), + .LANE_PIN_USAGE_0 (LANE_PIN_USAGE_0), + .LANE_PIN_USAGE_1 (LANE_PIN_USAGE_1), + .LANE_PIN_USAGE_2 (LANE_PIN_USAGE_2), + .LANE_PIN_USAGE_3 (LANE_PIN_USAGE_3), + .LANE_PIN_USAGE_4 (LANE_PIN_USAGE_4), + .LANE_PIN_USAGE_5 (LANE_PIN_USAGE_5), + .LANE_PIN_USAGE_6 (LANE_PIN_USAGE_6), + .LANE_PIN_USAGE_7 (LANE_PIN_USAGE_7), + .LANE_PIN_USAGE_8 (LANE_PIN_USAGE_8), + .LANE_PIN_USAGE_9 (LANE_PIN_USAGE_9), + .LANE_PIN_USAGE_10 (LANE_PIN_USAGE_10), + .LANE_PIN_USAGE_11 (LANE_PIN_USAGE_11), + .LANE_PIN_USAGE_12 (LANE_PIN_USAGE_12), + .LANE_PIN_USAGE_13 (LANE_PIN_USAGE_13), + .LANE_PIN_USAGE_14 (LANE_PIN_USAGE_14), + .LANE_PIN_USAGE_15 (LANE_PIN_USAGE_15), + .LANE_PIN_USAGE_16 (LANE_PIN_USAGE_16), + .LANE_PIN_USAGE_17 (LANE_PIN_USAGE_17), + .LANE_PIN_USAGE_18 (LANE_PIN_USAGE_18), + .LANE_PIN_USAGE_19 (LANE_PIN_USAGE_19), + .LANE_PIN_USAGE_20 (LANE_PIN_USAGE_20), + .LANE_PIN_USAGE_21 (LANE_PIN_USAGE_21), + .LANE_PIN_USAGE_22 (LANE_PIN_USAGE_22), + .LANE_PIN_USAGE_23 (LANE_PIN_USAGE_23), + .LANE_PIN_USAGE_24 (LANE_PIN_USAGE_24), + .LANE_PIN_USAGE_25 (LANE_PIN_USAGE_25), + .LANE_PIN_USAGE_26 (LANE_PIN_USAGE_26), + .LANE_PIN_USAGE_27 (LANE_PIN_USAGE_27), + .LANE_PIN_USAGE_28 (LANE_PIN_USAGE_28), + .LANE_PIN_USAGE_29 (LANE_PIN_USAGE_29), + .LANE_PIN_USAGE_30 (LANE_PIN_USAGE_30), + .LANE_PIN_USAGE_31 (LANE_PIN_USAGE_31), + .LANE_PIN_USAGE_32 (LANE_PIN_USAGE_32), + .LANE_PIN_USAGE_33 (LANE_PIN_USAGE_33), + .LANE_PIN_USAGE_34 (LANE_PIN_USAGE_34), + .LANE_PIN_USAGE_35 (LANE_PIN_USAGE_35), + .LANE_PIN_USAGE_36 (LANE_PIN_USAGE_36), + .LANE_PIN_USAGE_37 (LANE_PIN_USAGE_37), + .LANE_PIN_USAGE_38 (LANE_PIN_USAGE_38), + .LANE_PIN_USAGE_39 (LANE_PIN_USAGE_39), + .LANE_PIN_USAGE_40 (LANE_PIN_USAGE_40), + .LANE_PIN_USAGE_41 (LANE_PIN_USAGE_41), + .LANE_PIN_USAGE_42 (LANE_PIN_USAGE_42), + .LANE_PIN_USAGE_43 (LANE_PIN_USAGE_43), + .LANE_PIN_USAGE_44 (LANE_PIN_USAGE_44), + .LANE_PIN_USAGE_45 (LANE_PIN_USAGE_45), + .LANE_PIN_USAGE_46 (LANE_PIN_USAGE_46), + .LANE_PIN_USAGE_47 (LANE_PIN_USAGE_47), + .LANE_PIN_USAGE_48 (LANE_PIN_USAGE_48), + .LANE_PIN_USAGE_49 (LANE_PIN_USAGE_49), + .LANE_PIN_USAGE_50 (LANE_PIN_USAGE_50), + .LANE_PIN_USAGE_51 (LANE_PIN_USAGE_51), + .LANE_PIN_USAGE_AUTOGEN_WCNT (LANE_PIN_USAGE_AUTOGEN_WCNT), + .PINS_RATE_0 (PINS_RATE_0), + .PINS_RATE_1 (PINS_RATE_1), + .PINS_RATE_2 (PINS_RATE_2), + .PINS_RATE_3 (PINS_RATE_3), + .PINS_RATE_4 (PINS_RATE_4), + .PINS_RATE_5 (PINS_RATE_5), + .PINS_RATE_6 (PINS_RATE_6), + .PINS_RATE_7 (PINS_RATE_7), + .PINS_RATE_8 (PINS_RATE_8), + .PINS_RATE_9 (PINS_RATE_9), + .PINS_RATE_10 (PINS_RATE_10), + .PINS_RATE_11 (PINS_RATE_11), + .PINS_RATE_12 (PINS_RATE_12), + .PINS_RATE_AUTOGEN_WCNT (PINS_RATE_AUTOGEN_WCNT), + .DB_PINS_PROC_MODE_0 (DB_PINS_PROC_MODE_0), + .DB_PINS_PROC_MODE_1 (DB_PINS_PROC_MODE_1), + .DB_PINS_PROC_MODE_2 (DB_PINS_PROC_MODE_2), + .DB_PINS_PROC_MODE_3 (DB_PINS_PROC_MODE_3), + .DB_PINS_PROC_MODE_4 (DB_PINS_PROC_MODE_4), + .DB_PINS_PROC_MODE_5 (DB_PINS_PROC_MODE_5), + .DB_PINS_PROC_MODE_6 (DB_PINS_PROC_MODE_6), + .DB_PINS_PROC_MODE_7 (DB_PINS_PROC_MODE_7), + .DB_PINS_PROC_MODE_8 (DB_PINS_PROC_MODE_8), + .DB_PINS_PROC_MODE_9 (DB_PINS_PROC_MODE_9), + .DB_PINS_PROC_MODE_10 (DB_PINS_PROC_MODE_10), + .DB_PINS_PROC_MODE_11 (DB_PINS_PROC_MODE_11), + .DB_PINS_PROC_MODE_12 (DB_PINS_PROC_MODE_12), + .DB_PINS_PROC_MODE_13 (DB_PINS_PROC_MODE_13), + .DB_PINS_PROC_MODE_14 (DB_PINS_PROC_MODE_14), + .DB_PINS_PROC_MODE_15 (DB_PINS_PROC_MODE_15), + .DB_PINS_PROC_MODE_16 (DB_PINS_PROC_MODE_16), + .DB_PINS_PROC_MODE_17 (DB_PINS_PROC_MODE_17), + .DB_PINS_PROC_MODE_18 (DB_PINS_PROC_MODE_18), + .DB_PINS_PROC_MODE_19 (DB_PINS_PROC_MODE_19), + .DB_PINS_PROC_MODE_20 (DB_PINS_PROC_MODE_20), + .DB_PINS_PROC_MODE_21 (DB_PINS_PROC_MODE_21), + .DB_PINS_PROC_MODE_22 (DB_PINS_PROC_MODE_22), + .DB_PINS_PROC_MODE_23 (DB_PINS_PROC_MODE_23), + .DB_PINS_PROC_MODE_24 (DB_PINS_PROC_MODE_24), + .DB_PINS_PROC_MODE_25 (DB_PINS_PROC_MODE_25), + .DB_PINS_PROC_MODE_26 (DB_PINS_PROC_MODE_26), + .DB_PINS_PROC_MODE_27 (DB_PINS_PROC_MODE_27), + .DB_PINS_PROC_MODE_28 (DB_PINS_PROC_MODE_28), + .DB_PINS_PROC_MODE_29 (DB_PINS_PROC_MODE_29), + .DB_PINS_PROC_MODE_30 (DB_PINS_PROC_MODE_30), + .DB_PINS_PROC_MODE_31 (DB_PINS_PROC_MODE_31), + .DB_PINS_PROC_MODE_32 (DB_PINS_PROC_MODE_32), + .DB_PINS_PROC_MODE_33 (DB_PINS_PROC_MODE_33), + .DB_PINS_PROC_MODE_34 (DB_PINS_PROC_MODE_34), + .DB_PINS_PROC_MODE_35 (DB_PINS_PROC_MODE_35), + .DB_PINS_PROC_MODE_36 (DB_PINS_PROC_MODE_36), + .DB_PINS_PROC_MODE_37 (DB_PINS_PROC_MODE_37), + .DB_PINS_PROC_MODE_38 (DB_PINS_PROC_MODE_38), + .DB_PINS_PROC_MODE_39 (DB_PINS_PROC_MODE_39), + .DB_PINS_PROC_MODE_40 (DB_PINS_PROC_MODE_40), + .DB_PINS_PROC_MODE_41 (DB_PINS_PROC_MODE_41), + .DB_PINS_PROC_MODE_42 (DB_PINS_PROC_MODE_42), + .DB_PINS_PROC_MODE_43 (DB_PINS_PROC_MODE_43), + .DB_PINS_PROC_MODE_44 (DB_PINS_PROC_MODE_44), + .DB_PINS_PROC_MODE_45 (DB_PINS_PROC_MODE_45), + .DB_PINS_PROC_MODE_46 (DB_PINS_PROC_MODE_46), + .DB_PINS_PROC_MODE_47 (DB_PINS_PROC_MODE_47), + .DB_PINS_PROC_MODE_48 (DB_PINS_PROC_MODE_48), + .DB_PINS_PROC_MODE_49 (DB_PINS_PROC_MODE_49), + .DB_PINS_PROC_MODE_50 (DB_PINS_PROC_MODE_50), + .DB_PINS_PROC_MODE_51 (DB_PINS_PROC_MODE_51), + .DB_PINS_PROC_MODE_52 (DB_PINS_PROC_MODE_52), + .DB_PINS_PROC_MODE_53 (DB_PINS_PROC_MODE_53), + .DB_PINS_PROC_MODE_54 (DB_PINS_PROC_MODE_54), + .DB_PINS_PROC_MODE_55 (DB_PINS_PROC_MODE_55), + .DB_PINS_PROC_MODE_56 (DB_PINS_PROC_MODE_56), + .DB_PINS_PROC_MODE_57 (DB_PINS_PROC_MODE_57), + .DB_PINS_PROC_MODE_58 (DB_PINS_PROC_MODE_58), + .DB_PINS_PROC_MODE_59 (DB_PINS_PROC_MODE_59), + .DB_PINS_PROC_MODE_60 (DB_PINS_PROC_MODE_60), + .DB_PINS_PROC_MODE_61 (DB_PINS_PROC_MODE_61), + .DB_PINS_PROC_MODE_62 (DB_PINS_PROC_MODE_62), + .DB_PINS_PROC_MODE_63 (DB_PINS_PROC_MODE_63), + .DB_PINS_PROC_MODE_AUTOGEN_WCNT (DB_PINS_PROC_MODE_AUTOGEN_WCNT), + .PINS_DATA_IN_MODE_0 (PINS_DATA_IN_MODE_0), + .PINS_DATA_IN_MODE_1 (PINS_DATA_IN_MODE_1), + .PINS_DATA_IN_MODE_2 (PINS_DATA_IN_MODE_2), + .PINS_DATA_IN_MODE_3 (PINS_DATA_IN_MODE_3), + .PINS_DATA_IN_MODE_4 (PINS_DATA_IN_MODE_4), + .PINS_DATA_IN_MODE_5 (PINS_DATA_IN_MODE_5), + .PINS_DATA_IN_MODE_6 (PINS_DATA_IN_MODE_6), + .PINS_DATA_IN_MODE_7 (PINS_DATA_IN_MODE_7), + .PINS_DATA_IN_MODE_8 (PINS_DATA_IN_MODE_8), + .PINS_DATA_IN_MODE_9 (PINS_DATA_IN_MODE_9), + .PINS_DATA_IN_MODE_10 (PINS_DATA_IN_MODE_10), + .PINS_DATA_IN_MODE_11 (PINS_DATA_IN_MODE_11), + .PINS_DATA_IN_MODE_12 (PINS_DATA_IN_MODE_12), + .PINS_DATA_IN_MODE_13 (PINS_DATA_IN_MODE_13), + .PINS_DATA_IN_MODE_14 (PINS_DATA_IN_MODE_14), + .PINS_DATA_IN_MODE_15 (PINS_DATA_IN_MODE_15), + .PINS_DATA_IN_MODE_16 (PINS_DATA_IN_MODE_16), + .PINS_DATA_IN_MODE_17 (PINS_DATA_IN_MODE_17), + .PINS_DATA_IN_MODE_18 (PINS_DATA_IN_MODE_18), + .PINS_DATA_IN_MODE_19 (PINS_DATA_IN_MODE_19), + .PINS_DATA_IN_MODE_20 (PINS_DATA_IN_MODE_20), + .PINS_DATA_IN_MODE_21 (PINS_DATA_IN_MODE_21), + .PINS_DATA_IN_MODE_22 (PINS_DATA_IN_MODE_22), + .PINS_DATA_IN_MODE_23 (PINS_DATA_IN_MODE_23), + .PINS_DATA_IN_MODE_24 (PINS_DATA_IN_MODE_24), + .PINS_DATA_IN_MODE_25 (PINS_DATA_IN_MODE_25), + .PINS_DATA_IN_MODE_26 (PINS_DATA_IN_MODE_26), + .PINS_DATA_IN_MODE_27 (PINS_DATA_IN_MODE_27), + .PINS_DATA_IN_MODE_28 (PINS_DATA_IN_MODE_28), + .PINS_DATA_IN_MODE_29 (PINS_DATA_IN_MODE_29), + .PINS_DATA_IN_MODE_30 (PINS_DATA_IN_MODE_30), + .PINS_DATA_IN_MODE_31 (PINS_DATA_IN_MODE_31), + .PINS_DATA_IN_MODE_32 (PINS_DATA_IN_MODE_32), + .PINS_DATA_IN_MODE_33 (PINS_DATA_IN_MODE_33), + .PINS_DATA_IN_MODE_34 (PINS_DATA_IN_MODE_34), + .PINS_DATA_IN_MODE_35 (PINS_DATA_IN_MODE_35), + .PINS_DATA_IN_MODE_36 (PINS_DATA_IN_MODE_36), + .PINS_DATA_IN_MODE_37 (PINS_DATA_IN_MODE_37), + .PINS_DATA_IN_MODE_38 (PINS_DATA_IN_MODE_38), + .PINS_DATA_IN_MODE_AUTOGEN_WCNT (PINS_DATA_IN_MODE_AUTOGEN_WCNT), + .PINS_C2L_DRIVEN_0 (PINS_C2L_DRIVEN_0), + .PINS_C2L_DRIVEN_1 (PINS_C2L_DRIVEN_1), + .PINS_C2L_DRIVEN_2 (PINS_C2L_DRIVEN_2), + .PINS_C2L_DRIVEN_3 (PINS_C2L_DRIVEN_3), + .PINS_C2L_DRIVEN_4 (PINS_C2L_DRIVEN_4), + .PINS_C2L_DRIVEN_5 (PINS_C2L_DRIVEN_5), + .PINS_C2L_DRIVEN_6 (PINS_C2L_DRIVEN_6), + .PINS_C2L_DRIVEN_7 (PINS_C2L_DRIVEN_7), + .PINS_C2L_DRIVEN_8 (PINS_C2L_DRIVEN_8), + .PINS_C2L_DRIVEN_9 (PINS_C2L_DRIVEN_9), + .PINS_C2L_DRIVEN_10 (PINS_C2L_DRIVEN_10), + .PINS_C2L_DRIVEN_11 (PINS_C2L_DRIVEN_11), + .PINS_C2L_DRIVEN_12 (PINS_C2L_DRIVEN_12), + .PINS_C2L_DRIVEN_AUTOGEN_WCNT (PINS_C2L_DRIVEN_AUTOGEN_WCNT), + .PINS_OCT_MODE_0 (PINS_OCT_MODE_0), + .PINS_OCT_MODE_1 (PINS_OCT_MODE_1), + .PINS_OCT_MODE_2 (PINS_OCT_MODE_2), + .PINS_OCT_MODE_3 (PINS_OCT_MODE_3), + .PINS_OCT_MODE_4 (PINS_OCT_MODE_4), + .PINS_OCT_MODE_5 (PINS_OCT_MODE_5), + .PINS_OCT_MODE_6 (PINS_OCT_MODE_6), + .PINS_OCT_MODE_7 (PINS_OCT_MODE_7), + .PINS_OCT_MODE_8 (PINS_OCT_MODE_8), + .PINS_OCT_MODE_9 (PINS_OCT_MODE_9), + .PINS_OCT_MODE_10 (PINS_OCT_MODE_10), + .PINS_OCT_MODE_11 (PINS_OCT_MODE_11), + .PINS_OCT_MODE_12 (PINS_OCT_MODE_12), + .PINS_OCT_MODE_AUTOGEN_WCNT (PINS_OCT_MODE_AUTOGEN_WCNT), + .PINS_DCC_SPLIT_0 (PINS_DCC_SPLIT_0), + .PINS_DCC_SPLIT_1 (PINS_DCC_SPLIT_1), + .PINS_DCC_SPLIT_2 (PINS_DCC_SPLIT_2), + .PINS_DCC_SPLIT_3 (PINS_DCC_SPLIT_3), + .PINS_DCC_SPLIT_4 (PINS_DCC_SPLIT_4), + .PINS_DCC_SPLIT_5 (PINS_DCC_SPLIT_5), + .PINS_DCC_SPLIT_6 (PINS_DCC_SPLIT_6), + .PINS_DCC_SPLIT_7 (PINS_DCC_SPLIT_7), + .PINS_DCC_SPLIT_8 (PINS_DCC_SPLIT_8), + .PINS_DCC_SPLIT_9 (PINS_DCC_SPLIT_9), + .PINS_DCC_SPLIT_10 (PINS_DCC_SPLIT_10), + .PINS_DCC_SPLIT_11 (PINS_DCC_SPLIT_11), + .PINS_DCC_SPLIT_12 (PINS_DCC_SPLIT_12), + .PINS_DCC_SPLIT_AUTOGEN_WCNT (PINS_DCC_SPLIT_AUTOGEN_WCNT), + .UNUSED_MEM_PINS_PINLOC_0 (UNUSED_MEM_PINS_PINLOC_0), + .UNUSED_MEM_PINS_PINLOC_1 (UNUSED_MEM_PINS_PINLOC_1), + .UNUSED_MEM_PINS_PINLOC_2 (UNUSED_MEM_PINS_PINLOC_2), + .UNUSED_MEM_PINS_PINLOC_3 (UNUSED_MEM_PINS_PINLOC_3), + .UNUSED_MEM_PINS_PINLOC_4 (UNUSED_MEM_PINS_PINLOC_4), + .UNUSED_MEM_PINS_PINLOC_5 (UNUSED_MEM_PINS_PINLOC_5), + .UNUSED_MEM_PINS_PINLOC_6 (UNUSED_MEM_PINS_PINLOC_6), + .UNUSED_MEM_PINS_PINLOC_7 (UNUSED_MEM_PINS_PINLOC_7), + .UNUSED_MEM_PINS_PINLOC_8 (UNUSED_MEM_PINS_PINLOC_8), + .UNUSED_MEM_PINS_PINLOC_9 (UNUSED_MEM_PINS_PINLOC_9), + .UNUSED_MEM_PINS_PINLOC_10 (UNUSED_MEM_PINS_PINLOC_10), + .UNUSED_MEM_PINS_PINLOC_11 (UNUSED_MEM_PINS_PINLOC_11), + .UNUSED_MEM_PINS_PINLOC_12 (UNUSED_MEM_PINS_PINLOC_12), + .UNUSED_MEM_PINS_PINLOC_13 (UNUSED_MEM_PINS_PINLOC_13), + .UNUSED_MEM_PINS_PINLOC_14 (UNUSED_MEM_PINS_PINLOC_14), + .UNUSED_MEM_PINS_PINLOC_15 (UNUSED_MEM_PINS_PINLOC_15), + .UNUSED_MEM_PINS_PINLOC_16 (UNUSED_MEM_PINS_PINLOC_16), + .UNUSED_MEM_PINS_PINLOC_17 (UNUSED_MEM_PINS_PINLOC_17), + .UNUSED_MEM_PINS_PINLOC_18 (UNUSED_MEM_PINS_PINLOC_18), + .UNUSED_MEM_PINS_PINLOC_19 (UNUSED_MEM_PINS_PINLOC_19), + .UNUSED_MEM_PINS_PINLOC_20 (UNUSED_MEM_PINS_PINLOC_20), + .UNUSED_MEM_PINS_PINLOC_21 (UNUSED_MEM_PINS_PINLOC_21), + .UNUSED_MEM_PINS_PINLOC_22 (UNUSED_MEM_PINS_PINLOC_22), + .UNUSED_MEM_PINS_PINLOC_23 (UNUSED_MEM_PINS_PINLOC_23), + .UNUSED_MEM_PINS_PINLOC_24 (UNUSED_MEM_PINS_PINLOC_24), + .UNUSED_MEM_PINS_PINLOC_25 (UNUSED_MEM_PINS_PINLOC_25), + .UNUSED_MEM_PINS_PINLOC_26 (UNUSED_MEM_PINS_PINLOC_26), + .UNUSED_MEM_PINS_PINLOC_27 (UNUSED_MEM_PINS_PINLOC_27), + .UNUSED_MEM_PINS_PINLOC_28 (UNUSED_MEM_PINS_PINLOC_28), + .UNUSED_MEM_PINS_PINLOC_29 (UNUSED_MEM_PINS_PINLOC_29), + .UNUSED_MEM_PINS_PINLOC_30 (UNUSED_MEM_PINS_PINLOC_30), + .UNUSED_MEM_PINS_PINLOC_31 (UNUSED_MEM_PINS_PINLOC_31), + .UNUSED_MEM_PINS_PINLOC_32 (UNUSED_MEM_PINS_PINLOC_32), + .UNUSED_MEM_PINS_PINLOC_33 (UNUSED_MEM_PINS_PINLOC_33), + .UNUSED_MEM_PINS_PINLOC_34 (UNUSED_MEM_PINS_PINLOC_34), + .UNUSED_MEM_PINS_PINLOC_35 (UNUSED_MEM_PINS_PINLOC_35), + .UNUSED_MEM_PINS_PINLOC_36 (UNUSED_MEM_PINS_PINLOC_36), + .UNUSED_MEM_PINS_PINLOC_37 (UNUSED_MEM_PINS_PINLOC_37), + .UNUSED_MEM_PINS_PINLOC_38 (UNUSED_MEM_PINS_PINLOC_38), + .UNUSED_MEM_PINS_PINLOC_39 (UNUSED_MEM_PINS_PINLOC_39), + .UNUSED_MEM_PINS_PINLOC_40 (UNUSED_MEM_PINS_PINLOC_40), + .UNUSED_MEM_PINS_PINLOC_41 (UNUSED_MEM_PINS_PINLOC_41), + .UNUSED_MEM_PINS_PINLOC_42 (UNUSED_MEM_PINS_PINLOC_42), + .UNUSED_MEM_PINS_PINLOC_43 (UNUSED_MEM_PINS_PINLOC_43), + .UNUSED_MEM_PINS_PINLOC_44 (UNUSED_MEM_PINS_PINLOC_44), + .UNUSED_MEM_PINS_PINLOC_45 (UNUSED_MEM_PINS_PINLOC_45), + .UNUSED_MEM_PINS_PINLOC_46 (UNUSED_MEM_PINS_PINLOC_46), + .UNUSED_MEM_PINS_PINLOC_47 (UNUSED_MEM_PINS_PINLOC_47), + .UNUSED_MEM_PINS_PINLOC_48 (UNUSED_MEM_PINS_PINLOC_48), + .UNUSED_MEM_PINS_PINLOC_49 (UNUSED_MEM_PINS_PINLOC_49), + .UNUSED_MEM_PINS_PINLOC_50 (UNUSED_MEM_PINS_PINLOC_50), + .UNUSED_MEM_PINS_PINLOC_51 (UNUSED_MEM_PINS_PINLOC_51), + .UNUSED_MEM_PINS_PINLOC_52 (UNUSED_MEM_PINS_PINLOC_52), + .UNUSED_MEM_PINS_PINLOC_53 (UNUSED_MEM_PINS_PINLOC_53), + .UNUSED_MEM_PINS_PINLOC_54 (UNUSED_MEM_PINS_PINLOC_54), + .UNUSED_MEM_PINS_PINLOC_55 (UNUSED_MEM_PINS_PINLOC_55), + .UNUSED_MEM_PINS_PINLOC_56 (UNUSED_MEM_PINS_PINLOC_56), + .UNUSED_MEM_PINS_PINLOC_57 (UNUSED_MEM_PINS_PINLOC_57), + .UNUSED_MEM_PINS_PINLOC_58 (UNUSED_MEM_PINS_PINLOC_58), + .UNUSED_MEM_PINS_PINLOC_59 (UNUSED_MEM_PINS_PINLOC_59), + .UNUSED_MEM_PINS_PINLOC_60 (UNUSED_MEM_PINS_PINLOC_60), + .UNUSED_MEM_PINS_PINLOC_61 (UNUSED_MEM_PINS_PINLOC_61), + .UNUSED_MEM_PINS_PINLOC_62 (UNUSED_MEM_PINS_PINLOC_62), + .UNUSED_MEM_PINS_PINLOC_63 (UNUSED_MEM_PINS_PINLOC_63), + .UNUSED_MEM_PINS_PINLOC_64 (UNUSED_MEM_PINS_PINLOC_64), + .UNUSED_MEM_PINS_PINLOC_65 (UNUSED_MEM_PINS_PINLOC_65), + .UNUSED_MEM_PINS_PINLOC_66 (UNUSED_MEM_PINS_PINLOC_66), + .UNUSED_MEM_PINS_PINLOC_67 (UNUSED_MEM_PINS_PINLOC_67), + .UNUSED_MEM_PINS_PINLOC_68 (UNUSED_MEM_PINS_PINLOC_68), + .UNUSED_MEM_PINS_PINLOC_69 (UNUSED_MEM_PINS_PINLOC_69), + .UNUSED_MEM_PINS_PINLOC_70 (UNUSED_MEM_PINS_PINLOC_70), + .UNUSED_MEM_PINS_PINLOC_71 (UNUSED_MEM_PINS_PINLOC_71), + .UNUSED_MEM_PINS_PINLOC_72 (UNUSED_MEM_PINS_PINLOC_72), + .UNUSED_MEM_PINS_PINLOC_73 (UNUSED_MEM_PINS_PINLOC_73), + .UNUSED_MEM_PINS_PINLOC_74 (UNUSED_MEM_PINS_PINLOC_74), + .UNUSED_MEM_PINS_PINLOC_75 (UNUSED_MEM_PINS_PINLOC_75), + .UNUSED_MEM_PINS_PINLOC_76 (UNUSED_MEM_PINS_PINLOC_76), + .UNUSED_MEM_PINS_PINLOC_77 (UNUSED_MEM_PINS_PINLOC_77), + .UNUSED_MEM_PINS_PINLOC_78 (UNUSED_MEM_PINS_PINLOC_78), + .UNUSED_MEM_PINS_PINLOC_79 (UNUSED_MEM_PINS_PINLOC_79), + .UNUSED_MEM_PINS_PINLOC_80 (UNUSED_MEM_PINS_PINLOC_80), + .UNUSED_MEM_PINS_PINLOC_81 (UNUSED_MEM_PINS_PINLOC_81), + .UNUSED_MEM_PINS_PINLOC_82 (UNUSED_MEM_PINS_PINLOC_82), + .UNUSED_MEM_PINS_PINLOC_83 (UNUSED_MEM_PINS_PINLOC_83), + .UNUSED_MEM_PINS_PINLOC_84 (UNUSED_MEM_PINS_PINLOC_84), + .UNUSED_MEM_PINS_PINLOC_85 (UNUSED_MEM_PINS_PINLOC_85), + .UNUSED_MEM_PINS_PINLOC_86 (UNUSED_MEM_PINS_PINLOC_86), + .UNUSED_MEM_PINS_PINLOC_87 (UNUSED_MEM_PINS_PINLOC_87), + .UNUSED_MEM_PINS_PINLOC_88 (UNUSED_MEM_PINS_PINLOC_88), + .UNUSED_MEM_PINS_PINLOC_89 (UNUSED_MEM_PINS_PINLOC_89), + .UNUSED_MEM_PINS_PINLOC_90 (UNUSED_MEM_PINS_PINLOC_90), + .UNUSED_MEM_PINS_PINLOC_91 (UNUSED_MEM_PINS_PINLOC_91), + .UNUSED_MEM_PINS_PINLOC_92 (UNUSED_MEM_PINS_PINLOC_92), + .UNUSED_MEM_PINS_PINLOC_93 (UNUSED_MEM_PINS_PINLOC_93), + .UNUSED_MEM_PINS_PINLOC_94 (UNUSED_MEM_PINS_PINLOC_94), + .UNUSED_MEM_PINS_PINLOC_95 (UNUSED_MEM_PINS_PINLOC_95), + .UNUSED_MEM_PINS_PINLOC_96 (UNUSED_MEM_PINS_PINLOC_96), + .UNUSED_MEM_PINS_PINLOC_97 (UNUSED_MEM_PINS_PINLOC_97), + .UNUSED_MEM_PINS_PINLOC_98 (UNUSED_MEM_PINS_PINLOC_98), + .UNUSED_MEM_PINS_PINLOC_99 (UNUSED_MEM_PINS_PINLOC_99), + .UNUSED_MEM_PINS_PINLOC_100 (UNUSED_MEM_PINS_PINLOC_100), + .UNUSED_MEM_PINS_PINLOC_101 (UNUSED_MEM_PINS_PINLOC_101), + .UNUSED_MEM_PINS_PINLOC_102 (UNUSED_MEM_PINS_PINLOC_102), + .UNUSED_MEM_PINS_PINLOC_103 (UNUSED_MEM_PINS_PINLOC_103), + .UNUSED_MEM_PINS_PINLOC_104 (UNUSED_MEM_PINS_PINLOC_104), + .UNUSED_MEM_PINS_PINLOC_105 (UNUSED_MEM_PINS_PINLOC_105), + .UNUSED_MEM_PINS_PINLOC_106 (UNUSED_MEM_PINS_PINLOC_106), + .UNUSED_MEM_PINS_PINLOC_107 (UNUSED_MEM_PINS_PINLOC_107), + .UNUSED_MEM_PINS_PINLOC_108 (UNUSED_MEM_PINS_PINLOC_108), + .UNUSED_MEM_PINS_PINLOC_109 (UNUSED_MEM_PINS_PINLOC_109), + .UNUSED_MEM_PINS_PINLOC_110 (UNUSED_MEM_PINS_PINLOC_110), + .UNUSED_MEM_PINS_PINLOC_111 (UNUSED_MEM_PINS_PINLOC_111), + .UNUSED_MEM_PINS_PINLOC_112 (UNUSED_MEM_PINS_PINLOC_112), + .UNUSED_MEM_PINS_PINLOC_113 (UNUSED_MEM_PINS_PINLOC_113), + .UNUSED_MEM_PINS_PINLOC_114 (UNUSED_MEM_PINS_PINLOC_114), + .UNUSED_MEM_PINS_PINLOC_115 (UNUSED_MEM_PINS_PINLOC_115), + .UNUSED_MEM_PINS_PINLOC_116 (UNUSED_MEM_PINS_PINLOC_116), + .UNUSED_MEM_PINS_PINLOC_117 (UNUSED_MEM_PINS_PINLOC_117), + .UNUSED_MEM_PINS_PINLOC_118 (UNUSED_MEM_PINS_PINLOC_118), + .UNUSED_MEM_PINS_PINLOC_119 (UNUSED_MEM_PINS_PINLOC_119), + .UNUSED_MEM_PINS_PINLOC_120 (UNUSED_MEM_PINS_PINLOC_120), + .UNUSED_MEM_PINS_PINLOC_121 (UNUSED_MEM_PINS_PINLOC_121), + .UNUSED_MEM_PINS_PINLOC_122 (UNUSED_MEM_PINS_PINLOC_122), + .UNUSED_MEM_PINS_PINLOC_123 (UNUSED_MEM_PINS_PINLOC_123), + .UNUSED_MEM_PINS_PINLOC_124 (UNUSED_MEM_PINS_PINLOC_124), + .UNUSED_MEM_PINS_PINLOC_125 (UNUSED_MEM_PINS_PINLOC_125), + .UNUSED_MEM_PINS_PINLOC_126 (UNUSED_MEM_PINS_PINLOC_126), + .UNUSED_MEM_PINS_PINLOC_127 (UNUSED_MEM_PINS_PINLOC_127), + .UNUSED_MEM_PINS_PINLOC_128 (UNUSED_MEM_PINS_PINLOC_128), + .UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT (UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT), + .UNUSED_DQS_BUSES_LANELOC_0 (UNUSED_DQS_BUSES_LANELOC_0), + .UNUSED_DQS_BUSES_LANELOC_1 (UNUSED_DQS_BUSES_LANELOC_1), + .UNUSED_DQS_BUSES_LANELOC_2 (UNUSED_DQS_BUSES_LANELOC_2), + .UNUSED_DQS_BUSES_LANELOC_3 (UNUSED_DQS_BUSES_LANELOC_3), + .UNUSED_DQS_BUSES_LANELOC_4 (UNUSED_DQS_BUSES_LANELOC_4), + .UNUSED_DQS_BUSES_LANELOC_5 (UNUSED_DQS_BUSES_LANELOC_5), + .UNUSED_DQS_BUSES_LANELOC_6 (UNUSED_DQS_BUSES_LANELOC_6), + .UNUSED_DQS_BUSES_LANELOC_7 (UNUSED_DQS_BUSES_LANELOC_7), + .UNUSED_DQS_BUSES_LANELOC_8 (UNUSED_DQS_BUSES_LANELOC_8), + .UNUSED_DQS_BUSES_LANELOC_9 (UNUSED_DQS_BUSES_LANELOC_9), + .UNUSED_DQS_BUSES_LANELOC_10 (UNUSED_DQS_BUSES_LANELOC_10), + .UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT (UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT), + .DBC_EXTRA_PIPE_STAGE_EN (DBC_EXTRA_PIPE_STAGE_EN), + .DBC_PIPE_LATS_0 (DBC_PIPE_LATS_0), + .DBC_PIPE_LATS_1 (DBC_PIPE_LATS_1), + .DBC_PIPE_LATS_2 (DBC_PIPE_LATS_2), + .DBC_PIPE_LATS_3 (DBC_PIPE_LATS_3), + .DBC_PIPE_LATS_4 (DBC_PIPE_LATS_4), + .DBC_PIPE_LATS_AUTOGEN_WCNT (DBC_PIPE_LATS_AUTOGEN_WCNT), + .DB_PTR_PIPELINE_DEPTHS_0 (DB_PTR_PIPELINE_DEPTHS_0), + .DB_PTR_PIPELINE_DEPTHS_1 (DB_PTR_PIPELINE_DEPTHS_1), + .DB_PTR_PIPELINE_DEPTHS_2 (DB_PTR_PIPELINE_DEPTHS_2), + .DB_PTR_PIPELINE_DEPTHS_3 (DB_PTR_PIPELINE_DEPTHS_3), + .DB_PTR_PIPELINE_DEPTHS_4 (DB_PTR_PIPELINE_DEPTHS_4), + .DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT (DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT), + .DB_SEQ_RD_EN_FULL_PIPELINES_0 (DB_SEQ_RD_EN_FULL_PIPELINES_0), + .DB_SEQ_RD_EN_FULL_PIPELINES_1 (DB_SEQ_RD_EN_FULL_PIPELINES_1), + .DB_SEQ_RD_EN_FULL_PIPELINES_2 (DB_SEQ_RD_EN_FULL_PIPELINES_2), + .DB_SEQ_RD_EN_FULL_PIPELINES_3 (DB_SEQ_RD_EN_FULL_PIPELINES_3), + .DB_SEQ_RD_EN_FULL_PIPELINES_4 (DB_SEQ_RD_EN_FULL_PIPELINES_4), + .DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT (DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT), + .CENTER_TIDS_0 (CENTER_TIDS_0), + .CENTER_TIDS_1 (CENTER_TIDS_1), + .CENTER_TIDS_2 (CENTER_TIDS_2), + .CENTER_TIDS_AUTOGEN_WCNT (CENTER_TIDS_AUTOGEN_WCNT), + .HMC_TIDS_0 (HMC_TIDS_0), + .HMC_TIDS_1 (HMC_TIDS_1), + .HMC_TIDS_2 (HMC_TIDS_2), + .HMC_TIDS_AUTOGEN_WCNT (HMC_TIDS_AUTOGEN_WCNT), + .LANE_TIDS_0 (LANE_TIDS_0), + .LANE_TIDS_1 (LANE_TIDS_1), + .LANE_TIDS_2 (LANE_TIDS_2), + .LANE_TIDS_3 (LANE_TIDS_3), + .LANE_TIDS_4 (LANE_TIDS_4), + .LANE_TIDS_5 (LANE_TIDS_5), + .LANE_TIDS_6 (LANE_TIDS_6), + .LANE_TIDS_7 (LANE_TIDS_7), + .LANE_TIDS_8 (LANE_TIDS_8), + .LANE_TIDS_9 (LANE_TIDS_9), + .LANE_TIDS_AUTOGEN_WCNT (LANE_TIDS_AUTOGEN_WCNT), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DQSA_LGC_MODE (DQSA_LGC_MODE), + .DQSB_LGC_MODE (DQSB_LGC_MODE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .GENERATE_PHYLITE (GENERATE_PHYLITE), + .HPRX_CTLE_EN (HPRX_CTLE_EN), + .HPRX_OFFSET_CAL (HPRX_OFFSET_CAL), + .CPA_FB_MUX_1_SEL (CPA_FB_MUX_1_SEL), + .ENABLE_RD_TYPE (ENABLE_RD_TYPE), + .AMM_C2P_UFI_MODE (AMM_C2P_UFI_MODE), + .AMM_P2C_UFI_MODE (AMM_P2C_UFI_MODE), + .MMR_C2P_UFI_MODE (MMR_C2P_UFI_MODE), + .MMR_P2C_UFI_MODE (MMR_P2C_UFI_MODE), + .SIDEBAND_C2P_UFI_MODE (SIDEBAND_C2P_UFI_MODE), + .SIDEBAND_P2C_UFI_MODE (SIDEBAND_P2C_UFI_MODE), + .SEQ_C2P_UFI_MODE (SEQ_C2P_UFI_MODE), + .SEQ_P2C_UFI_MODE (SEQ_P2C_UFI_MODE), + .ECC_C2P_UFI_MODE (ECC_C2P_UFI_MODE), + .ECC_P2C_UFI_MODE (ECC_P2C_UFI_MODE), + .LANE_C2P_UFI_MODE (LANE_C2P_UFI_MODE), + .LANE_P2C_UFI_MODE (LANE_P2C_UFI_MODE), + .AMM_HIPI_DELAY (AMM_HIPI_DELAY), + .MMR_HIPI_DELAY (MMR_HIPI_DELAY), + .SIDEBAND_HIPI_DELAY (SIDEBAND_HIPI_DELAY), + .SEQ_HIPI_DELAY (SEQ_HIPI_DELAY), + .ECC_HIPI_DELAY (ECC_HIPI_DELAY), + .LANE_HIPI_DELAY (LANE_HIPI_DELAY), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_CS_ADDR_WIDTH (PRI_HMC_CFG_CS_ADDR_WIDTH), + .PRI_HMC_CFG_COL_ADDR_WIDTH (PRI_HMC_CFG_COL_ADDR_WIDTH), + .PRI_HMC_CFG_ROW_ADDR_WIDTH (PRI_HMC_CFG_ROW_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_ADDR_WIDTH (PRI_HMC_CFG_BANK_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH (PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_CTRL_ENABLE_RC (PRI_HMC_CFG_CTRL_ENABLE_RC), + .PRI_HMC_CFG_DBC0_ENABLE_RC (PRI_HMC_CFG_DBC0_ENABLE_RC), + .PRI_HMC_CFG_DBC1_ENABLE_RC (PRI_HMC_CFG_DBC1_ENABLE_RC), + .PRI_HMC_CFG_DBC2_ENABLE_RC (PRI_HMC_CFG_DBC2_ENABLE_RC), + .PRI_HMC_CFG_DBC3_ENABLE_RC (PRI_HMC_CFG_DBC3_ENABLE_RC), + .PRI_HMC_CFG_CTRL_ENABLE_ECC (PRI_HMC_CFG_CTRL_ENABLE_ECC), + .PRI_HMC_CFG_DBC0_ENABLE_ECC (PRI_HMC_CFG_DBC0_ENABLE_ECC), + .PRI_HMC_CFG_DBC1_ENABLE_ECC (PRI_HMC_CFG_DBC1_ENABLE_ECC), + .PRI_HMC_CFG_DBC2_ENABLE_ECC (PRI_HMC_CFG_DBC2_ENABLE_ECC), + .PRI_HMC_CFG_DBC3_ENABLE_ECC (PRI_HMC_CFG_DBC3_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_CTRL_REORDER_RDATA (PRI_HMC_CFG_CTRL_REORDER_RDATA), + .PRI_HMC_CFG_DBC0_REORDER_RDATA (PRI_HMC_CFG_DBC0_REORDER_RDATA), + .PRI_HMC_CFG_DBC1_REORDER_RDATA (PRI_HMC_CFG_DBC1_REORDER_RDATA), + .PRI_HMC_CFG_DBC2_REORDER_RDATA (PRI_HMC_CFG_DBC2_REORDER_RDATA), + .PRI_HMC_CFG_DBC3_REORDER_RDATA (PRI_HMC_CFG_DBC3_REORDER_RDATA), + .PRI_HMC_CFG_CTRL_SLOT_OFFSET (PRI_HMC_CFG_CTRL_SLOT_OFFSET), + .PRI_HMC_CFG_DBC0_SLOT_OFFSET (PRI_HMC_CFG_DBC0_SLOT_OFFSET), + .PRI_HMC_CFG_DBC1_SLOT_OFFSET (PRI_HMC_CFG_DBC1_SLOT_OFFSET), + .PRI_HMC_CFG_DBC2_SLOT_OFFSET (PRI_HMC_CFG_DBC2_SLOT_OFFSET), + .PRI_HMC_CFG_DBC3_SLOT_OFFSET (PRI_HMC_CFG_DBC3_SLOT_OFFSET), + .PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN (PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ROW_TO_COL_OFFSET (PRI_HMC_CFG_ROW_TO_COL_OFFSET), + .PRI_HMC_CFG_ROW_TO_ROW_OFFSET (PRI_HMC_CFG_ROW_TO_ROW_OFFSET), + .PRI_HMC_CFG_COL_TO_COL_OFFSET (PRI_HMC_CFG_COL_TO_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET (PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_ROW_OFFSET (PRI_HMC_CFG_COL_TO_ROW_OFFSET), + .PRI_HMC_CFG_SIDEBAND_OFFSET (PRI_HMC_CFG_SIDEBAND_OFFSET), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_CTL_ODT_ENABLED (PRI_HMC_CFG_CTL_ODT_ENABLED), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_CMD_FIFO_RESERVE_EN (PRI_HMC_CFG_CMD_FIFO_RESERVE_EN), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_PHY_DELAY_MISMATCH (PRI_HMC_CFG_PHY_DELAY_MISMATCH), + .PRI_HMC_CFG_DQSTRK_EN (PRI_HMC_CFG_DQSTRK_EN), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN (PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD (PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_MEM_AUTO_PD_CYCLES (PRI_HMC_CFG_MEM_AUTO_PD_CYCLES), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_MEMCLKGATE_SETTING (PRI_HMC_MEMCLKGATE_SETTING), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_MEM_IF_AL (PRI_HMC_MEM_IF_AL), + .PRI_HMC_MEM_IF_CS_PER_DIMM (PRI_HMC_MEM_IF_CS_PER_DIMM), + .PRI_HMC_MEM_IF_RD_PREAMBLE (PRI_HMC_MEM_IF_RD_PREAMBLE), + .PRI_HMC_MEM_IF_TCCD (PRI_HMC_MEM_IF_TCCD), + .PRI_HMC_MEM_IF_TCCD_S (PRI_HMC_MEM_IF_TCCD_S), + .PRI_HMC_MEM_IF_TCKESR (PRI_HMC_MEM_IF_TCKESR), + .PRI_HMC_MEM_IF_TCKSRX (PRI_HMC_MEM_IF_TCKSRX), + .PRI_HMC_MEM_IF_TCL (PRI_HMC_MEM_IF_TCL), + .PRI_HMC_MEM_IF_TCWL (PRI_HMC_MEM_IF_TCWL), + .PRI_HMC_MEM_IF_TDQSCKMAX (PRI_HMC_MEM_IF_TDQSCKMAX), + .PRI_HMC_MEM_IF_TFAW (PRI_HMC_MEM_IF_TFAW), + .PRI_HMC_MEM_IF_TMOD (PRI_HMC_MEM_IF_TMOD), + .PRI_HMC_MEM_IF_TPL (PRI_HMC_MEM_IF_TPL), + .PRI_HMC_MEM_IF_TRAS (PRI_HMC_MEM_IF_TRAS), + .PRI_HMC_MEM_IF_TRC (PRI_HMC_MEM_IF_TRC), + .PRI_HMC_MEM_IF_TRCD (PRI_HMC_MEM_IF_TRCD), + .PRI_HMC_MEM_IF_TREFI (PRI_HMC_MEM_IF_TREFI), + .PRI_HMC_MEM_IF_TRFC (PRI_HMC_MEM_IF_TRFC), + .PRI_HMC_MEM_IF_TRP (PRI_HMC_MEM_IF_TRP), + .PRI_HMC_MEM_IF_TRRD (PRI_HMC_MEM_IF_TRRD), + .PRI_HMC_MEM_IF_TRRD_S (PRI_HMC_MEM_IF_TRRD_S), + .PRI_HMC_MEM_IF_TRTP (PRI_HMC_MEM_IF_TRTP), + .PRI_HMC_MEM_IF_TWR (PRI_HMC_MEM_IF_TWR), + .PRI_HMC_MEM_IF_TWR_CRC_DM (PRI_HMC_MEM_IF_TWR_CRC_DM), + .PRI_HMC_MEM_IF_TWTR (PRI_HMC_MEM_IF_TWTR), + .PRI_HMC_MEM_IF_TWTR_L_CRC_DM (PRI_HMC_MEM_IF_TWTR_L_CRC_DM), + .PRI_HMC_MEM_IF_TWTR_S (PRI_HMC_MEM_IF_TWTR_S), + .PRI_HMC_MEM_IF_TWTR_S_CRC_DM (PRI_HMC_MEM_IF_TWTR_S_CRC_DM), + .PRI_HMC_MEM_IF_TXP (PRI_HMC_MEM_IF_TXP), + .PRI_HMC_MEM_IF_TXPDLL (PRI_HMC_MEM_IF_TXPDLL), + .PRI_HMC_MEM_IF_TXSR (PRI_HMC_MEM_IF_TXSR), + .PRI_HMC_MEM_IF_TZQCS (PRI_HMC_MEM_IF_TZQCS), + .PRI_HMC_MEM_IF_TZQOPER (PRI_HMC_MEM_IF_TZQOPER), + .PRI_HMC_MEM_IF_WR_CRC (PRI_HMC_MEM_IF_WR_CRC), + .PRI_HMC_MEM_IF_WR_PREAMBLE (PRI_HMC_MEM_IF_WR_PREAMBLE), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR (PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_TEMP_4_ACT_TO_ACT (PRI_HMC_TEMP_4_ACT_TO_ACT), + .PRI_HMC_TEMP_RD_TO_RD_DIFF_BG (PRI_HMC_TEMP_RD_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD (PRI_HMC_TEMP_WR_TO_RD), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_BG (PRI_HMC_TEMP_WR_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP (PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_TEMP_WR_TO_WR_DIFF_BG (PRI_HMC_TEMP_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CHIP_ID (PRI_HMC_CHIP_ID), + .PRI_HMC_CID_ADDR_WIDTH (PRI_HMC_CID_ADDR_WIDTH), + .PRI_HMC_3DS_EN (PRI_HMC_3DS_EN), + .PRI_HMC_3DS_LR_NUM0 (PRI_HMC_3DS_LR_NUM0), + .PRI_HMC_3DS_LR_NUM1 (PRI_HMC_3DS_LR_NUM1), + .PRI_HMC_3DS_LR_NUM2 (PRI_HMC_3DS_LR_NUM2), + .PRI_HMC_3DS_LR_NUM3 (PRI_HMC_3DS_LR_NUM3), + .PRI_HMC_3DS_PR_STAG_ENABLE (PRI_HMC_3DS_PR_STAG_ENABLE), + .PRI_HMC_3DS_REF2REF_DLR (PRI_HMC_3DS_REF2REF_DLR), + .PRI_HMC_3DSREF_ACK_ON_DONE (PRI_HMC_3DSREF_ACK_ON_DONE), + .PRI_HMC_CFG_MAJOR_MODE_EN (PRI_HMC_CFG_MAJOR_MODE_EN), + .PRI_HMC_CFG_REFRESH_TYPE (PRI_HMC_CFG_REFRESH_TYPE), + .PRI_HMC_CFG_PRE_REFRESH_EN (PRI_HMC_CFG_PRE_REFRESH_EN), + .PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT), + .PRI_HMC_CFG_POST_REFRESH_EN (PRI_HMC_CFG_POST_REFRESH_EN), + .PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT (PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT), + .PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT (PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_CS_ADDR_WIDTH (SEC_HMC_CFG_CS_ADDR_WIDTH), + .SEC_HMC_CFG_COL_ADDR_WIDTH (SEC_HMC_CFG_COL_ADDR_WIDTH), + .SEC_HMC_CFG_ROW_ADDR_WIDTH (SEC_HMC_CFG_ROW_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_ADDR_WIDTH (SEC_HMC_CFG_BANK_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH (SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_CTRL_ENABLE_RC (SEC_HMC_CFG_CTRL_ENABLE_RC), + .SEC_HMC_CFG_DBC0_ENABLE_RC (SEC_HMC_CFG_DBC0_ENABLE_RC), + .SEC_HMC_CFG_DBC1_ENABLE_RC (SEC_HMC_CFG_DBC1_ENABLE_RC), + .SEC_HMC_CFG_DBC2_ENABLE_RC (SEC_HMC_CFG_DBC2_ENABLE_RC), + .SEC_HMC_CFG_DBC3_ENABLE_RC (SEC_HMC_CFG_DBC3_ENABLE_RC), + .SEC_HMC_CFG_CTRL_ENABLE_ECC (SEC_HMC_CFG_CTRL_ENABLE_ECC), + .SEC_HMC_CFG_DBC0_ENABLE_ECC (SEC_HMC_CFG_DBC0_ENABLE_ECC), + .SEC_HMC_CFG_DBC1_ENABLE_ECC (SEC_HMC_CFG_DBC1_ENABLE_ECC), + .SEC_HMC_CFG_DBC2_ENABLE_ECC (SEC_HMC_CFG_DBC2_ENABLE_ECC), + .SEC_HMC_CFG_DBC3_ENABLE_ECC (SEC_HMC_CFG_DBC3_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_CTRL_REORDER_RDATA (SEC_HMC_CFG_CTRL_REORDER_RDATA), + .SEC_HMC_CFG_DBC0_REORDER_RDATA (SEC_HMC_CFG_DBC0_REORDER_RDATA), + .SEC_HMC_CFG_DBC1_REORDER_RDATA (SEC_HMC_CFG_DBC1_REORDER_RDATA), + .SEC_HMC_CFG_DBC2_REORDER_RDATA (SEC_HMC_CFG_DBC2_REORDER_RDATA), + .SEC_HMC_CFG_DBC3_REORDER_RDATA (SEC_HMC_CFG_DBC3_REORDER_RDATA), + .SEC_HMC_CFG_CTRL_SLOT_OFFSET (SEC_HMC_CFG_CTRL_SLOT_OFFSET), + .SEC_HMC_CFG_DBC0_SLOT_OFFSET (SEC_HMC_CFG_DBC0_SLOT_OFFSET), + .SEC_HMC_CFG_DBC1_SLOT_OFFSET (SEC_HMC_CFG_DBC1_SLOT_OFFSET), + .SEC_HMC_CFG_DBC2_SLOT_OFFSET (SEC_HMC_CFG_DBC2_SLOT_OFFSET), + .SEC_HMC_CFG_DBC3_SLOT_OFFSET (SEC_HMC_CFG_DBC3_SLOT_OFFSET), + .SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN (SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ROW_TO_COL_OFFSET (SEC_HMC_CFG_ROW_TO_COL_OFFSET), + .SEC_HMC_CFG_ROW_TO_ROW_OFFSET (SEC_HMC_CFG_ROW_TO_ROW_OFFSET), + .SEC_HMC_CFG_COL_TO_COL_OFFSET (SEC_HMC_CFG_COL_TO_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET (SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_ROW_OFFSET (SEC_HMC_CFG_COL_TO_ROW_OFFSET), + .SEC_HMC_CFG_SIDEBAND_OFFSET (SEC_HMC_CFG_SIDEBAND_OFFSET), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_CTL_ODT_ENABLED (SEC_HMC_CFG_CTL_ODT_ENABLED), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_CMD_FIFO_RESERVE_EN (SEC_HMC_CFG_CMD_FIFO_RESERVE_EN), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_PHY_DELAY_MISMATCH (SEC_HMC_CFG_PHY_DELAY_MISMATCH), + .SEC_HMC_CFG_DQSTRK_EN (SEC_HMC_CFG_DQSTRK_EN), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN (SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD (SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_MEM_AUTO_PD_CYCLES (SEC_HMC_CFG_MEM_AUTO_PD_CYCLES), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_MEMCLKGATE_SETTING (SEC_HMC_MEMCLKGATE_SETTING), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_MEM_IF_AL (SEC_HMC_MEM_IF_AL), + .SEC_HMC_MEM_IF_CS_PER_DIMM (SEC_HMC_MEM_IF_CS_PER_DIMM), + .SEC_HMC_MEM_IF_RD_PREAMBLE (SEC_HMC_MEM_IF_RD_PREAMBLE), + .SEC_HMC_MEM_IF_TCCD (SEC_HMC_MEM_IF_TCCD), + .SEC_HMC_MEM_IF_TCCD_S (SEC_HMC_MEM_IF_TCCD_S), + .SEC_HMC_MEM_IF_TCKESR (SEC_HMC_MEM_IF_TCKESR), + .SEC_HMC_MEM_IF_TCKSRX (SEC_HMC_MEM_IF_TCKSRX), + .SEC_HMC_MEM_IF_TCL (SEC_HMC_MEM_IF_TCL), + .SEC_HMC_MEM_IF_TCWL (SEC_HMC_MEM_IF_TCWL), + .SEC_HMC_MEM_IF_TDQSCKMAX (SEC_HMC_MEM_IF_TDQSCKMAX), + .SEC_HMC_MEM_IF_TFAW (SEC_HMC_MEM_IF_TFAW), + .SEC_HMC_MEM_IF_TMOD (SEC_HMC_MEM_IF_TMOD), + .SEC_HMC_MEM_IF_TPL (SEC_HMC_MEM_IF_TPL), + .SEC_HMC_MEM_IF_TRAS (SEC_HMC_MEM_IF_TRAS), + .SEC_HMC_MEM_IF_TRC (SEC_HMC_MEM_IF_TRC), + .SEC_HMC_MEM_IF_TRCD (SEC_HMC_MEM_IF_TRCD), + .SEC_HMC_MEM_IF_TREFI (SEC_HMC_MEM_IF_TREFI), + .SEC_HMC_MEM_IF_TRFC (SEC_HMC_MEM_IF_TRFC), + .SEC_HMC_MEM_IF_TRP (SEC_HMC_MEM_IF_TRP), + .SEC_HMC_MEM_IF_TRRD (SEC_HMC_MEM_IF_TRRD), + .SEC_HMC_MEM_IF_TRRD_S (SEC_HMC_MEM_IF_TRRD_S), + .SEC_HMC_MEM_IF_TRTP (SEC_HMC_MEM_IF_TRTP), + .SEC_HMC_MEM_IF_TWR (SEC_HMC_MEM_IF_TWR), + .SEC_HMC_MEM_IF_TWR_CRC_DM (SEC_HMC_MEM_IF_TWR_CRC_DM), + .SEC_HMC_MEM_IF_TWTR (SEC_HMC_MEM_IF_TWTR), + .SEC_HMC_MEM_IF_TWTR_L_CRC_DM (SEC_HMC_MEM_IF_TWTR_L_CRC_DM), + .SEC_HMC_MEM_IF_TWTR_S (SEC_HMC_MEM_IF_TWTR_S), + .SEC_HMC_MEM_IF_TWTR_S_CRC_DM (SEC_HMC_MEM_IF_TWTR_S_CRC_DM), + .SEC_HMC_MEM_IF_TXP (SEC_HMC_MEM_IF_TXP), + .SEC_HMC_MEM_IF_TXPDLL (SEC_HMC_MEM_IF_TXPDLL), + .SEC_HMC_MEM_IF_TXSR (SEC_HMC_MEM_IF_TXSR), + .SEC_HMC_MEM_IF_TZQCS (SEC_HMC_MEM_IF_TZQCS), + .SEC_HMC_MEM_IF_TZQOPER (SEC_HMC_MEM_IF_TZQOPER), + .SEC_HMC_MEM_IF_WR_CRC (SEC_HMC_MEM_IF_WR_CRC), + .SEC_HMC_MEM_IF_WR_PREAMBLE (SEC_HMC_MEM_IF_WR_PREAMBLE), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR (SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_TEMP_4_ACT_TO_ACT (SEC_HMC_TEMP_4_ACT_TO_ACT), + .SEC_HMC_TEMP_RD_TO_RD_DIFF_BG (SEC_HMC_TEMP_RD_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD (SEC_HMC_TEMP_WR_TO_RD), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_BG (SEC_HMC_TEMP_WR_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP (SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_TEMP_WR_TO_WR_DIFF_BG (SEC_HMC_TEMP_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CHIP_ID (SEC_HMC_CHIP_ID), + .SEC_HMC_CID_ADDR_WIDTH (SEC_HMC_CID_ADDR_WIDTH), + .SEC_HMC_3DS_EN (SEC_HMC_3DS_EN), + .SEC_HMC_3DS_LR_NUM0 (SEC_HMC_3DS_LR_NUM0), + .SEC_HMC_3DS_LR_NUM1 (SEC_HMC_3DS_LR_NUM1), + .SEC_HMC_3DS_LR_NUM2 (SEC_HMC_3DS_LR_NUM2), + .SEC_HMC_3DS_LR_NUM3 (SEC_HMC_3DS_LR_NUM3), + .SEC_HMC_3DS_PR_STAG_ENABLE (SEC_HMC_3DS_PR_STAG_ENABLE), + .SEC_HMC_3DS_REF2REF_DLR (SEC_HMC_3DS_REF2REF_DLR), + .SEC_HMC_3DSREF_ACK_ON_DONE (SEC_HMC_3DSREF_ACK_ON_DONE), + .SEC_HMC_CFG_MAJOR_MODE_EN (SEC_HMC_CFG_MAJOR_MODE_EN), + .SEC_HMC_CFG_REFRESH_TYPE (SEC_HMC_CFG_REFRESH_TYPE), + .SEC_HMC_CFG_PRE_REFRESH_EN (SEC_HMC_CFG_PRE_REFRESH_EN), + .SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT), + .SEC_HMC_CFG_POST_REFRESH_EN (SEC_HMC_CFG_POST_REFRESH_EN), + .SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT (SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT), + .SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT (SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_PINLOC_0 (PORT_MEM_CK_PINLOC_0), + .PORT_MEM_CK_PINLOC_1 (PORT_MEM_CK_PINLOC_1), + .PORT_MEM_CK_PINLOC_2 (PORT_MEM_CK_PINLOC_2), + .PORT_MEM_CK_PINLOC_3 (PORT_MEM_CK_PINLOC_3), + .PORT_MEM_CK_PINLOC_4 (PORT_MEM_CK_PINLOC_4), + .PORT_MEM_CK_PINLOC_5 (PORT_MEM_CK_PINLOC_5), + .PORT_MEM_CK_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_CK_N_PINLOC_0 (PORT_MEM_CK_N_PINLOC_0), + .PORT_MEM_CK_N_PINLOC_1 (PORT_MEM_CK_N_PINLOC_1), + .PORT_MEM_CK_N_PINLOC_2 (PORT_MEM_CK_N_PINLOC_2), + .PORT_MEM_CK_N_PINLOC_3 (PORT_MEM_CK_N_PINLOC_3), + .PORT_MEM_CK_N_PINLOC_4 (PORT_MEM_CK_N_PINLOC_4), + .PORT_MEM_CK_N_PINLOC_5 (PORT_MEM_CK_N_PINLOC_5), + .PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CK_BIDIR_WIDTH (PORT_MEM_CK_BIDIR_WIDTH), + .PORT_MEM_CK_BIDIR_PINLOC_0 (PORT_MEM_CK_BIDIR_PINLOC_0), + .PORT_MEM_CK_BIDIR_PINLOC_1 (PORT_MEM_CK_BIDIR_PINLOC_1), + .PORT_MEM_CK_BIDIR_PINLOC_2 (PORT_MEM_CK_BIDIR_PINLOC_2), + .PORT_MEM_CK_BIDIR_PINLOC_3 (PORT_MEM_CK_BIDIR_PINLOC_3), + .PORT_MEM_CK_BIDIR_PINLOC_4 (PORT_MEM_CK_BIDIR_PINLOC_4), + .PORT_MEM_CK_BIDIR_PINLOC_5 (PORT_MEM_CK_BIDIR_PINLOC_5), + .PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CK_BIDIR_N_WIDTH (PORT_MEM_CK_BIDIR_N_WIDTH), + .PORT_MEM_CK_BIDIR_N_PINLOC_0 (PORT_MEM_CK_BIDIR_N_PINLOC_0), + .PORT_MEM_CK_BIDIR_N_PINLOC_1 (PORT_MEM_CK_BIDIR_N_PINLOC_1), + .PORT_MEM_CK_BIDIR_N_PINLOC_2 (PORT_MEM_CK_BIDIR_N_PINLOC_2), + .PORT_MEM_CK_BIDIR_N_PINLOC_3 (PORT_MEM_CK_BIDIR_N_PINLOC_3), + .PORT_MEM_CK_BIDIR_N_PINLOC_4 (PORT_MEM_CK_BIDIR_N_PINLOC_4), + .PORT_MEM_CK_BIDIR_N_PINLOC_5 (PORT_MEM_CK_BIDIR_N_PINLOC_5), + .PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_PINLOC_0 (PORT_MEM_DK_PINLOC_0), + .PORT_MEM_DK_PINLOC_1 (PORT_MEM_DK_PINLOC_1), + .PORT_MEM_DK_PINLOC_2 (PORT_MEM_DK_PINLOC_2), + .PORT_MEM_DK_PINLOC_3 (PORT_MEM_DK_PINLOC_3), + .PORT_MEM_DK_PINLOC_4 (PORT_MEM_DK_PINLOC_4), + .PORT_MEM_DK_PINLOC_5 (PORT_MEM_DK_PINLOC_5), + .PORT_MEM_DK_PINLOC_AUTOGEN_WCNT (PORT_MEM_DK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DK_N_PINLOC_0 (PORT_MEM_DK_N_PINLOC_0), + .PORT_MEM_DK_N_PINLOC_1 (PORT_MEM_DK_N_PINLOC_1), + .PORT_MEM_DK_N_PINLOC_2 (PORT_MEM_DK_N_PINLOC_2), + .PORT_MEM_DK_N_PINLOC_3 (PORT_MEM_DK_N_PINLOC_3), + .PORT_MEM_DK_N_PINLOC_4 (PORT_MEM_DK_N_PINLOC_4), + .PORT_MEM_DK_N_PINLOC_5 (PORT_MEM_DK_N_PINLOC_5), + .PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_PINLOC_0 (PORT_MEM_DKA_PINLOC_0), + .PORT_MEM_DKA_PINLOC_1 (PORT_MEM_DKA_PINLOC_1), + .PORT_MEM_DKA_PINLOC_2 (PORT_MEM_DKA_PINLOC_2), + .PORT_MEM_DKA_PINLOC_3 (PORT_MEM_DKA_PINLOC_3), + .PORT_MEM_DKA_PINLOC_4 (PORT_MEM_DKA_PINLOC_4), + .PORT_MEM_DKA_PINLOC_5 (PORT_MEM_DKA_PINLOC_5), + .PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKA_N_PINLOC_0 (PORT_MEM_DKA_N_PINLOC_0), + .PORT_MEM_DKA_N_PINLOC_1 (PORT_MEM_DKA_N_PINLOC_1), + .PORT_MEM_DKA_N_PINLOC_2 (PORT_MEM_DKA_N_PINLOC_2), + .PORT_MEM_DKA_N_PINLOC_3 (PORT_MEM_DKA_N_PINLOC_3), + .PORT_MEM_DKA_N_PINLOC_4 (PORT_MEM_DKA_N_PINLOC_4), + .PORT_MEM_DKA_N_PINLOC_5 (PORT_MEM_DKA_N_PINLOC_5), + .PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_PINLOC_0 (PORT_MEM_DKB_PINLOC_0), + .PORT_MEM_DKB_PINLOC_1 (PORT_MEM_DKB_PINLOC_1), + .PORT_MEM_DKB_PINLOC_2 (PORT_MEM_DKB_PINLOC_2), + .PORT_MEM_DKB_PINLOC_3 (PORT_MEM_DKB_PINLOC_3), + .PORT_MEM_DKB_PINLOC_4 (PORT_MEM_DKB_PINLOC_4), + .PORT_MEM_DKB_PINLOC_5 (PORT_MEM_DKB_PINLOC_5), + .PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_DKB_N_PINLOC_0 (PORT_MEM_DKB_N_PINLOC_0), + .PORT_MEM_DKB_N_PINLOC_1 (PORT_MEM_DKB_N_PINLOC_1), + .PORT_MEM_DKB_N_PINLOC_2 (PORT_MEM_DKB_N_PINLOC_2), + .PORT_MEM_DKB_N_PINLOC_3 (PORT_MEM_DKB_N_PINLOC_3), + .PORT_MEM_DKB_N_PINLOC_4 (PORT_MEM_DKB_N_PINLOC_4), + .PORT_MEM_DKB_N_PINLOC_5 (PORT_MEM_DKB_N_PINLOC_5), + .PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_PINLOC_0 (PORT_MEM_K_PINLOC_0), + .PORT_MEM_K_PINLOC_1 (PORT_MEM_K_PINLOC_1), + .PORT_MEM_K_PINLOC_2 (PORT_MEM_K_PINLOC_2), + .PORT_MEM_K_PINLOC_3 (PORT_MEM_K_PINLOC_3), + .PORT_MEM_K_PINLOC_4 (PORT_MEM_K_PINLOC_4), + .PORT_MEM_K_PINLOC_5 (PORT_MEM_K_PINLOC_5), + .PORT_MEM_K_PINLOC_AUTOGEN_WCNT (PORT_MEM_K_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_K_N_PINLOC_0 (PORT_MEM_K_N_PINLOC_0), + .PORT_MEM_K_N_PINLOC_1 (PORT_MEM_K_N_PINLOC_1), + .PORT_MEM_K_N_PINLOC_2 (PORT_MEM_K_N_PINLOC_2), + .PORT_MEM_K_N_PINLOC_3 (PORT_MEM_K_N_PINLOC_3), + .PORT_MEM_K_N_PINLOC_4 (PORT_MEM_K_N_PINLOC_4), + .PORT_MEM_K_N_PINLOC_5 (PORT_MEM_K_N_PINLOC_5), + .PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_A_PINLOC_0 (PORT_MEM_A_PINLOC_0), + .PORT_MEM_A_PINLOC_1 (PORT_MEM_A_PINLOC_1), + .PORT_MEM_A_PINLOC_2 (PORT_MEM_A_PINLOC_2), + .PORT_MEM_A_PINLOC_3 (PORT_MEM_A_PINLOC_3), + .PORT_MEM_A_PINLOC_4 (PORT_MEM_A_PINLOC_4), + .PORT_MEM_A_PINLOC_5 (PORT_MEM_A_PINLOC_5), + .PORT_MEM_A_PINLOC_6 (PORT_MEM_A_PINLOC_6), + .PORT_MEM_A_PINLOC_7 (PORT_MEM_A_PINLOC_7), + .PORT_MEM_A_PINLOC_8 (PORT_MEM_A_PINLOC_8), + .PORT_MEM_A_PINLOC_9 (PORT_MEM_A_PINLOC_9), + .PORT_MEM_A_PINLOC_10 (PORT_MEM_A_PINLOC_10), + .PORT_MEM_A_PINLOC_11 (PORT_MEM_A_PINLOC_11), + .PORT_MEM_A_PINLOC_12 (PORT_MEM_A_PINLOC_12), + .PORT_MEM_A_PINLOC_13 (PORT_MEM_A_PINLOC_13), + .PORT_MEM_A_PINLOC_14 (PORT_MEM_A_PINLOC_14), + .PORT_MEM_A_PINLOC_15 (PORT_MEM_A_PINLOC_15), + .PORT_MEM_A_PINLOC_16 (PORT_MEM_A_PINLOC_16), + .PORT_MEM_A_PINLOC_AUTOGEN_WCNT (PORT_MEM_A_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BA_PINLOC_0 (PORT_MEM_BA_PINLOC_0), + .PORT_MEM_BA_PINLOC_1 (PORT_MEM_BA_PINLOC_1), + .PORT_MEM_BA_PINLOC_2 (PORT_MEM_BA_PINLOC_2), + .PORT_MEM_BA_PINLOC_3 (PORT_MEM_BA_PINLOC_3), + .PORT_MEM_BA_PINLOC_4 (PORT_MEM_BA_PINLOC_4), + .PORT_MEM_BA_PINLOC_5 (PORT_MEM_BA_PINLOC_5), + .PORT_MEM_BA_PINLOC_AUTOGEN_WCNT (PORT_MEM_BA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_BG_PINLOC_0 (PORT_MEM_BG_PINLOC_0), + .PORT_MEM_BG_PINLOC_1 (PORT_MEM_BG_PINLOC_1), + .PORT_MEM_BG_PINLOC_2 (PORT_MEM_BG_PINLOC_2), + .PORT_MEM_BG_PINLOC_3 (PORT_MEM_BG_PINLOC_3), + .PORT_MEM_BG_PINLOC_4 (PORT_MEM_BG_PINLOC_4), + .PORT_MEM_BG_PINLOC_5 (PORT_MEM_BG_PINLOC_5), + .PORT_MEM_BG_PINLOC_AUTOGEN_WCNT (PORT_MEM_BG_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_C_PINLOC_0 (PORT_MEM_C_PINLOC_0), + .PORT_MEM_C_PINLOC_1 (PORT_MEM_C_PINLOC_1), + .PORT_MEM_C_PINLOC_2 (PORT_MEM_C_PINLOC_2), + .PORT_MEM_C_PINLOC_3 (PORT_MEM_C_PINLOC_3), + .PORT_MEM_C_PINLOC_4 (PORT_MEM_C_PINLOC_4), + .PORT_MEM_C_PINLOC_5 (PORT_MEM_C_PINLOC_5), + .PORT_MEM_C_PINLOC_AUTOGEN_WCNT (PORT_MEM_C_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CKE_PINLOC_0 (PORT_MEM_CKE_PINLOC_0), + .PORT_MEM_CKE_PINLOC_1 (PORT_MEM_CKE_PINLOC_1), + .PORT_MEM_CKE_PINLOC_2 (PORT_MEM_CKE_PINLOC_2), + .PORT_MEM_CKE_PINLOC_3 (PORT_MEM_CKE_PINLOC_3), + .PORT_MEM_CKE_PINLOC_4 (PORT_MEM_CKE_PINLOC_4), + .PORT_MEM_CKE_PINLOC_5 (PORT_MEM_CKE_PINLOC_5), + .PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT (PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_CS_N_PINLOC_0 (PORT_MEM_CS_N_PINLOC_0), + .PORT_MEM_CS_N_PINLOC_1 (PORT_MEM_CS_N_PINLOC_1), + .PORT_MEM_CS_N_PINLOC_2 (PORT_MEM_CS_N_PINLOC_2), + .PORT_MEM_CS_N_PINLOC_3 (PORT_MEM_CS_N_PINLOC_3), + .PORT_MEM_CS_N_PINLOC_4 (PORT_MEM_CS_N_PINLOC_4), + .PORT_MEM_CS_N_PINLOC_5 (PORT_MEM_CS_N_PINLOC_5), + .PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_RM_PINLOC_0 (PORT_MEM_RM_PINLOC_0), + .PORT_MEM_RM_PINLOC_1 (PORT_MEM_RM_PINLOC_1), + .PORT_MEM_RM_PINLOC_2 (PORT_MEM_RM_PINLOC_2), + .PORT_MEM_RM_PINLOC_3 (PORT_MEM_RM_PINLOC_3), + .PORT_MEM_RM_PINLOC_4 (PORT_MEM_RM_PINLOC_4), + .PORT_MEM_RM_PINLOC_5 (PORT_MEM_RM_PINLOC_5), + .PORT_MEM_RM_PINLOC_AUTOGEN_WCNT (PORT_MEM_RM_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_ODT_PINLOC_0 (PORT_MEM_ODT_PINLOC_0), + .PORT_MEM_ODT_PINLOC_1 (PORT_MEM_ODT_PINLOC_1), + .PORT_MEM_ODT_PINLOC_2 (PORT_MEM_ODT_PINLOC_2), + .PORT_MEM_ODT_PINLOC_3 (PORT_MEM_ODT_PINLOC_3), + .PORT_MEM_ODT_PINLOC_4 (PORT_MEM_ODT_PINLOC_4), + .PORT_MEM_ODT_PINLOC_5 (PORT_MEM_ODT_PINLOC_5), + .PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT (PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_REQ_N_WIDTH (PORT_MEM_REQ_N_WIDTH), + .PORT_MEM_REQ_N_PINLOC_0 (PORT_MEM_REQ_N_PINLOC_0), + .PORT_MEM_REQ_N_PINLOC_1 (PORT_MEM_REQ_N_PINLOC_1), + .PORT_MEM_REQ_N_PINLOC_2 (PORT_MEM_REQ_N_PINLOC_2), + .PORT_MEM_REQ_N_PINLOC_3 (PORT_MEM_REQ_N_PINLOC_3), + .PORT_MEM_REQ_N_PINLOC_4 (PORT_MEM_REQ_N_PINLOC_4), + .PORT_MEM_REQ_N_PINLOC_5 (PORT_MEM_REQ_N_PINLOC_5), + .PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_GNT_N_WIDTH (PORT_MEM_GNT_N_WIDTH), + .PORT_MEM_GNT_N_PINLOC_0 (PORT_MEM_GNT_N_PINLOC_0), + .PORT_MEM_GNT_N_PINLOC_1 (PORT_MEM_GNT_N_PINLOC_1), + .PORT_MEM_GNT_N_PINLOC_2 (PORT_MEM_GNT_N_PINLOC_2), + .PORT_MEM_GNT_N_PINLOC_3 (PORT_MEM_GNT_N_PINLOC_3), + .PORT_MEM_GNT_N_PINLOC_4 (PORT_MEM_GNT_N_PINLOC_4), + .PORT_MEM_GNT_N_PINLOC_5 (PORT_MEM_GNT_N_PINLOC_5), + .PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ERR_N_WIDTH (PORT_MEM_ERR_N_WIDTH), + .PORT_MEM_ERR_N_PINLOC_0 (PORT_MEM_ERR_N_PINLOC_0), + .PORT_MEM_ERR_N_PINLOC_1 (PORT_MEM_ERR_N_PINLOC_1), + .PORT_MEM_ERR_N_PINLOC_2 (PORT_MEM_ERR_N_PINLOC_2), + .PORT_MEM_ERR_N_PINLOC_3 (PORT_MEM_ERR_N_PINLOC_3), + .PORT_MEM_ERR_N_PINLOC_4 (PORT_MEM_ERR_N_PINLOC_4), + .PORT_MEM_ERR_N_PINLOC_5 (PORT_MEM_ERR_N_PINLOC_5), + .PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_RAS_N_PINLOC_0 (PORT_MEM_RAS_N_PINLOC_0), + .PORT_MEM_RAS_N_PINLOC_1 (PORT_MEM_RAS_N_PINLOC_1), + .PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_CAS_N_PINLOC_0 (PORT_MEM_CAS_N_PINLOC_0), + .PORT_MEM_CAS_N_PINLOC_1 (PORT_MEM_CAS_N_PINLOC_1), + .PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_WE_N_PINLOC_0 (PORT_MEM_WE_N_PINLOC_0), + .PORT_MEM_WE_N_PINLOC_1 (PORT_MEM_WE_N_PINLOC_1), + .PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_RESET_N_PINLOC_0 (PORT_MEM_RESET_N_PINLOC_0), + .PORT_MEM_RESET_N_PINLOC_1 (PORT_MEM_RESET_N_PINLOC_1), + .PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_ACT_N_PINLOC_0 (PORT_MEM_ACT_N_PINLOC_0), + .PORT_MEM_ACT_N_PINLOC_1 (PORT_MEM_ACT_N_PINLOC_1), + .PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_PAR_PINLOC_0 (PORT_MEM_PAR_PINLOC_0), + .PORT_MEM_PAR_PINLOC_1 (PORT_MEM_PAR_PINLOC_1), + .PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT (PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_CA_PINLOC_0 (PORT_MEM_CA_PINLOC_0), + .PORT_MEM_CA_PINLOC_1 (PORT_MEM_CA_PINLOC_1), + .PORT_MEM_CA_PINLOC_2 (PORT_MEM_CA_PINLOC_2), + .PORT_MEM_CA_PINLOC_3 (PORT_MEM_CA_PINLOC_3), + .PORT_MEM_CA_PINLOC_4 (PORT_MEM_CA_PINLOC_4), + .PORT_MEM_CA_PINLOC_5 (PORT_MEM_CA_PINLOC_5), + .PORT_MEM_CA_PINLOC_6 (PORT_MEM_CA_PINLOC_6), + .PORT_MEM_CA_PINLOC_7 (PORT_MEM_CA_PINLOC_7), + .PORT_MEM_CA_PINLOC_8 (PORT_MEM_CA_PINLOC_8), + .PORT_MEM_CA_PINLOC_9 (PORT_MEM_CA_PINLOC_9), + .PORT_MEM_CA_PINLOC_10 (PORT_MEM_CA_PINLOC_10), + .PORT_MEM_CA_PINLOC_11 (PORT_MEM_CA_PINLOC_11), + .PORT_MEM_CA_PINLOC_12 (PORT_MEM_CA_PINLOC_12), + .PORT_MEM_CA_PINLOC_13 (PORT_MEM_CA_PINLOC_13), + .PORT_MEM_CA_PINLOC_14 (PORT_MEM_CA_PINLOC_14), + .PORT_MEM_CA_PINLOC_15 (PORT_MEM_CA_PINLOC_15), + .PORT_MEM_CA_PINLOC_16 (PORT_MEM_CA_PINLOC_16), + .PORT_MEM_CA_PINLOC_AUTOGEN_WCNT (PORT_MEM_CA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_REF_N_PINLOC_0 (PORT_MEM_REF_N_PINLOC_0), + .PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_WPS_N_PINLOC_0 (PORT_MEM_WPS_N_PINLOC_0), + .PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_RPS_N_PINLOC_0 (PORT_MEM_RPS_N_PINLOC_0), + .PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_DOFF_N_PINLOC_0 (PORT_MEM_DOFF_N_PINLOC_0), + .PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDA_N_PINLOC_0 (PORT_MEM_LDA_N_PINLOC_0), + .PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_LDB_N_PINLOC_0 (PORT_MEM_LDB_N_PINLOC_0), + .PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWA_N_PINLOC_0 (PORT_MEM_RWA_N_PINLOC_0), + .PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_RWB_N_PINLOC_0 (PORT_MEM_RWB_N_PINLOC_0), + .PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK0_N_PINLOC_0 (PORT_MEM_LBK0_N_PINLOC_0), + .PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_LBK1_N_PINLOC_0 (PORT_MEM_LBK1_N_PINLOC_0), + .PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_CFG_N_PINLOC_0 (PORT_MEM_CFG_N_PINLOC_0), + .PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AP_PINLOC_0 (PORT_MEM_AP_PINLOC_0), + .PORT_MEM_AP_PINLOC_AUTOGEN_WCNT (PORT_MEM_AP_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_AINV_PINLOC_0 (PORT_MEM_AINV_PINLOC_0), + .PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT (PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_DM_PINLOC_0 (PORT_MEM_DM_PINLOC_0), + .PORT_MEM_DM_PINLOC_1 (PORT_MEM_DM_PINLOC_1), + .PORT_MEM_DM_PINLOC_2 (PORT_MEM_DM_PINLOC_2), + .PORT_MEM_DM_PINLOC_3 (PORT_MEM_DM_PINLOC_3), + .PORT_MEM_DM_PINLOC_4 (PORT_MEM_DM_PINLOC_4), + .PORT_MEM_DM_PINLOC_5 (PORT_MEM_DM_PINLOC_5), + .PORT_MEM_DM_PINLOC_6 (PORT_MEM_DM_PINLOC_6), + .PORT_MEM_DM_PINLOC_7 (PORT_MEM_DM_PINLOC_7), + .PORT_MEM_DM_PINLOC_8 (PORT_MEM_DM_PINLOC_8), + .PORT_MEM_DM_PINLOC_9 (PORT_MEM_DM_PINLOC_9), + .PORT_MEM_DM_PINLOC_10 (PORT_MEM_DM_PINLOC_10), + .PORT_MEM_DM_PINLOC_11 (PORT_MEM_DM_PINLOC_11), + .PORT_MEM_DM_PINLOC_12 (PORT_MEM_DM_PINLOC_12), + .PORT_MEM_DM_PINLOC_AUTOGEN_WCNT (PORT_MEM_DM_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_BWS_N_PINLOC_0 (PORT_MEM_BWS_N_PINLOC_0), + .PORT_MEM_BWS_N_PINLOC_1 (PORT_MEM_BWS_N_PINLOC_1), + .PORT_MEM_BWS_N_PINLOC_2 (PORT_MEM_BWS_N_PINLOC_2), + .PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_D_PINLOC_0 (PORT_MEM_D_PINLOC_0), + .PORT_MEM_D_PINLOC_1 (PORT_MEM_D_PINLOC_1), + .PORT_MEM_D_PINLOC_2 (PORT_MEM_D_PINLOC_2), + .PORT_MEM_D_PINLOC_3 (PORT_MEM_D_PINLOC_3), + .PORT_MEM_D_PINLOC_4 (PORT_MEM_D_PINLOC_4), + .PORT_MEM_D_PINLOC_5 (PORT_MEM_D_PINLOC_5), + .PORT_MEM_D_PINLOC_6 (PORT_MEM_D_PINLOC_6), + .PORT_MEM_D_PINLOC_7 (PORT_MEM_D_PINLOC_7), + .PORT_MEM_D_PINLOC_8 (PORT_MEM_D_PINLOC_8), + .PORT_MEM_D_PINLOC_9 (PORT_MEM_D_PINLOC_9), + .PORT_MEM_D_PINLOC_10 (PORT_MEM_D_PINLOC_10), + .PORT_MEM_D_PINLOC_11 (PORT_MEM_D_PINLOC_11), + .PORT_MEM_D_PINLOC_12 (PORT_MEM_D_PINLOC_12), + .PORT_MEM_D_PINLOC_13 (PORT_MEM_D_PINLOC_13), + .PORT_MEM_D_PINLOC_14 (PORT_MEM_D_PINLOC_14), + .PORT_MEM_D_PINLOC_15 (PORT_MEM_D_PINLOC_15), + .PORT_MEM_D_PINLOC_16 (PORT_MEM_D_PINLOC_16), + .PORT_MEM_D_PINLOC_17 (PORT_MEM_D_PINLOC_17), + .PORT_MEM_D_PINLOC_18 (PORT_MEM_D_PINLOC_18), + .PORT_MEM_D_PINLOC_19 (PORT_MEM_D_PINLOC_19), + .PORT_MEM_D_PINLOC_20 (PORT_MEM_D_PINLOC_20), + .PORT_MEM_D_PINLOC_21 (PORT_MEM_D_PINLOC_21), + .PORT_MEM_D_PINLOC_22 (PORT_MEM_D_PINLOC_22), + .PORT_MEM_D_PINLOC_23 (PORT_MEM_D_PINLOC_23), + .PORT_MEM_D_PINLOC_24 (PORT_MEM_D_PINLOC_24), + .PORT_MEM_D_PINLOC_25 (PORT_MEM_D_PINLOC_25), + .PORT_MEM_D_PINLOC_26 (PORT_MEM_D_PINLOC_26), + .PORT_MEM_D_PINLOC_27 (PORT_MEM_D_PINLOC_27), + .PORT_MEM_D_PINLOC_28 (PORT_MEM_D_PINLOC_28), + .PORT_MEM_D_PINLOC_29 (PORT_MEM_D_PINLOC_29), + .PORT_MEM_D_PINLOC_30 (PORT_MEM_D_PINLOC_30), + .PORT_MEM_D_PINLOC_31 (PORT_MEM_D_PINLOC_31), + .PORT_MEM_D_PINLOC_32 (PORT_MEM_D_PINLOC_32), + .PORT_MEM_D_PINLOC_33 (PORT_MEM_D_PINLOC_33), + .PORT_MEM_D_PINLOC_34 (PORT_MEM_D_PINLOC_34), + .PORT_MEM_D_PINLOC_35 (PORT_MEM_D_PINLOC_35), + .PORT_MEM_D_PINLOC_36 (PORT_MEM_D_PINLOC_36), + .PORT_MEM_D_PINLOC_37 (PORT_MEM_D_PINLOC_37), + .PORT_MEM_D_PINLOC_38 (PORT_MEM_D_PINLOC_38), + .PORT_MEM_D_PINLOC_39 (PORT_MEM_D_PINLOC_39), + .PORT_MEM_D_PINLOC_40 (PORT_MEM_D_PINLOC_40), + .PORT_MEM_D_PINLOC_41 (PORT_MEM_D_PINLOC_41), + .PORT_MEM_D_PINLOC_42 (PORT_MEM_D_PINLOC_42), + .PORT_MEM_D_PINLOC_43 (PORT_MEM_D_PINLOC_43), + .PORT_MEM_D_PINLOC_44 (PORT_MEM_D_PINLOC_44), + .PORT_MEM_D_PINLOC_45 (PORT_MEM_D_PINLOC_45), + .PORT_MEM_D_PINLOC_46 (PORT_MEM_D_PINLOC_46), + .PORT_MEM_D_PINLOC_47 (PORT_MEM_D_PINLOC_47), + .PORT_MEM_D_PINLOC_48 (PORT_MEM_D_PINLOC_48), + .PORT_MEM_D_PINLOC_AUTOGEN_WCNT (PORT_MEM_D_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DQ_PINLOC_0 (PORT_MEM_DQ_PINLOC_0), + .PORT_MEM_DQ_PINLOC_1 (PORT_MEM_DQ_PINLOC_1), + .PORT_MEM_DQ_PINLOC_2 (PORT_MEM_DQ_PINLOC_2), + .PORT_MEM_DQ_PINLOC_3 (PORT_MEM_DQ_PINLOC_3), + .PORT_MEM_DQ_PINLOC_4 (PORT_MEM_DQ_PINLOC_4), + .PORT_MEM_DQ_PINLOC_5 (PORT_MEM_DQ_PINLOC_5), + .PORT_MEM_DQ_PINLOC_6 (PORT_MEM_DQ_PINLOC_6), + .PORT_MEM_DQ_PINLOC_7 (PORT_MEM_DQ_PINLOC_7), + .PORT_MEM_DQ_PINLOC_8 (PORT_MEM_DQ_PINLOC_8), + .PORT_MEM_DQ_PINLOC_9 (PORT_MEM_DQ_PINLOC_9), + .PORT_MEM_DQ_PINLOC_10 (PORT_MEM_DQ_PINLOC_10), + .PORT_MEM_DQ_PINLOC_11 (PORT_MEM_DQ_PINLOC_11), + .PORT_MEM_DQ_PINLOC_12 (PORT_MEM_DQ_PINLOC_12), + .PORT_MEM_DQ_PINLOC_13 (PORT_MEM_DQ_PINLOC_13), + .PORT_MEM_DQ_PINLOC_14 (PORT_MEM_DQ_PINLOC_14), + .PORT_MEM_DQ_PINLOC_15 (PORT_MEM_DQ_PINLOC_15), + .PORT_MEM_DQ_PINLOC_16 (PORT_MEM_DQ_PINLOC_16), + .PORT_MEM_DQ_PINLOC_17 (PORT_MEM_DQ_PINLOC_17), + .PORT_MEM_DQ_PINLOC_18 (PORT_MEM_DQ_PINLOC_18), + .PORT_MEM_DQ_PINLOC_19 (PORT_MEM_DQ_PINLOC_19), + .PORT_MEM_DQ_PINLOC_20 (PORT_MEM_DQ_PINLOC_20), + .PORT_MEM_DQ_PINLOC_21 (PORT_MEM_DQ_PINLOC_21), + .PORT_MEM_DQ_PINLOC_22 (PORT_MEM_DQ_PINLOC_22), + .PORT_MEM_DQ_PINLOC_23 (PORT_MEM_DQ_PINLOC_23), + .PORT_MEM_DQ_PINLOC_24 (PORT_MEM_DQ_PINLOC_24), + .PORT_MEM_DQ_PINLOC_25 (PORT_MEM_DQ_PINLOC_25), + .PORT_MEM_DQ_PINLOC_26 (PORT_MEM_DQ_PINLOC_26), + .PORT_MEM_DQ_PINLOC_27 (PORT_MEM_DQ_PINLOC_27), + .PORT_MEM_DQ_PINLOC_28 (PORT_MEM_DQ_PINLOC_28), + .PORT_MEM_DQ_PINLOC_29 (PORT_MEM_DQ_PINLOC_29), + .PORT_MEM_DQ_PINLOC_30 (PORT_MEM_DQ_PINLOC_30), + .PORT_MEM_DQ_PINLOC_31 (PORT_MEM_DQ_PINLOC_31), + .PORT_MEM_DQ_PINLOC_32 (PORT_MEM_DQ_PINLOC_32), + .PORT_MEM_DQ_PINLOC_33 (PORT_MEM_DQ_PINLOC_33), + .PORT_MEM_DQ_PINLOC_34 (PORT_MEM_DQ_PINLOC_34), + .PORT_MEM_DQ_PINLOC_35 (PORT_MEM_DQ_PINLOC_35), + .PORT_MEM_DQ_PINLOC_36 (PORT_MEM_DQ_PINLOC_36), + .PORT_MEM_DQ_PINLOC_37 (PORT_MEM_DQ_PINLOC_37), + .PORT_MEM_DQ_PINLOC_38 (PORT_MEM_DQ_PINLOC_38), + .PORT_MEM_DQ_PINLOC_39 (PORT_MEM_DQ_PINLOC_39), + .PORT_MEM_DQ_PINLOC_40 (PORT_MEM_DQ_PINLOC_40), + .PORT_MEM_DQ_PINLOC_41 (PORT_MEM_DQ_PINLOC_41), + .PORT_MEM_DQ_PINLOC_42 (PORT_MEM_DQ_PINLOC_42), + .PORT_MEM_DQ_PINLOC_43 (PORT_MEM_DQ_PINLOC_43), + .PORT_MEM_DQ_PINLOC_44 (PORT_MEM_DQ_PINLOC_44), + .PORT_MEM_DQ_PINLOC_45 (PORT_MEM_DQ_PINLOC_45), + .PORT_MEM_DQ_PINLOC_46 (PORT_MEM_DQ_PINLOC_46), + .PORT_MEM_DQ_PINLOC_47 (PORT_MEM_DQ_PINLOC_47), + .PORT_MEM_DQ_PINLOC_48 (PORT_MEM_DQ_PINLOC_48), + .PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DBI_N_PINLOC_0 (PORT_MEM_DBI_N_PINLOC_0), + .PORT_MEM_DBI_N_PINLOC_1 (PORT_MEM_DBI_N_PINLOC_1), + .PORT_MEM_DBI_N_PINLOC_2 (PORT_MEM_DBI_N_PINLOC_2), + .PORT_MEM_DBI_N_PINLOC_3 (PORT_MEM_DBI_N_PINLOC_3), + .PORT_MEM_DBI_N_PINLOC_4 (PORT_MEM_DBI_N_PINLOC_4), + .PORT_MEM_DBI_N_PINLOC_5 (PORT_MEM_DBI_N_PINLOC_5), + .PORT_MEM_DBI_N_PINLOC_6 (PORT_MEM_DBI_N_PINLOC_6), + .PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQA_PINLOC_0 (PORT_MEM_DQA_PINLOC_0), + .PORT_MEM_DQA_PINLOC_1 (PORT_MEM_DQA_PINLOC_1), + .PORT_MEM_DQA_PINLOC_2 (PORT_MEM_DQA_PINLOC_2), + .PORT_MEM_DQA_PINLOC_3 (PORT_MEM_DQA_PINLOC_3), + .PORT_MEM_DQA_PINLOC_4 (PORT_MEM_DQA_PINLOC_4), + .PORT_MEM_DQA_PINLOC_5 (PORT_MEM_DQA_PINLOC_5), + .PORT_MEM_DQA_PINLOC_6 (PORT_MEM_DQA_PINLOC_6), + .PORT_MEM_DQA_PINLOC_7 (PORT_MEM_DQA_PINLOC_7), + .PORT_MEM_DQA_PINLOC_8 (PORT_MEM_DQA_PINLOC_8), + .PORT_MEM_DQA_PINLOC_9 (PORT_MEM_DQA_PINLOC_9), + .PORT_MEM_DQA_PINLOC_10 (PORT_MEM_DQA_PINLOC_10), + .PORT_MEM_DQA_PINLOC_11 (PORT_MEM_DQA_PINLOC_11), + .PORT_MEM_DQA_PINLOC_12 (PORT_MEM_DQA_PINLOC_12), + .PORT_MEM_DQA_PINLOC_13 (PORT_MEM_DQA_PINLOC_13), + .PORT_MEM_DQA_PINLOC_14 (PORT_MEM_DQA_PINLOC_14), + .PORT_MEM_DQA_PINLOC_15 (PORT_MEM_DQA_PINLOC_15), + .PORT_MEM_DQA_PINLOC_16 (PORT_MEM_DQA_PINLOC_16), + .PORT_MEM_DQA_PINLOC_17 (PORT_MEM_DQA_PINLOC_17), + .PORT_MEM_DQA_PINLOC_18 (PORT_MEM_DQA_PINLOC_18), + .PORT_MEM_DQA_PINLOC_19 (PORT_MEM_DQA_PINLOC_19), + .PORT_MEM_DQA_PINLOC_20 (PORT_MEM_DQA_PINLOC_20), + .PORT_MEM_DQA_PINLOC_21 (PORT_MEM_DQA_PINLOC_21), + .PORT_MEM_DQA_PINLOC_22 (PORT_MEM_DQA_PINLOC_22), + .PORT_MEM_DQA_PINLOC_23 (PORT_MEM_DQA_PINLOC_23), + .PORT_MEM_DQA_PINLOC_24 (PORT_MEM_DQA_PINLOC_24), + .PORT_MEM_DQA_PINLOC_25 (PORT_MEM_DQA_PINLOC_25), + .PORT_MEM_DQA_PINLOC_26 (PORT_MEM_DQA_PINLOC_26), + .PORT_MEM_DQA_PINLOC_27 (PORT_MEM_DQA_PINLOC_27), + .PORT_MEM_DQA_PINLOC_28 (PORT_MEM_DQA_PINLOC_28), + .PORT_MEM_DQA_PINLOC_29 (PORT_MEM_DQA_PINLOC_29), + .PORT_MEM_DQA_PINLOC_30 (PORT_MEM_DQA_PINLOC_30), + .PORT_MEM_DQA_PINLOC_31 (PORT_MEM_DQA_PINLOC_31), + .PORT_MEM_DQA_PINLOC_32 (PORT_MEM_DQA_PINLOC_32), + .PORT_MEM_DQA_PINLOC_33 (PORT_MEM_DQA_PINLOC_33), + .PORT_MEM_DQA_PINLOC_34 (PORT_MEM_DQA_PINLOC_34), + .PORT_MEM_DQA_PINLOC_35 (PORT_MEM_DQA_PINLOC_35), + .PORT_MEM_DQA_PINLOC_36 (PORT_MEM_DQA_PINLOC_36), + .PORT_MEM_DQA_PINLOC_37 (PORT_MEM_DQA_PINLOC_37), + .PORT_MEM_DQA_PINLOC_38 (PORT_MEM_DQA_PINLOC_38), + .PORT_MEM_DQA_PINLOC_39 (PORT_MEM_DQA_PINLOC_39), + .PORT_MEM_DQA_PINLOC_40 (PORT_MEM_DQA_PINLOC_40), + .PORT_MEM_DQA_PINLOC_41 (PORT_MEM_DQA_PINLOC_41), + .PORT_MEM_DQA_PINLOC_42 (PORT_MEM_DQA_PINLOC_42), + .PORT_MEM_DQA_PINLOC_43 (PORT_MEM_DQA_PINLOC_43), + .PORT_MEM_DQA_PINLOC_44 (PORT_MEM_DQA_PINLOC_44), + .PORT_MEM_DQA_PINLOC_45 (PORT_MEM_DQA_PINLOC_45), + .PORT_MEM_DQA_PINLOC_46 (PORT_MEM_DQA_PINLOC_46), + .PORT_MEM_DQA_PINLOC_47 (PORT_MEM_DQA_PINLOC_47), + .PORT_MEM_DQA_PINLOC_48 (PORT_MEM_DQA_PINLOC_48), + .PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DQB_PINLOC_0 (PORT_MEM_DQB_PINLOC_0), + .PORT_MEM_DQB_PINLOC_1 (PORT_MEM_DQB_PINLOC_1), + .PORT_MEM_DQB_PINLOC_2 (PORT_MEM_DQB_PINLOC_2), + .PORT_MEM_DQB_PINLOC_3 (PORT_MEM_DQB_PINLOC_3), + .PORT_MEM_DQB_PINLOC_4 (PORT_MEM_DQB_PINLOC_4), + .PORT_MEM_DQB_PINLOC_5 (PORT_MEM_DQB_PINLOC_5), + .PORT_MEM_DQB_PINLOC_6 (PORT_MEM_DQB_PINLOC_6), + .PORT_MEM_DQB_PINLOC_7 (PORT_MEM_DQB_PINLOC_7), + .PORT_MEM_DQB_PINLOC_8 (PORT_MEM_DQB_PINLOC_8), + .PORT_MEM_DQB_PINLOC_9 (PORT_MEM_DQB_PINLOC_9), + .PORT_MEM_DQB_PINLOC_10 (PORT_MEM_DQB_PINLOC_10), + .PORT_MEM_DQB_PINLOC_11 (PORT_MEM_DQB_PINLOC_11), + .PORT_MEM_DQB_PINLOC_12 (PORT_MEM_DQB_PINLOC_12), + .PORT_MEM_DQB_PINLOC_13 (PORT_MEM_DQB_PINLOC_13), + .PORT_MEM_DQB_PINLOC_14 (PORT_MEM_DQB_PINLOC_14), + .PORT_MEM_DQB_PINLOC_15 (PORT_MEM_DQB_PINLOC_15), + .PORT_MEM_DQB_PINLOC_16 (PORT_MEM_DQB_PINLOC_16), + .PORT_MEM_DQB_PINLOC_17 (PORT_MEM_DQB_PINLOC_17), + .PORT_MEM_DQB_PINLOC_18 (PORT_MEM_DQB_PINLOC_18), + .PORT_MEM_DQB_PINLOC_19 (PORT_MEM_DQB_PINLOC_19), + .PORT_MEM_DQB_PINLOC_20 (PORT_MEM_DQB_PINLOC_20), + .PORT_MEM_DQB_PINLOC_21 (PORT_MEM_DQB_PINLOC_21), + .PORT_MEM_DQB_PINLOC_22 (PORT_MEM_DQB_PINLOC_22), + .PORT_MEM_DQB_PINLOC_23 (PORT_MEM_DQB_PINLOC_23), + .PORT_MEM_DQB_PINLOC_24 (PORT_MEM_DQB_PINLOC_24), + .PORT_MEM_DQB_PINLOC_25 (PORT_MEM_DQB_PINLOC_25), + .PORT_MEM_DQB_PINLOC_26 (PORT_MEM_DQB_PINLOC_26), + .PORT_MEM_DQB_PINLOC_27 (PORT_MEM_DQB_PINLOC_27), + .PORT_MEM_DQB_PINLOC_28 (PORT_MEM_DQB_PINLOC_28), + .PORT_MEM_DQB_PINLOC_29 (PORT_MEM_DQB_PINLOC_29), + .PORT_MEM_DQB_PINLOC_30 (PORT_MEM_DQB_PINLOC_30), + .PORT_MEM_DQB_PINLOC_31 (PORT_MEM_DQB_PINLOC_31), + .PORT_MEM_DQB_PINLOC_32 (PORT_MEM_DQB_PINLOC_32), + .PORT_MEM_DQB_PINLOC_33 (PORT_MEM_DQB_PINLOC_33), + .PORT_MEM_DQB_PINLOC_34 (PORT_MEM_DQB_PINLOC_34), + .PORT_MEM_DQB_PINLOC_35 (PORT_MEM_DQB_PINLOC_35), + .PORT_MEM_DQB_PINLOC_36 (PORT_MEM_DQB_PINLOC_36), + .PORT_MEM_DQB_PINLOC_37 (PORT_MEM_DQB_PINLOC_37), + .PORT_MEM_DQB_PINLOC_38 (PORT_MEM_DQB_PINLOC_38), + .PORT_MEM_DQB_PINLOC_39 (PORT_MEM_DQB_PINLOC_39), + .PORT_MEM_DQB_PINLOC_40 (PORT_MEM_DQB_PINLOC_40), + .PORT_MEM_DQB_PINLOC_41 (PORT_MEM_DQB_PINLOC_41), + .PORT_MEM_DQB_PINLOC_42 (PORT_MEM_DQB_PINLOC_42), + .PORT_MEM_DQB_PINLOC_43 (PORT_MEM_DQB_PINLOC_43), + .PORT_MEM_DQB_PINLOC_44 (PORT_MEM_DQB_PINLOC_44), + .PORT_MEM_DQB_PINLOC_45 (PORT_MEM_DQB_PINLOC_45), + .PORT_MEM_DQB_PINLOC_46 (PORT_MEM_DQB_PINLOC_46), + .PORT_MEM_DQB_PINLOC_47 (PORT_MEM_DQB_PINLOC_47), + .PORT_MEM_DQB_PINLOC_48 (PORT_MEM_DQB_PINLOC_48), + .PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVA_PINLOC_0 (PORT_MEM_DINVA_PINLOC_0), + .PORT_MEM_DINVA_PINLOC_1 (PORT_MEM_DINVA_PINLOC_1), + .PORT_MEM_DINVA_PINLOC_2 (PORT_MEM_DINVA_PINLOC_2), + .PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_DINVB_PINLOC_0 (PORT_MEM_DINVB_PINLOC_0), + .PORT_MEM_DINVB_PINLOC_1 (PORT_MEM_DINVB_PINLOC_1), + .PORT_MEM_DINVB_PINLOC_2 (PORT_MEM_DINVB_PINLOC_2), + .PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_Q_PINLOC_0 (PORT_MEM_Q_PINLOC_0), + .PORT_MEM_Q_PINLOC_1 (PORT_MEM_Q_PINLOC_1), + .PORT_MEM_Q_PINLOC_2 (PORT_MEM_Q_PINLOC_2), + .PORT_MEM_Q_PINLOC_3 (PORT_MEM_Q_PINLOC_3), + .PORT_MEM_Q_PINLOC_4 (PORT_MEM_Q_PINLOC_4), + .PORT_MEM_Q_PINLOC_5 (PORT_MEM_Q_PINLOC_5), + .PORT_MEM_Q_PINLOC_6 (PORT_MEM_Q_PINLOC_6), + .PORT_MEM_Q_PINLOC_7 (PORT_MEM_Q_PINLOC_7), + .PORT_MEM_Q_PINLOC_8 (PORT_MEM_Q_PINLOC_8), + .PORT_MEM_Q_PINLOC_9 (PORT_MEM_Q_PINLOC_9), + .PORT_MEM_Q_PINLOC_10 (PORT_MEM_Q_PINLOC_10), + .PORT_MEM_Q_PINLOC_11 (PORT_MEM_Q_PINLOC_11), + .PORT_MEM_Q_PINLOC_12 (PORT_MEM_Q_PINLOC_12), + .PORT_MEM_Q_PINLOC_13 (PORT_MEM_Q_PINLOC_13), + .PORT_MEM_Q_PINLOC_14 (PORT_MEM_Q_PINLOC_14), + .PORT_MEM_Q_PINLOC_15 (PORT_MEM_Q_PINLOC_15), + .PORT_MEM_Q_PINLOC_16 (PORT_MEM_Q_PINLOC_16), + .PORT_MEM_Q_PINLOC_17 (PORT_MEM_Q_PINLOC_17), + .PORT_MEM_Q_PINLOC_18 (PORT_MEM_Q_PINLOC_18), + .PORT_MEM_Q_PINLOC_19 (PORT_MEM_Q_PINLOC_19), + .PORT_MEM_Q_PINLOC_20 (PORT_MEM_Q_PINLOC_20), + .PORT_MEM_Q_PINLOC_21 (PORT_MEM_Q_PINLOC_21), + .PORT_MEM_Q_PINLOC_22 (PORT_MEM_Q_PINLOC_22), + .PORT_MEM_Q_PINLOC_23 (PORT_MEM_Q_PINLOC_23), + .PORT_MEM_Q_PINLOC_24 (PORT_MEM_Q_PINLOC_24), + .PORT_MEM_Q_PINLOC_25 (PORT_MEM_Q_PINLOC_25), + .PORT_MEM_Q_PINLOC_26 (PORT_MEM_Q_PINLOC_26), + .PORT_MEM_Q_PINLOC_27 (PORT_MEM_Q_PINLOC_27), + .PORT_MEM_Q_PINLOC_28 (PORT_MEM_Q_PINLOC_28), + .PORT_MEM_Q_PINLOC_29 (PORT_MEM_Q_PINLOC_29), + .PORT_MEM_Q_PINLOC_30 (PORT_MEM_Q_PINLOC_30), + .PORT_MEM_Q_PINLOC_31 (PORT_MEM_Q_PINLOC_31), + .PORT_MEM_Q_PINLOC_32 (PORT_MEM_Q_PINLOC_32), + .PORT_MEM_Q_PINLOC_33 (PORT_MEM_Q_PINLOC_33), + .PORT_MEM_Q_PINLOC_34 (PORT_MEM_Q_PINLOC_34), + .PORT_MEM_Q_PINLOC_35 (PORT_MEM_Q_PINLOC_35), + .PORT_MEM_Q_PINLOC_36 (PORT_MEM_Q_PINLOC_36), + .PORT_MEM_Q_PINLOC_37 (PORT_MEM_Q_PINLOC_37), + .PORT_MEM_Q_PINLOC_38 (PORT_MEM_Q_PINLOC_38), + .PORT_MEM_Q_PINLOC_39 (PORT_MEM_Q_PINLOC_39), + .PORT_MEM_Q_PINLOC_40 (PORT_MEM_Q_PINLOC_40), + .PORT_MEM_Q_PINLOC_41 (PORT_MEM_Q_PINLOC_41), + .PORT_MEM_Q_PINLOC_42 (PORT_MEM_Q_PINLOC_42), + .PORT_MEM_Q_PINLOC_43 (PORT_MEM_Q_PINLOC_43), + .PORT_MEM_Q_PINLOC_44 (PORT_MEM_Q_PINLOC_44), + .PORT_MEM_Q_PINLOC_45 (PORT_MEM_Q_PINLOC_45), + .PORT_MEM_Q_PINLOC_46 (PORT_MEM_Q_PINLOC_46), + .PORT_MEM_Q_PINLOC_47 (PORT_MEM_Q_PINLOC_47), + .PORT_MEM_Q_PINLOC_48 (PORT_MEM_Q_PINLOC_48), + .PORT_MEM_Q_PINLOC_AUTOGEN_WCNT (PORT_MEM_Q_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_PINLOC_0 (PORT_MEM_DQS_PINLOC_0), + .PORT_MEM_DQS_PINLOC_1 (PORT_MEM_DQS_PINLOC_1), + .PORT_MEM_DQS_PINLOC_2 (PORT_MEM_DQS_PINLOC_2), + .PORT_MEM_DQS_PINLOC_3 (PORT_MEM_DQS_PINLOC_3), + .PORT_MEM_DQS_PINLOC_4 (PORT_MEM_DQS_PINLOC_4), + .PORT_MEM_DQS_PINLOC_5 (PORT_MEM_DQS_PINLOC_5), + .PORT_MEM_DQS_PINLOC_6 (PORT_MEM_DQS_PINLOC_6), + .PORT_MEM_DQS_PINLOC_7 (PORT_MEM_DQS_PINLOC_7), + .PORT_MEM_DQS_PINLOC_8 (PORT_MEM_DQS_PINLOC_8), + .PORT_MEM_DQS_PINLOC_9 (PORT_MEM_DQS_PINLOC_9), + .PORT_MEM_DQS_PINLOC_10 (PORT_MEM_DQS_PINLOC_10), + .PORT_MEM_DQS_PINLOC_11 (PORT_MEM_DQS_PINLOC_11), + .PORT_MEM_DQS_PINLOC_12 (PORT_MEM_DQS_PINLOC_12), + .PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_DQS_N_PINLOC_0 (PORT_MEM_DQS_N_PINLOC_0), + .PORT_MEM_DQS_N_PINLOC_1 (PORT_MEM_DQS_N_PINLOC_1), + .PORT_MEM_DQS_N_PINLOC_2 (PORT_MEM_DQS_N_PINLOC_2), + .PORT_MEM_DQS_N_PINLOC_3 (PORT_MEM_DQS_N_PINLOC_3), + .PORT_MEM_DQS_N_PINLOC_4 (PORT_MEM_DQS_N_PINLOC_4), + .PORT_MEM_DQS_N_PINLOC_5 (PORT_MEM_DQS_N_PINLOC_5), + .PORT_MEM_DQS_N_PINLOC_6 (PORT_MEM_DQS_N_PINLOC_6), + .PORT_MEM_DQS_N_PINLOC_7 (PORT_MEM_DQS_N_PINLOC_7), + .PORT_MEM_DQS_N_PINLOC_8 (PORT_MEM_DQS_N_PINLOC_8), + .PORT_MEM_DQS_N_PINLOC_9 (PORT_MEM_DQS_N_PINLOC_9), + .PORT_MEM_DQS_N_PINLOC_10 (PORT_MEM_DQS_N_PINLOC_10), + .PORT_MEM_DQS_N_PINLOC_11 (PORT_MEM_DQS_N_PINLOC_11), + .PORT_MEM_DQS_N_PINLOC_12 (PORT_MEM_DQS_N_PINLOC_12), + .PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_PINLOC_0 (PORT_MEM_QK_PINLOC_0), + .PORT_MEM_QK_PINLOC_1 (PORT_MEM_QK_PINLOC_1), + .PORT_MEM_QK_PINLOC_2 (PORT_MEM_QK_PINLOC_2), + .PORT_MEM_QK_PINLOC_3 (PORT_MEM_QK_PINLOC_3), + .PORT_MEM_QK_PINLOC_4 (PORT_MEM_QK_PINLOC_4), + .PORT_MEM_QK_PINLOC_5 (PORT_MEM_QK_PINLOC_5), + .PORT_MEM_QK_PINLOC_AUTOGEN_WCNT (PORT_MEM_QK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QK_N_PINLOC_0 (PORT_MEM_QK_N_PINLOC_0), + .PORT_MEM_QK_N_PINLOC_1 (PORT_MEM_QK_N_PINLOC_1), + .PORT_MEM_QK_N_PINLOC_2 (PORT_MEM_QK_N_PINLOC_2), + .PORT_MEM_QK_N_PINLOC_3 (PORT_MEM_QK_N_PINLOC_3), + .PORT_MEM_QK_N_PINLOC_4 (PORT_MEM_QK_N_PINLOC_4), + .PORT_MEM_QK_N_PINLOC_5 (PORT_MEM_QK_N_PINLOC_5), + .PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_PINLOC_0 (PORT_MEM_QKA_PINLOC_0), + .PORT_MEM_QKA_PINLOC_1 (PORT_MEM_QKA_PINLOC_1), + .PORT_MEM_QKA_PINLOC_2 (PORT_MEM_QKA_PINLOC_2), + .PORT_MEM_QKA_PINLOC_3 (PORT_MEM_QKA_PINLOC_3), + .PORT_MEM_QKA_PINLOC_4 (PORT_MEM_QKA_PINLOC_4), + .PORT_MEM_QKA_PINLOC_5 (PORT_MEM_QKA_PINLOC_5), + .PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKA_N_PINLOC_0 (PORT_MEM_QKA_N_PINLOC_0), + .PORT_MEM_QKA_N_PINLOC_1 (PORT_MEM_QKA_N_PINLOC_1), + .PORT_MEM_QKA_N_PINLOC_2 (PORT_MEM_QKA_N_PINLOC_2), + .PORT_MEM_QKA_N_PINLOC_3 (PORT_MEM_QKA_N_PINLOC_3), + .PORT_MEM_QKA_N_PINLOC_4 (PORT_MEM_QKA_N_PINLOC_4), + .PORT_MEM_QKA_N_PINLOC_5 (PORT_MEM_QKA_N_PINLOC_5), + .PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_PINLOC_0 (PORT_MEM_QKB_PINLOC_0), + .PORT_MEM_QKB_PINLOC_1 (PORT_MEM_QKB_PINLOC_1), + .PORT_MEM_QKB_PINLOC_2 (PORT_MEM_QKB_PINLOC_2), + .PORT_MEM_QKB_PINLOC_3 (PORT_MEM_QKB_PINLOC_3), + .PORT_MEM_QKB_PINLOC_4 (PORT_MEM_QKB_PINLOC_4), + .PORT_MEM_QKB_PINLOC_5 (PORT_MEM_QKB_PINLOC_5), + .PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_QKB_N_PINLOC_0 (PORT_MEM_QKB_N_PINLOC_0), + .PORT_MEM_QKB_N_PINLOC_1 (PORT_MEM_QKB_N_PINLOC_1), + .PORT_MEM_QKB_N_PINLOC_2 (PORT_MEM_QKB_N_PINLOC_2), + .PORT_MEM_QKB_N_PINLOC_3 (PORT_MEM_QKB_N_PINLOC_3), + .PORT_MEM_QKB_N_PINLOC_4 (PORT_MEM_QKB_N_PINLOC_4), + .PORT_MEM_QKB_N_PINLOC_5 (PORT_MEM_QKB_N_PINLOC_5), + .PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_PINLOC_0 (PORT_MEM_CQ_PINLOC_0), + .PORT_MEM_CQ_PINLOC_1 (PORT_MEM_CQ_PINLOC_1), + .PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT (PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_CQ_N_PINLOC_0 (PORT_MEM_CQ_N_PINLOC_0), + .PORT_MEM_CQ_N_PINLOC_1 (PORT_MEM_CQ_N_PINLOC_1), + .PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_ALERT_N_PINLOC_0 (PORT_MEM_ALERT_N_PINLOC_0), + .PORT_MEM_ALERT_N_PINLOC_1 (PORT_MEM_ALERT_N_PINLOC_1), + .PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + .PORT_MEM_PE_N_PINLOC_0 (PORT_MEM_PE_N_PINLOC_0), + .PORT_MEM_PE_N_PINLOC_1 (PORT_MEM_PE_N_PINLOC_1), + .PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .PORT_CLKS_SHARING_SLAVE_OUT_WIDTH (PORT_CLKS_SHARING_SLAVE_OUT_WIDTH), + .PORT_AFI_RLAT_WIDTH (PORT_AFI_RLAT_WIDTH), + .PORT_AFI_WLAT_WIDTH (PORT_AFI_WLAT_WIDTH), + .PORT_AFI_SEQ_BUSY_WIDTH (PORT_AFI_SEQ_BUSY_WIDTH), + .PORT_AFI_ADDR_WIDTH (PORT_AFI_ADDR_WIDTH), + .PORT_AFI_BA_WIDTH (PORT_AFI_BA_WIDTH), + .PORT_AFI_BG_WIDTH (PORT_AFI_BG_WIDTH), + .PORT_AFI_C_WIDTH (PORT_AFI_C_WIDTH), + .PORT_AFI_CKE_WIDTH (PORT_AFI_CKE_WIDTH), + .PORT_AFI_CS_N_WIDTH (PORT_AFI_CS_N_WIDTH), + .PORT_AFI_RM_WIDTH (PORT_AFI_RM_WIDTH), + .PORT_AFI_ODT_WIDTH (PORT_AFI_ODT_WIDTH), + .PORT_AFI_RAS_N_WIDTH (PORT_AFI_RAS_N_WIDTH), + .PORT_AFI_CAS_N_WIDTH (PORT_AFI_CAS_N_WIDTH), + .PORT_AFI_WE_N_WIDTH (PORT_AFI_WE_N_WIDTH), + .PORT_AFI_RST_N_WIDTH (PORT_AFI_RST_N_WIDTH), + .PORT_AFI_ACT_N_WIDTH (PORT_AFI_ACT_N_WIDTH), + .PORT_AFI_REQ_N_WIDTH (PORT_AFI_REQ_N_WIDTH), + .PORT_AFI_GNT_N_WIDTH (PORT_AFI_GNT_N_WIDTH), + .PORT_AFI_ERR_N_WIDTH (PORT_AFI_ERR_N_WIDTH), + .PORT_AFI_PAR_WIDTH (PORT_AFI_PAR_WIDTH), + .PORT_AFI_CA_WIDTH (PORT_AFI_CA_WIDTH), + .PORT_AFI_REF_N_WIDTH (PORT_AFI_REF_N_WIDTH), + .PORT_AFI_WPS_N_WIDTH (PORT_AFI_WPS_N_WIDTH), + .PORT_AFI_RPS_N_WIDTH (PORT_AFI_RPS_N_WIDTH), + .PORT_AFI_DOFF_N_WIDTH (PORT_AFI_DOFF_N_WIDTH), + .PORT_AFI_LD_N_WIDTH (PORT_AFI_LD_N_WIDTH), + .PORT_AFI_RW_N_WIDTH (PORT_AFI_RW_N_WIDTH), + .PORT_AFI_LBK0_N_WIDTH (PORT_AFI_LBK0_N_WIDTH), + .PORT_AFI_LBK1_N_WIDTH (PORT_AFI_LBK1_N_WIDTH), + .PORT_AFI_CFG_N_WIDTH (PORT_AFI_CFG_N_WIDTH), + .PORT_AFI_AP_WIDTH (PORT_AFI_AP_WIDTH), + .PORT_AFI_AINV_WIDTH (PORT_AFI_AINV_WIDTH), + .PORT_AFI_DM_WIDTH (PORT_AFI_DM_WIDTH), + .PORT_AFI_DM_N_WIDTH (PORT_AFI_DM_N_WIDTH), + .PORT_AFI_BWS_N_WIDTH (PORT_AFI_BWS_N_WIDTH), + .PORT_AFI_RDATA_DBI_N_WIDTH (PORT_AFI_RDATA_DBI_N_WIDTH), + .PORT_AFI_WDATA_DBI_N_WIDTH (PORT_AFI_WDATA_DBI_N_WIDTH), + .PORT_AFI_RDATA_DINV_WIDTH (PORT_AFI_RDATA_DINV_WIDTH), + .PORT_AFI_WDATA_DINV_WIDTH (PORT_AFI_WDATA_DINV_WIDTH), + .PORT_AFI_DQS_BURST_WIDTH (PORT_AFI_DQS_BURST_WIDTH), + .PORT_AFI_WDATA_VALID_WIDTH (PORT_AFI_WDATA_VALID_WIDTH), + .PORT_AFI_WDATA_WIDTH (PORT_AFI_WDATA_WIDTH), + .PORT_AFI_RDATA_EN_FULL_WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH), + .PORT_AFI_RDATA_WIDTH (PORT_AFI_RDATA_WIDTH), + .PORT_AFI_RDATA_VALID_WIDTH (PORT_AFI_RDATA_VALID_WIDTH), + .PORT_AFI_RRANK_WIDTH (PORT_AFI_RRANK_WIDTH), + .PORT_AFI_WRANK_WIDTH (PORT_AFI_WRANK_WIDTH), + .PORT_AFI_ALERT_N_WIDTH (PORT_AFI_ALERT_N_WIDTH), + .PORT_AFI_PE_N_WIDTH (PORT_AFI_PE_N_WIDTH), + .PORT_CTRL_AST_CMD_DATA_WIDTH (PORT_CTRL_AST_CMD_DATA_WIDTH), + .PORT_CTRL_AST_WR_DATA_WIDTH (PORT_CTRL_AST_WR_DATA_WIDTH), + .PORT_CTRL_AST_RD_DATA_WIDTH (PORT_CTRL_AST_RD_DATA_WIDTH), + .PORT_CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .PORT_CTRL_AMM_RDATA_WIDTH (PORT_CTRL_AMM_RDATA_WIDTH), + .PORT_CTRL_AMM_WDATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .PORT_CTRL_AMM_BCOUNT_WIDTH (PORT_CTRL_AMM_BCOUNT_WIDTH), + .PORT_CTRL_AMM_BYTEEN_WIDTH (PORT_CTRL_AMM_BYTEEN_WIDTH), + .PORT_CTRL_STROBE_WIDTH (PORT_CTRL_STROBE_WIDTH), + .PORT_CTRL_STROBE_OE_WIDTH (PORT_CTRL_STROBE_OE_WIDTH), + .PORT_CTRL_DATA_OE_WIDTH (PORT_CTRL_DATA_OE_WIDTH), + .PORT_CTRL_DATA_OUT_WIDTH (PORT_CTRL_DATA_OUT_WIDTH), + .PORT_CTRL_DATA_IN_WIDTH (PORT_CTRL_DATA_IN_WIDTH), + .PORT_CTRL_RDATA_VALID_WIDTH (PORT_CTRL_RDATA_VALID_WIDTH), + .PORT_CTRL_LOCKED_WIDTH (PORT_CTRL_LOCKED_WIDTH), + .PORT_CTRL_RDATA_ENABLE_WIDTH (PORT_CTRL_RDATA_ENABLE_WIDTH), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (PORT_CTRL_USER_REFRESH_REQ_WIDTH), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (PORT_CTRL_USER_REFRESH_BANK_WIDTH), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (PORT_CTRL_SELF_REFRESH_REQ_WIDTH), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (PORT_CTRL_ECC_WRITE_INFO_WIDTH), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (PORT_CTRL_ECC_RDATA_ID_WIDTH), + .PORT_CTRL_ECC_READ_INFO_WIDTH (PORT_CTRL_ECC_READ_INFO_WIDTH), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (PORT_CTRL_ECC_CMD_INFO_WIDTH), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (PORT_CTRL_ECC_WB_POINTER_WIDTH), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (PORT_CTRL_MMR_SLAVE_RDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (PORT_CTRL_MMR_SLAVE_WDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH), + .PORT_HPS_EMIF_H2E_WIDTH (PORT_HPS_EMIF_H2E_WIDTH), + .PORT_HPS_EMIF_E2H_WIDTH (PORT_HPS_EMIF_E2H_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PORT_HPS_EMIF_E2H_GP_WIDTH (PORT_HPS_EMIF_E2H_GP_WIDTH), + .PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH), + .PORT_DFT_ND_PLL_CNTSEL_WIDTH (PORT_DFT_ND_PLL_CNTSEL_WIDTH), + .PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH (PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH), + .PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH (PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH), + .PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH (PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH), + .PORT_CALBUS_ADDRESS_WIDTH (PORT_CALBUS_ADDRESS_WIDTH), + .PORT_CALBUS_WDATA_WIDTH (PORT_CALBUS_WDATA_WIDTH), + .PORT_CALBUS_RDATA_WIDTH (PORT_CALBUS_RDATA_WIDTH), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (PORT_CALBUS_SEQ_PARAM_TBL_WIDTH), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .PLL_MEM_CLK_FREQ_PS (PLL_MEM_CLK_FREQ_PS), + .PLL_PHY_CLK_VCO_PHASE (PLL_PHY_CLK_VCO_PHASE), + .PLL_VCO_FREQ_PS_STR (PLL_VCO_FREQ_PS_STR), + .PLL_VCO_FREQ_MHZ_STR (PLL_VCO_FREQ_MHZ_STR), + .PLL_REF_CLK_FREQ_PS_STR (PLL_REF_CLK_FREQ_PS_STR), + .PLL_REF_CLK_FREQ_MHZ_STR (PLL_REF_CLK_FREQ_MHZ_STR), + .PLL_REF_CLK_FREQ_PS (PLL_REF_CLK_FREQ_PS), + .PLL_SIM_VCO_FREQ_PS (PLL_SIM_VCO_FREQ_PS), + .PLL_SIM_PHYCLK_0_FREQ_PS (PLL_SIM_PHYCLK_0_FREQ_PS), + .PLL_SIM_PHYCLK_1_FREQ_PS (PLL_SIM_PHYCLK_1_FREQ_PS), + .PLL_SIM_PHYCLK_FB_FREQ_PS (PLL_SIM_PHYCLK_FB_FREQ_PS), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (PLL_SIM_PHY_CLK_VCO_PHASE_PS), + .PLL_M_CNT_HIGH (PLL_M_CNT_HIGH), + .PLL_M_CNT_LOW (PLL_M_CNT_LOW), + .PLL_N_CNT_HIGH (PLL_N_CNT_HIGH), + .PLL_N_CNT_LOW (PLL_N_CNT_LOW), + .PLL_M_CNT_BYPASS_EN (PLL_M_CNT_BYPASS_EN), + .PLL_N_CNT_BYPASS_EN (PLL_N_CNT_BYPASS_EN), + .PLL_M_CNT_EVEN_DUTY_EN (PLL_M_CNT_EVEN_DUTY_EN), + .PLL_N_CNT_EVEN_DUTY_EN (PLL_N_CNT_EVEN_DUTY_EN), + .PLL_FBCLK_MUX_1 (PLL_FBCLK_MUX_1), + .PLL_FBCLK_MUX_2 (PLL_FBCLK_MUX_2), + .PLL_M_CNT_IN_SRC (PLL_M_CNT_IN_SRC), + .PLL_CP_SETTING (PLL_CP_SETTING), + .PLL_BW_CTRL (PLL_BW_CTRL), + .PLL_BW_SEL (PLL_BW_SEL), + .PLL_C_CNT_HIGH_0 (PLL_C_CNT_HIGH_0), + .PLL_C_CNT_LOW_0 (PLL_C_CNT_LOW_0), + .PLL_C_CNT_PRST_0 (PLL_C_CNT_PRST_0), + .PLL_C_CNT_PH_MUX_PRST_0 (PLL_C_CNT_PH_MUX_PRST_0), + .PLL_C_CNT_BYPASS_EN_0 (PLL_C_CNT_BYPASS_EN_0), + .PLL_C_CNT_EVEN_DUTY_EN_0 (PLL_C_CNT_EVEN_DUTY_EN_0), + .PLL_C_CNT_FREQ_PS_STR_0 (PLL_C_CNT_FREQ_PS_STR_0), + .PLL_C_CNT_FREQ_MHZ_STR_0 (PLL_C_CNT_FREQ_MHZ_STR_0), + .PLL_C_CNT_PHASE_PS_STR_0 (PLL_C_CNT_PHASE_PS_STR_0), + .PLL_C_CNT_DUTY_CYCLE_0 (PLL_C_CNT_DUTY_CYCLE_0), + .PLL_C_CNT_OUT_EN_0 (PLL_C_CNT_OUT_EN_0), + .PLL_C_CNT_HIGH_1 (PLL_C_CNT_HIGH_1), + .PLL_C_CNT_LOW_1 (PLL_C_CNT_LOW_1), + .PLL_C_CNT_PRST_1 (PLL_C_CNT_PRST_1), + .PLL_C_CNT_PH_MUX_PRST_1 (PLL_C_CNT_PH_MUX_PRST_1), + .PLL_C_CNT_BYPASS_EN_1 (PLL_C_CNT_BYPASS_EN_1), + .PLL_C_CNT_EVEN_DUTY_EN_1 (PLL_C_CNT_EVEN_DUTY_EN_1), + .PLL_C_CNT_FREQ_PS_STR_1 (PLL_C_CNT_FREQ_PS_STR_1), + .PLL_C_CNT_FREQ_MHZ_STR_1 (PLL_C_CNT_FREQ_MHZ_STR_1), + .PLL_C_CNT_PHASE_PS_STR_1 (PLL_C_CNT_PHASE_PS_STR_1), + .PLL_C_CNT_DUTY_CYCLE_1 (PLL_C_CNT_DUTY_CYCLE_1), + .PLL_C_CNT_OUT_EN_1 (PLL_C_CNT_OUT_EN_1), + .PLL_C_CNT_HIGH_2 (PLL_C_CNT_HIGH_2), + .PLL_C_CNT_LOW_2 (PLL_C_CNT_LOW_2), + .PLL_C_CNT_PRST_2 (PLL_C_CNT_PRST_2), + .PLL_C_CNT_PH_MUX_PRST_2 (PLL_C_CNT_PH_MUX_PRST_2), + .PLL_C_CNT_BYPASS_EN_2 (PLL_C_CNT_BYPASS_EN_2), + .PLL_C_CNT_EVEN_DUTY_EN_2 (PLL_C_CNT_EVEN_DUTY_EN_2), + .PLL_C_CNT_FREQ_PS_STR_2 (PLL_C_CNT_FREQ_PS_STR_2), + .PLL_C_CNT_FREQ_MHZ_STR_2 (PLL_C_CNT_FREQ_MHZ_STR_2), + .PLL_C_CNT_PHASE_PS_STR_2 (PLL_C_CNT_PHASE_PS_STR_2), + .PLL_C_CNT_DUTY_CYCLE_2 (PLL_C_CNT_DUTY_CYCLE_2), + .PLL_C_CNT_OUT_EN_2 (PLL_C_CNT_OUT_EN_2), + .PLL_C_CNT_HIGH_3 (PLL_C_CNT_HIGH_3), + .PLL_C_CNT_LOW_3 (PLL_C_CNT_LOW_3), + .PLL_C_CNT_PRST_3 (PLL_C_CNT_PRST_3), + .PLL_C_CNT_PH_MUX_PRST_3 (PLL_C_CNT_PH_MUX_PRST_3), + .PLL_C_CNT_BYPASS_EN_3 (PLL_C_CNT_BYPASS_EN_3), + .PLL_C_CNT_EVEN_DUTY_EN_3 (PLL_C_CNT_EVEN_DUTY_EN_3), + .PLL_C_CNT_FREQ_PS_STR_3 (PLL_C_CNT_FREQ_PS_STR_3), + .PLL_C_CNT_FREQ_MHZ_STR_3 (PLL_C_CNT_FREQ_MHZ_STR_3), + .PLL_C_CNT_PHASE_PS_STR_3 (PLL_C_CNT_PHASE_PS_STR_3), + .PLL_C_CNT_DUTY_CYCLE_3 (PLL_C_CNT_DUTY_CYCLE_3), + .PLL_C_CNT_OUT_EN_3 (PLL_C_CNT_OUT_EN_3), + .PLL_C_CNT_HIGH_4 (PLL_C_CNT_HIGH_4), + .PLL_C_CNT_LOW_4 (PLL_C_CNT_LOW_4), + .PLL_C_CNT_PRST_4 (PLL_C_CNT_PRST_4), + .PLL_C_CNT_PH_MUX_PRST_4 (PLL_C_CNT_PH_MUX_PRST_4), + .PLL_C_CNT_BYPASS_EN_4 (PLL_C_CNT_BYPASS_EN_4), + .PLL_C_CNT_EVEN_DUTY_EN_4 (PLL_C_CNT_EVEN_DUTY_EN_4), + .PLL_C_CNT_FREQ_PS_STR_4 (PLL_C_CNT_FREQ_PS_STR_4), + .PLL_C_CNT_FREQ_MHZ_STR_4 (PLL_C_CNT_FREQ_MHZ_STR_4), + .PLL_C_CNT_PHASE_PS_STR_4 (PLL_C_CNT_PHASE_PS_STR_4), + .PLL_C_CNT_DUTY_CYCLE_4 (PLL_C_CNT_DUTY_CYCLE_4), + .PLL_C_CNT_OUT_EN_4 (PLL_C_CNT_OUT_EN_4), + .PLL_C_CNT_HIGH_5 (PLL_C_CNT_HIGH_5), + .PLL_C_CNT_LOW_5 (PLL_C_CNT_LOW_5), + .PLL_C_CNT_PRST_5 (PLL_C_CNT_PRST_5), + .PLL_C_CNT_PH_MUX_PRST_5 (PLL_C_CNT_PH_MUX_PRST_5), + .PLL_C_CNT_BYPASS_EN_5 (PLL_C_CNT_BYPASS_EN_5), + .PLL_C_CNT_EVEN_DUTY_EN_5 (PLL_C_CNT_EVEN_DUTY_EN_5), + .PLL_C_CNT_FREQ_PS_STR_5 (PLL_C_CNT_FREQ_PS_STR_5), + .PLL_C_CNT_FREQ_MHZ_STR_5 (PLL_C_CNT_FREQ_MHZ_STR_5), + .PLL_C_CNT_PHASE_PS_STR_5 (PLL_C_CNT_PHASE_PS_STR_5), + .PLL_C_CNT_DUTY_CYCLE_5 (PLL_C_CNT_DUTY_CYCLE_5), + .PLL_C_CNT_OUT_EN_5 (PLL_C_CNT_OUT_EN_5), + .PLL_C_CNT_HIGH_6 (PLL_C_CNT_HIGH_6), + .PLL_C_CNT_LOW_6 (PLL_C_CNT_LOW_6), + .PLL_C_CNT_PRST_6 (PLL_C_CNT_PRST_6), + .PLL_C_CNT_PH_MUX_PRST_6 (PLL_C_CNT_PH_MUX_PRST_6), + .PLL_C_CNT_BYPASS_EN_6 (PLL_C_CNT_BYPASS_EN_6), + .PLL_C_CNT_EVEN_DUTY_EN_6 (PLL_C_CNT_EVEN_DUTY_EN_6), + .PLL_C_CNT_FREQ_PS_STR_6 (PLL_C_CNT_FREQ_PS_STR_6), + .PLL_C_CNT_FREQ_MHZ_STR_6 (PLL_C_CNT_FREQ_MHZ_STR_6), + .PLL_C_CNT_PHASE_PS_STR_6 (PLL_C_CNT_PHASE_PS_STR_6), + .PLL_C_CNT_DUTY_CYCLE_6 (PLL_C_CNT_DUTY_CYCLE_6), + .PLL_C_CNT_OUT_EN_6 (PLL_C_CNT_OUT_EN_6), + .PLL_C_CNT_HIGH_7 (PLL_C_CNT_HIGH_7), + .PLL_C_CNT_LOW_7 (PLL_C_CNT_LOW_7), + .PLL_C_CNT_PRST_7 (PLL_C_CNT_PRST_7), + .PLL_C_CNT_PH_MUX_PRST_7 (PLL_C_CNT_PH_MUX_PRST_7), + .PLL_C_CNT_BYPASS_EN_7 (PLL_C_CNT_BYPASS_EN_7), + .PLL_C_CNT_EVEN_DUTY_EN_7 (PLL_C_CNT_EVEN_DUTY_EN_7), + .PLL_C_CNT_FREQ_PS_STR_7 (PLL_C_CNT_FREQ_PS_STR_7), + .PLL_C_CNT_FREQ_MHZ_STR_7 (PLL_C_CNT_FREQ_MHZ_STR_7), + .PLL_C_CNT_PHASE_PS_STR_7 (PLL_C_CNT_PHASE_PS_STR_7), + .PLL_C_CNT_DUTY_CYCLE_7 (PLL_C_CNT_DUTY_CYCLE_7), + .PLL_C_CNT_OUT_EN_7 (PLL_C_CNT_OUT_EN_7), + .PLL_C_CNT_HIGH_8 (PLL_C_CNT_HIGH_8), + .PLL_C_CNT_LOW_8 (PLL_C_CNT_LOW_8), + .PLL_C_CNT_PRST_8 (PLL_C_CNT_PRST_8), + .PLL_C_CNT_PH_MUX_PRST_8 (PLL_C_CNT_PH_MUX_PRST_8), + .PLL_C_CNT_BYPASS_EN_8 (PLL_C_CNT_BYPASS_EN_8), + .PLL_C_CNT_EVEN_DUTY_EN_8 (PLL_C_CNT_EVEN_DUTY_EN_8), + .PLL_C_CNT_FREQ_PS_STR_8 (PLL_C_CNT_FREQ_PS_STR_8), + .PLL_C_CNT_FREQ_MHZ_STR_8 (PLL_C_CNT_FREQ_MHZ_STR_8), + .PLL_C_CNT_PHASE_PS_STR_8 (PLL_C_CNT_PHASE_PS_STR_8), + .PLL_C_CNT_DUTY_CYCLE_8 (PLL_C_CNT_DUTY_CYCLE_8), + .PLL_C_CNT_OUT_EN_8 (PLL_C_CNT_OUT_EN_8), + .SEQ_USE_SIM_PARAMS ("off") + ) arch_inst ( + .local_reset_req (local_reset_req), + .local_reset_done (local_reset_done), + .pll_ref_clk (pll_ref_clk), + .pll_ref_clk_out (pll_ref_clk_out), + .pll_locked (pll_locked), + .pll_extra_clk_0 (pll_extra_clk_0), + .pll_extra_clk_1 (pll_extra_clk_1), + .pll_extra_clk_2 (pll_extra_clk_2), + .pll_extra_clk_3 (pll_extra_clk_3), + .ac_parity_err (ac_parity_err), + .oct_rzqin (oct_rzqin), + .mem_ck (mem_ck), + .mem_ck_n (mem_ck_n), + .mem_a (mem_a), + .mem_act_n (mem_act_n), + .mem_ba (mem_ba), + .mem_bg (mem_bg), + .mem_c (mem_c), + .mem_cke (mem_cke), + .mem_cs_n (mem_cs_n), + .mem_rm (mem_rm), + .mem_odt (mem_odt), + .mem_reset_n (mem_reset_n), + .mem_par (mem_par), + .mem_alert_n (mem_alert_n), + .mem_dqs (mem_dqs), + .mem_dqs_n (mem_dqs_n), + .mem_dq (mem_dq), + .mem_dbi_n (mem_dbi_n), + .mem_ck_bidir (mem_ck_bidir), + .mem_ck_bidir_n (mem_ck_bidir_n), + .mem_dk (mem_dk), + .mem_dk_n (mem_dk_n), + .mem_dka (mem_dka), + .mem_dka_n (mem_dka_n), + .mem_dkb (mem_dkb), + .mem_dkb_n (mem_dkb_n), + .mem_k (mem_k), + .mem_k_n (mem_k_n), + .mem_req_n (mem_req_n), + .mem_gnt_n (mem_gnt_n), + .mem_err_n (mem_err_n), + .mem_ras_n (mem_ras_n), + .mem_cas_n (mem_cas_n), + .mem_we_n (mem_we_n), + .mem_ca (mem_ca), + .mem_ref_n (mem_ref_n), + .mem_wps_n (mem_wps_n), + .mem_rps_n (mem_rps_n), + .mem_doff_n (mem_doff_n), + .mem_lda_n (mem_lda_n), + .mem_ldb_n (mem_ldb_n), + .mem_rwa_n (mem_rwa_n), + .mem_rwb_n (mem_rwb_n), + .mem_lbk0_n (mem_lbk0_n), + .mem_lbk1_n (mem_lbk1_n), + .mem_cfg_n (mem_cfg_n), + .mem_ap (mem_ap), + .mem_ainv (mem_ainv), + .mem_dm (mem_dm), + .mem_bws_n (mem_bws_n), + .mem_d (mem_d), + .mem_dqa (mem_dqa), + .mem_dqb (mem_dqb), + .mem_dinva (mem_dinva), + .mem_dinvb (mem_dinvb), + .mem_q (mem_q), + .mem_qk (mem_qk), + .mem_qk_n (mem_qk_n), + .mem_qka (mem_qka), + .mem_qka_n (mem_qka_n), + .mem_qkb (mem_qkb), + .mem_qkb_n (mem_qkb_n), + .mem_cq (mem_cq), + .mem_cq_n (mem_cq_n), + .mem_pe_n (mem_pe_n), + .local_cal_success (local_cal_success), + .local_cal_fail (local_cal_fail), + .afi_reset_n (afi_reset_n), + .afi_clk (afi_clk), + .afi_half_clk (afi_half_clk), + .emif_usr_reset_n (emif_usr_reset_n), + .emif_usr_clk (emif_usr_clk), + .emif_usr_half_clk (emif_usr_half_clk), + .emif_usr_reset_n_sec (emif_usr_reset_n_sec), + .emif_usr_clk_sec (emif_usr_clk_sec), + .emif_usr_half_clk_sec (emif_usr_half_clk_sec), + .clks_sharing_master_out (clks_sharing_master_out), + .clks_sharing_slave_in (clks_sharing_slave_in), + .clks_sharing_slave_out (clks_sharing_slave_out), + .afi_cal_success (afi_cal_success), + .afi_cal_fail (afi_cal_fail), + .afi_cal_req (afi_cal_req), + .afi_rlat (afi_rlat), + .afi_wlat (afi_wlat), + .afi_seq_busy (afi_seq_busy), + .afi_ctl_refresh_done (afi_ctl_refresh_done), + .afi_ctl_long_idle (afi_ctl_long_idle), + .afi_mps_req (afi_mps_req), + .afi_mps_ack (afi_mps_ack), + .afi_addr (afi_addr), + .afi_ba (afi_ba), + .afi_bg (afi_bg), + .afi_c (afi_c), + .afi_cke (afi_cke), + .afi_cs_n (afi_cs_n), + .afi_rm (afi_rm), + .afi_odt (afi_odt), + .afi_ras_n (afi_ras_n), + .afi_cas_n (afi_cas_n), + .afi_we_n (afi_we_n), + .afi_rst_n (afi_rst_n), + .afi_act_n (afi_act_n), + .afi_req_n (afi_req_n), + .afi_gnt_n (afi_gnt_n), + .afi_err_n (afi_err_n), + .afi_par (afi_par), + .afi_ca (afi_ca), + .afi_ref_n (afi_ref_n), + .afi_wps_n (afi_wps_n), + .afi_rps_n (afi_rps_n), + .afi_doff_n (afi_doff_n), + .afi_ld_n (afi_ld_n), + .afi_rw_n (afi_rw_n), + .afi_lbk0_n (afi_lbk0_n), + .afi_lbk1_n (afi_lbk1_n), + .afi_cfg_n (afi_cfg_n), + .afi_ap (afi_ap), + .afi_ainv (afi_ainv), + .afi_dm (afi_dm), + .afi_dm_n (afi_dm_n), + .afi_bws_n (afi_bws_n), + .afi_rdata_dbi_n (afi_rdata_dbi_n), + .afi_wdata_dbi_n (afi_wdata_dbi_n), + .afi_rdata_dinv (afi_rdata_dinv), + .afi_wdata_dinv (afi_wdata_dinv), + .afi_dqs_burst (afi_dqs_burst), + .afi_wdata_valid (afi_wdata_valid), + .afi_wdata (afi_wdata), + .afi_rdata_en_full (afi_rdata_en_full), + .afi_rdata (afi_rdata), + .afi_rdata_valid (afi_rdata_valid), + .afi_rrank (afi_rrank), + .afi_wrank (afi_wrank), + .afi_alert_n (afi_alert_n), + .afi_pe_n (afi_pe_n), + .ast_cmd_valid_0 (ast_cmd_valid_0), + .ast_cmd_ready_0 (ast_cmd_ready_0), + .ast_cmd_data_0 (ast_cmd_data_0), + .ast_cmd_valid_1 (ast_cmd_valid_1), + .ast_cmd_ready_1 (ast_cmd_ready_1), + .ast_cmd_data_1 (ast_cmd_data_1), + .ast_wr_valid_0 (ast_wr_valid_0), + .ast_wr_ready_0 (ast_wr_ready_0), + .ast_wr_data_0 (ast_wr_data_0), + .ast_wr_valid_1 (ast_wr_valid_1), + .ast_wr_ready_1 (ast_wr_ready_1), + .ast_wr_data_1 (ast_wr_data_1), + .ast_rd_valid_0 (ast_rd_valid_0), + .ast_rd_ready_0 (ast_rd_ready_0), + .ast_rd_data_0 (ast_rd_data_0), + .ast_rd_valid_1 (ast_rd_valid_1), + .ast_rd_ready_1 (ast_rd_ready_1), + .ast_rd_data_1 (ast_rd_data_1), + .amm_ready_0 (amm_ready_0), + .amm_read_0 (amm_read_0), + .amm_write_0 (amm_write_0), + .amm_address_0 (amm_address_0), + .amm_readdata_0 (amm_readdata_0), + .amm_writedata_0 (amm_writedata_0), + .amm_burstcount_0 (amm_burstcount_0), + .amm_byteenable_0 (amm_byteenable_0), + .amm_beginbursttransfer_0 (amm_beginbursttransfer_0), + .amm_readdatavalid_0 (amm_readdatavalid_0), + .amm_ready_1 (amm_ready_1), + .amm_read_1 (amm_read_1), + .amm_write_1 (amm_write_1), + .amm_address_1 (amm_address_1), + .amm_readdata_1 (amm_readdata_1), + .amm_writedata_1 (amm_writedata_1), + .amm_burstcount_1 (amm_burstcount_1), + .amm_byteenable_1 (amm_byteenable_1), + .amm_beginbursttransfer_1 (amm_beginbursttransfer_1), + .amm_readdatavalid_1 (amm_readdatavalid_1), + .amm_early_ready_0 (amm_early_ready_0), + .amm_early_ready_1 (amm_early_ready_1), + .amm_rd_type_0 (amm_rd_type_0), + .amm_rd_type_1 (amm_rd_type_1), + .phylite_strobe (phylite_strobe), + .phylite_strobe_oe (phylite_strobe_oe), + .phylite_data_oe (phylite_data_oe), + .phylite_data_from_core (phylite_data_from_core), + .phylite_data_to_core (phylite_data_to_core), + .phylite_rdata_valid (phylite_rdata_valid), + .phylite_interface_locked (phylite_interface_locked), + .phylite_rdata_en (phylite_rdata_en), + .ctrl_user_priority_hi_0 (ctrl_user_priority_hi_0), + .ctrl_user_priority_hi_1 (ctrl_user_priority_hi_1), + .ctrl_auto_precharge_req_0 (ctrl_auto_precharge_req_0), + .ctrl_auto_precharge_req_1 (ctrl_auto_precharge_req_1), + .ctrl_user_refresh_req (ctrl_user_refresh_req), + .ctrl_user_refresh_bank (ctrl_user_refresh_bank), + .ctrl_user_refresh_ack (ctrl_user_refresh_ack), + .ctrl_self_refresh_req (ctrl_self_refresh_req), + .ctrl_self_refresh_ack (ctrl_self_refresh_ack), + .ctrl_will_refresh (ctrl_will_refresh), + .ctrl_deep_power_down_req (ctrl_deep_power_down_req), + .ctrl_deep_power_down_ack (ctrl_deep_power_down_ack), + .ctrl_power_down_ack (ctrl_power_down_ack), + .ctrl_zq_cal_long_req (ctrl_zq_cal_long_req), + .ctrl_zq_cal_short_req (ctrl_zq_cal_short_req), + .ctrl_zq_cal_ack (ctrl_zq_cal_ack), + .ctrl_ecc_write_info_0 (ctrl_ecc_write_info_0), + .ctrl_ecc_rdata_id_0 (ctrl_ecc_rdata_id_0), + .ctrl_ecc_read_info_0 (ctrl_ecc_read_info_0), + .ctrl_ecc_cmd_info_0 (ctrl_ecc_cmd_info_0), + .ctrl_ecc_idle_0 (ctrl_ecc_idle_0), + .ctrl_ecc_wr_pointer_info_0 (ctrl_ecc_wr_pointer_info_0), + .ctrl_ecc_write_info_1 (ctrl_ecc_write_info_1), + .ctrl_ecc_rdata_id_1 (ctrl_ecc_rdata_id_1), + .ctrl_ecc_read_info_1 (ctrl_ecc_read_info_1), + .ctrl_ecc_cmd_info_1 (ctrl_ecc_cmd_info_1), + .ctrl_ecc_idle_1 (ctrl_ecc_idle_1), + .ctrl_ecc_wr_pointer_info_1 (ctrl_ecc_wr_pointer_info_1), + .mmr_slave_waitrequest_0 (mmr_slave_waitrequest_0), + .mmr_slave_read_0 (mmr_slave_read_0), + .mmr_slave_write_0 (mmr_slave_write_0), + .mmr_slave_address_0 (mmr_slave_address_0), + .mmr_slave_readdata_0 (mmr_slave_readdata_0), + .mmr_slave_writedata_0 (mmr_slave_writedata_0), + .mmr_slave_burstcount_0 (mmr_slave_burstcount_0), + .mmr_slave_beginbursttransfer_0 (mmr_slave_beginbursttransfer_0), + .mmr_slave_readdatavalid_0 (mmr_slave_readdatavalid_0), + .mmr_slave_waitrequest_1 (mmr_slave_waitrequest_1), + .mmr_slave_read_1 (mmr_slave_read_1), + .mmr_slave_write_1 (mmr_slave_write_1), + .mmr_slave_address_1 (mmr_slave_address_1), + .mmr_slave_readdata_1 (mmr_slave_readdata_1), + .mmr_slave_writedata_1 (mmr_slave_writedata_1), + .mmr_slave_burstcount_1 (mmr_slave_burstcount_1), + .mmr_slave_beginbursttransfer_1 (mmr_slave_beginbursttransfer_1), + .mmr_slave_readdatavalid_1 (mmr_slave_readdatavalid_1), + .hps_to_emif (hps_to_emif), + .emif_to_hps (emif_to_hps), + .hps_to_emif_gp (hps_to_emif_gp), + .emif_to_hps_gp (emif_to_hps_gp), + .pa_dprio_clk (pa_dprio_clk), + .pa_dprio_read (pa_dprio_read), + .pa_dprio_reg_addr (pa_dprio_reg_addr), + .pa_dprio_rst_n (pa_dprio_rst_n), + .pa_dprio_write (pa_dprio_write), + .pa_dprio_writedata (pa_dprio_writedata), + .pa_dprio_block_select (pa_dprio_block_select), + .pa_dprio_readdata (pa_dprio_readdata), + .pll_phase_en (pll_phase_en), + .pll_up_dn (pll_up_dn), + .pll_cnt_sel (pll_cnt_sel), + .pll_num_phase_shifts (pll_num_phase_shifts), + .pll_phase_done (pll_phase_done), + .pll_core_refclk (pll_core_refclk), + .dft_core_clk_buf_out (dft_core_clk_buf_out), + .dft_core_clk_locked (dft_core_clk_locked), + .calbus_read (calbus_read), + .calbus_write (calbus_write), + .calbus_address (calbus_address), + .calbus_wdata (calbus_wdata), + .calbus_rdata (calbus_rdata), + .calbus_seq_param_tbl (calbus_seq_param_tbl), + .calbus_clk (calbus_clk) + ); +endmodule diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.dat b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.dat new file mode 100644 index 0000000000..07691f07c1 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.dat @@ -0,0 +1,438 @@ +********************************************************************* +* +* THIS IS AN AUTO-GENERATED FILE! +* ------------------------------- +* If you modify this files, all your changes will be lost if you +* regenerate the core! +* +* FILE DESCRIPTION +* ---------------- +* This file specifies the properties of the memory device and +* of the memory interface + + +* Auto-generated contents start below... +.param emif_corename=str('ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy') + +.param PROTOCOL = str('DDR4') +.param NUM_RANKS = 1 +.param SLEW_RATE_DRAM = 4.0 +.param SLEW_RATE_DRAM_CLOCK = 4.0 +.param VIN_Ms = 0.13 +.param VIN_Mh = 0.065 +.param SLEW_RATE_PHY = 2.0 +.param SLEW_RATE_PHY_CLOCK = 2.0 +.param SLEW_RATE_CA = 2.0 +.param SLEW_RATE_CLOCK = 4.0 +.param UI = 0.833 +.param tCK = 0.75 +.param tDQSQ = 0.052500000000000005 +.param tQH = 0.43 +.param tDS = 0.04166666666666667 +.param tDH = 0.04166666666666667 +.param tIS = 0.062 +.param tIH = 0.087 +.param tDQSCK = 0.175 +.param tDQSS = 0.27 +.param tWLS = 0.108 +.param tWLH = 0.108 +.param tDSS = 0.04166666666666667 +.param tDSH = 0.04166666666666667 +.param BD_PKG_SKEW = 0.02 +.param CA_BD_PKG_SKEW = 0.18 +.param CA_TO_CK_BD_PKG_SKEW = 0.0 +.param DQS_BOARD_SKEW = 0.02 +.param DQS_TO_CK_BOARD_SKEW = 0.02 +.param RD_ISI = 0.12 +.param WR_ISI = 0.13 +.param CA_ISI = 0.15 +.param DQSG_ISI = 0.15 +.param WL_ISI = 0.06 +.param X4 = 0 +.param RDBI = 1 +.param WDBI = 0 +.param MEM_VCC = 1.2 +.param MEM_AC_FREQ_PS = 833.3333333333334 +.param MEM_DQ_FREQ_PS = 833.3333333333334 +.param MEMCLK_IBIS = str('dsstl12_io_s2r40c_doff') +.param MEMCLK_COMP_IBIS = str('CLKIN') +.param MEMCLK_DIFF_SE = str('true') +.param MEMCLK_PHASE = 90 +.param MEMAC_IBIS = str('sstl12_io_s2r40c_doff') +.param MEMAC_COMP_IBIS = str('INPUT') +.param MEMAC_RANKS = 1 +.param MEMAC_COMPS_PER_RANK = 8 +.param MEM_DQ_RANKS = 1 +.param FPGA_DQ_WR_IBIS = str('pod12_io_s2r40c_dh') +.param FPGA_DBI_WR_IBIS = str('pod12_io_s2r40c_dh') +.param FPGA_DQS_WR_IBIS = str('dpod12_io_s2r40c_dh') +.param FPGA_DQS_WR_PHASE = 90 +.param WR_MEM_T0_R0_DQ_IBIS = str('DQ_IN_ODT60_3200') +.param WR_MEM_T0_R1_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R2_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R3_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R0_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R1_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R2_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R3_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R0_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R1_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R2_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R3_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R0_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R1_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R2_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R3_DQ_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R0_DQS_IBIS = str('DQS_IN_ODT60_3200') +.param WR_MEM_T0_R1_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R2_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R3_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R0_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R1_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R2_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R3_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R0_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R1_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R2_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R3_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R0_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R1_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R2_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R3_DQS_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R0_DBI_IBIS = str('DM_ODT60_3200') +.param WR_MEM_T0_R1_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R2_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T0_R3_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R0_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R1_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R2_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T1_R3_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R0_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R1_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R2_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T2_R3_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R0_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R1_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R2_DBI_IBIS = str('NF_INPUT') +.param WR_MEM_T3_R3_DBI_IBIS = str('NF_INPUT') +.param FPGA_DQ_RD_IBIS = str('pod12_in_g60c') +.param FPGA_DBI_RD_IBIS = str('pod12_in_g60c') +.param FPGA_DQS_RD_IBIS = str('dpod12_in_g60c') +.param FPGA_DQS_RD_PHASE = 0 +.param RD_MEM_T0_R0_DQ_IBIS = str('DQ_34_3200') +.param RD_MEM_T0_R1_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R2_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R3_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R0_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R1_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R2_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R3_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R0_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R1_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R2_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R3_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R0_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R1_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R2_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R3_DQ_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R0_DQS_IBIS = str('DQS_34_3200') +.param RD_MEM_T0_R1_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R2_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R3_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R0_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R1_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R2_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R3_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R0_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R1_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R2_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R3_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R0_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R1_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R2_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R3_DQS_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R0_DBI_IBIS = str('DQ_34_3200') +.param RD_MEM_T0_R1_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R2_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T0_R3_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R0_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R1_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R2_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T1_R3_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R0_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R1_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R2_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T2_R3_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R0_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R1_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R2_DBI_IBIS = str('NF_INPUT') +.param RD_MEM_T3_R3_DBI_IBIS = str('NF_INPUT') +.param AC_MASK_P1X = 0.16899999999999998 +.param AC_MASK_P1Y = 0.51 +.param AC_MASK_P2X = 0.16899999999999998 +.param AC_MASK_P2Y = 0.6 +.param AC_MASK_P3X = 0.16899999999999998 +.param AC_MASK_P3Y = 0.69 +.param AC_MASK_P4X = 0.831 +.param AC_MASK_P4Y = 0.69 +.param AC_MASK_P5X = 0.831 +.param AC_MASK_P5Y = 0.6 +.param AC_MASK_P6X = 0.831 +.param AC_MASK_P6Y = 0.51 +.param DQ_WR_MASK_P1X = 0.1795 +.param DQ_WR_MASK_P1Y = 0.775 +.param DQ_WR_MASK_P2X = 0.1795 +.param DQ_WR_MASK_P2Y = 0.875 +.param DQ_WR_MASK_P3X = 0.1795 +.param DQ_WR_MASK_P3Y = 0.975 +.param DQ_WR_MASK_P4X = 0.8205 +.param DQ_WR_MASK_P4Y = 0.975 +.param DQ_WR_MASK_P5X = 0.8205 +.param DQ_WR_MASK_P5Y = 0.875 +.param DQ_WR_MASK_P6X = 0.8205 +.param DQ_WR_MASK_P6Y = 0.775 +.param DQ_RD_MASK_P1X = 0.19199999999999995 +.param DQ_RD_MASK_P1Y = 0.885 +.param DQ_RD_MASK_P2X = 0.19199999999999995 +.param DQ_RD_MASK_P2Y = 0.985 +.param DQ_RD_MASK_P3X = 0.19199999999999995 +.param DQ_RD_MASK_P3Y = 1.085 +.param DQ_RD_MASK_P4X = 0.808 +.param DQ_RD_MASK_P4Y = 1.085 +.param DQ_RD_MASK_P5X = 0.808 +.param DQ_RD_MASK_P5Y = 0.985 +.param DQ_RD_MASK_P6X = 0.808 +.param DQ_RD_MASK_P6Y = 0.885 +.param AC_F_P0_BUFTYPE = 0 +.param AC_F_P0_DATATYPE = 0 +.param AC_F_P0_DATAPHASE = 0 +.param AC_F_P0_IBISTYPE = 4 +.param AC_F_P1_BUFTYPE = 0 +.param AC_F_P1_DATATYPE = 0 +.param AC_F_P1_DATAPHASE = 0 +.param AC_F_P1_IBISTYPE = 4 +.param AC_F_P2_BUFTYPE = 0 +.param AC_F_P2_DATATYPE = 0 +.param AC_F_P2_DATAPHASE = 0 +.param AC_F_P2_IBISTYPE = 4 +.param AC_F_P3_BUFTYPE = 0 +.param AC_F_P3_DATATYPE = 0 +.param AC_F_P3_DATAPHASE = 0 +.param AC_F_P3_IBISTYPE = 4 +.param AC_F_P4_BUFTYPE = 0 +.param AC_F_P4_DATATYPE = 0 +.param AC_F_P4_DATAPHASE = 0 +.param AC_F_P4_IBISTYPE = 4 +.param AC_F_P5_BUFTYPE = 0 +.param AC_F_P5_DATATYPE = 2 +.param AC_F_P5_DATAPHASE = 0 +.param AC_F_P5_IBISTYPE = 4 +.param AC_F_P6_BUFTYPE = 0 +.param AC_F_P6_DATATYPE = 0 +.param AC_F_P6_DATAPHASE = 0 +.param AC_F_P6_IBISTYPE = 4 +.param AC_F_P7_BUFTYPE = 0 +.param AC_F_P7_DATATYPE = 0 +.param AC_F_P7_DATAPHASE = 0 +.param AC_F_P7_IBISTYPE = 4 +.param AC_F_P8_BUFTYPE = 1 +.param AC_F_P8_DATATYPE = 4 +.param AC_F_P8_DATAPHASE = 270 +.param AC_F_P8_IBISTYPE = 4 +.param AC_F_P9_BUFTYPE = 1 +.param AC_F_P9_DATATYPE = 4 +.param AC_F_P9_DATAPHASE = 90 +.param AC_F_P9_IBISTYPE = 4 +.param AC_F_P10_BUFTYPE = 0 +.param AC_F_P10_DATATYPE = 0 +.param AC_F_P10_DATAPHASE = 0 +.param AC_F_P10_IBISTYPE = 4 +.param AC_F_P11_BUFTYPE = 0 +.param AC_F_P11_DATATYPE = 0 +.param AC_F_P11_DATAPHASE = 0 +.param AC_F_P11_IBISTYPE = 4 +.param AC_M_P0_BUFTYPE = 0 +.param AC_M_P0_IBISTYPE = 1 +.param AC_M_P1_BUFTYPE = 0 +.param AC_M_P1_IBISTYPE = 1 +.param AC_M_P2_BUFTYPE = 0 +.param AC_M_P2_IBISTYPE = 1 +.param AC_M_P3_BUFTYPE = 0 +.param AC_M_P3_IBISTYPE = 1 +.param AC_M_P4_BUFTYPE = 0 +.param AC_M_P4_IBISTYPE = 1 +.param AC_M_P5_BUFTYPE = 0 +.param AC_M_P5_IBISTYPE = 1 +.param AC_M_P6_BUFTYPE = 0 +.param AC_M_P6_IBISTYPE = 1 +.param AC_M_P7_BUFTYPE = 0 +.param AC_M_P7_IBISTYPE = 1 +.param AC_M_P8_BUFTYPE = 1 +.param AC_M_P8_IBISTYPE = 1 +.param AC_M_P9_BUFTYPE = 1 +.param AC_M_P9_IBISTYPE = 1 +.param AC_M_P10_BUFTYPE = 0 +.param AC_M_P10_IBISTYPE = 1 +.param AC_M_P11_BUFTYPE = 0 +.param AC_M_P11_IBISTYPE = 1 +.param DQ_WR_F_P0_BUFTYPE = 0 +.param DQ_WR_F_P0_DATATYPE = 1 +.param DQ_WR_F_P0_DATAPHASE = 0 +.param DQ_WR_F_P0_IBISTYPE = 4 +.param DQ_WR_F_P1_BUFTYPE = 0 +.param DQ_WR_F_P1_DATATYPE = 1 +.param DQ_WR_F_P1_DATAPHASE = 0 +.param DQ_WR_F_P1_IBISTYPE = 4 +.param DQ_WR_F_P2_BUFTYPE = 0 +.param DQ_WR_F_P2_DATATYPE = 3 +.param DQ_WR_F_P2_DATAPHASE = 0 +.param DQ_WR_F_P2_IBISTYPE = 4 +.param DQ_WR_F_P3_BUFTYPE = 0 +.param DQ_WR_F_P3_DATATYPE = 1 +.param DQ_WR_F_P3_DATAPHASE = 0 +.param DQ_WR_F_P3_IBISTYPE = 4 +.param DQ_WR_F_P4_BUFTYPE = 1 +.param DQ_WR_F_P4_DATATYPE = 4 +.param DQ_WR_F_P4_DATAPHASE = 270 +.param DQ_WR_F_P4_IBISTYPE = 4 +.param DQ_WR_F_P5_BUFTYPE = 1 +.param DQ_WR_F_P5_DATATYPE = 4 +.param DQ_WR_F_P5_DATAPHASE = 90 +.param DQ_WR_F_P5_IBISTYPE = 4 +.param DQ_WR_F_P6_BUFTYPE = 0 +.param DQ_WR_F_P6_DATATYPE = 1 +.param DQ_WR_F_P6_DATAPHASE = 0 +.param DQ_WR_F_P6_IBISTYPE = 4 +.param DQ_WR_F_P7_BUFTYPE = 0 +.param DQ_WR_F_P7_DATATYPE = 5 +.param DQ_WR_F_P7_DATAPHASE = 0 +.param DQ_WR_F_P7_IBISTYPE = 4 +.param DQ_WR_F_P8_BUFTYPE = 0 +.param DQ_WR_F_P8_DATATYPE = 1 +.param DQ_WR_F_P8_DATAPHASE = 0 +.param DQ_WR_F_P8_IBISTYPE = 4 +.param DQ_WR_F_P9_BUFTYPE = 0 +.param DQ_WR_F_P9_DATATYPE = 1 +.param DQ_WR_F_P9_DATAPHASE = 0 +.param DQ_WR_F_P9_IBISTYPE = 4 +.param DQ_WR_F_P10_BUFTYPE = 0 +.param DQ_WR_F_P10_DATATYPE = 1 +.param DQ_WR_F_P10_DATAPHASE = 0 +.param DQ_WR_F_P10_IBISTYPE = 4 +.param DQ_WR_F_P11_BUFTYPE = 0 +.param DQ_WR_F_P11_DATATYPE = 1 +.param DQ_WR_F_P11_DATAPHASE = 0 +.param DQ_WR_F_P11_IBISTYPE = 4 +.param DQ_WR_M_P0_BUFTYPE = 0 +.param DQ_WR_M_P0_IBISTYPE = 1 +.param DQ_WR_M_P1_BUFTYPE = 0 +.param DQ_WR_M_P1_IBISTYPE = 1 +.param DQ_WR_M_P2_BUFTYPE = 0 +.param DQ_WR_M_P2_IBISTYPE = 1 +.param DQ_WR_M_P3_BUFTYPE = 0 +.param DQ_WR_M_P3_IBISTYPE = 1 +.param DQ_WR_M_P4_BUFTYPE = 1 +.param DQ_WR_M_P4_IBISTYPE = 1 +.param DQ_WR_M_P5_BUFTYPE = 1 +.param DQ_WR_M_P5_IBISTYPE = 1 +.param DQ_WR_M_P6_BUFTYPE = 2 +.param DQ_WR_M_P6_IBISTYPE = 1 +.param DQ_WR_M_P7_BUFTYPE = 999 +.param DQ_WR_M_P7_IBISTYPE = 1 +.param DQ_WR_M_P8_BUFTYPE = 0 +.param DQ_WR_M_P8_IBISTYPE = 1 +.param DQ_WR_M_P9_BUFTYPE = 0 +.param DQ_WR_M_P9_IBISTYPE = 1 +.param DQ_WR_M_P10_BUFTYPE = 0 +.param DQ_WR_M_P10_IBISTYPE = 1 +.param DQ_WR_M_P11_BUFTYPE = 0 +.param DQ_WR_M_P11_IBISTYPE = 1 +.param DQ_RD_M_P0_BUFTYPE = 0 +.param DQ_RD_M_P0_DATATYPE = 1 +.param DQ_RD_M_P0_DATAPHASE = 0 +.param DQ_RD_M_P0_IBISTYPE = 3 +.param DQ_RD_M_P1_BUFTYPE = 0 +.param DQ_RD_M_P1_DATATYPE = 1 +.param DQ_RD_M_P1_DATAPHASE = 0 +.param DQ_RD_M_P1_IBISTYPE = 3 +.param DQ_RD_M_P2_BUFTYPE = 0 +.param DQ_RD_M_P2_DATATYPE = 3 +.param DQ_RD_M_P2_DATAPHASE = 0 +.param DQ_RD_M_P2_IBISTYPE = 3 +.param DQ_RD_M_P3_BUFTYPE = 0 +.param DQ_RD_M_P3_DATATYPE = 1 +.param DQ_RD_M_P3_DATAPHASE = 0 +.param DQ_RD_M_P3_IBISTYPE = 3 +.param DQ_RD_M_P4_BUFTYPE = 1 +.param DQ_RD_M_P4_DATATYPE = 4 +.param DQ_RD_M_P4_DATAPHASE = 0 +.param DQ_RD_M_P4_IBISTYPE = 3 +.param DQ_RD_M_P5_BUFTYPE = 1 +.param DQ_RD_M_P5_DATATYPE = 4 +.param DQ_RD_M_P5_DATAPHASE = 180 +.param DQ_RD_M_P5_IBISTYPE = 3 +.param DQ_RD_M_P6_BUFTYPE = 999 +.param DQ_RD_M_P6_DATATYPE = 5 +.param DQ_RD_M_P6_DATAPHASE = 0 +.param DQ_RD_M_P6_IBISTYPE = 3 +.param DQ_RD_M_P7_BUFTYPE = 999 +.param DQ_RD_M_P7_DATATYPE = 5 +.param DQ_RD_M_P7_DATAPHASE = 0 +.param DQ_RD_M_P7_IBISTYPE = 3 +.param DQ_RD_M_P8_BUFTYPE = 0 +.param DQ_RD_M_P8_DATATYPE = 1 +.param DQ_RD_M_P8_DATAPHASE = 0 +.param DQ_RD_M_P8_IBISTYPE = 3 +.param DQ_RD_M_P9_BUFTYPE = 0 +.param DQ_RD_M_P9_DATATYPE = 1 +.param DQ_RD_M_P9_DATAPHASE = 0 +.param DQ_RD_M_P9_IBISTYPE = 3 +.param DQ_RD_M_P10_BUFTYPE = 0 +.param DQ_RD_M_P10_DATATYPE = 1 +.param DQ_RD_M_P10_DATAPHASE = 0 +.param DQ_RD_M_P10_IBISTYPE = 3 +.param DQ_RD_M_P11_BUFTYPE = 0 +.param DQ_RD_M_P11_DATATYPE = 1 +.param DQ_RD_M_P11_DATAPHASE = 0 +.param DQ_RD_M_P11_IBISTYPE = 3 +.param DQ_RD_F_P0_BUFTYPE = 0 +.param DQ_RD_F_P0_IBISTYPE = 1 +.param DQ_RD_F_P1_BUFTYPE = 0 +.param DQ_RD_F_P1_IBISTYPE = 1 +.param DQ_RD_F_P2_BUFTYPE = 0 +.param DQ_RD_F_P2_IBISTYPE = 1 +.param DQ_RD_F_P3_BUFTYPE = 0 +.param DQ_RD_F_P3_IBISTYPE = 1 +.param DQ_RD_F_P4_BUFTYPE = 1 +.param DQ_RD_F_P4_IBISTYPE = 1 +.param DQ_RD_F_P5_BUFTYPE = 1 +.param DQ_RD_F_P5_IBISTYPE = 1 +.param DQ_RD_F_P6_BUFTYPE = 999 +.param DQ_RD_F_P6_IBISTYPE = 1 +.param DQ_RD_F_P7_BUFTYPE = 999 +.param DQ_RD_F_P7_IBISTYPE = 1 +.param DQ_RD_F_P8_BUFTYPE = 0 +.param DQ_RD_F_P8_IBISTYPE = 1 +.param DQ_RD_F_P9_BUFTYPE = 0 +.param DQ_RD_F_P9_IBISTYPE = 1 +.param DQ_RD_F_P10_BUFTYPE = 0 +.param DQ_RD_F_P10_IBISTYPE = 1 +.param DQ_RD_F_P11_BUFTYPE = 0 +.param DQ_RD_F_P11_IBISTYPE = 1 +.param IBIS_MODEL_DIRECTORY = str('""') +.param FPGA_IBIS_MODEL_FILE = str('""') +.param MEM_IBIS_MODEL_FILE = str('""') +.param USE_AC_PCB_EXTRACTION = 0 +.param AC_PCB_EXTRACTION_FILE = str('"null"') +.param USE_DQ_PCB_EXTRACTION = 0 +.param DQ_PCB_EXTRACTION_FILE = str('"null"') +.param USE_AC_MULTIRANK_CONNECTOR_EXTRACTION = 0 +.param AC_MULTIRANK_CONNECTOR_EXTRACTION_FILE = str('"null"') +.param USE_DQ_MULTIRANK_CONNECTOR_EXTRACTION = 0 +.param DQ_MULTIRANK_CONNECTOR_EXTRACTION_FILE = str('"null"') +.param USE_AC_FLYBY_EXTRACTION = 0 +.param AC_FLYBY_EXTRACTION_FILE = str('"null"') + +.param MEM_FORMAT_ENUM = str('MEM_FORMAT_RDIMM') +.param MEM_DATA_MASK_EN = str('true') + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl new file mode 100644 index 0000000000..bb83e85ae1 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl @@ -0,0 +1,375 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file specifies the timing properties of the memory device and +# of the memory interface + +package require ::quartus::clock_uncertainty + + +set ::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy + +set var(PROTOCOL) DDR4 +set var(NUM_RANKS) 1 +set var(SLEW_RATE_DRAM) 4.0 +set var(SLEW_RATE_DRAM_CLOCK) 8.0 +set var(VIN_Ms) 0.13 +set var(VIN_Mh) 0.065 +set var(SLEW_RATE_PHY) 2.0 +set var(SLEW_RATE_PHY_CLOCK) 4.0 +set var(SLEW_RATE_CA) 2.0 +set var(SLEW_RATE_CLOCK) 4.0 +set var(UI) 0.833 +set var(tCK) 0.75 +set var(tDQSQ) 0.052500000000000005 +set var(tQH) 0.43 +set var(tDS) 0.04166666666666667 +set var(tDH) 0.04166666666666667 +set var(tIS) 0.062 +set var(tIH) 0.087 +set var(tDQSCK) 0.175 +set var(tDQSS) 0.27 +set var(tWLS) 0.108 +set var(tWLH) 0.108 +set var(tDSS) 0.18 +set var(tDSH) 0.18 +set var(BD_PKG_SKEW) 0.02 +set var(CA_BD_PKG_SKEW) 0.18 +set var(CA_TO_CK_BD_PKG_SKEW) 0.0 +set var(DQS_BOARD_SKEW) 0.02 +set var(DQS_TO_CK_BOARD_SKEW) 0.02 +set var(RD_ISI) 0.12 +set var(WR_ISI) 0.13 +set var(CA_ISI) 0.15 +set var(DQSG_ISI) 0.15 +set var(WL_ISI) 0.06 +set var(X4) 0 +set var(IS_DLL_ON) 1 +set var(OCT_RECAL) 1 +set var(RDBI) 1 +set var(WDBI) 1 +set var(CUT_C2P_P2C_PATHS) 0 +set var(CA_DESKEW) 1 + +set var(PHY_TARGET_SPEEDGRADE) E2V +set var(PHY_TARGET_IS_ES) false +set var(PHY_TARGET_IS_ES2) false +set var(PHY_TARGET_IS_ES3) true +set var(PHY_TARGET_IS_PRODUCTION) false +set var(PHY_CORE_CLKS_SHARING_ENUM) CORE_CLKS_SHARING_DISABLED +set var(PHY_CONFIG_ENUM) CONFIG_PHY_AND_HARD_CTRL +set var(PHY_PING_PONG_EN) false +set var(IS_HPS) false +set var(PHY_MEM_CLK_FREQ_MHZ) 1200.0 +set var(PHY_REF_CLK_FREQ_MHZ) 33.333 +set var(PHY_REF_CLK_JITTER_PS) 10.0 +set var(PLL_REF_CLK_FREQ_PS_STR) "30024 ps" +set var(PLL_VCO_FREQ_PS_STR) "834 ps" +set var(PLL_VCO_TO_MEM_CLK_FREQ_RATIO) 1 +set var(PLL_PHY_CLK_VCO_PHASE) 0 +set var(USER_CLK_RATIO) 4 +set var(C2P_P2C_CLK_RATIO) 4 +set var(PHY_HMC_CLK_RATIO) 2 +set var(MEM_FORMAT_ENUM) MEM_FORMAT_RDIMM +set var(MEM_DATA_MASK_EN) true +set var(DIAG_TIMING_REGTEST_MODE) false +set var(DIAG_CPA_OUT_1_EN) false +set var(DIAG_USE_CPA_LOCK) true +set var(PHY_USERMODE_OCT) false +set var(AMM_C2P_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(AMM_P2C_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(MMR_C2P_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(MMR_P2C_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(SIDEBAND_C2P_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(SIDEBAND_P2C_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(SEQ_C2P_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(SEQ_P2C_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(ECC_C2P_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(ECC_P2C_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(LANE_C2P_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(LANE_P2C_UFI_MODE) pin_ufi_use_in_direct_out_direct +set var(PLL_NUM_OF_EXTRA_CLKS) 0 +set var(PLL_C_CNT_LOW_3) 1 +set var(PLL_C_CNT_HIGH_3) 1 +set var(PLL_C_CNT_BYPASS_EN_3) false +set var(PLL_C_CNT_PHASE_PS_STR_3) "0 ps" +set var(PLL_C_CNT_DUTY_CYCLE_3) 50 +set var(PLL_C_CNT_LOW_4) 2 +set var(PLL_C_CNT_HIGH_4) 2 +set var(PLL_C_CNT_BYPASS_EN_4) false +set var(PLL_C_CNT_PHASE_PS_STR_4) "0 ps" +set var(PLL_C_CNT_DUTY_CYCLE_4) 50 +set var(PLL_C_CNT_LOW_5) 256 +set var(PLL_C_CNT_HIGH_5) 256 +set var(PLL_C_CNT_BYPASS_EN_5) true +set var(PLL_C_CNT_PHASE_PS_STR_5) "0 ps" +set var(PLL_C_CNT_DUTY_CYCLE_5) 50 +set var(PLL_C_CNT_LOW_6) 256 +set var(PLL_C_CNT_HIGH_6) 256 +set var(PLL_C_CNT_BYPASS_EN_6) true +set var(PLL_C_CNT_PHASE_PS_STR_6) "0 ps" +set var(PLL_C_CNT_DUTY_CYCLE_6) 50 +set var(PLL_C_CNT_LOW_7) 256 +set var(PLL_C_CNT_HIGH_7) 256 +set var(PLL_C_CNT_BYPASS_EN_7) true +set var(PLL_C_CNT_PHASE_PS_STR_7) "0 ps" +set var(PLL_C_CNT_DUTY_CYCLE_7) 50 +set var(PLL_C_CNT_LOW_8) 256 +set var(PLL_C_CNT_HIGH_8) 256 +set var(PLL_C_CNT_BYPASS_EN_8) true +set var(PLL_C_CNT_PHASE_PS_STR_8) "0 ps" +set var(PLL_C_CNT_DUTY_CYCLE_8) 50 + +set var(C2P_SETUP_OC_NS) 0.000 +set var(C2P_HOLD_OC_NS) 0.000 +set var(P2C_SETUP_OC_NS) 0.000 +set var(P2C_HOLD_OC_NS) 0.000 +set var(C2C_SAME_CLK_SETUP_OC_NS) 0.000 +set var(C2C_SAME_CLK_HOLD_OC_NS) 0.000 +set var(C2C_DIFF_CLK_SETUP_OC_NS) 0.000 +set var(C2C_DIFF_CLK_HOLD_OC_NS) 0.000 +set var(C2C_TG_FALSE_PATH) false +set var(C2P_P2C_PR) false + +set var(PATTERNS_AC_CLK) [list arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].b|cal_oct.obuf|o] +set var(PATTERNS_AC_CLK_N) [list arch|arch_inst|bufs_inst|gen_mem_ck.inst[0].b|cal_oct.obuf_bar|o] +set var(PATTERNS_AC_SYNC) [list arch|arch_inst|bufs_inst|gen_mem_a.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[2].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[3].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[4].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[5].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[6].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[7].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[8].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[9].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[10].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[11].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[12].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[13].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[14].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[15].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_a.inst[16].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_act_n.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_ba.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_ba.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_bg.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_bg.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_cke.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_cs_n.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_odt.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_par.inst[0].b|cal_oct.obuf|o] +set var(PATTERNS_AC_ASYNC) [list arch|arch_inst|bufs_inst|gen_mem_reset_n.inst[0].b|no_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_alert_n.inst[0].b|no_oct.ibuf|i] +set var(PATTERNS_RCLK) [list arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[8].b|cal_oct.obuf|o] +set var(PATTERNS_RCLK_N) [list arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[8].b|cal_oct.obuf_bar|o] +set var(PATTERNS_WCLK) [list arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[8].b|cal_oct.obuf|o] +set var(PATTERNS_WCLK_N) [list arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf_bar|o \ + arch|arch_inst|bufs_inst|gen_mem_dqs.inst[8].b|cal_oct.obuf_bar|o] +set var(PATTERNS_RDATA) [list arch|arch_inst|bufs_inst|gen_mem_dq.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[2].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[3].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[4].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[5].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[6].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[7].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[8].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[9].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[10].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[11].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[12].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[13].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[14].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[15].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[16].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[17].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[18].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[19].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[20].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[21].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[22].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[23].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[24].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[25].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[26].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[27].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[28].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[29].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[30].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[31].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[32].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[33].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[34].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[35].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[36].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[37].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[38].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[39].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[40].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[41].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[42].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[43].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[44].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[45].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[46].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[47].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[48].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[49].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[50].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[51].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[52].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[53].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[54].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[55].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[56].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[57].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[58].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[59].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[60].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[61].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[62].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[63].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[64].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[65].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[66].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[67].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[68].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[69].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[70].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[71].b|cal_oct.obuf|o] +set var(PATTERNS_WDATA) [list arch|arch_inst|bufs_inst|gen_mem_dq.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[2].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[3].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[4].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[5].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[6].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[7].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[8].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[9].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[10].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[11].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[12].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[13].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[14].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[15].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[16].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[17].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[18].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[19].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[20].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[21].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[22].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[23].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[24].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[25].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[26].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[27].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[28].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[29].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[30].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[31].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[32].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[33].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[34].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[35].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[36].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[37].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[38].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[39].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[40].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[41].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[42].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[43].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[44].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[45].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[46].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[47].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[48].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[49].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[50].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[51].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[52].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[53].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[54].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[55].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[56].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[57].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[58].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[59].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[60].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[61].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[62].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[63].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[64].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[65].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[66].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[67].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[68].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[69].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[70].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dq.inst[71].b|cal_oct.obuf|o] +set var(PATTERNS_DM) [list ] +set var(PATTERNS_DBI) [list arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[0].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[1].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[2].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[3].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[4].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[5].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[6].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[7].b|cal_oct.obuf|o \ + arch|arch_inst|bufs_inst|gen_mem_dbi_n.inst[8].b|cal_oct.obuf|o] +set var(PATTERNS_ALERT_N) [list arch|arch_inst|bufs_inst|gen_mem_alert_n.inst[0].b|no_oct.ibuf|i] + +initialize_clock_uncertainty_data diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl new file mode 100644 index 0000000000..334b6b9459 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl @@ -0,0 +1,28 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file specifies the timing properties of the memory device and +# of the memory interface +# Note - this file is no longer used and will be blank + + + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl new file mode 100644 index 0000000000..878740f6f2 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl @@ -0,0 +1,861 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +set script_dir [file dirname [info script]] +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_utils.tcl" + +load_package sdc_ext + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_ddr_pins { instname allpins var_array_name} { + # We need to make a local copy of the allpins associative array + upvar allpins pins + upvar 1 $var_array_name var + set debug 0 + + set var(pll_inclock_search_depth) 30 + set var(pll_outclock_search_depth) 20 + set var(pll_vcoclock_search_depth) 5 + + # ######################################## + # 1.0 find all of the PLL output clocks + + + set pll_c0_periph_clock_pin_name "lvds_clk\[0\]" + set pll_c1_periph_clock_pin_name "loaden\[0\]" + set vco_clock_pin_name "vcoph\[0\]" + + # C0 output in the periphery + set pins(pll_c0_periph_clock) [list] + set pins(pll_c0_periph_clock_pin_id) [get_pins -nowarn [list ${instname}|arch|arch_inst|pll_inst|pll_inst*|$pll_c0_periph_clock_pin_name]] + + foreach_in_collection c $pins(pll_c0_periph_clock_pin_id) { + set pin_info [get_pin_info -net $c] + set net_name [get_net_info -name $pin_info] + + if {$debug} { + puts "PLL pin -> PLL Net: [get_node_info -name $c] -> $net_name" + } + lappend pins(pll_c0_periph_clock) [regsub -all {\\} $net_name {\\\\}] + } + set pins(pll_c0_periph_clock) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_duplicate_names $pins(pll_c0_periph_clock)] + + # C1 output in the periphery + set pins(pll_c1_periph_clock) [list] + set pins(pll_c1_periph_clock_pin_id) [get_pins -nowarn [list ${instname}|arch|arch_inst|pll_inst|pll_inst*|$pll_c1_periph_clock_pin_name]] + + foreach_in_collection c $pins(pll_c1_periph_clock_pin_id) { + set pin_info [get_pin_info -net $c] + set net_name [get_net_info -name $pin_info] + + if {$debug} { + puts "PLL pin -> PLL Net: [get_node_info -name $c] -> $net_name" + } + + lappend pins(pll_c1_periph_clock) [regsub -all {\\} $net_name {\\\\}] + } + set pins(pll_c1_periph_clock) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_duplicate_names $pins(pll_c1_periph_clock)] + + # VCO clock (used for the system clock) + set pins(vco_clock) [list] + set pins(vco_clock_pin_id) [get_pins -nowarn [list ${instname}|arch|arch_inst|pll_inst|pll_inst*|$vco_clock_pin_name]] + + foreach_in_collection c $pins(vco_clock_pin_id) { + set pin_info [get_pin_info -net $c] + set net_name [get_net_info -name $pin_info] + + if {$debug} { + puts "PLL pin -> PLL Net: [get_node_info -name $c] -> $net_name" + } + + lappend pins(vco_clock) [regsub -all {\\} $net_name {\\\\}] + } + set pins(vco_clock) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_duplicate_names $pins(vco_clock)] + set pins(pll_vco_clock) $pins(vco_clock) + set pins(pll_phy_clock) $pins(pll_c1_periph_clock) + set pins(pll_phy_clock_l) $pins(pll_c0_periph_clock) + + if {$debug == 1} { + puts "VCO: $pins(pll_vco_clock)" + puts "PHY: $pins(pll_phy_clock)" + puts "PHY_L: $pins(pll_phy_clock_l)" + puts "" + } + + ######################################### + # 2.0 Find the actual master core clock + # As it could come from another interface + # In master/slave configurations + # + # Skip this if we're in HPS mode as core clocks don't exist + + set pins(master_vco_clock) "" + set pins(master_vco_clock_sec) "" + set pins(master_core_usr_clock) "" + set pins(master_core_usr_half_clock) "" + set pins(master_core_usr_clock_sec) "" + set pins(master_core_usr_half_clock_sec) "" + set pins(master_core_afi_clock) "" + set pins(master_core_dft_cpa_1_clock) "" + set pins(master_cal_master_clk) "" + set pins(master_cal_slave_clk) "" + + if {$var(IS_HPS)} { + set pins(master_instname) $instname + + } else { + set msg_list [ list ] + + set num_of_cpa_blocks [expr {$var(PHY_PING_PONG_EN) ? 2 : 1}] + + for {set cpa_idx 0} {$cpa_idx < $num_of_cpa_blocks} {incr cpa_idx} { + + if {$cpa_idx == 0} { + set sync_reset_reg ${instname}|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor + } else { + set sync_reset_reg ${instname}|arch|arch_inst|non_hps.core_clks_rsts_inst|pp.reset_sync_sec_sdc_anchor + } + + set core_reset_sync_clock "_UNDEFINED_PIN_" + set core_reset_sync_clock_id [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_output_clock_id $sync_reset_reg "Usr clock" msg_list var] + if {$core_reset_sync_clock_id == -1} { + foreach {msg_type msg} $msg_list { + post_message -type $msg_type "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: $msg" + } + post_message -type error "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: Failed to find clock source for register $sync_reset_reg" + + if {$var(PHY_CORE_CLKS_SHARING_ENUM) == "CORE_CLKS_SHARING_SLAVE"} { + post_message -type error "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: This is a clock sharing SLAVE interface. Please ensure that the clks_sharing_master_out port of the master is connected to the clks_sharing_master_in port of the slave(s)." + if {$cpa_idx > 0} { + post_message -type error "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: This clock sharing slave interface uses a Ping-Pong PHY and has extra clock/reset requirements. Please ensure that the master interface is also a ping-pong interface. A ping-pong interface can act as clock sharing master for both ping-pong and non-ping-pong interfaces." + } + } else { + post_message -type error "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: Please ensure that the register has not been removed or optimized away." + } + } else { + set core_reset_sync_clock [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_pll_clock_name $core_reset_sync_clock_id] + } + + if {[regexp {(^.*)\|arch\|arch_inst\|io_tiles_wrap_inst\|io_tiles_inst\|tile_gen\[([0-9])\].tile_ctrl_inst(.*)\|pa_core_clk_out\[[0-9]\]$} $core_reset_sync_clock matched pins(master_instname) tilegen_num tile_instnum] == 1} { + if {$var(PHY_CONFIG_ENUM) == "CONFIG_PHY_AND_HARD_CTRL"} { + if {$var(USER_CLK_RATIO) == 2 && $var(C2P_P2C_CLK_RATIO) == 4} { + if {$cpa_idx == 0} { + set pins(master_core_usr_clock) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[0\]" + set pins(master_core_usr_half_clock) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[1\]" + } else { + set pins(master_core_usr_clock_sec) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[0\]" + set pins(master_core_usr_half_clock_sec) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[1\]" + } + } else { + if {$cpa_idx == 0} { + set pins(master_core_usr_clock) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[0\]" + } else { + set pins(master_core_usr_clock_sec) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[0\]" + } + } + set pins(master_core_dft_cpa_1_clock) [expr {$var(DIAG_CPA_OUT_1_EN) ? "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[1\]" : ""}] + + } else { + set pins(master_core_afi_clock) "$pins(master_instname)|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen\[${tilegen_num}\].tile_ctrl_inst${tile_instnum}|pa_core_clk_out\[0\]" + } + + if { $::TimeQuestInfo(nameofexecutable) == "quartus_map" || $::TimeQuestInfo(nameofexecutable) == "quartus_syn"} { + set vco_clock_name "_UNDEFINED_PIN_" + } else { + set vco_clock_id [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_vco_clk_id $core_reset_sync_clock_id var] + set vco_clock_name [get_net_info -name [get_pin_info -net $vco_clock_id]] + } + if {$cpa_idx == 0} { + set pins(master_vco_clock) $vco_clock_name + } else { + set pins(master_vco_clock_sec) $vco_clock_name + } + + } else { + post_message -type error "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: Failed to find CPA outputs." + } + } + + if {!$var(DIAG_USE_CPA_LOCK)} { + set pins(counter_lock_reg) $pins(master_instname)|arch|arch_inst|non_hps.core_clks_rsts_inst|counter_lock + } + + set pll_master_user_clock_base [string range $pins(master_vco_clock) 0 [string last "|" $pins(master_vco_clock)] ]pll_inst|outclk + + set var(pll_c3_cnt) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_calculate_counter_value $var(PLL_C_CNT_HIGH_3) $var(PLL_C_CNT_LOW_3) $var(PLL_C_CNT_BYPASS_EN_3)] + set pins(master_cal_slave_clk) "$pll_master_user_clock_base\[3\]" + + set var(pll_c4_cnt) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_calculate_counter_value $var(PLL_C_CNT_HIGH_4) $var(PLL_C_CNT_LOW_4) $var(PLL_C_CNT_BYPASS_EN_4)] + set pins(master_cal_master_clk) "$pll_master_user_clock_base\[4\]" + } + + if {$debug == 1} { + puts "Master VCO : $pins(master_vco_clock)" + puts "Master Core USR : $pins(master_core_usr_clock)" + puts "Master Core USR Half : $pins(master_core_usr_half_clock)" + puts "Master Core AFI : $pins(master_core_afi_clock)" + puts "Master VCO (SECONDARY) : $pins(master_vco_clock_sec)" + puts "Master Core USR (SECONDARY) : $pins(master_core_usr_clock_sec)" + puts "Master Core USR Half (SECONDARY) : $pins(master_core_usr_half_clock_sec)" + puts "" + } + + # ######################################## + # 2.5 Find the reference clock input of the PLL + + set pins(pll_cascade_in_id) [get_pins -nowarn -compatibility_mode $pins(master_instname)|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in] + if {[get_collection_size $pins(pll_cascade_in_id)] == 0} { + set pins(pll_cascade_in_id) [get_pins -compatibility_mode $pins(master_instname)|arch|arch_inst|pll_inst|pll_inst|core_refclk] + } + set pll_ref_clock_id [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_input_clk_id $pins(pll_cascade_in_id) var] + if {$pll_ref_clock_id == -1} { + post_message -type critical_warning "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl: Failed to find PLL reference clock" + } else { + set pll_ref_clock [get_node_info -name $pll_ref_clock_id] + } + set pins(pll_ref_clock) $pll_ref_clock + + if {$debug == 1} { + puts "REF: $pins(pll_ref_clock)" + puts "" + } + + ######################################### + # 3.0 find the FPGA pins + + # The hierarchy paths to all the pins are stored in the *_ip_parameters.tcl + # file which is a generated file. Pins are divided into the following + # protocol-agnostic categories. For each pin category, we need to + # fully-resolve the hierarchy path patterns and store the results into + # the "pins" arrays. + + set pin_categories [list ac_clk \ + ac_clk_n \ + ac_sync \ + ac_async \ + rclk \ + rclk_n \ + wclk \ + wclk_n \ + rdata \ + wdata \ + dm \ + dbi ] + + set patterns [ list ] + foreach pin_category $pin_categories { + set pins($pin_category) [list] + + foreach pattern $var(PATTERNS_[string toupper $pin_category]) { + set pattern "${instname}|$pattern" + lappend patterns $pin_category $pattern + } + } + + foreach {pin_type pattern} $patterns { + if {[string match "*|o" $pattern]} { + set local_pins [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_names_in_collection [ get_fanouts $pattern ] ] + } else { + set local_pins [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_names_in_collection [ get_fanins $pattern ] ] + } + + if {[llength $local_pins] == 0} { + post_message -type critical_warning "Could not find pin of type $pin_type from pattern $pattern" + } else { + foreach pin [lsort -unique $local_pins] { + lappend pins($pin_type) $pin + } + } + } + + + ######################################### + # 4.0 setup extra PLL clocks parameters + + # User can use remaining PLL clocks from EMIF GUI and this is to + # setup the parameters for those clocks such as multiply_by + # and divide_by + + if {$var(PLL_NUM_OF_EXTRA_CLKS) > 0} { + + set pll_master_user_clock_base [string range $pins(master_vco_clock) 0 [string last "|" $pins(master_vco_clock)] ]pll_inst|outclk + + set var(pll_num_of_reserved_cnts) 5 + + for {set i 0} {$i < $var(PLL_NUM_OF_EXTRA_CLKS)} {incr i} { + set i_cnt_num [expr $i + $var(pll_num_of_reserved_cnts)] + set var(pll_c${i_cnt_num}_cnt) [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_calculate_counter_value $var(PLL_C_CNT_HIGH_${i_cnt_num}) $var(PLL_C_CNT_LOW_${i_cnt_num}) $var(PLL_C_CNT_BYPASS_EN_${i_cnt_num})] + set pins(pll_extra_clk_${i}) "$pll_master_user_clock_base\[$i_cnt_num\]" + } + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_initialize_ddr_db { ddr_db_par var_array_name} { + upvar $ddr_db_par local_ddr_db + upvar 1 $var_array_name var + + global ::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename + global ::io_only_analysis + + post_sdc_message info "Initializing DDR database for CORE $::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename" + set instance_list [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_instance_list $::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename] + + foreach instname $instance_list { + + if {$::io_only_analysis == 0} { + post_sdc_message info "Finding port-to-pin mapping for CORE: $::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename INSTANCE: $instname" + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_ddr_pins $instname allpins var + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_verify_ddr_pins allpins var + } + + set local_ddr_db($instname) [ array get allpins ] + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_verify_ddr_pins { pins_par var_array_name} { + + upvar 1 $var_array_name var + upvar $pins_par pins + + if { [ llength $pins(pll_phy_clock) ] != [ llength $pins(pll_vco_clock) ] } { + post_message -type critical_warning "Found different amounts of the phy_clocks compared to the vco_clocks" + } + if {!$var(IS_HPS)} { + if {$var(PHY_CONFIG_ENUM) == "CONFIG_PHY_AND_HARD_CTRL"} { + if { [ llength $pins(master_core_usr_clock) ] != 1 } { + post_message -type critical_warning "Found [ llength $pins(master_core_usr_clock) ] of master_core_usr_clock when there should be 1" + } + + if {$var(USER_CLK_RATIO) == 2 && $var(C2P_P2C_CLK_RATIO) == 4} { + if { [ llength $pins(master_core_usr_half_clock) ] != 1 } { + post_message -type critical_warning "Found [ llength $pins(master_core_usr_half_clock) ] of master_core_usr_half_clock when there should be 1" + } + } + + if {$var(PHY_PING_PONG_EN)} { + if { [ llength $pins(master_core_usr_clock_sec) ] != 1 } { + post_message -type critical_warning "Found [ llength $pins(master_core_usr_clock_sec) ] of master_core_usr_clock_sec when there should be 1" + } + + if {$var(USER_CLK_RATIO) == 2 && $var(C2P_P2C_CLK_RATIO) == 4} { + if { [ llength $pins(master_core_usr_half_clock_sec) ] != 1 } { + post_message -type critical_warning "Found [ llength $pins(master_core_usr_half_clock_sec) ] of master_core_usr_half_clock_sec when there should be 1" + } + } + } + } else { + if { [ llength $pins(master_core_afi_clock) ] != 1 } { + post_message -type critical_warning "Found [ llength $pins(master_core_afi_clock) ] of master_core_afi_clock when there should be 1" + } + } + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_all_instances_dqs_pins { ddr_db_par } { + upvar $ddr_db_par local_ddr_db + + set dqs_pins [ list ] + set instnames [ array names local_ddr_db ] + foreach instance $instnames { + array set pins $local_ddr_db($instance) + + foreach { dqs_pin } $pins(dqs_pins) { + lappend dqs_pins ${dqs_pin}_IN + lappend dqs_pins ${dqs_pin}_OUT + } + foreach { dqsn_pin } $pins(dqsn_pins) { + lappend dqs_pins ${dqsn_pin}_OUT + } + foreach { ck_pin } $pins(ck_pins) { + lappend dqs_pins $ck_pin + } + } + + return $dqs_pins +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_calculate_counter_value { cnt_hi cnt_lo cnt_bypass } { + if {$cnt_bypass} { + set result 1 + } else { + set result [expr {$cnt_hi + $cnt_lo}] + } + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_input_clk_id { pll_inclk_id var_array_name} { + upvar 1 $var_array_name var + + array set results_array [list] + + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_fanin_up_to_depth $pll_inclk_id ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_is_node_type_pin clock results_array $var(pll_inclock_search_depth) + if {[array size results_array] == 1} { + set pin_id [lindex [array names results_array] 0] + set result $pin_id + } else { + post_message -type critical_warning "Could not find PLL clock for [get_node_info -name $pll_inclk_id]" + set result -1 + } + + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_output_clock_id { pin_list pin_type msg_list_name var_array_name} { + upvar 1 $msg_list_name msg_list + upvar 1 $var_array_name var + set output_clock_id -1 + + set output_id_list [list] + set pin_collection [get_keepers -no_duplicates $pin_list] + if {[get_collection_size $pin_collection] == [llength $pin_list]} { + foreach_in_collection id $pin_collection { + lappend output_id_list $id + } + } elseif {[get_collection_size $pin_collection] == 0} { + lappend msg_list "warning" "Could not find any $pin_type pins" + } else { + lappend msg_list "warning" "Could not find all $pin_type pins" + } + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_pll_clock $output_id_list $pin_type output_clock_id $var(pll_outclock_search_depth) + return $output_clock_id +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_pll_clock { dest_id_list node_type clock_id_name search_depth} { + if {$clock_id_name != ""} { + upvar 1 $clock_id_name clock_id + } + set clock_id -1 + + array set clk_array [list] + foreach node_id $dest_id_list { + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_fanin_up_to_depth $node_id ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_is_node_type_pll_clk clock clk_array $search_depth + } + if {[array size clk_array] == 1} { + set clock_id [lindex [array names clk_array] 0] + set clk [get_node_info -name $clock_id] + } elseif {[array size clk_array] > 1} { + puts "Found more than 1 clock driving the $node_type" + set clk "" + } else { + set clk "" + } + + return $clk +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_vco_clk_id { wf_clock_id var_array_name} { + upvar 1 $var_array_name var + + array set results_array [list] + + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_fanin_up_to_depth $wf_clock_id ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_is_node_type_vco clock results_array $var(pll_vcoclock_search_depth) + if {[array size results_array] == 1} { + set pin_id [lindex [array names results_array] 0] + set result $pin_id + } else { + post_message -type critical_warning "Could not find VCO clock for [get_node_info -name $wf_clock_id]" + set result -1 + } + + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_is_node_type_pll_clk { node_id } { + set cell_id [get_node_info -cell $node_id] + + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "IOPLL"} { + set node_name [get_node_info -name $node_id] + + if {[regexp {pll_inst~.*OUTCLK[0-9]$} $node_name]} { + set result 1 + } else { + set result 0 + } + } elseif {$atom_type == "TILE_CTRL"} { + set node_name [get_node_info -name $node_id] + + if {[regexp {tile_ctrl_inst.*\|pa_core_clk_out\[[0-9]\]$} $node_name]} { + set result 1 + } else { + set result 0 + } + } else { + set result 0 + } + } + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_is_node_type_vco { node_id } { + set cell_id [get_node_info -cell $node_id] + + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "IOPLL"} { + set node_name [get_node_info -name $node_id] + + if {[regexp {pll_inst.*\|.*vcoph\[0\]$} $node_name]} { + set result 1 + } elseif {[regexp {pll_inst.*VCOPH0$} $node_name]} { + set result 1 + } else { + set result 0 + } + } else { + set result 0 + } + } + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_does_ref_clk_exist { ref_clk_name } { + + set ref_clock_found 0 + foreach_in_collection iclk [get_clocks -nowarn] { + if { ![is_clock_defined $iclk] } { + continue + } + set clk_targets [get_clock_info -target $iclk] + foreach_in_collection itgt $clk_targets { + set node_name [get_node_info -name $itgt] + if {[string compare $node_name $ref_clk_name] == 0} { + set ref_clock_found 1 + break + } + } + if {$ref_clock_found == 1} { + break; + } + } + + return $ref_clock_found +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_p2c_c2p_clock_uncertainty { instname var_array_name } { + + set success 1 + set error_message "" + set clock_uncertainty 0 + set debug 0 + + package require ::quartus::atoms + upvar 1 $var_array_name var + + catch {read_atom_netlist} read_atom_netlist_out + set read_atom_netlist_error [regexp "ERROR" $read_atom_netlist_out] + + if {$read_atom_netlist_error == 0} { + if {[ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_are_entity_names_on]} { + regsub -all {\|} $instname "|*:" instname + } + regsub -all {\\} $instname {\\\\} instname + regsub -all {\[} $instname "\\\[" instname + regsub -all {\]} $instname "\\\]" instname + + # Find the IOPLLs + if {$success == 1} { + if {[ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_are_entity_names_on]} { + set pll_atoms [get_atom_nodes -matching *${instname}|*:arch|*:arch_inst|*:pll_inst|* -type IOPLL] + } else { + set pll_atoms [get_atom_nodes -matching *${instname}|arch|arch_inst|pll_inst|* -type IOPLL] + } + set num_pll_inst [get_collection_size $pll_atoms] + + if {$num_pll_inst == 0} { + set success 0 + post_message -type critical_warning "The auto-constraining script was not able to detect any PLLs in the < $instname > memory interface." + } + } + + # Get atom parameters + if {$success == 1} { + + set mcnt_list [list] + set bw_list [list] + set cp_setting_list [list] + set vco_period_list [list] + + foreach_in_collection pll_atom $pll_atoms { + + # M-counter value + if {[get_atom_node_info -node $pll_atom -key BOOL_IOPLL_M_COUNTER_BYPASS_EN] == 1} { + set mcnt 1 + } else { + set mcnt [expr [get_atom_node_info -node $pll_atom -key INT_IOPLL_M_COUNTER_HIGH] + [get_atom_node_info -node $pll_atom -key INT_IOPLL_M_COUNTER_LOW]] + } + lappend mcnt_list $mcnt + + # BW + set bw [get_atom_node_info -node $pll_atom -key ENUM_IOPLL_BW_MODE] + if {[string compare -nocase $bw "AUTO"] == 0} { + set bw "LBW" + } elseif {[string compare -nocase $bw "LOW_BW"] == 0} { + set bw "LBW" + } elseif {[string compare -nocase $bw "MID_BW"] == 0} { + set bw "MBW" + } elseif {[string compare -nocase $bw "HI_BW"] == 0} { + set bw "HBW" + } + lappend bw_list $bw + + # CP current setting (stubbed out for now as this is set internally) + set cp_setting PLL_CP_SETTING0 + lappend cp_setting_list $cp_setting + + # VCO frequency setting + set vco_period [get_atom_node_info -node $pll_atom -key TIME_IOPLL_VCO] + lappend vco_period_list $vco_period + } + + # Make sure all IOPLL parameters are the same + for {set i [expr [llength $mcnt_list] - 1]} {$i > 0} {set i [expr $i - 1]} { + if {[lindex $mcnt_list $i] != [lindex $mcnt_list [expr $i - 1]]} { + set success 0 + post_message -type critical_warning "The auto-constraining script found multiple PLLs in the < $instname > memory interface with different parameters." + } + } + for {set i [expr [llength $bw_list] - 1]} {$i > 0} {set i [expr $i - 1]} { + set bw_a [lindex $bw_list $i] + set bw_b [lindex $bw_list [expr $i - 1]] + if {[string compare -nocase $bw_a $bw_b] != 0} { + set success 0 + post_message -type critical_warning "The auto-constraining script found multiple PLLs in the < $instname > memory interface with different parameters." + } + } + for {set i [expr [llength $cp_setting_list] - 1]} {$i > 0} {set i [expr $i - 1]} { + set cp_a [lindex $cp_setting_list $i] + set cp_b [lindex $cp_setting_list [expr $i - 1]] + if {[string compare -nocase $cp_a $cp_b] != 0} { + set success 0 + post_message -type critical_warning "The auto-constraining script found multiple PLLs in the < $instname > memory interface with different parameters." + } + } + + for {set i [expr [llength $vco_period_list] - 1]} {$i > 0} {set i [expr $i - 1]} { + set vco_a [lindex $vco_period_list $i] + set vco_b [lindex $vco_period_list [expr $i - 1]] + if {[string compare -nocase $vco_a $vco_b] != 0} { + set success 0 + post_message -type critical_warning "The auto-constraining script found multiple PLLs in the < $instname > memory interface with different parameters." + } + } + } + + # Calculate clock uncertainty + if {$success == 1} { + + set mcnt [lindex $mcnt_list 0] + set bw [string toupper [lindex $bw_list 0]] + set cp_setting [lindex $cp_setting_list 0] + set cp_current [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_cp_current_from_setting $cp_setting] + set vco_period [lindex $vco_period_list 0] + if {[regexp {([0-9]+) ps} $vco_period matched vco_period] == 1} { + } else { + post_message -type critical_warning "The auto-constraining script was not able to read the netlist." + set success 0 + } + set vco_frequency_in_mhz [expr 1000000 / $vco_period] + + if {$debug} { + puts "MCNT : $mcnt" + puts "BW : $bw" + puts "CP : $cp_setting ($cp_current)" + puts "VCO : $vco_period" + } + + set HFR [get_clock_frequency_uncertainty_data PLL $vco_frequency_in_mhz $bw OFFSET${mcnt} HFR] + set LFD [get_clock_frequency_uncertainty_data PLL $vco_frequency_in_mhz $bw OFFSET${mcnt} LFD] + set SPE [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_spe_from_cp_current $cp_current] + + if {$success == 1} { + set clock_uncertainty_sqrt [expr sqrt(($LFD/2)*($LFD/2) + ($LFD/2)*($LFD/2))] + set clock_uncertainty [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp [expr ($clock_uncertainty_sqrt + $SPE)*1e9]] + + if {$debug} { + puts "HFR : $HFR" + puts "LFD : $LFD" + puts "SPE : $SPE" + puts "TOTAL: $clock_uncertainty" + } + } + } + + } else { + set success 0 + post_message -type critical_warning "The auto-constraining script was not able to read the netlist." + } + + # Output warning in the case that clock uncertainty can't be determined + if {$success == 0} { + post_message -type critical_warning "Verify the following:" + post_message -type critical_warning " The core < $instname > is instantiated within another component (wrapper)" + post_message -type critical_warning " The core is not the top-level of the project" + post_message -type critical_warning " The memory interface pins are exported to the top-level of the project" + post_message -type critical_warning " The core < $instname > RTL has not been modified manually" + } + + return $clock_uncertainty +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_cp_current_from_setting { cp_setting } { + + set cp_current 0 + + if {[string compare -nocase $cp_setting "PLL_CP_SETTING0"] == 0} { + set cp_current 0 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING1"] == 0} { + set cp_current 5 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING2"] == 0} { + set cp_current 10 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING3"] == 0} { + set cp_current 15 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING4"] == 0} { + set cp_current 20 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING5"] == 0} { + set cp_current 25 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING6"] == 0} { + set cp_current 30 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING7"] == 0} { + set cp_current 35 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING8"] == 0} { + set cp_current 40 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING9"] == 0} { + set cp_current 45 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING10"] == 0} { + set cp_current 50 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING11"] == 0} { + set cp_current 55 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING12"] == 0} { + set cp_current 60 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING13"] == 0} { + set cp_current 65 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING14"] == 0} { + set cp_current 70 + } elseif {[string compare -nocase $cp_setting "PLL_CP_SETTING15"] == 0} { + set cp_current 75 + } else { + set cp_current 0 + } + + return $cp_current +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_spe_from_cp_current { cp_current } { + + set spe 158.0e-12 + + if {$cp_current <= 15} { + set spe 158e-012 + } elseif {$cp_current <= 20} { + set spe 130.62e-12 + } elseif {$cp_current <= 25} { + set spe 117.3e-12 + } elseif {$cp_current <= 30} { + set spe 109.5e-12 + } elseif {$cp_current <= 35} { + set spe 104.5e-12 + } elseif {$cp_current <= 40} { + set spe 100.9e-12 + } elseif {$cp_current <= 60} { + set spe 93.3e-12 + } else { + set spe 93.3e-12 + } + + return $spe +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_periphery_clock_uncertainty { results_array_name var_array_name } { + upvar 1 $results_array_name results + upvar 1 $var_array_name var + + if {$var(DIAG_TIMING_REGTEST_MODE)} { + set c2p_setup 0.050 + set c2p_hold 0.0 + set p2c_setup 0.050 + set p2c_hold 0.0 + } else { + set c2p_setup 0.0 + set c2p_hold 0.0 + set p2c_setup 0.0 + set p2c_hold 0.0 + } + + set results [list $c2p_setup $c2p_hold $p2c_setup $p2c_hold] +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_clock_uncertainty { results_array_name var_array_name } { + upvar 1 $results_array_name results + upvar 1 $var_array_name var + + set c2c_same_setup 0 + set c2c_same_hold 0 + set c2c_diff_setup 0 + set c2c_diff_hold 0 + + set results [list $c2c_same_setup $c2c_same_hold $c2c_diff_setup $c2c_diff_hold] +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_overconstraints { results_array_name var_array_name } { + upvar 1 $results_array_name results + upvar 1 $var_array_name var + + set results [list $var(C2C_SAME_CLK_SETUP_OC_NS) $var(C2C_SAME_CLK_HOLD_OC_NS) $var(C2C_DIFF_CLK_SETUP_OC_NS) $var(C2C_DIFF_CLK_HOLD_OC_NS)] +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_periphery_overconstraints { results_st_array_name results_mt_array_name var_array_name } { + upvar 1 $results_st_array_name results_st + upvar 1 $results_mt_array_name results_mt + upvar 1 $var_array_name var + + set c2p_p2c_frequency [expr $var(PHY_MEM_CLK_FREQ_MHZ)/$var(C2P_P2C_CLK_RATIO)] + + set results_st [list $var(C2P_SETUP_OC_NS) $var(C2P_HOLD_OC_NS) $var(P2C_SETUP_OC_NS) $var(P2C_HOLD_OC_NS)] + set results_mt [list [expr $var(C2P_SETUP_OC_NS) + 0.000] [expr $var(C2P_HOLD_OC_NS) + 0.000] [expr $var(P2C_SETUP_OC_NS) + 0.000] [expr $var(P2C_HOLD_OC_NS) + 0.000]] + +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_duplicate_names { names_array } { + + set main_name "" + set duplicate_names [list] + + # Find the main name as opposed to all the duplicate names + foreach { name } $names_array { + if {[regexp {Duplicate} $name]} { + lappend duplicate_names $name + } else { + if {$main_name == ""} { + set main_name $name + } else { + post_message -type error "More than one main tile name ($main_name and $name). Please verify the connectivity of these pins." + } + } + } + + # Now sort the duplicate names + set duplicate_names [lsort -decreasing $duplicate_names] + + # Prepend the main name and then return + set result [join [linsert $duplicate_names 0 $main_name]] + + return $result +} + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_readme.txt b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_readme.txt new file mode 100644 index 0000000000..a34cc42be4 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_readme.txt @@ -0,0 +1,1374 @@ +--------------------- +; Table of Contents ; +--------------------- + 1. About this file + 2. Outputs of IP generation + 3. Instantiating IP in a Quartus Prime project + 4. Board Signal Integrity Analysis + 5. I/O assignments + 6. Pin locations + 7. Sharing core clocks between interfaces + 8. Sharing PLL reference clock pin between interfaces + 9. Local reset request. Output signal from local_reset_combiner + 10. Local reset status. Input signal to the local_reset_combiner + 11. PLL reference clock input + 12. PLL locked signal + 13. On-Chip Termination (OCT) interface + 14. Interface between FPGA and external memory + 15. PHY calibration status interface + 16. User clock domain reset interface + 17. User clock interface + 18. Controller Avalon Streaming command interface 0 + 19. Controller Avalon Streaming write data interface 0 + 20. Controller Avalon Streaming read data interface 0 + 21. Controller ECC interface 0 + 22. EMIF calibration component interface + 23. EMIF calibration component clock input interface + 24. Instantiating IP in a simulation project + 25. Full-calibration versus skip-calibration simulation + 26. IP Settings + + +------------------------ +; 1. About this file ; +------------------------ + + This is the readme file for the Intel External Memory Interface (EMIF) IP v24.1. + + The file provides a high-level overview of the IP. For details, refer to the + handbook chapter on Agilex DDR4 External Memory Interface. + + This file was auto-generated. + + +--------------------------------- +; 2. Outputs of IP generation ; +--------------------------------- + + IP generation supports the following output filesets: + + Synthesis - This is the fileset you should use when instantiating the IP in + your Quartus Prime project. RTL files in this fileset can be + simulated, but your simulator must support SystemVerilog. + Simulating the synthesis files yields identical results as + simulating the simulation files. + + Simulation - This fileset contains scripts and source files to help you + integrate the IP into your simulation project targeting a + 3rd-party simulator of your choice. If you select VHDL + during IP generation, the fileset contains IEEE-encrypted + Verilog files that can be used in VHDL-only simulators, such + as ModelSim - Intel FPGA edition. All source files in the simulation + filesets are functionally equivalent to the synthesis fileset. + + Signal Integrity - This fileset contains SPICE simulation decks and compliance + mask information for evaluating if your PCB meets the signal + integrity requirements of your desired interface. It is + strongly recommended that customers obtain 12-line extractions of + their PCBs and evaluate them using this flow in order to + reduce the risk of encountering signal-integrity issues + in their memory interface design. SPICE decks are provided to + generate eye diagrams at the receiver for the address/command + channel, the data write channel, and the data read channel. + + Example Design - This fileset contains scripts to generate example Quartus Prime project + and simulation projects for 3rd-party simulators. An example + design contains an instantiation of the IP, a simple traffic + generator, and in the case of a simulation example design, a + simple memory model. + + +---------------------------------------------------- +; 3. Instantiating IP in a Quartus Prime project ; +---------------------------------------------------- + + If you instantiate the IP as part of a Platform Designer system, follow the Platform Designer + documentation on how to instantiate the system in a Quartus Prime project. + + If the IP was generated as a standalone component, it is sufficient to add + the generated .qip file from the synthesis fileset to your Quartus Prime project. + The .qip file allows the Quartus Prime software to locate all the files of + the IP, including RTL files, SDC files, hex files, and timing scripts. Once the + .qip file is added, you can instantiate the memory interface in your RTL. + + +---------------------------------------- +; 4. Board Signal Integrity Analysis ; +---------------------------------------- + + The Board Signal Integrity analysis allows you to evaluate whether or not your + External Memory Interface channel meets the impedance, crosstalk and ISI requirements + to operate your memory interface at the target frequency while meeting the minimum + data eye height and width requirements for reliable data capture. + The analysis environment takes into account the signal integrity settings you have + selected in the IP GUI for FPGA-side drive/receive strength, memory-side termination + settings, and where applicable, termination settings for channels with multiple memory + ranks (including the associated dynamic/nominal/park termination settings). + Customers must supply the location of the FPGA and memory IBIS models, as well as the + location of the 12-line PCB extraction models for the interface address/command and + data channel models. Package RLC values for the FPGA and memory must also be specified + for accurate simulation. + + To run signal integrity analysis: + + 1) Open the EMIF IP GUI + 2) Select all of the FPGA and Memory drive strength and termination settings for your design + 3) Select the "Signal Integrity" checkbox under the "Example Designs" tab + 4) Generate the IP or click the "Generate Example Design" button + 5) Locate the *_spice_files.zip and *_ip_parameters.dat files + 6) Update the *_ip_parameters.dat file with the location of your IBIS models and RLC values + 7) Unzip the *_spice_files.zip file, update the top-level SPICE decks to include the *.dat file + above, and run the simulations for Address/Command, Data Write and Data Read channels. + + Note that most of the settings that are relevant to this instance of IP are contained within the + auto-generated *_ip_parameters.dat file. If you modify this file, please be sure to save a backup + copy in case you need to restore the original simulation parameters. The *_spice_files.zip file + contails files that are common to all instances of IP, with the exception of the file + "pin_parasitics.dat", which must be updated with the pin RLC parasitic information for both the + FPGA and memory devices. Consult the EMIF IP Handbook for further details. + + +------------------------ +; 5. I/O assignments ; +------------------------ + + The generated .qip file in the synthesis fileset contains the I/O standard and input/output + termination assignments required by the memory interface pins to function correctly. + The values to the assignments are based on user inputs provided during generation. + + Unlike previous EMIF IP, there is no need to manually run a *_pin_assignments.tcl + script to annotate the assignments into the project's .qsf file. + Assignments in the .qip file are read and applied during every compilation, regardless + of how you name the memory interface pins in your design top-level component. No new + assignment is created in the project's .qsf file during the process. + + You should never edit the generated .qip file, because changes made to this file + are overwritten when you regenerate the IP. To override an I/O assignment made in + the .qip file, simply add an assignment to the project's .qsf file. Assignments in + the .qsf file always take precedence over those in the .qip file. Note that I/O + assignments in the .qsf file must specify the names of your top-level pins as + target (i.e. -to), and you must not use the -entity and -library options. + + Consult the .qip file for the set of I/O assignments that come with the IP. + + +---------------------- +; 6. Pin locations ; +---------------------- + + The Agilex I/O subsystem is located in the I/O rows. + + The pins of a memory interface must be placed within a single I/O row. A memory + interface can occupy one or more banks. When multiple banks are needed, the banks must + be consecutive. + + All address/command pins of a memory interface must be placed within a single bank. + This bank is denoted as the "address/command" bank. While any physical bank within + an I/O row can be used as an "address/command" bank, for a multi-bank memory + interface, the "address/command" bank must be at the center of the interface. + + Address/command pins within the "address/command" bank must follow a fixed pinout + scheme within the bank. Note that the pinout scheme used is dependent on the topology + of the memory interface, and is a hardware requirement. An I/O lane unused in the + "address/command" bank can be used to implement a data group (e.g. a x8 DQS group). + + A read data group must be placed based on the DQS/CQ/QK grouping in the pin table. + Specifically, read data strobes/clocks must be placed at physical pins capable of + functioning as DQS/CK/QK for a specific read data group size, and the associated + data pins must be placed within the same group. + A x8/x9 read data group occupies one lane; a x16/x18 read data group occupies either + the top or bottom 2 lanes of a bank; a x36 read data group occupies all four lanes of + a bank. For protocols/topologies where a write data group consists of multiple read data + groups, the read data groups should be placed in the same bank to improve I/O timing. + + I/Os that are unused by memory interface pins can be used as general-purpose I/Os with + compatible I/O standard and termination settings. + + The following shows one possible grouping of memory interface pins into logical banks. To + implement the scheme in your Quartus Prime project, you need to: + + 1) Decide which physical I/O banks the logical banks occupy. + 2) Add location assignments for the following pins: + All read data strobes/clocks (e.g. DQS/CQ/DQ) + One of the address/command pins + PLL reference clock pins (unless using a shared PLL reference clock pin in another interface) + RZQ pin + The Quartus Prime Fitter automatically places the remaining pins. + + The current memory interface occupies 4 banks. + + Note that this is only an example and other possible schemes may exist. The example + is functionally correct and legal, but is not necessarily optimal from the resource + consumption, timing, and board routability perspective. + + Logical bank 3: + ---------------------- + + Lane index Pin index Port + ------------------------------------------------------- + 3 47 - + . 46 - + . 45 - + . 44 - + . 43 - + . 42 - + . 41 - + . 40 - + . 39 - + . 38 - + . 37 - + . 36 - + 2 35 - + . 34 - + . 33 - + . 32 - + . 31 - + . 30 - + . 29 - + . 28 - + . 27 - + . 26 - + . 25 - + . 24 - + 1 23 - + . 22 - + . 21 - + . 20 - + . 19 - + . 18 - + . 17 - + . 16 - + . 15 - + . 14 - + . 13 - + . 12 - + 0 11 mem_dq[71] + . 10 mem_dq[70] + . 9 mem_dq[69] + . 8 mem_dq[68] + . 7 - + . 6 mem_dbi_n[8] + . 5 mem_dqs_n[8] + . 4 mem_dqs[8] + . 3 mem_dq[67] + . 2 mem_dq[66] + . 1 mem_dq[65] + . 0 mem_dq[64] + + Logical bank 2: + ---------------------- + + Lane index Pin index Port + ------------------------------------------------------- + 3 47 mem_dq[63] + . 46 mem_dq[62] + . 45 mem_dq[61] + . 44 mem_dq[60] + . 43 - + . 42 mem_dbi_n[7] + . 41 mem_dqs_n[7] + . 40 mem_dqs[7] + . 39 mem_dq[59] + . 38 mem_dq[58] + . 37 mem_dq[57] + . 36 mem_dq[56] + 2 35 mem_dq[55] + . 34 mem_dq[54] + . 33 mem_dq[53] + . 32 mem_dq[52] + . 31 - + . 30 mem_dbi_n[6] + . 29 mem_dqs_n[6] + . 28 mem_dqs[6] + . 27 mem_dq[51] + . 26 mem_dq[50] + . 25 mem_dq[49] + . 24 mem_dq[48] + 1 23 mem_dq[47] + . 22 mem_dq[46] + . 21 mem_dq[45] + . 20 mem_dq[44] + . 19 - + . 18 mem_dbi_n[5] + . 17 mem_dqs_n[5] + . 16 mem_dqs[5] + . 15 mem_dq[43] + . 14 mem_dq[42] + . 13 mem_dq[41] + . 12 mem_dq[40] + 0 11 mem_dq[39] + . 10 mem_dq[38] + . 9 mem_dq[37] + . 8 mem_dq[36] + . 7 - + . 6 mem_dbi_n[4] + . 5 mem_dqs_n[4] + . 4 mem_dqs[4] + . 3 mem_dq[35] + . 2 mem_dq[34] + . 1 mem_dq[33] + . 0 mem_dq[32] + + Logical bank 1 (address/command bank): + -------------------------------------------- + + Address/command pinout scheme : DDR4 Scheme 1A: Component and DIMM (with A17) + Number of address/command lanes: 4 + + Lane index Pin index Port + ------------------------------------------------------- + 3 47 - + . 46 - + . 45 - + . 44 mem_alert_n[0] + . 43 - + . 42 - + . 41 - + . 40 - + . 39 - + . 38 - + . 37 - + . 36 - + 2 35 mem_bg[0] + . 34 mem_ba[1] + . 33 mem_ba[0] + . 32 - + . 31 mem_a[16] + . 30 mem_a[15] + . 29 mem_a[14] + . 28 mem_a[13] + . 27 mem_a[12] + . 26 oct_rzqin - if needed + . 25 pll_ref_clk (negative leg) - if needed + . 24 pll_ref_clk (positive leg) - if needed + 1 23 mem_a[11] + . 22 mem_a[10] + . 21 mem_a[9] + . 20 mem_a[8] + . 19 mem_a[7] + . 18 mem_a[6] + . 17 mem_a[5] + . 16 mem_a[4] + . 15 mem_a[3] + . 14 mem_a[2] + . 13 mem_a[1] + . 12 mem_a[0] + 0 11 mem_par[0] + . 10 - + . 9 mem_ck_n[0] + . 8 mem_ck[0] + . 7 - + . 6 mem_cke[0] + . 5 - + . 4 mem_odt[0] + . 3 mem_act_n[0] + . 2 mem_cs_n[0] + . 1 mem_reset_n[0] + . 0 mem_bg[1] + + Logical bank 0: + ---------------------- + + Lane index Pin index Port + ------------------------------------------------------- + 3 47 mem_dq[31] + . 46 mem_dq[30] + . 45 mem_dq[29] + . 44 mem_dq[28] + . 43 - + . 42 mem_dbi_n[3] + . 41 mem_dqs_n[3] + . 40 mem_dqs[3] + . 39 mem_dq[27] + . 38 mem_dq[26] + . 37 mem_dq[25] + . 36 mem_dq[24] + 2 35 mem_dq[23] + . 34 mem_dq[22] + . 33 mem_dq[21] + . 32 mem_dq[20] + . 31 - + . 30 mem_dbi_n[2] + . 29 mem_dqs_n[2] + . 28 mem_dqs[2] + . 27 mem_dq[19] + . 26 mem_dq[18] + . 25 mem_dq[17] + . 24 mem_dq[16] + 1 23 mem_dq[15] + . 22 mem_dq[14] + . 21 mem_dq[13] + . 20 mem_dq[12] + . 19 - + . 18 mem_dbi_n[1] + . 17 mem_dqs_n[1] + . 16 mem_dqs[1] + . 15 mem_dq[11] + . 14 mem_dq[10] + . 13 mem_dq[9] + . 12 mem_dq[8] + 0 11 mem_dq[7] + . 10 mem_dq[6] + . 9 mem_dq[5] + . 8 mem_dq[4] + . 7 - + . 6 mem_dbi_n[0] + . 5 mem_dqs_n[0] + . 4 mem_dqs[0] + . 3 mem_dq[3] + . 2 mem_dq[2] + . 1 mem_dq[1] + . 0 mem_dq[0] + + +----------------------------------------------- +; 7. Sharing core clocks between interfaces ; +----------------------------------------------- + + When a design contains multiple memory interfaces of the same protocol, rate, + frequency, and PLL reference clock source, it is possible for these interfaces + to share a common set of core clock signals. Core clocks sharing allows your + logic to use a single clock domain to synchronously access all interfaces. + The feature also reduces the number of core clock networks required. + + In order for multiple memory interfaces to share core clocks, one of the interfaces + must be specified as "Master" using the "Core clocks sharing" setting during + generation, and the remaining interfaces must be denoted as "Slave". There is no + preference to which interface needs to be a master. In the RTL, connect the + clks_sharing_master_out signal from the master interface to the clks_sharing_slave_in + signal of all the slave interfaces. Note that both the master and slave interfaces + expose their own output clock ports in the RTL (e.g. emif_usr_clk, afi_clk), but the + physical signals are equivalent and so it does not matter whether a clock port from a + master or a slave is used. + + Core clocks sharing necessitates PLL reference clock sharing. Therefore, + only the master interface exposes an input port for the PLL reference clock. The + same PLL reference clock signal is used by all the slave interfaces. See section + on PLL reference clock sharing for additional requirements. + + The core clocks sharing mode of the current IP is "No Sharing" + + +----------------------------------------------------------- +; 8. Sharing PLL reference clock pin between interfaces ; +----------------------------------------------------------- + + To share a single PLL reference clock signal between multiple memory interfaces, + simply connect the same PLL reference clock signal to all interfaces in the RTL. + + Interfaces that share the same PLL reference clock signal must be placed in the + same I/O row and must occupy consecutive banks. + + +---------------------------------------------------------------------- +; 9. Local reset request. Output signal from local_reset_combiner ; +---------------------------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + local_reset_req 1 input Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. + + +--------------------------------------------------------------------- +; 10. Local reset status. Input signal to the local_reset_combiner ; +--------------------------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + local_reset_done 1 output Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. + + +---------------------------------- +; 11. PLL reference clock input ; +---------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + pll_ref_clk 1 input PLL reference clock input + + +-------------------------- +; 12. PLL locked signal ; +-------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + pll_locked 1 output PLL lock signal to indicate whether the PLL has locked + + +-------------------------------------------- +; 13. On-Chip Termination (OCT) interface ; +-------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + oct_rzqin 1 input Calibrated On-Chip Termination (OCT) RZQ input pin + + +--------------------------------------------------- +; 14. Interface between FPGA and external memory ; +--------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + mem_ck 1 output CK clock + mem_ck_n 1 output CK clock (negative leg) + mem_a 17 output Address + mem_act_n 1 output Activation command + mem_ba 2 output Bank address + mem_bg 2 output Bank group + mem_cke 1 output Clock enable + mem_cs_n 1 output Chip select + mem_odt 1 output On-die termination + mem_reset_n 1 output Asynchronous reset + mem_par 1 output Command and address parity + mem_alert_n 1 input Alert flag + mem_dqs 9 bidir Data strobe + mem_dqs_n 9 bidir Data strobe (negative leg) + mem_dq 72 bidir Read/write data + mem_dbi_n 9 bidir Acts as either the data bus inversion pin, or the data mask pin, depending on configuration. + + +----------------------------------------- +; 15. PHY calibration status interface ; +----------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + local_cal_success 1 output When high, indicates that PHY calibration was successful + local_cal_fail 1 output When high, indicates that PHY calibration failed + + +------------------------------------------ +; 16. User clock domain reset interface ; +------------------------------------------ + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + emif_usr_reset_n 1 output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion + + +----------------------------- +; 17. User clock interface ; +----------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + emif_usr_clk 1 output User clock domain + + +-------------------------------------------------------- +; 18. Controller Avalon Streaming command interface 0 ; +-------------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + ast_cmd_valid_0 1 input Indicates whether command is valid + ast_cmd_ready_0 1 output Comand request signal + ast_cmd_data_0 61 input Command data + + +----------------------------------------------------------- +; 19. Controller Avalon Streaming write data interface 0 ; +----------------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + ast_wr_valid_0 1 input Indicates whether write data is valid + ast_wr_ready_0 1 output Write request signal + ast_wr_data_0 648 input Write data + + +---------------------------------------------------------- +; 20. Controller Avalon Streaming read data interface 0 ; +---------------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + ast_rd_valid_0 1 output Read request signal + ast_rd_ready_0 1 input Indicates whether read data is valid + ast_rd_data_0 576 output Read data + + +----------------------------------- +; 21. Controller ECC interface 0 ; +----------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + ctrl_ecc_write_info_0 15 input ctrl_ecc_write_info_0 + ctrl_ecc_rdata_id_0 13 output ctrl_ecc_rdata_id_0 + ctrl_ecc_read_info_0 3 output ctrl_ecc_read_info_0 + ctrl_ecc_cmd_info_0 3 output ctrl_ecc_cmd_info_0 + ctrl_ecc_idle_0 1 output ctrl_ecc_idle_0 + ctrl_ecc_wr_pointer_info_0 12 output ctrl_ecc_wr_pointer_info_0 + + +--------------------------------------------- +; 22. EMIF calibration component interface ; +--------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + calbus_read 1 output EMIF Calibration component bus for read + calbus_write 1 output EMIF Calibration component bus for write + calbus_address 20 output EMIF Calibration component bus for address + calbus_wdata 32 output EMIF Calibration component bus for write data + calbus_rdata 32 input EMIF Calibration component bus for read data + calbus_seq_param_tbl 4096 input EMIF Calibration component bus for parameter table data + + +--------------------------------------------------------- +; 23. EMIF calibration component clock input interface ; +--------------------------------------------------------- + + Port Width Direction Description + ------------------------------------------------------------------------------------------------------ + calbus_clk 1 output EMIF Calibration component bus for the clock + + +------------------------------------------------- +; 24. Instantiating IP in a simulation project ; +------------------------------------------------- + + The simulation fileset as well as the simulation example design contain scripts + that illustrate what files are required when including the EMIF IP for simulation. + The scripts are customized for all the 3rd-party simulators supported. It is highly + recommended that you use these scripts as reference when setting up your simulation + environment. + + +------------------------------------------------------------ +; 25. Full-calibration versus skip-calibration simulation ; +------------------------------------------------------------ + + During generation, you can specify the default RTL simulation behavior for PHY calibration. + If you specify full-calibration simulation, the simulation time can take a very long time + because all the stages and the detailed behavior of PHY calibration are simulated. If you + specify skip-calibration simulation, the detailed behavior of PHY calibration is not + simulated. Skip-calibration simulation is recommended unless you suspect a functional + issue with the PHY calibration algorithm. Note however, that RTL simulation is a zero-delay + simulation, and so timing-related calibration failures on hardware do not manifest themselves + during RTL simulations. + + The setting that controls the calibration mode is encoded within the *_seq_params_sim.hex file + and the *_seq_params_synth.hex file. When the IP is compiled under the Quartus Prime software, + synthesis-directive causes the *_seq_params_synth.hex file to always be used. Outside of the + Quartus Prime software (e.g. 3rd-party simulator), the *_seq_params_sim.hex file is always used. + The behavior is the same regardless of which fileset is being synthesized or simulated. + The calibration mode setting specified during generation only affects the *_seq_params_sim.hex + file. The *_seq_params_synth.hex file always specifies full-calibration since full calibration + is key to functional hardware. + The RTL simulation behavior of the current IP is "Skip Calibration" + + +-------------------- +; 26. IP Settings ; +-------------------- + + SYS_INFO_DEVICE_FAMILY : Agilex 7 + SYS_INFO_DEVICE : AGFB014R24B2E2V + SYS_INFO_DEVICE_SPEEDGRADE : 2 + SYS_INFO_DEVICE_TEMPERATURE_GRADE : EXTENDED + SYS_INFO_DEVICE_POWER_MODEL : STANDARD_POWER + SYS_INFO_DEVICE_DIE_REVISIONS : HSSI_WHR_REVA HSSI_CRETE3_REVA MAIN_FM6_REVB + FAMILY_ENUM : FAMILY_AGILEX + TRAIT_SUPPORTS_VID : 1 + TRAIT_IOBANK_REVISION : IO96A_REVB2 + PROTOCOL_ENUM : PROTOCOL_DDR4 + IS_ED_SLAVE : false + INTERNAL_TESTING_MODE : false + CAL_DEBUG_CLOCK_FREQUENCY : 50000000 + SYS_INFO_UNIQUE_ID : ed_synth_emif_fm_0_emif_fm_0 + PREV_PROTOCOL_ENUM : PROTOCOL_DDR4 + PHY_FPGA_SPEEDGRADE_GUI : E2V (ES3) - change device under 'View'->'Device Family' + PHY_TARGET_SPEEDGRADE : E2V + PHY_TARGET_IS_ES : false + PHY_TARGET_IS_ES2 : false + PHY_TARGET_IS_ES3 : true + PHY_TARGET_IS_PRODUCTION : false + PHY_CONFIG_ENUM : CONFIG_PHY_AND_HARD_CTRL + PHY_PING_PONG_EN : false + PHY_CLAMSHELL_EN : false + PHY_RATE_ENUM : RATE_QUARTER + PHY_MEM_CLK_FREQ_MHZ : 1200.0 + PHY_REF_CLK_FREQ_MHZ : 33.333 + PHY_REF_CLK_JITTER_PS : 10.0 + PHY_DLL_CORE_UPDN_EN : false + PHY_CORE_CLKS_SHARING_ENUM : CORE_CLKS_SHARING_DISABLED + PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT : false + PHY_CALIBRATED_OCT : true + PHY_AC_CALIBRATED_OCT : true + PHY_CK_CALIBRATED_OCT : true + PHY_DATA_CALIBRATED_OCT : true + PHY_RZQ : 240 + PHY_HPS_ENABLE_EARLY_RELEASE : false + PHY_USER_PERIODIC_OCT_RECAL_ENUM : PERIODIC_OCT_RECAL_AUTO + PHY_AC_IO_STD_ENUM : IO_STD_SSTL_12 + PHY_CK_IO_STD_ENUM : IO_STD_SSTL_12 + PHY_DATA_IO_STD_ENUM : IO_STD_POD_12 + PHY_AC_MODE_ENUM : OUT_OCT_40_CAL + PHY_CK_MODE_ENUM : OUT_OCT_40_CAL + PHY_AC_DEEMPHASIS_ENUM : DEEMPHASIS_MODE_OFF + PHY_CK_DEEMPHASIS_ENUM : DEEMPHASIS_MODE_OFF + PHY_DATA_OUT_DEEMPHASIS_ENUM : DEEMPHASIS_MODE_HIGH + PHY_DATA_OUT_SLEW_RATE_ENUM : + PHY_DATA_OUT_MODE_ENUM : OUT_OCT_40_CAL + PHY_MIMIC_HPS_EMIF : false + PLL_ADD_EXTRA_CLKS : false + PLL_USER_NUM_OF_EXTRA_CLKS : 0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 : 50.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 : 0.0 + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 : 0.0 + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 : ps + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 : 0.0 + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 : 50.0 + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 : 50.0 + PLL_VCO_CLK_FREQ_MHZ : 1200.0 + PLL_NUM_OF_EXTRA_CLKS : 0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 : 0.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 : 1200.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 : 1200.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 : 1200.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 : 0.0 + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 : 1200.0 + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 : 0.0 + PHY_DDR4_CONFIG_ENUM : CONFIG_PHY_AND_HARD_CTRL + PHY_DDR4_USER_PING_PONG_EN : false + PHY_DDR4_USER_CLAMSHELL_EN : false + PHY_DDR4_USER_DLL_CORE_UPDN_EN : true + PHY_DDR4_MEM_CLK_FREQ_MHZ : 1200.0 + PHY_DDR4_DEFAULT_REF_CLK_FREQ : false + PHY_DDR4_USER_REF_CLK_FREQ_MHZ : 33.333 + PHY_DDR4_REF_CLK_JITTER_PS : 10.0 + PHY_DDR4_RATE_ENUM : RATE_QUARTER + PHY_DDR4_CORE_CLKS_SHARING_ENUM : CORE_CLKS_SHARING_DISABLED + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT : false + PHY_DDR4_IO_VOLTAGE : 1.2 + PHY_DDR4_DEFAULT_IO : false + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE : false + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM : PERIODIC_OCT_RECAL_AUTO + PHY_DDR4_MIMIC_HPS_EMIF : false + PHY_DDR4_ALLOW_72_DQ_WIDTH : false + PHY_DDR4_REF_CLK_FREQ_MHZ : 33.333 + PHY_DDR4_PING_PONG_EN : false + PHY_DDR4_CLAMSHELL_EN : false + PHY_DDR4_USER_AC_IO_STD_ENUM : IO_STD_SSTL_12 + PHY_DDR4_USER_AC_MODE_ENUM : OUT_OCT_40_CAL + PHY_DDR4_USER_AC_SLEW_RATE_ENUM : unset + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM : unset + PHY_DDR4_USER_CK_IO_STD_ENUM : IO_STD_SSTL_12 + PHY_DDR4_USER_CK_MODE_ENUM : OUT_OCT_40_CAL + PHY_DDR4_USER_CK_SLEW_RATE_ENUM : unset + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM : unset + PHY_DDR4_USER_DATA_IO_STD_ENUM : IO_STD_POD_12 + PHY_DDR4_USER_DATA_OUT_MODE_ENUM : OUT_OCT_40_CAL + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM : unset + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM : unset + PHY_DDR4_USER_DATA_IN_MODE_ENUM : IN_OCT_60_CAL + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN : true + PHY_DDR4_USER_STARTING_VREFIN : 70.0 + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM : IO_STD_TRUE_DIFF_SIGNALING + PHY_DDR4_USER_RZQ_IO_STD_ENUM : IO_STD_CMOS_12 + PHY_DDR4_AC_IO_STD_ENUM : IO_STD_SSTL_12 + PHY_DDR4_AC_MODE_ENUM : OUT_OCT_40_CAL + PHY_DDR4_AC_SLEW_RATE_ENUM : SLEW_RATE_FM_FAST + PHY_DDR4_AC_DEEMPHASIS_ENUM : DEEMPHASIS_MODE_OFF + PHY_DDR4_CK_IO_STD_ENUM : IO_STD_SSTL_12 + PHY_DDR4_CK_MODE_ENUM : OUT_OCT_40_CAL + PHY_DDR4_CK_SLEW_RATE_ENUM : SLEW_RATE_FM_FAST + PHY_DDR4_CK_DEEMPHASIS_ENUM : DEEMPHASIS_MODE_OFF + PHY_DDR4_DATA_IO_STD_ENUM : IO_STD_POD_12 + PHY_DDR4_DATA_OUT_MODE_ENUM : OUT_OCT_40_CAL + PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM : SLEW_RATE_FM_FAST + PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM : DEEMPHASIS_MODE_HIGH + PHY_DDR4_DATA_IN_MODE_ENUM : IN_OCT_60_CAL + PHY_DDR4_AUTO_STARTING_VREFIN_EN : true + PHY_DDR4_STARTING_VREFIN : 68.0 + PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM : IO_STD_TRUE_DIFF_SIGNALING + PHY_DDR4_RZQ_IO_STD_ENUM : IO_STD_CMOS_12 + MEM_FORMAT_ENUM : MEM_FORMAT_RDIMM + MEM_READ_LATENCY : 23.0 + MEM_WRITE_LATENCY : 18 + MEM_BURST_LENGTH : 8 + MEM_DATA_MASK_EN : true + MEM_HAS_SIM_SUPPORT : true + MEM_HAS_BSI_SUPPORT : true + MEM_NUM_OF_PHYSICAL_RANKS : 1 + MEM_NUM_OF_LOGICAL_RANKS : 1 + MEM_NUM_OF_DATA_ENDPOINTS : 1 + MEM_TTL_DATA_WIDTH : 72 + MEM_TTL_NUM_OF_READ_GROUPS : 9 + MEM_TTL_NUM_OF_WRITE_GROUPS : 9 + MEM_DDR4_FORMAT_ENUM : MEM_FORMAT_RDIMM + MEM_DDR4_DQ_WIDTH : 72 + MEM_DDR4_DQ_PER_DQS : 8 + MEM_DDR4_DISCRETE_CS_WIDTH : 1 + MEM_DDR4_NUM_OF_DIMMS : 1 + MEM_DDR4_CHIP_ID_WIDTH : 0 + MEM_DDR4_RANKS_PER_DIMM : 1 + MEM_DDR4_CKE_PER_DIMM : 1 + MEM_DDR4_CK_WIDTH : 1 + MEM_DDR4_ROW_ADDR_WIDTH : 16 + MEM_DDR4_COL_ADDR_WIDTH : 10 + MEM_DDR4_BANK_ADDR_WIDTH : 2 + MEM_DDR4_BANK_GROUP_WIDTH : 2 + MEM_DDR4_DM_EN : true + MEM_DDR4_ALERT_PAR_EN : true + MEM_DDR4_ALERT_N_PLACEMENT_ENUM : DDR4_ALERT_N_PLACEMENT_FM_LANE3 + MEM_DDR4_ALERT_N_DQS_GROUP : 0 + MEM_DDR4_ALERT_N_AC_LANE : 3 + MEM_DDR4_ALERT_N_AC_PIN : 8 + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN : false + MEM_DDR4_MIRROR_ADDRESSING_EN : true + MEM_DDR4_HIDE_ADV_MR_SETTINGS : true + MEM_DDR4_INTEL_DEFAULT_TERM : true + MEM_DDR4_BL_ENUM : DDR4_BL_BL8 + MEM_DDR4_BT_ENUM : DDR4_BT_SEQUENTIAL + MEM_DDR4_TCL : 21 + MEM_DDR4_RTT_NOM_ENUM : DDR4_RTT_NOM_RZQ_4 + MEM_DDR4_DLL_EN : true + MEM_DDR4_ATCL_ENUM : DDR4_ATCL_DISABLED + MEM_DDR4_DRV_STR_ENUM : DDR4_DRV_STR_RZQ_7 + MEM_DDR4_ASR_ENUM : DDR4_ASR_MANUAL_NORMAL + MEM_DDR4_RTT_WR_ENUM : DDR4_RTT_WR_ODT_DISABLED + MEM_DDR4_WTCL : 16 + MEM_DDR4_WRITE_CRC : false + MEM_DDR4_GEARDOWN : DDR4_GEARDOWN_HR + MEM_DDR4_PER_DRAM_ADDR : false + MEM_DDR4_TEMP_SENSOR_READOUT : false + MEM_DDR4_FINE_GRANULARITY_REFRESH : DDR4_FINE_REFRESH_FIXED_1X + MEM_DDR4_MPR_READ_FORMAT : DDR4_MPR_READ_FORMAT_SERIAL + MEM_DDR4_MAX_POWERDOWN : false + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE : DDR4_TEMP_CONTROLLED_RFSH_NORMAL + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA : false + MEM_DDR4_INTERNAL_VREFDQ_MONITOR : false + MEM_DDR4_CAL_MODE : 0 + MEM_DDR4_SELF_RFSH_ABORT : false + MEM_DDR4_READ_PREAMBLE_TRAINING : false + MEM_DDR4_READ_PREAMBLE : 2 + MEM_DDR4_WRITE_PREAMBLE : 1 + MEM_DDR4_AC_PARITY_LATENCY : DDR4_AC_PARITY_LATENCY_DISABLE + MEM_DDR4_ODT_IN_POWERDOWN : true + MEM_DDR4_RTT_PARK : DDR4_RTT_PARK_ODT_DISABLED + MEM_DDR4_AC_PERSISTENT_ERROR : false + MEM_DDR4_WRITE_DBI : false + MEM_DDR4_READ_DBI : true + MEM_DDR4_DEFAULT_VREFOUT : true + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE : 56.0 + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE : DDR4_VREFDQ_TRAINING_RANGE_1 + MEM_DDR4_RCD_CA_IBT_ENUM : DDR4_RCD_CA_IBT_100 + MEM_DDR4_RCD_CS_IBT_ENUM : DDR4_RCD_CS_IBT_100 + MEM_DDR4_RCD_CKE_IBT_ENUM : DDR4_RCD_CKE_IBT_100 + MEM_DDR4_RCD_ODT_IBT_ENUM : DDR4_RCD_ODT_IBT_100 + MEM_DDR4_DB_RTT_NOM_ENUM : DDR4_DB_RTT_NOM_ODT_DISABLED + MEM_DDR4_DB_RTT_WR_ENUM : DDR4_DB_RTT_WR_RZQ_3 + MEM_DDR4_DB_RTT_PARK_ENUM : DDR4_DB_RTT_PARK_ODT_DISABLED + MEM_DDR4_DB_DQ_DRV_ENUM : DDR4_DB_DRV_STR_RZQ_7 + MEM_DDR4_SPD_137_RCD_CA_DRV : 101 + MEM_DDR4_SPD_138_RCD_CK_DRV : 5 + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 : 29 + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 : 29 + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 : 29 + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 : 29 + MEM_DDR4_SPD_144_DB_VREFDQ : 37 + MEM_DDR4_SPD_145_DB_MDQ_DRV : 21 + MEM_DDR4_SPD_148_DRAM_DRV : 0 + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM : 20 + MEM_DDR4_SPD_152_DRAM_RTT_PARK : 39 + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE : 0 + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB : 0 + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB : 0 + MEM_DDR4_SPD_135_RCD_REV : 0 + MEM_DDR4_SPD_139_DB_REV : 0 + MEM_DDR4_LRDIMM_ODT_LESS_BS : true + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM : 240 + MEM_DDR4_DQS_WIDTH : 9 + MEM_DDR4_CS_WIDTH : 1 + MEM_DDR4_CS_PER_DIMM : 1 + MEM_DDR4_CKE_WIDTH : 1 + MEM_DDR4_ODT_WIDTH : 1 + MEM_DDR4_ADDR_WIDTH : 17 + MEM_DDR4_RM_WIDTH : 0 + MEM_DDR4_NUM_OF_PHYSICAL_RANKS : 1 + MEM_DDR4_NUM_OF_LOGICAL_RANKS : 1 + MEM_DDR4_IDEAL_VREF_IN_PCT : 68.0 + MEM_DDR4_IDEAL_VREF_OUT_PCT : 70.0 + MEM_DDR4_VREFDQ_TRAINING_VALUE : 70.0 + MEM_DDR4_VREFDQ_TRAINING_RANGE : DDR4_VREFDQ_TRAINING_RANGE_0 + MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP : Range 1 - 60% to 92.5% + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM : DDR4_DRV_STR_RZQ_7 + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM : DDR4_RTT_WR_ODT_DISABLED + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM : DDR4_RTT_NOM_ODT_DISABLED + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM : DDR4_RTT_PARK_RZQ_4 + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP : RZQ/7 (34 Ohm) + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP : Dynamic ODT off + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP : ODT Disabled + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP : RZQ/4 (60 Ohm) + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM : DDR4_DB_RTT_NOM_ODT_DISABLED + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM : DDR4_DB_RTT_WR_RZQ_3 + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM : DDR4_DB_RTT_PARK_ODT_DISABLED + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM : DDR4_DB_DRV_STR_RZQ_7 + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP : RTT_NOM disabled + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP : RZQ/3 (80 Ohm) + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP : RTT_PARK disabled + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP : RZQ/7 (34 Ohm) + MEM_DDR4_TTL_DQS_WIDTH : 9 + MEM_DDR4_TTL_DQ_WIDTH : 72 + MEM_DDR4_TTL_CS_WIDTH : 1 + MEM_DDR4_TTL_CK_WIDTH : 1 + MEM_DDR4_TTL_CKE_WIDTH : 1 + MEM_DDR4_TTL_ODT_WIDTH : 1 + MEM_DDR4_TTL_BANK_ADDR_WIDTH : 2 + MEM_DDR4_TTL_BANK_GROUP_WIDTH : 2 + MEM_DDR4_TTL_CHIP_ID_WIDTH : 0 + MEM_DDR4_TTL_ADDR_WIDTH : 17 + MEM_DDR4_TTL_RM_WIDTH : 0 + MEM_DDR4_TTL_NUM_OF_DIMMS : 1 + MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS : 1 + MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS : 1 + MEM_DDR4_MR0 : 0x874 + MEM_DDR4_MR1 : 0x10001 + MEM_DDR4_MR2 : 0x20028 + MEM_DDR4_MR3 : 0x30400 + MEM_DDR4_MR4 : 0x40800 + MEM_DDR4_MR5 : 0x51460 + MEM_DDR4_MR6 : 0x6080f + MEM_DDR4_RDIMM_CONFIG : 00000020000000003900000D40030B0F556000 + MEM_DDR4_LRDIMM_EXTENDED_CONFIG : + MEM_DDR4_ADDRESS_MIRROR_BITVEC : 0 + MEM_DDR4_RCD_PARITY_CONTROL_WORD : 13 + MEM_DDR4_RCD_COMMAND_LATENCY : 1 + MEM_DDR4_USE_DEFAULT_ODT : true + MEM_DDR4_R_ODTN_1X1 : {Rank 0} + MEM_DDR4_R_ODT0_1X1 : off + MEM_DDR4_W_ODTN_1X1 : {Rank 0} + MEM_DDR4_W_ODT0_1X1 : on + MEM_DDR4_R_ODTN_2X2 : {Rank 0} {Rank 1} + MEM_DDR4_R_ODT0_2X2 : off off + MEM_DDR4_R_ODT1_2X2 : off off + MEM_DDR4_W_ODTN_2X2 : {Rank 0} {Rank 1} + MEM_DDR4_W_ODT0_2X2 : on off + MEM_DDR4_W_ODT1_2X2 : off on + MEM_DDR4_R_ODTN_4X2 : {Rank 0} {Rank 1} {Rank 2} {Rank 3} + MEM_DDR4_R_ODT0_4X2 : off off on on + MEM_DDR4_R_ODT1_4X2 : on on off off + MEM_DDR4_W_ODTN_4X2 : {Rank 0} {Rank 1} {Rank 2} {Rank 3} + MEM_DDR4_W_ODT0_4X2 : off off on on + MEM_DDR4_W_ODT1_4X2 : on on off off + MEM_DDR4_R_ODTN_4X4 : {Rank 0} {Rank 1} {Rank 2} {Rank 3} + MEM_DDR4_R_ODT0_4X4 : off off on off + MEM_DDR4_R_ODT1_4X4 : off off off on + MEM_DDR4_R_ODT2_4X4 : on off off off + MEM_DDR4_R_ODT3_4X4 : off on off off + MEM_DDR4_W_ODTN_4X4 : {Rank 0} {Rank 1} {Rank 2} {Rank 3} + MEM_DDR4_W_ODT0_4X4 : on off on off + MEM_DDR4_W_ODT1_4X4 : off on off on + MEM_DDR4_W_ODT2_4X4 : on off on off + MEM_DDR4_W_ODT3_4X4 : off on off on + MEM_DDR4_R_DERIVED_ODTN : {Rank 0} - - - + MEM_DDR4_R_DERIVED_ODT0 : {(Drive) RZQ/7 (34 Ohm)} - - - + MEM_DDR4_R_DERIVED_ODT1 : - - - - + MEM_DDR4_R_DERIVED_ODT2 : - - - - + MEM_DDR4_R_DERIVED_ODT3 : - - - - + MEM_DDR4_R_DERIVED_BODTN : + MEM_DDR4_R_DERIVED_BODT0 : + MEM_DDR4_R_DERIVED_BODT1 : + MEM_DDR4_W_DERIVED_ODTN : {Rank 0} - - - + MEM_DDR4_W_DERIVED_ODT0 : {(Park) RZQ/4 (60 Ohm)} - - - + MEM_DDR4_W_DERIVED_ODT1 : - - - - + MEM_DDR4_W_DERIVED_ODT2 : - - - - + MEM_DDR4_W_DERIVED_ODT3 : - - - - + MEM_DDR4_W_DERIVED_BODTN : + MEM_DDR4_W_DERIVED_BODT0 : + MEM_DDR4_W_DERIVED_BODT1 : + MEM_DDR4_SEQ_ODT_TABLE_LO : 0 + MEM_DDR4_SEQ_ODT_TABLE_HI : 0 + MEM_DDR4_CTRL_CFG_READ_ODT_CHIP : 0 + MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP : 0 + MEM_DDR4_CTRL_CFG_READ_ODT_RANK : 0 + MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK : 0 + MEM_DDR4_SPEEDBIN_ENUM : DDR4_SPEEDBIN_2666 + MEM_DDR4_TIS_PS : 62 + MEM_DDR4_TIS_AC_MV : 100 + MEM_DDR4_TIH_PS : 87 + MEM_DDR4_TIH_DC_MV : 75 + MEM_DDR4_TDIVW_TOTAL_UI : 0.2 + MEM_DDR4_VDIVW_TOTAL : 130 + MEM_DDR4_TDQSQ_UI : 0.14 + MEM_DDR4_TQH_UI : 0.74 + MEM_DDR4_TDVWP_UI : 0.72 + MEM_DDR4_TDQSCK_PS : 175 + MEM_DDR4_TDQSS_CYC : 0.27 + MEM_DDR4_TQSH_CYC : 0.4 + MEM_DDR4_TDSH_CYC : 0.18 + MEM_DDR4_TDSS_CYC : 0.18 + MEM_DDR4_TWLS_CYC : 0.13 + MEM_DDR4_TWLH_CYC : 0.13 + MEM_DDR4_TINIT_US : 500 + MEM_DDR4_TMRD_CK_CYC : 8 + MEM_DDR4_TRAS_NS : 32.0 + MEM_DDR4_TRCD_NS : 14.16 + MEM_DDR4_TRP_NS : 14.16 + MEM_DDR4_TREFI_US : 7.8 + MEM_DDR4_TRFC_NS : 350.0 + MEM_DDR4_TWR_NS : 15.0 + MEM_DDR4_TWTR_L_CYC : 9 + MEM_DDR4_TWTR_S_CYC : 3 + MEM_DDR4_TFAW_NS : 21.0 + MEM_DDR4_TRRD_L_CYC : 6 + MEM_DDR4_TRRD_S_CYC : 4 + MEM_DDR4_TCCD_L_CYC : 6 + MEM_DDR4_TCCD_S_CYC : 4 + MEM_DDR4_TRFC_DLR_NS : 90.0 + MEM_DDR4_TFAW_DLR_CYC : 16 + MEM_DDR4_TRRD_DLR_CYC : 4 + MEM_DDR4_TDIVW_DJ_CYC : 0.1 + MEM_DDR4_TDQSQ_PS : 66 + MEM_DDR4_TQH_CYC : 0.38 + MEM_DDR4_TINIT_CK : 600000 + MEM_DDR4_TDQSCK_DERV_PS : 2 + MEM_DDR4_TDQSCKDS : 450 + MEM_DDR4_TDQSCKDM : 900 + MEM_DDR4_TDQSCKDL : 1200 + MEM_DDR4_TRAS_CYC : 39 + MEM_DDR4_TRCD_CYC : 17 + MEM_DDR4_TRP_CYC : 17 + MEM_DDR4_TRFC_CYC : 420 + MEM_DDR4_TWR_CYC : 18 + MEM_DDR4_TRTP_CYC : 9 + MEM_DDR4_TFAW_CYC : 26 + MEM_DDR4_TREFI_CYC : 9360 + MEM_DDR4_WRITE_CMD_LATENCY : 6 + MEM_DDR4_TRFC_DLR_CYC : 108 + MEM_DDR4_CFG_GEN_SBE : false + MEM_DDR4_CFG_GEN_DBE : false + MEM_DDR4_LRDIMM_VREFDQ_VALUE : + MEM_DDR4_TWLS_PS : 0.0 + MEM_DDR4_TWLH_PS : 0.0 + BOARD_DDR4_USE_DEFAULT_SLEW_RATES : true + BOARD_DDR4_USE_DEFAULT_ISI_VALUES : true + BOARD_DDR4_USER_CK_SLEW_RATE : 4.0 + BOARD_DDR4_USER_AC_SLEW_RATE : 2.0 + BOARD_DDR4_USER_RCLK_SLEW_RATE : 8.0 + BOARD_DDR4_USER_WCLK_SLEW_RATE : 4.0 + BOARD_DDR4_USER_RDATA_SLEW_RATE : 4.0 + BOARD_DDR4_USER_WDATA_SLEW_RATE : 2.0 + BOARD_DDR4_USER_AC_ISI_NS : 0.0 + BOARD_DDR4_USER_RCLK_ISI_NS : 0.0 + BOARD_DDR4_USER_WCLK_ISI_NS : 0.0 + BOARD_DDR4_USER_RDATA_ISI_NS : 0.0 + BOARD_DDR4_USER_WDATA_ISI_NS : 0.0 + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED : true + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS : 0.02 + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS : 0.02 + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED : false + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS : 0.02 + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS : 0.02 + BOARD_DDR4_DQS_TO_CK_SKEW_NS : 0.02 + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS : 0.05 + BOARD_DDR4_SKEW_BETWEEN_DQS_NS : 0.02 + BOARD_DDR4_AC_TO_CK_SKEW_NS : 0.0 + BOARD_DDR4_MAX_CK_DELAY_NS : 0.6 + BOARD_DDR4_MAX_DQS_DELAY_NS : 0.6 + BOARD_DDR4_TIS_DERATING_PS : 0 + BOARD_DDR4_TIH_DERATING_PS : 0 + BOARD_DDR4_CK_SLEW_RATE : 4.0 + BOARD_DDR4_AC_SLEW_RATE : 2.0 + BOARD_DDR4_RCLK_SLEW_RATE : 8.0 + BOARD_DDR4_WCLK_SLEW_RATE : 4.0 + BOARD_DDR4_RDATA_SLEW_RATE : 4.0 + BOARD_DDR4_WDATA_SLEW_RATE : 2.0 + BOARD_DDR4_AC_ISI_NS : 0.15 + BOARD_DDR4_RCLK_ISI_NS : 0.15 + BOARD_DDR4_WCLK_ISI_NS : 0.06 + BOARD_DDR4_RDATA_ISI_NS : 0.12 + BOARD_DDR4_WDATA_ISI_NS : 0.13 + BOARD_DDR4_SKEW_WITHIN_DQS_NS : 0.02 + BOARD_DDR4_SKEW_WITHIN_AC_NS : 0.18 + CTRL_ECC_EN : true + CTRL_MMR_EN : false + CTRL_AUTO_PRECHARGE_EN : false + CTRL_USER_PRIORITY_EN : false + CTRL_REORDER_EN : true + CTRL_ECC_READDATAERROR_EN : false + CTRL_ECC_STATUS_EN : false + CTRL_DDR4_AVL_PROTOCOL_ENUM : CTRL_AVL_PROTOCOL_MM + CTRL_DDR4_SELF_REFRESH_EN : false + CTRL_DDR4_AUTO_POWER_DOWN_EN : false + CTRL_DDR4_AUTO_POWER_DOWN_CYCS : 32 + CTRL_DDR4_USER_REFRESH_EN : false + CTRL_DDR4_USER_PRIORITY_EN : false + CTRL_DDR4_AUTO_PRECHARGE_EN : false + CTRL_DDR4_ADDR_ORDER_ENUM : DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + CTRL_DDR4_ECC_EN : true + CTRL_DDR4_ECC_AUTO_CORRECTION_EN : false + CTRL_DDR4_ECC_READDATAERROR_EN : false + CTRL_DDR4_ECC_STATUS_EN : false + CTRL_DDR4_REORDER_EN : true + CTRL_DDR4_STARVE_LIMIT : 10 + CTRL_DDR4_MMR_EN : false + CTRL_DDR4_MAJOR_MODE_EN : false + CTRL_DDR4_POST_REFRESH_EN : true + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT : 0 + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT : 2 + CTRL_DDR4_PRE_REFRESH_EN : false + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT : 1 + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS : 0 + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS : 0 + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS : 0 + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS : 0 + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS : 0 + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS : 0 + DIAG_SIM_REGTEST_MODE : false + DIAG_TIMING_REGTEST_MODE : false + DIAG_SYNTH_FOR_SIM : false + DIAG_FAST_SIM_OVERRIDE : FAST_SIM_OVERRIDE_DEFAULT + DIAG_SEQ_RESET_AUTO_RELEASE : avl + DIAG_DB_RESET_AUTO_RELEASE : avl_release + DIAG_ADD_READY_PIPELINE : true + DIAG_EXPOSE_EARLY_READY : false + DIAG_EXPOSE_RD_TYPE : false + DIAG_VERBOSE_IOAUX : false + DIAG_ECLIPSE_DEBUG : false + DIAG_EXPORT_VJI : false + DIAG_ENABLE_JTAG_UART : false + DIAG_ENABLE_JTAG_UART_HEX : false + DIAG_ENABLE_HPS_EMIF_DEBUG : false + DIAG_SOFT_NIOS_MODE : SOFT_NIOS_MODE_DISABLED + DIAG_SOFT_NIOS_CLOCK_FREQUENCY : 100 + DIAG_USE_RS232_UART : false + DIAG_RS232_UART_BAUDRATE : 57600 + DIAG_EX_DESIGN_ADD_TEST_EMIFS : + DIAG_EX_DESIGN_SEPARATE_RESETS : false + DIAG_EXPOSE_DFT_SIGNALS : false + DIAG_EXTRA_CONFIGS : + DIAG_USE_BOARD_DELAY_MODEL : false + DIAG_BOARD_DELAY_CONFIG_STR : + DIAG_TG_AVL_2_NUM_CFG_INTERFACES : 0 + DIAG_EXPORT_PLL_REF_CLK_OUT : false + DIAG_EXPORT_PLL_LOCKED : true + DIAG_HMC_HRC : auto + SHORT_QSYS_INTERFACE_NAMES : true + DIAG_EXT_DOCS : false + DIAG_SIM_CAL_MODE_ENUM : SIM_CAL_MODE_SKIP + DIAG_EXPORT_SEQ_AVALON_SLAVE : CAL_DEBUG_EXPORT_MODE_JTAG + DIAG_EXPORT_SEQ_AVALON_MASTER : false + DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN : true + DIAG_EX_DESIGN_NUM_OF_SLAVES : 1 + DIAG_EX_DESIGN_ISSP_EN : true + DIAG_INTERFACE_ID : 0 + DIAG_EFFICIENCY_MONITOR : EFFMON_MODE_DISABLED + DIAG_USE_NEW_EFFMON_S10 : false + DIAG_USE_ABSTRACT_PHY : false + DIAG_SIM_MEMORY_PRELOAD : false + DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE : + DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE : + DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE : + DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE : + DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE : + DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE : + DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE : + DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE : + DIAG_USE_SIM_MEMORY_VALIDATION_TG : false + DIAG_SIM_VERBOSE_LEVEL : 5 + DIAG_FAST_SIM : true + DIAG_USE_TG_AVL_2 : false + DIAG_TG2_TEST_DURATION : SHORT + DIAG_USE_TG_HBM : false + DIAG_EXPORT_TG_CFG_AVALON_SLAVE : TG_CFG_AMM_EXPORT_MODE_EXPORT + DIAG_ENABLE_DEFAULT_MODE : false + DIAG_ENABLE_USER_MODE : true + DIAG_ENABLE_SOFT_M20K : false + DIAG_SIM_CHECKER_SKIP_TG : false + DIAG_AC_PARITY_ERR : false + DIAG_DISABLE_AFI_P2C_REGISTERS : false + DIAG_EX_DESIGN_SEPARATE_RZQS : true + DIAG_DDR4_SIM_CAL_MODE_ENUM : SIM_CAL_MODE_SKIP + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE : CAL_DEBUG_EXPORT_MODE_JTAG + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER : false + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN : true + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES : 1 + DIAG_DDR4_EX_DESIGN_ISSP_EN : true + DIAG_DDR4_INTERFACE_ID : 0 + DIAG_DDR4_EFFICIENCY_MONITOR : EFFMON_MODE_DISABLED + DIAG_DDR4_USE_NEW_EFFMON_S10 : false + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD : false + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE : EMIF_PRI_PRELOAD.txt + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE : EMIF_SEC_PRELOAD.txt + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG : true + DIAG_DDR4_USE_TG_AVL_2 : false + DIAG_DDR4_USE_TG_HBM : false + DIAG_DDR4_ABSTRACT_PHY : false + DIAG_DDR4_ENABLE_DEFAULT_MODE : false + DIAG_DDR4_ENABLE_USER_MODE : true + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE : TG_CFG_AMM_EXPORT_MODE_EXPORT + DIAG_DDR4_TG2_TEST_DURATION : SHORT + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS : false + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS : false + DIAG_DDR4_AC_PARITY_ERR : false + DIAG_DDR4_SIM_MEMORY_PRELOAD : false + DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE : + DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE : + DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG : false + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS : true + DIAG_DDR4_SIM_VERBOSE : true + DIAG_DDR4_SKIP_CA_LEVEL : false + DIAG_DDR4_SKIP_CA_DESKEW : false + DIAG_DDR4_SKIP_VREF_CAL : false + DIAG_DDR4_SKIP_AC_PARITY_CHECK : false + DIAG_DDR4_CAL_ADDR0 : 0 + DIAG_DDR4_CAL_ADDR1 : 8 + DIAG_DDR4_CAL_ENABLE_NON_DES : false + DIAG_DDR4_CAL_FULL_CAL_ON_RESET : true + NUM_IPS : 1 + EMIF_0_CONN_TO_CALIP : CALIP_0 + EMIF_0_STORED_PARAM : + EMIF_0_REF_CLK_SHARING : EXPORTED + EMIF_1_CONN_TO_CALIP : CALIP_0 + EMIF_1_STORED_PARAM : + EMIF_1_REF_CLK_SHARING : EXPORTED + EMIF_2_CONN_TO_CALIP : CALIP_0 + EMIF_2_STORED_PARAM : + EMIF_2_REF_CLK_SHARING : EXPORTED + EMIF_3_CONN_TO_CALIP : CALIP_0 + EMIF_3_STORED_PARAM : + EMIF_3_REF_CLK_SHARING : EXPORTED + EMIF_4_CONN_TO_CALIP : CALIP_0 + EMIF_4_STORED_PARAM : + EMIF_4_REF_CLK_SHARING : EXPORTED + EMIF_5_CONN_TO_CALIP : CALIP_0 + EMIF_5_STORED_PARAM : + EMIF_5_REF_CLK_SHARING : EXPORTED + EMIF_6_CONN_TO_CALIP : CALIP_0 + EMIF_6_STORED_PARAM : + EMIF_6_REF_CLK_SHARING : EXPORTED + EMIF_7_CONN_TO_CALIP : CALIP_0 + EMIF_7_STORED_PARAM : + EMIF_7_REF_CLK_SHARING : EXPORTED + EMIF_8_CONN_TO_CALIP : CALIP_0 + EMIF_8_STORED_PARAM : + EMIF_8_REF_CLK_SHARING : EXPORTED + EMIF_9_CONN_TO_CALIP : CALIP_0 + EMIF_9_STORED_PARAM : + EMIF_9_REF_CLK_SHARING : EXPORTED + EMIF_10_CONN_TO_CALIP : CALIP_0 + EMIF_10_STORED_PARAM : + EMIF_10_REF_CLK_SHARING : EXPORTED + EMIF_11_CONN_TO_CALIP : CALIP_0 + EMIF_11_STORED_PARAM : + EMIF_11_REF_CLK_SHARING : EXPORTED + EMIF_12_CONN_TO_CALIP : CALIP_0 + EMIF_12_STORED_PARAM : + EMIF_12_REF_CLK_SHARING : EXPORTED + EMIF_13_CONN_TO_CALIP : CALIP_0 + EMIF_13_STORED_PARAM : + EMIF_13_REF_CLK_SHARING : EXPORTED + EMIF_14_CONN_TO_CALIP : CALIP_0 + EMIF_14_STORED_PARAM : + EMIF_14_REF_CLK_SHARING : EXPORTED + EMIF_15_CONN_TO_CALIP : CALIP_0 + EMIF_15_STORED_PARAM : + EMIF_15_REF_CLK_SHARING : EXPORTED + EX_DESIGN_GUI_GEN_SIM : true + EX_DESIGN_GUI_GEN_SYNTH : true + EX_DESIGN_GUI_GEN_BSI : false + EX_DESIGN_GUI_GEN_CDC : false + EX_DESIGN_GUI_TARGET_DEV_KIT : TARGET_DEV_KIT_NONE + NUM_IPS_SAVED : 0 + EX_DESIGN_GUI_PREV_PRESET : TARGET_DEV_KIT_NONE + EX_DESIGN_GUI_DDR4_SEL_DESIGN : AVAIL_EX_DESIGNS_GEN_DESIGN + EX_DESIGN_GUI_DDR4_GEN_SIM : true + EX_DESIGN_GUI_DDR4_GEN_SYNTH : true + EX_DESIGN_GUI_DDR4_GEN_BSI : false + EX_DESIGN_GUI_DDR4_GEN_CDC : false + EX_DESIGN_GUI_DDR4_HDL_FORMAT : HDL_FORMAT_VERILOG + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT : TARGET_DEV_KIT_NONE + EX_DESIGN_GUI_DDR4_PREV_PRESET : TARGET_DEV_KIT_NONE + + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_io_timing.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_io_timing.tcl new file mode 100644 index 0000000000..b3b43969e2 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_io_timing.tcl @@ -0,0 +1,221 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +#################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the routines to generate the early external memory +# interface timing report at the before the start of the compile flow. +# +# These routines are only meant to be used in this specific context. +# Trying to using them in a different context can have unexpected +# results. +# +# In performing the above timing analysis, the script +# calls procedures that are found in a separate file (report_timing_core.tcl) +# that has all the details of the timing analysis, and this +# file only serves as the top-level timing analysis flow. +# +# To reduce data lookups in all the procuedures that perform +# the individual timing analysis, data that is needed for +# multiple procedures is lookup up in this file and passed +# to the various parameters. These data include both values +# that are applicable over all operating conditions, and those +# that are applicable to only one operating condition. +# +############################################################# + +# Determin if only doing IO analysis +set ::io_only_analysis 1 + +############################################################# +# Initialize the environment / Error Checking +############################################################# + +if { ![info exists quartus(nameofexecutable)] || $quartus(nameofexecutable) != "quartus_sta" } { + post_message -type error "This script must be run from quartus_sta" + return 1 +} + +# Check the project +if { ! [ is_project_open ] } { + if { [ llength $quartus(args) ] > 0 } { + set project_name [lindex $quartus(args) 0] + project_open -revision [ get_current_revision $project_name ] $project_name + } else { + post_message -type error "Missing project_name argument" + return 1 + } +} + + +# Load the timing netlist if required +if { ! [timing_netlist_exist] } { + # In IO only flow, check to see if we could even create a timing nelist + # First try to see if we could even create a + catch {create_timing_netlist} create_timing_netlist_out + set create_timing_netlist_error [regexp "ERROR" $create_timing_netlist_out] + + # If create timing netlist cannot run, then the IO flow is a valid flow + if {$create_timing_netlist_error == 1} { + create_emif_netlist -revision $::quartus(project) + sta_create_empty_report + } else { + delete_timing_netlist + post_message -type error "Early EMIF IO timing estimate cannot be run once the Fitter has been run" + return 1 + } + +} else { + post_message -type error "Early EMIF IO timing estimate cannot be run once the Fitter has been run" + return 1 +} + +# Load the reports +load_package report +set current_timing_report_type [get_current_report_type] +if { [catch {load_report_database -type_name $current_timing_report_type} load_report_out ] } { + create_report_database -type_name $current_timing_report_type +} + +############################################################# +# Some useful functions +############################################################# +set script_dir [file dirname [info script]] +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl" + + +if [ info exists ddr_db ] { + unset ddr_db +} +ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_initialize_ddr_db ddr_db var + + +# If multiple instances of this core are present in the +# design they will all be analyzed through the +# following loop +set instances [ array names ddr_db ] +set inst_id 0 +foreach inst $instances { + + if { [ info exists pins ] } { + # Clean-up stale content + unset pins + } + array set pins $ddr_db($inst) + + ################################################################################# + # Find some design values and parameters that will used during the timing analysis + # that do not change accross the operating conditions + + set fname "" + set fbasename "" + if {[llength $instances] <= 1} { + set fbasename "${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename}" + } else { + set fbasename "${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename}_${inst_id}" + } + + ################################################################################# + # Now loop the timing analysis over the various operating conditions + set summary [list] + + set opcname "All conditions" + set opcname [string trim $opcname] + + ####################################### + # PHY Analyses + + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_perform_core_analysis $opcname $inst pins var summary + + ####################################### + # Print out the Summary Panel for this instance + + set summary [lsort -command ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_proc $summary] + + post_message -type info "Core: ${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename} - Instance: $inst" + post_message -type info " setup hold" + set panel_name "[get_report_folder -relative]||$inst" + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + # Create summary panel + set total_failures 0 + set rows [list] + lappend rows "add_row_to_table -id \$panel_id \[list \"Path\" \"Operating Condition\" \"Setup Slack\" \"Hold Slack\"\]" + foreach summary_line $summary { + foreach {corner order path su hold num_su num_hold} $summary_line { } + if {($num_su == 0) || ([string trim $su] == "")} { + set su "--" + } + if {($num_hold == 0) || ([string trim $hold] == "")} { + set hold "--" + } + + + if { ($su != "--" && $su < 0) || ($hold != "--" && $hold < 0) } { + incr total_failures + set type warning + set offset 50 + } else { + set type info + set offset 53 + } + if {$su != "--"} { + set su [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp $su] + } + if {$hold != "--"} { + set hold [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp $hold] + } + post_message -type $type [format "%-${offset}s | %6s %6s" $path $su $hold] + set fg_colours [list black black] + if { $su != "--" && $su < 0 } { + lappend fg_colours red + } else { + lappend fg_colours black + } + + if { $hold != "" && $hold < 0 } { + lappend fg_colours red + } else { + lappend fg_colours black + } + lappend rows "add_row_to_table -id \$panel_id -fcolors \"$fg_colours\" \[list \"$path\" \"$corner\" \"$su\" \"$hold\"\]" + } + if {$total_failures > 0} { + post_message -type critical_warning "DDR Timing requirements not met" + set panel_id [create_report_panel -table $panel_name -color red] + } else { + set panel_id [create_report_panel -table $panel_name] + } + foreach row $rows { + eval $row + } + + incr inst_id +} +# end foreach inst + + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing.tcl new file mode 100644 index 0000000000..a775dd45ba --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing.tcl @@ -0,0 +1,273 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +#################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the routines to generate the external memory +# interface timing report at the end of the compile flow. +# +# These routines are only meant to be used in this specific context. +# Trying to using them in a different context can have unexpected +# results. +# +# In performing the above timing analysis, the script +# calls procedures that are found in a separate file (report_timing_core.tcl) +# that has all the details of the timing analysis, and this +# file only serves as the top-level timing analysis flow. +# +# To reduce data lookups in all the procuedures that perform +# the individual timing analysis, data that is needed for +# multiple procedures is lookup up in this file and passed +# to the various parameters. These data include both values +# that are applicable over all operating conditions, and those +# that are applicable to only one operating condition. +# +############################################################# + +# Determine if only doing IO analysis +set ::io_only_analysis 0 + +############################################################# +# Initialize the environment / Error Checking +############################################################# + +proc get_speedgrade_from_opn {part} { + set temp_grade [get_part_info -temperature_grade $part] + set speed_grade [get_part_info -speed_grade $part] + set power_model [get_part_info -power_model $part] + + if {$temp_grade == "Extended"} { + set temp_grade "E" + } elseif {$temp_grade == "Industrial"} { + set temp_grade "I" + } elseif {$temp_grade == "Commercial"} { + set temp_grade "C" + } else { + set temp_grade [string index $part 12] + } + + if {$power_model == "{Standard Power}"} { + set power_model "V" + } elseif {$power_model == "{Lower Power}"} { + set power_model "E" + } elseif {$power_model == "{Extreme Low Power}"} { + set power_model "X" + } elseif {$power_model == "{Fixed Voltage}"} { + set power_model "F" + } else { + set power_model [string index $part 14] + } + + set retval $temp_grade + append retval $speed_grade + append retval $power_model + return $retval +} + +if { ![info exists quartus(nameofexecutable)] || $quartus(nameofexecutable) != "quartus_sta" } { + post_message -type error "This script must be run from quartus_sta" + return 1 +} + +# Check the project +if { ! [ is_project_open ] } { + if { [ llength $quartus(args) ] > 0 } { + set project_name [lindex $quartus(args) 0] + project_open -revision [ get_current_revision $project_name ] $project_name + } else { + post_message -type error "Missing project_name argument" + return 1 + } +} + + +# Load the timing netlist if required +if { ! [timing_netlist_exist] } { + create_timing_netlist + read_sdc + update_timing_netlist + + set script_dir [file dirname [info script]] + source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl" + source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl" + source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl" + source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl" + if { ! [timing_netlist_exist] } { + post_message -type error "Timing Netlist has not been created. Run the 'Update Timing Netlist' task first." + return 1 + } +} + + +# Load the atom netlist if required +load_package atoms +read_atom_netlist + +# Load the reports +load_package report +set current_timing_report_type [get_current_report_type] +load_report_database -type_name $current_timing_report_type + +############################################################# +# Some useful functions +############################################################# +set script_dir [file dirname [info script]] +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl" +source "$script_dir/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl" + +############################################### +# This is the main call to the netlist traversal routines +# that will automatically find all pins and registers required +# to timing analyze the Core. + +if [ info exists ddr_db ] { + unset ddr_db +} +ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_initialize_ddr_db ddr_db var + +set old_active_clocks [get_active_clocks] +set_active_clocks [all_clocks] + +# If multiple instances of this core are present in the +# design they will all be analyzed through the +# following loop +set instances [ array names ddr_db ] +set inst_id 0 +foreach inst $instances { + + if { [ info exists pins ] } { + # Clean-up stale content + unset pins + } + array set pins $ddr_db($inst) + + ################################################################################# + # Find some design values and parameters that will used during the timing analysis + # that do not change accross the operating conditions + + set fname "" + set fbasename "" + if {[llength $instances] <= 1} { + set fbasename "${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename}" + } else { + set fbasename "${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename}_${inst_id}" + } + + ################################################################################# + # Now loop the timing analysis over the various operating conditions + set summary [list] + + set opcname [get_operating_conditions_info [get_operating_conditions] -display_name] + set hold_only_corner [get_operating_conditions_info [get_operating_conditions] -is_hold_only] + set opcname [string trim $opcname] + + if {$hold_only_corner} { + set opcname "${opcname}, Hold Only" + } + + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_perform_core_analysis $opcname $inst pins var summary + + + set summary [lsort -command ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_proc $summary] + + post_message -type info "Core: ${::GLOBAL_ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_corename} - Instance: $inst" + post_message -type info " setup hold" + set panel_name "[get_report_folder -relative]||$inst" + # Delete any pre-existing summary panel + set panel_id [get_report_panel_id $panel_name] + if {$panel_id != -1} { + delete_report_panel -id $panel_id + } + + # Create summary panel + set total_failures 0 + set rows [list] + lappend rows "add_row_to_table -id \$panel_id \[list \"Path\" \"Operating Condition\" \"Setup Slack\" \"Hold Slack\"\]" + foreach summary_line $summary { + foreach {corner order path su hold num_su num_hold} $summary_line { } + if {($num_su == 0) || ([string trim $su] == "")} { + set su "--" + } + if {($num_hold == 0) || ([string trim $hold] == "")} { + set hold "--" + } + + set type info + set offset 59 + + if { ($su != "--" && $su < 0) || ($hold != "--" && $hold < 0) } { + incr total_failures + } + if {$su != "--"} { + set su [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp $su] + } + if {$hold != "--"} { + set hold [ ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp $hold] + } + post_message -type $type [format "%-${offset}s | %6s %6s" $path $su $hold] + set fg_colours [list black black] + if { $su != "--" && $su < 0 } { + lappend fg_colours red + } else { + lappend fg_colours black + } + + if { $hold != "" && $hold < 0 } { + lappend fg_colours red + } else { + lappend fg_colours black + } + lappend rows "add_row_to_table -id \$panel_id -fcolors \"$fg_colours\" \[list \"$path\" \"$corner\" \"$su\" \"$hold\"\]" + } + if {$total_failures > 0} { + post_message -type critical_warning "DDR Timing requirements not met" + set panel_id [create_report_panel -table $panel_name -color red] + } else { + set panel_id [create_report_panel -table $panel_name] + } + foreach row $rows { + eval $row + } + + incr inst_id +} +# end foreach inst + + +set_active_clocks $old_active_clocks + +set curr_part $::TimeQuestInfo(part) +set curr_speedgrade [get_speedgrade_from_opn $curr_part] + +if {![test_part_trait_of $curr_part -trait FINAL_TIMING_MODEL]} { + post_message -type critical_warning "Timing analysis was performed using a non-final timing model and/or constraints. You must regenerate the external memory interface IP and recheck timing closure in a future version of Quartus Prime." +} + +if {$var(PHY_TARGET_SPEEDGRADE) == ""} { + set effective_target_speedgrade "E1" +} else { + set effective_target_speedgrade $var(PHY_TARGET_SPEEDGRADE) +} + +if {$curr_speedgrade != $effective_target_speedgrade} { + post_message -type critical_warning "This External Memory Interface IP core was generated for a speed grade $effective_target_speedgrade device, but the speed grade of $curr_part is $curr_speedgrade. You should regenerate the IP core to match the target device to avoid hardware issue." +} diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl new file mode 100644 index 0000000000..e08f659c8b --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl @@ -0,0 +1,257 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + + + +################################################################ +# Helper function to add a report_timing-based analysis section +################################################################ +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_report_timing_analysis {opcname inst var_array_name summary_name title from_clks to_clks from_nodes to_nodes } { + + ####################################### + # Need access to global variables + upvar 1 $summary_name global_summary + upvar 1 $var_array_name var + + set num_failing_path 10 + + set setup_margin 999.9 + set hold_margin 999.9 + set recovery_margin 999.9 + set removal_margin 999.9 + + set hold_only_corner [get_operating_conditions_info [get_operating_conditions] -is_hold_only] + + if {!$hold_only_corner && ([get_collection_size [get_timing_paths -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths 1 -setup]] > 0)} { + set res_0 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name "$inst $title (setup)" -setup] + set setup_margin [lindex $res_0 1] + } else { + set setup_margin "--" + } + + if {[get_collection_size [get_timing_paths -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths 1 -hold]] > 0} { + set res_1 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name "$inst $title (hold)" -hold] + set hold_margin [lindex $res_1 1] + } + + if {$var(DIAG_TIMING_REGTEST_MODE)} { + lappend global_summary [list $opcname 0 "$title ($opcname)" $setup_margin $hold_margin] + } + + if {!$hold_only_corner && ([get_collection_size [get_timing_paths -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths 1 -recovery]] > 0)} { + set res_0 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name "$inst $title (recovery)" -recovery] + set recovery_margin [lindex $res_0 1] + } else { + set recovery_margin "--" + } + + if {[get_collection_size [get_timing_paths -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths 1 -removal]] > 0} { + set res_1 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name "$inst $title (removal)" -removal] + set removal_margin [lindex $res_1 1] + } else { + set removal_margin "--" + } + + if {$var(DIAG_TIMING_REGTEST_MODE)} { + lappend global_summary [list $opcname 0 "$title Recovery/Removal ($opcname)" $recovery_margin $removal_margin] + } + + return [list $setup_margin $hold_margin $recovery_margin $removal_margin] +} + +############################################################# +# Other Core-Logic related Timing Analysis +############################################################# + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_c2p_p2c_report_timing_analysis {opcname inst pin_array_name var_array_name summary_name title from_clks to_clks from_nodes to_nodes p2c} { + + ####################################### + # Need access to global variables + upvar 1 $summary_name global_summary + upvar 1 $var_array_name var + upvar 1 $pin_array_name pins + + set num_failing_path 10 + + set setup_margin 999.9 + set hold_margin 999.9 + set recovery_margin 999.9 + set removal_margin 999.9 + set debug 0 + + set hold_only_corner [get_operating_conditions_info [get_operating_conditions] -is_hold_only] + + set positive_fcolour [list "black" "blue" "blue"] + set negative_fcolour [list "black" "red" "red"] + set summary [list] + + # Get the periphery clocks + if {$p2c} { + set phyclks $from_clks + } else { + set phyclks $to_clks + } + + # Set panel names + set panel_name_setup "$inst $title (setup)" + set panel_name_hold "$inst $title (hold)" + set panel_name_recovery "$inst $title (recovery)" + set panel_name_removal "$inst $title (removal)" + set disable_panel_color_flag "" + set quiet_flag "" + + # Generate the default margins + if {!$hold_only_corner} { + set res_0 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name $panel_name_setup -setup $disable_panel_color_flag $quiet_flag] + set setup_margin [lindex $res_0 1] + } else { + set setup_margin "--" + } + set res_1 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name $panel_name_hold -hold $disable_panel_color_flag $quiet_flag] + set hold_margin [lindex $res_1 1] + + set recovery_paths 0 + set removal_paths 0 + + if {!$hold_only_corner && ([get_collection_size [get_timing_paths -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths 1 -recovery]] > 0)} { + set recovery_paths 1 + set res_2 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name $panel_name_recovery -recovery $disable_panel_color_flag $quiet_flag] + set recovery_margin [lindex $res_2 1] + } else { + set recovery_margin "--" + } + + if {[get_collection_size [get_timing_paths -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths 1 -removal]] > 0} { + set removal_paths 1 + set res_3 [report_timing -quiet -detail full_path -from_clock $from_clks -to_clock $to_clks -from $from_nodes -to $to_nodes -npaths $num_failing_path -panel_name $panel_name_removal -removal $disable_panel_color_flag $quiet_flag] + set removal_margin [lindex $res_3 1] + } else { + set removal_margin "--" + } + + if {$var(DIAG_TIMING_REGTEST_MODE)} { + lappend global_summary [list $opcname 0 "$title ($opcname)" $setup_margin $hold_margin] + if {($recovery_paths == 1) || ($removal_paths == 1)} { + lappend global_summary [list $opcname 0 "$title Recovery/Removal ($opcname)" $recovery_margin $hold_margin] + } + } + + return [list $setup_margin $hold_margin $recovery_margin $removal_margin] +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_perform_core_analysis {opcname inst pin_array_name var_array_name summary_name} { + + ####################################### + # Need access to global variables + upvar 1 $summary_name global_summary + upvar 1 $var_array_name var + upvar 1 $pin_array_name pins + global ::io_only_analysis + + # Debug switch. Change to 1 to get more run-time debug information + set debug 0 + set result 1 + + ############################### + # PHY analysis + ############################### + + set analysis_name "Core" + + if {$::io_only_analysis == 1} { + set setup_slack "--" + set hold_slack "--" + lappend global_summary [list $opcname 0 "$analysis_name ($opcname)" $setup_slack $hold_slack] + post_message -type warning "Early EMIF IO timing estimate does not include core FPGA timing" + } elseif {$var(IS_HPS)} { + # No core timing analysis required by HPS interface + set setup_slack "--" + set hold_slack "--" + lappend global_summary [list $opcname 0 "$analysis_name ($opcname)" $setup_slack $hold_slack] + lappend global_summary [list $opcname 0 "$analysis_name Recovery/Removal ($opcname)" $setup_slack $hold_slack] + } else { + + set master_instname $pins(master_instname) + set coreclkname [list ${master_instname}_core_usr_* ${master_instname}_core_afi_* ${master_instname}_core_dft_* ${master_instname}_ref_clock ${master_instname}_core_nios_clk [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_name_from_pin_name $pins(pll_ref_clock)]] + set coreclks [get_clocks -nowarn $coreclkname] + + set phyclkname [list ${inst}_phy_*] + set phyclks [get_clocks -nowarn $phyclkname] + + set emif_regs [get_registers $inst|*] + set rest_regs [remove_from_collection [all_registers] $emif_regs] + + set setup_margin 999.9 + set hold_margin 999.9 + set recovery_margin 999.9 + set removal_margin 999.9 + + # Core/periphery transfers + + # Core-to-periphery + set res [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_c2p_p2c_report_timing_analysis $opcname $inst $pin_array_name var global_summary "Core To Periphery" $coreclks $phyclks "*" $emif_regs 0] + set setup_margin [min $setup_margin [lindex $res 0]] + set hold_margin [min $hold_margin [lindex $res 1]] + set recovery_margin [min $recovery_margin [lindex $res 2]] + set removal_margin [min $removal_margin [lindex $res 3]] + + # Periphery-to-core + set res [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_c2p_p2c_report_timing_analysis $opcname $inst $pin_array_name var global_summary "Periphery To Core" $phyclks $coreclks $emif_regs "*" 1] + set setup_margin [min $setup_margin [lindex $res 0]] + set hold_margin [min $hold_margin [lindex $res 1]] + set recovery_margin [min $recovery_margin [lindex $res 2]] + set removal_margin [min $removal_margin [lindex $res 3]] + + # Pure Core transfers + + set_active_clocks [remove_from_collection [all_clocks] $phyclks] + + # EMIF logic within FPGA core + set res [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_report_timing_analysis $opcname $inst var global_summary "Within Core" $coreclks $coreclks $emif_regs $emif_regs] + set setup_margin [min $setup_margin [lindex $res 0]] + set hold_margin [min $hold_margin [lindex $res 1]] + set recovery_margin [min $recovery_margin [lindex $res 2]] + set removal_margin [min $removal_margin [lindex $res 3]] + + # Transfers between EMIF and user logic + set res [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_report_timing_analysis $opcname $inst var global_summary "IP to User Logic" "*" "*" $emif_regs $rest_regs] + set setup_margin [min $setup_margin [lindex $res 0]] + set hold_margin [min $hold_margin [lindex $res 1]] + set recovery_margin [min $recovery_margin [lindex $res 2]] + set removal_margin [min $removal_margin [lindex $res 3]] + + # Transfers between user and EMIF logic + set res [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_report_timing_analysis $opcname $inst var global_summary "User Logic to IP" "*" "*" $rest_regs $emif_regs] + set setup_margin [min $setup_margin [lindex $res 0]] + set hold_margin [min $hold_margin [lindex $res 1]] + set recovery_margin [min $recovery_margin [lindex $res 2]] + set removal_margin [min $removal_margin [lindex $res 3]] + + # Transfers within non-EMIF logic (not reported by default since they are irrelevant to EMIF IP) + if {$var(DIAG_TIMING_REGTEST_MODE)} { + set res [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_add_report_timing_analysis $opcname $inst var global_summary "Within User Logic" $coreclks $coreclks $rest_regs $rest_regs] + set setup_margin [min $setup_margin [lindex $res 0]] + set hold_margin [min $hold_margin [lindex $res 1]] + set recovery_margin [min $recovery_margin [lindex $res 2]] + set removal_margin [min $removal_margin [lindex $res 3]] + } + + set_active_clocks [all_clocks] + + lappend global_summary [list $opcname 0 "$analysis_name ($opcname)" $setup_margin $hold_margin] + lappend global_summary [list $opcname 0 "$analysis_name Recovery/Removal ($opcname)" $recovery_margin $removal_margin] + } +} + + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_sim.txt b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_sim.txt new file mode 100644 index 0000000000..4fd22e31c2 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_sim.txt @@ -0,0 +1,239 @@ +// This file is dynamically generated and is for information purposes only. +// It is not used during compilation or simulation. + +SEQ_PT + 0x7419 SEQ_PT_IP_VER : 19520 0x4C40 + 0x741B SEQ_PT_INTERFACE_PAR_VER : 2 0x0002 + 0x741D SEQ_PT_DEBUG_DATA_PTR : 0 0x0000 + 0x741F SEQ_PT_USER_COMMAND_PTR : 0 0x0000 + 0x7421 SEQ_PT_MEMORY_TYPE : 1 0x01 + 0x7422 SEQ_PT_DIMM_TYPE : 2 0x02 + 0x7423 SEQ_PT_CONTROLLER_TYPE : 0 0x00 + 0x7424 SEQ_PT_RESERVED : 0 0x00 + 0x7425 SEQ_PT_AFI_CLK_FREQ_KHZ : 600000 0x000927C0 + 0x7429 SEQ_PT_BURST_LEN : 8 0x08 + 0x742A SEQ_PT_READ_LATENCY : 23 0x17 + 0x742B SEQ_PT_WRITE_LATENCY : 18 0x12 + 0x742C SEQ_PT_NUM_RANKS : 1 0x01 + 0x742D SEQ_PT_NUM_DIMMS : 1 0x01 + 0x742E SEQ_PT_NUM_DQS_WR : 9 0x09 + 0x742F SEQ_PT_NUM_DQS_RD : 9 0x09 + 0x7430 SEQ_PT_NUM_DQ : 72 0x48 + 0x7431 SEQ_PT_NUM_DM : 9 0x09 + 0x7432 SEQ_PT_ADDR_WIDTH : 17 0x11 + 0x7433 SEQ_PT_BANK_WIDTH : 2 0x02 + 0x7434 SEQ_PT_CS_WIDTH : 1 0x01 + 0x7435 SEQ_PT_CKE_WIDTH : 1 0x01 + 0x7436 SEQ_PT_ODT_WIDTH : 1 0x01 + 0x7437 SEQ_PT_C_WIDTH : 0 0x00 + 0x7438 SEQ_PT_BANK_GROUP_WIDTH : 2 0x02 + 0x7439 SEQ_PT_ADDR_MIRROR : 0 0x00 + 0x743A SEQ_PT_CK_WIDTH : 1 0x01 + 0x743B SEQ_PT_CAL_DATA_SIZE : 20 0x14 + 0x743C SEQ_PT_NUM_LRDIMM_CFG : 5 0x05 + 0x743D SEQ_PT_NUM_AC_ROM_ENUMS : 52 0x34 + 0x743E SEQ_PT_NUM_CENTERS : 4 0x04 + 0x743F SEQ_PT_NUM_CA_LANES : 4 0x04 + 0x7440 SEQ_PT_NUM_DATA_LANES : 9 0x09 + 0x7441 SEQ_PT_ODT_TABLE_LO : 0 0x00000000 + 0x7445 SEQ_PT_ODT_TABLE_HI : 0 0x00000000 + 0x7449 SEQ_PT_CAL_CONFIG : 220258433 0x0D20E081 + 0x744D SEQ_PT_FILLER : 0 0x0000 + 0x744F SEQ_PT_CAL_DATA_PTR : 176 0x00B0 + 0x00B0 STARTING_VREFIN : 291 0x00000123 (Range 2 - 45%-77.5%, setting = 35) + 0x00B4 CAL_TREFI : 7800 0x00001E78 7800 + 0x00B8 CAL_TRFC : 350 0x0000015E 350 + 0x00BC CAL_ADDR0 : 0 0x00000000 0 + 0x00C0 CAL_ADDR1 : 8 0x00000008 8 + 0x7451 SEQ_PT_DBG_SKIP_RANKS : 0 0x00000000 + 0x7455 SEQ_PT_DBG_SKIP_GROUPS : 0 0x00000000 + 0x7459 SEQ_PT_DBG_SKIP_STEPS : 1350030720 0x5077D580 + 0x745D SEQ_PT_NUM_MR : 12 0x0C + 0x745E SEQ_PT_NUM_DIMM_MR : 7 0x07 + 0x745F SEQ_PT_TILE_ID_PTR : 196 0x00C4 + 0x00C4 TILE [0] : 12 0x0C (T) = (1) + 0x00C5 TILE [1] : 4 0x04 (T) = (0) + 0x00C6 TILE [2] : 20 0x14 (T) = (2) + 0x00C7 TILE [3] : 28 0x1C (T) = (3) + 0x00C8 AC_LANE [0] : 8 0x08 (T L) = (1 0) + 0x00C9 AC_LANE [1] : 9 0x09 (T L) = (1 1) + 0x00CA AC_LANE [2] : 10 0x0A (T L) = (1 2) + 0x00CB AC_LANE [3] : 11 0x0B (T L) = (1 3) + 0x00CC DATA_LANE [0] : 0 0x00 (T L) = (0 0) + 0x00CD DATA_LANE [1] : 1 0x01 (T L) = (0 1) + 0x00CE DATA_LANE [2] : 2 0x02 (T L) = (0 2) + 0x00CF DATA_LANE [3] : 3 0x03 (T L) = (0 3) + 0x00D0 DATA_LANE [4] : 16 0x10 (T L) = (2 0) + 0x00D1 DATA_LANE [5] : 17 0x11 (T L) = (2 1) + 0x00D2 DATA_LANE [6] : 18 0x12 (T L) = (2 2) + 0x00D3 DATA_LANE [7] : 19 0x13 (T L) = (2 3) + 0x00D4 DATA_LANE [8] : 24 0x18 (T L) = (3 0) + 0x00D5 ALIGN_PAD : 0 0x00 + 0x00D6 ALIGN_PAD : 0 0x00 + 0x00D7 ALIGN_PAD : 0 0x00 + 0x7461 SEQ_PT_PIN_ADDR_PTR : 216 0x00D8 + 0x00D8 PORT_MEM_CKE [0] : 6 0x06 (T L P) = (1 0 6 ) AC_LANE [0] + 0x00D9 : 0 0x00 UNUSED_AC_PORT + 0x00DA : 0 0x00 UNUSED_AC_PORT + 0x00DB : 0 0x00 UNUSED_AC_PORT + 0x00DC PORT_MEM_ODT [0] : 4 0x04 (T L P) = (1 0 4 ) AC_LANE [0] + 0x00DD : 0 0x00 UNUSED_AC_PORT + 0x00DE : 0 0x00 UNUSED_AC_PORT + 0x00DF : 0 0x00 UNUSED_AC_PORT + 0x00E0 PORT_MEM_RESET_N [0] : 1 0x01 (T L P) = (1 0 1 ) AC_LANE [0] + 0x00E1 PORT_MEM_ACT_N [0] : 3 0x03 (T L P) = (1 0 3 ) AC_LANE [0] + 0x00E2 PORT_MEM_CS_N [0] : 2 0x02 (T L P) = (1 0 2 ) AC_LANE [0] + 0x00E3 : 0 0x00 UNUSED_AC_PORT + 0x00E4 : 0 0x00 UNUSED_AC_PORT + 0x00E5 : 0 0x00 UNUSED_AC_PORT + 0x00E6 : 0 0x00 UNUSED_AC_PORT + 0x00E7 : 0 0x00 UNUSED_AC_PORT + 0x00E8 : 0 0x00 UNUSED_AC_PORT + 0x00E9 PORT_MEM_BA [0] : 41 0x29 (T L P) = (1 2 9 ) AC_LANE [2] + 0x00EA PORT_MEM_BA [1] : 42 0x2A (T L P) = (1 2 10) AC_LANE [2] + 0x00EB PORT_MEM_BG [0] : 43 0x2B (T L P) = (1 2 11) AC_LANE [2] + 0x00EC PORT_MEM_BG [1] : 0 0x00 (T L P) = (1 0 0 ) AC_LANE [0] + 0x00ED PORT_MEM_A [0] : 16 0x10 (T L P) = (1 1 0 ) AC_LANE [1] + 0x00EE PORT_MEM_A [1] : 17 0x11 (T L P) = (1 1 1 ) AC_LANE [1] + 0x00EF PORT_MEM_A [2] : 18 0x12 (T L P) = (1 1 2 ) AC_LANE [1] + 0x00F0 PORT_MEM_A [3] : 19 0x13 (T L P) = (1 1 3 ) AC_LANE [1] + 0x00F1 PORT_MEM_A [4] : 20 0x14 (T L P) = (1 1 4 ) AC_LANE [1] + 0x00F2 PORT_MEM_A [5] : 21 0x15 (T L P) = (1 1 5 ) AC_LANE [1] + 0x00F3 PORT_MEM_A [6] : 22 0x16 (T L P) = (1 1 6 ) AC_LANE [1] + 0x00F4 PORT_MEM_A [7] : 23 0x17 (T L P) = (1 1 7 ) AC_LANE [1] + 0x00F5 PORT_MEM_A [8] : 24 0x18 (T L P) = (1 1 8 ) AC_LANE [1] + 0x00F6 PORT_MEM_A [9] : 25 0x19 (T L P) = (1 1 9 ) AC_LANE [1] + 0x00F7 PORT_MEM_A [10] : 26 0x1A (T L P) = (1 1 10) AC_LANE [1] + 0x00F8 PORT_MEM_A [11] : 27 0x1B (T L P) = (1 1 11) AC_LANE [1] + 0x00F9 PORT_MEM_A [12] : 35 0x23 (T L P) = (1 2 3 ) AC_LANE [2] + 0x00FA PORT_MEM_A [13] : 36 0x24 (T L P) = (1 2 4 ) AC_LANE [2] + 0x00FB PORT_MEM_A [14] : 37 0x25 (T L P) = (1 2 5 ) AC_LANE [2] + 0x00FC PORT_MEM_A [15] : 38 0x26 (T L P) = (1 2 6 ) AC_LANE [2] + 0x00FD PORT_MEM_A [16] : 39 0x27 (T L P) = (1 2 7 ) AC_LANE [2] + 0x00FE : 0 0x00 UNUSED_AC_PORT + 0x00FF : 0 0x00 UNUSED_AC_PORT + 0x0100 : 0 0x00 UNUSED_AC_PORT + 0x0101 PORT_MEM_PAR [0] : 11 0x0B (T L P) = (1 0 11) AC_LANE [0] + 0x0102 PORT_MEM_ALERT_N [0] : 56 0x38 (T L P) = (1 3 8 ) AC_LANE [3] + 0x0103 : 0 0x00 UNUSED_AC_PORT + 0x0104 PORT_MEM_CK [0] : 8 0x08 (T L P) = (1 0 8 ) AC_LANE [0] + 0x0105 PORT_MEM_CK_N [0] : 9 0x09 (T L P) = (1 0 9 ) AC_LANE [0] + 0x0106 : 0 0x00 UNUSED_AC_PORT + 0x0107 : 0 0x00 UNUSED_AC_PORT + 0x0108 : 0 0x00 UNUSED_AC_PORT + 0x0109 : 0 0x00 UNUSED_AC_PORT + 0x010A : 0 0x00 UNUSED_AC_PORT + 0x010B : 0 0x00 UNUSED_AC_PORT + 0x010C PORT_MEM_DQS [0] : 4 0x04 (T L P) = (0 0 4 ) DATA_LANE [0] + 0x010D PORT_MEM_DQS [1] : 20 0x14 (T L P) = (0 1 4 ) DATA_LANE [1] + 0x010E PORT_MEM_DQS [2] : 36 0x24 (T L P) = (0 2 4 ) DATA_LANE [2] + 0x010F PORT_MEM_DQS [3] : 52 0x34 (T L P) = (0 3 4 ) DATA_LANE [3] + 0x0110 PORT_MEM_DQS [4] : 68 0x44 (T L P) = (2 0 4 ) DATA_LANE [4] + 0x0111 PORT_MEM_DQS [5] : 84 0x54 (T L P) = (2 1 4 ) DATA_LANE [5] + 0x0112 PORT_MEM_DQS [6] : 100 0x64 (T L P) = (2 2 4 ) DATA_LANE [6] + 0x0113 PORT_MEM_DQS [7] : 116 0x74 (T L P) = (2 3 4 ) DATA_LANE [7] + 0x0114 PORT_MEM_DQS [8] : 132 0x84 (T L P) = (3 0 4 ) DATA_LANE [8] + 0x0115 PORT_MEM_DQS_N [0] : 5 0x05 (T L P) = (0 0 5 ) DATA_LANE [0] + 0x0116 PORT_MEM_DQS_N [1] : 21 0x15 (T L P) = (0 1 5 ) DATA_LANE [1] + 0x0117 PORT_MEM_DQS_N [2] : 37 0x25 (T L P) = (0 2 5 ) DATA_LANE [2] + 0x0118 PORT_MEM_DQS_N [3] : 53 0x35 (T L P) = (0 3 5 ) DATA_LANE [3] + 0x0119 PORT_MEM_DQS_N [4] : 69 0x45 (T L P) = (2 0 5 ) DATA_LANE [4] + 0x011A PORT_MEM_DQS_N [5] : 85 0x55 (T L P) = (2 1 5 ) DATA_LANE [5] + 0x011B PORT_MEM_DQS_N [6] : 101 0x65 (T L P) = (2 2 5 ) DATA_LANE [6] + 0x011C PORT_MEM_DQS_N [7] : 117 0x75 (T L P) = (2 3 5 ) DATA_LANE [7] + 0x011D PORT_MEM_DQS_N [8] : 133 0x85 (T L P) = (3 0 5 ) DATA_LANE [8] + 0x011E PORT_MEM_DBI_N [0] : 6 0x06 (T L P) = (0 0 6 ) DATA_LANE [0] + 0x011F PORT_MEM_DBI_N [1] : 22 0x16 (T L P) = (0 1 6 ) DATA_LANE [1] + 0x0120 PORT_MEM_DBI_N [2] : 38 0x26 (T L P) = (0 2 6 ) DATA_LANE [2] + 0x0121 PORT_MEM_DBI_N [3] : 54 0x36 (T L P) = (0 3 6 ) DATA_LANE [3] + 0x0122 PORT_MEM_DBI_N [4] : 70 0x46 (T L P) = (2 0 6 ) DATA_LANE [4] + 0x0123 PORT_MEM_DBI_N [5] : 86 0x56 (T L P) = (2 1 6 ) DATA_LANE [5] + 0x0124 PORT_MEM_DBI_N [6] : 102 0x66 (T L P) = (2 2 6 ) DATA_LANE [6] + 0x0125 PORT_MEM_DBI_N [7] : 118 0x76 (T L P) = (2 3 6 ) DATA_LANE [7] + 0x0126 PORT_MEM_DBI_N [8] : 134 0x86 (T L P) = (3 0 6 ) DATA_LANE [8] + 0x0127 PORT_MEM_DQ [0] : 0 0x00 (T L P) = (0 0 0 ) DATA_LANE [0] + 0x0128 PORT_MEM_DQ [1] : 1 0x01 (T L P) = (0 0 1 ) DATA_LANE [0] + 0x0129 PORT_MEM_DQ [2] : 2 0x02 (T L P) = (0 0 2 ) DATA_LANE [0] + 0x012A PORT_MEM_DQ [3] : 3 0x03 (T L P) = (0 0 3 ) DATA_LANE [0] + 0x012B PORT_MEM_DQ [4] : 8 0x08 (T L P) = (0 0 8 ) DATA_LANE [0] + 0x012C PORT_MEM_DQ [5] : 9 0x09 (T L P) = (0 0 9 ) DATA_LANE [0] + 0x012D PORT_MEM_DQ [6] : 10 0x0A (T L P) = (0 0 10) DATA_LANE [0] + 0x012E PORT_MEM_DQ [7] : 11 0x0B (T L P) = (0 0 11) DATA_LANE [0] + 0x012F PORT_MEM_DQ [8] : 16 0x10 (T L P) = (0 1 0 ) DATA_LANE [1] + 0x0130 PORT_MEM_DQ [9] : 17 0x11 (T L P) = (0 1 1 ) DATA_LANE [1] + 0x0131 PORT_MEM_DQ [10] : 18 0x12 (T L P) = (0 1 2 ) DATA_LANE [1] + 0x0132 PORT_MEM_DQ [11] : 19 0x13 (T L P) = (0 1 3 ) DATA_LANE [1] + 0x0133 PORT_MEM_DQ [12] : 24 0x18 (T L P) = (0 1 8 ) DATA_LANE [1] + 0x0134 PORT_MEM_DQ [13] : 25 0x19 (T L P) = (0 1 9 ) DATA_LANE [1] + 0x0135 PORT_MEM_DQ [14] : 26 0x1A (T L P) = (0 1 10) DATA_LANE [1] + 0x0136 PORT_MEM_DQ [15] : 27 0x1B (T L P) = (0 1 11) DATA_LANE [1] + 0x0137 PORT_MEM_DQ [16] : 32 0x20 (T L P) = (0 2 0 ) DATA_LANE [2] + 0x0138 PORT_MEM_DQ [17] : 33 0x21 (T L P) = (0 2 1 ) DATA_LANE [2] + 0x0139 PORT_MEM_DQ [18] : 34 0x22 (T L P) = (0 2 2 ) DATA_LANE [2] + 0x013A PORT_MEM_DQ [19] : 35 0x23 (T L P) = (0 2 3 ) DATA_LANE [2] + 0x013B PORT_MEM_DQ [20] : 40 0x28 (T L P) = (0 2 8 ) DATA_LANE [2] + 0x013C PORT_MEM_DQ [21] : 41 0x29 (T L P) = (0 2 9 ) DATA_LANE [2] + 0x013D PORT_MEM_DQ [22] : 42 0x2A (T L P) = (0 2 10) DATA_LANE [2] + 0x013E PORT_MEM_DQ [23] : 43 0x2B (T L P) = (0 2 11) DATA_LANE [2] + 0x013F PORT_MEM_DQ [24] : 48 0x30 (T L P) = (0 3 0 ) DATA_LANE [3] + 0x0140 PORT_MEM_DQ [25] : 49 0x31 (T L P) = (0 3 1 ) DATA_LANE [3] + 0x0141 PORT_MEM_DQ [26] : 50 0x32 (T L P) = (0 3 2 ) DATA_LANE [3] + 0x0142 PORT_MEM_DQ [27] : 51 0x33 (T L P) = (0 3 3 ) DATA_LANE [3] + 0x0143 PORT_MEM_DQ [28] : 56 0x38 (T L P) = (0 3 8 ) DATA_LANE [3] + 0x0144 PORT_MEM_DQ [29] : 57 0x39 (T L P) = (0 3 9 ) DATA_LANE [3] + 0x0145 PORT_MEM_DQ [30] : 58 0x3A (T L P) = (0 3 10) DATA_LANE [3] + 0x0146 PORT_MEM_DQ [31] : 59 0x3B (T L P) = (0 3 11) DATA_LANE [3] + 0x0147 PORT_MEM_DQ [32] : 64 0x40 (T L P) = (2 0 0 ) DATA_LANE [4] + 0x0148 PORT_MEM_DQ [33] : 65 0x41 (T L P) = (2 0 1 ) DATA_LANE [4] + 0x0149 PORT_MEM_DQ [34] : 66 0x42 (T L P) = (2 0 2 ) DATA_LANE [4] + 0x014A PORT_MEM_DQ [35] : 67 0x43 (T L P) = (2 0 3 ) DATA_LANE [4] + 0x014B PORT_MEM_DQ [36] : 72 0x48 (T L P) = (2 0 8 ) DATA_LANE [4] + 0x014C PORT_MEM_DQ [37] : 73 0x49 (T L P) = (2 0 9 ) DATA_LANE [4] + 0x014D PORT_MEM_DQ [38] : 74 0x4A (T L P) = (2 0 10) DATA_LANE [4] + 0x014E PORT_MEM_DQ [39] : 75 0x4B (T L P) = (2 0 11) DATA_LANE [4] + 0x014F PORT_MEM_DQ [40] : 80 0x50 (T L P) = (2 1 0 ) DATA_LANE [5] + 0x0150 PORT_MEM_DQ [41] : 81 0x51 (T L P) = (2 1 1 ) DATA_LANE [5] + 0x0151 PORT_MEM_DQ [42] : 82 0x52 (T L P) = (2 1 2 ) DATA_LANE [5] + 0x0152 PORT_MEM_DQ [43] : 83 0x53 (T L P) = (2 1 3 ) DATA_LANE [5] + 0x0153 PORT_MEM_DQ [44] : 88 0x58 (T L P) = (2 1 8 ) DATA_LANE [5] + 0x0154 PORT_MEM_DQ [45] : 89 0x59 (T L P) = (2 1 9 ) DATA_LANE [5] + 0x0155 PORT_MEM_DQ [46] : 90 0x5A (T L P) = (2 1 10) DATA_LANE [5] + 0x0156 PORT_MEM_DQ [47] : 91 0x5B (T L P) = (2 1 11) DATA_LANE [5] + 0x0157 PORT_MEM_DQ [48] : 96 0x60 (T L P) = (2 2 0 ) DATA_LANE [6] + 0x0158 PORT_MEM_DQ [49] : 97 0x61 (T L P) = (2 2 1 ) DATA_LANE [6] + 0x0159 PORT_MEM_DQ [50] : 98 0x62 (T L P) = (2 2 2 ) DATA_LANE [6] + 0x015A PORT_MEM_DQ [51] : 99 0x63 (T L P) = (2 2 3 ) DATA_LANE [6] + 0x015B PORT_MEM_DQ [52] : 104 0x68 (T L P) = (2 2 8 ) DATA_LANE [6] + 0x015C PORT_MEM_DQ [53] : 105 0x69 (T L P) = (2 2 9 ) DATA_LANE [6] + 0x015D PORT_MEM_DQ [54] : 106 0x6A (T L P) = (2 2 10) DATA_LANE [6] + 0x015E PORT_MEM_DQ [55] : 107 0x6B (T L P) = (2 2 11) DATA_LANE [6] + 0x015F PORT_MEM_DQ [56] : 112 0x70 (T L P) = (2 3 0 ) DATA_LANE [7] + 0x0160 PORT_MEM_DQ [57] : 113 0x71 (T L P) = (2 3 1 ) DATA_LANE [7] + 0x0161 PORT_MEM_DQ [58] : 114 0x72 (T L P) = (2 3 2 ) DATA_LANE [7] + 0x0162 PORT_MEM_DQ [59] : 115 0x73 (T L P) = (2 3 3 ) DATA_LANE [7] + 0x0163 PORT_MEM_DQ [60] : 120 0x78 (T L P) = (2 3 8 ) DATA_LANE [7] + 0x0164 PORT_MEM_DQ [61] : 121 0x79 (T L P) = (2 3 9 ) DATA_LANE [7] + 0x0165 PORT_MEM_DQ [62] : 122 0x7A (T L P) = (2 3 10) DATA_LANE [7] + 0x0166 PORT_MEM_DQ [63] : 123 0x7B (T L P) = (2 3 11) DATA_LANE [7] + 0x0167 PORT_MEM_DQ [64] : 128 0x80 (T L P) = (3 0 0 ) DATA_LANE [8] + 0x0168 PORT_MEM_DQ [65] : 129 0x81 (T L P) = (3 0 1 ) DATA_LANE [8] + 0x0169 PORT_MEM_DQ [66] : 130 0x82 (T L P) = (3 0 2 ) DATA_LANE [8] + 0x016A PORT_MEM_DQ [67] : 131 0x83 (T L P) = (3 0 3 ) DATA_LANE [8] + 0x016B PORT_MEM_DQ [68] : 136 0x88 (T L P) = (3 0 8 ) DATA_LANE [8] + 0x016C PORT_MEM_DQ [69] : 137 0x89 (T L P) = (3 0 9 ) DATA_LANE [8] + 0x016D PORT_MEM_DQ [70] : 138 0x8A (T L P) = (3 0 10) DATA_LANE [8] + 0x016E PORT_MEM_DQ [71] : 139 0x8B (T L P) = (3 0 11) DATA_LANE [8] + 0x016F ALIGN_PAD : 0 0x00 + 0x7463 SEQ_PT_MR_PTR : 368 0x0170 + 0x0170 MR0 : 2164 0x00000874 00000000100001110100 + 0x0174 MR1 : 65537 0x00010001 00010000000000000001 + 0x0178 MR2 : 131112 0x00020028 00100000000000101000 + 0x017C MR3 : 197632 0x00030400 00110000010000000000 + 0x0180 MR4 : 264192 0x00040800 01000000100000000000 + 0x0184 MR5 : 332896 0x00051460 01010001010001100000 + 0x0188 MR6 : 395279 0x0006080F 01100000100000001111 + 0x018C RDIMM CONTROL WORD : 257253376 0x0F556000 00001111010101010110000000000000 + 0x0190 RDIMM CONTROL WORD : 222298891 0x0D40030B 00001101010000000000001100001011 + 0x0194 RDIMM CONTROL WORD : 3735552 0x00390000 00000000001110010000000000000000 + 0x0198 RDIMM CONTROL WORD : 536870912 0x20000000 00100000000000000000000000000000 + 0x019C RDIMM CONTROL WORD : 0 0x00000000 00000000000000000000000000000000 diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.hex b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.hex new file mode 100644 index 0000000000..0f151abb02 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.hex @@ -0,0 +1,80 @@ +:0474190000024C40E1 +:04741A00000000006E +:04741B00000002016A +:04741C00000927C07C +:04741D000112170839 +:04741E00480909010F +:04741F00010211094C +:047420000200010164 +:04742100051401004D +:047422000904043421 +:047423000000000065 +:047424000000000064 +:047425000D00C08115 +:0474260000B00000B2 +:047427000000000061 +:047428000000000060 +:047429005066008029 +:04742A0000C4070C87 +:04742B00017000D814 +:04742C000000012338 +:04742D0000001E78C5 +:04742E000000015EFB +:04742F000000000059 +:047430000000000850 +:047431001C14040C17 +:047432000B0A090830 +:04743300030201004F +:04743400131211100E +:04743500000000183B +:04743600000000064C +:04743700000000044D +:04743800000203014A +:04743900000000004F +:04743A002B2A2900D0 +:04743B00121110001A +:04743C0016151413FA +:04743D001A191817E9 +:04743E002524231BC3 +:04743F0000002726FC +:0474400000380B0005 +:047441000000090836 +:047442000000000046 +:0474430034241404D5 +:0474440074645444D4 +:047445002515058480 +:04744600655545350E +:04744700160685752B +:047448005646362648 +:0474490000867666DD +:04744A000803020130 +:04744B00100B0A090F +:04744C0018131211EE +:04744D00201B1A19CD +:04744E0028232221AC +:04744F00302B2A298B +:04745000383332316A +:04745100403B3A3949 +:047452004843424128 +:04745300504B4A4907 +:0474540058535251E6 +:04745500605B5A59C5 +:0474560068636261A4 +:04745700706B6A6983 +:047458007873727162 +:04745900807B7A7941 +:04745A008883828120 +:04745B00008B8A898F +:04745C0000000874B0 +:04745D000001000129 +:04745E000002002800 +:04745F000003040022 +:04746000000408001C +:0474610000051460AE +:047462000006080F09 +:047463000F55600061 +:047464000D40030BC9 +:0474650000390000EA +:047466002000000002 +:047467000000000021 +:00000001FF diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.txt b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.txt new file mode 100644 index 0000000000..20ddc02529 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.txt @@ -0,0 +1,239 @@ +// This file is dynamically generated and is for information purposes only. +// It is not used during compilation or simulation. + +SEQ_PT + 0x7419 SEQ_PT_IP_VER : 19520 0x4C40 + 0x741B SEQ_PT_INTERFACE_PAR_VER : 2 0x0002 + 0x741D SEQ_PT_DEBUG_DATA_PTR : 0 0x0000 + 0x741F SEQ_PT_USER_COMMAND_PTR : 0 0x0000 + 0x7421 SEQ_PT_MEMORY_TYPE : 1 0x01 + 0x7422 SEQ_PT_DIMM_TYPE : 2 0x02 + 0x7423 SEQ_PT_CONTROLLER_TYPE : 0 0x00 + 0x7424 SEQ_PT_RESERVED : 0 0x00 + 0x7425 SEQ_PT_AFI_CLK_FREQ_KHZ : 600000 0x000927C0 + 0x7429 SEQ_PT_BURST_LEN : 8 0x08 + 0x742A SEQ_PT_READ_LATENCY : 23 0x17 + 0x742B SEQ_PT_WRITE_LATENCY : 18 0x12 + 0x742C SEQ_PT_NUM_RANKS : 1 0x01 + 0x742D SEQ_PT_NUM_DIMMS : 1 0x01 + 0x742E SEQ_PT_NUM_DQS_WR : 9 0x09 + 0x742F SEQ_PT_NUM_DQS_RD : 9 0x09 + 0x7430 SEQ_PT_NUM_DQ : 72 0x48 + 0x7431 SEQ_PT_NUM_DM : 9 0x09 + 0x7432 SEQ_PT_ADDR_WIDTH : 17 0x11 + 0x7433 SEQ_PT_BANK_WIDTH : 2 0x02 + 0x7434 SEQ_PT_CS_WIDTH : 1 0x01 + 0x7435 SEQ_PT_CKE_WIDTH : 1 0x01 + 0x7436 SEQ_PT_ODT_WIDTH : 1 0x01 + 0x7437 SEQ_PT_C_WIDTH : 0 0x00 + 0x7438 SEQ_PT_BANK_GROUP_WIDTH : 2 0x02 + 0x7439 SEQ_PT_ADDR_MIRROR : 0 0x00 + 0x743A SEQ_PT_CK_WIDTH : 1 0x01 + 0x743B SEQ_PT_CAL_DATA_SIZE : 20 0x14 + 0x743C SEQ_PT_NUM_LRDIMM_CFG : 5 0x05 + 0x743D SEQ_PT_NUM_AC_ROM_ENUMS : 52 0x34 + 0x743E SEQ_PT_NUM_CENTERS : 4 0x04 + 0x743F SEQ_PT_NUM_CA_LANES : 4 0x04 + 0x7440 SEQ_PT_NUM_DATA_LANES : 9 0x09 + 0x7441 SEQ_PT_ODT_TABLE_LO : 0 0x00000000 + 0x7445 SEQ_PT_ODT_TABLE_HI : 0 0x00000000 + 0x7449 SEQ_PT_CAL_CONFIG : 218153089 0x0D00C081 + 0x744D SEQ_PT_FILLER : 0 0x0000 + 0x744F SEQ_PT_CAL_DATA_PTR : 176 0x00B0 + 0x00B0 STARTING_VREFIN : 291 0x00000123 (Range 2 - 45%-77.5%, setting = 35) + 0x00B4 CAL_TREFI : 7800 0x00001E78 7800 + 0x00B8 CAL_TRFC : 350 0x0000015E 350 + 0x00BC CAL_ADDR0 : 0 0x00000000 0 + 0x00C0 CAL_ADDR1 : 8 0x00000008 8 + 0x7451 SEQ_PT_DBG_SKIP_RANKS : 0 0x00000000 + 0x7455 SEQ_PT_DBG_SKIP_GROUPS : 0 0x00000000 + 0x7459 SEQ_PT_DBG_SKIP_STEPS : 1348862080 0x50660080 + 0x745D SEQ_PT_NUM_MR : 12 0x0C + 0x745E SEQ_PT_NUM_DIMM_MR : 7 0x07 + 0x745F SEQ_PT_TILE_ID_PTR : 196 0x00C4 + 0x00C4 TILE [0] : 12 0x0C (T) = (1) + 0x00C5 TILE [1] : 4 0x04 (T) = (0) + 0x00C6 TILE [2] : 20 0x14 (T) = (2) + 0x00C7 TILE [3] : 28 0x1C (T) = (3) + 0x00C8 AC_LANE [0] : 8 0x08 (T L) = (1 0) + 0x00C9 AC_LANE [1] : 9 0x09 (T L) = (1 1) + 0x00CA AC_LANE [2] : 10 0x0A (T L) = (1 2) + 0x00CB AC_LANE [3] : 11 0x0B (T L) = (1 3) + 0x00CC DATA_LANE [0] : 0 0x00 (T L) = (0 0) + 0x00CD DATA_LANE [1] : 1 0x01 (T L) = (0 1) + 0x00CE DATA_LANE [2] : 2 0x02 (T L) = (0 2) + 0x00CF DATA_LANE [3] : 3 0x03 (T L) = (0 3) + 0x00D0 DATA_LANE [4] : 16 0x10 (T L) = (2 0) + 0x00D1 DATA_LANE [5] : 17 0x11 (T L) = (2 1) + 0x00D2 DATA_LANE [6] : 18 0x12 (T L) = (2 2) + 0x00D3 DATA_LANE [7] : 19 0x13 (T L) = (2 3) + 0x00D4 DATA_LANE [8] : 24 0x18 (T L) = (3 0) + 0x00D5 ALIGN_PAD : 0 0x00 + 0x00D6 ALIGN_PAD : 0 0x00 + 0x00D7 ALIGN_PAD : 0 0x00 + 0x7461 SEQ_PT_PIN_ADDR_PTR : 216 0x00D8 + 0x00D8 PORT_MEM_CKE [0] : 6 0x06 (T L P) = (1 0 6 ) AC_LANE [0] + 0x00D9 : 0 0x00 UNUSED_AC_PORT + 0x00DA : 0 0x00 UNUSED_AC_PORT + 0x00DB : 0 0x00 UNUSED_AC_PORT + 0x00DC PORT_MEM_ODT [0] : 4 0x04 (T L P) = (1 0 4 ) AC_LANE [0] + 0x00DD : 0 0x00 UNUSED_AC_PORT + 0x00DE : 0 0x00 UNUSED_AC_PORT + 0x00DF : 0 0x00 UNUSED_AC_PORT + 0x00E0 PORT_MEM_RESET_N [0] : 1 0x01 (T L P) = (1 0 1 ) AC_LANE [0] + 0x00E1 PORT_MEM_ACT_N [0] : 3 0x03 (T L P) = (1 0 3 ) AC_LANE [0] + 0x00E2 PORT_MEM_CS_N [0] : 2 0x02 (T L P) = (1 0 2 ) AC_LANE [0] + 0x00E3 : 0 0x00 UNUSED_AC_PORT + 0x00E4 : 0 0x00 UNUSED_AC_PORT + 0x00E5 : 0 0x00 UNUSED_AC_PORT + 0x00E6 : 0 0x00 UNUSED_AC_PORT + 0x00E7 : 0 0x00 UNUSED_AC_PORT + 0x00E8 : 0 0x00 UNUSED_AC_PORT + 0x00E9 PORT_MEM_BA [0] : 41 0x29 (T L P) = (1 2 9 ) AC_LANE [2] + 0x00EA PORT_MEM_BA [1] : 42 0x2A (T L P) = (1 2 10) AC_LANE [2] + 0x00EB PORT_MEM_BG [0] : 43 0x2B (T L P) = (1 2 11) AC_LANE [2] + 0x00EC PORT_MEM_BG [1] : 0 0x00 (T L P) = (1 0 0 ) AC_LANE [0] + 0x00ED PORT_MEM_A [0] : 16 0x10 (T L P) = (1 1 0 ) AC_LANE [1] + 0x00EE PORT_MEM_A [1] : 17 0x11 (T L P) = (1 1 1 ) AC_LANE [1] + 0x00EF PORT_MEM_A [2] : 18 0x12 (T L P) = (1 1 2 ) AC_LANE [1] + 0x00F0 PORT_MEM_A [3] : 19 0x13 (T L P) = (1 1 3 ) AC_LANE [1] + 0x00F1 PORT_MEM_A [4] : 20 0x14 (T L P) = (1 1 4 ) AC_LANE [1] + 0x00F2 PORT_MEM_A [5] : 21 0x15 (T L P) = (1 1 5 ) AC_LANE [1] + 0x00F3 PORT_MEM_A [6] : 22 0x16 (T L P) = (1 1 6 ) AC_LANE [1] + 0x00F4 PORT_MEM_A [7] : 23 0x17 (T L P) = (1 1 7 ) AC_LANE [1] + 0x00F5 PORT_MEM_A [8] : 24 0x18 (T L P) = (1 1 8 ) AC_LANE [1] + 0x00F6 PORT_MEM_A [9] : 25 0x19 (T L P) = (1 1 9 ) AC_LANE [1] + 0x00F7 PORT_MEM_A [10] : 26 0x1A (T L P) = (1 1 10) AC_LANE [1] + 0x00F8 PORT_MEM_A [11] : 27 0x1B (T L P) = (1 1 11) AC_LANE [1] + 0x00F9 PORT_MEM_A [12] : 35 0x23 (T L P) = (1 2 3 ) AC_LANE [2] + 0x00FA PORT_MEM_A [13] : 36 0x24 (T L P) = (1 2 4 ) AC_LANE [2] + 0x00FB PORT_MEM_A [14] : 37 0x25 (T L P) = (1 2 5 ) AC_LANE [2] + 0x00FC PORT_MEM_A [15] : 38 0x26 (T L P) = (1 2 6 ) AC_LANE [2] + 0x00FD PORT_MEM_A [16] : 39 0x27 (T L P) = (1 2 7 ) AC_LANE [2] + 0x00FE : 0 0x00 UNUSED_AC_PORT + 0x00FF : 0 0x00 UNUSED_AC_PORT + 0x0100 : 0 0x00 UNUSED_AC_PORT + 0x0101 PORT_MEM_PAR [0] : 11 0x0B (T L P) = (1 0 11) AC_LANE [0] + 0x0102 PORT_MEM_ALERT_N [0] : 56 0x38 (T L P) = (1 3 8 ) AC_LANE [3] + 0x0103 : 0 0x00 UNUSED_AC_PORT + 0x0104 PORT_MEM_CK [0] : 8 0x08 (T L P) = (1 0 8 ) AC_LANE [0] + 0x0105 PORT_MEM_CK_N [0] : 9 0x09 (T L P) = (1 0 9 ) AC_LANE [0] + 0x0106 : 0 0x00 UNUSED_AC_PORT + 0x0107 : 0 0x00 UNUSED_AC_PORT + 0x0108 : 0 0x00 UNUSED_AC_PORT + 0x0109 : 0 0x00 UNUSED_AC_PORT + 0x010A : 0 0x00 UNUSED_AC_PORT + 0x010B : 0 0x00 UNUSED_AC_PORT + 0x010C PORT_MEM_DQS [0] : 4 0x04 (T L P) = (0 0 4 ) DATA_LANE [0] + 0x010D PORT_MEM_DQS [1] : 20 0x14 (T L P) = (0 1 4 ) DATA_LANE [1] + 0x010E PORT_MEM_DQS [2] : 36 0x24 (T L P) = (0 2 4 ) DATA_LANE [2] + 0x010F PORT_MEM_DQS [3] : 52 0x34 (T L P) = (0 3 4 ) DATA_LANE [3] + 0x0110 PORT_MEM_DQS [4] : 68 0x44 (T L P) = (2 0 4 ) DATA_LANE [4] + 0x0111 PORT_MEM_DQS [5] : 84 0x54 (T L P) = (2 1 4 ) DATA_LANE [5] + 0x0112 PORT_MEM_DQS [6] : 100 0x64 (T L P) = (2 2 4 ) DATA_LANE [6] + 0x0113 PORT_MEM_DQS [7] : 116 0x74 (T L P) = (2 3 4 ) DATA_LANE [7] + 0x0114 PORT_MEM_DQS [8] : 132 0x84 (T L P) = (3 0 4 ) DATA_LANE [8] + 0x0115 PORT_MEM_DQS_N [0] : 5 0x05 (T L P) = (0 0 5 ) DATA_LANE [0] + 0x0116 PORT_MEM_DQS_N [1] : 21 0x15 (T L P) = (0 1 5 ) DATA_LANE [1] + 0x0117 PORT_MEM_DQS_N [2] : 37 0x25 (T L P) = (0 2 5 ) DATA_LANE [2] + 0x0118 PORT_MEM_DQS_N [3] : 53 0x35 (T L P) = (0 3 5 ) DATA_LANE [3] + 0x0119 PORT_MEM_DQS_N [4] : 69 0x45 (T L P) = (2 0 5 ) DATA_LANE [4] + 0x011A PORT_MEM_DQS_N [5] : 85 0x55 (T L P) = (2 1 5 ) DATA_LANE [5] + 0x011B PORT_MEM_DQS_N [6] : 101 0x65 (T L P) = (2 2 5 ) DATA_LANE [6] + 0x011C PORT_MEM_DQS_N [7] : 117 0x75 (T L P) = (2 3 5 ) DATA_LANE [7] + 0x011D PORT_MEM_DQS_N [8] : 133 0x85 (T L P) = (3 0 5 ) DATA_LANE [8] + 0x011E PORT_MEM_DBI_N [0] : 6 0x06 (T L P) = (0 0 6 ) DATA_LANE [0] + 0x011F PORT_MEM_DBI_N [1] : 22 0x16 (T L P) = (0 1 6 ) DATA_LANE [1] + 0x0120 PORT_MEM_DBI_N [2] : 38 0x26 (T L P) = (0 2 6 ) DATA_LANE [2] + 0x0121 PORT_MEM_DBI_N [3] : 54 0x36 (T L P) = (0 3 6 ) DATA_LANE [3] + 0x0122 PORT_MEM_DBI_N [4] : 70 0x46 (T L P) = (2 0 6 ) DATA_LANE [4] + 0x0123 PORT_MEM_DBI_N [5] : 86 0x56 (T L P) = (2 1 6 ) DATA_LANE [5] + 0x0124 PORT_MEM_DBI_N [6] : 102 0x66 (T L P) = (2 2 6 ) DATA_LANE [6] + 0x0125 PORT_MEM_DBI_N [7] : 118 0x76 (T L P) = (2 3 6 ) DATA_LANE [7] + 0x0126 PORT_MEM_DBI_N [8] : 134 0x86 (T L P) = (3 0 6 ) DATA_LANE [8] + 0x0127 PORT_MEM_DQ [0] : 0 0x00 (T L P) = (0 0 0 ) DATA_LANE [0] + 0x0128 PORT_MEM_DQ [1] : 1 0x01 (T L P) = (0 0 1 ) DATA_LANE [0] + 0x0129 PORT_MEM_DQ [2] : 2 0x02 (T L P) = (0 0 2 ) DATA_LANE [0] + 0x012A PORT_MEM_DQ [3] : 3 0x03 (T L P) = (0 0 3 ) DATA_LANE [0] + 0x012B PORT_MEM_DQ [4] : 8 0x08 (T L P) = (0 0 8 ) DATA_LANE [0] + 0x012C PORT_MEM_DQ [5] : 9 0x09 (T L P) = (0 0 9 ) DATA_LANE [0] + 0x012D PORT_MEM_DQ [6] : 10 0x0A (T L P) = (0 0 10) DATA_LANE [0] + 0x012E PORT_MEM_DQ [7] : 11 0x0B (T L P) = (0 0 11) DATA_LANE [0] + 0x012F PORT_MEM_DQ [8] : 16 0x10 (T L P) = (0 1 0 ) DATA_LANE [1] + 0x0130 PORT_MEM_DQ [9] : 17 0x11 (T L P) = (0 1 1 ) DATA_LANE [1] + 0x0131 PORT_MEM_DQ [10] : 18 0x12 (T L P) = (0 1 2 ) DATA_LANE [1] + 0x0132 PORT_MEM_DQ [11] : 19 0x13 (T L P) = (0 1 3 ) DATA_LANE [1] + 0x0133 PORT_MEM_DQ [12] : 24 0x18 (T L P) = (0 1 8 ) DATA_LANE [1] + 0x0134 PORT_MEM_DQ [13] : 25 0x19 (T L P) = (0 1 9 ) DATA_LANE [1] + 0x0135 PORT_MEM_DQ [14] : 26 0x1A (T L P) = (0 1 10) DATA_LANE [1] + 0x0136 PORT_MEM_DQ [15] : 27 0x1B (T L P) = (0 1 11) DATA_LANE [1] + 0x0137 PORT_MEM_DQ [16] : 32 0x20 (T L P) = (0 2 0 ) DATA_LANE [2] + 0x0138 PORT_MEM_DQ [17] : 33 0x21 (T L P) = (0 2 1 ) DATA_LANE [2] + 0x0139 PORT_MEM_DQ [18] : 34 0x22 (T L P) = (0 2 2 ) DATA_LANE [2] + 0x013A PORT_MEM_DQ [19] : 35 0x23 (T L P) = (0 2 3 ) DATA_LANE [2] + 0x013B PORT_MEM_DQ [20] : 40 0x28 (T L P) = (0 2 8 ) DATA_LANE [2] + 0x013C PORT_MEM_DQ [21] : 41 0x29 (T L P) = (0 2 9 ) DATA_LANE [2] + 0x013D PORT_MEM_DQ [22] : 42 0x2A (T L P) = (0 2 10) DATA_LANE [2] + 0x013E PORT_MEM_DQ [23] : 43 0x2B (T L P) = (0 2 11) DATA_LANE [2] + 0x013F PORT_MEM_DQ [24] : 48 0x30 (T L P) = (0 3 0 ) DATA_LANE [3] + 0x0140 PORT_MEM_DQ [25] : 49 0x31 (T L P) = (0 3 1 ) DATA_LANE [3] + 0x0141 PORT_MEM_DQ [26] : 50 0x32 (T L P) = (0 3 2 ) DATA_LANE [3] + 0x0142 PORT_MEM_DQ [27] : 51 0x33 (T L P) = (0 3 3 ) DATA_LANE [3] + 0x0143 PORT_MEM_DQ [28] : 56 0x38 (T L P) = (0 3 8 ) DATA_LANE [3] + 0x0144 PORT_MEM_DQ [29] : 57 0x39 (T L P) = (0 3 9 ) DATA_LANE [3] + 0x0145 PORT_MEM_DQ [30] : 58 0x3A (T L P) = (0 3 10) DATA_LANE [3] + 0x0146 PORT_MEM_DQ [31] : 59 0x3B (T L P) = (0 3 11) DATA_LANE [3] + 0x0147 PORT_MEM_DQ [32] : 64 0x40 (T L P) = (2 0 0 ) DATA_LANE [4] + 0x0148 PORT_MEM_DQ [33] : 65 0x41 (T L P) = (2 0 1 ) DATA_LANE [4] + 0x0149 PORT_MEM_DQ [34] : 66 0x42 (T L P) = (2 0 2 ) DATA_LANE [4] + 0x014A PORT_MEM_DQ [35] : 67 0x43 (T L P) = (2 0 3 ) DATA_LANE [4] + 0x014B PORT_MEM_DQ [36] : 72 0x48 (T L P) = (2 0 8 ) DATA_LANE [4] + 0x014C PORT_MEM_DQ [37] : 73 0x49 (T L P) = (2 0 9 ) DATA_LANE [4] + 0x014D PORT_MEM_DQ [38] : 74 0x4A (T L P) = (2 0 10) DATA_LANE [4] + 0x014E PORT_MEM_DQ [39] : 75 0x4B (T L P) = (2 0 11) DATA_LANE [4] + 0x014F PORT_MEM_DQ [40] : 80 0x50 (T L P) = (2 1 0 ) DATA_LANE [5] + 0x0150 PORT_MEM_DQ [41] : 81 0x51 (T L P) = (2 1 1 ) DATA_LANE [5] + 0x0151 PORT_MEM_DQ [42] : 82 0x52 (T L P) = (2 1 2 ) DATA_LANE [5] + 0x0152 PORT_MEM_DQ [43] : 83 0x53 (T L P) = (2 1 3 ) DATA_LANE [5] + 0x0153 PORT_MEM_DQ [44] : 88 0x58 (T L P) = (2 1 8 ) DATA_LANE [5] + 0x0154 PORT_MEM_DQ [45] : 89 0x59 (T L P) = (2 1 9 ) DATA_LANE [5] + 0x0155 PORT_MEM_DQ [46] : 90 0x5A (T L P) = (2 1 10) DATA_LANE [5] + 0x0156 PORT_MEM_DQ [47] : 91 0x5B (T L P) = (2 1 11) DATA_LANE [5] + 0x0157 PORT_MEM_DQ [48] : 96 0x60 (T L P) = (2 2 0 ) DATA_LANE [6] + 0x0158 PORT_MEM_DQ [49] : 97 0x61 (T L P) = (2 2 1 ) DATA_LANE [6] + 0x0159 PORT_MEM_DQ [50] : 98 0x62 (T L P) = (2 2 2 ) DATA_LANE [6] + 0x015A PORT_MEM_DQ [51] : 99 0x63 (T L P) = (2 2 3 ) DATA_LANE [6] + 0x015B PORT_MEM_DQ [52] : 104 0x68 (T L P) = (2 2 8 ) DATA_LANE [6] + 0x015C PORT_MEM_DQ [53] : 105 0x69 (T L P) = (2 2 9 ) DATA_LANE [6] + 0x015D PORT_MEM_DQ [54] : 106 0x6A (T L P) = (2 2 10) DATA_LANE [6] + 0x015E PORT_MEM_DQ [55] : 107 0x6B (T L P) = (2 2 11) DATA_LANE [6] + 0x015F PORT_MEM_DQ [56] : 112 0x70 (T L P) = (2 3 0 ) DATA_LANE [7] + 0x0160 PORT_MEM_DQ [57] : 113 0x71 (T L P) = (2 3 1 ) DATA_LANE [7] + 0x0161 PORT_MEM_DQ [58] : 114 0x72 (T L P) = (2 3 2 ) DATA_LANE [7] + 0x0162 PORT_MEM_DQ [59] : 115 0x73 (T L P) = (2 3 3 ) DATA_LANE [7] + 0x0163 PORT_MEM_DQ [60] : 120 0x78 (T L P) = (2 3 8 ) DATA_LANE [7] + 0x0164 PORT_MEM_DQ [61] : 121 0x79 (T L P) = (2 3 9 ) DATA_LANE [7] + 0x0165 PORT_MEM_DQ [62] : 122 0x7A (T L P) = (2 3 10) DATA_LANE [7] + 0x0166 PORT_MEM_DQ [63] : 123 0x7B (T L P) = (2 3 11) DATA_LANE [7] + 0x0167 PORT_MEM_DQ [64] : 128 0x80 (T L P) = (3 0 0 ) DATA_LANE [8] + 0x0168 PORT_MEM_DQ [65] : 129 0x81 (T L P) = (3 0 1 ) DATA_LANE [8] + 0x0169 PORT_MEM_DQ [66] : 130 0x82 (T L P) = (3 0 2 ) DATA_LANE [8] + 0x016A PORT_MEM_DQ [67] : 131 0x83 (T L P) = (3 0 3 ) DATA_LANE [8] + 0x016B PORT_MEM_DQ [68] : 136 0x88 (T L P) = (3 0 8 ) DATA_LANE [8] + 0x016C PORT_MEM_DQ [69] : 137 0x89 (T L P) = (3 0 9 ) DATA_LANE [8] + 0x016D PORT_MEM_DQ [70] : 138 0x8A (T L P) = (3 0 10) DATA_LANE [8] + 0x016E PORT_MEM_DQ [71] : 139 0x8B (T L P) = (3 0 11) DATA_LANE [8] + 0x016F ALIGN_PAD : 0 0x00 + 0x7463 SEQ_PT_MR_PTR : 368 0x0170 + 0x0170 MR0 : 2164 0x00000874 00000000100001110100 + 0x0174 MR1 : 65537 0x00010001 00010000000000000001 + 0x0178 MR2 : 131112 0x00020028 00100000000000101000 + 0x017C MR3 : 197632 0x00030400 00110000010000000000 + 0x0180 MR4 : 264192 0x00040800 01000000100000000000 + 0x0184 MR5 : 332896 0x00051460 01010001010001100000 + 0x0188 MR6 : 395279 0x0006080F 01100000100000001111 + 0x018C RDIMM CONTROL WORD : 257253376 0x0F556000 00001111010101010110000000000000 + 0x0190 RDIMM CONTROL WORD : 222298891 0x0D40030B 00001101010000000000001100001011 + 0x0194 RDIMM CONTROL WORD : 3735552 0x00390000 00000000001110010000000000000000 + 0x0198 RDIMM CONTROL WORD : 536870912 0x20000000 00100000000000000000000000000000 + 0x019C RDIMM CONTROL WORD : 0 0x00000000 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b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_top.sv @@ -0,0 +1,4041 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +/////////////////////////////////////////////////////////////////////////////// +// Top-level wrapper of 10nm hardened EMIF component. +// +/////////////////////////////////////////////////////////////////////////////// + +module ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_top #( + + // Interface properties + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter PHY_CONFIG_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter IS_HPS = 0, + parameter PHY_TARGET_IS_ES = 0, + parameter PHY_TARGET_IS_ES2 = 0, + parameter PHY_TARGET_IS_PRODUCTION = 1, + parameter SILICON_REV = "", + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter DQS_BUS_MODE_ENUM = "", + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + parameter PHY_MIMIC_HPS_EMIF = 0, + + // Core logic related properties + parameter REGISTER_AFI_C2P = 0, + parameter REGISTER_AFI_P2C = 0, + parameter REGISTER_AMM_C2P = 0, + parameter REGISTER_AMM_P2C = 0, + + // Parameter to turn connect phylite core signals to the lane atoms + parameter GENERATE_PHYLITE = 0, + + // OCT-related properties + parameter PHY_CALIBRATED_OCT = 1, + parameter PHY_AC_CALIBRATED_OCT = 1, + parameter PHY_CK_CALIBRATED_OCT = 1, + parameter PHY_DATA_CALIBRATED_OCT = 1, + parameter PHY_USERMODE_OCT = 1, + parameter PHY_PERIODIC_OCT_RECAL = 1, + + parameter HPRX_CTLE_EN = "on", + parameter HPRX_OFFSET_CAL = "true", + + // Debug parameters + parameter DIAG_SIM_REGTEST_MODE = 0, + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_SIM_VERBOSE_LEVEL = 2, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 1, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_SEQ_RESET_AUTO_RELEASE = "avl", + parameter DIAG_DB_RESET_AUTO_RELEASE = "avl_release", + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 3, + parameter DIAG_ABSTRACT_PHY_RLAT = 8, + parameter ABPHY_WRITE_PROTOCOL = 1, + + // Parameter table params + parameter SEQ_USE_SIM_PARAMS = "", + parameter SEQ_PT_SIM_CONTENT = "", + parameter SEQ_PT_SYN_CONTENT = "", + + // Calbus parameters + parameter PORT_CALBUS_ADDRESS_WIDTH = 1, + parameter PORT_CALBUS_RDATA_WIDTH = 1, + parameter PORT_CALBUS_WDATA_WIDTH = 1, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 1, + + // Family traits + parameter LANES_PER_TILE = 1, + parameter PINS_PER_LANE = 1, + parameter OCT_CONTROL_WIDTH = 1, + + // PLL parameters + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_VCO_FREQ_MHZ_STR = "", + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_MEM_CLK_FREQ_PS = 0, + parameter PLL_PHY_CLK_VCO_PHASE = 0, + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_REF_CLK_FREQ_MHZ_STR = "", + parameter PLL_REF_CLK_FREQ_MHZ_INT = 0, + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_OUT_EN_8 = "", + + parameter PLL_C_CNT_FREQ_MHZ_STR_0 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_1 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_2 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_3 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_4 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_5 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_6 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_7 = "", + parameter PLL_C_CNT_FREQ_MHZ_STR_8 = "", + + // CPA parameters + parameter CPA_FB_MUX_1_SEL = "", + + // Parameters describing HMC configuration + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter HMC_READY_LATENCY = 0, + + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter PRI_HMC_CFG_CS_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_COL_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_RC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_RC = "", + parameter PRI_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter PRI_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter PRI_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter [ 1: 0] PRI_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter [ 1: 0] PRI_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter [ 31: 0] PRI_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter [ 31: 0] PRI_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 31: 0] PRI_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter PRI_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 7: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter [ 31: 0] PRI_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter PRI_HMC_CFG_DQSTRK_EN = "", + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 31: 0] PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter [ 31: 0] PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter [ 31: 0] PRI_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 7: 0] PRI_HMC_MEMCLKGATE_SETTING = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_AL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCCD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCCD_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCKESR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCKSRX = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TCWL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TDQSCKMAX = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TFAW = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TMOD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TPL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRAS = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRCD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TREFI = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRFC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRRD = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRRD_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TRTP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_S = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXP = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXPDLL = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TXSR = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TZQCS = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_TZQOPER = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_WR_CRC = 0, + parameter [ 31: 0] PRI_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 9: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter [ 1: 0] PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter [ 31: 0] PRI_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter [ 31: 0] PRI_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 31: 0] PRI_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter PRI_HMC_CFG_MAJOR_MODE_EN = "", + parameter [ 1: 0] PRI_HMC_CFG_REFRESH_TYPE = 0, + parameter PRI_HMC_CFG_POST_REFRESH_EN = "", + parameter [ 4: 0] PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter [ 4: 0] PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter PRI_HMC_CFG_PRE_REFRESH_EN = "", + parameter [ 3: 0] PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter [ 8: 0] PRI_HMC_CHIP_ID = 0, + parameter [ 1: 0] PRI_HMC_CID_ADDR_WIDTH = 0, + parameter PRI_HMC_3DS_EN = "", + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM0 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM1 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM2 = 0, + parameter [ 3: 0] PRI_HMC_3DS_LR_NUM3 = 0, + parameter PRI_HMC_3DS_PR_STAG_ENABLE = "", + parameter [ 6: 0] PRI_HMC_3DS_REF2REF_DLR = 0, + parameter PRI_HMC_3DSREF_ACK_ON_DONE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter SEC_HMC_CFG_CS_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_COL_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ROW_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_RC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_RC = "", + parameter SEC_HMC_CFG_CTRL_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC0_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC1_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC2_ENABLE_ECC = "", + parameter SEC_HMC_CFG_DBC3_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_CTRL_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC0_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC1_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC2_REORDER_RDATA = "", + parameter SEC_HMC_CFG_DBC3_REORDER_RDATA = "", + parameter [ 1: 0] SEC_HMC_CFG_CTRL_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC0_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC1_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC2_SLOT_OFFSET = 0, + parameter [ 1: 0] SEC_HMC_CFG_DBC3_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN = "", + parameter SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN = "", + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter [ 31: 0] SEC_HMC_CFG_ROW_TO_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_ROW_TO_ROW_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_COL_TO_ROW_OFFSET = 0, + parameter [ 31: 0] SEC_HMC_CFG_SIDEBAND_OFFSET = 0, + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 31: 0] SEC_HMC_CFG_CTL_ODT_ENABLED = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter SEC_HMC_CFG_CMD_FIFO_RESERVE_EN = "", + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 7: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter [ 31: 0] SEC_HMC_CFG_PHY_DELAY_MISMATCH = 0, + parameter SEC_HMC_CFG_DQSTRK_EN = "", + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 31: 0] SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN = 0, + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter [ 31: 0] SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD = 0, + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter [ 31: 0] SEC_HMC_CFG_MEM_AUTO_PD_CYCLES = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 7: 0] SEC_HMC_MEMCLKGATE_SETTING = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_AL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_CS_PER_DIMM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_RD_PREAMBLE = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCCD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCCD_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCKESR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCKSRX = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TCWL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TDQSCKMAX = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TFAW = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TMOD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TPL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRAS = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRCD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TREFI = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRFC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRRD = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRRD_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TRTP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWR_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_L_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_S = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TWTR_S_CRC_DM = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXP = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXPDLL = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TXSR = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TZQCS = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_TZQOPER = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_WR_CRC = 0, + parameter [ 31: 0] SEC_HMC_MEM_IF_WR_PREAMBLE = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 9: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter [ 1: 0] SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter [ 31: 0] SEC_HMC_TEMP_4_ACT_TO_ACT = 0, + parameter [ 31: 0] SEC_HMC_TEMP_RD_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD_DIFF_BG = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 31: 0] SEC_HMC_TEMP_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter SEC_HMC_CFG_MAJOR_MODE_EN = "", + parameter [ 1: 0] SEC_HMC_CFG_REFRESH_TYPE = 0, + parameter SEC_HMC_CFG_POST_REFRESH_EN = "", + parameter [ 4: 0] SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT = 0, + parameter [ 4: 0] SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT = 0, + parameter SEC_HMC_CFG_PRE_REFRESH_EN = "", + parameter [ 3: 0] SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT = 0, + parameter [ 8: 0] SEC_HMC_CHIP_ID = 0, + parameter [ 1: 0] SEC_HMC_CID_ADDR_WIDTH = 0, + parameter SEC_HMC_3DS_EN = "", + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM0 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM1 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM2 = 0, + parameter [ 3: 0] SEC_HMC_3DS_LR_NUM3 = 0, + parameter SEC_HMC_3DS_PR_STAG_ENABLE = "", + parameter [ 6: 0] SEC_HMC_3DS_REF2REF_DLR = 0, + parameter SEC_HMC_3DSREF_ACK_ON_DONE = "", + + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = 1, + parameter DQSA_LGC_MODE = "", + parameter DQSB_LGC_MODE = "", + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter [10:0] DLL_CODEWORD = 0, + + // Parameters describing logical tile/lane/pin allocation in the RTL + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + + // Parameters describing UFI configurations in the RTL + parameter AMM_C2P_UFI_MODE = "", + parameter AMM_P2C_UFI_MODE = "", + parameter MMR_C2P_UFI_MODE = "", + parameter MMR_P2C_UFI_MODE = "", + parameter SIDEBAND_C2P_UFI_MODE = "", + parameter SIDEBAND_P2C_UFI_MODE = "", + parameter SEQ_C2P_UFI_MODE = "", + parameter SEQ_P2C_UFI_MODE = "", + parameter ECC_C2P_UFI_MODE = "", + parameter ECC_P2C_UFI_MODE = "", + parameter LANE_C2P_UFI_MODE = "", + parameter LANE_P2C_UFI_MODE = "", + parameter AMM_HIPI_DELAY = 225, + parameter MMR_HIPI_DELAY = 225, + parameter SIDEBAND_HIPI_DELAY = 225, + parameter SEQ_HIPI_DELAY = 225, + parameter ECC_HIPI_DELAY = 225, + parameter LANE_HIPI_DELAY = 225, + parameter ENABLE_RD_TYPE = 0, + + // Definition of port widhts for "clks_sharing_master_out" interface + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 1, + + // Definition of port widhts for "clks_sharing_slave_in" interface + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 1, + + // Definition of port widhts for "clks_sharing_slave_out" interface + parameter PORT_CLKS_SHARING_SLAVE_OUT_WIDTH = 1, + + // Definition of port widths for "mem" interface + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_CK_BIDIR_WIDTH = 1, + parameter PORT_MEM_CK_BIDIR_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_GNT_N_WIDTH = 1, + parameter PORT_MEM_REQ_N_WIDTH = 1, + parameter PORT_MEM_ERR_N_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + // Definition of port widths for "afi" interface + //AUTOGEN_BEGIN: Definition of afi port widths + parameter PORT_AFI_RLAT_WIDTH = 1, + parameter PORT_AFI_WLAT_WIDTH = 1, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 1, + parameter PORT_AFI_ADDR_WIDTH = 1, + parameter PORT_AFI_BA_WIDTH = 1, + parameter PORT_AFI_BG_WIDTH = 1, + parameter PORT_AFI_C_WIDTH = 1, + parameter PORT_AFI_CKE_WIDTH = 1, + parameter PORT_AFI_CS_N_WIDTH = 1, + parameter PORT_AFI_RM_WIDTH = 1, + parameter PORT_AFI_ODT_WIDTH = 1, + parameter PORT_AFI_GNT_N_WIDTH = 1, + parameter PORT_AFI_REQ_N_WIDTH = 1, + parameter PORT_AFI_ERR_N_WIDTH = 1, + parameter PORT_AFI_RAS_N_WIDTH = 1, + parameter PORT_AFI_CAS_N_WIDTH = 1, + parameter PORT_AFI_WE_N_WIDTH = 1, + parameter PORT_AFI_RST_N_WIDTH = 1, + parameter PORT_AFI_ACT_N_WIDTH = 1, + parameter PORT_AFI_PAR_WIDTH = 1, + parameter PORT_AFI_CA_WIDTH = 1, + parameter PORT_AFI_REF_N_WIDTH = 1, + parameter PORT_AFI_WPS_N_WIDTH = 1, + parameter PORT_AFI_RPS_N_WIDTH = 1, + parameter PORT_AFI_DOFF_N_WIDTH = 1, + parameter PORT_AFI_LD_N_WIDTH = 1, + parameter PORT_AFI_RW_N_WIDTH = 1, + parameter PORT_AFI_LBK0_N_WIDTH = 1, + parameter PORT_AFI_LBK1_N_WIDTH = 1, + parameter PORT_AFI_CFG_N_WIDTH = 1, + parameter PORT_AFI_AP_WIDTH = 1, + parameter PORT_AFI_AINV_WIDTH = 1, + parameter PORT_AFI_DM_WIDTH = 1, + parameter PORT_AFI_DM_N_WIDTH = 1, + parameter PORT_AFI_BWS_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DINV_WIDTH = 1, + parameter PORT_AFI_WDATA_DINV_WIDTH = 1, + parameter PORT_AFI_DQS_BURST_WIDTH = 1, + parameter PORT_AFI_WDATA_VALID_WIDTH = 1, + parameter PORT_AFI_WDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 1, + parameter PORT_AFI_RDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_VALID_WIDTH = 1, + parameter PORT_AFI_RRANK_WIDTH = 1, + parameter PORT_AFI_WRANK_WIDTH = 1, + parameter PORT_AFI_ALERT_N_WIDTH = 1, + parameter PORT_AFI_PE_N_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_cmd" interface + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_wr" interface + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_rd" interface + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_amm" interface + parameter PORT_CTRL_AMM_RDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 1, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 1, + + // Definition of port widths for "phylite" interface + parameter PORT_CTRL_STROBE_WIDTH = 1, + parameter PORT_CTRL_STROBE_OE_WIDTH = 1, + parameter PORT_CTRL_DATA_OE_WIDTH = 1, + parameter PORT_CTRL_DATA_OUT_WIDTH = 1, + parameter PORT_CTRL_DATA_IN_WIDTH = 1, + parameter PORT_CTRL_RDATA_VALID_WIDTH = 1, + parameter PORT_CTRL_RDATA_ENABLE_WIDTH = 1, + parameter PORT_CTRL_LOCKED_WIDTH = 1, + + // Definition of port widths for "ctrl_user_refresh" interface + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 1, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 1, + + // Definition of port widths for "ctrl_self_refresh" interface + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 1, + + // Definition of port widths for "ctrl_ecc" interface + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 1, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 1, + + // Definition of port widths for "ctrl_mmr" interface + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 1, + + // Definition of port widths for "hps_emif" interface + parameter PORT_HPS_EMIF_H2E_WIDTH = 1, + parameter PORT_HPS_EMIF_E2H_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 2, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 1, + + // Definition of port widths for "cal_debug" interface + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + + // Definition of port widths for "dft_nd" interface + parameter PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH = 1, + parameter PORT_DFT_ND_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH = 1, + parameter PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH = 1, + parameter PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH = 1, + + parameter LANES_USAGE_AUTOGEN_WCNT = 0, + parameter LANES_USAGE_3 = 1'b0, + parameter LANES_USAGE_2 = 1'b0, + parameter LANES_USAGE_1 = 1'b0, + parameter LANES_USAGE_0 = 1'b0, + parameter PINS_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_USAGE_12 = 1'b0, + parameter PINS_USAGE_11 = 1'b0, + parameter PINS_USAGE_10 = 1'b0, + parameter PINS_USAGE_9 = 1'b0, + parameter PINS_USAGE_8 = 1'b0, + parameter PINS_USAGE_7 = 1'b0, + parameter PINS_USAGE_6 = 1'b0, + parameter PINS_USAGE_5 = 1'b0, + parameter PINS_USAGE_4 = 1'b0, + parameter PINS_USAGE_3 = 1'b0, + parameter PINS_USAGE_2 = 1'b0, + parameter PINS_USAGE_1 = 1'b0, + parameter PINS_USAGE_0 = 1'b0, + parameter PINS_RATE_AUTOGEN_WCNT = 0, + parameter PINS_RATE_12 = 1'b0, + parameter PINS_RATE_11 = 1'b0, + parameter PINS_RATE_10 = 1'b0, + parameter PINS_RATE_9 = 1'b0, + parameter PINS_RATE_8 = 1'b0, + parameter PINS_RATE_7 = 1'b0, + parameter PINS_RATE_6 = 1'b0, + parameter PINS_RATE_5 = 1'b0, + parameter PINS_RATE_4 = 1'b0, + parameter PINS_RATE_3 = 1'b0, + parameter PINS_RATE_2 = 1'b0, + parameter PINS_RATE_1 = 1'b0, + parameter PINS_RATE_0 = 1'b0, + parameter LANE_PIN_USAGE_AUTOGEN_WCNT = 0, + parameter LANE_PIN_USAGE_0 = 0, + parameter LANE_PIN_USAGE_1 = 0, + parameter LANE_PIN_USAGE_2 = 0, + parameter LANE_PIN_USAGE_3 = 0, + parameter LANE_PIN_USAGE_4 = 0, + parameter LANE_PIN_USAGE_5 = 0, + parameter LANE_PIN_USAGE_6 = 0, + parameter LANE_PIN_USAGE_7 = 0, + parameter LANE_PIN_USAGE_8 = 0, + parameter LANE_PIN_USAGE_9 = 0, + parameter LANE_PIN_USAGE_10 = 0, + parameter LANE_PIN_USAGE_11 = 0, + parameter LANE_PIN_USAGE_12 = 0, + parameter LANE_PIN_USAGE_13 = 0, + parameter LANE_PIN_USAGE_14 = 0, + parameter LANE_PIN_USAGE_15 = 0, + parameter LANE_PIN_USAGE_16 = 0, + parameter LANE_PIN_USAGE_17 = 0, + parameter LANE_PIN_USAGE_18 = 0, + parameter LANE_PIN_USAGE_19 = 0, + parameter LANE_PIN_USAGE_20 = 0, + parameter LANE_PIN_USAGE_21 = 0, + parameter LANE_PIN_USAGE_22 = 0, + parameter LANE_PIN_USAGE_23 = 0, + parameter LANE_PIN_USAGE_24 = 0, + parameter LANE_PIN_USAGE_25 = 0, + parameter LANE_PIN_USAGE_26 = 0, + parameter LANE_PIN_USAGE_27 = 0, + parameter LANE_PIN_USAGE_28 = 0, + parameter LANE_PIN_USAGE_29 = 0, + parameter LANE_PIN_USAGE_30 = 0, + parameter LANE_PIN_USAGE_31 = 0, + parameter LANE_PIN_USAGE_32 = 0, + parameter LANE_PIN_USAGE_33 = 0, + parameter LANE_PIN_USAGE_34 = 0, + parameter LANE_PIN_USAGE_35 = 0, + parameter LANE_PIN_USAGE_36 = 0, + parameter LANE_PIN_USAGE_37 = 0, + parameter LANE_PIN_USAGE_38 = 0, + parameter LANE_PIN_USAGE_39 = 0, + parameter LANE_PIN_USAGE_40 = 0, + parameter LANE_PIN_USAGE_41 = 0, + parameter LANE_PIN_USAGE_42 = 0, + parameter LANE_PIN_USAGE_43 = 0, + parameter LANE_PIN_USAGE_44 = 0, + parameter LANE_PIN_USAGE_45 = 0, + parameter LANE_PIN_USAGE_46 = 0, + parameter LANE_PIN_USAGE_47 = 0, + parameter LANE_PIN_USAGE_48 = 0, + parameter LANE_PIN_USAGE_49 = 0, + parameter LANE_PIN_USAGE_50 = 0, + parameter LANE_PIN_USAGE_51 = 0, + parameter DB_PINS_PROC_MODE_AUTOGEN_WCNT = 0, + parameter DB_PINS_PROC_MODE_63 = 1'b0, + parameter DB_PINS_PROC_MODE_62 = 1'b0, + parameter DB_PINS_PROC_MODE_61 = 1'b0, + parameter DB_PINS_PROC_MODE_60 = 1'b0, + parameter DB_PINS_PROC_MODE_59 = 1'b0, + parameter DB_PINS_PROC_MODE_58 = 1'b0, + parameter DB_PINS_PROC_MODE_57 = 1'b0, + parameter DB_PINS_PROC_MODE_56 = 1'b0, + parameter DB_PINS_PROC_MODE_55 = 1'b0, + parameter DB_PINS_PROC_MODE_54 = 1'b0, + parameter DB_PINS_PROC_MODE_53 = 1'b0, + parameter DB_PINS_PROC_MODE_52 = 1'b0, + parameter DB_PINS_PROC_MODE_51 = 1'b0, + parameter DB_PINS_PROC_MODE_50 = 1'b0, + parameter DB_PINS_PROC_MODE_49 = 1'b0, + parameter DB_PINS_PROC_MODE_48 = 1'b0, + parameter DB_PINS_PROC_MODE_47 = 1'b0, + parameter DB_PINS_PROC_MODE_46 = 1'b0, + parameter DB_PINS_PROC_MODE_45 = 1'b0, + parameter DB_PINS_PROC_MODE_44 = 1'b0, + parameter DB_PINS_PROC_MODE_43 = 1'b0, + parameter DB_PINS_PROC_MODE_42 = 1'b0, + parameter DB_PINS_PROC_MODE_41 = 1'b0, + parameter DB_PINS_PROC_MODE_40 = 1'b0, + parameter DB_PINS_PROC_MODE_39 = 1'b0, + parameter DB_PINS_PROC_MODE_38 = 1'b0, + parameter DB_PINS_PROC_MODE_37 = 1'b0, + parameter DB_PINS_PROC_MODE_36 = 1'b0, + parameter DB_PINS_PROC_MODE_35 = 1'b0, + parameter DB_PINS_PROC_MODE_34 = 1'b0, + parameter DB_PINS_PROC_MODE_33 = 1'b0, + parameter DB_PINS_PROC_MODE_32 = 1'b0, + parameter DB_PINS_PROC_MODE_31 = 1'b0, + parameter DB_PINS_PROC_MODE_30 = 1'b0, + parameter DB_PINS_PROC_MODE_29 = 1'b0, + parameter DB_PINS_PROC_MODE_28 = 1'b0, + parameter DB_PINS_PROC_MODE_27 = 1'b0, + parameter DB_PINS_PROC_MODE_26 = 1'b0, + parameter DB_PINS_PROC_MODE_25 = 1'b0, + parameter DB_PINS_PROC_MODE_24 = 1'b0, + parameter DB_PINS_PROC_MODE_23 = 1'b0, + parameter DB_PINS_PROC_MODE_22 = 1'b0, + parameter DB_PINS_PROC_MODE_21 = 1'b0, + parameter DB_PINS_PROC_MODE_20 = 1'b0, + parameter DB_PINS_PROC_MODE_19 = 1'b0, + parameter DB_PINS_PROC_MODE_18 = 1'b0, + parameter DB_PINS_PROC_MODE_17 = 1'b0, + parameter DB_PINS_PROC_MODE_16 = 1'b0, + parameter DB_PINS_PROC_MODE_15 = 1'b0, + parameter DB_PINS_PROC_MODE_14 = 1'b0, + parameter DB_PINS_PROC_MODE_13 = 1'b0, + parameter DB_PINS_PROC_MODE_12 = 1'b0, + parameter DB_PINS_PROC_MODE_11 = 1'b0, + parameter DB_PINS_PROC_MODE_10 = 1'b0, + parameter DB_PINS_PROC_MODE_9 = 1'b0, + parameter DB_PINS_PROC_MODE_8 = 1'b0, + parameter DB_PINS_PROC_MODE_7 = 1'b0, + parameter DB_PINS_PROC_MODE_6 = 1'b0, + parameter DB_PINS_PROC_MODE_5 = 1'b0, + parameter DB_PINS_PROC_MODE_4 = 1'b0, + parameter DB_PINS_PROC_MODE_3 = 1'b0, + parameter DB_PINS_PROC_MODE_2 = 1'b0, + parameter DB_PINS_PROC_MODE_1 = 1'b0, + parameter DB_PINS_PROC_MODE_0 = 1'b0, + parameter PINS_DATA_IN_MODE_AUTOGEN_WCNT = 0, + parameter PINS_DATA_IN_MODE_38 = 1'b0, + parameter PINS_DATA_IN_MODE_37 = 1'b0, + parameter PINS_DATA_IN_MODE_36 = 1'b0, + parameter PINS_DATA_IN_MODE_35 = 1'b0, + parameter PINS_DATA_IN_MODE_34 = 1'b0, + parameter PINS_DATA_IN_MODE_33 = 1'b0, + parameter PINS_DATA_IN_MODE_32 = 1'b0, + parameter PINS_DATA_IN_MODE_31 = 1'b0, + parameter PINS_DATA_IN_MODE_30 = 1'b0, + parameter PINS_DATA_IN_MODE_29 = 1'b0, + parameter PINS_DATA_IN_MODE_28 = 1'b0, + parameter PINS_DATA_IN_MODE_27 = 1'b0, + parameter PINS_DATA_IN_MODE_26 = 1'b0, + parameter PINS_DATA_IN_MODE_25 = 1'b0, + parameter PINS_DATA_IN_MODE_24 = 1'b0, + parameter PINS_DATA_IN_MODE_23 = 1'b0, + parameter PINS_DATA_IN_MODE_22 = 1'b0, + parameter PINS_DATA_IN_MODE_21 = 1'b0, + parameter PINS_DATA_IN_MODE_20 = 1'b0, + parameter PINS_DATA_IN_MODE_19 = 1'b0, + parameter PINS_DATA_IN_MODE_18 = 1'b0, + parameter PINS_DATA_IN_MODE_17 = 1'b0, + parameter PINS_DATA_IN_MODE_16 = 1'b0, + parameter PINS_DATA_IN_MODE_15 = 1'b0, + parameter PINS_DATA_IN_MODE_14 = 1'b0, + parameter PINS_DATA_IN_MODE_13 = 1'b0, + parameter PINS_DATA_IN_MODE_12 = 1'b0, + parameter PINS_DATA_IN_MODE_11 = 1'b0, + parameter PINS_DATA_IN_MODE_10 = 1'b0, + parameter PINS_DATA_IN_MODE_9 = 1'b0, + parameter PINS_DATA_IN_MODE_8 = 1'b0, + parameter PINS_DATA_IN_MODE_7 = 1'b0, + parameter PINS_DATA_IN_MODE_6 = 1'b0, + parameter PINS_DATA_IN_MODE_5 = 1'b0, + parameter PINS_DATA_IN_MODE_4 = 1'b0, + parameter PINS_DATA_IN_MODE_3 = 1'b0, + parameter PINS_DATA_IN_MODE_2 = 1'b0, + parameter PINS_DATA_IN_MODE_1 = 1'b0, + parameter PINS_DATA_IN_MODE_0 = 1'b0, + parameter PINS_C2L_DRIVEN_AUTOGEN_WCNT = 0, + parameter PINS_C2L_DRIVEN_12 = 1'b0, + parameter PINS_C2L_DRIVEN_11 = 1'b0, + parameter PINS_C2L_DRIVEN_10 = 1'b0, + parameter PINS_C2L_DRIVEN_9 = 1'b0, + parameter PINS_C2L_DRIVEN_8 = 1'b0, + parameter PINS_C2L_DRIVEN_7 = 1'b0, + parameter PINS_C2L_DRIVEN_6 = 1'b0, + parameter PINS_C2L_DRIVEN_5 = 1'b0, + parameter PINS_C2L_DRIVEN_4 = 1'b0, + parameter PINS_C2L_DRIVEN_3 = 1'b0, + parameter PINS_C2L_DRIVEN_2 = 1'b0, + parameter PINS_C2L_DRIVEN_1 = 1'b0, + parameter PINS_C2L_DRIVEN_0 = 1'b0, + parameter PINS_OCT_MODE_AUTOGEN_WCNT = 0, + parameter PINS_OCT_MODE_12 = 1'b0, + parameter PINS_OCT_MODE_11 = 1'b0, + parameter PINS_OCT_MODE_10 = 1'b0, + parameter PINS_OCT_MODE_9 = 1'b0, + parameter PINS_OCT_MODE_8 = 1'b0, + parameter PINS_OCT_MODE_7 = 1'b0, + parameter PINS_OCT_MODE_6 = 1'b0, + parameter PINS_OCT_MODE_5 = 1'b0, + parameter PINS_OCT_MODE_4 = 1'b0, + parameter PINS_OCT_MODE_3 = 1'b0, + parameter PINS_OCT_MODE_2 = 1'b0, + parameter PINS_OCT_MODE_1 = 1'b0, + parameter PINS_OCT_MODE_0 = 1'b0, + parameter PINS_DCC_SPLIT_AUTOGEN_WCNT = 0, + parameter PINS_DCC_SPLIT_12 = 1'b0, + parameter PINS_DCC_SPLIT_11 = 1'b0, + parameter PINS_DCC_SPLIT_10 = 1'b0, + parameter PINS_DCC_SPLIT_9 = 1'b0, + parameter PINS_DCC_SPLIT_8 = 1'b0, + parameter PINS_DCC_SPLIT_7 = 1'b0, + parameter PINS_DCC_SPLIT_6 = 1'b0, + parameter PINS_DCC_SPLIT_5 = 1'b0, + parameter PINS_DCC_SPLIT_4 = 1'b0, + parameter PINS_DCC_SPLIT_3 = 1'b0, + parameter PINS_DCC_SPLIT_2 = 1'b0, + parameter PINS_DCC_SPLIT_1 = 1'b0, + parameter PINS_DCC_SPLIT_0 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT = 0, + parameter UNUSED_MEM_PINS_PINLOC_128 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_127 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_126 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_125 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_124 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_123 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_122 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_121 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_120 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_119 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_118 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_117 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_116 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_115 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_114 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_113 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_112 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_111 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_110 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_109 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_108 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_107 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_106 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_105 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_104 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_103 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_102 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_101 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_100 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_99 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_98 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_97 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_96 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_95 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_94 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_93 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_92 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_91 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_90 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_89 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_88 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_87 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_86 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_85 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_84 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_83 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_82 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_81 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_80 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_79 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_78 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_77 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_76 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_75 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_74 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_73 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_72 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_71 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_70 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_69 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_68 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_67 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_66 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_65 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_64 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_63 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_62 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_61 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_60 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_59 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_58 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_57 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_56 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_55 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_54 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_53 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_52 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_51 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_50 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_49 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_48 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_47 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_46 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_45 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_44 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_43 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_42 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_41 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_40 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_39 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_38 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_37 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_36 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_35 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_34 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_33 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_32 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_31 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_30 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_29 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_28 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_27 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_26 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_25 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_24 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_23 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_22 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_21 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_20 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_19 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_18 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_17 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_16 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_15 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_14 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_13 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_12 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_11 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_10 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_9 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_8 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_7 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_6 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_5 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_4 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_3 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_2 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_1 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_0 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT = 0, + parameter UNUSED_DQS_BUSES_LANELOC_10 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_9 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_8 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_7 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_6 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_5 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_4 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_3 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_2 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_1 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_0 = 1'b0, + parameter DBC_EXTRA_PIPE_STAGE_EN = "", + parameter DBC_PIPE_LATS_AUTOGEN_WCNT = 0, + parameter DBC_PIPE_LATS_4 = 1'b0, + parameter DBC_PIPE_LATS_3 = 1'b0, + parameter DBC_PIPE_LATS_2 = 1'b0, + parameter DBC_PIPE_LATS_1 = 1'b0, + parameter DBC_PIPE_LATS_0 = 1'b0, + parameter DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT = 0, + parameter DB_PTR_PIPELINE_DEPTHS_4 = 1'b0, + parameter DB_PTR_PIPELINE_DEPTHS_3 = 1'b0, + parameter DB_PTR_PIPELINE_DEPTHS_2 = 1'b0, + parameter DB_PTR_PIPELINE_DEPTHS_1 = 1'b0, + parameter DB_PTR_PIPELINE_DEPTHS_0 = 1'b0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT= 0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_4 = 1'b0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_3 = 1'b0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_2 = 1'b0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_1 = 1'b0, + parameter DB_SEQ_RD_EN_FULL_PIPELINES_0 = 1'b0, + parameter CENTER_TIDS_AUTOGEN_WCNT = 0, + parameter CENTER_TIDS_2 = 1'b0, + parameter CENTER_TIDS_1 = 1'b0, + parameter CENTER_TIDS_0 = 1'b0, + parameter HMC_TIDS_AUTOGEN_WCNT = 0, + parameter HMC_TIDS_2 = 1'b0, + parameter HMC_TIDS_1 = 1'b0, + parameter HMC_TIDS_0 = 1'b0, + parameter LANE_TIDS_AUTOGEN_WCNT = 0, + parameter LANE_TIDS_9 = 1'b0, + parameter LANE_TIDS_8 = 1'b0, + parameter LANE_TIDS_7 = 1'b0, + parameter LANE_TIDS_6 = 1'b0, + parameter LANE_TIDS_5 = 1'b0, + parameter LANE_TIDS_4 = 1'b0, + parameter LANE_TIDS_3 = 1'b0, + parameter LANE_TIDS_2 = 1'b0, + parameter LANE_TIDS_1 = 1'b0, + parameter LANE_TIDS_0 = 1'b0, + parameter PORT_MEM_CK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_PINLOC_0 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_BIDIR_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_BIDIR_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_BIDIR_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_BIDIR_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_BIDIR_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_BIDIR_PINLOC_0 = 1'b0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_BIDIR_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_PINLOC_5 = 1'b0, + parameter PORT_MEM_DK_PINLOC_4 = 1'b0, + parameter PORT_MEM_DK_PINLOC_3 = 1'b0, + parameter PORT_MEM_DK_PINLOC_2 = 1'b0, + parameter PORT_MEM_DK_PINLOC_1 = 1'b0, + parameter PORT_MEM_DK_PINLOC_0 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_K_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_PINLOC_5 = 1'b0, + parameter PORT_MEM_K_PINLOC_4 = 1'b0, + parameter PORT_MEM_K_PINLOC_3 = 1'b0, + parameter PORT_MEM_K_PINLOC_2 = 1'b0, + parameter PORT_MEM_K_PINLOC_1 = 1'b0, + parameter PORT_MEM_K_PINLOC_0 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_A_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_A_PINLOC_16 = 1'b0, + parameter PORT_MEM_A_PINLOC_15 = 1'b0, + parameter PORT_MEM_A_PINLOC_14 = 1'b0, + parameter PORT_MEM_A_PINLOC_13 = 1'b0, + parameter PORT_MEM_A_PINLOC_12 = 1'b0, + parameter PORT_MEM_A_PINLOC_11 = 1'b0, + parameter PORT_MEM_A_PINLOC_10 = 1'b0, + parameter PORT_MEM_A_PINLOC_9 = 1'b0, + parameter PORT_MEM_A_PINLOC_8 = 1'b0, + parameter PORT_MEM_A_PINLOC_7 = 1'b0, + parameter PORT_MEM_A_PINLOC_6 = 1'b0, + parameter PORT_MEM_A_PINLOC_5 = 1'b0, + parameter PORT_MEM_A_PINLOC_4 = 1'b0, + parameter PORT_MEM_A_PINLOC_3 = 1'b0, + parameter PORT_MEM_A_PINLOC_2 = 1'b0, + parameter PORT_MEM_A_PINLOC_1 = 1'b0, + parameter PORT_MEM_A_PINLOC_0 = 1'b0, + parameter PORT_MEM_BA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BA_PINLOC_5 = 1'b0, + parameter PORT_MEM_BA_PINLOC_4 = 1'b0, + parameter PORT_MEM_BA_PINLOC_3 = 1'b0, + parameter PORT_MEM_BA_PINLOC_2 = 1'b0, + parameter PORT_MEM_BA_PINLOC_1 = 1'b0, + parameter PORT_MEM_BA_PINLOC_0 = 1'b0, + parameter PORT_MEM_BG_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BG_PINLOC_5 = 1'b0, + parameter PORT_MEM_BG_PINLOC_4 = 1'b0, + parameter PORT_MEM_BG_PINLOC_3 = 1'b0, + parameter PORT_MEM_BG_PINLOC_2 = 1'b0, + parameter PORT_MEM_BG_PINLOC_1 = 1'b0, + parameter PORT_MEM_BG_PINLOC_0 = 1'b0, + parameter PORT_MEM_C_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_C_PINLOC_5 = 1'b0, + parameter PORT_MEM_C_PINLOC_4 = 1'b0, + parameter PORT_MEM_C_PINLOC_3 = 1'b0, + parameter PORT_MEM_C_PINLOC_2 = 1'b0, + parameter PORT_MEM_C_PINLOC_1 = 1'b0, + parameter PORT_MEM_C_PINLOC_0 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CKE_PINLOC_5 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_4 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_3 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_2 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_1 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_0 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CS_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RM_PINLOC_5 = 1'b0, + parameter PORT_MEM_RM_PINLOC_4 = 1'b0, + parameter PORT_MEM_RM_PINLOC_3 = 1'b0, + parameter PORT_MEM_RM_PINLOC_2 = 1'b0, + parameter PORT_MEM_RM_PINLOC_1 = 1'b0, + parameter PORT_MEM_RM_PINLOC_0 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ODT_PINLOC_5 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_4 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_3 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_2 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_1 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_0 = 1'b0, + parameter PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_GNT_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_GNT_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_GNT_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_GNT_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_GNT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_GNT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REQ_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_REQ_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_REQ_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_REQ_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_REQ_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_REQ_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ERR_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_ERR_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_ERR_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_ERR_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_ERR_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ERR_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RAS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_RAS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CAS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CAS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WE_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_WE_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RESET_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_RESET_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ACT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ACT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PAR_PINLOC_1 = 1'b0, + parameter PORT_MEM_PAR_PINLOC_0 = 1'b0, + parameter PORT_MEM_CA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CA_PINLOC_16 = 1'b0, + parameter PORT_MEM_CA_PINLOC_15 = 1'b0, + parameter PORT_MEM_CA_PINLOC_14 = 1'b0, + parameter PORT_MEM_CA_PINLOC_13 = 1'b0, + parameter PORT_MEM_CA_PINLOC_12 = 1'b0, + parameter PORT_MEM_CA_PINLOC_11 = 1'b0, + parameter PORT_MEM_CA_PINLOC_10 = 1'b0, + parameter PORT_MEM_CA_PINLOC_9 = 1'b0, + parameter PORT_MEM_CA_PINLOC_8 = 1'b0, + parameter PORT_MEM_CA_PINLOC_7 = 1'b0, + parameter PORT_MEM_CA_PINLOC_6 = 1'b0, + parameter PORT_MEM_CA_PINLOC_5 = 1'b0, + parameter PORT_MEM_CA_PINLOC_4 = 1'b0, + parameter PORT_MEM_CA_PINLOC_3 = 1'b0, + parameter PORT_MEM_CA_PINLOC_2 = 1'b0, + parameter PORT_MEM_CA_PINLOC_1 = 1'b0, + parameter PORT_MEM_CA_PINLOC_0 = 1'b0, + parameter PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REF_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WPS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RPS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DOFF_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK0_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK1_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CFG_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_AP_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AP_PINLOC_0 = 1'b0, + parameter PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AINV_PINLOC_0 = 1'b0, + parameter PORT_MEM_DM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DM_PINLOC_12 = 1'b0, + parameter PORT_MEM_DM_PINLOC_11 = 1'b0, + parameter PORT_MEM_DM_PINLOC_10 = 1'b0, + parameter PORT_MEM_DM_PINLOC_9 = 1'b0, + parameter PORT_MEM_DM_PINLOC_8 = 1'b0, + parameter PORT_MEM_DM_PINLOC_7 = 1'b0, + parameter PORT_MEM_DM_PINLOC_6 = 1'b0, + parameter PORT_MEM_DM_PINLOC_5 = 1'b0, + parameter PORT_MEM_DM_PINLOC_4 = 1'b0, + parameter PORT_MEM_DM_PINLOC_3 = 1'b0, + parameter PORT_MEM_DM_PINLOC_2 = 1'b0, + parameter PORT_MEM_DM_PINLOC_1 = 1'b0, + parameter PORT_MEM_DM_PINLOC_0 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BWS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_D_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_D_PINLOC_48 = 1'b0, + parameter PORT_MEM_D_PINLOC_47 = 1'b0, + parameter PORT_MEM_D_PINLOC_46 = 1'b0, + parameter PORT_MEM_D_PINLOC_45 = 1'b0, + parameter PORT_MEM_D_PINLOC_44 = 1'b0, + parameter PORT_MEM_D_PINLOC_43 = 1'b0, + parameter PORT_MEM_D_PINLOC_42 = 1'b0, + parameter PORT_MEM_D_PINLOC_41 = 1'b0, + parameter PORT_MEM_D_PINLOC_40 = 1'b0, + parameter PORT_MEM_D_PINLOC_39 = 1'b0, + parameter PORT_MEM_D_PINLOC_38 = 1'b0, + parameter PORT_MEM_D_PINLOC_37 = 1'b0, + parameter PORT_MEM_D_PINLOC_36 = 1'b0, + parameter PORT_MEM_D_PINLOC_35 = 1'b0, + parameter PORT_MEM_D_PINLOC_34 = 1'b0, + parameter PORT_MEM_D_PINLOC_33 = 1'b0, + parameter PORT_MEM_D_PINLOC_32 = 1'b0, + parameter PORT_MEM_D_PINLOC_31 = 1'b0, + parameter PORT_MEM_D_PINLOC_30 = 1'b0, + parameter PORT_MEM_D_PINLOC_29 = 1'b0, + parameter PORT_MEM_D_PINLOC_28 = 1'b0, + parameter PORT_MEM_D_PINLOC_27 = 1'b0, + parameter PORT_MEM_D_PINLOC_26 = 1'b0, + parameter PORT_MEM_D_PINLOC_25 = 1'b0, + parameter PORT_MEM_D_PINLOC_24 = 1'b0, + parameter PORT_MEM_D_PINLOC_23 = 1'b0, + parameter PORT_MEM_D_PINLOC_22 = 1'b0, + parameter PORT_MEM_D_PINLOC_21 = 1'b0, + parameter PORT_MEM_D_PINLOC_20 = 1'b0, + parameter PORT_MEM_D_PINLOC_19 = 1'b0, + parameter PORT_MEM_D_PINLOC_18 = 1'b0, + parameter PORT_MEM_D_PINLOC_17 = 1'b0, + parameter PORT_MEM_D_PINLOC_16 = 1'b0, + parameter PORT_MEM_D_PINLOC_15 = 1'b0, + parameter PORT_MEM_D_PINLOC_14 = 1'b0, + parameter PORT_MEM_D_PINLOC_13 = 1'b0, + parameter PORT_MEM_D_PINLOC_12 = 1'b0, + parameter PORT_MEM_D_PINLOC_11 = 1'b0, + parameter PORT_MEM_D_PINLOC_10 = 1'b0, + parameter PORT_MEM_D_PINLOC_9 = 1'b0, + parameter PORT_MEM_D_PINLOC_8 = 1'b0, + parameter PORT_MEM_D_PINLOC_7 = 1'b0, + parameter PORT_MEM_D_PINLOC_6 = 1'b0, + parameter PORT_MEM_D_PINLOC_5 = 1'b0, + parameter PORT_MEM_D_PINLOC_4 = 1'b0, + parameter PORT_MEM_D_PINLOC_3 = 1'b0, + parameter PORT_MEM_D_PINLOC_2 = 1'b0, + parameter PORT_MEM_D_PINLOC_1 = 1'b0, + parameter PORT_MEM_D_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQ_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_0 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DBI_N_PINLOC_6 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQA_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQB_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_0 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_0 = 1'b0, + parameter PORT_MEM_Q_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_Q_PINLOC_48 = 1'b0, + parameter PORT_MEM_Q_PINLOC_47 = 1'b0, + parameter PORT_MEM_Q_PINLOC_46 = 1'b0, + parameter PORT_MEM_Q_PINLOC_45 = 1'b0, + parameter PORT_MEM_Q_PINLOC_44 = 1'b0, + parameter PORT_MEM_Q_PINLOC_43 = 1'b0, + parameter PORT_MEM_Q_PINLOC_42 = 1'b0, + parameter PORT_MEM_Q_PINLOC_41 = 1'b0, + parameter PORT_MEM_Q_PINLOC_40 = 1'b0, + parameter PORT_MEM_Q_PINLOC_39 = 1'b0, + parameter PORT_MEM_Q_PINLOC_38 = 1'b0, + parameter PORT_MEM_Q_PINLOC_37 = 1'b0, + parameter PORT_MEM_Q_PINLOC_36 = 1'b0, + parameter PORT_MEM_Q_PINLOC_35 = 1'b0, + parameter PORT_MEM_Q_PINLOC_34 = 1'b0, + parameter PORT_MEM_Q_PINLOC_33 = 1'b0, + parameter PORT_MEM_Q_PINLOC_32 = 1'b0, + parameter PORT_MEM_Q_PINLOC_31 = 1'b0, + parameter PORT_MEM_Q_PINLOC_30 = 1'b0, + parameter PORT_MEM_Q_PINLOC_29 = 1'b0, + parameter PORT_MEM_Q_PINLOC_28 = 1'b0, + parameter PORT_MEM_Q_PINLOC_27 = 1'b0, + parameter PORT_MEM_Q_PINLOC_26 = 1'b0, + parameter PORT_MEM_Q_PINLOC_25 = 1'b0, + parameter PORT_MEM_Q_PINLOC_24 = 1'b0, + parameter PORT_MEM_Q_PINLOC_23 = 1'b0, + parameter PORT_MEM_Q_PINLOC_22 = 1'b0, + parameter PORT_MEM_Q_PINLOC_21 = 1'b0, + parameter PORT_MEM_Q_PINLOC_20 = 1'b0, + parameter PORT_MEM_Q_PINLOC_19 = 1'b0, + parameter PORT_MEM_Q_PINLOC_18 = 1'b0, + parameter PORT_MEM_Q_PINLOC_17 = 1'b0, + parameter PORT_MEM_Q_PINLOC_16 = 1'b0, + parameter PORT_MEM_Q_PINLOC_15 = 1'b0, + parameter PORT_MEM_Q_PINLOC_14 = 1'b0, + parameter PORT_MEM_Q_PINLOC_13 = 1'b0, + parameter PORT_MEM_Q_PINLOC_12 = 1'b0, + parameter PORT_MEM_Q_PINLOC_11 = 1'b0, + parameter PORT_MEM_Q_PINLOC_10 = 1'b0, + parameter PORT_MEM_Q_PINLOC_9 = 1'b0, + parameter PORT_MEM_Q_PINLOC_8 = 1'b0, + parameter PORT_MEM_Q_PINLOC_7 = 1'b0, + parameter PORT_MEM_Q_PINLOC_6 = 1'b0, + parameter PORT_MEM_Q_PINLOC_5 = 1'b0, + parameter PORT_MEM_Q_PINLOC_4 = 1'b0, + parameter PORT_MEM_Q_PINLOC_3 = 1'b0, + parameter PORT_MEM_Q_PINLOC_2 = 1'b0, + parameter PORT_MEM_Q_PINLOC_1 = 1'b0, + parameter PORT_MEM_Q_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_N_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_PINLOC_5 = 1'b0, + parameter PORT_MEM_QK_PINLOC_4 = 1'b0, + parameter PORT_MEM_QK_PINLOC_3 = 1'b0, + parameter PORT_MEM_QK_PINLOC_2 = 1'b0, + parameter PORT_MEM_QK_PINLOC_1 = 1'b0, + parameter PORT_MEM_QK_PINLOC_0 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_PINLOC_1 = 1'b0, + parameter PORT_MEM_CQ_PINLOC_0 = 1'b0, + parameter PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CQ_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ALERT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ALERT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PE_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_PE_N_PINLOC_0 = 1'b0 +) ( + // Reset request and acknowledgement + input logic local_reset_req, + output logic local_reset_done, + + // PLL signals + input logic pll_ref_clk, + output logic pll_ref_clk_out, + output logic pll_locked, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + + // OCT signals + input logic oct_rzqin, + + // Status signals + output logic local_cal_success, + output logic local_cal_fail, + output logic ac_parity_err, + + // User reset signal going to core (for PHY + hard controller interfaces) + output logic emif_usr_reset_n, + output logic emif_usr_reset_n_sec, + + // User clock going to core (for PHY + hard controller interfaces) + output logic emif_usr_clk, + output logic emif_usr_clk_sec, + + // A clock that runs at half the frequency of emif_usr_clk going to core + output logic emif_usr_half_clk, + output logic emif_usr_half_clk_sec, + + // AFI reset going to core + output logic afi_reset_n, + + // AFI clock going to core + output logic afi_clk, + + // A clock that runs at half the frequency of afi_clk going to core + output logic afi_half_clk, + + // Signals required to share core clocking resources between across + // compatible interfaces. An interface can be configured as a "master" + // which exports the core clocks, or a "slave" which imports the + // core clocks from a master interface. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_SLAVE_OUT_WIDTH-1:0] clks_sharing_slave_out, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // Ports for "mem" interface + //AUTOGEN_BEGIN: Definition of memory ports + output logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + output logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + inout tri [PORT_MEM_CK_BIDIR_WIDTH-1:0] mem_ck_bidir, + inout tri [PORT_MEM_CK_BIDIR_N_WIDTH-1:0] mem_ck_bidir_n, + output logic [PORT_MEM_DK_WIDTH-1:0] mem_dk, + output logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n, + output logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka, + output logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n, + output logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb, + output logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n, + output logic [PORT_MEM_K_WIDTH-1:0] mem_k, + output logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n, + output logic [PORT_MEM_A_WIDTH-1:0] mem_a, + output logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + output logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + output logic [PORT_MEM_C_WIDTH-1:0] mem_c, + output logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke, + output logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n, + output logic [PORT_MEM_RM_WIDTH-1:0] mem_rm, + output logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + output logic [PORT_MEM_GNT_N_WIDTH-1:0] mem_gnt_n, + input logic [PORT_MEM_REQ_N_WIDTH-1:0] mem_req_n, + input logic [PORT_MEM_ERR_N_WIDTH-1:0] mem_err_n, + output logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n, + output logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n, + output logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n, + output logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n, + output logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n, + output logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + output logic [PORT_MEM_CA_WIDTH-1:0] mem_ca, + output logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n, + output logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n, + output logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n, + output logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n, + output logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n, + output logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n, + output logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n, + output logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n, + output logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n, + output logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n, + output logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n, + output logic [PORT_MEM_AP_WIDTH-1:0] mem_ap, + output logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv, + output logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + output logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n, + output logic [PORT_MEM_D_WIDTH-1:0] mem_d, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa, + inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb, + inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva, + inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb, + input logic [PORT_MEM_Q_WIDTH-1:0] mem_q, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n, + input logic [PORT_MEM_QK_WIDTH-1:0] mem_qk, + input logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n, + input logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka, + input logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n, + input logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb, + input logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n, + input logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq, + input logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n, + input logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n, + + // Ports for "afi" interface + //AUTOGEN_BEGIN: Definition of afi ports + output logic afi_cal_success, + output logic afi_cal_fail, + input logic afi_cal_req, + output logic [PORT_AFI_RLAT_WIDTH-1:0] afi_rlat, + output logic [PORT_AFI_WLAT_WIDTH-1:0] afi_wlat, + output logic [PORT_AFI_SEQ_BUSY_WIDTH-1:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic afi_mps_ack, + input logic [PORT_AFI_ADDR_WIDTH-1:0] afi_addr, + input logic [PORT_AFI_BA_WIDTH-1:0] afi_ba, + input logic [PORT_AFI_BG_WIDTH-1:0] afi_bg, + input logic [PORT_AFI_C_WIDTH-1:0] afi_c, + input logic [PORT_AFI_CKE_WIDTH-1:0] afi_cke, + input logic [PORT_AFI_CS_N_WIDTH-1:0] afi_cs_n, + input logic [PORT_AFI_RM_WIDTH-1:0] afi_rm, + input logic [PORT_AFI_ODT_WIDTH-1:0] afi_odt, + input logic [PORT_AFI_GNT_N_WIDTH-1:0] afi_gnt_n, + output logic [PORT_AFI_REQ_N_WIDTH-1:0] afi_req_n, + output logic [PORT_AFI_ERR_N_WIDTH-1:0] afi_err_n, + input logic [PORT_AFI_RAS_N_WIDTH-1:0] afi_ras_n, + input logic [PORT_AFI_CAS_N_WIDTH-1:0] afi_cas_n, + input logic [PORT_AFI_WE_N_WIDTH-1:0] afi_we_n, + input logic [PORT_AFI_RST_N_WIDTH-1:0] afi_rst_n, + input logic [PORT_AFI_ACT_N_WIDTH-1:0] afi_act_n, + input logic [PORT_AFI_PAR_WIDTH-1:0] afi_par, + input logic [PORT_AFI_CA_WIDTH-1:0] afi_ca, + input logic [PORT_AFI_REF_N_WIDTH-1:0] afi_ref_n, + input logic [PORT_AFI_WPS_N_WIDTH-1:0] afi_wps_n, + input logic [PORT_AFI_RPS_N_WIDTH-1:0] afi_rps_n, + input logic [PORT_AFI_DOFF_N_WIDTH-1:0] afi_doff_n, + input logic [PORT_AFI_LD_N_WIDTH-1:0] afi_ld_n, + input logic [PORT_AFI_RW_N_WIDTH-1:0] afi_rw_n, + input logic [PORT_AFI_LBK0_N_WIDTH-1:0] afi_lbk0_n, + input logic [PORT_AFI_LBK1_N_WIDTH-1:0] afi_lbk1_n, + input logic [PORT_AFI_CFG_N_WIDTH-1:0] afi_cfg_n, + input logic [PORT_AFI_AP_WIDTH-1:0] afi_ap, + input logic [PORT_AFI_AINV_WIDTH-1:0] afi_ainv, + input logic [PORT_AFI_DM_WIDTH-1:0] afi_dm, + input logic [PORT_AFI_DM_N_WIDTH-1:0] afi_dm_n, + input logic [PORT_AFI_BWS_N_WIDTH-1:0] afi_bws_n, + output logic [PORT_AFI_RDATA_DBI_N_WIDTH-1:0] afi_rdata_dbi_n, + input logic [PORT_AFI_WDATA_DBI_N_WIDTH-1:0] afi_wdata_dbi_n, + output logic [PORT_AFI_RDATA_DINV_WIDTH-1:0] afi_rdata_dinv, + input logic [PORT_AFI_WDATA_DINV_WIDTH-1:0] afi_wdata_dinv, + input logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst, + input logic [PORT_AFI_WDATA_VALID_WIDTH-1:0] afi_wdata_valid, + input logic [PORT_AFI_WDATA_WIDTH-1:0] afi_wdata, + input logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full, + output logic [PORT_AFI_RDATA_WIDTH-1:0] afi_rdata, + output logic [PORT_AFI_RDATA_VALID_WIDTH-1:0] afi_rdata_valid, + input logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank, + input logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank, + output logic [PORT_AFI_ALERT_N_WIDTH-1:0] afi_alert_n, + output logic [PORT_AFI_PE_N_WIDTH-1:0] afi_pe_n, + + // Ports for "ctrl_ast_cmd" interfaces + output logic ast_cmd_ready_0, + input logic ast_cmd_valid_0, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_0, + + output logic ast_cmd_ready_1, + input logic ast_cmd_valid_1, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_1, + + // Ports for "ctrl_ast_wr" interfaces + output logic ast_wr_ready_0, + input logic ast_wr_valid_0, + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_0, + + output logic ast_wr_ready_1, + input logic ast_wr_valid_1, + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_1, + + // Ports for "ctrl_ast_rd" interfaces + input logic ast_rd_ready_0, + output logic ast_rd_valid_0, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_0, + + input logic ast_rd_ready_1, + output logic ast_rd_valid_1, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_1, + + // Ports for "ctrl_amm" interfaces + input logic amm_write_0, + input logic amm_read_0, + output logic amm_ready_0, + output logic amm_early_ready_0, + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_0, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_0, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_0, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + output logic amm_rd_type_0, + + input logic amm_write_1, + input logic amm_read_1, + output logic amm_ready_1, + output logic amm_early_ready_1, + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_1, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_1, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_1, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + output logic amm_rd_type_1, + + // Ports for "ctrl_user_priority" interface + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + + // Ports for "ctrl_auto_precharge" interface + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + + // Ports for "ctrl_user_refresh" interface + input logic [PORT_CTRL_USER_REFRESH_REQ_WIDTH-1:0] ctrl_user_refresh_req, + input logic [PORT_CTRL_USER_REFRESH_BANK_WIDTH-1:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + + // Ports for "ctrl_self_refresh" interface + input logic [PORT_CTRL_SELF_REFRESH_REQ_WIDTH-1:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + + // Ports for "ctrl_will_refresh" interface + output logic ctrl_will_refresh, + + // Ports for "ctrl_deep_power_down" interface + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + + // Ports for "ctrl_power_down" interface + output logic ctrl_power_down_ack, + + // Ports for "ctrl_zq_cal" interface + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_0, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_0, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_0, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_0, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_1, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_1, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_1, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_1, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + + // Ports for "ctrl_mmr" interface + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_0, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_0, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_0, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + + // Ports for "ctrl_mmr" interface + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_1, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_1, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_1, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1, + + // Ports for the HPS<->EMIF conduit + input logic [PORT_HPS_EMIF_H2E_WIDTH-1:0] hps_to_emif, + output logic [PORT_HPS_EMIF_E2H_WIDTH-1:0] emif_to_hps, + input logic [PORT_HPS_EMIF_H2E_GP_WIDTH-1:0] hps_to_emif_gp, + output logic [PORT_HPS_EMIF_E2H_GP_WIDTH-1:0] emif_to_hps_gp, + + // EMIF Calibration Bus I/F + input logic calbus_clk, + input logic calbus_read, + input logic calbus_write, + input logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address, + input logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata, + output logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata, + output logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl, + + + // Ports for internal test and debug + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_ND_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done, + input logic [PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH-1:0] pll_core_refclk, + output logic [PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked, + + // phylite interface + input logic [PORT_CTRL_STROBE_WIDTH-1:0] phylite_strobe, + input logic [PORT_CTRL_DATA_OE_WIDTH-1:0] phylite_data_oe, + input logic [PORT_CTRL_DATA_OUT_WIDTH-1: 0] phylite_data_from_core, + input logic [PORT_CTRL_STROBE_OE_WIDTH-1:0] phylite_strobe_oe, + output logic [PORT_CTRL_RDATA_VALID_WIDTH-1:0] phylite_rdata_valid, + input logic [PORT_CTRL_RDATA_ENABLE_WIDTH-1:0] phylite_rdata_en, + output logic [PORT_CTRL_DATA_IN_WIDTH-1 :0] phylite_data_to_core, + output logic phylite_interface_locked +); + timeunit 1ns; + timeprecision 1ps; + + // Below is used to override the user selection for ABSTRACT PHY for synthesis + // synthesis translate_off + `define ENABLE_SIM_PARAMS_FOR_SIM TRUE + // synthesis translate_on + `ifdef ENABLE_SIM_PARAMS_FOR_SIM + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = DIAG_USE_ABSTRACT_PHY; + `else + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = 0; + `endif + + localparam SEQ_PT_CONTENT = (SEQ_USE_SIM_PARAMS == "on") ? SEQ_PT_SIM_CONTENT : ((DIAG_SYNTH_FOR_SIM) ? SEQ_PT_SIM_CONTENT : SEQ_PT_SYN_CONTENT); + + // Assertions + // synthesis translate_off + initial begin + assert(LANES_USAGE_AUTOGEN_WCNT == 4) else $fatal(1, "LANES_USAGE_AUTOGEN_WCNT != 4 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_USAGE_AUTOGEN_WCNT == 13) else $fatal(1, "PINS_USAGE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(LANE_PIN_USAGE_AUTOGEN_WCNT == 52) else $fatal(1, "LANE_PIN_USAGE_AUTOGEN_WCNT != 52 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_RATE_AUTOGEN_WCNT == 13) else $fatal(1, "PINS_RATE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(DB_PINS_PROC_MODE_AUTOGEN_WCNT == 64) else $fatal(1, "DB_PINS_PROC_MODE_AUTOGEN_WCNT != 64 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DATA_IN_MODE_AUTOGEN_WCNT == 39) else $fatal(1, "PINS_DATA_IN_MODE_AUTOGEN_WCNT != 39 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_C2L_DRIVEN_AUTOGEN_WCNT == 13) else $fatal(1, "PINS_C2L_DRIVEN_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_OCT_MODE_AUTOGEN_WCNT == 13) else $fatal(1, "PINS_OCT_MODE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DCC_SPLIT_AUTOGEN_WCNT == 13) else $fatal(1, "PINS_DCC_SPLIT_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT == 129) else $fatal(1, "UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT != 129 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT == 11) else $fatal(1, "UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT != 11 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(DBC_PIPE_LATS_AUTOGEN_WCNT == 5) else $fatal(1, "DBC_PIPE_LATS_AUTOGEN_WCNT != 5 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT == 5) else $fatal(1, "DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT != 5 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT == 5) else $fatal(1, "DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT != 5 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(CENTER_TIDS_AUTOGEN_WCNT == 3) else $fatal(1, "CENTER_TIDS_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(HMC_TIDS_AUTOGEN_WCNT == 3) else $fatal(1, "HMC_TIDS_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(LANE_TIDS_AUTOGEN_WCNT == 10) else $fatal(1, "LANE_TIDS_AUTOGEN_WCNT != 10 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CK_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_CK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DK_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_DK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_K_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_K_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_A_PINLOC_AUTOGEN_WCNT == 17) else $fatal(1, "PORT_MEM_A_PINLOC_AUTOGEN_WCNT != 17 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BA_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_BA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BG_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_BG_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_C_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_C_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RM_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_RM_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CA_PINLOC_AUTOGEN_WCNT == 17) else $fatal(1, "PORT_MEM_CA_PINLOC_AUTOGEN_WCNT != 17 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_AP_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_AP_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT == 1) else $fatal(1, "PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DM_PINLOC_AUTOGEN_WCNT == 13) else $fatal(1, "PORT_MEM_DM_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT == 3) else $fatal(1, "PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_D_PINLOC_AUTOGEN_WCNT == 49) else $fatal(1, "PORT_MEM_D_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT == 49) else $fatal(1, "PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT == 7) else $fatal(1, "PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT != 7 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT == 49) else $fatal(1, "PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT == 49) else $fatal(1, "PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT == 3) else $fatal(1, "PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT == 3) else $fatal(1, "PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_Q_PINLOC_AUTOGEN_WCNT == 49) else $fatal(1, "PORT_MEM_Q_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT == 13) else $fatal(1, "PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT == 13) else $fatal(1, "PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QK_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_QK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal(1, "PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal(1, "PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + end + // synthesis translate_on + + // Derive localparam values + //AUTOGEN_BEGIN: Derive bit-vector parameters + localparam LANES_USAGE = {LANES_USAGE_3[29:0],LANES_USAGE_2[29:0],LANES_USAGE_1[29:0],LANES_USAGE_0[29:0]}; + localparam PINS_USAGE = {PINS_USAGE_12[29:0],PINS_USAGE_11[29:0],PINS_USAGE_10[29:0],PINS_USAGE_9[29:0],PINS_USAGE_8[29:0],PINS_USAGE_7[29:0],PINS_USAGE_6[29:0],PINS_USAGE_5[29:0],PINS_USAGE_4[29:0],PINS_USAGE_3[29:0],PINS_USAGE_2[29:0],PINS_USAGE_1[29:0],PINS_USAGE_0[29:0]}; + localparam LANE_PIN_USAGE = {LANE_PIN_USAGE_51[29:0],LANE_PIN_USAGE_50[29:0],LANE_PIN_USAGE_49[29:0],LANE_PIN_USAGE_48[29:0],LANE_PIN_USAGE_47[29:0],LANE_PIN_USAGE_46[29:0],LANE_PIN_USAGE_45[29:0],LANE_PIN_USAGE_44[29:0],LANE_PIN_USAGE_43[29:0],LANE_PIN_USAGE_42[29:0],LANE_PIN_USAGE_41[29:0],LANE_PIN_USAGE_40[29:0],LANE_PIN_USAGE_39[29:0],LANE_PIN_USAGE_38[29:0],LANE_PIN_USAGE_37[29:0],LANE_PIN_USAGE_36[29:0],LANE_PIN_USAGE_35[29:0],LANE_PIN_USAGE_34[29:0],LANE_PIN_USAGE_33[29:0],LANE_PIN_USAGE_32[29:0],LANE_PIN_USAGE_31[29:0],LANE_PIN_USAGE_30[29:0],LANE_PIN_USAGE_29[29:0],LANE_PIN_USAGE_28[29:0],LANE_PIN_USAGE_27[29:0],LANE_PIN_USAGE_26[29:0],LANE_PIN_USAGE_25[29:0],LANE_PIN_USAGE_24[29:0],LANE_PIN_USAGE_23[29:0],LANE_PIN_USAGE_22[29:0],LANE_PIN_USAGE_21[29:0],LANE_PIN_USAGE_20[29:0],LANE_PIN_USAGE_19[29:0],LANE_PIN_USAGE_18[29:0],LANE_PIN_USAGE_17[29:0],LANE_PIN_USAGE_16[29:0],LANE_PIN_USAGE_15[29:0],LANE_PIN_USAGE_14[29:0],LANE_PIN_USAGE_13[29:0],LANE_PIN_USAGE_12[29:0],LANE_PIN_USAGE_11[29:0],LANE_PIN_USAGE_10[29:0],LANE_PIN_USAGE_9[29:0],LANE_PIN_USAGE_8[29:0],LANE_PIN_USAGE_7[29:0],LANE_PIN_USAGE_6[29:0],LANE_PIN_USAGE_5[29:0],LANE_PIN_USAGE_4[29:0],LANE_PIN_USAGE_3[29:0],LANE_PIN_USAGE_2[29:0],LANE_PIN_USAGE_1[29:0],LANE_PIN_USAGE_0[29:0]}; + localparam PINS_RATE = {PINS_RATE_12[29:0],PINS_RATE_11[29:0],PINS_RATE_10[29:0],PINS_RATE_9[29:0],PINS_RATE_8[29:0],PINS_RATE_7[29:0],PINS_RATE_6[29:0],PINS_RATE_5[29:0],PINS_RATE_4[29:0],PINS_RATE_3[29:0],PINS_RATE_2[29:0],PINS_RATE_1[29:0],PINS_RATE_0[29:0]}; + localparam DB_PINS_PROC_MODE = {DB_PINS_PROC_MODE_63[29:0],DB_PINS_PROC_MODE_62[29:0],DB_PINS_PROC_MODE_61[29:0],DB_PINS_PROC_MODE_60[29:0],DB_PINS_PROC_MODE_59[29:0],DB_PINS_PROC_MODE_58[29:0],DB_PINS_PROC_MODE_57[29:0],DB_PINS_PROC_MODE_56[29:0],DB_PINS_PROC_MODE_55[29:0],DB_PINS_PROC_MODE_54[29:0],DB_PINS_PROC_MODE_53[29:0],DB_PINS_PROC_MODE_52[29:0],DB_PINS_PROC_MODE_51[29:0],DB_PINS_PROC_MODE_50[29:0],DB_PINS_PROC_MODE_49[29:0],DB_PINS_PROC_MODE_48[29:0],DB_PINS_PROC_MODE_47[29:0],DB_PINS_PROC_MODE_46[29:0],DB_PINS_PROC_MODE_45[29:0],DB_PINS_PROC_MODE_44[29:0],DB_PINS_PROC_MODE_43[29:0],DB_PINS_PROC_MODE_42[29:0],DB_PINS_PROC_MODE_41[29:0],DB_PINS_PROC_MODE_40[29:0],DB_PINS_PROC_MODE_39[29:0],DB_PINS_PROC_MODE_38[29:0],DB_PINS_PROC_MODE_37[29:0],DB_PINS_PROC_MODE_36[29:0],DB_PINS_PROC_MODE_35[29:0],DB_PINS_PROC_MODE_34[29:0],DB_PINS_PROC_MODE_33[29:0],DB_PINS_PROC_MODE_32[29:0],DB_PINS_PROC_MODE_31[29:0],DB_PINS_PROC_MODE_30[29:0],DB_PINS_PROC_MODE_29[29:0],DB_PINS_PROC_MODE_28[29:0],DB_PINS_PROC_MODE_27[29:0],DB_PINS_PROC_MODE_26[29:0],DB_PINS_PROC_MODE_25[29:0],DB_PINS_PROC_MODE_24[29:0],DB_PINS_PROC_MODE_23[29:0],DB_PINS_PROC_MODE_22[29:0],DB_PINS_PROC_MODE_21[29:0],DB_PINS_PROC_MODE_20[29:0],DB_PINS_PROC_MODE_19[29:0],DB_PINS_PROC_MODE_18[29:0],DB_PINS_PROC_MODE_17[29:0],DB_PINS_PROC_MODE_16[29:0],DB_PINS_PROC_MODE_15[29:0],DB_PINS_PROC_MODE_14[29:0],DB_PINS_PROC_MODE_13[29:0],DB_PINS_PROC_MODE_12[29:0],DB_PINS_PROC_MODE_11[29:0],DB_PINS_PROC_MODE_10[29:0],DB_PINS_PROC_MODE_9[29:0],DB_PINS_PROC_MODE_8[29:0],DB_PINS_PROC_MODE_7[29:0],DB_PINS_PROC_MODE_6[29:0],DB_PINS_PROC_MODE_5[29:0],DB_PINS_PROC_MODE_4[29:0],DB_PINS_PROC_MODE_3[29:0],DB_PINS_PROC_MODE_2[29:0],DB_PINS_PROC_MODE_1[29:0],DB_PINS_PROC_MODE_0[29:0]}; + localparam PINS_DATA_IN_MODE = {PINS_DATA_IN_MODE_38[29:0],PINS_DATA_IN_MODE_37[29:0],PINS_DATA_IN_MODE_36[29:0],PINS_DATA_IN_MODE_35[29:0],PINS_DATA_IN_MODE_34[29:0],PINS_DATA_IN_MODE_33[29:0],PINS_DATA_IN_MODE_32[29:0],PINS_DATA_IN_MODE_31[29:0],PINS_DATA_IN_MODE_30[29:0],PINS_DATA_IN_MODE_29[29:0],PINS_DATA_IN_MODE_28[29:0],PINS_DATA_IN_MODE_27[29:0],PINS_DATA_IN_MODE_26[29:0],PINS_DATA_IN_MODE_25[29:0],PINS_DATA_IN_MODE_24[29:0],PINS_DATA_IN_MODE_23[29:0],PINS_DATA_IN_MODE_22[29:0],PINS_DATA_IN_MODE_21[29:0],PINS_DATA_IN_MODE_20[29:0],PINS_DATA_IN_MODE_19[29:0],PINS_DATA_IN_MODE_18[29:0],PINS_DATA_IN_MODE_17[29:0],PINS_DATA_IN_MODE_16[29:0],PINS_DATA_IN_MODE_15[29:0],PINS_DATA_IN_MODE_14[29:0],PINS_DATA_IN_MODE_13[29:0],PINS_DATA_IN_MODE_12[29:0],PINS_DATA_IN_MODE_11[29:0],PINS_DATA_IN_MODE_10[29:0],PINS_DATA_IN_MODE_9[29:0],PINS_DATA_IN_MODE_8[29:0],PINS_DATA_IN_MODE_7[29:0],PINS_DATA_IN_MODE_6[29:0],PINS_DATA_IN_MODE_5[29:0],PINS_DATA_IN_MODE_4[29:0],PINS_DATA_IN_MODE_3[29:0],PINS_DATA_IN_MODE_2[29:0],PINS_DATA_IN_MODE_1[29:0],PINS_DATA_IN_MODE_0[29:0]}; + localparam PINS_C2L_DRIVEN = {PINS_C2L_DRIVEN_12[29:0],PINS_C2L_DRIVEN_11[29:0],PINS_C2L_DRIVEN_10[29:0],PINS_C2L_DRIVEN_9[29:0],PINS_C2L_DRIVEN_8[29:0],PINS_C2L_DRIVEN_7[29:0],PINS_C2L_DRIVEN_6[29:0],PINS_C2L_DRIVEN_5[29:0],PINS_C2L_DRIVEN_4[29:0],PINS_C2L_DRIVEN_3[29:0],PINS_C2L_DRIVEN_2[29:0],PINS_C2L_DRIVEN_1[29:0],PINS_C2L_DRIVEN_0[29:0]}; + localparam PINS_OCT_MODE = {PINS_OCT_MODE_12[29:0],PINS_OCT_MODE_11[29:0],PINS_OCT_MODE_10[29:0],PINS_OCT_MODE_9[29:0],PINS_OCT_MODE_8[29:0],PINS_OCT_MODE_7[29:0],PINS_OCT_MODE_6[29:0],PINS_OCT_MODE_5[29:0],PINS_OCT_MODE_4[29:0],PINS_OCT_MODE_3[29:0],PINS_OCT_MODE_2[29:0],PINS_OCT_MODE_1[29:0],PINS_OCT_MODE_0[29:0]}; + localparam PINS_DCC_SPLIT = {PINS_DCC_SPLIT_12[29:0],PINS_DCC_SPLIT_11[29:0],PINS_DCC_SPLIT_10[29:0],PINS_DCC_SPLIT_9[29:0],PINS_DCC_SPLIT_8[29:0],PINS_DCC_SPLIT_7[29:0],PINS_DCC_SPLIT_6[29:0],PINS_DCC_SPLIT_5[29:0],PINS_DCC_SPLIT_4[29:0],PINS_DCC_SPLIT_3[29:0],PINS_DCC_SPLIT_2[29:0],PINS_DCC_SPLIT_1[29:0],PINS_DCC_SPLIT_0[29:0]}; + localparam UNUSED_MEM_PINS_PINLOC = {UNUSED_MEM_PINS_PINLOC_128[29:0],UNUSED_MEM_PINS_PINLOC_127[29:0],UNUSED_MEM_PINS_PINLOC_126[29:0],UNUSED_MEM_PINS_PINLOC_125[29:0],UNUSED_MEM_PINS_PINLOC_124[29:0],UNUSED_MEM_PINS_PINLOC_123[29:0],UNUSED_MEM_PINS_PINLOC_122[29:0],UNUSED_MEM_PINS_PINLOC_121[29:0],UNUSED_MEM_PINS_PINLOC_120[29:0],UNUSED_MEM_PINS_PINLOC_119[29:0],UNUSED_MEM_PINS_PINLOC_118[29:0],UNUSED_MEM_PINS_PINLOC_117[29:0],UNUSED_MEM_PINS_PINLOC_116[29:0],UNUSED_MEM_PINS_PINLOC_115[29:0],UNUSED_MEM_PINS_PINLOC_114[29:0],UNUSED_MEM_PINS_PINLOC_113[29:0],UNUSED_MEM_PINS_PINLOC_112[29:0],UNUSED_MEM_PINS_PINLOC_111[29:0],UNUSED_MEM_PINS_PINLOC_110[29:0],UNUSED_MEM_PINS_PINLOC_109[29:0],UNUSED_MEM_PINS_PINLOC_108[29:0],UNUSED_MEM_PINS_PINLOC_107[29:0],UNUSED_MEM_PINS_PINLOC_106[29:0],UNUSED_MEM_PINS_PINLOC_105[29:0],UNUSED_MEM_PINS_PINLOC_104[29:0],UNUSED_MEM_PINS_PINLOC_103[29:0],UNUSED_MEM_PINS_PINLOC_102[29:0],UNUSED_MEM_PINS_PINLOC_101[29:0],UNUSED_MEM_PINS_PINLOC_100[29:0],UNUSED_MEM_PINS_PINLOC_99[29:0],UNUSED_MEM_PINS_PINLOC_98[29:0],UNUSED_MEM_PINS_PINLOC_97[29:0],UNUSED_MEM_PINS_PINLOC_96[29:0],UNUSED_MEM_PINS_PINLOC_95[29:0],UNUSED_MEM_PINS_PINLOC_94[29:0],UNUSED_MEM_PINS_PINLOC_93[29:0],UNUSED_MEM_PINS_PINLOC_92[29:0],UNUSED_MEM_PINS_PINLOC_91[29:0],UNUSED_MEM_PINS_PINLOC_90[29:0],UNUSED_MEM_PINS_PINLOC_89[29:0],UNUSED_MEM_PINS_PINLOC_88[29:0],UNUSED_MEM_PINS_PINLOC_87[29:0],UNUSED_MEM_PINS_PINLOC_86[29:0],UNUSED_MEM_PINS_PINLOC_85[29:0],UNUSED_MEM_PINS_PINLOC_84[29:0],UNUSED_MEM_PINS_PINLOC_83[29:0],UNUSED_MEM_PINS_PINLOC_82[29:0],UNUSED_MEM_PINS_PINLOC_81[29:0],UNUSED_MEM_PINS_PINLOC_80[29:0],UNUSED_MEM_PINS_PINLOC_79[29:0],UNUSED_MEM_PINS_PINLOC_78[29:0],UNUSED_MEM_PINS_PINLOC_77[29:0],UNUSED_MEM_PINS_PINLOC_76[29:0],UNUSED_MEM_PINS_PINLOC_75[29:0],UNUSED_MEM_PINS_PINLOC_74[29:0],UNUSED_MEM_PINS_PINLOC_73[29:0],UNUSED_MEM_PINS_PINLOC_72[29:0],UNUSED_MEM_PINS_PINLOC_71[29:0],UNUSED_MEM_PINS_PINLOC_70[29:0],UNUSED_MEM_PINS_PINLOC_69[29:0],UNUSED_MEM_PINS_PINLOC_68[29:0],UNUSED_MEM_PINS_PINLOC_67[29:0],UNUSED_MEM_PINS_PINLOC_66[29:0],UNUSED_MEM_PINS_PINLOC_65[29:0],UNUSED_MEM_PINS_PINLOC_64[29:0],UNUSED_MEM_PINS_PINLOC_63[29:0],UNUSED_MEM_PINS_PINLOC_62[29:0],UNUSED_MEM_PINS_PINLOC_61[29:0],UNUSED_MEM_PINS_PINLOC_60[29:0],UNUSED_MEM_PINS_PINLOC_59[29:0],UNUSED_MEM_PINS_PINLOC_58[29:0],UNUSED_MEM_PINS_PINLOC_57[29:0],UNUSED_MEM_PINS_PINLOC_56[29:0],UNUSED_MEM_PINS_PINLOC_55[29:0],UNUSED_MEM_PINS_PINLOC_54[29:0],UNUSED_MEM_PINS_PINLOC_53[29:0],UNUSED_MEM_PINS_PINLOC_52[29:0],UNUSED_MEM_PINS_PINLOC_51[29:0],UNUSED_MEM_PINS_PINLOC_50[29:0],UNUSED_MEM_PINS_PINLOC_49[29:0],UNUSED_MEM_PINS_PINLOC_48[29:0],UNUSED_MEM_PINS_PINLOC_47[29:0],UNUSED_MEM_PINS_PINLOC_46[29:0],UNUSED_MEM_PINS_PINLOC_45[29:0],UNUSED_MEM_PINS_PINLOC_44[29:0],UNUSED_MEM_PINS_PINLOC_43[29:0],UNUSED_MEM_PINS_PINLOC_42[29:0],UNUSED_MEM_PINS_PINLOC_41[29:0],UNUSED_MEM_PINS_PINLOC_40[29:0],UNUSED_MEM_PINS_PINLOC_39[29:0],UNUSED_MEM_PINS_PINLOC_38[29:0],UNUSED_MEM_PINS_PINLOC_37[29:0],UNUSED_MEM_PINS_PINLOC_36[29:0],UNUSED_MEM_PINS_PINLOC_35[29:0],UNUSED_MEM_PINS_PINLOC_34[29:0],UNUSED_MEM_PINS_PINLOC_33[29:0],UNUSED_MEM_PINS_PINLOC_32[29:0],UNUSED_MEM_PINS_PINLOC_31[29:0],UNUSED_MEM_PINS_PINLOC_30[29:0],UNUSED_MEM_PINS_PINLOC_29[29:0],UNUSED_MEM_PINS_PINLOC_28[29:0],UNUSED_MEM_PINS_PINLOC_27[29:0],UNUSED_MEM_PINS_PINLOC_26[29:0],UNUSED_MEM_PINS_PINLOC_25[29:0],UNUSED_MEM_PINS_PINLOC_24[29:0],UNUSED_MEM_PINS_PINLOC_23[29:0],UNUSED_MEM_PINS_PINLOC_22[29:0],UNUSED_MEM_PINS_PINLOC_21[29:0],UNUSED_MEM_PINS_PINLOC_20[29:0],UNUSED_MEM_PINS_PINLOC_19[29:0],UNUSED_MEM_PINS_PINLOC_18[29:0],UNUSED_MEM_PINS_PINLOC_17[29:0],UNUSED_MEM_PINS_PINLOC_16[29:0],UNUSED_MEM_PINS_PINLOC_15[29:0],UNUSED_MEM_PINS_PINLOC_14[29:0],UNUSED_MEM_PINS_PINLOC_13[29:0],UNUSED_MEM_PINS_PINLOC_12[29:0],UNUSED_MEM_PINS_PINLOC_11[29:0],UNUSED_MEM_PINS_PINLOC_10[29:0],UNUSED_MEM_PINS_PINLOC_9[29:0],UNUSED_MEM_PINS_PINLOC_8[29:0],UNUSED_MEM_PINS_PINLOC_7[29:0],UNUSED_MEM_PINS_PINLOC_6[29:0],UNUSED_MEM_PINS_PINLOC_5[29:0],UNUSED_MEM_PINS_PINLOC_4[29:0],UNUSED_MEM_PINS_PINLOC_3[29:0],UNUSED_MEM_PINS_PINLOC_2[29:0],UNUSED_MEM_PINS_PINLOC_1[29:0],UNUSED_MEM_PINS_PINLOC_0[29:0]}; + localparam UNUSED_DQS_BUSES_LANELOC = {UNUSED_DQS_BUSES_LANELOC_10[29:0],UNUSED_DQS_BUSES_LANELOC_9[29:0],UNUSED_DQS_BUSES_LANELOC_8[29:0],UNUSED_DQS_BUSES_LANELOC_7[29:0],UNUSED_DQS_BUSES_LANELOC_6[29:0],UNUSED_DQS_BUSES_LANELOC_5[29:0],UNUSED_DQS_BUSES_LANELOC_4[29:0],UNUSED_DQS_BUSES_LANELOC_3[29:0],UNUSED_DQS_BUSES_LANELOC_2[29:0],UNUSED_DQS_BUSES_LANELOC_1[29:0],UNUSED_DQS_BUSES_LANELOC_0[29:0]}; + localparam DBC_PIPE_LATS = {DBC_PIPE_LATS_4[29:0],DBC_PIPE_LATS_3[29:0],DBC_PIPE_LATS_2[29:0],DBC_PIPE_LATS_1[29:0],DBC_PIPE_LATS_0[29:0]}; + localparam DB_PTR_PIPELINE_DEPTHS = {DB_PTR_PIPELINE_DEPTHS_4[29:0],DB_PTR_PIPELINE_DEPTHS_3[29:0],DB_PTR_PIPELINE_DEPTHS_2[29:0],DB_PTR_PIPELINE_DEPTHS_1[29:0],DB_PTR_PIPELINE_DEPTHS_0[29:0]}; + localparam DB_SEQ_RD_EN_FULL_PIPELINES = {DB_SEQ_RD_EN_FULL_PIPELINES_4[29:0],DB_SEQ_RD_EN_FULL_PIPELINES_3[29:0],DB_SEQ_RD_EN_FULL_PIPELINES_2[29:0],DB_SEQ_RD_EN_FULL_PIPELINES_1[29:0],DB_SEQ_RD_EN_FULL_PIPELINES_0[29:0]}; + localparam CENTER_TIDS = {CENTER_TIDS_2[29:0],CENTER_TIDS_1[29:0],CENTER_TIDS_0[29:0]}; + localparam HMC_TIDS = {HMC_TIDS_2[29:0],HMC_TIDS_1[29:0],HMC_TIDS_0[29:0]}; + localparam LANE_TIDS = {LANE_TIDS_9[29:0],LANE_TIDS_8[29:0],LANE_TIDS_7[29:0],LANE_TIDS_6[29:0],LANE_TIDS_5[29:0],LANE_TIDS_4[29:0],LANE_TIDS_3[29:0],LANE_TIDS_2[29:0],LANE_TIDS_1[29:0],LANE_TIDS_0[29:0]}; + localparam PORT_MEM_CK_PINLOC = {PORT_MEM_CK_PINLOC_5[29:0],PORT_MEM_CK_PINLOC_4[29:0],PORT_MEM_CK_PINLOC_3[29:0],PORT_MEM_CK_PINLOC_2[29:0],PORT_MEM_CK_PINLOC_1[29:0],PORT_MEM_CK_PINLOC_0[29:0]}; + localparam PORT_MEM_CK_N_PINLOC = {PORT_MEM_CK_N_PINLOC_5[29:0],PORT_MEM_CK_N_PINLOC_4[29:0],PORT_MEM_CK_N_PINLOC_3[29:0],PORT_MEM_CK_N_PINLOC_2[29:0],PORT_MEM_CK_N_PINLOC_1[29:0],PORT_MEM_CK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DK_PINLOC = {PORT_MEM_DK_PINLOC_5[29:0],PORT_MEM_DK_PINLOC_4[29:0],PORT_MEM_DK_PINLOC_3[29:0],PORT_MEM_DK_PINLOC_2[29:0],PORT_MEM_DK_PINLOC_1[29:0],PORT_MEM_DK_PINLOC_0[29:0]}; + localparam PORT_MEM_DK_N_PINLOC = {PORT_MEM_DK_N_PINLOC_5[29:0],PORT_MEM_DK_N_PINLOC_4[29:0],PORT_MEM_DK_N_PINLOC_3[29:0],PORT_MEM_DK_N_PINLOC_2[29:0],PORT_MEM_DK_N_PINLOC_1[29:0],PORT_MEM_DK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DKA_PINLOC = {PORT_MEM_DKA_PINLOC_5[29:0],PORT_MEM_DKA_PINLOC_4[29:0],PORT_MEM_DKA_PINLOC_3[29:0],PORT_MEM_DKA_PINLOC_2[29:0],PORT_MEM_DKA_PINLOC_1[29:0],PORT_MEM_DKA_PINLOC_0[29:0]}; + localparam PORT_MEM_DKA_N_PINLOC = {PORT_MEM_DKA_N_PINLOC_5[29:0],PORT_MEM_DKA_N_PINLOC_4[29:0],PORT_MEM_DKA_N_PINLOC_3[29:0],PORT_MEM_DKA_N_PINLOC_2[29:0],PORT_MEM_DKA_N_PINLOC_1[29:0],PORT_MEM_DKA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DKB_PINLOC = {PORT_MEM_DKB_PINLOC_5[29:0],PORT_MEM_DKB_PINLOC_4[29:0],PORT_MEM_DKB_PINLOC_3[29:0],PORT_MEM_DKB_PINLOC_2[29:0],PORT_MEM_DKB_PINLOC_1[29:0],PORT_MEM_DKB_PINLOC_0[29:0]}; + localparam PORT_MEM_DKB_N_PINLOC = {PORT_MEM_DKB_N_PINLOC_5[29:0],PORT_MEM_DKB_N_PINLOC_4[29:0],PORT_MEM_DKB_N_PINLOC_3[29:0],PORT_MEM_DKB_N_PINLOC_2[29:0],PORT_MEM_DKB_N_PINLOC_1[29:0],PORT_MEM_DKB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_K_PINLOC = {PORT_MEM_K_PINLOC_5[29:0],PORT_MEM_K_PINLOC_4[29:0],PORT_MEM_K_PINLOC_3[29:0],PORT_MEM_K_PINLOC_2[29:0],PORT_MEM_K_PINLOC_1[29:0],PORT_MEM_K_PINLOC_0[29:0]}; + localparam PORT_MEM_K_N_PINLOC = {PORT_MEM_K_N_PINLOC_5[29:0],PORT_MEM_K_N_PINLOC_4[29:0],PORT_MEM_K_N_PINLOC_3[29:0],PORT_MEM_K_N_PINLOC_2[29:0],PORT_MEM_K_N_PINLOC_1[29:0],PORT_MEM_K_N_PINLOC_0[29:0]}; + localparam PORT_MEM_A_PINLOC = {PORT_MEM_A_PINLOC_16[29:0],PORT_MEM_A_PINLOC_15[29:0],PORT_MEM_A_PINLOC_14[29:0],PORT_MEM_A_PINLOC_13[29:0],PORT_MEM_A_PINLOC_12[29:0],PORT_MEM_A_PINLOC_11[29:0],PORT_MEM_A_PINLOC_10[29:0],PORT_MEM_A_PINLOC_9[29:0],PORT_MEM_A_PINLOC_8[29:0],PORT_MEM_A_PINLOC_7[29:0],PORT_MEM_A_PINLOC_6[29:0],PORT_MEM_A_PINLOC_5[29:0],PORT_MEM_A_PINLOC_4[29:0],PORT_MEM_A_PINLOC_3[29:0],PORT_MEM_A_PINLOC_2[29:0],PORT_MEM_A_PINLOC_1[29:0],PORT_MEM_A_PINLOC_0[29:0]}; + localparam PORT_MEM_BA_PINLOC = {PORT_MEM_BA_PINLOC_5[29:0],PORT_MEM_BA_PINLOC_4[29:0],PORT_MEM_BA_PINLOC_3[29:0],PORT_MEM_BA_PINLOC_2[29:0],PORT_MEM_BA_PINLOC_1[29:0],PORT_MEM_BA_PINLOC_0[29:0]}; + localparam PORT_MEM_BG_PINLOC = {PORT_MEM_BG_PINLOC_5[29:0],PORT_MEM_BG_PINLOC_4[29:0],PORT_MEM_BG_PINLOC_3[29:0],PORT_MEM_BG_PINLOC_2[29:0],PORT_MEM_BG_PINLOC_1[29:0],PORT_MEM_BG_PINLOC_0[29:0]}; + localparam PORT_MEM_C_PINLOC = {PORT_MEM_C_PINLOC_5[29:0],PORT_MEM_C_PINLOC_4[29:0],PORT_MEM_C_PINLOC_3[29:0],PORT_MEM_C_PINLOC_2[29:0],PORT_MEM_C_PINLOC_1[29:0],PORT_MEM_C_PINLOC_0[29:0]}; + localparam PORT_MEM_CKE_PINLOC = {PORT_MEM_CKE_PINLOC_5[29:0],PORT_MEM_CKE_PINLOC_4[29:0],PORT_MEM_CKE_PINLOC_3[29:0],PORT_MEM_CKE_PINLOC_2[29:0],PORT_MEM_CKE_PINLOC_1[29:0],PORT_MEM_CKE_PINLOC_0[29:0]}; + localparam PORT_MEM_CS_N_PINLOC = {PORT_MEM_CS_N_PINLOC_5[29:0],PORT_MEM_CS_N_PINLOC_4[29:0],PORT_MEM_CS_N_PINLOC_3[29:0],PORT_MEM_CS_N_PINLOC_2[29:0],PORT_MEM_CS_N_PINLOC_1[29:0],PORT_MEM_CS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RM_PINLOC = {PORT_MEM_RM_PINLOC_5[29:0],PORT_MEM_RM_PINLOC_4[29:0],PORT_MEM_RM_PINLOC_3[29:0],PORT_MEM_RM_PINLOC_2[29:0],PORT_MEM_RM_PINLOC_1[29:0],PORT_MEM_RM_PINLOC_0[29:0]}; + localparam PORT_MEM_ODT_PINLOC = {PORT_MEM_ODT_PINLOC_5[29:0],PORT_MEM_ODT_PINLOC_4[29:0],PORT_MEM_ODT_PINLOC_3[29:0],PORT_MEM_ODT_PINLOC_2[29:0],PORT_MEM_ODT_PINLOC_1[29:0],PORT_MEM_ODT_PINLOC_0[29:0]}; + localparam PORT_MEM_RAS_N_PINLOC = {PORT_MEM_RAS_N_PINLOC_1[29:0],PORT_MEM_RAS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CAS_N_PINLOC = {PORT_MEM_CAS_N_PINLOC_1[29:0],PORT_MEM_CAS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_WE_N_PINLOC = {PORT_MEM_WE_N_PINLOC_1[29:0],PORT_MEM_WE_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RESET_N_PINLOC = {PORT_MEM_RESET_N_PINLOC_1[29:0],PORT_MEM_RESET_N_PINLOC_0[29:0]}; + localparam PORT_MEM_ACT_N_PINLOC = {PORT_MEM_ACT_N_PINLOC_1[29:0],PORT_MEM_ACT_N_PINLOC_0[29:0]}; + localparam PORT_MEM_PAR_PINLOC = {PORT_MEM_PAR_PINLOC_1[29:0],PORT_MEM_PAR_PINLOC_0[29:0]}; + localparam PORT_MEM_CA_PINLOC = {PORT_MEM_CA_PINLOC_16[29:0],PORT_MEM_CA_PINLOC_15[29:0],PORT_MEM_CA_PINLOC_14[29:0],PORT_MEM_CA_PINLOC_13[29:0],PORT_MEM_CA_PINLOC_12[29:0],PORT_MEM_CA_PINLOC_11[29:0],PORT_MEM_CA_PINLOC_10[29:0],PORT_MEM_CA_PINLOC_9[29:0],PORT_MEM_CA_PINLOC_8[29:0],PORT_MEM_CA_PINLOC_7[29:0],PORT_MEM_CA_PINLOC_6[29:0],PORT_MEM_CA_PINLOC_5[29:0],PORT_MEM_CA_PINLOC_4[29:0],PORT_MEM_CA_PINLOC_3[29:0],PORT_MEM_CA_PINLOC_2[29:0],PORT_MEM_CA_PINLOC_1[29:0],PORT_MEM_CA_PINLOC_0[29:0]}; + localparam PORT_MEM_REF_N_PINLOC = {PORT_MEM_REF_N_PINLOC_0[29:0]}; + localparam PORT_MEM_WPS_N_PINLOC = {PORT_MEM_WPS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RPS_N_PINLOC = {PORT_MEM_RPS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DOFF_N_PINLOC = {PORT_MEM_DOFF_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LDA_N_PINLOC = {PORT_MEM_LDA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LDB_N_PINLOC = {PORT_MEM_LDB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RWA_N_PINLOC = {PORT_MEM_RWA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RWB_N_PINLOC = {PORT_MEM_RWB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LBK0_N_PINLOC = {PORT_MEM_LBK0_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LBK1_N_PINLOC = {PORT_MEM_LBK1_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CFG_N_PINLOC = {PORT_MEM_CFG_N_PINLOC_0[29:0]}; + localparam PORT_MEM_AP_PINLOC = {PORT_MEM_AP_PINLOC_0[29:0]}; + localparam PORT_MEM_AINV_PINLOC = {PORT_MEM_AINV_PINLOC_0[29:0]}; + localparam PORT_MEM_DM_PINLOC = {PORT_MEM_DM_PINLOC_12[29:0],PORT_MEM_DM_PINLOC_11[29:0],PORT_MEM_DM_PINLOC_10[29:0],PORT_MEM_DM_PINLOC_9[29:0],PORT_MEM_DM_PINLOC_8[29:0],PORT_MEM_DM_PINLOC_7[29:0],PORT_MEM_DM_PINLOC_6[29:0],PORT_MEM_DM_PINLOC_5[29:0],PORT_MEM_DM_PINLOC_4[29:0],PORT_MEM_DM_PINLOC_3[29:0],PORT_MEM_DM_PINLOC_2[29:0],PORT_MEM_DM_PINLOC_1[29:0],PORT_MEM_DM_PINLOC_0[29:0]}; + localparam PORT_MEM_BWS_N_PINLOC = {PORT_MEM_BWS_N_PINLOC_2[29:0],PORT_MEM_BWS_N_PINLOC_1[29:0],PORT_MEM_BWS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_D_PINLOC = {PORT_MEM_D_PINLOC_48[29:0],PORT_MEM_D_PINLOC_47[29:0],PORT_MEM_D_PINLOC_46[29:0],PORT_MEM_D_PINLOC_45[29:0],PORT_MEM_D_PINLOC_44[29:0],PORT_MEM_D_PINLOC_43[29:0],PORT_MEM_D_PINLOC_42[29:0],PORT_MEM_D_PINLOC_41[29:0],PORT_MEM_D_PINLOC_40[29:0],PORT_MEM_D_PINLOC_39[29:0],PORT_MEM_D_PINLOC_38[29:0],PORT_MEM_D_PINLOC_37[29:0],PORT_MEM_D_PINLOC_36[29:0],PORT_MEM_D_PINLOC_35[29:0],PORT_MEM_D_PINLOC_34[29:0],PORT_MEM_D_PINLOC_33[29:0],PORT_MEM_D_PINLOC_32[29:0],PORT_MEM_D_PINLOC_31[29:0],PORT_MEM_D_PINLOC_30[29:0],PORT_MEM_D_PINLOC_29[29:0],PORT_MEM_D_PINLOC_28[29:0],PORT_MEM_D_PINLOC_27[29:0],PORT_MEM_D_PINLOC_26[29:0],PORT_MEM_D_PINLOC_25[29:0],PORT_MEM_D_PINLOC_24[29:0],PORT_MEM_D_PINLOC_23[29:0],PORT_MEM_D_PINLOC_22[29:0],PORT_MEM_D_PINLOC_21[29:0],PORT_MEM_D_PINLOC_20[29:0],PORT_MEM_D_PINLOC_19[29:0],PORT_MEM_D_PINLOC_18[29:0],PORT_MEM_D_PINLOC_17[29:0],PORT_MEM_D_PINLOC_16[29:0],PORT_MEM_D_PINLOC_15[29:0],PORT_MEM_D_PINLOC_14[29:0],PORT_MEM_D_PINLOC_13[29:0],PORT_MEM_D_PINLOC_12[29:0],PORT_MEM_D_PINLOC_11[29:0],PORT_MEM_D_PINLOC_10[29:0],PORT_MEM_D_PINLOC_9[29:0],PORT_MEM_D_PINLOC_8[29:0],PORT_MEM_D_PINLOC_7[29:0],PORT_MEM_D_PINLOC_6[29:0],PORT_MEM_D_PINLOC_5[29:0],PORT_MEM_D_PINLOC_4[29:0],PORT_MEM_D_PINLOC_3[29:0],PORT_MEM_D_PINLOC_2[29:0],PORT_MEM_D_PINLOC_1[29:0],PORT_MEM_D_PINLOC_0[29:0]}; + localparam PORT_MEM_DQ_PINLOC = {PORT_MEM_DQ_PINLOC_48[29:0],PORT_MEM_DQ_PINLOC_47[29:0],PORT_MEM_DQ_PINLOC_46[29:0],PORT_MEM_DQ_PINLOC_45[29:0],PORT_MEM_DQ_PINLOC_44[29:0],PORT_MEM_DQ_PINLOC_43[29:0],PORT_MEM_DQ_PINLOC_42[29:0],PORT_MEM_DQ_PINLOC_41[29:0],PORT_MEM_DQ_PINLOC_40[29:0],PORT_MEM_DQ_PINLOC_39[29:0],PORT_MEM_DQ_PINLOC_38[29:0],PORT_MEM_DQ_PINLOC_37[29:0],PORT_MEM_DQ_PINLOC_36[29:0],PORT_MEM_DQ_PINLOC_35[29:0],PORT_MEM_DQ_PINLOC_34[29:0],PORT_MEM_DQ_PINLOC_33[29:0],PORT_MEM_DQ_PINLOC_32[29:0],PORT_MEM_DQ_PINLOC_31[29:0],PORT_MEM_DQ_PINLOC_30[29:0],PORT_MEM_DQ_PINLOC_29[29:0],PORT_MEM_DQ_PINLOC_28[29:0],PORT_MEM_DQ_PINLOC_27[29:0],PORT_MEM_DQ_PINLOC_26[29:0],PORT_MEM_DQ_PINLOC_25[29:0],PORT_MEM_DQ_PINLOC_24[29:0],PORT_MEM_DQ_PINLOC_23[29:0],PORT_MEM_DQ_PINLOC_22[29:0],PORT_MEM_DQ_PINLOC_21[29:0],PORT_MEM_DQ_PINLOC_20[29:0],PORT_MEM_DQ_PINLOC_19[29:0],PORT_MEM_DQ_PINLOC_18[29:0],PORT_MEM_DQ_PINLOC_17[29:0],PORT_MEM_DQ_PINLOC_16[29:0],PORT_MEM_DQ_PINLOC_15[29:0],PORT_MEM_DQ_PINLOC_14[29:0],PORT_MEM_DQ_PINLOC_13[29:0],PORT_MEM_DQ_PINLOC_12[29:0],PORT_MEM_DQ_PINLOC_11[29:0],PORT_MEM_DQ_PINLOC_10[29:0],PORT_MEM_DQ_PINLOC_9[29:0],PORT_MEM_DQ_PINLOC_8[29:0],PORT_MEM_DQ_PINLOC_7[29:0],PORT_MEM_DQ_PINLOC_6[29:0],PORT_MEM_DQ_PINLOC_5[29:0],PORT_MEM_DQ_PINLOC_4[29:0],PORT_MEM_DQ_PINLOC_3[29:0],PORT_MEM_DQ_PINLOC_2[29:0],PORT_MEM_DQ_PINLOC_1[29:0],PORT_MEM_DQ_PINLOC_0[29:0]}; + localparam PORT_MEM_DBI_N_PINLOC = {PORT_MEM_DBI_N_PINLOC_6[29:0],PORT_MEM_DBI_N_PINLOC_5[29:0],PORT_MEM_DBI_N_PINLOC_4[29:0],PORT_MEM_DBI_N_PINLOC_3[29:0],PORT_MEM_DBI_N_PINLOC_2[29:0],PORT_MEM_DBI_N_PINLOC_1[29:0],PORT_MEM_DBI_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DQA_PINLOC = {PORT_MEM_DQA_PINLOC_48[29:0],PORT_MEM_DQA_PINLOC_47[29:0],PORT_MEM_DQA_PINLOC_46[29:0],PORT_MEM_DQA_PINLOC_45[29:0],PORT_MEM_DQA_PINLOC_44[29:0],PORT_MEM_DQA_PINLOC_43[29:0],PORT_MEM_DQA_PINLOC_42[29:0],PORT_MEM_DQA_PINLOC_41[29:0],PORT_MEM_DQA_PINLOC_40[29:0],PORT_MEM_DQA_PINLOC_39[29:0],PORT_MEM_DQA_PINLOC_38[29:0],PORT_MEM_DQA_PINLOC_37[29:0],PORT_MEM_DQA_PINLOC_36[29:0],PORT_MEM_DQA_PINLOC_35[29:0],PORT_MEM_DQA_PINLOC_34[29:0],PORT_MEM_DQA_PINLOC_33[29:0],PORT_MEM_DQA_PINLOC_32[29:0],PORT_MEM_DQA_PINLOC_31[29:0],PORT_MEM_DQA_PINLOC_30[29:0],PORT_MEM_DQA_PINLOC_29[29:0],PORT_MEM_DQA_PINLOC_28[29:0],PORT_MEM_DQA_PINLOC_27[29:0],PORT_MEM_DQA_PINLOC_26[29:0],PORT_MEM_DQA_PINLOC_25[29:0],PORT_MEM_DQA_PINLOC_24[29:0],PORT_MEM_DQA_PINLOC_23[29:0],PORT_MEM_DQA_PINLOC_22[29:0],PORT_MEM_DQA_PINLOC_21[29:0],PORT_MEM_DQA_PINLOC_20[29:0],PORT_MEM_DQA_PINLOC_19[29:0],PORT_MEM_DQA_PINLOC_18[29:0],PORT_MEM_DQA_PINLOC_17[29:0],PORT_MEM_DQA_PINLOC_16[29:0],PORT_MEM_DQA_PINLOC_15[29:0],PORT_MEM_DQA_PINLOC_14[29:0],PORT_MEM_DQA_PINLOC_13[29:0],PORT_MEM_DQA_PINLOC_12[29:0],PORT_MEM_DQA_PINLOC_11[29:0],PORT_MEM_DQA_PINLOC_10[29:0],PORT_MEM_DQA_PINLOC_9[29:0],PORT_MEM_DQA_PINLOC_8[29:0],PORT_MEM_DQA_PINLOC_7[29:0],PORT_MEM_DQA_PINLOC_6[29:0],PORT_MEM_DQA_PINLOC_5[29:0],PORT_MEM_DQA_PINLOC_4[29:0],PORT_MEM_DQA_PINLOC_3[29:0],PORT_MEM_DQA_PINLOC_2[29:0],PORT_MEM_DQA_PINLOC_1[29:0],PORT_MEM_DQA_PINLOC_0[29:0]}; + localparam PORT_MEM_DQB_PINLOC = {PORT_MEM_DQB_PINLOC_48[29:0],PORT_MEM_DQB_PINLOC_47[29:0],PORT_MEM_DQB_PINLOC_46[29:0],PORT_MEM_DQB_PINLOC_45[29:0],PORT_MEM_DQB_PINLOC_44[29:0],PORT_MEM_DQB_PINLOC_43[29:0],PORT_MEM_DQB_PINLOC_42[29:0],PORT_MEM_DQB_PINLOC_41[29:0],PORT_MEM_DQB_PINLOC_40[29:0],PORT_MEM_DQB_PINLOC_39[29:0],PORT_MEM_DQB_PINLOC_38[29:0],PORT_MEM_DQB_PINLOC_37[29:0],PORT_MEM_DQB_PINLOC_36[29:0],PORT_MEM_DQB_PINLOC_35[29:0],PORT_MEM_DQB_PINLOC_34[29:0],PORT_MEM_DQB_PINLOC_33[29:0],PORT_MEM_DQB_PINLOC_32[29:0],PORT_MEM_DQB_PINLOC_31[29:0],PORT_MEM_DQB_PINLOC_30[29:0],PORT_MEM_DQB_PINLOC_29[29:0],PORT_MEM_DQB_PINLOC_28[29:0],PORT_MEM_DQB_PINLOC_27[29:0],PORT_MEM_DQB_PINLOC_26[29:0],PORT_MEM_DQB_PINLOC_25[29:0],PORT_MEM_DQB_PINLOC_24[29:0],PORT_MEM_DQB_PINLOC_23[29:0],PORT_MEM_DQB_PINLOC_22[29:0],PORT_MEM_DQB_PINLOC_21[29:0],PORT_MEM_DQB_PINLOC_20[29:0],PORT_MEM_DQB_PINLOC_19[29:0],PORT_MEM_DQB_PINLOC_18[29:0],PORT_MEM_DQB_PINLOC_17[29:0],PORT_MEM_DQB_PINLOC_16[29:0],PORT_MEM_DQB_PINLOC_15[29:0],PORT_MEM_DQB_PINLOC_14[29:0],PORT_MEM_DQB_PINLOC_13[29:0],PORT_MEM_DQB_PINLOC_12[29:0],PORT_MEM_DQB_PINLOC_11[29:0],PORT_MEM_DQB_PINLOC_10[29:0],PORT_MEM_DQB_PINLOC_9[29:0],PORT_MEM_DQB_PINLOC_8[29:0],PORT_MEM_DQB_PINLOC_7[29:0],PORT_MEM_DQB_PINLOC_6[29:0],PORT_MEM_DQB_PINLOC_5[29:0],PORT_MEM_DQB_PINLOC_4[29:0],PORT_MEM_DQB_PINLOC_3[29:0],PORT_MEM_DQB_PINLOC_2[29:0],PORT_MEM_DQB_PINLOC_1[29:0],PORT_MEM_DQB_PINLOC_0[29:0]}; + localparam PORT_MEM_DINVA_PINLOC = {PORT_MEM_DINVA_PINLOC_2[29:0],PORT_MEM_DINVA_PINLOC_1[29:0],PORT_MEM_DINVA_PINLOC_0[29:0]}; + localparam PORT_MEM_DINVB_PINLOC = {PORT_MEM_DINVB_PINLOC_2[29:0],PORT_MEM_DINVB_PINLOC_1[29:0],PORT_MEM_DINVB_PINLOC_0[29:0]}; + localparam PORT_MEM_Q_PINLOC = {PORT_MEM_Q_PINLOC_48[29:0],PORT_MEM_Q_PINLOC_47[29:0],PORT_MEM_Q_PINLOC_46[29:0],PORT_MEM_Q_PINLOC_45[29:0],PORT_MEM_Q_PINLOC_44[29:0],PORT_MEM_Q_PINLOC_43[29:0],PORT_MEM_Q_PINLOC_42[29:0],PORT_MEM_Q_PINLOC_41[29:0],PORT_MEM_Q_PINLOC_40[29:0],PORT_MEM_Q_PINLOC_39[29:0],PORT_MEM_Q_PINLOC_38[29:0],PORT_MEM_Q_PINLOC_37[29:0],PORT_MEM_Q_PINLOC_36[29:0],PORT_MEM_Q_PINLOC_35[29:0],PORT_MEM_Q_PINLOC_34[29:0],PORT_MEM_Q_PINLOC_33[29:0],PORT_MEM_Q_PINLOC_32[29:0],PORT_MEM_Q_PINLOC_31[29:0],PORT_MEM_Q_PINLOC_30[29:0],PORT_MEM_Q_PINLOC_29[29:0],PORT_MEM_Q_PINLOC_28[29:0],PORT_MEM_Q_PINLOC_27[29:0],PORT_MEM_Q_PINLOC_26[29:0],PORT_MEM_Q_PINLOC_25[29:0],PORT_MEM_Q_PINLOC_24[29:0],PORT_MEM_Q_PINLOC_23[29:0],PORT_MEM_Q_PINLOC_22[29:0],PORT_MEM_Q_PINLOC_21[29:0],PORT_MEM_Q_PINLOC_20[29:0],PORT_MEM_Q_PINLOC_19[29:0],PORT_MEM_Q_PINLOC_18[29:0],PORT_MEM_Q_PINLOC_17[29:0],PORT_MEM_Q_PINLOC_16[29:0],PORT_MEM_Q_PINLOC_15[29:0],PORT_MEM_Q_PINLOC_14[29:0],PORT_MEM_Q_PINLOC_13[29:0],PORT_MEM_Q_PINLOC_12[29:0],PORT_MEM_Q_PINLOC_11[29:0],PORT_MEM_Q_PINLOC_10[29:0],PORT_MEM_Q_PINLOC_9[29:0],PORT_MEM_Q_PINLOC_8[29:0],PORT_MEM_Q_PINLOC_7[29:0],PORT_MEM_Q_PINLOC_6[29:0],PORT_MEM_Q_PINLOC_5[29:0],PORT_MEM_Q_PINLOC_4[29:0],PORT_MEM_Q_PINLOC_3[29:0],PORT_MEM_Q_PINLOC_2[29:0],PORT_MEM_Q_PINLOC_1[29:0],PORT_MEM_Q_PINLOC_0[29:0]}; + localparam PORT_MEM_DQS_PINLOC = {PORT_MEM_DQS_PINLOC_12[29:0],PORT_MEM_DQS_PINLOC_11[29:0],PORT_MEM_DQS_PINLOC_10[29:0],PORT_MEM_DQS_PINLOC_9[29:0],PORT_MEM_DQS_PINLOC_8[29:0],PORT_MEM_DQS_PINLOC_7[29:0],PORT_MEM_DQS_PINLOC_6[29:0],PORT_MEM_DQS_PINLOC_5[29:0],PORT_MEM_DQS_PINLOC_4[29:0],PORT_MEM_DQS_PINLOC_3[29:0],PORT_MEM_DQS_PINLOC_2[29:0],PORT_MEM_DQS_PINLOC_1[29:0],PORT_MEM_DQS_PINLOC_0[29:0]}; + localparam PORT_MEM_DQS_N_PINLOC = {PORT_MEM_DQS_N_PINLOC_12[29:0],PORT_MEM_DQS_N_PINLOC_11[29:0],PORT_MEM_DQS_N_PINLOC_10[29:0],PORT_MEM_DQS_N_PINLOC_9[29:0],PORT_MEM_DQS_N_PINLOC_8[29:0],PORT_MEM_DQS_N_PINLOC_7[29:0],PORT_MEM_DQS_N_PINLOC_6[29:0],PORT_MEM_DQS_N_PINLOC_5[29:0],PORT_MEM_DQS_N_PINLOC_4[29:0],PORT_MEM_DQS_N_PINLOC_3[29:0],PORT_MEM_DQS_N_PINLOC_2[29:0],PORT_MEM_DQS_N_PINLOC_1[29:0],PORT_MEM_DQS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QK_PINLOC = {PORT_MEM_QK_PINLOC_5[29:0],PORT_MEM_QK_PINLOC_4[29:0],PORT_MEM_QK_PINLOC_3[29:0],PORT_MEM_QK_PINLOC_2[29:0],PORT_MEM_QK_PINLOC_1[29:0],PORT_MEM_QK_PINLOC_0[29:0]}; + localparam PORT_MEM_QK_N_PINLOC = {PORT_MEM_QK_N_PINLOC_5[29:0],PORT_MEM_QK_N_PINLOC_4[29:0],PORT_MEM_QK_N_PINLOC_3[29:0],PORT_MEM_QK_N_PINLOC_2[29:0],PORT_MEM_QK_N_PINLOC_1[29:0],PORT_MEM_QK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QKA_PINLOC = {PORT_MEM_QKA_PINLOC_5[29:0],PORT_MEM_QKA_PINLOC_4[29:0],PORT_MEM_QKA_PINLOC_3[29:0],PORT_MEM_QKA_PINLOC_2[29:0],PORT_MEM_QKA_PINLOC_1[29:0],PORT_MEM_QKA_PINLOC_0[29:0]}; + localparam PORT_MEM_QKA_N_PINLOC = {PORT_MEM_QKA_N_PINLOC_5[29:0],PORT_MEM_QKA_N_PINLOC_4[29:0],PORT_MEM_QKA_N_PINLOC_3[29:0],PORT_MEM_QKA_N_PINLOC_2[29:0],PORT_MEM_QKA_N_PINLOC_1[29:0],PORT_MEM_QKA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QKB_PINLOC = {PORT_MEM_QKB_PINLOC_5[29:0],PORT_MEM_QKB_PINLOC_4[29:0],PORT_MEM_QKB_PINLOC_3[29:0],PORT_MEM_QKB_PINLOC_2[29:0],PORT_MEM_QKB_PINLOC_1[29:0],PORT_MEM_QKB_PINLOC_0[29:0]}; + localparam PORT_MEM_QKB_N_PINLOC = {PORT_MEM_QKB_N_PINLOC_5[29:0],PORT_MEM_QKB_N_PINLOC_4[29:0],PORT_MEM_QKB_N_PINLOC_3[29:0],PORT_MEM_QKB_N_PINLOC_2[29:0],PORT_MEM_QKB_N_PINLOC_1[29:0],PORT_MEM_QKB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CQ_PINLOC = {PORT_MEM_CQ_PINLOC_1[29:0],PORT_MEM_CQ_PINLOC_0[29:0]}; + localparam PORT_MEM_CQ_N_PINLOC = {PORT_MEM_CQ_N_PINLOC_1[29:0],PORT_MEM_CQ_N_PINLOC_0[29:0]}; + localparam PORT_MEM_ALERT_N_PINLOC = {PORT_MEM_ALERT_N_PINLOC_1[29:0],PORT_MEM_ALERT_N_PINLOC_0[29:0]}; + localparam PORT_MEM_PE_N_PINLOC = {PORT_MEM_PE_N_PINLOC_1[29:0],PORT_MEM_PE_N_PINLOC_0[29:0]}; + + localparam LANES_IN_RTL_TILES = NUM_OF_RTL_TILES * LANES_PER_TILE; + localparam PINS_IN_RTL_TILES = NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE; + + // Select which DBC to use as shadow for the primary HMC. + // We always pick "dbc1_to_local" as it's guaranteed to be used by the interface (as an A/C lane). + localparam PRI_HMC_DBC_SHADOW_LANE_INDEX = 1; + localparam UFI_LATENCY =(NUM_OF_HMC_PORTS == 0) ? 2 : HMC_READY_LATENCY; + + // The actual PLL ref clock signal, selected from either the local signal or from master + logic pll_ref_clk_int; + + // The actual reset request signal, selected from either the local signal or from master + logic local_reset_req_int; + + // Signals for various clocks + logic pll_dll_clk; // PLL -> DLL output clock + logic [7:0] phy_clk_phs; // FR PHY clock signals (8 phases, 45-deg apart) + logic [1:0] phy_clk; // {phy_clk[1], phy_clk[0]} + logic [1:0] global_phy_clk; // {phy_clk[1], phy_clk[0]} + logic phy_fb_clk_to_tile; // PHY feedback clock (to tile) + logic phy_fb_clk_to_pll; // PHY feedback clock (to PLL) + logic [8:0] pll_c_counters; // PLL C counter outputs + logic pll_extra_clk_diag_ok; // Internal test signal for PLL extra clocks + + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + logic [1:0] core_clks_from_cpa_pri; + logic [1:0] core_clks_locked_cpa_pri; + logic [1:0] core_clks_fb_to_cpa_pri; + logic [1:0] core_clks_from_cpa_sec; + logic [1:0] core_clks_locked_cpa_sec; + logic [1:0] core_clks_fb_to_cpa_sec; + logic seq2core_reset_n; + + /////////////////////////////////////////////////////////////////// + // C2P & P2C interconnecting wires in/out towards UFIs + /////////////////////////////////////////////////////////////////// + // Avalon interfaces between core and HMC + logic [62:0] core2ctl_avl_0; + logic [62:0] core2ctl_avl_1; + logic core2ctl_avl_rd_data_ready_0; + logic core2ctl_avl_rd_data_ready_1; + logic ctl2core_avl_cmd_ready_0; + logic ctl2core_avl_cmd_ready_1; + logic [12:0] ctl2core_avl_rdata_id_0; + logic [12:0] ctl2core_avl_rdata_id_1; + + // Avalon interfaces between core and lanes + logic l2core_rd_data_vld_avl; + logic l2core_wr_data_rdy_ast; + logic l2core_rd_type; + + logic core2l_wr_data_vld_ast; + logic core2l_rd_data_rdy_ast; + + // ECC signals between core and lanes + logic [12:0] core2l_wr_ecc_info; + logic [11:0] l2core_wb_pointer_for_ecc; + + // Signals between core and data lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] core2l_oe; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_read; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] core2l_mrnk_write; + logic [3:0] l2core_rdata_valid_pri; + logic [3:0] l2core_rdata_valid_sec; + logic [5:0] l2core_afi_rlat; + logic [5:0] l2core_afi_wlat; + + // AFI signals between tile and core + logic [17:0] c2t_afi; + logic [26:0] t2c_afi; + + // Side-band signals between core and HMC + logic [41:0] core2ctl_sideband_0; + logic [13:0] ctl2core_sideband_0; + logic [41:0] core2ctl_sideband_1; + logic [13:0] ctl2core_sideband_1; + + + // MMR signals between core and HMC + logic [33:0] ctl2core_mmr_0; + logic [50:0] core2ctl_mmr_0; + logic [33:0] ctl2core_mmr_1; + logic [50:0] core2ctl_mmr_1; + + // Output from UFIs + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] actual_core2l_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][47:0] actual_core2l_oe; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] actual_core2l_rdata_en_full; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] actual_core2l_mrnk_read; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] actual_core2l_mrnk_write; + logic actual_l2core_rd_type; + logic [3:0] actual_l2core_rdata_valid_pri; + logic [3:0] actual_l2core_rdata_valid_sec; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][12:0] actual_core2l_wr_ecc_info; + logic [11:0] actual_l2core_wb_pointer_for_ecc; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] actual_core2l_wr_data_vld_ast; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] actual_core2l_rd_data_rdy_ast; + + + logic [62:0] actual_core2ctl_avl_0; + logic actual_core2ctl_avl_rd_data_ready_0; + logic [62:0] actual_core2ctl_avl_1; + logic actual_core2ctl_avl_rd_data_ready_1; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] actual_l2core_data; + logic actual_l2core_rd_data_vld_avl; + logic actual_l2core_wr_data_rdy_ast; + logic actual_ctl2core_avl_cmd_ready_0; + logic actual_ctl2core_avl_cmd_ready_1; + logic [12:0] actual_ctl2core_avl_rdata_id_0; + logic [12:0] actual_ctl2core_avl_rdata_id_1; + + logic [33:0] actual_ctl2core_mmr_0; + logic [50:0] actual_core2ctl_mmr_0; + logic [33:0] actual_ctl2core_mmr_1; + logic [50:0] actual_core2ctl_mmr_1; + logic [41:0] actual_core2ctl_sideband_0; + logic [13:0] actual_ctl2core_sideband_0; + logic [41:0] actual_core2ctl_sideband_1; + logic [13:0] actual_ctl2core_sideband_1; + + logic [17:0] actual_c2t_afi; + logic [26:0] actual_t2c_afi; + + // Signals for connecting OCT block to I/O buffers + logic oct_rzqin2ter; + logic oct_termin; + + // Signals for connecting emif signals between lanes/tiles and I/O buffers + logic [PINS_IN_RTL_TILES-1:0] l2b_data; // lane-to-buffer data + logic [PINS_IN_RTL_TILES-1:0] l2b_oe; // lane-to-buffer output-enable + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc; // lane-to-buffer dynamic-termination-control + logic [PINS_IN_RTL_TILES-1:0] b2l_data; // buffer-to-lane data + logic [LANES_IN_RTL_TILES-1:0] b2t_dqs; // buffer-to-tile DQS + logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb; // buffer-to-tile DQSb + + // Reset related + logic seq2core_reset_done; + logic core2seq_reset_req; + + // Internal signal for cal_counter + logic afi_cal_in_progress; + + assign local_cal_success = afi_cal_success & pll_extra_clk_diag_ok; + assign local_cal_fail = afi_cal_fail; + assign pll_ref_clk_out = pll_ref_clk_int; + assign clks_sharing_slave_out = clks_sharing_slave_in; + + wire runAbstractPhySim; + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALP"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_success ( + .probe (local_cal_success) + ); + + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALF"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_fail ( + .probe (local_cal_fail) + ); + + // Parity ISSP checks DDR4 parity flag in firmware. Currently only used for DDR4 + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PRTY"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) ac_parity_check ( + .probe (ac_parity_err) + ); + + +`endif + + //////////////////////////////////////////////////////////////////////////// + // PLL + //////////////////////////////////////////////////////////////////////////// + generate + // synthesis translate_off + if (DIAG_FAST_SIM) begin : gen_fast_sim + altera_emif_arch_fm_pll_fast_sim # ( + .PLL_SIM_VCO_FREQ_PS (PLL_SIM_VCO_FREQ_PS), + .PLL_SIM_PHYCLK_0_FREQ_PS (PLL_SIM_PHYCLK_0_FREQ_PS), + .PLL_SIM_PHYCLK_1_FREQ_PS (PLL_SIM_PHYCLK_1_FREQ_PS), + .PLL_SIM_PHYCLK_FB_FREQ_PS (PLL_SIM_PHYCLK_FB_FREQ_PS), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (PLL_SIM_PHY_CLK_VCO_PHASE_PS), + .PORT_DFT_ND_PLL_CNTSEL_WIDTH (PORT_DFT_ND_PLL_CNTSEL_WIDTH), + .PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH (PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH), + .PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH (PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH) + ) pll_inst ( + .* + ); + end else begin : gen_normal + // synthesis translate_on + altera_emif_arch_fm_pll # ( + .PORT_DFT_ND_PLL_CNTSEL_WIDTH (PORT_DFT_ND_PLL_CNTSEL_WIDTH), + .PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH (PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH), + .PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH (PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH), + .PLL_REF_CLK_FREQ_PS_STR (PLL_REF_CLK_FREQ_PS_STR), + .PLL_REF_CLK_FREQ_MHZ_STR (PLL_REF_CLK_FREQ_MHZ_STR), + .PLL_VCO_FREQ_PS_STR (PLL_VCO_FREQ_PS_STR), + .PLL_VCO_FREQ_MHZ_STR (PLL_VCO_FREQ_MHZ_STR), + .PLL_M_CNT_HIGH (PLL_M_CNT_HIGH), + .PLL_M_CNT_LOW (PLL_M_CNT_LOW), + .PLL_N_CNT_HIGH (PLL_N_CNT_HIGH), + .PLL_N_CNT_LOW (PLL_N_CNT_LOW), + .PLL_M_CNT_BYPASS_EN (PLL_M_CNT_BYPASS_EN), + .PLL_N_CNT_BYPASS_EN (PLL_N_CNT_BYPASS_EN), + .PLL_M_CNT_EVEN_DUTY_EN (PLL_M_CNT_EVEN_DUTY_EN), + .PLL_N_CNT_EVEN_DUTY_EN (PLL_N_CNT_EVEN_DUTY_EN), + .PLL_CP_SETTING (PLL_CP_SETTING), + .PLL_BW_CTRL (PLL_BW_CTRL), + .PLL_C_CNT_HIGH_0 (PLL_C_CNT_HIGH_0), + .PLL_C_CNT_LOW_0 (PLL_C_CNT_LOW_0), + .PLL_C_CNT_PRST_0 (PLL_C_CNT_PRST_0), + .PLL_C_CNT_PH_MUX_PRST_0 (PLL_C_CNT_PH_MUX_PRST_0), + .PLL_C_CNT_BYPASS_EN_0 (PLL_C_CNT_BYPASS_EN_0), + .PLL_C_CNT_EVEN_DUTY_EN_0 (PLL_C_CNT_EVEN_DUTY_EN_0), + .PLL_C_CNT_HIGH_1 (PLL_C_CNT_HIGH_1), + .PLL_C_CNT_LOW_1 (PLL_C_CNT_LOW_1), + .PLL_C_CNT_PRST_1 (PLL_C_CNT_PRST_1), + .PLL_C_CNT_PH_MUX_PRST_1 (PLL_C_CNT_PH_MUX_PRST_1), + .PLL_C_CNT_BYPASS_EN_1 (PLL_C_CNT_BYPASS_EN_1), + .PLL_C_CNT_EVEN_DUTY_EN_1 (PLL_C_CNT_EVEN_DUTY_EN_1), + .PLL_C_CNT_HIGH_2 (PLL_C_CNT_HIGH_2), + .PLL_C_CNT_LOW_2 (PLL_C_CNT_LOW_2), + .PLL_C_CNT_PRST_2 (PLL_C_CNT_PRST_2), + .PLL_C_CNT_PH_MUX_PRST_2 (PLL_C_CNT_PH_MUX_PRST_2), + .PLL_C_CNT_BYPASS_EN_2 (PLL_C_CNT_BYPASS_EN_2), + .PLL_C_CNT_EVEN_DUTY_EN_2 (PLL_C_CNT_EVEN_DUTY_EN_2), + .PLL_C_CNT_HIGH_3 (PLL_C_CNT_HIGH_3), + .PLL_C_CNT_LOW_3 (PLL_C_CNT_LOW_3), + .PLL_C_CNT_PRST_3 (PLL_C_CNT_PRST_3), + .PLL_C_CNT_PH_MUX_PRST_3 (PLL_C_CNT_PH_MUX_PRST_3), + .PLL_C_CNT_BYPASS_EN_3 (PLL_C_CNT_BYPASS_EN_3), + .PLL_C_CNT_EVEN_DUTY_EN_3 (PLL_C_CNT_EVEN_DUTY_EN_3), + .PLL_C_CNT_HIGH_4 (PLL_C_CNT_HIGH_4), + .PLL_C_CNT_LOW_4 (PLL_C_CNT_LOW_4), + .PLL_C_CNT_PRST_4 (PLL_C_CNT_PRST_4), + .PLL_C_CNT_PH_MUX_PRST_4 (PLL_C_CNT_PH_MUX_PRST_4), + .PLL_C_CNT_BYPASS_EN_4 (PLL_C_CNT_BYPASS_EN_4), + .PLL_C_CNT_EVEN_DUTY_EN_4 (PLL_C_CNT_EVEN_DUTY_EN_4), + .PLL_C_CNT_HIGH_5 (PLL_C_CNT_HIGH_5), + .PLL_C_CNT_LOW_5 (PLL_C_CNT_LOW_5), + .PLL_C_CNT_PRST_5 (PLL_C_CNT_PRST_5), + .PLL_C_CNT_PH_MUX_PRST_5 (PLL_C_CNT_PH_MUX_PRST_5), + .PLL_C_CNT_BYPASS_EN_5 (PLL_C_CNT_BYPASS_EN_5), + .PLL_C_CNT_EVEN_DUTY_EN_5 (PLL_C_CNT_EVEN_DUTY_EN_5), + .PLL_C_CNT_HIGH_6 (PLL_C_CNT_HIGH_6), + .PLL_C_CNT_LOW_6 (PLL_C_CNT_LOW_6), + .PLL_C_CNT_PRST_6 (PLL_C_CNT_PRST_6), + .PLL_C_CNT_PH_MUX_PRST_6 (PLL_C_CNT_PH_MUX_PRST_6), + .PLL_C_CNT_BYPASS_EN_6 (PLL_C_CNT_BYPASS_EN_6), + .PLL_C_CNT_EVEN_DUTY_EN_6 (PLL_C_CNT_EVEN_DUTY_EN_6), + .PLL_C_CNT_HIGH_7 (PLL_C_CNT_HIGH_7), + .PLL_C_CNT_LOW_7 (PLL_C_CNT_LOW_7), + .PLL_C_CNT_PRST_7 (PLL_C_CNT_PRST_7), + .PLL_C_CNT_PH_MUX_PRST_7 (PLL_C_CNT_PH_MUX_PRST_7), + .PLL_C_CNT_BYPASS_EN_7 (PLL_C_CNT_BYPASS_EN_7), + .PLL_C_CNT_EVEN_DUTY_EN_7 (PLL_C_CNT_EVEN_DUTY_EN_7), + .PLL_C_CNT_HIGH_8 (PLL_C_CNT_HIGH_8), + .PLL_C_CNT_LOW_8 (PLL_C_CNT_LOW_8), + .PLL_C_CNT_PRST_8 (PLL_C_CNT_PRST_8), + .PLL_C_CNT_PH_MUX_PRST_8 (PLL_C_CNT_PH_MUX_PRST_8), + .PLL_C_CNT_BYPASS_EN_8 (PLL_C_CNT_BYPASS_EN_8), + .PLL_C_CNT_EVEN_DUTY_EN_8 (PLL_C_CNT_EVEN_DUTY_EN_8), + .PLL_C_CNT_FREQ_PS_STR_0 (PLL_C_CNT_FREQ_PS_STR_0), + .PLL_C_CNT_PHASE_PS_STR_0 (PLL_C_CNT_PHASE_PS_STR_0), + .PLL_C_CNT_DUTY_CYCLE_0 (PLL_C_CNT_DUTY_CYCLE_0), + .PLL_C_CNT_FREQ_PS_STR_1 (PLL_C_CNT_FREQ_PS_STR_1), + .PLL_C_CNT_PHASE_PS_STR_1 (PLL_C_CNT_PHASE_PS_STR_1), + .PLL_C_CNT_DUTY_CYCLE_1 (PLL_C_CNT_DUTY_CYCLE_1), + .PLL_C_CNT_FREQ_PS_STR_2 (PLL_C_CNT_FREQ_PS_STR_2), + .PLL_C_CNT_PHASE_PS_STR_2 (PLL_C_CNT_PHASE_PS_STR_2), + .PLL_C_CNT_DUTY_CYCLE_2 (PLL_C_CNT_DUTY_CYCLE_2), + .PLL_C_CNT_FREQ_PS_STR_3 (PLL_C_CNT_FREQ_PS_STR_3), + .PLL_C_CNT_PHASE_PS_STR_3 (PLL_C_CNT_PHASE_PS_STR_3), + .PLL_C_CNT_DUTY_CYCLE_3 (PLL_C_CNT_DUTY_CYCLE_3), + .PLL_C_CNT_FREQ_PS_STR_4 (PLL_C_CNT_FREQ_PS_STR_4), + .PLL_C_CNT_PHASE_PS_STR_4 (PLL_C_CNT_PHASE_PS_STR_4), + .PLL_C_CNT_DUTY_CYCLE_4 (PLL_C_CNT_DUTY_CYCLE_4), + .PLL_C_CNT_FREQ_PS_STR_5 (PLL_C_CNT_FREQ_PS_STR_5), + .PLL_C_CNT_PHASE_PS_STR_5 (PLL_C_CNT_PHASE_PS_STR_5), + .PLL_C_CNT_DUTY_CYCLE_5 (PLL_C_CNT_DUTY_CYCLE_5), + .PLL_C_CNT_FREQ_PS_STR_6 (PLL_C_CNT_FREQ_PS_STR_6), + .PLL_C_CNT_PHASE_PS_STR_6 (PLL_C_CNT_PHASE_PS_STR_6), + .PLL_C_CNT_DUTY_CYCLE_6 (PLL_C_CNT_DUTY_CYCLE_6), + .PLL_C_CNT_FREQ_PS_STR_7 (PLL_C_CNT_FREQ_PS_STR_7), + .PLL_C_CNT_PHASE_PS_STR_7 (PLL_C_CNT_PHASE_PS_STR_7), + .PLL_C_CNT_DUTY_CYCLE_7 (PLL_C_CNT_DUTY_CYCLE_7), + .PLL_C_CNT_FREQ_PS_STR_8 (PLL_C_CNT_FREQ_PS_STR_8), + .PLL_C_CNT_PHASE_PS_STR_8 (PLL_C_CNT_PHASE_PS_STR_8), + .PLL_C_CNT_DUTY_CYCLE_8 (PLL_C_CNT_DUTY_CYCLE_8), + .PLL_C_CNT_OUT_EN_0 (PLL_C_CNT_OUT_EN_0), + .PLL_C_CNT_OUT_EN_1 (PLL_C_CNT_OUT_EN_1), + .PLL_C_CNT_OUT_EN_2 (PLL_C_CNT_OUT_EN_2), + .PLL_C_CNT_OUT_EN_3 (PLL_C_CNT_OUT_EN_3), + .PLL_C_CNT_OUT_EN_4 (PLL_C_CNT_OUT_EN_4), + .PLL_C_CNT_OUT_EN_5 (PLL_C_CNT_OUT_EN_5), + .PLL_C_CNT_OUT_EN_6 (PLL_C_CNT_OUT_EN_6), + .PLL_C_CNT_OUT_EN_7 (PLL_C_CNT_OUT_EN_7), + .PLL_C_CNT_OUT_EN_8 (PLL_C_CNT_OUT_EN_8), + .PLL_FBCLK_MUX_1 (PLL_FBCLK_MUX_1), + .PLL_FBCLK_MUX_2 (PLL_FBCLK_MUX_2), + .PLL_M_CNT_IN_SRC (PLL_M_CNT_IN_SRC), + + .PLL_C_CNT_FREQ_MHZ_STR_0 (PLL_C_CNT_FREQ_MHZ_STR_0), + .PLL_C_CNT_FREQ_MHZ_STR_1 (PLL_C_CNT_FREQ_MHZ_STR_1), + .PLL_C_CNT_FREQ_MHZ_STR_2 (PLL_C_CNT_FREQ_MHZ_STR_2), + .PLL_C_CNT_FREQ_MHZ_STR_3 (PLL_C_CNT_FREQ_MHZ_STR_3), + .PLL_C_CNT_FREQ_MHZ_STR_4 (PLL_C_CNT_FREQ_MHZ_STR_4), + .PLL_C_CNT_FREQ_MHZ_STR_5 (PLL_C_CNT_FREQ_MHZ_STR_5), + .PLL_C_CNT_FREQ_MHZ_STR_6 (PLL_C_CNT_FREQ_MHZ_STR_6), + .PLL_C_CNT_FREQ_MHZ_STR_7 (PLL_C_CNT_FREQ_MHZ_STR_7), + .PLL_C_CNT_FREQ_MHZ_STR_8 (PLL_C_CNT_FREQ_MHZ_STR_8), + + .PLL_BW_SEL (PLL_BW_SEL), + .IS_HPS (IS_HPS) + ) pll_inst ( + .* + ); + // synthesis translate_off + end + // synthesis translate_on + endgenerate + + altera_emif_arch_fm_pll_extra_clks # ( + .PLL_NUM_OF_EXTRA_CLKS (PLL_NUM_OF_EXTRA_CLKS), + .DIAG_SIM_REGTEST_MODE (DIAG_SIM_REGTEST_MODE) + ) pll_extra_clks_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // OCT Block + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_oct # ( + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT) + ) oct_inst ( + .oct_rzqin (oct_rzqin2ter), + .oct_termin (oct_termin) + ); + + //////////////////////////////////////////////////////////////////////////// + // Output clock and reset signals + //////////////////////////////////////////////////////////////////////////// + generate + if (IS_HPS) begin : hps + altera_emif_arch_fm_hps_clks_rsts # ( + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH (PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH) + ) hps_clks_rsts_inst ( + .* + ); + end else begin : non_hps + altera_emif_arch_fm_core_clks_rsts # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .PHY_CORE_CLKS_SHARING_ENUM (PHY_CORE_CLKS_SHARING_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .USER_CLK_RATIO (USER_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_USE_CPA_LOCK (DIAG_USE_CPA_LOCK), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH (PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH) + ) core_clks_rsts_inst ( + .* + ); + end + endgenerate + + //////////////////////////////////////////////////////////////////////////// + // Reset request control + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_local_reset # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .IS_HPS (IS_HPS) + ) local_reset_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // I/O Buffers + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_bufs # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PINS_PER_LANE (PINS_PER_LANE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .UNUSED_MEM_PINS_PINLOC (UNUSED_MEM_PINS_PINLOC), + .UNUSED_DQS_BUSES_LANELOC (UNUSED_DQS_BUSES_LANELOC), + + // Assignment of port widths for "mem" interface + //AUTOGEN_BEGIN: Assignment of memory port widths + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_GNT_N_WIDTH (PORT_MEM_GNT_N_WIDTH), + .PORT_MEM_REQ_N_WIDTH (PORT_MEM_REQ_N_WIDTH), + .PORT_MEM_ERR_N_WIDTH (PORT_MEM_ERR_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + + // Assignment of parameters describing logical pin allocation + //AUTOGEN_BEGIN: Assignment of memory port pinlocs + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_CK_N_PINLOC (PORT_MEM_CK_N_PINLOC), + .PORT_MEM_DK_PINLOC (PORT_MEM_DK_PINLOC), + .PORT_MEM_DK_N_PINLOC (PORT_MEM_DK_N_PINLOC), + .PORT_MEM_DKA_PINLOC (PORT_MEM_DKA_PINLOC), + .PORT_MEM_DKA_N_PINLOC (PORT_MEM_DKA_N_PINLOC), + .PORT_MEM_DKB_PINLOC (PORT_MEM_DKB_PINLOC), + .PORT_MEM_DKB_N_PINLOC (PORT_MEM_DKB_N_PINLOC), + .PORT_MEM_K_PINLOC (PORT_MEM_K_PINLOC), + .PORT_MEM_K_N_PINLOC (PORT_MEM_K_N_PINLOC), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_C_PINLOC (PORT_MEM_C_PINLOC), + .PORT_MEM_CKE_PINLOC (PORT_MEM_CKE_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_RM_PINLOC (PORT_MEM_RM_PINLOC), + .PORT_MEM_ODT_PINLOC (PORT_MEM_ODT_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_RESET_N_PINLOC (PORT_MEM_RESET_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_PAR_PINLOC (PORT_MEM_PAR_PINLOC), + .PORT_MEM_CA_PINLOC (PORT_MEM_CA_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_DOFF_N_PINLOC (PORT_MEM_DOFF_N_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_LBK0_N_PINLOC (PORT_MEM_LBK0_N_PINLOC), + .PORT_MEM_LBK1_N_PINLOC (PORT_MEM_LBK1_N_PINLOC), + .PORT_MEM_CFG_N_PINLOC (PORT_MEM_CFG_N_PINLOC), + .PORT_MEM_AP_PINLOC (PORT_MEM_AP_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_QK_N_PINLOC (PORT_MEM_QK_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKA_N_PINLOC (PORT_MEM_QKA_N_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_QKB_N_PINLOC (PORT_MEM_QKB_N_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_CQ_N_PINLOC (PORT_MEM_CQ_N_PINLOC), + .PORT_MEM_ALERT_N_PINLOC (PORT_MEM_ALERT_N_PINLOC), + .PORT_MEM_PE_N_PINLOC (PORT_MEM_PE_N_PINLOC), + + .HPRX_CTLE_EN (HPRX_CTLE_EN), + .HPRX_OFFSET_CAL (HPRX_OFFSET_CAL), + + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_AC_CALIBRATED_OCT (PHY_AC_CALIBRATED_OCT), + .PHY_CK_CALIBRATED_OCT (PHY_CK_CALIBRATED_OCT), + .PHY_DATA_CALIBRATED_OCT (PHY_DATA_CALIBRATED_OCT) + ) bufs_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Tiles and Lanes + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_io_tiles_wrap # ( + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .DIAG_SIM_VERBOSE_LEVEL (DIAG_SIM_VERBOSE_LEVEL), + .DIAG_SEQ_RESET_AUTO_RELEASE (DIAG_SEQ_RESET_AUTO_RELEASE), + .DIAG_DB_RESET_AUTO_RELEASE (DIAG_DB_RESET_AUTO_RELEASE), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_MEM_CLK_FREQ_PS (PLL_MEM_CLK_FREQ_PS), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .PHY_MIMIC_HPS_EMIF (PHY_MIMIC_HPS_EMIF), + .CPA_FB_MUX_1_SEL (CPA_FB_MUX_1_SEL), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_CS_ADDR_WIDTH (PRI_HMC_CFG_CS_ADDR_WIDTH), + .PRI_HMC_CFG_COL_ADDR_WIDTH (PRI_HMC_CFG_COL_ADDR_WIDTH), + .PRI_HMC_CFG_ROW_ADDR_WIDTH (PRI_HMC_CFG_ROW_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_ADDR_WIDTH (PRI_HMC_CFG_BANK_ADDR_WIDTH), + .PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH (PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_CTRL_ENABLE_RC (PRI_HMC_CFG_CTRL_ENABLE_RC), + .PRI_HMC_CFG_DBC0_ENABLE_RC (PRI_HMC_CFG_DBC0_ENABLE_RC), + .PRI_HMC_CFG_DBC1_ENABLE_RC (PRI_HMC_CFG_DBC1_ENABLE_RC), + .PRI_HMC_CFG_DBC2_ENABLE_RC (PRI_HMC_CFG_DBC2_ENABLE_RC), + .PRI_HMC_CFG_DBC3_ENABLE_RC (PRI_HMC_CFG_DBC3_ENABLE_RC), + .PRI_HMC_CFG_CTRL_ENABLE_ECC (PRI_HMC_CFG_CTRL_ENABLE_ECC), + .PRI_HMC_CFG_DBC0_ENABLE_ECC (PRI_HMC_CFG_DBC0_ENABLE_ECC), + .PRI_HMC_CFG_DBC1_ENABLE_ECC (PRI_HMC_CFG_DBC1_ENABLE_ECC), + .PRI_HMC_CFG_DBC2_ENABLE_ECC (PRI_HMC_CFG_DBC2_ENABLE_ECC), + .PRI_HMC_CFG_DBC3_ENABLE_ECC (PRI_HMC_CFG_DBC3_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_CTRL_REORDER_RDATA (PRI_HMC_CFG_CTRL_REORDER_RDATA), + .PRI_HMC_CFG_DBC0_REORDER_RDATA (PRI_HMC_CFG_DBC0_REORDER_RDATA), + .PRI_HMC_CFG_DBC1_REORDER_RDATA (PRI_HMC_CFG_DBC1_REORDER_RDATA), + .PRI_HMC_CFG_DBC2_REORDER_RDATA (PRI_HMC_CFG_DBC2_REORDER_RDATA), + .PRI_HMC_CFG_DBC3_REORDER_RDATA (PRI_HMC_CFG_DBC3_REORDER_RDATA), + .PRI_HMC_CFG_CTRL_SLOT_OFFSET (PRI_HMC_CFG_CTRL_SLOT_OFFSET), + .PRI_HMC_CFG_DBC0_SLOT_OFFSET (PRI_HMC_CFG_DBC0_SLOT_OFFSET), + .PRI_HMC_CFG_DBC1_SLOT_OFFSET (PRI_HMC_CFG_DBC1_SLOT_OFFSET), + .PRI_HMC_CFG_DBC2_SLOT_OFFSET (PRI_HMC_CFG_DBC2_SLOT_OFFSET), + .PRI_HMC_CFG_DBC3_SLOT_OFFSET (PRI_HMC_CFG_DBC3_SLOT_OFFSET), + .PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN (PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN (PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ROW_TO_COL_OFFSET (PRI_HMC_CFG_ROW_TO_COL_OFFSET), + .PRI_HMC_CFG_ROW_TO_ROW_OFFSET (PRI_HMC_CFG_ROW_TO_ROW_OFFSET), + .PRI_HMC_CFG_COL_TO_COL_OFFSET (PRI_HMC_CFG_COL_TO_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET (PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .PRI_HMC_CFG_COL_TO_ROW_OFFSET (PRI_HMC_CFG_COL_TO_ROW_OFFSET), + .PRI_HMC_CFG_SIDEBAND_OFFSET (PRI_HMC_CFG_SIDEBAND_OFFSET), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_CTL_ODT_ENABLED (PRI_HMC_CFG_CTL_ODT_ENABLED), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_CMD_FIFO_RESERVE_EN (PRI_HMC_CFG_CMD_FIFO_RESERVE_EN), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_PHY_DELAY_MISMATCH (PRI_HMC_CFG_PHY_DELAY_MISMATCH), + .PRI_HMC_CFG_DQSTRK_EN (PRI_HMC_CFG_DQSTRK_EN), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN (PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD (PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_MEM_AUTO_PD_CYCLES (PRI_HMC_CFG_MEM_AUTO_PD_CYCLES), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_MEMCLKGATE_SETTING (PRI_HMC_MEMCLKGATE_SETTING), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_MEM_IF_AL (PRI_HMC_MEM_IF_AL), + .PRI_HMC_MEM_IF_CS_PER_DIMM (PRI_HMC_MEM_IF_CS_PER_DIMM), + .PRI_HMC_MEM_IF_RD_PREAMBLE (PRI_HMC_MEM_IF_RD_PREAMBLE), + .PRI_HMC_MEM_IF_TCCD (PRI_HMC_MEM_IF_TCCD), + .PRI_HMC_MEM_IF_TCCD_S (PRI_HMC_MEM_IF_TCCD_S), + .PRI_HMC_MEM_IF_TCKESR (PRI_HMC_MEM_IF_TCKESR), + .PRI_HMC_MEM_IF_TCKSRX (PRI_HMC_MEM_IF_TCKSRX), + .PRI_HMC_MEM_IF_TCL (PRI_HMC_MEM_IF_TCL), + .PRI_HMC_MEM_IF_TCWL (PRI_HMC_MEM_IF_TCWL), + .PRI_HMC_MEM_IF_TDQSCKMAX (PRI_HMC_MEM_IF_TDQSCKMAX), + .PRI_HMC_MEM_IF_TFAW (PRI_HMC_MEM_IF_TFAW), + .PRI_HMC_MEM_IF_TMOD (PRI_HMC_MEM_IF_TMOD), + .PRI_HMC_MEM_IF_TPL (PRI_HMC_MEM_IF_TPL), + .PRI_HMC_MEM_IF_TRAS (PRI_HMC_MEM_IF_TRAS), + .PRI_HMC_MEM_IF_TRC (PRI_HMC_MEM_IF_TRC), + .PRI_HMC_MEM_IF_TRCD (PRI_HMC_MEM_IF_TRCD), + .PRI_HMC_MEM_IF_TREFI (PRI_HMC_MEM_IF_TREFI), + .PRI_HMC_MEM_IF_TRFC (PRI_HMC_MEM_IF_TRFC), + .PRI_HMC_MEM_IF_TRP (PRI_HMC_MEM_IF_TRP), + .PRI_HMC_MEM_IF_TRRD (PRI_HMC_MEM_IF_TRRD), + .PRI_HMC_MEM_IF_TRRD_S (PRI_HMC_MEM_IF_TRRD_S), + .PRI_HMC_MEM_IF_TRTP (PRI_HMC_MEM_IF_TRTP), + .PRI_HMC_MEM_IF_TWR (PRI_HMC_MEM_IF_TWR), + .PRI_HMC_MEM_IF_TWR_CRC_DM (PRI_HMC_MEM_IF_TWR_CRC_DM), + .PRI_HMC_MEM_IF_TWTR (PRI_HMC_MEM_IF_TWTR), + .PRI_HMC_MEM_IF_TWTR_L_CRC_DM (PRI_HMC_MEM_IF_TWTR_L_CRC_DM), + .PRI_HMC_MEM_IF_TWTR_S (PRI_HMC_MEM_IF_TWTR_S), + .PRI_HMC_MEM_IF_TWTR_S_CRC_DM (PRI_HMC_MEM_IF_TWTR_S_CRC_DM), + .PRI_HMC_MEM_IF_TXP (PRI_HMC_MEM_IF_TXP), + .PRI_HMC_MEM_IF_TXPDLL (PRI_HMC_MEM_IF_TXPDLL), + .PRI_HMC_MEM_IF_TXSR (PRI_HMC_MEM_IF_TXSR), + .PRI_HMC_MEM_IF_TZQCS (PRI_HMC_MEM_IF_TZQCS), + .PRI_HMC_MEM_IF_TZQOPER (PRI_HMC_MEM_IF_TZQOPER), + .PRI_HMC_MEM_IF_WR_CRC (PRI_HMC_MEM_IF_WR_CRC), + .PRI_HMC_MEM_IF_WR_PREAMBLE (PRI_HMC_MEM_IF_WR_PREAMBLE), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR (PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_TEMP_4_ACT_TO_ACT (PRI_HMC_TEMP_4_ACT_TO_ACT), + .PRI_HMC_TEMP_RD_TO_RD_DIFF_BG (PRI_HMC_TEMP_RD_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD (PRI_HMC_TEMP_WR_TO_RD), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_BG (PRI_HMC_TEMP_WR_TO_RD_DIFF_BG), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP (PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_TEMP_WR_TO_WR_DIFF_BG (PRI_HMC_TEMP_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MAJOR_MODE_EN (PRI_HMC_CFG_MAJOR_MODE_EN), + .PRI_HMC_CFG_REFRESH_TYPE (PRI_HMC_CFG_REFRESH_TYPE), + .PRI_HMC_CFG_POST_REFRESH_EN (PRI_HMC_CFG_POST_REFRESH_EN), + .PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT (PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT), + .PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT (PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT), + .PRI_HMC_CFG_PRE_REFRESH_EN (PRI_HMC_CFG_PRE_REFRESH_EN), + .PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT), + .PRI_HMC_CHIP_ID (PRI_HMC_CHIP_ID), + .PRI_HMC_CID_ADDR_WIDTH (PRI_HMC_CID_ADDR_WIDTH), + .PRI_HMC_3DS_EN (PRI_HMC_3DS_EN), + .PRI_HMC_3DS_LR_NUM0 (PRI_HMC_3DS_LR_NUM0), + .PRI_HMC_3DS_LR_NUM1 (PRI_HMC_3DS_LR_NUM1), + .PRI_HMC_3DS_LR_NUM2 (PRI_HMC_3DS_LR_NUM2), + .PRI_HMC_3DS_LR_NUM3 (PRI_HMC_3DS_LR_NUM3), + .PRI_HMC_3DS_PR_STAG_ENABLE (PRI_HMC_3DS_PR_STAG_ENABLE), + .PRI_HMC_3DS_REF2REF_DLR (PRI_HMC_3DS_REF2REF_DLR), + .PRI_HMC_3DSREF_ACK_ON_DONE (PRI_HMC_3DSREF_ACK_ON_DONE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_CS_ADDR_WIDTH (SEC_HMC_CFG_CS_ADDR_WIDTH), + .SEC_HMC_CFG_COL_ADDR_WIDTH (SEC_HMC_CFG_COL_ADDR_WIDTH), + .SEC_HMC_CFG_ROW_ADDR_WIDTH (SEC_HMC_CFG_ROW_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_ADDR_WIDTH (SEC_HMC_CFG_BANK_ADDR_WIDTH), + .SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH (SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_CTRL_ENABLE_RC (SEC_HMC_CFG_CTRL_ENABLE_RC), + .SEC_HMC_CFG_DBC0_ENABLE_RC (SEC_HMC_CFG_DBC0_ENABLE_RC), + .SEC_HMC_CFG_DBC1_ENABLE_RC (SEC_HMC_CFG_DBC1_ENABLE_RC), + .SEC_HMC_CFG_DBC2_ENABLE_RC (SEC_HMC_CFG_DBC2_ENABLE_RC), + .SEC_HMC_CFG_DBC3_ENABLE_RC (SEC_HMC_CFG_DBC3_ENABLE_RC), + .SEC_HMC_CFG_CTRL_ENABLE_ECC (SEC_HMC_CFG_CTRL_ENABLE_ECC), + .SEC_HMC_CFG_DBC0_ENABLE_ECC (SEC_HMC_CFG_DBC0_ENABLE_ECC), + .SEC_HMC_CFG_DBC1_ENABLE_ECC (SEC_HMC_CFG_DBC1_ENABLE_ECC), + .SEC_HMC_CFG_DBC2_ENABLE_ECC (SEC_HMC_CFG_DBC2_ENABLE_ECC), + .SEC_HMC_CFG_DBC3_ENABLE_ECC (SEC_HMC_CFG_DBC3_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_CTRL_REORDER_RDATA (SEC_HMC_CFG_CTRL_REORDER_RDATA), + .SEC_HMC_CFG_DBC0_REORDER_RDATA (SEC_HMC_CFG_DBC0_REORDER_RDATA), + .SEC_HMC_CFG_DBC1_REORDER_RDATA (SEC_HMC_CFG_DBC1_REORDER_RDATA), + .SEC_HMC_CFG_DBC2_REORDER_RDATA (SEC_HMC_CFG_DBC2_REORDER_RDATA), + .SEC_HMC_CFG_DBC3_REORDER_RDATA (SEC_HMC_CFG_DBC3_REORDER_RDATA), + .SEC_HMC_CFG_CTRL_SLOT_OFFSET (SEC_HMC_CFG_CTRL_SLOT_OFFSET), + .SEC_HMC_CFG_DBC0_SLOT_OFFSET (SEC_HMC_CFG_DBC0_SLOT_OFFSET), + .SEC_HMC_CFG_DBC1_SLOT_OFFSET (SEC_HMC_CFG_DBC1_SLOT_OFFSET), + .SEC_HMC_CFG_DBC2_SLOT_OFFSET (SEC_HMC_CFG_DBC2_SLOT_OFFSET), + .SEC_HMC_CFG_DBC3_SLOT_OFFSET (SEC_HMC_CFG_DBC3_SLOT_OFFSET), + .SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN (SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN), + .SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN (SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ROW_TO_COL_OFFSET (SEC_HMC_CFG_ROW_TO_COL_OFFSET), + .SEC_HMC_CFG_ROW_TO_ROW_OFFSET (SEC_HMC_CFG_ROW_TO_ROW_OFFSET), + .SEC_HMC_CFG_COL_TO_COL_OFFSET (SEC_HMC_CFG_COL_TO_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET (SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET), + .SEC_HMC_CFG_COL_TO_ROW_OFFSET (SEC_HMC_CFG_COL_TO_ROW_OFFSET), + .SEC_HMC_CFG_SIDEBAND_OFFSET (SEC_HMC_CFG_SIDEBAND_OFFSET), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_CTL_ODT_ENABLED (SEC_HMC_CFG_CTL_ODT_ENABLED), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_CMD_FIFO_RESERVE_EN (SEC_HMC_CFG_CMD_FIFO_RESERVE_EN), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_PHY_DELAY_MISMATCH (SEC_HMC_CFG_PHY_DELAY_MISMATCH), + .SEC_HMC_CFG_DQSTRK_EN (SEC_HMC_CFG_DQSTRK_EN), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN (SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD (SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_MEM_AUTO_PD_CYCLES (SEC_HMC_CFG_MEM_AUTO_PD_CYCLES), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_MEMCLKGATE_SETTING (SEC_HMC_MEMCLKGATE_SETTING), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_MEM_IF_AL (SEC_HMC_MEM_IF_AL), + .SEC_HMC_MEM_IF_CS_PER_DIMM (SEC_HMC_MEM_IF_CS_PER_DIMM), + .SEC_HMC_MEM_IF_RD_PREAMBLE (SEC_HMC_MEM_IF_RD_PREAMBLE), + .SEC_HMC_MEM_IF_TCCD (SEC_HMC_MEM_IF_TCCD), + .SEC_HMC_MEM_IF_TCCD_S (SEC_HMC_MEM_IF_TCCD_S), + .SEC_HMC_MEM_IF_TCKESR (SEC_HMC_MEM_IF_TCKESR), + .SEC_HMC_MEM_IF_TCKSRX (SEC_HMC_MEM_IF_TCKSRX), + .SEC_HMC_MEM_IF_TCL (SEC_HMC_MEM_IF_TCL), + .SEC_HMC_MEM_IF_TCWL (SEC_HMC_MEM_IF_TCWL), + .SEC_HMC_MEM_IF_TDQSCKMAX (SEC_HMC_MEM_IF_TDQSCKMAX), + .SEC_HMC_MEM_IF_TFAW (SEC_HMC_MEM_IF_TFAW), + .SEC_HMC_MEM_IF_TMOD (SEC_HMC_MEM_IF_TMOD), + .SEC_HMC_MEM_IF_TPL (SEC_HMC_MEM_IF_TPL), + .SEC_HMC_MEM_IF_TRAS (SEC_HMC_MEM_IF_TRAS), + .SEC_HMC_MEM_IF_TRC (SEC_HMC_MEM_IF_TRC), + .SEC_HMC_MEM_IF_TRCD (SEC_HMC_MEM_IF_TRCD), + .SEC_HMC_MEM_IF_TREFI (SEC_HMC_MEM_IF_TREFI), + .SEC_HMC_MEM_IF_TRFC (SEC_HMC_MEM_IF_TRFC), + .SEC_HMC_MEM_IF_TRP (SEC_HMC_MEM_IF_TRP), + .SEC_HMC_MEM_IF_TRRD (SEC_HMC_MEM_IF_TRRD), + .SEC_HMC_MEM_IF_TRRD_S (SEC_HMC_MEM_IF_TRRD_S), + .SEC_HMC_MEM_IF_TRTP (SEC_HMC_MEM_IF_TRTP), + .SEC_HMC_MEM_IF_TWR (SEC_HMC_MEM_IF_TWR), + .SEC_HMC_MEM_IF_TWR_CRC_DM (SEC_HMC_MEM_IF_TWR_CRC_DM), + .SEC_HMC_MEM_IF_TWTR (SEC_HMC_MEM_IF_TWTR), + .SEC_HMC_MEM_IF_TWTR_L_CRC_DM (SEC_HMC_MEM_IF_TWTR_L_CRC_DM), + .SEC_HMC_MEM_IF_TWTR_S (SEC_HMC_MEM_IF_TWTR_S), + .SEC_HMC_MEM_IF_TWTR_S_CRC_DM (SEC_HMC_MEM_IF_TWTR_S_CRC_DM), + .SEC_HMC_MEM_IF_TXP (SEC_HMC_MEM_IF_TXP), + .SEC_HMC_MEM_IF_TXPDLL (SEC_HMC_MEM_IF_TXPDLL), + .SEC_HMC_MEM_IF_TXSR (SEC_HMC_MEM_IF_TXSR), + .SEC_HMC_MEM_IF_TZQCS (SEC_HMC_MEM_IF_TZQCS), + .SEC_HMC_MEM_IF_TZQOPER (SEC_HMC_MEM_IF_TZQOPER), + .SEC_HMC_MEM_IF_WR_CRC (SEC_HMC_MEM_IF_WR_CRC), + .SEC_HMC_MEM_IF_WR_PREAMBLE (SEC_HMC_MEM_IF_WR_PREAMBLE), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR (SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_TEMP_4_ACT_TO_ACT (SEC_HMC_TEMP_4_ACT_TO_ACT), + .SEC_HMC_TEMP_RD_TO_RD_DIFF_BG (SEC_HMC_TEMP_RD_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD (SEC_HMC_TEMP_WR_TO_RD), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_BG (SEC_HMC_TEMP_WR_TO_RD_DIFF_BG), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP (SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_TEMP_WR_TO_WR_DIFF_BG (SEC_HMC_TEMP_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MAJOR_MODE_EN (SEC_HMC_CFG_MAJOR_MODE_EN), + .SEC_HMC_CFG_REFRESH_TYPE (SEC_HMC_CFG_REFRESH_TYPE), + .SEC_HMC_CFG_POST_REFRESH_EN (SEC_HMC_CFG_POST_REFRESH_EN), + .SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT (SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT), + .SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT (SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT), + .SEC_HMC_CFG_PRE_REFRESH_EN (SEC_HMC_CFG_PRE_REFRESH_EN), + .SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT), + .SEC_HMC_CHIP_ID (SEC_HMC_CHIP_ID), + .SEC_HMC_CID_ADDR_WIDTH (SEC_HMC_CID_ADDR_WIDTH), + .SEC_HMC_3DS_EN (SEC_HMC_3DS_EN), + .SEC_HMC_3DS_LR_NUM0 (SEC_HMC_3DS_LR_NUM0), + .SEC_HMC_3DS_LR_NUM1 (SEC_HMC_3DS_LR_NUM1), + .SEC_HMC_3DS_LR_NUM2 (SEC_HMC_3DS_LR_NUM2), + .SEC_HMC_3DS_LR_NUM3 (SEC_HMC_3DS_LR_NUM3), + .SEC_HMC_3DS_PR_STAG_ENABLE (SEC_HMC_3DS_PR_STAG_ENABLE), + .SEC_HMC_3DS_REF2REF_DLR (SEC_HMC_3DS_REF2REF_DLR), + .SEC_HMC_3DSREF_ACK_ON_DONE (SEC_HMC_3DSREF_ACK_ON_DONE), + .SEQ_PT_CONTENT (SEQ_PT_CONTENT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .PINS_USAGE (PINS_USAGE), + .LANE_PIN_USAGE (LANE_PIN_USAGE), + .PINS_RATE (PINS_RATE), + .DB_PINS_PROC_MODE (DB_PINS_PROC_MODE), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_DCC_SPLIT (PINS_DCC_SPLIT), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .DBC_EXTRA_PIPE_STAGE_EN (DBC_EXTRA_PIPE_STAGE_EN), + .DBC_PIPE_LATS (DBC_PIPE_LATS), + .DB_PTR_PIPELINE_DEPTHS (DB_PTR_PIPELINE_DEPTHS), + .DB_SEQ_RD_EN_FULL_PIPELINES (DB_SEQ_RD_EN_FULL_PIPELINES), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DQSA_LGC_MODE (DQSA_LGC_MODE), + .DQSB_LGC_MODE (DQSB_LGC_MODE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH (PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH), + + .PORT_CALBUS_ADDRESS_WIDTH (PORT_CALBUS_ADDRESS_WIDTH), + .PORT_CALBUS_RDATA_WIDTH (PORT_CALBUS_RDATA_WIDTH), + .PORT_CALBUS_WDATA_WIDTH (PORT_CALBUS_WDATA_WIDTH), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (PORT_CALBUS_SEQ_PARAM_TBL_WIDTH), + + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL) + ) io_tiles_wrap_inst ( + .runAbstractPhySim (runAbstractPhySim), + .core2l_data (actual_core2l_data), + .core2l_oe (actual_core2l_oe), + .core2l_rdata_en_full (actual_core2l_rdata_en_full), + .core2l_mrnk_read (actual_core2l_mrnk_read), + .core2l_mrnk_write (actual_core2l_mrnk_write), + + .core2l_wr_ecc_info (actual_core2l_wr_ecc_info), + .core2l_wr_data_vld_ast (actual_core2l_wr_data_vld_ast), + .core2l_rd_data_rdy_ast (actual_core2l_rd_data_rdy_ast), + + .core2ctl_avl_0 (actual_core2ctl_avl_0 ), + .core2ctl_avl_rd_data_ready_0 (actual_core2ctl_avl_rd_data_ready_0 ), + .core2ctl_avl_1 (actual_core2ctl_avl_1 ), + .core2ctl_avl_rd_data_ready_1 (actual_core2ctl_avl_rd_data_ready_1 ), + .core2ctl_mmr_0 (actual_core2ctl_mmr_0 ), + .core2ctl_mmr_1 (actual_core2ctl_mmr_1 ), + .core2ctl_sideband_0 (actual_core2ctl_sideband_0 ), + .core2ctl_sideband_1 (actual_core2ctl_sideband_1 ), + + .c2t_afi (actual_c2t_afi), + + // Avalon-MM bus for the calibration commands between io_aux and tiles + .cal_bus_clk (calbus_clk), + .cal_bus_avl_read (calbus_read), + .cal_bus_avl_write (calbus_write), + .cal_bus_avl_address (calbus_address), + .cal_bus_avl_read_data (calbus_rdata), + .cal_bus_avl_write_data (calbus_wdata), + .cal_bus_seq_param_tbl (calbus_seq_param_tbl), + .* + ); + + assign ufi_phy_clk = (PRI_HMC_CFG_CTRL_ENABLE_RC == "enable") ? global_phy_clk[1] : global_phy_clk[0]; + assign ufi_core_clk = (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") ? emif_usr_clk : afi_clk; + + altera_emif_arch_fm_ufis #( + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_PER_LANE (PINS_PER_LANE), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + + .AMM_C2P_UFI_MODE (AMM_C2P_UFI_MODE), + .AMM_P2C_UFI_MODE (AMM_P2C_UFI_MODE), + .MMR_C2P_UFI_MODE (MMR_C2P_UFI_MODE), + .MMR_P2C_UFI_MODE (MMR_P2C_UFI_MODE), + .SIDEBAND_C2P_UFI_MODE (SIDEBAND_C2P_UFI_MODE), + .SIDEBAND_P2C_UFI_MODE (SIDEBAND_P2C_UFI_MODE), + .SEQ_C2P_UFI_MODE (SEQ_C2P_UFI_MODE), + .SEQ_P2C_UFI_MODE (SEQ_P2C_UFI_MODE), + .ECC_C2P_UFI_MODE (ECC_C2P_UFI_MODE), + .ECC_P2C_UFI_MODE (ECC_P2C_UFI_MODE), + .LANE_C2P_UFI_MODE (LANE_C2P_UFI_MODE), + .LANE_P2C_UFI_MODE (LANE_P2C_UFI_MODE), + .LANE_PIN_USAGE (LANE_PIN_USAGE), + .LANES_USAGE (LANES_USAGE), + .DB_PINS_PROC_MODE (DB_PINS_PROC_MODE), + + .AMM_HIPI_DELAY (AMM_HIPI_DELAY), + .MMR_HIPI_DELAY (MMR_HIPI_DELAY), + .SIDEBAND_HIPI_DELAY (SIDEBAND_HIPI_DELAY), + .SEQ_HIPI_DELAY (SEQ_HIPI_DELAY), + .ECC_HIPI_DELAY (ECC_HIPI_DELAY), + .LANE_HIPI_DELAY (LANE_HIPI_DELAY), + + .ENABLE_RD_TYPE (ENABLE_RD_TYPE), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .IS_HPS (IS_HPS), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX) + ) fm_ufis ( + .ufi_phy_clk (ufi_phy_clk), + .ufi_core_clk (ufi_core_clk), + + .i_core2ctl_avl_0 (core2ctl_avl_0 ), + .i_core2ctl_avl_1 (core2ctl_avl_1 ), + .i_core2ctl_avl_rd_data_ready_0 (core2ctl_avl_rd_data_ready_0 ), + .i_core2ctl_avl_rd_data_ready_1 (core2ctl_avl_rd_data_ready_1 ), + + .i_ctl2core_avl_cmd_ready_0 (ctl2core_avl_cmd_ready_0 ), + .i_ctl2core_avl_cmd_ready_1 (ctl2core_avl_cmd_ready_1 ), + .i_ctl2core_avl_rdata_id_0 (ctl2core_avl_rdata_id_0 ), + .i_ctl2core_avl_rdata_id_1 (ctl2core_avl_rdata_id_1 ), + + .i_core2l_wr_data_vld_ast (core2l_wr_data_vld_ast ), + .i_core2l_rd_data_rdy_ast (core2l_rd_data_rdy_ast ), + .i_core2l_wr_ecc_info (core2l_wr_ecc_info ), + .i_l2core_wb_pointer_for_ecc (l2core_wb_pointer_for_ecc ), + + .i_l2core_rd_type (l2core_rd_type ), + .i_l2core_rd_data_vld_avl (l2core_rd_data_vld_avl ), + .i_l2core_wr_data_rdy_ast (l2core_wr_data_rdy_ast ), + + .i_c2t_afi (c2t_afi ), + .i_t2c_afi (t2c_afi ), + .i_ctl2core_mmr_0 (ctl2core_mmr_0 ), + .i_core2ctl_mmr_0 (core2ctl_mmr_0 ), + .i_ctl2core_mmr_1 (ctl2core_mmr_1 ), + .i_core2ctl_mmr_1 (core2ctl_mmr_1 ), + .i_core2ctl_sideband_0 (core2ctl_sideband_0 ), + .i_ctl2core_sideband_0 (ctl2core_sideband_0 ), + .i_core2ctl_sideband_1 (core2ctl_sideband_1 ), + .i_ctl2core_sideband_1 (ctl2core_sideband_1 ), + + + .i_core2l_data (core2l_data ), + .i_l2core_data (l2core_data ), + .i_core2l_oe (core2l_oe ), + .i_core2l_rdata_en_full (core2l_rdata_en_full ), + .i_core2l_mrnk_read (core2l_mrnk_read ), + .i_core2l_mrnk_write (core2l_mrnk_write ), + .i_l2core_rdata_valid_pri (l2core_rdata_valid_pri ), + .i_l2core_rdata_valid_sec (l2core_rdata_valid_sec ), + + // actual_* buses are UFI outputs or bypass ports + .* + ); + + + //////////////////////////////////////////////////////////////////////////// + // Expose sequencer interface + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_seq_if # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .REGISTER_AFI_C2P (REGISTER_AFI_C2P), + .REGISTER_AFI_P2C (REGISTER_AFI_P2C), + .PORT_AFI_RLAT_WIDTH (PORT_AFI_RLAT_WIDTH), + .PORT_AFI_WLAT_WIDTH (PORT_AFI_WLAT_WIDTH), + .PORT_AFI_SEQ_BUSY_WIDTH (PORT_AFI_SEQ_BUSY_WIDTH), + .PORT_HPS_EMIF_E2H_GP_WIDTH (PORT_HPS_EMIF_E2H_GP_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .IS_HPS (IS_HPS) + ) seq_if_inst ( + + .t2c_afi(actual_t2c_afi), + .* + ); + + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC signals from io_tiles as proper Avalon signals + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_hmc_avl_if # ( + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_READY_LATENCY (HMC_READY_LATENCY), + .REGISTER_AMM_C2P (REGISTER_AMM_C2P), + .REGISTER_AMM_P2C (REGISTER_AMM_P2C), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PORT_CTRL_AST_CMD_DATA_WIDTH (PORT_CTRL_AST_CMD_DATA_WIDTH), + .PORT_CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .PORT_CTRL_AMM_BCOUNT_WIDTH (PORT_CTRL_AMM_BCOUNT_WIDTH) + ) hmc_avl_if_inst ( + .ctl2core_avl_cmd_ready_0 ( actual_ctl2core_avl_cmd_ready_0 ), + .ctl2core_avl_cmd_ready_1 ( actual_ctl2core_avl_cmd_ready_1 ), + .l2core_rd_data_vld_avl ( actual_l2core_rd_data_vld_avl ), + .l2core_wr_data_rdy_ast ( actual_l2core_wr_data_rdy_ast ), + .l2core_rd_type ( actual_l2core_rd_type ), + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC sideband interfaces + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_hmc_sideband_if # ( + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_CTRL_ENABLE_ECC), + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_CTRL_ENABLE_ECC), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (PORT_CTRL_USER_REFRESH_REQ_WIDTH), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (PORT_CTRL_USER_REFRESH_BANK_WIDTH), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (PORT_CTRL_SELF_REFRESH_REQ_WIDTH), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (PORT_CTRL_ECC_WRITE_INFO_WIDTH), + .PORT_CTRL_ECC_READ_INFO_WIDTH (PORT_CTRL_ECC_READ_INFO_WIDTH), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (PORT_CTRL_ECC_CMD_INFO_WIDTH), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (PORT_CTRL_ECC_WB_POINTER_WIDTH), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (PORT_CTRL_ECC_RDATA_ID_WIDTH) + ) hmc_sideband_if_inst ( + .ctl2core_sideband_0 (actual_ctl2core_sideband_0 ), + .ctl2core_sideband_1 (actual_ctl2core_sideband_1 ), + .l2core_wb_pointer_for_ecc (actual_l2core_wb_pointer_for_ecc), + .ctl2core_avl_rdata_id_0 (actual_ctl2core_avl_rdata_id_0), + .ctl2core_avl_rdata_id_1 (actual_ctl2core_avl_rdata_id_1), + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC MMR interface + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_fm_hmc_mmr_if # ( + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (PORT_CTRL_MMR_SLAVE_RDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (PORT_CTRL_MMR_SLAVE_WDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH) + ) hmc_mmr_if_inst ( + .ctl2core_mmr_0 (actual_ctl2core_mmr_0), + .ctl2core_mmr_1 (actual_ctl2core_mmr_1), + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Rewire and expose data signals + //////////////////////////////////////////////////////////////////////////// + generate + if (NUM_OF_HMC_PORTS == 0) + begin : afi + altera_emif_arch_fm_afi_if # ( + .MEM_TTL_DATA_WIDTH (MEM_TTL_DATA_WIDTH), + .MEM_TTL_NUM_OF_READ_GROUPS (MEM_TTL_NUM_OF_READ_GROUPS), + .MEM_TTL_NUM_OF_WRITE_GROUPS (MEM_TTL_NUM_OF_WRITE_GROUPS), + .REGISTER_AFI_C2P (REGISTER_AFI_C2P), + .REGISTER_AFI_P2C (REGISTER_AFI_P2C), + + .PORT_AFI_ADDR_WIDTH (PORT_AFI_ADDR_WIDTH), + .PORT_AFI_BA_WIDTH (PORT_AFI_BA_WIDTH), + .PORT_AFI_BG_WIDTH (PORT_AFI_BG_WIDTH), + .PORT_AFI_C_WIDTH (PORT_AFI_C_WIDTH), + .PORT_AFI_CKE_WIDTH (PORT_AFI_CKE_WIDTH), + .PORT_AFI_CS_N_WIDTH (PORT_AFI_CS_N_WIDTH), + .PORT_AFI_RM_WIDTH (PORT_AFI_RM_WIDTH), + .PORT_AFI_ODT_WIDTH (PORT_AFI_ODT_WIDTH), + .PORT_AFI_GNT_N_WIDTH (PORT_AFI_GNT_N_WIDTH), + .PORT_AFI_REQ_N_WIDTH (PORT_AFI_REQ_N_WIDTH), + .PORT_AFI_ERR_N_WIDTH (PORT_AFI_ERR_N_WIDTH), + .PORT_AFI_RAS_N_WIDTH (PORT_AFI_RAS_N_WIDTH), + .PORT_AFI_CAS_N_WIDTH (PORT_AFI_CAS_N_WIDTH), + .PORT_AFI_WE_N_WIDTH (PORT_AFI_WE_N_WIDTH), + .PORT_AFI_RST_N_WIDTH (PORT_AFI_RST_N_WIDTH), + .PORT_AFI_ACT_N_WIDTH (PORT_AFI_ACT_N_WIDTH), + .PORT_AFI_PAR_WIDTH (PORT_AFI_PAR_WIDTH), + .PORT_AFI_CA_WIDTH (PORT_AFI_CA_WIDTH), + .PORT_AFI_REF_N_WIDTH (PORT_AFI_REF_N_WIDTH), + .PORT_AFI_WPS_N_WIDTH (PORT_AFI_WPS_N_WIDTH), + .PORT_AFI_RPS_N_WIDTH (PORT_AFI_RPS_N_WIDTH), + .PORT_AFI_DOFF_N_WIDTH (PORT_AFI_DOFF_N_WIDTH), + .PORT_AFI_LD_N_WIDTH (PORT_AFI_LD_N_WIDTH), + .PORT_AFI_RW_N_WIDTH (PORT_AFI_RW_N_WIDTH), + .PORT_AFI_LBK0_N_WIDTH (PORT_AFI_LBK0_N_WIDTH), + .PORT_AFI_LBK1_N_WIDTH (PORT_AFI_LBK1_N_WIDTH), + .PORT_AFI_CFG_N_WIDTH (PORT_AFI_CFG_N_WIDTH), + .PORT_AFI_AP_WIDTH (PORT_AFI_AP_WIDTH), + .PORT_AFI_AINV_WIDTH (PORT_AFI_AINV_WIDTH), + .PORT_AFI_DM_WIDTH (PORT_AFI_DM_WIDTH), + .PORT_AFI_DM_N_WIDTH (PORT_AFI_DM_N_WIDTH), + .PORT_AFI_BWS_N_WIDTH (PORT_AFI_BWS_N_WIDTH), + .PORT_AFI_RDATA_DBI_N_WIDTH (PORT_AFI_RDATA_DBI_N_WIDTH), + .PORT_AFI_WDATA_DBI_N_WIDTH (PORT_AFI_WDATA_DBI_N_WIDTH), + .PORT_AFI_RDATA_DINV_WIDTH (PORT_AFI_RDATA_DINV_WIDTH), + .PORT_AFI_WDATA_DINV_WIDTH (PORT_AFI_WDATA_DINV_WIDTH), + .PORT_AFI_DQS_BURST_WIDTH (PORT_AFI_DQS_BURST_WIDTH), + .PORT_AFI_WDATA_VALID_WIDTH (PORT_AFI_WDATA_VALID_WIDTH), + .PORT_AFI_WDATA_WIDTH (PORT_AFI_WDATA_WIDTH), + .PORT_AFI_RDATA_EN_FULL_WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH), + .PORT_AFI_RDATA_WIDTH (PORT_AFI_RDATA_WIDTH), + .PORT_AFI_RDATA_VALID_WIDTH (PORT_AFI_RDATA_VALID_WIDTH), + .PORT_AFI_RRANK_WIDTH (PORT_AFI_RRANK_WIDTH), + .PORT_AFI_WRANK_WIDTH (PORT_AFI_WRANK_WIDTH), + .PORT_AFI_ALERT_N_WIDTH (PORT_AFI_ALERT_N_WIDTH), + .PORT_AFI_PE_N_WIDTH (PORT_AFI_PE_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_GNT_N_WIDTH (PORT_MEM_GNT_N_WIDTH), + .PORT_MEM_REQ_N_WIDTH (PORT_MEM_REQ_N_WIDTH), + .PORT_MEM_ERR_N_WIDTH (PORT_MEM_ERR_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_CK_N_PINLOC (PORT_MEM_CK_N_PINLOC), + .PORT_MEM_DK_PINLOC (PORT_MEM_DK_PINLOC), + .PORT_MEM_DK_N_PINLOC (PORT_MEM_DK_N_PINLOC), + .PORT_MEM_DKA_PINLOC (PORT_MEM_DKA_PINLOC), + .PORT_MEM_DKA_N_PINLOC (PORT_MEM_DKA_N_PINLOC), + .PORT_MEM_DKB_PINLOC (PORT_MEM_DKB_PINLOC), + .PORT_MEM_DKB_N_PINLOC (PORT_MEM_DKB_N_PINLOC), + .PORT_MEM_K_PINLOC (PORT_MEM_K_PINLOC), + .PORT_MEM_K_N_PINLOC (PORT_MEM_K_N_PINLOC), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_C_PINLOC (PORT_MEM_C_PINLOC), + .PORT_MEM_CKE_PINLOC (PORT_MEM_CKE_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_RM_PINLOC (PORT_MEM_RM_PINLOC), + .PORT_MEM_ODT_PINLOC (PORT_MEM_ODT_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_RESET_N_PINLOC (PORT_MEM_RESET_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_PAR_PINLOC (PORT_MEM_PAR_PINLOC), + .PORT_MEM_CA_PINLOC (PORT_MEM_CA_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_DOFF_N_PINLOC (PORT_MEM_DOFF_N_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_LBK0_N_PINLOC (PORT_MEM_LBK0_N_PINLOC), + .PORT_MEM_LBK1_N_PINLOC (PORT_MEM_LBK1_N_PINLOC), + .PORT_MEM_CFG_N_PINLOC (PORT_MEM_CFG_N_PINLOC), + .PORT_MEM_AP_PINLOC (PORT_MEM_AP_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_QK_N_PINLOC (PORT_MEM_QK_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKA_N_PINLOC (PORT_MEM_QKA_N_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_QKB_N_PINLOC (PORT_MEM_QKB_N_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_CQ_N_PINLOC (PORT_MEM_CQ_N_PINLOC), + .PORT_MEM_ALERT_N_PINLOC (PORT_MEM_ALERT_N_PINLOC), + .PORT_MEM_PE_N_PINLOC (PORT_MEM_PE_N_PINLOC), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .LANES_USAGE (LANES_USAGE), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN), + .DB_PINS_PROC_MODE (DB_PINS_PROC_MODE), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO) + ) if_inst ( + .l2core_data (actual_l2core_data), + .l2core_rdata_valid_pri (actual_l2core_rdata_valid_pri), + .l2core_rdata_valid_sec (actual_l2core_rdata_valid_sec), + .* + ); + + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + assign phylite_interface_locked = '0; + assign phylite_data_to_core = '0; + assign phylite_rdata_valid = '0; + end else + begin : hmc + if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM") + begin : amm + if (GENERATE_PHYLITE) + begin: phylite + altera_emif_arch_fm_phylite_if # ( + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .UFI_LATENCY (UFI_LATENCY), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN), + .PORT_CTRL_DATA_OUT_WIDTH (PORT_CTRL_DATA_OUT_WIDTH), + .PORT_CTRL_DATA_IN_WIDTH (PORT_CTRL_DATA_IN_WIDTH), + .PORT_CTRL_STROBE_WIDTH (PORT_CTRL_STROBE_WIDTH), + .PORT_CTRL_RDATA_VALID_WIDTH (PORT_CTRL_RDATA_VALID_WIDTH), + .PORT_CTRL_RDATA_ENABLE_WIDTH (PORT_CTRL_RDATA_ENABLE_WIDTH), + .PORT_CTRL_DATA_OE_WIDTH (PORT_CTRL_DATA_OE_WIDTH), + .PORT_CTRL_STROBE_OE_WIDTH (PORT_CTRL_STROBE_OE_WIDTH) + ) phylite_if_inst ( + .l2core_data (actual_l2core_data), + .l2core_rdata_valid(l2core_rdata_valid_pri), + .* + ); + + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + end else + begin: amm + altera_emif_arch_fm_hmc_amm_data_if # ( + .HMC_READY_LATENCY (HMC_READY_LATENCY), + .REGISTER_AMM_C2P (REGISTER_AMM_C2P), + .REGISTER_AMM_P2C (REGISTER_AMM_P2C), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PORT_CTRL_AMM_RDATA_WIDTH (PORT_CTRL_AMM_RDATA_WIDTH), + .PORT_CTRL_AMM_WDATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .PORT_CTRL_AMM_BYTEEN_WIDTH (PORT_CTRL_AMM_BYTEEN_WIDTH), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN) + ) data_if_inst ( + .l2core_data (actual_l2core_data), + .* + ); + + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + assign phylite_rdata_valid = '0; + assign phylite_data_to_core = '0; + assign core2l_rdata_en_full = '0; + assign phylite_interface_locked = '0; + end + end else + begin : hmc_ast + altera_emif_arch_fm_hmc_ast_data_if # ( + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PORT_CTRL_AST_WR_DATA_WIDTH (PORT_CTRL_AST_WR_DATA_WIDTH), + .PORT_CTRL_AST_RD_DATA_WIDTH (PORT_CTRL_AST_RD_DATA_WIDTH), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN) + ) data_if_inst ( + .l2core_data (actual_l2core_data), + .* + ); + + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + assign core2l_rdata_en_full = '0; + assign phylite_rdata_valid = '0; + assign phylite_data_to_core = '0; + assign phylite_interface_locked = '0; + end + + assign afi_rdata_dbi_n = '0; + assign afi_rdata_dinv = '0; + assign afi_rdata = '0; + assign afi_rdata_valid = '0; + assign afi_alert_n = '0; + assign afi_pe_n = '0; + assign afi_err_n = '0; + assign afi_req_n = '0; + assign core2l_mrnk_read = '0; + assign core2l_mrnk_write = '0; + end + endgenerate + + altera_emif_arch_fm_cal_counter # ( + .IS_HPS (IS_HPS) + ) cal_counter_inst ( + .* + ); + + assign emif_to_hps = '0; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "EVeqkz9MvDzapiiVw7+udc++m43wu2P9R6Bkf/lfBn9ZttFzW71hzuu9P3yzPlvUUu1GESHEht8oUjkuxH5nYF5m2Y4yEaZOsor1W+qakklkcNM5gczDB8G/zUljAitcohcjlH9xX4F5r3RrLLQB1HrtXmnxKKrsVs2RsxKt4plRYJGUCxRjs6twKgr6lps1q22taZT7+7dZh7dYE0uKJfWB1PYeKR+rbOxvrAyMNm06gI1dBK7Kte80ufbyaP7O2JhiYO5lVNycMBuEdCZHNpyFt3EKGRmfHo9sUzcv1aWmjde16kIEHW7Gv+236xA8FIKQ+NGI4Wr4blbaVni38KK1hltcybOGnvqFSCzmw5JJL58pbWWPLD3Y33ZYcjmYuWSWwvDIUaw65A+eh3yB9sH29S+NZlKlFM/WY8z2bUSsn7Gv3DvxXHuZNXQFgqB14RO4l92kXwHRT8/mtX+inj/VRrcp0Dx94h6n6Fa5MsMw+5Fv+B9pe409UWcLpJqSF1JUpTU6/v9VGGT1d+/11ucJOmUOb8u6fXvXLMiv12IzwRGa7AFadnIP+H/+3pfhJI5CQzTyD4jf0U5cb61OJL5H6YOtLtfc0qVQvcYifpMDgYHbnP3ZRtjiobKypezlIUpVEW6QcriQ7iyGyRLPlt4VSOinLM4epVgKDQCzjjvODgIVDEUJRvq5C0+7fftiYyd3mZsh7czHBbGCKS4k57CswPR1CVa6CiqdU4K5SuZEYXyBMHG9JLZpZMPZ+/06C+A9kyvf/9rnyjd/fdmNX/eleQ6SDgRprMN1Dr6hsVYX7kEuIyVThCgb3H1yeiAsvCYDLXUVpFcACq45uo3+qAvt+Gu2ZSsMujNSEdBqEAYSkvY1xGjmOOrgIPEJOsHeV9pGfNLhoQwLswQcl34HWwVXU2YuT5wujpAAeluGGoXhTkVVhmPP2h8Mqf4/DCafXnNwG/WBQl4aXLouhCStCqe6bnXaNpomzeNw4sW60BNaOOyURi0W0j+ziThLb+YY" +`endif diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_utils.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_utils.tcl new file mode 100644 index 0000000000..dc75372bb4 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_utils.tcl @@ -0,0 +1,613 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + + +set script_dir [file dirname [info script]] + +load_package sdc_ext +load_package design + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_index_in_collection { col j } { + set i 0 + foreach_in_collection path $col { + if {$i == $j} { + return $path + } + set i [expr $i + 1] + } + return "" +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_to_pin_name_mapping {} { + set result [list] + set clocks_collection [get_clocks] + foreach_in_collection clock $clocks_collection { + if { ![is_clock_defined $clock] } { + continue + } + set clock_name [get_clock_info -name $clock] + set clock_target [get_clock_info -targets $clock] + set first_index [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_index_in_collection $clock_target 0] + set catch_exception_net [catch {get_net_info -name $first_index} pin_name_net] + if {$catch_exception_net == 0} { + lappend result [list $clock_name $pin_name_net] + } else { + set catch_exception_port [catch {get_port_info -name $first_index} pin_name_port] + if {$catch_exception_port == 0} { + lappend result [list $clock_name $pin_name_port] + } else { + set catch_exception_reg [catch {get_register_info -name $first_index} pin_name_reg] + if {$catch_exception_reg == 0} { + lappend result [list $clock_name $pin_name_reg] + } else { + set catch_exception_pin [catch {get_pin_info -name $first_index} pin_name_pin] + if {$catch_exception_pin == 0} { + lappend result [list $clock_name $pin_name_pin] + } + } + } + } + } + return $result +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_name_from_pin_name { pin_name } { + set table [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_to_pin_name_mapping] + foreach entry $table { + if {[string compare [lindex [lindex [split $entry] 1] 0] $pin_name] == 0} { + return [lindex $entry 0] + } + } + return "" +} + + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_find_all_keepers { mystring } { + set allkeepers [get_keepers $mystring ] + + foreach_in_collection keeper $allkeepers { + set keepername [ get_node_info -name $keeper ] + + puts "$keepername" + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_round_3dp { x } { + return [expr { round($x * 1000) / 1000.0 } ] +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_current_timequest_report_folder {} { + + set catch_exception [catch {get_current_timequest_report_folder} error_message] + if {[regexp ERROR $error_message] == 1} { + return "ReportDDR" + } else { + return [get_current_timequest_report_folder] + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_timequest_name {hier_name} { + set sta_name $hier_name + return $sta_name +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_are_entity_names_on { } { + return [set_project_mode -is_show_entity] +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_instance_list {corename} { + global ::io_only_analysis + + if {$::io_only_analysis == 1} { + set instance_list [list $corename] + + } else { + set full_instance_list [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_full_instance_list $corename] + set instance_list [list] + + foreach inst $full_instance_list { + set sta_name [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_timequest_name $inst] + if {[lsearch $instance_list [escape_brackets $sta_name]] == -1} { + lappend instance_list $sta_name + } + } + + } + return $instance_list +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_or_add_generated_clock {args} { + array set opts [list -name "" -target "" -source "" -multiply_by 1 -divide_by 1 -phase 0] + array set opts $args + + set multiply_by [expr int($opts(-multiply_by))] + if {[expr $multiply_by - $opts(-multiply_by)] != 0.0} { + post_message -type error "Specify an integer ranging from 0 to 99999999 for the option -multiply_by" + return "" + } + + set clock_name [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_name_from_pin_name $opts(-target)] + + if {[string compare -nocase $clock_name ""] == 0} { + set nets [get_nets $opts(-target) -nowarn] + if {[get_collection_size $nets] > 0} { + set pin_name [get_pin_info -name [get_net_info -pin $nets]] + set clock_name [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_clock_name_from_pin_name $pin_name] + + if {[string compare -nocase $clock_name ""] != 0} { + if {[regexp -nocase "lvds_clk" $pin_name] || [regexp -nocase "loaden" $pin_name] } { + remove_clock $clock_name + set clock_name "" + } + } + } + } else { + if {([string compare -nocase $opts(-name) ""] != 0) && ([string compare -nocase $opts(-name) $clock_name])} { + + if {[regexp -nocase "pll_inst\|outclk" $opts(-target)]} { + remove_clock $clock_name + set clock_name "" + } + } + } + + if {[string compare -nocase $clock_name ""] == 0} { + set clock_name $opts(-name) + + create_generated_clock \ + -name $clock_name \ + -source $opts(-source) \ + -multiply_by $multiply_by \ + -divide_by $opts(-divide_by) \ + -phase $opts(-phase) \ + $opts(-target) + } + + return $clock_name +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_core_full_instance_list {corename} { + + set instance_list [list] + + if {[is_fitter_in_qhd_mode]} { + set instance_list_pre [design::get_instances -entity $corename] + + } else { + set instance_list_pre [get_entity_instances $corename] + } + + foreach instance $instance_list_pre { + regsub {\|arch$} $instance "" instance_no_arch + lappend instance_list $instance_no_arch + } + + if {[ llength $instance_list ] == 0} { + post_message -type error "The auto-constraining script was not able to detect any instance for core < $corename >" + post_message -type error "Make sure the core < $corename > is instantiated within another component (wrapper)" + post_message -type error "and it's not the top-level for your project" + } + + return $instance_list +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_fanin_up_to_depth { node_id match_command edge_type results_array_name depth} { + upvar 1 $results_array_name results + + if {$depth < 0} { + error "Internal error: Bad timing netlist search depth" + } + set fanin_edges [get_node_info -${edge_type}_edges $node_id] + set number_of_fanin_edges [llength $fanin_edges] + for {set i 0} {$i != $number_of_fanin_edges} {incr i} { + set fanin_edge [lindex $fanin_edges $i] + set fanin_id [get_edge_info -src $fanin_edge] + if {$match_command == "" || [eval $match_command $fanin_id] != 0} { + set results($fanin_id) 1 + } elseif {$depth == 0} { + } else { + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_fanin_up_to_depth $fanin_id $match_command $edge_type results [expr {$depth - 1}] + } + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_is_node_type_pin { node_id } { + set node_type [get_node_info -type $node_id] + if {$node_type == "port"} { + set result 1 + } else { + set result 0 + } + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_pll_clock_name { clock_id } { + set clock_name [get_node_info -name $clock_id] + + return $clock_name +} + +proc post_sdc_message {msg_type msg} { + global ::io_only_analysis + + if {($::io_only_analysis == 1) || $::TimeQuestInfo(nameofexecutable) != "quartus_fit"} { + post_message -type $msg_type $msg + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_names_in_collection { col } { + set res [list] + foreach_in_collection node $col { + lappend res [ get_node_info -name $node ] + } + return $res +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_format_3dp { x } { + return [format %.3f $x] +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_colours { x y } { + + set fcolour [list "black"] + if {$x < 0} { + lappend fcolour "red" + } else { + lappend fcolour "blue" + } + if {$y < 0} { + lappend fcolour "red" + } else { + lappend fcolour "blue" + } + + return $fcolour +} + +proc min { a b } { + if { $a == "" } { + return $b + } elseif { $a < $b } { + return $a + } else { + return $b + } +} + +proc max { a b } { + if { $a == "" } { + return $b + } elseif { $a > $b } { + return $a + } else { + return $b + } +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_max_in_collection { col attribute } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + return $max +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection { col attribute } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection_to_clock { col attribute clock } { + set i 0 + set min ERROR + foreach_in_collection path $col { + if {[get_clock_info -name [get_path_info $path -to_clock]] == $clock} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection_from_clock { col attribute clock } { + set i 0 + set min ERROR + foreach_in_collection path $col { + if {[get_clock_info -name [get_path_info $path -from_clock]] == $clock} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection_to_name { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -to]] == $name} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection_from_name { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -from]] == $name} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_max_in_collection_to_name { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -to]] == $name} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_max_in_collection_from_name { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[get_node_info -name [get_path_info $path -from]] == $name} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection_to_name2 { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -to]]]} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_min_in_collection_from_name2 { col attribute name } { + set i 0 + set min 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -from]]]} { + if {$i == 0} { + set min [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp < $min} { + set min $temp + } + } + set i [expr $i + 1] + } + } + return $min +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_max_in_collection_to_name2 { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -to]]]} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_max_in_collection_from_name2 { col attribute name } { + set i 0 + set max 0 + foreach_in_collection path $col { + if {[regexp $name [get_node_info -name [get_path_info $path -from]]]} { + if {$i == 0} { + set max [get_path_info $path -${attribute}] + } else { + set temp [get_path_info $path -${attribute}] + if {$temp > $max} { + set max $temp + } + } + set i [expr $i + 1] + } + } + return $max +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_sort_proc {a b} { + set idxs [list 1 2 0] + foreach i $idxs { + set ai [lindex $a $i] + set bi [lindex $b $i] + if {$ai > $bi} { + return 1 + } elseif { $ai < $bi } { + return -1 + } + } + return 0 +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_gcd {p q} { + set p [expr {abs($p)}] + set q [expr {abs($q)}] + while {$q != 0} { + set r [expr {$p % $q}] + set p $q + set q $r + } + return $p +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_atom_path {atom_id atom_oport_id path} { + # Return list of {atom oterm_id} pairs by tracing the atom netlist starting from the given atom_id through the given path + # Path consists of list of {atom_type fanin|fanout|end <-optional>} + set result [list] + if {[llength $path] > 0} { + set path_point [lindex $path 0] + set atom_type [lindex $path_point 0] + set next_direction [lindex $path_point 1] + set port_type [lindex $path_point 2] + set atom_optional [lindex $path_point 3] + if {[get_atom_node_info -key type -node $atom_id] == $atom_type} { + if {$next_direction == "end"} { + if {[get_atom_port_info -key type -node $atom_id -port_id $atom_oport_id -type oport] == $port_type} { + lappend result [list $atom_id $atom_oport_id] + } + } elseif {$next_direction == "atom"} { + lappend result [list $atom_id] + } elseif {$next_direction == "fanin"} { + set atom_iport [get_atom_iport_by_type -node $atom_id -type $port_type] + if {$atom_iport != -1} { + set iport_fanin [get_atom_port_info -key fanin -node $atom_id -port_id $atom_iport -type iport] + set source_atom [lindex $iport_fanin 0] + set source_oterm [lindex $iport_fanin 1] + set result [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_atom_path $source_atom $source_oterm [lrange $path 1 end]] + } elseif {$atom_optional == "-optional"} { + set result [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_atom_path $atom_id $atom_oport_id [lrange $path 1 end]] + } + } elseif {$next_direction == "fanout"} { + set atom_oport [get_atom_oport_by_type -node $atom_id -type $port_type] + if {$atom_oport != -1} { + set oport_fanout [get_atom_port_info -key fanout -node $atom_id -port_id $atom_oport -type oport] + foreach dest $oport_fanout { + set dest_atom [lindex $dest 0] + set dest_iterm [lindex $dest 1] + set fanout_result_list [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_atom_path $dest_atom -1 [lrange $path 1 end]] + foreach fanout_result $fanout_result_list { + if {[lsearch $result $fanout_result] == -1} { + lappend result $fanout_result + } + } + } + } + } else { + error "Unexpected path" + } + } elseif {$atom_optional == "-optional"} { + set result [ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_traverse_atom_path $atom_id $atom_oport_id [lrange $path 1 end]] + } + } + return $result +} + +proc ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_get_operating_conditions_number {} { + set cur_operating_condition [get_operating_conditions] + set counter 0 + foreach_in_collection op [get_available_operating_conditions] { + if {[string compare $cur_operating_condition $op] == 0} { + return $counter + } + incr counter + } + return $counter +} diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_191/synth/ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_191/synth/ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq.v new file mode 100644 index 0000000000..a9e1e45ffc --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_191/synth/ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq.v @@ -0,0 +1,211 @@ +// ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq.v + +// This file was auto-generated from altera_emif_ecc_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq ( + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n, Reset for the user clock domain. Asynchronous assertion and synchronous deassertion + output wire emif_usr_clk, // emif_usr_clk.clk, User clock domain + input wire emif_usr_reset_n_in, // emif_usr_reset_n_in.reset_n, Reset for the user clock domain. Asynchronous assertion and synchronous deassertion + input wire emif_usr_clk_in, // emif_usr_clk_in.clk, User clock domain + output wire [14:0] ctrl_ecc_write_info_0, // ctrl_ecc_0.ctrl_ecc_write_info + input wire [12:0] ctrl_ecc_rdata_id_0, // .ctrl_ecc_rdata_id + input wire [2:0] ctrl_ecc_read_info_0, // .ctrl_ecc_read_info + input wire [2:0] ctrl_ecc_cmd_info_0, // .ctrl_ecc_cmd_info + input wire ctrl_ecc_idle_0, // .ctrl_ecc_idle + input wire [11:0] ctrl_ecc_wr_pointer_info_0, // .ctrl_ecc_wr_pointer_info + output wire ctrl_ecc_user_interrupt_0, // ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt, Controller ECC user interrupt signal to determine whether there is a bit error + output wire ast_cmd_valid_0, // ctrl_ast_cmd_0.valid, Indicates whether command is valid + input wire ast_cmd_ready_0, // .ready, Comand request signal + output wire [60:0] ast_cmd_data_0, // .data, Command data + output wire ast_wr_valid_0, // ctrl_ast_wr_0.valid, Indicates whether write data is valid + input wire ast_wr_ready_0, // .ready, Write request signal + output wire [647:0] ast_wr_data_0, // .data, Write data + input wire ast_rd_valid_0, // ctrl_ast_rd_0.valid, Read request signal + output wire ast_rd_ready_0, // .ready, Indicates whether read data is valid + input wire [575:0] ast_rd_data_0, // .data, Read data + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n, Wait-request is asserted when controller is busy + input wire amm_read_0, // .read, Read request signal + input wire amm_write_0, // .write, Write request signal + input wire [26:0] amm_address_0, // .address, Address for the read/write request + output wire [511:0] amm_readdata_0, // .readdata, Read data + input wire [511:0] amm_writedata_0, // .writedata, Write data + input wire [6:0] amm_burstcount_0, // .burstcount, Number of transfers in each read/write burst + input wire [63:0] amm_byteenable_0, // .byteenable, Byte-enable for write data + output wire amm_readdatavalid_0 // .readdatavalid, Indicates whether read data is valid + ); + + altera_emif_ecc_core #( + .PHY_PING_PONG_EN (0), + .CTRL_MMR_EN (0), + .DIAG_USE_ABSTRACT_PHY (0), + .DIAG_SIM_MEMORY_PRELOAD (0), + .DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE (""), + .DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE (""), + .DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE (""), + .DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE (""), + .DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE (""), + .DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE (""), + .USER_CLK_RATIO (4), + .C2P_P2C_CLK_RATIO (4), + .PHY_HMC_CLK_RATIO (2), + .USE_AVL_BYTEEN (1), + .ENABLE_ECC (1), + .ENABLE_ECC_AUTO_CORRECTION (0), + .REGISTER_RDATA_PATH_NUM (2), + .REGISTER_WDATA_PATH_NUM (2), + .REGISTER_UFI_RDATA_PATH_NUM (0), + .REGISTER_ST_WDATA_RDY_LAT_PATH (0), + .REGISTER_ST_RDATA_RDY_LAT_PATH (0), + .REGISTER_ST_CMD_RDY_LAT_PATH (0), + .REGISTER_CORE_CMD_PIPELINE_WDATA (0), + .MEM_DQ_WIDTH (72), + .ECC_MMR_READ_LATENCY (5), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (15), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (13), + .PORT_CTRL_ECC_READ_INFO_WIDTH (3), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (3), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (12), + .PORT_CTRL_ECC_STS_INTR_WIDTH (1), + .PORT_CTRL_ECC_STS_SBE_ERROR_WIDTH (1), + .PORT_CTRL_ECC_STS_DBE_ERROR_WIDTH (1), + .PORT_CTRL_ECC_STS_CORR_DROPPED_WIDTH (1), + .PORT_CTRL_ECC_STS_SBE_COUNT_WIDTH (4), + .PORT_CTRL_ECC_STS_DBE_COUNT_WIDTH (4), + .PORT_CTRL_ECC_STS_CORR_DROPPED_COUNT_WIDTH (4), + .PORT_CTRL_ECC_STS_ERR_ADDR_WIDTH (35), + .PORT_CTRL_ECC_STS_CORR_DROPPED_ADDR_WIDTH (35), + .PORT_CTRL_AST_CMD_DATA_WIDTH (61), + .PORT_CTRL_AST_WR_DATA_WIDTH (648), + .PORT_CTRL_AST_RD_DATA_WIDTH (576), + .PORT_CTRL_AMM_ADDRESS_WIDTH (27), + .PORT_CTRL_AMM_RDATA_WIDTH (512), + .PORT_CTRL_AMM_WDATA_WIDTH (512), + .PORT_CTRL_AMM_BCOUNT_WIDTH (7), + .PORT_CTRL_AMM_BYTEEN_WIDTH (64), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (10), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (2), + .PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH (10), + .PORT_CTRL_MMR_MASTER_RDATA_WIDTH (32), + .PORT_CTRL_MMR_MASTER_WDATA_WIDTH (32), + .PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH (2) + ) core ( + .emif_usr_reset_n (emif_usr_reset_n), // output, width = 1, emif_usr_reset_n.reset_n + .emif_usr_clk (emif_usr_clk), // output, width = 1, emif_usr_clk.clk + .emif_usr_reset_n_in (emif_usr_reset_n_in), // input, width = 1, emif_usr_reset_n_in.reset_n + .emif_usr_clk_in (emif_usr_clk_in), // input, width = 1, emif_usr_clk_in.clk + .ctrl_ecc_write_info_0 (ctrl_ecc_write_info_0), // output, width = 15, ctrl_ecc_0.ctrl_ecc_write_info + .ctrl_ecc_rdata_id_0 (ctrl_ecc_rdata_id_0), // input, width = 13, .ctrl_ecc_rdata_id + .ctrl_ecc_read_info_0 (ctrl_ecc_read_info_0), // input, width = 3, .ctrl_ecc_read_info + .ctrl_ecc_cmd_info_0 (ctrl_ecc_cmd_info_0), // input, width = 3, .ctrl_ecc_cmd_info + .ctrl_ecc_idle_0 (ctrl_ecc_idle_0), // input, width = 1, .ctrl_ecc_idle + .ctrl_ecc_wr_pointer_info_0 (ctrl_ecc_wr_pointer_info_0), // input, width = 12, .ctrl_ecc_wr_pointer_info + .ctrl_ecc_user_interrupt_0 (ctrl_ecc_user_interrupt_0), // output, width = 1, ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt + .ast_cmd_valid_0 (ast_cmd_valid_0), // output, width = 1, ctrl_ast_cmd_0.valid + .ast_cmd_ready_0 (ast_cmd_ready_0), // input, width = 1, .ready + .ast_cmd_data_0 (ast_cmd_data_0), // output, width = 61, .data + .ast_wr_valid_0 (ast_wr_valid_0), // output, width = 1, ctrl_ast_wr_0.valid + .ast_wr_ready_0 (ast_wr_ready_0), // input, width = 1, .ready + .ast_wr_data_0 (ast_wr_data_0), // output, width = 648, .data + .ast_rd_valid_0 (ast_rd_valid_0), // input, width = 1, ctrl_ast_rd_0.valid + .ast_rd_ready_0 (ast_rd_ready_0), // output, width = 1, .ready + .ast_rd_data_0 (ast_rd_data_0), // input, width = 576, .data + .amm_ready_0 (amm_ready_0), // output, width = 1, ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // input, width = 1, .read + .amm_write_0 (amm_write_0), // input, width = 1, .write + .amm_address_0 (amm_address_0), // input, width = 27, .address + .amm_readdata_0 (amm_readdata_0), // output, width = 512, .readdata + .amm_writedata_0 (amm_writedata_0), // input, width = 512, .writedata + .amm_burstcount_0 (amm_burstcount_0), // input, width = 7, .burstcount + .amm_byteenable_0 (amm_byteenable_0), // input, width = 64, .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0), // output, width = 1, .readdatavalid + .amm_beginbursttransfer_0 (1'b0), // (terminated), + .amm_beginbursttransfer_1 (1'b0), // (terminated), + .emif_usr_reset_n_sec (), // (terminated), + .emif_usr_clk_sec (), // (terminated), + .emif_usr_reset_n_sec_in (1'b1), // (terminated), + .emif_usr_clk_sec_in (1'b0), // (terminated), + .ctrl_ecc_write_info_1 (), // (terminated), + .ctrl_ecc_rdata_id_1 (13'b0000000000000), // (terminated), + .ctrl_ecc_read_info_1 (3'b000), // (terminated), + .ctrl_ecc_cmd_info_1 (3'b000), // (terminated), + .ctrl_ecc_idle_1 (1'b0), // (terminated), + .ctrl_ecc_wr_pointer_info_1 (12'b000000000000), // (terminated), + .ctrl_ecc_user_interrupt_1 (), // (terminated), + .ctrl_ecc_readdataerror_0 (), // (terminated), + .ctrl_ecc_readdataerror_1 (), // (terminated), + .ctrl_ecc_sts_intr (), // (terminated), + .ctrl_ecc_sts_sbe_error (), // (terminated), + .ctrl_ecc_sts_dbe_error (), // (terminated), + .ctrl_ecc_sts_corr_dropped (), // (terminated), + .ctrl_ecc_sts_sbe_count (), // (terminated), + .ctrl_ecc_sts_dbe_count (), // (terminated), + .ctrl_ecc_sts_corr_dropped_count (), // (terminated), + .ctrl_ecc_sts_err_addr (), // (terminated), + .ctrl_ecc_sts_corr_dropped_addr (), // (terminated), + .ast_cmd_valid_1 (), // (terminated), + .ast_cmd_ready_1 (1'b0), // (terminated), + .ast_cmd_data_1 (), // (terminated), + .ast_wr_valid_1 (), // (terminated), + .ast_wr_ready_1 (1'b0), // (terminated), + .ast_wr_data_1 (), // (terminated), + .ast_rd_valid_1 (1'b0), // (terminated), + .ast_rd_ready_1 (), // (terminated), + .ast_rd_data_1 (576'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .amm_ready_1 (), // (terminated), + .amm_read_1 (1'b0), // (terminated), + .amm_write_1 (1'b0), // (terminated), + .amm_address_1 (27'b000000000000000000000000000), // (terminated), + .amm_readdata_1 (), // (terminated), + .amm_writedata_1 (512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .amm_burstcount_1 (7'b0000000), // (terminated), + .amm_byteenable_1 (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .amm_readdatavalid_1 (), // (terminated), + .mmr_slave_waitrequest_0 (), // (terminated), + .mmr_slave_read_0 (1'b0), // (terminated), + .mmr_slave_write_0 (1'b0), // (terminated), + .mmr_slave_address_0 (10'b0000000000), // (terminated), + .mmr_slave_readdata_0 (), // (terminated), + .mmr_slave_writedata_0 (32'b00000000000000000000000000000000), // (terminated), + .mmr_slave_burstcount_0 (2'b00), // (terminated), + .mmr_slave_beginbursttransfer_0 (1'b0), // (terminated), + .mmr_slave_readdatavalid_0 (), // (terminated), + .mmr_slave_waitrequest_1 (), // (terminated), + .mmr_slave_read_1 (1'b0), // (terminated), + .mmr_slave_write_1 (1'b0), // (terminated), + .mmr_slave_address_1 (10'b0000000000), // (terminated), + .mmr_slave_readdata_1 (), // (terminated), + .mmr_slave_writedata_1 (32'b00000000000000000000000000000000), // (terminated), + .mmr_slave_burstcount_1 (2'b00), // (terminated), + .mmr_slave_beginbursttransfer_1 (1'b0), // (terminated), + .mmr_slave_readdatavalid_1 (), // (terminated), + .mmr_master_waitrequest_0 (1'b0), // (terminated), + .mmr_master_read_0 (), // (terminated), + .mmr_master_write_0 (), // (terminated), + .mmr_master_address_0 (), // (terminated), + .mmr_master_readdata_0 (32'b00000000000000000000000000000000), // (terminated), + .mmr_master_writedata_0 (), // (terminated), + .mmr_master_burstcount_0 (), // (terminated), + .mmr_master_beginbursttransfer_0 (), // (terminated), + .mmr_master_readdatavalid_0 (1'b0), // (terminated), + .mmr_master_waitrequest_1 (1'b0), // (terminated), + .mmr_master_read_1 (), // (terminated), + .mmr_master_write_1 (), // (terminated), + .mmr_master_address_1 (), // (terminated), + .mmr_master_readdata_1 (32'b00000000000000000000000000000000), // (terminated), + .mmr_master_writedata_1 (), // (terminated), + .mmr_master_burstcount_1 (), // (terminated), + .mmr_master_beginbursttransfer_1 (), // (terminated), + .mmr_master_readdatavalid_1 (1'b0), // (terminated), + .ctrl_user_priority_hi_0 (1'b0), // (terminated), + .ctrl_user_priority_hi_1 (1'b0), // (terminated), + .ctrl_auto_precharge_req_0 (1'b0), // (terminated), + .ctrl_auto_precharge_req_1 (1'b0) // (terminated), + ); + +endmodule diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/altera_emif_ecc_core.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/altera_emif_ecc_core.v new file mode 100644 index 0000000000..f05b25cf12 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/altera_emif_ecc_core.v @@ -0,0 +1,908 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module altera_emif_ecc_core # +( + parameter USER_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter PHY_PING_PONG_EN = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_SIM_MEMORY_PRELOAD = 0, + parameter DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE = "", + parameter REGISTER_RDATA_PATH_NUM = 2, + parameter REGISTER_UFI_RDATA_PATH_NUM = 2, + parameter REGISTER_WDATA_PATH_NUM = 2, + parameter REGISTER_ST_WDATA_RDY_LAT_PATH = 0, + parameter REGISTER_ST_RDATA_RDY_LAT_PATH = 0, + parameter REGISTER_ST_CMD_RDY_LAT_PATH = 0, + parameter REGISTER_CORE_CMD_PIPELINE_WDATA = 1, + parameter USE_AVL_BYTEEN = 1, + parameter ENABLE_ECC = 1, + parameter ENABLE_ECC_AUTO_CORRECTION = 1, + parameter MEM_DQ_WIDTH = 1, + parameter CTRL_MMR_EN = 0, + parameter ECC_MMR_READ_LATENCY = 2, + + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 1, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 1, + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 1, + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 1, + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 1, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_AMM_RDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 1, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 1, + parameter PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_MASTER_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_MASTER_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 1, + + parameter PORT_CTRL_ECC_STS_INTR_WIDTH = 1, + parameter PORT_CTRL_ECC_STS_SBE_ERROR_WIDTH = 1, + parameter PORT_CTRL_ECC_STS_DBE_ERROR_WIDTH = 1, + parameter PORT_CTRL_ECC_STS_CORR_DROPPED_WIDTH = 1, + parameter PORT_CTRL_ECC_STS_SBE_COUNT_WIDTH = 4, + parameter PORT_CTRL_ECC_STS_DBE_COUNT_WIDTH = 4, + parameter PORT_CTRL_ECC_STS_CORR_DROPPED_COUNT_WIDTH = 4, + parameter PORT_CTRL_ECC_STS_ERR_ADDR_WIDTH = 35, + parameter PORT_CTRL_ECC_STS_CORR_DROPPED_ADDR_WIDTH = 35 +) +( + emif_usr_reset_n, + emif_usr_clk, + emif_usr_reset_n_in, + emif_usr_clk_in, + + emif_usr_reset_n_sec, + emif_usr_clk_sec, + emif_usr_reset_n_sec_in, + emif_usr_clk_sec_in, + + amm_ready_0, + amm_read_0, + amm_write_0, + amm_address_0, + amm_readdata_0, + amm_writedata_0, + amm_burstcount_0, + amm_byteenable_0, + amm_readdatavalid_0, + amm_beginbursttransfer_0, + + amm_ready_1, + amm_read_1, + amm_write_1, + amm_address_1, + amm_readdata_1, + amm_writedata_1, + amm_burstcount_1, + amm_byteenable_1, + amm_readdatavalid_1, + amm_beginbursttransfer_1, + + mmr_slave_waitrequest_0, + mmr_slave_address_0, + mmr_slave_write_0, + mmr_slave_read_0, + mmr_slave_burstcount_0, + mmr_slave_beginbursttransfer_0, + mmr_slave_writedata_0, + mmr_slave_readdata_0, + mmr_slave_readdatavalid_0, + + mmr_slave_waitrequest_1, + mmr_slave_address_1, + mmr_slave_write_1, + mmr_slave_read_1, + mmr_slave_burstcount_1, + mmr_slave_beginbursttransfer_1, + mmr_slave_writedata_1, + mmr_slave_readdata_1, + mmr_slave_readdatavalid_1, + + mmr_master_waitrequest_0, + mmr_master_address_0, + mmr_master_write_0, + mmr_master_read_0, + mmr_master_burstcount_0, + mmr_master_beginbursttransfer_0, + mmr_master_writedata_0, + mmr_master_readdata_0, + mmr_master_readdatavalid_0, + + mmr_master_waitrequest_1, + mmr_master_address_1, + mmr_master_write_1, + mmr_master_read_1, + mmr_master_burstcount_1, + mmr_master_beginbursttransfer_1, + mmr_master_writedata_1, + mmr_master_readdata_1, + mmr_master_readdatavalid_1, + + ctrl_user_priority_hi_0, + ctrl_auto_precharge_req_0, + + ctrl_user_priority_hi_1, + ctrl_auto_precharge_req_1, + + ast_cmd_ready_0, + ast_cmd_valid_0, + ast_cmd_data_0, + ast_wr_ready_0, + ast_wr_valid_0, + ast_wr_data_0, + ast_rd_ready_0, + ast_rd_valid_0, + ast_rd_data_0, + + ast_cmd_ready_1, + ast_cmd_valid_1, + ast_cmd_data_1, + ast_wr_ready_1, + ast_wr_valid_1, + ast_wr_data_1, + ast_rd_ready_1, + ast_rd_valid_1, + ast_rd_data_1, + + ctrl_ecc_sts_intr, + ctrl_ecc_sts_sbe_error, + ctrl_ecc_sts_dbe_error, + ctrl_ecc_sts_corr_dropped, + ctrl_ecc_sts_sbe_count, + ctrl_ecc_sts_dbe_count, + ctrl_ecc_sts_corr_dropped_count, + ctrl_ecc_sts_err_addr, + ctrl_ecc_sts_corr_dropped_addr, + + ctrl_ecc_cmd_info_0, + ctrl_ecc_rdata_id_0, + ctrl_ecc_write_info_0, + ctrl_ecc_read_info_0, + ctrl_ecc_wr_pointer_info_0, + ctrl_ecc_idle_0, + ctrl_ecc_user_interrupt_0, + ctrl_ecc_readdataerror_0, + + ctrl_ecc_cmd_info_1, + ctrl_ecc_rdata_id_1, + ctrl_ecc_write_info_1, + ctrl_ecc_read_info_1, + ctrl_ecc_wr_pointer_info_1, + ctrl_ecc_idle_1, + ctrl_ecc_user_interrupt_1, + ctrl_ecc_readdataerror_1 +); + +// Override simulation-specific parameters for synthesis +// synthesis read_comments_as_HDL on +// `define DISABLE_SIM_PARAMS_FOR_SYNTH TRUE +// synthesis read_comments_as_HDL off +`ifdef DISABLE_SIM_PARAMS_FOR_SYNTH + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = 0; + localparam DIAG_SIM_MEMORY_PRELOAD_AFT_SYNTH_OVRD = 0; +`else + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = DIAG_USE_ABSTRACT_PHY; + localparam DIAG_SIM_MEMORY_PRELOAD_AFT_SYNTH_OVRD = DIAG_SIM_MEMORY_PRELOAD; +`endif + +localparam PORT_CTRL_ECC_STS_MR_DATA = PORT_CTRL_AST_RD_DATA_WIDTH; +localparam PORT_CTRL_ECC_STS_MR_DATA_VALID = 1; + +localparam CFG_LOCAL_CMD_WIDTH = 2; +localparam CFG_LOCAL_ADDR_WIDTH = PORT_CTRL_AMM_ADDRESS_WIDTH; +localparam CFG_LOCAL_SIZE_WIDTH = PORT_CTRL_AMM_BCOUNT_WIDTH; +localparam CFG_LOCAL_ID_WIDTH = 13; +localparam CFG_LOCAL_PRI_WIDTH = 1; +localparam CFG_LOCAL_AP_WIDTH = 1; +localparam CFG_LOCAL_MC_WIDTH = 1; +localparam CFG_ECC_CODE_WIDTH = 8; +localparam CFG_LOCAL_CMD_DATA_WIDTH = PORT_CTRL_AST_CMD_DATA_WIDTH; +localparam CFG_LOCAL_CMD_INFO_WIDTH = PORT_CTRL_ECC_CMD_INFO_WIDTH; +localparam CFG_LOCAL_DATA_WIDTH = PORT_CTRL_AMM_WDATA_WIDTH; +localparam CFG_LOCAL_BE_WIDTH = PORT_CTRL_AMM_WDATA_WIDTH / 8; +localparam CFG_LOCAL_DATA_INFO_WIDTH = PORT_CTRL_ECC_READ_INFO_WIDTH; +localparam CFG_LOCAL_DATA_PTR_WIDTH = PORT_CTRL_ECC_WB_POINTER_WIDTH; +localparam CFG_MEM_IF_DATA_WIDTH = PORT_CTRL_AMM_WDATA_WIDTH / USER_CLK_RATIO / 2; +localparam CFG_ECC_DATA_WIDTH = PORT_CTRL_AST_RD_DATA_WIDTH; +localparam CFG_ECC_BE_WIDTH = PORT_CTRL_AST_RD_DATA_WIDTH / 8; +localparam CFG_ECC_MULTIPLE_INSTANCE = (CFG_MEM_IF_DATA_WIDTH <= 72) ? (USER_CLK_RATIO == 4) ? 8 : 4 : (USER_CLK_RATIO == 4) ? 16 : 8; + +localparam CFG_ADDR_ENCODE_ENABLED = 0; +localparam CFG_REGISTER_CMD_PATH = 1; +localparam CFG_REGISTER_RDATA_PATH = 1; +localparam CFG_REGISTER_WDATA_PATH = 1; +localparam CFG_MMR_WRPATH_PIPELINE_EN = 1; +localparam CFG_WRBUFFER_ADDR_WIDTH = 5; +localparam CFG_PORT_WIDTH_DRAM_DATA_WIDTH = 8; +localparam CFG_PORT_WIDTH_LOCAL_DATA_WIDTH = 8; +localparam CFG_PORT_WIDTH_ADDR_WIDTH = 6; +localparam CFG_PORT_WIDTH_DATA_RATE = 4; +localparam CFG_PORT_WIDTH_ECC_IN_PROTOCOL = 1; +localparam CFG_PORT_WIDTH_WRPATH_PIPELINE_EN = 1; +localparam CFG_PORT_WIDTH_ENABLE_ECC = 1; +localparam CFG_PORT_WIDTH_ENABLE_DM = 1; +localparam CFG_PORT_WIDTH_ENABLE_RMW = 1; +localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1; +localparam CFG_PORT_WIDTH_ECC_CODE_OVERWRITE = 1; +localparam CFG_PORT_WIDTH_GEN_SBE = 1; +localparam CFG_PORT_WIDTH_GEN_DBE = 1; +localparam CFG_PORT_WIDTH_ENABLE_INTR = 1; +localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1; +localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1; +localparam CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1; +localparam CFG_PORT_WIDTH_MASK_HMI_INTR = 1; +localparam CFG_PORT_WIDTH_CLR_INTR = 1; +localparam CFG_PORT_WIDTH_CLR_MR_RDATA = 1; +localparam CFG_MMR_DATA_WIDTH = 32; + +localparam STS_PORT_WIDTH_ECC_INTR = 1; +localparam STS_PORT_WIDTH_SBE_ERROR = 1; +localparam STS_PORT_WIDTH_DBE_ERROR = 1; +localparam STS_PORT_WIDTH_CORR_DROPPED = 1; +localparam STS_PORT_WIDTH_SBE_COUNT = 4; +localparam STS_PORT_WIDTH_DBE_COUNT = 4; +localparam STS_PORT_WIDTH_CORR_DROPPED_COUNT = 4; +localparam STS_PORT_WIDTH_ERR_ADDR = 35; +localparam STS_PORT_WIDTH_CORR_DROPPED_ADDR = 35; +localparam STS_PORT_WIDTH_MR_DATA = PORT_CTRL_AST_RD_DATA_WIDTH; +localparam STS_PORT_WIDTH_MR_DATA_VALID = 1; + + +input emif_usr_reset_n_in; +input emif_usr_clk_in; +output emif_usr_reset_n; +output emif_usr_clk; + +input emif_usr_reset_n_sec_in; +input emif_usr_clk_sec_in; +output emif_usr_reset_n_sec; +output emif_usr_clk_sec; + +output wire [PORT_CTRL_ECC_STS_INTR_WIDTH - 1 : 0] ctrl_ecc_sts_intr; +output wire [PORT_CTRL_ECC_STS_SBE_ERROR_WIDTH - 1 : 0] ctrl_ecc_sts_sbe_error; +output wire [PORT_CTRL_ECC_STS_DBE_ERROR_WIDTH - 1 : 0] ctrl_ecc_sts_dbe_error; +output wire [PORT_CTRL_ECC_STS_CORR_DROPPED_WIDTH - 1 : 0] ctrl_ecc_sts_corr_dropped; +output wire [PORT_CTRL_ECC_STS_SBE_COUNT_WIDTH - 1 : 0] ctrl_ecc_sts_sbe_count; +output wire [PORT_CTRL_ECC_STS_DBE_COUNT_WIDTH - 1 : 0] ctrl_ecc_sts_dbe_count; +output wire [PORT_CTRL_ECC_STS_CORR_DROPPED_COUNT_WIDTH - 1 : 0] ctrl_ecc_sts_corr_dropped_count; +output wire [PORT_CTRL_ECC_STS_ERR_ADDR_WIDTH - 1 : 0] ctrl_ecc_sts_err_addr; +output wire [PORT_CTRL_ECC_STS_CORR_DROPPED_ADDR_WIDTH - 1 : 0] ctrl_ecc_sts_corr_dropped_addr; + +wire [STS_PORT_WIDTH_ECC_INTR - 1 : 0] sts_ecc_intr_0; +wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error_0; +wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error_0; +wire [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] sts_corr_dropped_0; +wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count_0; +wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count_0; +wire [STS_PORT_WIDTH_CORR_DROPPED_COUNT - 1 : 0] sts_corr_dropped_count_0; +wire [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] sts_err_addr_0; +wire [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] sts_corr_dropped_addr_0; + +wire [STS_PORT_WIDTH_ECC_INTR - 1 : 0] sts_ecc_intr_1; +wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error_1; +wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error_1; +wire [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] sts_corr_dropped_1; +wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count_1; +wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count_1; +wire [STS_PORT_WIDTH_CORR_DROPPED_COUNT - 1 : 0] sts_corr_dropped_count_1; +wire [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] sts_err_addr_1; +wire [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] sts_corr_dropped_addr_1; + +output amm_ready_0; +input amm_read_0; +input amm_write_0; +input [PORT_CTRL_AMM_ADDRESS_WIDTH - 1 : 0] amm_address_0; +output [PORT_CTRL_AMM_RDATA_WIDTH - 1 : 0] amm_readdata_0; +input [PORT_CTRL_AMM_WDATA_WIDTH - 1 : 0] amm_writedata_0; +input [PORT_CTRL_AMM_BCOUNT_WIDTH - 1 : 0] amm_burstcount_0; +input [PORT_CTRL_AMM_BYTEEN_WIDTH - 1 : 0] amm_byteenable_0; +input amm_beginbursttransfer_0; +output amm_readdatavalid_0; + +output amm_ready_1; +input amm_read_1; +input amm_write_1; +input [PORT_CTRL_AMM_ADDRESS_WIDTH - 1 : 0] amm_address_1; +output [PORT_CTRL_AMM_RDATA_WIDTH - 1 : 0] amm_readdata_1; +input [PORT_CTRL_AMM_WDATA_WIDTH - 1 : 0] amm_writedata_1; +input [PORT_CTRL_AMM_BCOUNT_WIDTH - 1 : 0] amm_burstcount_1; +input [PORT_CTRL_AMM_BYTEEN_WIDTH - 1 : 0] amm_byteenable_1; +input amm_beginbursttransfer_1; +output amm_readdatavalid_1; + +output mmr_slave_waitrequest_0; +input [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH - 1 : 0] mmr_slave_address_0; +input mmr_slave_write_0; +input mmr_slave_read_0; +input [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH - 1 : 0] mmr_slave_burstcount_0; +input mmr_slave_beginbursttransfer_0; +input [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH - 1 : 0] mmr_slave_writedata_0; +output [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH - 1 : 0] mmr_slave_readdata_0; +output mmr_slave_readdatavalid_0; + +output mmr_slave_waitrequest_1; +input [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH - 1 : 0] mmr_slave_address_1; +input mmr_slave_write_1; +input mmr_slave_read_1; +input [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH - 1 : 0] mmr_slave_burstcount_1; +input mmr_slave_beginbursttransfer_1; +input [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH - 1 : 0] mmr_slave_writedata_1; +output [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH - 1 : 0] mmr_slave_readdata_1; +output mmr_slave_readdatavalid_1; + +input mmr_master_waitrequest_0; +output [PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH - 1 : 0] mmr_master_address_0; +output mmr_master_write_0; +output mmr_master_read_0; +output [PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH - 1 : 0] mmr_master_burstcount_0; +output mmr_master_beginbursttransfer_0; +output [PORT_CTRL_MMR_MASTER_WDATA_WIDTH - 1 : 0] mmr_master_writedata_0; +input [PORT_CTRL_MMR_MASTER_RDATA_WIDTH - 1 : 0] mmr_master_readdata_0; +input mmr_master_readdatavalid_0; + +input mmr_master_waitrequest_1; +output [PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH - 1 : 0] mmr_master_address_1; +output mmr_master_write_1; +output mmr_master_read_1; +output [PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH - 1 : 0] mmr_master_burstcount_1; +output mmr_master_beginbursttransfer_1; +output [PORT_CTRL_MMR_MASTER_WDATA_WIDTH - 1 : 0] mmr_master_writedata_1; +input [PORT_CTRL_MMR_MASTER_RDATA_WIDTH - 1 : 0] mmr_master_readdata_1; +input mmr_master_readdatavalid_1; + +input ctrl_user_priority_hi_0; +input ctrl_auto_precharge_req_0; + +input ctrl_user_priority_hi_1; +input ctrl_auto_precharge_req_1; + +input ast_cmd_ready_0; +output ast_cmd_valid_0; +output [PORT_CTRL_AST_CMD_DATA_WIDTH - 1 : 0] ast_cmd_data_0; +input ast_wr_ready_0; +output ast_wr_valid_0; +output [PORT_CTRL_AST_WR_DATA_WIDTH - 1 : 0] ast_wr_data_0; +output ast_rd_ready_0; +input ast_rd_valid_0; +input [PORT_CTRL_AST_RD_DATA_WIDTH - 1 : 0] ast_rd_data_0; + +input ast_cmd_ready_1; +output ast_cmd_valid_1; +output [PORT_CTRL_AST_CMD_DATA_WIDTH - 1 : 0] ast_cmd_data_1; +input ast_wr_ready_1; +output ast_wr_valid_1; +output [PORT_CTRL_AST_WR_DATA_WIDTH - 1 : 0] ast_wr_data_1; +output ast_rd_ready_1; +input ast_rd_valid_1; +input [PORT_CTRL_AST_RD_DATA_WIDTH - 1 : 0] ast_rd_data_1; + + +input [PORT_CTRL_ECC_CMD_INFO_WIDTH - 1 : 0] ctrl_ecc_cmd_info_0; +input [PORT_CTRL_ECC_RDATA_ID_WIDTH - 1 : 0] ctrl_ecc_rdata_id_0; +output [PORT_CTRL_ECC_WRITE_INFO_WIDTH - 1 : 0] ctrl_ecc_write_info_0; +input [PORT_CTRL_ECC_READ_INFO_WIDTH - 1 : 0] ctrl_ecc_read_info_0; +input [PORT_CTRL_ECC_WB_POINTER_WIDTH - 1 : 0] ctrl_ecc_wr_pointer_info_0; +input ctrl_ecc_idle_0; +output ctrl_ecc_user_interrupt_0; +output ctrl_ecc_readdataerror_0; + +input [PORT_CTRL_ECC_CMD_INFO_WIDTH - 1 : 0] ctrl_ecc_cmd_info_1; +input [PORT_CTRL_ECC_RDATA_ID_WIDTH - 1 : 0] ctrl_ecc_rdata_id_1; +output [PORT_CTRL_ECC_WRITE_INFO_WIDTH - 1 : 0] ctrl_ecc_write_info_1; +input [PORT_CTRL_ECC_READ_INFO_WIDTH - 1 : 0] ctrl_ecc_read_info_1; +input [PORT_CTRL_ECC_WB_POINTER_WIDTH - 1 : 0] ctrl_ecc_wr_pointer_info_1; +input ctrl_ecc_idle_1; +output ctrl_ecc_user_interrupt_1; +output ctrl_ecc_readdataerror_1; + +assign emif_usr_reset_n = emif_usr_reset_n_in; +assign emif_usr_clk = emif_usr_clk_in; + +assign emif_usr_reset_n_sec = emif_usr_reset_n_sec_in; +assign emif_usr_clk_sec = emif_usr_clk_sec_in; + +generate + + wire [CFG_ECC_BE_WIDTH - 1 : 0] ctrl_ecc_wr_byte_enable_0; + wire [CFG_ECC_DATA_WIDTH -1 : 0] ast_wr_data_without_byteen_0; + wire [34:0] amm_address_padded_0; + wire [7:0] amm_burstcount_padded_0; + wire slave_mmr_ready_0; + + if (PORT_CTRL_AST_WR_DATA_WIDTH == PORT_CTRL_AST_RD_DATA_WIDTH) + assign ast_wr_data_0 = ast_wr_data_without_byteen_0; + else + assign ast_wr_data_0 = {ctrl_ecc_wr_byte_enable_0, ast_wr_data_without_byteen_0}; + + if (PORT_CTRL_AMM_ADDRESS_WIDTH >= 35) begin + assign amm_address_padded_0 = amm_address_0; + end else begin + assign amm_address_padded_0 = {{(35 - PORT_CTRL_AMM_ADDRESS_WIDTH){1'b0}}, amm_address_0}; + end + + if (PORT_CTRL_AMM_BCOUNT_WIDTH >= 8) begin + assign amm_burstcount_padded_0 = amm_burstcount_0; + end else begin + assign amm_burstcount_padded_0 = {{(8 - PORT_CTRL_AMM_BCOUNT_WIDTH){1'b0}}, amm_burstcount_0}; + end + + wire [CFG_LOCAL_CMD_DATA_WIDTH - 1 : 0] slave_cmd_data_wire_0; + + assign slave_cmd_data_wire_0 = {{13{1'b0}}, + 1'b0, + ctrl_auto_precharge_req_0, + ctrl_user_priority_hi_0, + amm_burstcount_padded_0, + amm_address_padded_0, + amm_write_0, + amm_read_0}; + + fmiohmc_ecc_wrapper #( + .CFG_LOCAL_CMD_WIDTH (CFG_LOCAL_CMD_WIDTH), + .CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH), + .CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH), + .CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH), + .CFG_LOCAL_PRI_WIDTH (CFG_LOCAL_PRI_WIDTH), + .CFG_LOCAL_AP_WIDTH (CFG_LOCAL_AP_WIDTH), + .CFG_LOCAL_MC_WIDTH (CFG_LOCAL_MC_WIDTH), + .CFG_CMD_DATA_WIDTH (CFG_LOCAL_CMD_DATA_WIDTH), + .CFG_CMD_INFO_WIDTH (CFG_LOCAL_CMD_INFO_WIDTH), + .CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH), + .CFG_LOCAL_BE_WIDTH (CFG_LOCAL_BE_WIDTH), + .CFG_LOCAL_DATA_INFO_WIDTH (CFG_LOCAL_DATA_INFO_WIDTH), + .CFG_LOCAL_DATA_PTR_WIDTH (CFG_LOCAL_DATA_PTR_WIDTH), + .CFG_ECC_DATA_WIDTH (CFG_ECC_DATA_WIDTH), + .CFG_ECC_BE_WIDTH (CFG_ECC_BE_WIDTH), + .CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH), + .CFG_ECC_MULTIPLE_INSTANCE (CFG_ECC_MULTIPLE_INSTANCE), + .CFG_REGISTER_CMD_PATH (CFG_REGISTER_CMD_PATH), + .CFG_REGISTER_RDATA_PATH (CFG_REGISTER_RDATA_PATH), + .CFG_REGISTER_RDATA_PATH_NUM (REGISTER_RDATA_PATH_NUM), + .CFG_REGISTER_UFI_RDATA_PATH_NUM (REGISTER_UFI_RDATA_PATH_NUM), + .CFG_REGISTER_WDATA_PATH (CFG_REGISTER_WDATA_PATH), + .CFG_REGISTER_WDATA_PATH_NUM (REGISTER_WDATA_PATH_NUM), + .CFG_REGISTER_ST_WDATA_RDY_LAT_PATH (REGISTER_ST_WDATA_RDY_LAT_PATH), + .CFG_REGISTER_ST_RDATA_RDY_LAT_PATH (REGISTER_ST_RDATA_RDY_LAT_PATH), + .CFG_REGISTER_ST_CMD_RDY_LAT_PATH (REGISTER_ST_CMD_RDY_LAT_PATH), + .CORE_CMD_PIPELINE_WDATA (REGISTER_CORE_CMD_PIPELINE_WDATA), + .CFG_MMR_DATA_WIDTH (CFG_MMR_DATA_WIDTH), + .MMR_DRAM_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLE_INSTANCE + CFG_ECC_CODE_WIDTH), + .MMR_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLE_INSTANCE), + .MMR_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH), + .MMR_DATA_RATE ((USER_CLK_RATIO == 4) ? 4'd8 : 4'd4), + .MMR_ECC_IN_PROTOCOL (1), + .MMR_WRPATH_PIPELINE_EN (CFG_MMR_WRPATH_PIPELINE_EN), + .MMR_ENABLE_ECC (ENABLE_ECC), + .MMR_ENABLE_DM ((USE_AVL_BYTEEN) ? 1 : 0), + .MMR_ENABLE_RMW (ENABLE_ECC), + .MMR_ENABLE_AUTO_CORR (ENABLE_ECC_AUTO_CORRECTION), + .MMR_ECC_CODE_OVERWRITE (0), + .MMR_GEN_SBE (0), + .MMR_GEN_DBE (0), + .MMR_ENABLE_INTR (1), + .MMR_MASK_SBE_INTR (0), + .MMR_MASK_DBE_INTR (0), + .MMR_MASK_CORR_DROPPED_INTR (0), + .MMR_MASK_HMI_INTR (0), + .MMR_CLR_INTR (0), + .MMR_CLR_MR_RDATA (0), + .ECC_MMR_READ_LATENCY (ECC_MMR_READ_LATENCY), + .CFG_WRBUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH), + .CFG_PORT_WIDTH_DRAM_DATA_WIDTH (CFG_PORT_WIDTH_DRAM_DATA_WIDTH), + .CFG_PORT_WIDTH_LOCAL_DATA_WIDTH (CFG_PORT_WIDTH_LOCAL_DATA_WIDTH), + .CFG_PORT_WIDTH_ADDR_WIDTH (CFG_PORT_WIDTH_ADDR_WIDTH), + .CFG_PORT_WIDTH_DATA_RATE (CFG_PORT_WIDTH_DATA_RATE), + .CFG_PORT_WIDTH_ECC_IN_PROTOCOL (CFG_PORT_WIDTH_ECC_IN_PROTOCOL), + .CFG_PORT_WIDTH_WRPATH_PIPELINE_EN (CFG_PORT_WIDTH_WRPATH_PIPELINE_EN), + .CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC), + .CFG_PORT_WIDTH_ENABLE_DM (CFG_PORT_WIDTH_ENABLE_DM), + .CFG_PORT_WIDTH_ENABLE_RMW (CFG_PORT_WIDTH_ENABLE_RMW), + .CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR), + .CFG_PORT_WIDTH_ECC_CODE_OVERWRITE (CFG_PORT_WIDTH_ECC_CODE_OVERWRITE), + .CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE), + .CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE), + .CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR), + .CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR), + .CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR), + .CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR), + .CFG_PORT_WIDTH_MASK_HMI_INTR (CFG_PORT_WIDTH_MASK_HMI_INTR), + .CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR), + .CFG_PORT_WIDTH_CLR_MR_RDATA (CFG_PORT_WIDTH_CLR_MR_RDATA), + .STS_PORT_WIDTH_ECC_INTR (STS_PORT_WIDTH_ECC_INTR), + .STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR), + .STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR), + .STS_PORT_WIDTH_CORR_DROPPED (STS_PORT_WIDTH_CORR_DROPPED), + .STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT), + .STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT), + .STS_PORT_WIDTH_CORR_DROPPED_COUNT (STS_PORT_WIDTH_CORR_DROPPED_COUNT), + .STS_PORT_WIDTH_ERR_ADDR (STS_PORT_WIDTH_ERR_ADDR), + .STS_PORT_WIDTH_CORR_DROPPED_ADDR (STS_PORT_WIDTH_CORR_DROPPED_ADDR), + .STS_PORT_WIDTH_MR_DATA (STS_PORT_WIDTH_MR_DATA), + .STS_PORT_WIDTH_MR_DATA_VALID (STS_PORT_WIDTH_MR_DATA_VALID) + ) ecc ( + .ctl_clk (emif_usr_clk_in), + .ctl_reset_n_pre_reg (emif_usr_reset_n_in), + + .slave_cmd_ready (amm_ready_0), + .slave_cmd_data (slave_cmd_data_wire_0), + .slave_cmd_valid (amm_write_0 | amm_read_0), + .slave_wr_data_ready (), + .slave_wr_data_byte_enable ((USE_AVL_BYTEEN) ? amm_byteenable_0 : {(CFG_LOCAL_BE_WIDTH){1'b1}}), + .slave_wr_data (amm_writedata_0), + .slave_wr_data_id ({(CFG_LOCAL_ID_WIDTH){1'b0}}), + .slave_wr_data_valid (amm_write_0), + .slave_rd_data_ready (1'b1), + .slave_rd_data (amm_readdata_0), + .slave_rd_data_id (), + .slave_rd_data_valid (amm_readdatavalid_0), + .slave_rd_data_error (ctrl_ecc_readdataerror_0), + + .master_cmd_ready (ast_cmd_ready_0), + .master_cmd_data (ast_cmd_data_0), + .master_cmd_valid (ast_cmd_valid_0), + .master_cmd_data_combi (), + .master_cmd_valid_combi (), + .master_cmd_info (ctrl_ecc_cmd_info_0), + .master_wr_data_ready (ast_wr_ready_0), + .master_wr_data_byte_enable (ctrl_ecc_wr_byte_enable_0), + .master_wr_data (ast_wr_data_without_byteen_0), + .master_wr_data_id (), + .master_wr_data_info (ctrl_ecc_write_info_0[2:0]), + .master_wr_data_ptr_in (ctrl_ecc_wr_pointer_info_0), + .master_wr_data_ptr_out (ctrl_ecc_write_info_0[PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:3]), + .master_wr_data_valid (ast_wr_valid_0), + .master_rd_data_ready (ast_rd_ready_0), + .master_rd_data (ast_rd_data_0), + .master_rd_data_id (ctrl_ecc_rdata_id_0), + .master_rd_data_info (ctrl_ecc_read_info_0), + .master_rd_data_valid (ast_rd_valid_0), + .master_rd_data_type (1'b0), + + .slave_mmr_ready (slave_mmr_ready_0), + .slave_mmr_address ((CTRL_MMR_EN) ? mmr_slave_address_0 : {(PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH){1'b0}}), + .slave_mmr_write ((CTRL_MMR_EN) ? mmr_slave_write_0 : 1'b0), + .slave_mmr_read ((CTRL_MMR_EN) ? mmr_slave_read_0 : 1'b0), + .slave_mmr_burstcount ((CTRL_MMR_EN) ? mmr_slave_burstcount_0 : {(PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH){1'b0}}), + .slave_mmr_begintransfer ((CTRL_MMR_EN) ? mmr_slave_beginbursttransfer_0 : 1'b0), + .slave_mmr_wr_data ((CTRL_MMR_EN) ? mmr_slave_writedata_0 : {(PORT_CTRL_MMR_SLAVE_WDATA_WIDTH){1'b0}}), + .slave_mmr_rd_data (mmr_slave_readdata_0), + .slave_mmr_rd_data_valid (mmr_slave_readdatavalid_0), + + .master_mmr_ready ((CTRL_MMR_EN) ? ~mmr_master_waitrequest_0 : 1'b1), + .master_mmr_address (mmr_master_address_0), + .master_mmr_write (mmr_master_write_0), + .master_mmr_read (mmr_master_read_0), + .master_mmr_burstcount (mmr_master_burstcount_0), + .master_mmr_begintransfer (mmr_master_beginbursttransfer_0), + .master_mmr_wr_data (mmr_master_writedata_0), + .master_mmr_rd_data ((CTRL_MMR_EN) ? mmr_master_readdata_0 : {(PORT_CTRL_MMR_MASTER_RDATA_WIDTH){1'b0}}), + .master_mmr_rd_data_valid ((CTRL_MMR_EN) ? mmr_master_readdatavalid_0 : 1'b0), + + .sts_ecc_intr (sts_ecc_intr_0), + .sts_sbe_error (sts_sbe_error_0), + .sts_dbe_error (sts_dbe_error_0), + .sts_corr_dropped (sts_corr_dropped_0), + .sts_sbe_count (sts_sbe_count_0), + .sts_dbe_count (sts_dbe_count_0), + .sts_corr_dropped_count (sts_corr_dropped_count_0), + .sts_err_addr (sts_err_addr_0), + .sts_corr_dropped_addr (sts_corr_dropped_addr_0), + + .user_interrupt (ctrl_ecc_user_interrupt_0), + .hmi_interrupt (1'b0) + ); + + assign mmr_slave_waitrequest_0 = ~slave_mmr_ready_0; + + if (DIAG_SIM_MEMORY_PRELOAD_AFT_SYNTH_OVRD) begin : gen_preload + altera_emif_preload_ecc_encoder # + ( + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD), + .DIAG_SIM_MEMORY_PRELOAD_ECC_FILE (DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE), + .DIAG_SIM_MEMORY_PRELOAD_MEM_FILE (DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE), + .DIAG_SIM_MEMORY_PRELOAD_ABPHY_FILE (DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE), + .CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .CTRL_AMM_DATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .MEM_DQ_WIDTH (MEM_DQ_WIDTH), + .USE_AVL_BYTEEN (USE_AVL_BYTEEN), + .CFG_ADDR_ENCODE_ENABLED (CFG_ADDR_ENCODE_ENABLED) + ) preload_inst ( + .emif_usr_clk (emif_usr_clk_in) + ); + end + + if (PHY_PING_PONG_EN) begin : pp_ecc + + wire [CFG_ECC_BE_WIDTH - 1 : 0] ctrl_ecc_wr_byte_enable_1; + wire [CFG_ECC_DATA_WIDTH -1 : 0] ast_wr_data_without_byteen_1; + wire [34:0] amm_address_padded_1; + wire [7:0] amm_burstcount_padded_1; + wire slave_mmr_ready_1; + + if (PORT_CTRL_AST_WR_DATA_WIDTH == PORT_CTRL_AST_RD_DATA_WIDTH) + assign ast_wr_data_1 = ast_wr_data_without_byteen_1; + else + assign ast_wr_data_1 = {ctrl_ecc_wr_byte_enable_1, ast_wr_data_without_byteen_1}; + + if (PORT_CTRL_AMM_ADDRESS_WIDTH >= 35) begin + assign amm_address_padded_1 = amm_address_1; + end else begin + assign amm_address_padded_1 = {{(35 - PORT_CTRL_AMM_ADDRESS_WIDTH){1'b0}}, amm_address_1}; + end + + if (PORT_CTRL_AMM_BCOUNT_WIDTH >= 8) begin + assign amm_burstcount_padded_1 = amm_burstcount_1; + end else begin + assign amm_burstcount_padded_1 = {{(8 - PORT_CTRL_AMM_BCOUNT_WIDTH){1'b0}}, amm_burstcount_1}; + end + + wire [CFG_LOCAL_CMD_DATA_WIDTH - 1 : 0] slave_cmd_data_wire_1; + + assign slave_cmd_data_wire_1 = {{13{1'b0}}, + 1'b0, + ctrl_auto_precharge_req_1, + ctrl_user_priority_hi_1, + amm_burstcount_padded_1, + amm_address_padded_1, + amm_write_1, + amm_read_1}; + + fmiohmc_ecc_wrapper #( + .CFG_LOCAL_CMD_WIDTH (CFG_LOCAL_CMD_WIDTH), + .CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH), + .CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH), + .CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH), + .CFG_LOCAL_PRI_WIDTH (CFG_LOCAL_PRI_WIDTH), + .CFG_LOCAL_AP_WIDTH (CFG_LOCAL_AP_WIDTH), + .CFG_LOCAL_MC_WIDTH (CFG_LOCAL_MC_WIDTH), + .CFG_CMD_DATA_WIDTH (CFG_LOCAL_CMD_DATA_WIDTH), + .CFG_CMD_INFO_WIDTH (CFG_LOCAL_CMD_INFO_WIDTH), + .CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH), + .CFG_LOCAL_BE_WIDTH (CFG_LOCAL_BE_WIDTH), + .CFG_LOCAL_DATA_INFO_WIDTH (CFG_LOCAL_DATA_INFO_WIDTH), + .CFG_LOCAL_DATA_PTR_WIDTH (CFG_LOCAL_DATA_PTR_WIDTH), + .CFG_ECC_DATA_WIDTH (CFG_ECC_DATA_WIDTH), + .CFG_ECC_BE_WIDTH (CFG_ECC_BE_WIDTH), + .CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH), + .CFG_ECC_MULTIPLE_INSTANCE (CFG_ECC_MULTIPLE_INSTANCE), + .CFG_REGISTER_CMD_PATH (CFG_REGISTER_CMD_PATH), + .CFG_REGISTER_RDATA_PATH (CFG_REGISTER_RDATA_PATH), + .CFG_REGISTER_RDATA_PATH_NUM (REGISTER_RDATA_PATH_NUM), + .CFG_REGISTER_UFI_RDATA_PATH_NUM (REGISTER_UFI_RDATA_PATH_NUM), + .CFG_REGISTER_WDATA_PATH (CFG_REGISTER_WDATA_PATH), + .CFG_REGISTER_WDATA_PATH_NUM (REGISTER_WDATA_PATH_NUM), + .CFG_REGISTER_ST_WDATA_RDY_LAT_PATH (REGISTER_ST_WDATA_RDY_LAT_PATH), + .CFG_REGISTER_ST_RDATA_RDY_LAT_PATH (REGISTER_ST_RDATA_RDY_LAT_PATH), + .CFG_REGISTER_ST_CMD_RDY_LAT_PATH (REGISTER_ST_CMD_RDY_LAT_PATH), + .CORE_CMD_PIPELINE_WDATA (REGISTER_CORE_CMD_PIPELINE_WDATA), + .CFG_MMR_DATA_WIDTH (CFG_MMR_DATA_WIDTH), + .MMR_DRAM_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLE_INSTANCE + CFG_ECC_CODE_WIDTH), + .MMR_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLE_INSTANCE), + .MMR_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH), + .MMR_DATA_RATE ((USER_CLK_RATIO == 4) ? 4'd8 : 4'd4), + .MMR_ECC_IN_PROTOCOL (1), + .MMR_WRPATH_PIPELINE_EN (CFG_MMR_WRPATH_PIPELINE_EN), + .MMR_ENABLE_ECC (ENABLE_ECC), + .MMR_ENABLE_DM ((USE_AVL_BYTEEN) ? 1 : 0), + .MMR_ENABLE_RMW (ENABLE_ECC), + .MMR_ENABLE_AUTO_CORR (ENABLE_ECC_AUTO_CORRECTION), + .MMR_ECC_CODE_OVERWRITE (0), + .MMR_GEN_SBE (0), + .MMR_GEN_DBE (0), + .MMR_ENABLE_INTR (1), + .MMR_MASK_SBE_INTR (0), + .MMR_MASK_DBE_INTR (0), + .MMR_MASK_CORR_DROPPED_INTR (0), + .MMR_MASK_HMI_INTR (0), + .MMR_CLR_INTR (0), + .MMR_CLR_MR_RDATA (0), + .CFG_WRBUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH), + .CFG_PORT_WIDTH_DRAM_DATA_WIDTH (CFG_PORT_WIDTH_DRAM_DATA_WIDTH), + .CFG_PORT_WIDTH_LOCAL_DATA_WIDTH (CFG_PORT_WIDTH_LOCAL_DATA_WIDTH), + .CFG_PORT_WIDTH_ADDR_WIDTH (CFG_PORT_WIDTH_ADDR_WIDTH), + .CFG_PORT_WIDTH_DATA_RATE (CFG_PORT_WIDTH_DATA_RATE), + .CFG_PORT_WIDTH_ECC_IN_PROTOCOL (CFG_PORT_WIDTH_ECC_IN_PROTOCOL), + .CFG_PORT_WIDTH_WRPATH_PIPELINE_EN (CFG_PORT_WIDTH_WRPATH_PIPELINE_EN), + .CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC), + .CFG_PORT_WIDTH_ENABLE_DM (CFG_PORT_WIDTH_ENABLE_DM), + .CFG_PORT_WIDTH_ENABLE_RMW (CFG_PORT_WIDTH_ENABLE_RMW), + .CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR), + .CFG_PORT_WIDTH_ECC_CODE_OVERWRITE (CFG_PORT_WIDTH_ECC_CODE_OVERWRITE), + .CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE), + .CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE), + .CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR), + .CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR), + .CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR), + .CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR), + .CFG_PORT_WIDTH_MASK_HMI_INTR (CFG_PORT_WIDTH_MASK_HMI_INTR), + .CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR), + .CFG_PORT_WIDTH_CLR_MR_RDATA (CFG_PORT_WIDTH_CLR_MR_RDATA), + .STS_PORT_WIDTH_ECC_INTR (STS_PORT_WIDTH_ECC_INTR), + .STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR), + .STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR), + .STS_PORT_WIDTH_CORR_DROPPED (STS_PORT_WIDTH_CORR_DROPPED), + .STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT), + .STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT), + .STS_PORT_WIDTH_CORR_DROPPED_COUNT (STS_PORT_WIDTH_CORR_DROPPED_COUNT), + .STS_PORT_WIDTH_ERR_ADDR (STS_PORT_WIDTH_ERR_ADDR), + .STS_PORT_WIDTH_CORR_DROPPED_ADDR (STS_PORT_WIDTH_CORR_DROPPED_ADDR), + .STS_PORT_WIDTH_MR_DATA (STS_PORT_WIDTH_MR_DATA), + .STS_PORT_WIDTH_MR_DATA_VALID (STS_PORT_WIDTH_MR_DATA_VALID) + ) ecc ( + .ctl_clk (emif_usr_clk_sec_in), + .ctl_reset_n_pre_reg (emif_usr_reset_n_sec_in), + + .slave_cmd_ready (amm_ready_1), + .slave_cmd_data (slave_cmd_data_wire_1), + .slave_cmd_valid (amm_write_1 | amm_read_1), + .slave_wr_data_ready (), + .slave_wr_data_byte_enable ((USE_AVL_BYTEEN) ? amm_byteenable_1 : {(CFG_LOCAL_BE_WIDTH){1'b1}}), + .slave_wr_data (amm_writedata_1), + .slave_wr_data_id ({(CFG_LOCAL_ID_WIDTH){1'b0}}), + .slave_wr_data_valid (amm_write_1), + .slave_rd_data_ready (1'b1), + .slave_rd_data (amm_readdata_1), + .slave_rd_data_id (), + .slave_rd_data_valid (amm_readdatavalid_1), + .slave_rd_data_error (ctrl_ecc_readdataerror_1), + + .master_cmd_ready (ast_cmd_ready_1), + .master_cmd_data (ast_cmd_data_1), + .master_cmd_valid (ast_cmd_valid_1), + .master_cmd_data_combi (), + .master_cmd_valid_combi (), + .master_cmd_info (ctrl_ecc_cmd_info_1), + .master_wr_data_ready (ast_wr_ready_1), + .master_wr_data_byte_enable (ctrl_ecc_wr_byte_enable_1), + .master_wr_data (ast_wr_data_without_byteen_1), + .master_wr_data_id (), + .master_wr_data_info (ctrl_ecc_write_info_1[2:0]), + .master_wr_data_ptr_in (ctrl_ecc_wr_pointer_info_1), + .master_wr_data_ptr_out (ctrl_ecc_write_info_1[PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:3]), + .master_wr_data_valid (ast_wr_valid_1), + .master_rd_data_ready (ast_rd_ready_1), + .master_rd_data (ast_rd_data_1), + .master_rd_data_id (ctrl_ecc_rdata_id_1), + .master_rd_data_info (ctrl_ecc_read_info_1), + .master_rd_data_valid (ast_rd_valid_1), + .master_rd_data_type (1'b0), + + .slave_mmr_ready (slave_mmr_ready_1), + .slave_mmr_address ((CTRL_MMR_EN) ? mmr_slave_address_1 : {(PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH){1'b0}}), + .slave_mmr_write ((CTRL_MMR_EN) ? mmr_slave_write_1 : 1'b0), + .slave_mmr_read ((CTRL_MMR_EN) ? mmr_slave_read_1 : 1'b0), + .slave_mmr_burstcount ((CTRL_MMR_EN) ? mmr_slave_burstcount_1 : {(PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH){1'b0}}), + .slave_mmr_begintransfer ((CTRL_MMR_EN) ? mmr_slave_beginbursttransfer_1 : 1'b0), + .slave_mmr_wr_data ((CTRL_MMR_EN) ? mmr_slave_writedata_1 : {(PORT_CTRL_MMR_SLAVE_WDATA_WIDTH){1'b0}}), + .slave_mmr_rd_data (mmr_slave_readdata_1), + .slave_mmr_rd_data_valid (mmr_slave_readdatavalid_1), + + .master_mmr_ready ((CTRL_MMR_EN) ? ~mmr_master_waitrequest_1 : 1'b1), + .master_mmr_address (mmr_master_address_1), + .master_mmr_write (mmr_master_write_1), + .master_mmr_read (mmr_master_read_1), + .master_mmr_burstcount (mmr_master_burstcount_1), + .master_mmr_begintransfer (mmr_master_beginbursttransfer_1), + .master_mmr_wr_data (mmr_master_writedata_1), + .master_mmr_rd_data ((CTRL_MMR_EN) ? mmr_master_readdata_1 : {(PORT_CTRL_MMR_MASTER_RDATA_WIDTH){1'b0}}), + .master_mmr_rd_data_valid ((CTRL_MMR_EN) ? mmr_master_readdatavalid_1 : 1'b0), + + .sts_ecc_intr (sts_ecc_intr_1), + .sts_sbe_error (sts_sbe_error_1), + .sts_dbe_error (sts_dbe_error_1), + .sts_corr_dropped (sts_corr_dropped_1), + .sts_sbe_count (sts_sbe_count_1), + .sts_dbe_count (sts_dbe_count_1), + .sts_corr_dropped_count (sts_corr_dropped_count_1), + .sts_err_addr (sts_err_addr_1), + .sts_corr_dropped_addr (sts_corr_dropped_addr_1), + + .user_interrupt (ctrl_ecc_user_interrupt_1), + .hmi_interrupt (1'b0) + ); + + assign mmr_slave_waitrequest_1 = ~slave_mmr_ready_1; + + if (DIAG_SIM_MEMORY_PRELOAD_AFT_SYNTH_OVRD) begin : gen_preload + altera_emif_preload_ecc_encoder # + ( + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD), + .DIAG_SIM_MEMORY_PRELOAD_ECC_FILE (DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE), + .DIAG_SIM_MEMORY_PRELOAD_MEM_FILE (DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE), + .DIAG_SIM_MEMORY_PRELOAD_ABPHY_FILE (DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE), + .CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .CTRL_AMM_DATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .MEM_DQ_WIDTH (MEM_DQ_WIDTH), + .USE_AVL_BYTEEN (USE_AVL_BYTEEN), + .CFG_ADDR_ENCODE_ENABLED (CFG_ADDR_ENCODE_ENABLED) + ) preload_inst ( + .emif_usr_clk (emif_usr_clk_sec_in) + ); + end + + assign ctrl_ecc_sts_intr = {sts_ecc_intr_0, sts_ecc_intr_1}; + assign ctrl_ecc_sts_sbe_error = {sts_sbe_error_0, sts_sbe_error_1}; + assign ctrl_ecc_sts_dbe_error = {sts_dbe_error_0, sts_dbe_error_1}; + assign ctrl_ecc_sts_corr_dropped = {sts_corr_dropped_0, sts_corr_dropped_1}; + assign ctrl_ecc_sts_sbe_count = {sts_sbe_count_0, sts_sbe_count_1}; + assign ctrl_ecc_sts_dbe_count = {sts_dbe_count_0, sts_dbe_count_1}; + assign ctrl_ecc_sts_corr_dropped_count = {sts_corr_dropped_count_0, sts_corr_dropped_count_1}; + assign ctrl_ecc_sts_err_addr = {sts_err_addr_0, sts_err_addr_1}; + assign ctrl_ecc_sts_corr_dropped_addr = {sts_corr_dropped_addr_0, sts_corr_dropped_addr_1}; + + end else begin : no_pp + assign ctrl_ecc_sts_intr = sts_ecc_intr_0; + assign ctrl_ecc_sts_sbe_error = sts_sbe_error_0; + assign ctrl_ecc_sts_dbe_error = sts_dbe_error_0; + assign ctrl_ecc_sts_corr_dropped = sts_corr_dropped_0; + assign ctrl_ecc_sts_sbe_count = sts_sbe_count_0; + assign ctrl_ecc_sts_dbe_count = sts_dbe_count_0; + assign ctrl_ecc_sts_corr_dropped_count = sts_corr_dropped_count_0; + assign ctrl_ecc_sts_err_addr = sts_err_addr_0; + assign ctrl_ecc_sts_corr_dropped_addr = sts_corr_dropped_addr_0; + + assign amm_readdata_1 = {(PORT_CTRL_AMM_RDATA_WIDTH){1'b0}}; + assign mmr_slave_readdata_1 = {(PORT_CTRL_MMR_SLAVE_RDATA_WIDTH){1'b0}}; + assign mmr_master_burstcount_1 = {(PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH){1'b0}}; + assign mmr_master_writedata_1 = {(PORT_CTRL_MMR_MASTER_WDATA_WIDTH){1'b0}}; + assign mmr_master_address_1 = {(PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH){1'b0}}; + assign ast_cmd_data_1 = {(PORT_CTRL_AST_CMD_DATA_WIDTH){1'b0}}; + assign ast_wr_data_1 = {(PORT_CTRL_AST_WR_DATA_WIDTH){1'b0}}; + assign ctrl_ecc_write_info_1 = {(PORT_CTRL_ECC_WRITE_INFO_WIDTH){1'b0}}; + assign amm_ready_1 = 1'b0; + assign amm_readdatavalid_1 = 1'b0; + assign mmr_slave_waitrequest_1 = 1'b0; + assign mmr_slave_readdatavalid_1 = 1'b0; + assign mmr_master_write_1 = 1'b0; + assign mmr_master_read_1 = 1'b0; + assign mmr_master_beginbursttransfer_1 = 1'b0; + assign ast_cmd_valid_1 = 1'b0; + assign ast_wr_valid_1 = 1'b0; + assign ast_rd_ready_1 = 1'b0; + assign ctrl_ecc_user_interrupt_1 = 1'b0; + assign ctrl_ecc_readdataerror_1 = 1'b0; + + assign sts_ecc_intr_1 = 'b0; + assign sts_sbe_error_1 = 'b0; + assign sts_dbe_error_1 = 'b0; + assign sts_corr_dropped_1 = 'b0; + assign sts_sbe_count_1 = 'b0; + assign sts_dbe_count_1 = 'b0; + assign sts_corr_dropped_count_1 = 'b0; + assign sts_err_addr_1 = 'b0; + assign sts_corr_dropped_addr_1 = 'b0; + end +endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0ECCy5xW0zVEhjVRYnBlvIZ0gabXjoi++UuH0Ry+p4WHjlOAwTfLhMEdy81sX9ucGLj3DSJZHTEcA6olC3FUtERI4eS530tdEhTR/rWvDsC3pVrXe0iMkS0+qpk6Z7xYD0QQeYxmR11sH9fVeH6vxfVgHN1nmO/04w80cvaFdAM4d2JT39YMz3CUHSatbmmgSCTUD0rDMLwW+TB4b6eGv10dSWf3Eaogt1QrDjOksgAPD42DXu/cLSXhpEQ//Ng6tpWvug3Yxe4efOvQXSsj5CwsSNhZjsGV7yljdDMP+OVqm8u5O9mjuIZ+ZNMwsqSUvDVbWoNbhF0WgPqP/HlTyS2NO3GDnxE4XX1kNiBgZF3c42u0s4MQbvDENl6/l+H7NW9CXLIKs9qM0V88YRXEpbM4da3IwZqsUBRzMSJF7G9DUItgq0MSr/1fhHtE0lgMMEuVzukFDnCqruyjIeDW6tAWkj8KZgDLWOxZMUewKSqGrRyxuD2Y4ksE3f6Nf0ikZQxNV8ixOlzKODCvfLwKYV4HJea2EMCwE+XWK57pvYerjTJ/UCnZryNgHG5qDGD2D2pvVTmbeMnU3KlXFt5qCjqEuRxOkpQ6Agtkr1fdynpZTWIRZUr17g4pBKNXSEEtRC54mibOeYSO3I9eQm1h00Ig0gRvyCrsxgW8qhCR1JOyppIN3yxaZzxfkAIgq7p0MAz6CTtEvdv6ifik8az6iSgFVsAf4zRD4TyLSeHtT3wi7fb+a5g1UWTHNRPX6FLYua+fSr9br/Fk1tpXinpIn+Z1" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/altera_emif_preload_ecc_encoder.sv b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/altera_emif_preload_ecc_encoder.sv new file mode 100644 index 0000000000..9c241ab486 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/altera_emif_preload_ecc_encoder.sv @@ -0,0 +1,401 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module is used for simulation memory preloading to append ECC bits +// to the preload data +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns / 1 ps + +module altera_emif_preload_ecc_encoder # +( + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_SIM_MEMORY_PRELOAD_ECC_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_MEM_FILE = "", + parameter DIAG_SIM_MEMORY_PRELOAD_ABPHY_FILE = "", + parameter CTRL_AMM_ADDRESS_WIDTH = 1, + parameter CTRL_AMM_DATA_WIDTH = 1, + parameter MEM_DQ_WIDTH = 1, + + parameter USE_AVL_BYTEEN = 0, + parameter CFG_ADDR_ENCODE_ENABLED = 0, + parameter CFG_PORT_WIDTH_ECC_CODE_OVERWRITE = 1 +) +( + emif_usr_clk, + cfg_ecc_code_overwrite +); + + function automatic integer ceil_log2; + input integer value; + begin + value = value - 1; + for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) + value = value >> 1; + end + endfunction + + localparam OUTPUT_FILE = (DIAG_USE_ABSTRACT_PHY) ? DIAG_SIM_MEMORY_PRELOAD_ABPHY_FILE : ( + DIAG_SIM_MEMORY_PRELOAD_MEM_FILE ); + localparam INT_MEM_DQ_WIDTH = MEM_DQ_WIDTH - 8; + localparam BYTEEN_WIDTH = INT_MEM_DQ_WIDTH / 8; + localparam BYTEEN_W_ECC_WIDTH = MEM_DQ_WIDTH / 8; + localparam NUM_DQ_BURSTS = CTRL_AMM_DATA_WIDTH / INT_MEM_DQ_WIDTH; + localparam ADDRESS_WIDTH = CTRL_AMM_ADDRESS_WIDTH + ceil_log2(NUM_DQ_BURSTS); + + input emif_usr_clk; + input [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0] cfg_ecc_code_overwrite; + + // synthesis translate_off + + logic preload_ready; + logic preload_done; + + function automatic void check_preload_ready (); + integer fd; + string filename; + string line; + + filename = DIAG_SIM_MEMORY_PRELOAD_ECC_FILE; + fd = $fopen(filename, "r"); + if (fd != 0 && $fgets(line, fd)) begin + preload_ready = '1; + end + $fclose(fd); + endfunction + + task automatic encode_ecc_to_addr_data ( + input [ADDRESS_WIDTH - 1:0] address, + input [INT_MEM_DQ_WIDTH - 1:0] data, + output [MEM_DQ_WIDTH - 1:0] ecc_data + ); + + + $fatal(1, "CFG_ADDR_ENCODE_ENABLED = 1 - Feature not supported for simulation memory preload!"); + endtask + + task automatic encode_ecc_to_data ( + input [INT_MEM_DQ_WIDTH - 1:0] data, + output [MEM_DQ_WIDTH - 1:0] ecc_data + ); + logic [63:0] data_input; + logic [71:0] data_output; + + logic [63:0] data_wire; + logic [34:0] parity_01_wire; + logic [17:0] parity_02_wire; + logic [ 8:0] parity_03_wire; + logic [ 3:0] parity_04_wire; + logic [ 1:0] parity_05_wire; + logic [30:0] parity_06_wire; + logic [ 6:0] parity_07_wire; + logic [70:0] parity_final_wire; + logic [71:0] q_wire; + + + if (INT_MEM_DQ_WIDTH < 64) + data_input = {{(64 - INT_MEM_DQ_WIDTH){1'b0}}, data}; + else + data_input = data[63:0]; + + data_wire = data_input; + + parity_01_wire[0] = data_wire[0]; + parity_01_wire[1] = (data_wire[1] ^ parity_01_wire[0]); + parity_01_wire[2] = (data_wire[3] ^ parity_01_wire[1]); + parity_01_wire[3] = (data_wire[4] ^ parity_01_wire[2]); + parity_01_wire[4] = (data_wire[6] ^ parity_01_wire[3]); + parity_01_wire[5] = (data_wire[8] ^ parity_01_wire[4]); + parity_01_wire[6] = (data_wire[10] ^ parity_01_wire[5]); + parity_01_wire[7] = (data_wire[11] ^ parity_01_wire[6]); + parity_01_wire[8] = (data_wire[13] ^ parity_01_wire[7]); + parity_01_wire[9] = (data_wire[15] ^ parity_01_wire[8]); + parity_01_wire[10] = (data_wire[17] ^ parity_01_wire[9]); + parity_01_wire[11] = (data_wire[19] ^ parity_01_wire[10]); + parity_01_wire[12] = (data_wire[21] ^ parity_01_wire[11]); + parity_01_wire[13] = (data_wire[23] ^ parity_01_wire[12]); + parity_01_wire[14] = (data_wire[25] ^ parity_01_wire[13]); + parity_01_wire[15] = (data_wire[26] ^ parity_01_wire[14]); + parity_01_wire[16] = (data_wire[28] ^ parity_01_wire[15]); + parity_01_wire[17] = (data_wire[30] ^ parity_01_wire[16]); + parity_01_wire[18] = (data_wire[32] ^ parity_01_wire[17]); + parity_01_wire[19] = (data_wire[34] ^ parity_01_wire[18]); + parity_01_wire[20] = (data_wire[36] ^ parity_01_wire[19]); + parity_01_wire[21] = (data_wire[38] ^ parity_01_wire[20]); + parity_01_wire[22] = (data_wire[40] ^ parity_01_wire[21]); + parity_01_wire[23] = (data_wire[42] ^ parity_01_wire[22]); + parity_01_wire[24] = (data_wire[44] ^ parity_01_wire[23]); + parity_01_wire[25] = (data_wire[46] ^ parity_01_wire[24]); + parity_01_wire[26] = (data_wire[48] ^ parity_01_wire[25]); + parity_01_wire[27] = (data_wire[50] ^ parity_01_wire[26]); + parity_01_wire[28] = (data_wire[52] ^ parity_01_wire[27]); + parity_01_wire[29] = (data_wire[54] ^ parity_01_wire[28]); + parity_01_wire[30] = (data_wire[56] ^ parity_01_wire[29]); + parity_01_wire[31] = (data_wire[57] ^ parity_01_wire[30]); + parity_01_wire[32] = (data_wire[59] ^ parity_01_wire[31]); + parity_01_wire[33] = (data_wire[61] ^ parity_01_wire[32]); + parity_01_wire[34] = (data_wire[63] ^ parity_01_wire[33]); + + parity_02_wire[0] = data_wire[0]; + parity_02_wire[1] = ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]); + parity_02_wire[2] = ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]); + parity_02_wire[3] = ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]); + parity_02_wire[4] = ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]); + parity_02_wire[5] = ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]); + parity_02_wire[6] = ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]); + parity_02_wire[7] = ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]); + parity_02_wire[8] = ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]); + parity_02_wire[9] = ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]); + parity_02_wire[10] = ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]); + parity_02_wire[11] = ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]); + parity_02_wire[12] = ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]); + parity_02_wire[13] = ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]); + parity_02_wire[14] = ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]); + parity_02_wire[15] = ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]); + parity_02_wire[16] = ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]); + parity_02_wire[17] = ((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]); + + parity_03_wire[0] = ((data_wire[1] ^ data_wire[2]) ^ data_wire[3]); + parity_03_wire[1] = ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]); + parity_03_wire[2] = ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]); + parity_03_wire[3] = ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]); + parity_03_wire[4] = ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]); + parity_03_wire[5] = ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]); + parity_03_wire[6] = ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]); + parity_03_wire[7] = ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]); + parity_03_wire[8] = ((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]); + + parity_04_wire[0] = ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]); + parity_04_wire[1] = ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]); + parity_04_wire[2] = ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]); + parity_04_wire[3] = ((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]); + + parity_05_wire[0] = ((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]); + parity_05_wire[1] = ((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]); + + parity_06_wire[0] = data_wire[26]; + parity_06_wire[1] = (data_wire[27] ^ parity_06_wire[0]); + parity_06_wire[2] = (data_wire[28] ^ parity_06_wire[1]); + parity_06_wire[3] = (data_wire[29] ^ parity_06_wire[2]); + parity_06_wire[4] = (data_wire[30] ^ parity_06_wire[3]); + parity_06_wire[5] = (data_wire[31] ^ parity_06_wire[4]); + parity_06_wire[6] = (data_wire[32] ^ parity_06_wire[5]); + parity_06_wire[7] = (data_wire[33] ^ parity_06_wire[6]); + parity_06_wire[8] = (data_wire[34] ^ parity_06_wire[7]); + parity_06_wire[9] = (data_wire[35] ^ parity_06_wire[8]); + parity_06_wire[10] = (data_wire[36] ^ parity_06_wire[9]); + parity_06_wire[11] = (data_wire[37] ^ parity_06_wire[10]); + parity_06_wire[12] = (data_wire[38] ^ parity_06_wire[11]); + parity_06_wire[13] = (data_wire[39] ^ parity_06_wire[12]); + parity_06_wire[14] = (data_wire[40] ^ parity_06_wire[13]); + parity_06_wire[15] = (data_wire[41] ^ parity_06_wire[14]); + parity_06_wire[16] = (data_wire[42] ^ parity_06_wire[15]); + parity_06_wire[17] = (data_wire[43] ^ parity_06_wire[16]); + parity_06_wire[18] = (data_wire[44] ^ parity_06_wire[17]); + parity_06_wire[19] = (data_wire[45] ^ parity_06_wire[18]); + parity_06_wire[20] = (data_wire[46] ^ parity_06_wire[19]); + parity_06_wire[21] = (data_wire[47] ^ parity_06_wire[20]); + parity_06_wire[22] = (data_wire[48] ^ parity_06_wire[21]); + parity_06_wire[23] = (data_wire[49] ^ parity_06_wire[22]); + parity_06_wire[24] = (data_wire[50] ^ parity_06_wire[23]); + parity_06_wire[25] = (data_wire[51] ^ parity_06_wire[24]); + parity_06_wire[26] = (data_wire[52] ^ parity_06_wire[25]); + parity_06_wire[27] = (data_wire[53] ^ parity_06_wire[26]); + parity_06_wire[28] = (data_wire[54] ^ parity_06_wire[27]); + parity_06_wire[29] = (data_wire[55] ^ parity_06_wire[28]); + parity_06_wire[30] = (data_wire[56] ^ parity_06_wire[29]); + + parity_07_wire[0] = data_wire[57]; + parity_07_wire[1] = (data_wire[58] ^ parity_07_wire[0]); + parity_07_wire[2] = (data_wire[59] ^ parity_07_wire[1]); + parity_07_wire[3] = (data_wire[60] ^ parity_07_wire[2]); + parity_07_wire[4] = (data_wire[61] ^ parity_07_wire[3]); + parity_07_wire[5] = (data_wire[62] ^ parity_07_wire[4]); + parity_07_wire[6] = (data_wire[63] ^ parity_07_wire[5]); + + q_wire[63:0] = data_wire; + q_wire[64] = parity_01_wire[34]; + q_wire[65] = parity_02_wire[17]; + q_wire[66] = parity_03_wire[8]; + q_wire[67] = parity_04_wire[3]; + q_wire[68] = parity_05_wire[1]; + q_wire[69] = parity_06_wire[30]; + q_wire[70] = parity_07_wire[6]; + + parity_final_wire[0] = q_wire[0]; + parity_final_wire[1] = (q_wire[1] ^ parity_final_wire[0]); + parity_final_wire[2] = (q_wire[2] ^ parity_final_wire[1]); + parity_final_wire[3] = (q_wire[3] ^ parity_final_wire[2]); + parity_final_wire[4] = (q_wire[4] ^ parity_final_wire[3]); + parity_final_wire[5] = (q_wire[5] ^ parity_final_wire[4]); + parity_final_wire[6] = (q_wire[6] ^ parity_final_wire[5]); + parity_final_wire[7] = (q_wire[7] ^ parity_final_wire[6]); + parity_final_wire[8] = (q_wire[8] ^ parity_final_wire[7]); + parity_final_wire[9] = (q_wire[9] ^ parity_final_wire[8]); + parity_final_wire[10] = (q_wire[10] ^ parity_final_wire[9]); + parity_final_wire[11] = (q_wire[11] ^ parity_final_wire[10]); + parity_final_wire[12] = (q_wire[12] ^ parity_final_wire[11]); + parity_final_wire[13] = (q_wire[13] ^ parity_final_wire[12]); + parity_final_wire[14] = (q_wire[14] ^ parity_final_wire[13]); + parity_final_wire[15] = (q_wire[15] ^ parity_final_wire[14]); + parity_final_wire[16] = (q_wire[16] ^ parity_final_wire[15]); + parity_final_wire[17] = (q_wire[17] ^ parity_final_wire[16]); + parity_final_wire[18] = (q_wire[18] ^ parity_final_wire[17]); + parity_final_wire[19] = (q_wire[19] ^ parity_final_wire[18]); + parity_final_wire[20] = (q_wire[20] ^ parity_final_wire[19]); + parity_final_wire[21] = (q_wire[21] ^ parity_final_wire[20]); + parity_final_wire[22] = (q_wire[22] ^ parity_final_wire[21]); + parity_final_wire[23] = (q_wire[23] ^ parity_final_wire[22]); + parity_final_wire[24] = (q_wire[24] ^ parity_final_wire[23]); + parity_final_wire[25] = (q_wire[25] ^ parity_final_wire[24]); + parity_final_wire[26] = (q_wire[26] ^ parity_final_wire[25]); + parity_final_wire[27] = (q_wire[27] ^ parity_final_wire[26]); + parity_final_wire[28] = (q_wire[28] ^ parity_final_wire[27]); + parity_final_wire[29] = (q_wire[29] ^ parity_final_wire[28]); + parity_final_wire[30] = (q_wire[30] ^ parity_final_wire[29]); + parity_final_wire[31] = (q_wire[31] ^ parity_final_wire[30]); + parity_final_wire[32] = (q_wire[32] ^ parity_final_wire[31]); + parity_final_wire[33] = (q_wire[33] ^ parity_final_wire[32]); + parity_final_wire[34] = (q_wire[34] ^ parity_final_wire[33]); + parity_final_wire[35] = (q_wire[35] ^ parity_final_wire[34]); + parity_final_wire[36] = (q_wire[36] ^ parity_final_wire[35]); + parity_final_wire[37] = (q_wire[37] ^ parity_final_wire[36]); + parity_final_wire[38] = (q_wire[38] ^ parity_final_wire[37]); + parity_final_wire[39] = (q_wire[39] ^ parity_final_wire[38]); + parity_final_wire[40] = (q_wire[40] ^ parity_final_wire[39]); + parity_final_wire[41] = (q_wire[41] ^ parity_final_wire[40]); + parity_final_wire[42] = (q_wire[42] ^ parity_final_wire[41]); + parity_final_wire[43] = (q_wire[43] ^ parity_final_wire[42]); + parity_final_wire[44] = (q_wire[44] ^ parity_final_wire[43]); + parity_final_wire[45] = (q_wire[45] ^ parity_final_wire[44]); + parity_final_wire[46] = (q_wire[46] ^ parity_final_wire[45]); + parity_final_wire[47] = (q_wire[47] ^ parity_final_wire[46]); + parity_final_wire[48] = (q_wire[48] ^ parity_final_wire[47]); + parity_final_wire[49] = (q_wire[49] ^ parity_final_wire[48]); + parity_final_wire[50] = (q_wire[50] ^ parity_final_wire[49]); + parity_final_wire[51] = (q_wire[51] ^ parity_final_wire[50]); + parity_final_wire[52] = (q_wire[52] ^ parity_final_wire[51]); + parity_final_wire[53] = (q_wire[53] ^ parity_final_wire[52]); + parity_final_wire[54] = (q_wire[54] ^ parity_final_wire[53]); + parity_final_wire[55] = (q_wire[55] ^ parity_final_wire[54]); + parity_final_wire[56] = (q_wire[56] ^ parity_final_wire[55]); + parity_final_wire[57] = (q_wire[57] ^ parity_final_wire[56]); + parity_final_wire[58] = (q_wire[58] ^ parity_final_wire[57]); + parity_final_wire[59] = (q_wire[59] ^ parity_final_wire[58]); + parity_final_wire[60] = (q_wire[60] ^ parity_final_wire[59]); + parity_final_wire[61] = (q_wire[61] ^ parity_final_wire[60]); + parity_final_wire[62] = (q_wire[62] ^ parity_final_wire[61]); + parity_final_wire[63] = (q_wire[63] ^ parity_final_wire[62]); + parity_final_wire[64] = (q_wire[64] ^ parity_final_wire[63]); + parity_final_wire[65] = (q_wire[65] ^ parity_final_wire[64]); + parity_final_wire[66] = (q_wire[66] ^ parity_final_wire[65]); + parity_final_wire[67] = (q_wire[67] ^ parity_final_wire[66]); + parity_final_wire[68] = (q_wire[68] ^ parity_final_wire[67]); + parity_final_wire[69] = (q_wire[69] ^ parity_final_wire[68]); + parity_final_wire[70] = (q_wire[70] ^ parity_final_wire[69]); + + q_wire[71] = parity_final_wire[70]; + + data_output = q_wire; + + if (INT_MEM_DQ_WIDTH < 64) + ecc_data = {data_output[71:64], data_output[INT_MEM_DQ_WIDTH-1:0]}; + else + ecc_data = {data_output[71:64], data_output[63:0]}; + + endtask + + task automatic preload_encode_ecc (); + integer fd_in; + integer fd_out; + string line; + string cs; + string c; + string bg; + string ba; + string row; + string col; + + logic [ADDRESS_WIDTH - 1:0] addr; + logic [INT_MEM_DQ_WIDTH - 1:0] data; + logic [BYTEEN_WIDTH -1:0] byteen; + logic [MEM_DQ_WIDTH - 1:0] data_w_ecc; + logic [BYTEEN_W_ECC_WIDTH -1:0] byteen_w_ecc; + + fd_in = $fopen(DIAG_SIM_MEMORY_PRELOAD_ECC_FILE, "r"); + fd_out = $fopen(OUTPUT_FILE, "w"); + if (fd_in != 0 && fd_out != 0) begin + while ($fgets(line, fd_in)) begin + if ($sscanf(line, "ECC: CS=%s C=%s BG=%s BA=%s ROW=%s COL=%s ADDRESS=%h DATA=%h BYTEENABLE=%h", cs, c, bg, ba, row, col, addr, data, byteen) == 9) begin + + if (byteen != '1) begin + $fatal(1, "Error: When ECC is enabled, byte-enable must be enabled for all bytes in simulation memory preload data. Violation found in file %s at line %s", + DIAG_SIM_MEMORY_PRELOAD_ECC_FILE, line); + end + + if (CFG_ADDR_ENCODE_ENABLED) begin + encode_ecc_to_addr_data(.address(addr), .data(data), .ecc_data(data_w_ecc)); + end else begin + encode_ecc_to_data(.data(data), .ecc_data(data_w_ecc)); + end + byteen_w_ecc = {1'b1, byteen}; + + if (DIAG_USE_ABSTRACT_PHY) begin + $fwrite(fd_out, "ABPHY: CS=%s C=%s BG=%s BA=%s ROW=%s COL=%s DATA=%h BYTEENABLE=%h\n", cs, c, bg, ba, row, col, data_w_ecc, byteen_w_ecc); + end else begin + $fwrite(fd_out, "DDRX: CS=%s C=%s BG=%s BA=%s ROW=%s COL=%s DATA=%h BYTEENABLE=%h\n", cs, c, bg, ba, row, col, data_w_ecc, byteen_w_ecc); + end + end else begin + $error(1, "Error: Missing information in file %s at line: %s", DIAG_SIM_MEMORY_PRELOAD_ECC_FILE, line); + end + end + end else begin + if (fd_in == 0) begin + $error(1, "Error: Unable to open file %s for reading", DIAG_SIM_MEMORY_PRELOAD_ECC_FILE); + end + if (fd_out == 0) begin + $error(1, "Error: Unable to open file %s for writing", OUTPUT_FILE); + end + end + $fflush(fd_out); + $fclose(fd_in); + $fclose(fd_out); + + endtask + + initial begin + integer fd_out; + + preload_ready = '0; + preload_done = '0; + + fd_out = $fopen(OUTPUT_FILE, "w"); + $fclose(fd_out); + end + + always @ (posedge emif_usr_clk) begin + if (!preload_ready) begin + check_preload_ready(); + end else if (!preload_done) begin + preload_encode_ecc(); + preload_done = '1; + end + end + + // synthesis translate_on +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EBMsHfgvgLrHe8UYp8Wl0pTxPxLOCWp7/jsVWNsp+Nt2lMmk4xxD1dSJfR8jxa81tihafHkJYGoi7tgC8DEETB4D8H/dYw2e8ihCN+19edns8PY+pZ5TA0RbFNmWaEK2vrbdNey7MubXJYNWNLKd0nOCTev7W5Up2V0gJn9+E4UHRoVBT7rUE7io/lL0G3UYmTV1mhrNeLkZPVusB612xgNAk0iraplNHhjzYMOEerIDetneUKw+2oLwjNJauKVmdS7jRvhlAWYWC7GQZDpF5D9vNLpk0WtZvsmXjZc7ahajIRlWH547JuDpZ6cM5rzCs5ISNBXGGYHSgF7bkVoHH8dWFMAizSUSZgnM5r6erReXPHajIW+tc4gdFi4H2U8mtqBTKyyp7r5k/moceTYU55tTxHKIC/nAgsj9+4uiN/LH8Z8IZSwXk2UAyod17BSp9sHGCR7qODmjQ1iaLaQTOw5+R0kB0kkHXWHBBm+aeEOT9Quivz8s9aGX/k58XrfU3OOcyoS5wdOVm9hM8HZcDf5ta3VqQpNpTyP0QVxJ8NYnGbmvRyXIbwA4OssXggw8OGW3T1Km2/zDUQUi8Ev4RWkE9pu/NyIoRV6xd/Tu65CWquQVff51lXxwzeBS2BlSIZyHIq653EYRkdEU0E1SChTAiVt/nZhUDbtL1/w03dJJAnCFx/oryRpm/6nwJzBYBzteqJ6eMGtPX38e1fj391ANUB2Xrlk6E8U3jhNqAL8OZT9a6gGiuhWJF/LEmqYE4REs5N/pdl+rz+My2q+z6UE" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc.v new file mode 100644 index 0000000000..6b9db63664 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc.v @@ -0,0 +1,2673 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc # + ( parameter + CFG_LOCAL_CMD_WIDTH = 2, + CFG_LOCAL_ADDR_WIDTH = 35, + CFG_LOCAL_SIZE_WIDTH = 8, + CFG_LOCAL_ID_WIDTH = 13, + CFG_LOCAL_PRI_WIDTH = 1, + CFG_LOCAL_AP_WIDTH = 1, + CFG_LOCAL_MC_WIDTH = 1, + CFG_CMD_DATA_WIDTH = 61, + CFG_CMD_INFO_WIDTH = 3, + CFG_LOCAL_DATA_WIDTH = 81*8, + CFG_LOCAL_BE_WIDTH = 9*8, + CFG_LOCAL_DATA_INFO_WIDTH = 3, + CFG_LOCAL_DATA_PTR_WIDTH = 6*2, + CFG_ECC_DATA_WIDTH = 81*8, + CFG_ECC_BE_WIDTH = 9*8, + CFG_ECC_CODE_WIDTH = 8, + CFG_ECC_MULTIPLE_INSTANCE = 8, + CFG_ECC_IN_PROTOCOL = 0, + + CFG_REGISTER_RDATA_PATH = 0, + CFG_REGISTER_WDATA_PATH = 0, + CFG_REGISTER_WDATA_PATH_NUM = 0, + CFG_REGISTER_UFI_RDATA_PATH_NUM = 0, + CFG_REGISTER_ST_WDATA_RDY_LAT_PATH = 0, + CFG_REGISTER_ST_RDATA_RDY_LAT_PATH = 0, + CFG_REGISTER_ST_CMD_RDY_LAT_PATH = 0, + CORE_CMD_PIPELINE_WDATA = 0, + + CFG_WRBUFFER_ADDR_WIDTH = 5, + CFG_PORT_WIDTH_DRAM_DATA_WIDTH = 8, + CFG_PORT_WIDTH_LOCAL_DATA_WIDTH = 8, + CFG_PORT_WIDTH_ADDR_WIDTH = 6, + CFG_PORT_WIDTH_DATA_RATE = 4, + CFG_PORT_WIDTH_ECC_IN_PROTOCOL = 1, + CFG_PORT_WIDTH_WRPATH_PIPELINE_EN = 1, + CFG_PORT_WIDTH_ENABLE_ECC = 1, + CFG_PORT_WIDTH_ENABLE_DM = 1, + CFG_PORT_WIDTH_ENABLE_RMW = 1, + CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1, + CFG_PORT_WIDTH_ECC_CODE_OVERWRITE = 1, + CFG_PORT_WIDTH_GEN_SBE = 1, + CFG_PORT_WIDTH_GEN_DBE = 1, + CFG_PORT_WIDTH_ENABLE_INTR = 1, + CFG_PORT_WIDTH_MASK_SBE_INTR = 1, + CFG_PORT_WIDTH_MASK_DBE_INTR = 1, + CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1, + CFG_PORT_WIDTH_MASK_HMI_INTR = 1, + CFG_PORT_WIDTH_CLR_INTR = 1, + CFG_PORT_WIDTH_CLR_MR_RDATA = 1, + + STS_PORT_WIDTH_ECC_INTR = 1, + STS_PORT_WIDTH_SBE_ERROR = 1, + STS_PORT_WIDTH_DBE_ERROR = 1, + STS_PORT_WIDTH_CORR_DROPPED = 1, + STS_PORT_WIDTH_SBE_COUNT = 4, + STS_PORT_WIDTH_DBE_COUNT = 4, + STS_PORT_WIDTH_CORR_DROPPED_COUNT = 4, + STS_PORT_WIDTH_ERR_ADDR = 35, + STS_PORT_WIDTH_CORR_DROPPED_ADDR = 35, + STS_PORT_WIDTH_MR_DATA = 81*8, + STS_PORT_WIDTH_MR_DATA_VALID = 1 + ) + ( + ctl_clk, + ctl_reset_n, + + cfg_dram_data_width, + cfg_local_data_width, + cfg_addr_width, + cfg_data_rate, + cfg_ecc_in_protocol, + cfg_wrpath_pipeline_en, + cfg_enable_ecc, + cfg_enable_dm, + cfg_enable_rmw, + cfg_enable_auto_corr, + cfg_ecc_code_overwrite, + cfg_gen_sbe, + cfg_gen_dbe, + cfg_enable_intr, + cfg_mask_sbe_intr, + cfg_mask_dbe_intr, + cfg_mask_corr_dropped_intr, + cfg_mask_hmi_intr, + cfg_clr_intr, + cfg_clr_mr_rdata, + + sts_ecc_intr, + sts_sbe_error, + sts_dbe_error, + sts_corr_dropped, + sts_sbe_count, + sts_dbe_count, + sts_corr_dropped_count, + sts_err_addr, + sts_corr_dropped_addr, + sts_mr_rdata_0, + sts_mr_rdata_1, + sts_mr_rdata_valid, + + sts_corr_dropped_valid, + sts_current_addr, + decoder_output_err_addr, + decoder_output_data_valid, + decoder_output_sbe, + decoder_output_dbe, + decoder_output_data_dbe, + decoder_output_addrerr, + + slave_cmd_ready, + slave_cmd_data, + slave_cmd_valid, + slave_wr_data_ready, + slave_wr_data_byte_enable, + slave_wr_data, + slave_wr_data_id, + slave_wr_data_valid, + slave_rd_data_ready, + slave_rd_data, + slave_rd_data_id, + slave_rd_data_valid, + slave_rd_data_error, + slave_rd_data_type, + + master_cmd_ready, + master_cmd_data, + master_cmd_valid, + master_cmd_data_combi, + master_cmd_valid_combi, + master_cmd_info, + master_wr_data_ready, + master_wr_data_byte_enable, + master_wr_data, + master_wr_data_id, + master_wr_data_info, + master_wr_data_ptr_in, + master_wr_data_ptr_out, + master_wr_data_valid, + master_rd_data_ready, + master_rd_data, + master_rd_data_id, + master_rd_data_info, + master_rd_data_valid, + master_rd_data_type, + + mux_master_cmd_ready, + user_interrupt, + hmi_interrupt, + idle, + push_to_error_address_fifo + ); + +localparam LOG2_CFG_ECC_MULTIPLE_INSTANCE = log2(CFG_ECC_MULTIPLE_INSTANCE); + +localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLE_INSTANCE; +localparam CFG_LOCAL_BE_PER_WORD_WIDTH = CFG_LOCAL_BE_WIDTH / CFG_ECC_MULTIPLE_INSTANCE; +localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLE_INSTANCE; +localparam CFG_ECC_BE_PER_WORD_WIDTH = CFG_ECC_BE_WIDTH / CFG_ECC_MULTIPLE_INSTANCE; + +localparam CFG_ENCODER_ADDR_WIDTH = CFG_LOCAL_ADDR_WIDTH + LOG2_CFG_ECC_MULTIPLE_INSTANCE; +localparam CFG_DECODER_ADDR_WIDTH = CFG_LOCAL_ADDR_WIDTH + LOG2_CFG_ECC_MULTIPLE_INSTANCE; + +localparam CFG_ENCODER_DATA_WIDTH = 81; +localparam CFG_DECODER_DATA_WIDTH = 81; + +localparam PARTIAL_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_LOCAL_BE_WIDTH; +localparam PARTIAL_FIFO_ADDR_WIDTH = CFG_WRBUFFER_ADDR_WIDTH + 1; +localparam PARTIAL_FIFO_REGISTERED_OUTPUT = 1; +localparam PARTIAL_FIFO_SHOWAHEAD = 1; + +localparam WR_ADDR_FIFO_DATA_WIDTH = CFG_LOCAL_ADDR_WIDTH; +localparam WR_ADDR_FIFO_ADDR_WIDTH = CFG_WRBUFFER_ADDR_WIDTH + 1; +localparam WR_ADDR_FIFO_REGISTERED_OUTPUT = 1; +localparam WR_ADDR_FIFO_SHOWAHEAD = 1; + +localparam PTR_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_PTR_WIDTH; +localparam PTR_FIFO_ADDR_WIDTH = CFG_WRBUFFER_ADDR_WIDTH + 1; +localparam PTR_FIFO_REGISTERED_OUTPUT = 1; +localparam PTR_FIFO_SHOWAHEAD = 1; + +localparam CMD_INFO_FIFO_DATA_WIDTH = CFG_CMD_INFO_WIDTH - 1; +localparam CMD_INFO_FIFO_ADDR_WIDTH = CFG_WRBUFFER_ADDR_WIDTH; +localparam CMD_INFO_FIFO_REGISTERED_OUTPUT = 1; +localparam CMD_INFO_FIFO_SHOWAHEAD = 1; + +localparam READ_FIFO_DATA_WIDTH = CFG_LOCAL_ADDR_WIDTH + CFG_LOCAL_SIZE_WIDTH; +localparam READ_FIFO_ADDR_WIDTH = 6 + 1; +localparam READ_FIFO_REGISTERED_OUTPUT = 1; +localparam READ_FIFO_SHOWAHEAD = 1; + +localparam ERROR_FIFO_DATA_WIDTH = CFG_LOCAL_ADDR_WIDTH; +localparam ERROR_FIFO_ADDR_WIDTH = 4; +localparam ERROR_FIFO_REGISTERED_OUTPUT = 1; +localparam ERROR_FIFO_SHOWAHEAD = 1; + +localparam CFG_PENDING_WRITE_DATA_WIDTH = CFG_LOCAL_SIZE_WIDTH; +localparam CFG_PENDING_ERROR_WRITE_DATA_WIDTH = CFG_LOCAL_SIZE_WIDTH; + +localparam NORMAL_WRITE_DATA = 3'b000; +localparam NORMAL_DUMMY_WRITE_DATA = 3'b010; +localparam NORMAL_FULL_WRITE_DATA = 3'b001; +localparam NORMAL_PARTIAL_WRITE_DATA = 3'b011; +localparam MERGED_WRITE_DATA = 3'b100; +localparam MERGED_DUMMY_WRITE_DATA = 3'b110; +localparam MERGED_FULL_WRITE_DATA = 3'b101; +localparam MERGED_PARTIAL_WRITE_DATA = 3'b111; + +localparam NORMAL_READ_DATA = 3'b000; +localparam NORMAL_DUMMY_READ_DATA = 3'b010; +localparam NORMAL_FULL_READ_DATA = 3'b001; +localparam NORMAL_PARTIAL_READ_DATA = 3'b011; + +localparam INFO_DUMMY_WRITE_DATA = 2'b10; +localparam INFO_FULL_WRITE_DATA = 2'b01; +localparam INFO_PARTIAL_WRITE_DATA = 2'b11; + +localparam CFG_INPUT_AST = 1'b0; +localparam CFG_INPUT_AMM = 1'b1; + +localparam CFG_PENDING_DATA_FIFO_WIDTH = 1; +localparam CFG_PENDING_DATA_FIFO_DEPTH = 2 ** CFG_PENDING_DATA_FIFO_WIDTH; + + +localparam WR_FIFO_WIDTH = CFG_LOCAL_BE_WIDTH + CFG_LOCAL_DATA_WIDTH + CFG_LOCAL_ID_WIDTH + 1; + +localparam AVMM_W_CORE_PIPELINE = CFG_ECC_IN_PROTOCOL & CORE_CMD_PIPELINE_WDATA; + +localparam CFG_ADDR_ENCODE_ENABLED = 0; + +input ctl_clk; +input [23:0] ctl_reset_n; + +input [CFG_PORT_WIDTH_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width; +input [CFG_PORT_WIDTH_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width; +input [CFG_PORT_WIDTH_ADDR_WIDTH - 1 : 0] cfg_addr_width; +input [CFG_PORT_WIDTH_DATA_RATE - 1 : 0] cfg_data_rate; +input [CFG_PORT_WIDTH_ECC_IN_PROTOCOL - 1 : 0] cfg_ecc_in_protocol; +input [CFG_PORT_WIDTH_WRPATH_PIPELINE_EN - 1 : 0] cfg_wrpath_pipeline_en; +input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc; +input [CFG_PORT_WIDTH_ENABLE_DM - 1 : 0] cfg_enable_dm; +input [CFG_PORT_WIDTH_ENABLE_RMW - 1 : 0] cfg_enable_rmw; +input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr; +input [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0] cfg_ecc_code_overwrite; +input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe; +input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe; +input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr; +input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr; +input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr; +input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr; +input [CFG_PORT_WIDTH_MASK_HMI_INTR - 1 : 0] cfg_mask_hmi_intr; +input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr; +input [CFG_PORT_WIDTH_CLR_MR_RDATA - 1 : 0] cfg_clr_mr_rdata; + +output [STS_PORT_WIDTH_ECC_INTR - 1 : 0] sts_ecc_intr; +output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error; +output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error; +output [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] sts_corr_dropped; +output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count; +output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count; +output [STS_PORT_WIDTH_CORR_DROPPED_COUNT - 1 : 0] sts_corr_dropped_count; +output [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] sts_err_addr; +output [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] sts_corr_dropped_addr; +output [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_0; +output [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_1; +output [STS_PORT_WIDTH_MR_DATA_VALID - 1 : 0] sts_mr_rdata_valid; + +output sts_corr_dropped_valid; +output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_current_addr; +output [CFG_DECODER_ADDR_WIDTH * CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_err_addr; +output [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_valid; +output [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_sbe; +output [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_dbe; +output [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_dbe; +output [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_addrerr; + + +output slave_cmd_ready; +input [CFG_CMD_DATA_WIDTH - 1 : 0] slave_cmd_data; +input slave_cmd_valid; +output slave_wr_data_ready; +input [CFG_LOCAL_BE_WIDTH - 1 : 0] slave_wr_data_byte_enable; +input [CFG_LOCAL_DATA_WIDTH - 1 : 0] slave_wr_data; +input [CFG_LOCAL_ID_WIDTH - 1 : 0] slave_wr_data_id; +input slave_wr_data_valid; +input slave_rd_data_ready; +output [CFG_LOCAL_DATA_WIDTH - 1 : 0] slave_rd_data; +output [CFG_LOCAL_ID_WIDTH - 1 : 0] slave_rd_data_id; +output slave_rd_data_valid; +output slave_rd_data_error; +output slave_rd_data_type; + +input master_cmd_ready; +output [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data; +output master_cmd_valid; +output [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data_combi; +output master_cmd_valid_combi; +input [CFG_CMD_INFO_WIDTH - 1 : 0] master_cmd_info; +input master_wr_data_ready; +output [CFG_ECC_BE_WIDTH - 1 : 0] master_wr_data_byte_enable; +output [CFG_ECC_DATA_WIDTH - 1 : 0] master_wr_data; +output [CFG_LOCAL_ID_WIDTH - 1 : 0] master_wr_data_id; +output [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info; +input [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] master_wr_data_ptr_in; +output [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] master_wr_data_ptr_out; +output master_wr_data_valid; +output master_rd_data_ready; +input [CFG_ECC_DATA_WIDTH - 1 : 0] master_rd_data; +input [CFG_LOCAL_ID_WIDTH - 1 : 0] master_rd_data_id; +input [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_rd_data_info; +input master_rd_data_valid; +input master_rd_data_type; + +output mux_master_cmd_ready; +output user_interrupt; +input hmi_interrupt; +output idle; +output push_to_error_address_fifo; + + + + wire push_slave_fifo_data; + wire pop_slave_fifo_data; + wire [CFG_CMD_DATA_WIDTH + CFG_LOCAL_DATA_WIDTH + CFG_LOCAL_BE_WIDTH - 1 : 0] slave_data_fifo_out; + wire slave_data_fifo_empty_n; + + reg slave_cmd_ready; + reg slave_wr_data_ready; + reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] slave_rd_data; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] slave_rd_data_id; + reg slave_rd_data_valid; + reg slave_rd_data_error; + reg slave_rd_data_type; + + reg [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data; + reg master_cmd_valid; + reg [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data_combi; + reg master_cmd_valid_combi; + reg [CFG_ECC_BE_WIDTH - 1 : 0] master_wr_data_byte_enable; + reg [CFG_ECC_BE_WIDTH - 1 : 0] master_wr_data_byte_enable_ori; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] master_wr_data; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] master_wr_addr; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] master_wr_addr_r; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] master_wr_data_id; + wire [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] mux_master_wr_data_info; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r1; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r2; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r3; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r4; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r5; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r6; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r7; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r8; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r9; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info_r10; + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] master_wr_data_ptr_out; + reg master_wr_data_valid; + reg master_rd_data_ready; + + reg user_interrupt; + wire idle; + + reg [STS_PORT_WIDTH_ECC_INTR - 1 : 0] sts_ecc_intr; + reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error; + reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error; + reg [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] sts_corr_dropped; + reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count; + reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count; + reg [STS_PORT_WIDTH_CORR_DROPPED_COUNT - 1 : 0] sts_corr_dropped_count; + reg [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] sts_err_addr; + reg [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] sts_corr_dropped_addr; + reg [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_0; + reg [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_1; + reg [STS_PORT_WIDTH_MR_DATA_VALID - 1 : 0] sts_mr_rdata_valid; + wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_current_addr; + + reg internal_master_cmd_ready; + reg int_ast_master_cmd_ready; + + wire int_master_cmd_ready; + wire [CFG_CMD_INFO_WIDTH - 1 : 0] int_master_cmd_info; + reg [CFG_CMD_INFO_WIDTH - 1 : 0] int_master_cmd_info_r1; + wire int_master_wr_data_ready; + wire [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] int_master_wr_data_ptr_in; + wire [CFG_ECC_DATA_WIDTH - 1 : 0] int_master_rd_data; + wire [CFG_LOCAL_ID_WIDTH - 1 : 0] int_master_rd_data_id; + wire [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] int_master_rd_data_info; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] int_master_rd_data_info_r; + wire int_master_rd_data_valid; + reg int_master_rd_data_valid_r; + + wire internal_master_rd_data_ready; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] internal_master_rd_data; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] internal_master_rd_data_id; + (* altera_attribute = {"-name MAX_FANOUT 1"}*) reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] internal_master_rd_data_info; + (* altera_attribute = {"-name MAX_FANOUT 1"}*) reg internal_master_rd_data_valid; + reg internal_master_rd_data_type; + + wire [CFG_CMD_DATA_WIDTH - 1 : 0] int_slave_cmd_data; + wire int_slave_cmd_valid; + reg int_slave_cmd_ready; + wire [CFG_LOCAL_BE_WIDTH - 1 : 0] int_slave_wr_data_byte_enable; + wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_slave_wr_data; + wire [CFG_LOCAL_ID_WIDTH - 1 : 0] int_slave_wr_data_id; + wire int_slave_wr_data_valid; + wire int_slave_rd_data_ready; + + wire int_slave_cmd_wr; + wire int_slave_cmd_rd; + wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_slave_cmd_addr; + wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] int_slave_cmd_size; + wire [CFG_LOCAL_ID_WIDTH - 1 : 0] int_slave_cmd_id; + wire int_slave_cmd_priority; + wire int_slave_cmd_auto_precharge; + wire int_slave_cmd_multicast; + + reg [CFG_LOCAL_BE_WIDTH - 1 : 0] int_slave_wr_data_byte_enable_ones; + reg [CFG_LOCAL_BE_WIDTH - 1 : 0] int_slave_wr_data_byte_enable_zeros; + + wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] amm_cmd_size; + wire amm_cmd_wr; + wire amm_cmd_rd; + wire ast_cmd_ready; + wire ast_wr_data_ready; + + wire amm_ready; + wire ast_cmd_valid; + wire ast_wr_data_valid; + + reg int_partial_write_detected; + reg int_partial_write_be_all_zeros; + reg int_partial_write_be_all_ones; + + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] partial_write_detected; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] partial_write_be_all_zeros; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] partial_write_be_all_ones; + reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] partial_write_data; + reg [CFG_LOCAL_BE_WIDTH - 1 : 0] partial_write_data_byte_enable; + reg [CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] partial_write_ecc_code; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] partial_write_ecc_code_overwrite; + + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] partial_write_addr; + + reg partial_read_data_returned_combi_early; + reg empty_read_data_returned_combi_early; + reg normal_read_data_returned_combi_early; + + reg partial_read_data_returned_combi; + reg empty_read_data_returned_combi; + reg normal_read_data_returned_combi; + reg mpr_read_data_returned_combi; + + reg mpr_read_data_returned_valid; + + (* altera_attribute = {"-name MAX_FANOUT 32"}*) reg partial_read_data_returned; + reg empty_read_data_returned; + reg normal_read_data_returned; + + reg prolong_write_back_data_fifo_empty_combi; + + reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] merge_write_data; + + reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] encoder_input_data; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] encoder_input_addr; + reg [CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] encoder_input_ecc_code; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] encoder_input_ecc_code_overwrite; + reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] encoder_input_data_r; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] encoder_input_addr_r; + reg [CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] encoder_input_ecc_code_r; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] encoder_input_ecc_code_overwrite_r; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_input_data; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] decoder_input_addr; + reg decoder_input_data_valid; + + reg [CFG_ECC_BE_WIDTH - 1 : 0] encoder_output_data_byte_enable_combi; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] encoder_output_data_id_combi; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] encoder_output_data_info_combi; + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] encoder_output_data_ptr_combi; + reg encoder_output_data_valid_combi; + + reg [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_output_data; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] encoder_output_addr; + reg [CFG_ECC_BE_WIDTH - 1 : 0] encoder_output_data_byte_enable; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] encoder_output_data_id; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] encoder_output_data_info; + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] encoder_output_data_ptr; + reg encoder_output_data_valid; + + reg pending_data_not_empty; + reg [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0] pending_data_valid_update; + reg [CFG_PENDING_DATA_FIFO_WIDTH - 1 : 0] pending_data_valid_wr_ptr_combi; + reg [CFG_PENDING_DATA_FIFO_WIDTH - 1 : 0] pending_data_valid_rd_ptr_combi; + reg [CFG_PENDING_DATA_FIFO_WIDTH - 1 : 0] pending_data_valid_wr_ptr; + reg [CFG_PENDING_DATA_FIFO_WIDTH - 1 : 0] pending_data_valid_rd_ptr; + reg [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0] pending_data_valid; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] pending_data [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] pending_addr [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + reg [CFG_ECC_BE_WIDTH - 1 : 0] pending_data_byte_enable [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + reg [CFG_ECC_BE_WIDTH - 1 : 0] pending_data_byte_enable_ori [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] pending_data_id [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] pending_data_info [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] pending_data_ptr [CFG_PENDING_DATA_FIFO_DEPTH - 1 : 0]; + + reg load_pending_data; + + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] int_wr_data_info; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] wr_data_info; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] wr_data_info_r; + + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] int_wr_data_ptr; + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] wr_data_ptr; + + wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] int_encoder_input_data_combi [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_ENCODER_ADDR_WIDTH - 1 : 0] int_encoder_input_addr_combi [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_ECC_CODE_WIDTH - 1 : 0] int_encoder_input_ecc_code_combi [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_encoder_input_ecc_code_overwrite_combi [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg [CFG_ECC_BE_WIDTH - 1 : 0] int_encoder_output_data_byte_enable_combi; + reg [CFG_ENCODER_DATA_WIDTH - 1 : 0] int_encoder_input_data [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg [CFG_ENCODER_ADDR_WIDTH - 1 : 0] int_encoder_input_addr [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_encoder_input_ecc_code [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg int_encoder_input_ecc_code_overwrite [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] int_encoder_output_data [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg [CFG_ECC_BE_WIDTH - 1 : 0] int_encoder_output_data_byte_enable; + + wire [CFG_DECODER_DATA_WIDTH - 1 : 0] int_decoder_input_data [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_DECODER_ADDR_WIDTH - 1 : 0] int_decoder_input_addr [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_input_data_valid [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_DECODER_DATA_WIDTH - 1 : 0] int_decoder_output_data [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_output_data_valid [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_ECC_CODE_WIDTH - 1 : 0] int_decoder_output_ecc_code [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_output_err_corrected [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_output_err_detected [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_output_err_fatal [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_output_err_sbe [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire int_decoder_output_err_addr_detected [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + wire [CFG_DECODER_ADDR_WIDTH - 1 : 0] int_decoder_output_err_addr [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg int_decoder_output_sbe [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + reg int_decoder_output_dbe [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]; + + reg [CFG_DECODER_ADDR_WIDTH *CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_err_addr; + + wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] decoder_output_data_combi; + wire [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_valid_combi; + wire [CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_ecc_code_combi; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] decoder_output_data_id_combi; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_sbe_combi; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_dbe_combi; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_dbe_combi; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_dbe; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_addrerr_combi; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_addrerr; + reg decoder_output_rd_data_type_combi; + reg decoder_output_rd_data_type; + + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_valid_combi_r; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_sbe_combi_r; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_dbe_combi_r; + + reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] decoder_output_data; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] decoder_output_addr; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_data_valid; + reg [CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_ecc_code; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] decoder_output_data_id; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_sbe; + reg [CFG_ECC_MULTIPLE_INSTANCE - 1 : 0] decoder_output_dbe; + + wire partial_wdata_fifo_wr; + wire [PARTIAL_FIFO_DATA_WIDTH - 1 : 0] partial_wdata_fifo_wr_data; + wire partial_wdata_fifo_rd; + wire [PARTIAL_FIFO_DATA_WIDTH - 1 : 0] partial_wdata_fifo_rd_data; + wire partial_wdata_fifo_rd_data_valid; + wire partial_wdata_fifo_empty; + + wire initial_wr_addr_fifo_wr; + wire [WR_ADDR_FIFO_DATA_WIDTH - 1 : 0] initial_wr_addr_fifo_wr_data; + wire initial_wr_addr_fifo_rd; + wire [WR_ADDR_FIFO_DATA_WIDTH - 1 : 0] initial_wr_addr_fifo_rd_data; + wire initial_wr_addr_fifo_rd_data_valid; + wire initial_wr_addr_fifo_empty; + wire initial_wr_addr_fifo_full; + + wire wr_addr_fifo_wr; + wire [WR_ADDR_FIFO_DATA_WIDTH - 1 : 0] wr_addr_fifo_wr_data; + wire wr_addr_fifo_rd; + wire [WR_ADDR_FIFO_DATA_WIDTH - 1 : 0] wr_addr_fifo_rd_data; + wire wr_addr_fifo_rd_data_valid; + wire wr_addr_fifo_empty; + wire wr_addr_fifo_full; + + wire initial_pointer_fifo_wr; + wire [PTR_FIFO_DATA_WIDTH + 2 - 1 : 0] initial_pointer_fifo_wr_data; + wire initial_pointer_fifo_rd; + wire [PTR_FIFO_DATA_WIDTH + 2 - 1 : 0] initial_pointer_fifo_rd_data; + wire initial_pointer_fifo_rd_data_valid; + wire initial_pointer_fifo_empty; + wire initial_pointer_fifo_full; + + wire mux_push_to_initial_pointer_fifo; + reg push_to_initial_pointer_fifo; + reg push_to_initial_pointer_fifo_r1; + reg push_to_initial_pointer_fifo_r2; + reg push_to_initial_pointer_fifo_r3; + reg push_to_initial_pointer_fifo_r4; + reg push_to_initial_pointer_fifo_r5; + reg push_to_initial_pointer_fifo_r6; + reg push_to_initial_pointer_fifo_r7; + reg push_to_initial_pointer_fifo_r8; + reg push_to_initial_pointer_fifo_r9; + + reg [PTR_FIFO_DATA_WIDTH - 1 : 0] int_pointer_fifo_rd_data; + reg [WR_ADDR_FIFO_DATA_WIDTH - 1 : 0] int_wr_addr_fifo_rd_data; + + wire pointer_fifo_wr; + wire [PTR_FIFO_DATA_WIDTH - 1 : 0] pointer_fifo_wr_data; + wire pointer_fifo_rd; + wire [PTR_FIFO_DATA_WIDTH - 1 : 0] pointer_fifo_rd_data; + wire pointer_fifo_rd_data_valid; + wire pointer_fifo_empty; + wire pointer_fifo_full; + + wire cmd_info_fifo_wr; + wire [CMD_INFO_FIFO_DATA_WIDTH - 1 : 0] cmd_info_fifo_wr_data; + wire cmd_info_fifo_rd; + wire [CMD_INFO_FIFO_DATA_WIDTH - 1 : 0] cmd_info_fifo_rd_data; + wire cmd_info_fifo_rd_data_valid; + wire cmd_info_fifo_empty; + wire cmd_info_fifo_full; + + wire read_address_fifo_wr; + wire [READ_FIFO_DATA_WIDTH - 1 : 0] read_address_fifo_wr_data; + wire read_address_fifo_rd; + wire [READ_FIFO_DATA_WIDTH - 1 : 0] read_address_fifo_rd_data; + wire read_address_fifo_rd_data_valid; + wire read_address_fifo_empty; + wire read_address_fifo_full; + + wire error_address_fifo_wr; + wire [ERROR_FIFO_DATA_WIDTH - 1 : 0] error_address_fifo_wr_data; + wire error_address_fifo_rd; + wire [ERROR_FIFO_DATA_WIDTH - 1 : 0] error_address_fifo_rd_data; + wire error_address_fifo_rd_data_valid; + wire error_address_fifo_empty; + wire error_address_fifo_full; + + wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] read_address_fifo_addr; + wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] read_address_fifo_size; + + wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] error_address_fifo_addr; + + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] current_addr; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_current_addr; + + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] error_cmd_addr; + reg [35 - 1 : 0] error_cmd_addr_padded; + wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] error_cmd_size; + reg [8 - 1 : 0] error_cmd_size_padded; + reg [CFG_LOCAL_SIZE_WIDTH - 1 : 0] error_cmd_size_decrement; + reg error_cmd_valid; + + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] error_wr_addr; + + reg error_wr_data_valid; + + reg [CFG_CMD_DATA_WIDTH - 1 : 0] int_cmd_data; + reg int_cmd_valid; + reg [CFG_CMD_DATA_WIDTH - 1 : 0] prev_int_cmd_data; + reg prev_int_cmd_valid; + + reg [CFG_CMD_DATA_WIDTH - 1 : 0] int_master_cmd_data; + reg int_master_cmd_valid; + reg [CFG_CMD_DATA_WIDTH - 1 : 0] int_master_cmd_data_combi; + reg int_master_cmd_valid_combi; + +(* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) reg [CFG_ECC_BE_WIDTH - 1 : 0] int_master_wr_data_byte_enable; + reg [CFG_ECC_BE_WIDTH - 1 : 0] int_master_wr_data_byte_enable_ori; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_master_wr_data; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_master_wr_addr; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] int_master_wr_data_id; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] int_master_wr_data_info; + reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] int_master_wr_data_ptr_out; + reg int_master_wr_data_valid; + + reg pop_from_read_address_fifo; + reg last_read_data; + reg [CFG_LOCAL_SIZE_WIDTH - 1 : 0] read_size_counter; + + reg [CFG_PENDING_WRITE_DATA_WIDTH - 1 : 0] pending_write_data_counter; + reg pending_write_data_counter_underflow; + reg pending_write_data_counter_is_zero; + reg pending_write_data_counter_is_one; + reg data_before_write_command; + reg push_to_error_address_fifo; + reg pop_from_error_address_fifo; + reg issuing_dummy_write_command; + reg issuing_dummy_write_data; + reg issuing_dummy_write_data_non_gated; + + reg load_rmw_write_data; + reg load_rmw_busy; + reg load_rmw_busy_non_gated; + reg loading_rmw_data; + + reg int_load_rmw_write_data; + reg int_load_rmw_write_data_r; + reg int_load_rmw_busy; + reg int_load_rmw_busy_non_gated; + reg int_load_rmw_busy_r; + + reg [1 : 0] int_error_inject; + + wire mux_master_cmd_ready; + reg master_cmd_ready_r1; + reg master_cmd_ready_r2; + reg master_cmd_ready_r3; + reg master_cmd_ready_r4; + reg master_cmd_ready_r5; + reg master_cmd_ready_r6; + reg master_cmd_ready_r7; + reg master_cmd_ready_r8; + + wire mux_slave_cmd_ready; + reg slave_cmd_ready_r1; + reg slave_cmd_ready_r2; + reg slave_cmd_ready_r3; + reg slave_cmd_ready_r4; + reg slave_cmd_ready_r5; + reg slave_cmd_ready_r6; + reg slave_cmd_ready_r7; + reg slave_cmd_ready_r8; + + wire mux_slave_wr_data_ready; + reg int_slave_wr_data_ready; + reg slave_wr_data_ready_r1; + reg slave_wr_data_ready_r2; + reg slave_wr_data_ready_r3; + reg slave_wr_data_ready_r4; + reg slave_wr_data_ready_r5; + reg slave_wr_data_ready_r6; + reg slave_wr_data_ready_r7; + reg slave_wr_data_ready_r8; + + wire mux_slave_rd_data_ready; + reg slave_rd_data_ready_r1; + reg slave_rd_data_ready_r2; + reg slave_rd_data_ready_r3; + reg slave_rd_data_ready_r4; + + wire is_ast; + + wire one = 1'b1; + wire zero = 1'b0; + + wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] internal_slave_wr_data; + wire [CFG_LOCAL_ID_WIDTH - 1 : 0] internal_slave_wr_data_id; + wire [CFG_LOCAL_BE_WIDTH - 1 : 0] internal_slave_wr_data_byte_enable; + wire internal_slave_wr_data_valid; + + wire [WR_FIFO_WIDTH - 1 : 0] wr_fifo_wr_data; + wire wr_fifo_wr_ready; + wire wr_fifo_wr_valid; + wire [WR_FIFO_WIDTH - 1 : 0] wr_fifo_rd_data; + wire wr_fifo_rd_ready; + wire wr_fifo_rd_valid; + + wire [CFG_CMD_DATA_WIDTH - 1 : 0] internal_slave_cmd_data; + wire internal_slave_cmd_valid; + + wire [CFG_CMD_DATA_WIDTH - 1 : 0] cmd_fifo_rd_data; + wire cmd_fifo_wr_ready; + wire cmd_fifo_rd_valid; + wire [CFG_CMD_DATA_WIDTH - 1 : 0] cmd_fifo_cmd_data; + wire cmd_fifo_rd_ready; + wire cmd_fifo_cmd_valid; + + genvar i; + genvar j; + + assign int_slave_cmd_rd = int_slave_cmd_data[0]; + assign int_slave_cmd_wr = int_slave_cmd_data[1]; + assign int_slave_cmd_addr = int_slave_cmd_data[(2+CFG_LOCAL_ADDR_WIDTH-1):2]; + assign int_slave_cmd_size = int_slave_cmd_data[(37+CFG_LOCAL_SIZE_WIDTH-1):37]; + assign int_slave_cmd_priority = int_slave_cmd_data[45]; + assign int_slave_cmd_auto_precharge = int_slave_cmd_data[46]; + assign int_slave_cmd_multicast = int_slave_cmd_data[47]; + assign int_slave_cmd_id = int_slave_cmd_data[(48+CFG_LOCAL_ID_WIDTH-1):48]; + + assign is_ast = (cfg_ecc_in_protocol == CFG_INPUT_AST)? 1'b1 : 1'b0; + + always @ (*) + begin + int_slave_cmd_ready = int_master_cmd_ready; + slave_cmd_ready = int_master_cmd_ready & cmd_fifo_wr_ready; + int_slave_wr_data_ready = int_master_wr_data_ready & ~load_rmw_busy_non_gated & ~pending_data_not_empty; + slave_wr_data_ready = int_master_wr_data_ready & ~load_rmw_busy_non_gated & ~pending_data_not_empty & wr_fifo_wr_ready; + slave_rd_data = decoder_output_data; + slave_rd_data_id = decoder_output_data_id; + slave_rd_data_valid = |decoder_output_data_valid | mpr_read_data_returned_valid; + slave_rd_data_error = (cfg_enable_ecc) ? |decoder_output_dbe : 1'b0; + slave_rd_data_type = decoder_output_rd_data_type; + end + + always @ (*) + begin + master_cmd_data = int_master_cmd_data; + master_cmd_valid = int_master_cmd_valid; + master_cmd_data_combi = int_master_cmd_data_combi; + master_cmd_valid_combi = int_master_cmd_valid_combi; + master_wr_data_byte_enable = int_master_wr_data_byte_enable; + master_wr_data_byte_enable_ori = int_master_wr_data_byte_enable_ori; + master_wr_data = int_master_wr_data; + master_wr_addr = int_master_wr_addr; + master_wr_data_id = int_master_wr_data_id; + master_wr_data_info = int_master_wr_data_info; + master_wr_data_ptr_out = int_master_wr_data_ptr_out; + master_wr_data_valid = int_master_wr_data_valid & (int_master_wr_data_ready | int_master_wr_data_info[2]); + master_rd_data_ready = internal_master_rd_data_ready; + end + + always @ (posedge ctl_clk) + begin + master_wr_addr_r <= master_wr_addr; + end + + always @ (posedge ctl_clk) + begin + loading_rmw_data <= ~load_rmw_busy | issuing_dummy_write_data; + end + + generate + for (i = 0; i < CFG_PENDING_DATA_FIFO_DEPTH; i = i + 1) + begin : pending_loop + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[0]) + begin + pending_data_valid[i] <= 1'b0; + end + else + begin + if (encoder_output_data_valid && pending_data_valid_wr_ptr == i && ~encoder_output_data_info[2]) + begin + pending_data_valid[i] <= 1'b1; + end + else if (load_pending_data && pending_data_valid_rd_ptr == i) + begin + pending_data_valid[i] <= 1'b0; + end + end + end + + always @ (posedge ctl_clk) + begin + if (encoder_output_data_valid && pending_data_valid_wr_ptr == i && ~encoder_output_data_info[2]) + begin + pending_data_byte_enable [i] <= encoder_output_data_byte_enable; + pending_data_byte_enable_ori [i] <= int_encoder_output_data_byte_enable; + pending_data [i] <= encoder_output_data; + pending_addr [i] <= encoder_output_addr; + pending_data_id [i] <= encoder_output_data_id; + pending_data_info [i] <= encoder_output_data_info; + pending_data_ptr [i] <= encoder_output_data_ptr; + end + end + + always @ (*) + begin + if (load_pending_data && pending_data_valid_rd_ptr == i) + begin + pending_data_valid_update [i] = 1'b0; + end + else + begin + pending_data_valid_update [i] = pending_data_valid [i]; + end + end + end + + always @ (*) + begin + pending_data_valid_wr_ptr_combi = pending_data_valid_wr_ptr; + pending_data_valid_rd_ptr_combi = pending_data_valid_rd_ptr; + + if (encoder_output_data_valid && ~encoder_output_data_info[2]) + begin + pending_data_valid_wr_ptr_combi = pending_data_valid_wr_ptr + 1'b1; + end + + if (load_pending_data) + begin + pending_data_valid_rd_ptr_combi = pending_data_valid_rd_ptr + 1'b1; + end + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[1]) + begin + pending_data_valid_wr_ptr <= 1'b0; + pending_data_valid_rd_ptr <= 1'b0; + end + else + begin + pending_data_valid_wr_ptr <= pending_data_valid_wr_ptr_combi; + pending_data_valid_rd_ptr <= pending_data_valid_rd_ptr_combi; + end + end + + always @ (*) + begin + pending_data_not_empty = |pending_data_valid_update; + end + + always @ (*) + begin + load_pending_data = int_master_wr_data_ready && ~master_wr_data_info[2] && master_wr_data_valid && |pending_data_valid; + end + + always @ (posedge ctl_clk) + begin + if ((int_master_wr_data_ready && loading_rmw_data && ~pending_data_not_empty) || encoder_output_data_info[2]) + begin + int_master_wr_data_byte_enable <= encoder_output_data_byte_enable; + int_master_wr_data_byte_enable_ori <= int_encoder_output_data_byte_enable; + int_master_wr_data <= encoder_output_data; + int_master_wr_addr <= encoder_output_addr; + int_master_wr_data_id <= encoder_output_data_id; + int_master_wr_data_info <= encoder_output_data_info; + int_master_wr_data_ptr_out <= encoder_output_data_ptr; + int_master_wr_data_valid <= encoder_output_data_valid; + end + else if (!(int_master_wr_data_ready && loading_rmw_data && ~pending_data_not_empty)) + begin + int_master_wr_data_byte_enable <= pending_data_byte_enable [pending_data_valid_rd_ptr_combi]; + int_master_wr_data_byte_enable_ori <= pending_data_byte_enable_ori [pending_data_valid_rd_ptr_combi]; + int_master_wr_data <= pending_data [pending_data_valid_rd_ptr_combi]; + int_master_wr_addr <= pending_addr [pending_data_valid_rd_ptr_combi]; + int_master_wr_data_id <= pending_data_id [pending_data_valid_rd_ptr_combi]; + int_master_wr_data_info <= pending_data_info [pending_data_valid_rd_ptr_combi]; + int_master_wr_data_ptr_out <= pending_data_ptr [pending_data_valid_rd_ptr_combi]; + int_master_wr_data_valid <= pending_data_valid [pending_data_valid_rd_ptr_combi]; + end + end + endgenerate + + always @ (*) + begin + if (mux_master_cmd_ready) + begin + int_master_cmd_data_combi = (internal_master_cmd_ready) ? int_cmd_data : prev_int_cmd_data; + int_master_cmd_valid_combi = (internal_master_cmd_ready) ? int_cmd_valid : prev_int_cmd_valid; + end + else + begin + int_master_cmd_data_combi = int_master_cmd_data; + int_master_cmd_valid_combi = int_master_cmd_valid; + end + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[2]) + begin + int_master_cmd_valid <= 1'b0; + prev_int_cmd_valid <= 1'b0; + end + else + begin + int_master_cmd_valid <= int_master_cmd_valid_combi; + + if (internal_master_cmd_ready) + begin + prev_int_cmd_valid <= int_cmd_valid; + end + end + end + + always @ (posedge ctl_clk) + begin + int_master_cmd_data <= int_master_cmd_data_combi; + + if (internal_master_cmd_ready) + begin + prev_int_cmd_data <= int_cmd_data; + end + end + + always @ (posedge ctl_clk) + begin + internal_master_cmd_ready <= mux_master_cmd_ready; + end + + always @ (posedge ctl_clk) + begin + int_ast_master_cmd_ready <= master_cmd_ready; + end + + always @ (posedge ctl_clk) + begin + master_wr_data_info_r1 <= master_wr_data_info; + master_wr_data_info_r2 <= master_wr_data_info_r1; + master_wr_data_info_r3 <= master_wr_data_info_r2; + master_wr_data_info_r4 <= master_wr_data_info_r3; + master_wr_data_info_r5 <= master_wr_data_info_r4; + master_wr_data_info_r6 <= master_wr_data_info_r5; + master_wr_data_info_r7 <= master_wr_data_info_r6; + master_wr_data_info_r8 <= master_wr_data_info_r7; + master_wr_data_info_r9 <= master_wr_data_info_r8; + master_wr_data_info_r10<= master_wr_data_info_r9; + end + + always @ (posedge ctl_clk) + begin + master_cmd_ready_r1 <= master_cmd_ready; + master_cmd_ready_r2 <= master_cmd_ready_r1; + master_cmd_ready_r3 <= master_cmd_ready_r2; + master_cmd_ready_r4 <= master_cmd_ready_r3; + master_cmd_ready_r5 <= master_cmd_ready_r4; + master_cmd_ready_r6 <= master_cmd_ready_r5; + master_cmd_ready_r7 <= master_cmd_ready_r6; + master_cmd_ready_r8 <= master_cmd_ready_r7; + end + + always @ (posedge ctl_clk) + begin + slave_cmd_ready_r1 <= slave_cmd_ready; + slave_cmd_ready_r2 <= slave_cmd_ready_r1; + slave_cmd_ready_r3 <= slave_cmd_ready_r2; + slave_cmd_ready_r4 <= slave_cmd_ready_r3; + slave_cmd_ready_r5 <= slave_cmd_ready_r4; + slave_cmd_ready_r6 <= slave_cmd_ready_r5; + slave_cmd_ready_r7 <= slave_cmd_ready_r6; + slave_cmd_ready_r8 <= slave_cmd_ready_r7; + end + + always @ (posedge ctl_clk) + begin + slave_wr_data_ready_r1 <= slave_wr_data_ready; + slave_wr_data_ready_r2 <= slave_wr_data_ready_r1; + slave_wr_data_ready_r3 <= slave_wr_data_ready_r2; + slave_wr_data_ready_r4 <= slave_wr_data_ready_r3; + slave_wr_data_ready_r5 <= slave_wr_data_ready_r4; + slave_wr_data_ready_r6 <= slave_wr_data_ready_r5; + slave_wr_data_ready_r7 <= slave_wr_data_ready_r6; + slave_wr_data_ready_r8 <= slave_wr_data_ready_r7; + end + + always @ (posedge ctl_clk) + begin + slave_rd_data_ready_r1 <= slave_rd_data_ready; + slave_rd_data_ready_r2 <= slave_rd_data_ready_r1; + slave_rd_data_ready_r3 <= slave_rd_data_ready_r2; + slave_rd_data_ready_r4 <= slave_rd_data_ready_r3; + end + + assign internal_master_rd_data_ready = int_slave_rd_data_ready & ~(prolong_write_back_data_fifo_empty_combi); + +`ifdef USE_AVST + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[23]) + begin + internal_master_rd_data_valid <= 1'b0; + end + else + begin + if (master_rd_data_ready) + begin + internal_master_rd_data_valid <= master_rd_data_valid; + end + else if (int_slave_rd_data_ready) + begin + internal_master_rd_data_valid <= 1'b0; + end + end + end +`else + always @ (posedge ctl_clk) + begin + if (master_rd_data_ready) + begin + internal_master_rd_data_valid <= master_rd_data_valid; + end + else if (int_slave_rd_data_ready) + begin + internal_master_rd_data_valid <= 1'b0; + end + end +`endif + + always @ (posedge ctl_clk) + begin + if (master_rd_data_ready) + begin + internal_master_rd_data <= master_rd_data; + internal_master_rd_data_id <= master_rd_data_id; + internal_master_rd_data_info <= master_rd_data_info; + internal_master_rd_data_type <= master_rd_data_type; + int_pointer_fifo_rd_data <= pointer_fifo_rd_data; + int_wr_addr_fifo_rd_data <= wr_addr_fifo_rd_data; + end + end + + assign idle = partial_wdata_fifo_empty & + initial_pointer_fifo_empty & + pointer_fifo_empty & + cmd_info_fifo_empty & + initial_wr_addr_fifo_empty & + wr_addr_fifo_empty & + read_address_fifo_empty & + (read_size_counter == {CFG_LOCAL_SIZE_WIDTH{1'b0}}) & + error_address_fifo_empty; + + + fmiohmc_ecc_amm2ast # + ( + .CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ) + ) + amm_ast_converter + ( + .clk (ctl_clk ), + .reset_n (ctl_reset_n[3] ), + .amm_ready (amm_ready ), + .amm_cmd_size (amm_cmd_size ), + .amm_cmd_wr (amm_cmd_wr ), + .amm_cmd_rd (amm_cmd_rd ), + .ast_cmd_ready (ast_cmd_ready ), + .ast_cmd_valid (ast_cmd_valid ), + .ast_wr_data_ready (ast_wr_data_ready ), + .ast_wr_data_valid (ast_wr_data_valid ) + ); + + assign amm_cmd_size = int_slave_cmd_size; + assign amm_cmd_wr = int_slave_cmd_wr; + assign amm_cmd_rd = int_slave_cmd_rd; + assign ast_cmd_ready = int_ast_master_cmd_ready & ~(error_cmd_valid | pop_from_error_address_fifo); + assign ast_wr_data_ready = int_slave_wr_data_ready; + + assign int_slave_cmd_data = internal_slave_cmd_data ; + assign int_slave_cmd_valid = is_ast ? internal_slave_cmd_valid : (ast_cmd_valid & (~load_rmw_busy | amm_cmd_rd)) ; + assign int_slave_wr_data_byte_enable = internal_slave_wr_data_byte_enable ; + assign int_slave_wr_data = internal_slave_wr_data ; + assign int_slave_wr_data_id = internal_slave_wr_data_id ; + assign int_slave_wr_data_valid = is_ast ? (internal_slave_wr_data_valid & int_slave_wr_data_ready) : (ast_wr_data_valid & ~issuing_dummy_write_command) ; + assign int_slave_rd_data_ready = mux_slave_rd_data_ready ; + + assign int_master_cmd_ready = is_ast ? ast_cmd_ready : amm_ready ; + assign int_master_cmd_info = master_cmd_info ; + assign int_master_wr_data_ready = master_wr_data_ready ; + assign int_master_wr_data_ptr_in = master_wr_data_ptr_in ; + assign int_master_rd_data = internal_master_rd_data ; + assign int_master_rd_data_id = internal_master_rd_data_id ; + assign int_master_rd_data_info = {internal_master_rd_data_type, internal_master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 2 : 0]} ; + assign int_master_rd_data_valid = internal_master_rd_data_valid & internal_master_rd_data_ready ; + + + assign partial_wdata_fifo_wr = master_wr_data_valid & (master_wr_data_info == NORMAL_PARTIAL_WRITE_DATA); + assign partial_wdata_fifo_rd = partial_read_data_returned; + + generate + for (i = 0; i < CFG_ECC_MULTIPLE_INSTANCE; i = i + 1) + begin : fifo_data_loop + assign partial_wdata_fifo_wr_data [(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH + CFG_LOCAL_DATA_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH + CFG_LOCAL_DATA_WIDTH] = master_wr_data_byte_enable_ori [i * CFG_ECC_BE_PER_WORD_WIDTH + CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH ]; + assign partial_wdata_fifo_wr_data [(i + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_DATA_PER_WORD_WIDTH ] = master_wr_data [i * CFG_ECC_DATA_PER_WORD_WIDTH + CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : i * CFG_ECC_DATA_PER_WORD_WIDTH]; + end + endgenerate + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (PARTIAL_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (PARTIAL_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (PARTIAL_FIFO_REGISTERED_OUTPUT ), + .CFG_REGISTERED_INPUT (2 ), + .CFG_SHOWAHEAD (PARTIAL_FIFO_SHOWAHEAD ) + ) + partial_write_data_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[4] ), + .write_request (partial_wdata_fifo_wr ), + .write_data (partial_wdata_fifo_wr_data ), + .read_request (partial_wdata_fifo_rd ), + .read_data (partial_wdata_fifo_rd_data ), + .read_data_valid (partial_wdata_fifo_rd_data_valid ), + .fifo_empty (partial_wdata_fifo_empty ) + ); + generate + for (i = 0;i < CFG_ECC_MULTIPLE_INSTANCE;i = i + 1) + begin : ratio_loop + for (j = 0; j < CFG_LOCAL_BE_PER_WORD_WIDTH; j = j + 1) + begin : be_loop + always @ (*) + begin + if ((j < (cfg_local_data_width / 4'd8)) && (i < cfg_data_rate)) + begin + int_slave_wr_data_byte_enable_ones [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j] = int_slave_wr_data_byte_enable [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j]; + int_slave_wr_data_byte_enable_zeros [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j] = int_slave_wr_data_byte_enable [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j]; + end + else + begin + int_slave_wr_data_byte_enable_ones [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j] = 1'b1; + int_slave_wr_data_byte_enable_zeros [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j] = 1'b0; + end + end + end + + always @ (*) + begin + if (cfg_enable_rmw) + begin + if ( + int_slave_wr_data_byte_enable_zeros [(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH] != {CFG_LOCAL_BE_PER_WORD_WIDTH{1'b0}} && + int_slave_wr_data_byte_enable_ones [(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH] != {CFG_LOCAL_BE_PER_WORD_WIDTH{1'b1}} + ) + begin + partial_write_detected [i] = 1'b1; + end + else + begin + partial_write_detected [i] = 1'b0; + end + + if (cfg_enable_ecc && int_slave_wr_data_byte_enable_zeros [(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH] == {CFG_LOCAL_BE_PER_WORD_WIDTH{1'b0}}) + begin + partial_write_be_all_zeros [i] = 1'b1; + end + else + begin + partial_write_be_all_zeros [i] = 1'b0; + end + + if (int_slave_wr_data_byte_enable_ones [(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH] == {CFG_LOCAL_BE_PER_WORD_WIDTH{1'b1}}) + begin + partial_write_be_all_ones [i] = 1'b1; + end + else + begin + partial_write_be_all_ones [i] = 1'b0; + end + end + else + begin + partial_write_detected [i] = 1'b0; + partial_write_be_all_zeros [i] = 1'b0; + partial_write_be_all_ones [i] = 1'b0; + end + end + end + endgenerate + + always @ (*) + begin + if (cfg_enable_rmw) + begin + if (cfg_enable_dm) + begin + int_partial_write_detected = |partial_write_detected; + int_partial_write_be_all_zeros = &partial_write_be_all_zeros; + int_partial_write_be_all_ones = ~|partial_write_detected & ~&partial_write_be_all_zeros; + end + else + begin + int_partial_write_detected = ~&partial_write_be_all_ones; + int_partial_write_be_all_zeros = &partial_write_be_all_zeros; + int_partial_write_be_all_ones = &partial_write_be_all_ones; + end + end + else + begin + int_partial_write_detected = 1'b0; + int_partial_write_be_all_zeros = 1'b0; + int_partial_write_be_all_ones = 1'b0; + end + end + + always @ (*) + begin + int_wr_data_info = 3'b000; + + if (int_partial_write_detected) + begin + int_wr_data_info [1:0] = 2'b11; + end + else + begin + if (int_partial_write_be_all_zeros) + begin + int_wr_data_info [1:0] = 2'b10; + end + + if (int_partial_write_be_all_ones) + begin + int_wr_data_info [1:0] = 2'b01; + end + end + end + + always @ (posedge ctl_clk) + begin + int_master_rd_data_info_r <= int_master_rd_data_info; + end + + always @ (*) + begin + if (partial_read_data_returned | empty_read_data_returned) + begin + wr_data_info = {1'b1, int_master_rd_data_info_r [1:0]}; + end + else if (issuing_dummy_write_data) + begin + wr_data_info = NORMAL_DUMMY_WRITE_DATA; + end + else + begin + wr_data_info = int_wr_data_info; + end + end + + +generate + if (AVMM_W_CORE_PIPELINE) + begin : gen_avmm_w_core_pipeline + assign push_slave_fifo_data = ~slave_cmd_ready & slave_cmd_ready_r2; + assign pop_slave_fifo_data = int_slave_cmd_ready & slave_data_fifo_empty_n; + + fmiohmc_ecc_interface_fifo + #( + .DATA_WIDTH (CFG_CMD_DATA_WIDTH + CFG_LOCAL_DATA_WIDTH + CFG_LOCAL_BE_WIDTH), + .RESERVE_ENTRY (0) + ) + iohmc_slave_data_fifo_inst + ( + .clk (ctl_clk ), + .reset_n (ctl_reset_n[0] ), + .in_ready ( ), + .in_valid (push_slave_fifo_data ), + .in_data ({slave_wr_data_byte_enable, slave_wr_data, slave_cmd_data}), + .out_ready (pop_slave_fifo_data ), + .out_valid (slave_data_fifo_empty_n ), + .out_data (slave_data_fifo_out ) + ); + end + + if (CFG_REGISTER_ST_WDATA_RDY_LAT_PATH > 0) + begin : gen_cfg_reg_st_wdata_rdy_lat_path_gt0 + + assign wr_fifo_wr_data = {slave_wr_data, slave_wr_data_id, slave_wr_data_byte_enable}; + assign wr_fifo_wr_valid = slave_wr_data_valid & mux_slave_wr_data_ready; + assign wr_fifo_rd_ready = int_slave_wr_data_ready; + + assign {internal_slave_wr_data, internal_slave_wr_data_id, internal_slave_wr_data_byte_enable} = wr_fifo_rd_data; + assign internal_slave_wr_data_valid = wr_fifo_rd_valid; + + fmiohmc_ecc_interface_fifo + #( + .DATA_WIDTH (WR_FIFO_WIDTH ), + .RESERVE_ENTRY (CFG_REGISTER_ST_WDATA_RDY_LAT_PATH) + ) + iohmc_ecc_wr_pipeline_fifo_inst + ( + .clk (ctl_clk ), + .reset_n (ctl_reset_n[0] ), + .in_ready (wr_fifo_wr_ready ), + .in_valid (wr_fifo_wr_valid ), + .in_data (wr_fifo_wr_data ), + .out_ready (wr_fifo_rd_ready ), + .out_valid (wr_fifo_rd_valid ), + .out_data (wr_fifo_rd_data ) + ); + end + else + begin : gen_cfg_reg_st_wdata_rdy_lat_path_zero + assign internal_slave_wr_data = AVMM_W_CORE_PIPELINE ? (slave_data_fifo_empty_n ? slave_data_fifo_out[CFG_CMD_DATA_WIDTH +: CFG_LOCAL_DATA_WIDTH] : slave_wr_data) : slave_wr_data; + assign internal_slave_wr_data_byte_enable = AVMM_W_CORE_PIPELINE ? (slave_data_fifo_empty_n ? slave_data_fifo_out[(CFG_CMD_DATA_WIDTH+CFG_LOCAL_DATA_WIDTH) +: CFG_LOCAL_BE_WIDTH] : slave_wr_data_byte_enable) : slave_wr_data_byte_enable; + assign internal_slave_wr_data_id = slave_wr_data_id; + assign internal_slave_wr_data_valid = slave_wr_data_valid; + assign wr_fifo_wr_ready = 1'b1; + end + + if (CFG_REGISTER_ST_CMD_RDY_LAT_PATH > 0) + begin : gen_cfg_reg_st_cmd_rdy_lat_path_gt0 + + assign cmd_fifo_cmd_data = slave_cmd_data; + assign cmd_fifo_cmd_valid = slave_cmd_valid & mux_slave_cmd_ready; + assign cmd_fifo_rd_ready = int_slave_cmd_ready; + + assign internal_slave_cmd_data = cmd_fifo_rd_data; + assign internal_slave_cmd_valid = cmd_fifo_rd_valid; + + fmiohmc_ecc_interface_fifo + #( + .DATA_WIDTH (CFG_CMD_DATA_WIDTH ), + .RESERVE_ENTRY (CFG_REGISTER_ST_CMD_RDY_LAT_PATH) + ) + iohmc_ecc_cmd_pipeline_fifo_inst + ( + .clk (ctl_clk ), + .reset_n (ctl_reset_n[0] ), + .in_ready (cmd_fifo_wr_ready ), + .in_valid (cmd_fifo_cmd_valid ), + .in_data (cmd_fifo_cmd_data ), + .out_ready (cmd_fifo_rd_ready ), + .out_valid (cmd_fifo_rd_valid ), + .out_data (cmd_fifo_rd_data ) + ); + end + else + begin : gen_cfg_reg_st_cmd_rdy_lat_path_zero + assign internal_slave_cmd_data = AVMM_W_CORE_PIPELINE ? (slave_data_fifo_empty_n ? slave_data_fifo_out[CFG_CMD_DATA_WIDTH-1:0] : slave_cmd_data) : slave_cmd_data; + assign internal_slave_cmd_valid = slave_cmd_valid; + assign cmd_fifo_wr_ready = AVMM_W_CORE_PIPELINE ? ~slave_data_fifo_empty_n : 1'b1; + end +endgenerate + + reg pop_from_cmd_info_fifo; + reg pop_from_initial_pointer_fifo; + reg pop_from_pointer_fifo; + reg push_to_pointer_fifo; + reg doing_second_write_data_burst; + reg finish_write_data_burst; + + assign mux_push_to_initial_pointer_fifo = ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 0) ? push_to_initial_pointer_fifo_r1 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 1) ? push_to_initial_pointer_fifo_r2 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 2) ? push_to_initial_pointer_fifo_r3 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 3) ? push_to_initial_pointer_fifo_r4 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 4) ? push_to_initial_pointer_fifo_r5 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 5) ? push_to_initial_pointer_fifo_r6 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 6) ? push_to_initial_pointer_fifo_r7 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 7) ? push_to_initial_pointer_fifo_r8 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 8) ? push_to_initial_pointer_fifo_r9 : push_to_initial_pointer_fifo_r1; + + assign mux_master_wr_data_info = ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 0) ? master_wr_data_info_r2 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 1) ? master_wr_data_info_r3 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 2) ? master_wr_data_info_r4 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 3) ? master_wr_data_info_r5 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 4) ? master_wr_data_info_r6 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 5) ? master_wr_data_info_r7 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 6) ? master_wr_data_info_r8 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 7) ? master_wr_data_info_r9 : + ((2*(CFG_REGISTER_WDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) == 8) ? master_wr_data_info_r10 : master_wr_data_info_r2; + + assign mux_slave_cmd_ready = (CFG_REGISTER_ST_CMD_RDY_LAT_PATH == 0) ? slave_cmd_ready: + (CFG_REGISTER_ST_CMD_RDY_LAT_PATH == 1) ? slave_cmd_ready_r1 : + (CFG_REGISTER_ST_CMD_RDY_LAT_PATH == 2) ? slave_cmd_ready_r2 : + (CFG_REGISTER_ST_CMD_RDY_LAT_PATH == 3) ? slave_cmd_ready_r3 : + (CFG_REGISTER_ST_CMD_RDY_LAT_PATH == 4) ? slave_cmd_ready_r4 : slave_cmd_ready; + + assign mux_master_cmd_ready = master_cmd_ready; + + assign mux_slave_wr_data_ready = (CFG_REGISTER_ST_WDATA_RDY_LAT_PATH == 0) ? slave_wr_data_ready : + (CFG_REGISTER_ST_WDATA_RDY_LAT_PATH == 1) ? slave_wr_data_ready_r1 : + (CFG_REGISTER_ST_WDATA_RDY_LAT_PATH == 2) ? slave_wr_data_ready_r2 : slave_wr_data_ready; + + assign mux_slave_rd_data_ready = (CFG_REGISTER_ST_RDATA_RDY_LAT_PATH == 0) ? slave_rd_data_ready : + (CFG_REGISTER_ST_RDATA_RDY_LAT_PATH == 1) ? slave_rd_data_ready_r1 : + (CFG_REGISTER_ST_RDATA_RDY_LAT_PATH == 2) ? slave_rd_data_ready_r2 : slave_rd_data_ready; + + assign initial_pointer_fifo_wr = (cfg_wrpath_pipeline_en == 1'b1) ? mux_push_to_initial_pointer_fifo : push_to_initial_pointer_fifo_r1; + assign initial_pointer_fifo_wr_data = {((cfg_wrpath_pipeline_en == 1'b1) ? mux_master_wr_data_info [1 : 0] : master_wr_data_info_r2 [1 : 0]), int_master_wr_data_ptr_in}; + assign initial_pointer_fifo_rd = pop_from_initial_pointer_fifo; + + assign pointer_fifo_wr = push_to_pointer_fifo; + assign pointer_fifo_wr_data = initial_pointer_fifo_rd_data [PTR_FIFO_DATA_WIDTH - 1 : 0]; + assign pointer_fifo_rd = pop_from_pointer_fifo; + + assign cmd_info_fifo_wr = cfg_enable_rmw & ((cfg_wrpath_pipeline_en == 1'b1) ? int_master_cmd_info_r1[0] : int_master_cmd_info[0]); + assign cmd_info_fifo_wr_data = (cfg_wrpath_pipeline_en == 1'b1) ? int_master_cmd_info_r1[CFG_CMD_INFO_WIDTH - 1 : 1] : int_master_cmd_info[CFG_CMD_INFO_WIDTH - 1 : 1]; + assign cmd_info_fifo_rd = pop_from_cmd_info_fifo; + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (PTR_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (PTR_FIFO_DATA_WIDTH + 2 ), + .CFG_REGISTERED_OUTPUT (PTR_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (PTR_FIFO_SHOWAHEAD ) + ) + initial_pointer_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[5] ), + .write_request (initial_pointer_fifo_wr ), + .write_data (initial_pointer_fifo_wr_data ), + .read_request (initial_pointer_fifo_rd ), + .read_data (initial_pointer_fifo_rd_data ), + .read_data_valid (initial_pointer_fifo_rd_data_valid ), + .fifo_empty (initial_pointer_fifo_empty ), + .fifo_full (initial_pointer_fifo_full ) + ); + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (PTR_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (PTR_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (PTR_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (PTR_FIFO_SHOWAHEAD ) + ) + pointer_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[6] ), + .write_request (pointer_fifo_wr ), + .write_data (pointer_fifo_wr_data ), + .read_request (pointer_fifo_rd ), + .read_data (pointer_fifo_rd_data ), + .read_data_valid (pointer_fifo_rd_data_valid ), + .fifo_empty (pointer_fifo_empty ), + .fifo_full (pointer_fifo_full ) + ); + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (CMD_INFO_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (CMD_INFO_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (CMD_INFO_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (CMD_INFO_FIFO_SHOWAHEAD ) + ) + cmd_info_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[7] ), + .write_request (cmd_info_fifo_wr ), + .write_data (cmd_info_fifo_wr_data ), + .read_request (cmd_info_fifo_rd ), + .read_data (cmd_info_fifo_rd_data ), + .read_data_valid (cmd_info_fifo_rd_data_valid ), + .fifo_empty (cmd_info_fifo_empty ), + .fifo_full (cmd_info_fifo_full ) + ); + + generate + if (CFG_ADDR_ENCODE_ENABLED) + begin : gen_cfg_addr_encode_en + assign initial_wr_addr_fifo_wr = push_to_initial_pointer_fifo; + assign initial_wr_addr_fifo_wr_data = master_wr_addr_r; + assign initial_wr_addr_fifo_rd = pop_from_initial_pointer_fifo; + + assign wr_addr_fifo_wr = push_to_pointer_fifo; + assign wr_addr_fifo_wr_data = initial_wr_addr_fifo_rd_data; + assign wr_addr_fifo_rd = pop_from_pointer_fifo; + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (WR_ADDR_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (WR_ADDR_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (WR_ADDR_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (WR_ADDR_FIFO_SHOWAHEAD ) + ) + initial_wr_addr_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[8] ), + .write_request (initial_wr_addr_fifo_wr ), + .write_data (initial_wr_addr_fifo_wr_data ), + .read_request (initial_wr_addr_fifo_rd ), + .read_data (initial_wr_addr_fifo_rd_data ), + .read_data_valid (initial_wr_addr_fifo_rd_data_valid ), + .fifo_empty (initial_wr_addr_fifo_empty ), + .fifo_full (initial_wr_addr_fifo_full ) + ); + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (WR_ADDR_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (WR_ADDR_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (WR_ADDR_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (WR_ADDR_FIFO_SHOWAHEAD ) + ) + wr_addr_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[9] ), + .write_request (wr_addr_fifo_wr ), + .write_data (wr_addr_fifo_wr_data ), + .read_request (wr_addr_fifo_rd ), + .read_data (wr_addr_fifo_rd_data ), + .read_data_valid (wr_addr_fifo_rd_data_valid ), + .fifo_empty (wr_addr_fifo_empty ), + .fifo_full (wr_addr_fifo_full ) + ); + end + else + begin : gen_cfg_addr_encode_dis + assign initial_wr_addr_fifo_rd_data = {WR_ADDR_FIFO_DATA_WIDTH{1'b0}}; + assign initial_wr_addr_fifo_rd_data_valid = initial_pointer_fifo_rd_data_valid; + assign initial_wr_addr_fifo_empty = 1'b1; + + assign wr_addr_fifo_rd_data = {WR_ADDR_FIFO_DATA_WIDTH{1'b0}}; + assign wr_addr_fifo_rd_data_valid = 1'b0; + assign wr_addr_fifo_empty = 1'b1; + end + endgenerate + + always @ (*) + begin + if (cfg_enable_rmw && ((cmd_info_fifo_rd_data_valid && initial_pointer_fifo_rd_data_valid && initial_wr_addr_fifo_rd_data_valid) || doing_second_write_data_burst)) + begin + pop_from_initial_pointer_fifo = 1'b1; + end + else + begin + pop_from_initial_pointer_fifo = 1'b0; + end + end + + always @ (posedge ctl_clk) + begin + if (pop_from_cmd_info_fifo) + begin + doing_second_write_data_burst <= 1'b0; + end + else if (cmd_info_fifo_rd_data_valid && cmd_info_fifo_rd_data[1] == 1'b1) + begin + doing_second_write_data_burst <= 1'b1; + end + else + begin + doing_second_write_data_burst <= 1'b0; + end + end + + always @ (*) + begin + if (((cmd_info_fifo_rd_data_valid && initial_pointer_fifo_rd_data_valid) && cmd_info_fifo_rd_data[1] == 1'b0) || doing_second_write_data_burst) + begin + pop_from_cmd_info_fifo = 1'b1; + end + else + begin + pop_from_cmd_info_fifo = 1'b0; + end + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[22]) + begin + push_to_initial_pointer_fifo <= 1'b0; + end else begin + push_to_initial_pointer_fifo <= cfg_enable_rmw & master_wr_data_valid & int_master_wr_data_ready & ~master_wr_data_info[2]; + end + end + always @ (posedge ctl_clk) + begin + push_to_initial_pointer_fifo_r1 <= push_to_initial_pointer_fifo; + push_to_initial_pointer_fifo_r2 <= push_to_initial_pointer_fifo_r1; + push_to_initial_pointer_fifo_r3 <= push_to_initial_pointer_fifo_r2; + push_to_initial_pointer_fifo_r4 <= push_to_initial_pointer_fifo_r3; + push_to_initial_pointer_fifo_r5 <= push_to_initial_pointer_fifo_r4; + push_to_initial_pointer_fifo_r6 <= push_to_initial_pointer_fifo_r5; + push_to_initial_pointer_fifo_r7 <= push_to_initial_pointer_fifo_r6; + push_to_initial_pointer_fifo_r8 <= push_to_initial_pointer_fifo_r7; + push_to_initial_pointer_fifo_r9 <= push_to_initial_pointer_fifo_r8; + end + + always @ (posedge ctl_clk) + begin + int_master_cmd_info_r1 <= int_master_cmd_info; + end + + always @ (*) + begin + if ( + initial_pointer_fifo_rd && cmd_info_fifo_rd_data[0] == 1'b1 && + ( + initial_pointer_fifo_rd_data [PTR_FIFO_DATA_WIDTH + 2 - 1 : PTR_FIFO_DATA_WIDTH] == INFO_DUMMY_WRITE_DATA || + initial_pointer_fifo_rd_data [PTR_FIFO_DATA_WIDTH + 2 - 1 : PTR_FIFO_DATA_WIDTH] == INFO_PARTIAL_WRITE_DATA + ) + ) + begin + push_to_pointer_fifo = 1'b1; + end + else + begin + push_to_pointer_fifo = 1'b0; + end + end + + always @ (*) + begin + pop_from_pointer_fifo = (empty_read_data_returned_combi_early | partial_read_data_returned_combi_early) & ~pointer_fifo_empty; + end + + always @ (*) + begin + int_wr_data_ptr = wr_data_ptr & {CFG_LOCAL_DATA_PTR_WIDTH {load_rmw_write_data}}; + end + + always @ (posedge ctl_clk) + begin + wr_data_ptr <= int_pointer_fifo_rd_data; + end + + always @ (*) + begin + partial_write_addr = int_wr_addr_fifo_rd_data; + end + + + always @ (*) + begin + partial_read_data_returned_combi_early = int_slave_rd_data_ready & master_rd_data_valid & ({master_rd_data_type, master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 2 : 0]} == NORMAL_PARTIAL_READ_DATA); + empty_read_data_returned_combi_early = int_slave_rd_data_ready & master_rd_data_valid & ({master_rd_data_type, master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 2 : 0]} == NORMAL_DUMMY_READ_DATA); + normal_read_data_returned_combi_early = int_slave_rd_data_ready & master_rd_data_valid & ({master_rd_data_type, master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 2 : 0]} == NORMAL_READ_DATA); + end + + always @ (*) + begin + partial_read_data_returned_combi = int_slave_rd_data_ready & internal_master_rd_data_valid & (int_master_rd_data_info == NORMAL_PARTIAL_READ_DATA); + empty_read_data_returned_combi = int_slave_rd_data_ready & internal_master_rd_data_valid & (int_master_rd_data_info == NORMAL_DUMMY_READ_DATA); + normal_read_data_returned_combi = int_slave_rd_data_ready & internal_master_rd_data_valid & (int_master_rd_data_info == NORMAL_READ_DATA); + mpr_read_data_returned_combi = int_slave_rd_data_ready & internal_master_rd_data_valid & int_master_rd_data_info[CFG_LOCAL_DATA_INFO_WIDTH - 1]; + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[21]) + mpr_read_data_returned_valid <= 1'b0; + else + mpr_read_data_returned_valid <= mpr_read_data_returned_combi; + end + + always @ (posedge ctl_clk) + begin + partial_read_data_returned <= partial_read_data_returned_combi; + empty_read_data_returned <= empty_read_data_returned_combi; + normal_read_data_returned <= normal_read_data_returned_combi; + end + + always @ (*) + begin + int_load_rmw_write_data = (partial_read_data_returned_combi | empty_read_data_returned_combi); + int_load_rmw_busy_non_gated = (partial_read_data_returned | empty_read_data_returned | issuing_dummy_write_data_non_gated); + int_load_rmw_busy = (partial_read_data_returned | empty_read_data_returned | issuing_dummy_write_data); + end + + always @ (posedge ctl_clk) + begin + int_load_rmw_write_data_r <= int_load_rmw_write_data; + int_load_rmw_busy_r <= int_load_rmw_busy; + end + + always @ (*) + begin + load_rmw_write_data = int_load_rmw_write_data_r; + load_rmw_busy_non_gated = int_load_rmw_busy_non_gated | (int_load_rmw_busy_r & |pending_data_valid & ~load_pending_data); + load_rmw_busy = int_load_rmw_busy | (int_load_rmw_busy_r & |pending_data_valid & ~load_pending_data); + end + + always @ (*) + begin + {partial_write_data_byte_enable, partial_write_data} = partial_wdata_fifo_rd_data; + end + + always @ (*) + begin + prolong_write_back_data_fifo_empty_combi = (partial_read_data_returned_combi_early || empty_read_data_returned_combi_early) && pointer_fifo_empty; + end + + + always @ (*) + begin + partial_write_ecc_code = decoder_output_ecc_code; + partial_write_ecc_code_overwrite = {CFG_ECC_MULTIPLE_INSTANCE{cfg_ecc_code_overwrite}} & decoder_output_dbe & {CFG_ECC_MULTIPLE_INSTANCE{~partial_read_data_returned}}; + end + + generate + for (i = 0;i < CFG_ECC_MULTIPLE_INSTANCE;i = i + 1) + begin : instance_loop + if (CFG_LOCAL_DATA_PER_WORD_WIDTH > (CFG_LOCAL_BE_PER_WORD_WIDTH * 8)) + begin + always @ (*) + begin + merge_write_data [((i + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH) - 1 : (i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + (CFG_LOCAL_BE_PER_WORD_WIDTH * 8)] = {(((i + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH) - (CFG_LOCAL_BE_PER_WORD_WIDTH * 8)){zero}}; + end + end + + for (j = 0;j < CFG_LOCAL_BE_PER_WORD_WIDTH;j = j + 1) + begin : local_be_loop + always @ (*) + begin + if (partial_write_data_byte_enable [(i * CFG_LOCAL_BE_PER_WORD_WIDTH) + j]) + begin + merge_write_data [(i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + ((j + 1) * 8) - 1 : (i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + (j * 8)] = partial_write_data [(i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + ((j + 1) * 8) - 1 : (i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + (j * 8)]; + end + else + begin + merge_write_data [(i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + ((j + 1) * 8) - 1 : (i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + (j * 8)] = decoder_output_data [(i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + ((j + 1) * 8) - 1 : (i * CFG_LOCAL_DATA_PER_WORD_WIDTH) + (j * 8)]; + end + end + end + end + endgenerate + + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] current_write_address; + reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] current_write_address_incr; + + always @ (posedge ctl_clk) + begin + if (int_slave_cmd_wr && int_slave_cmd_valid) + begin + current_write_address_incr <= int_slave_cmd_addr + 1'b1; + end + else if (int_slave_wr_data_valid) + begin + current_write_address_incr <= current_write_address_incr + 1'b1; + end + end + + always @ (*) + begin + if (int_slave_cmd_wr && int_slave_cmd_valid) + begin + current_write_address = int_slave_cmd_addr; + end + else + begin + current_write_address = current_write_address_incr; + end + end + + always @ (*) + begin + encoder_input_data = int_slave_wr_data; + encoder_input_addr = current_write_address; + encoder_input_ecc_code = {(CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE){1'b0}}; + encoder_input_ecc_code_overwrite = {CFG_ECC_MULTIPLE_INSTANCE{1'b0}}; + + if (partial_read_data_returned) + begin + encoder_input_data = merge_write_data; + encoder_input_addr = decoder_output_addr; + encoder_input_ecc_code = partial_write_ecc_code; + encoder_input_ecc_code_overwrite = partial_write_ecc_code_overwrite; + end + else if (empty_read_data_returned) + begin + encoder_input_data = decoder_output_data; + encoder_input_addr = decoder_output_addr; + encoder_input_ecc_code = partial_write_ecc_code; + encoder_input_ecc_code_overwrite = partial_write_ecc_code_overwrite; + end + else if (issuing_dummy_write_data) + begin + encoder_input_addr = error_wr_addr; + encoder_input_ecc_code = {(CFG_ECC_CODE_WIDTH * CFG_ECC_MULTIPLE_INSTANCE){1'b0}}; + encoder_input_ecc_code_overwrite = {CFG_ECC_MULTIPLE_INSTANCE{1'b0}}; + end + end + + + always @ (*) + begin + encoder_output_data_id_combi = int_slave_wr_data_id; + encoder_output_data_info_combi = wr_data_info; + encoder_output_data_ptr_combi = int_wr_data_ptr; + encoder_output_data_valid_combi = int_slave_wr_data_valid | load_rmw_write_data | issuing_dummy_write_data; + end + + always @ (posedge ctl_clk) + begin + encoder_output_data_id <= encoder_output_data_id_combi; + encoder_output_data_info <= encoder_output_data_info_combi; + encoder_output_data_ptr <= encoder_output_data_ptr_combi; + encoder_output_data_valid <= encoder_output_data_valid_combi; + end + + generate + for (i = 0; i < CFG_ECC_MULTIPLE_INSTANCE; i = i + 1) + begin : byte_enable_loop + always @ (*) + begin + if (CFG_ECC_BE_PER_WORD_WIDTH > CFG_LOCAL_BE_PER_WORD_WIDTH) + begin + int_encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = {{(CFG_ECC_BE_PER_WORD_WIDTH - CFG_LOCAL_BE_PER_WORD_WIDTH){1'b0}}, int_slave_wr_data_byte_enable[(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH]}; + end + else + begin + int_encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = int_slave_wr_data_byte_enable[(i + 1) * CFG_LOCAL_BE_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_BE_PER_WORD_WIDTH]; + end + + if (partial_read_data_returned) + begin + int_encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH]= {CFG_ECC_BE_PER_WORD_WIDTH{1'b1}}; + end + else if (empty_read_data_returned) + begin + int_encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH]= {CFG_ECC_BE_PER_WORD_WIDTH{1'b1}}; + end + else if (issuing_dummy_write_data) + begin + int_encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH]= {CFG_ECC_BE_PER_WORD_WIDTH{1'b0}}; + end + end + end + endgenerate + + always @ (posedge ctl_clk) + begin + int_encoder_output_data_byte_enable <= int_encoder_output_data_byte_enable_combi; + end + + always @ (*) + begin + if (cfg_gen_sbe) + begin + int_error_inject = 2'b01; + end + else if (cfg_gen_dbe) + begin + int_error_inject = 2'b11; + end + else + begin + int_error_inject = 2'b00; + end + end + + generate + for (i = 0;i < CFG_ECC_MULTIPLE_INSTANCE;i = i + 1) + begin : encoder_instance_loop + if (CFG_ENCODER_DATA_WIDTH > CFG_LOCAL_DATA_PER_WORD_WIDTH) + begin + assign int_encoder_input_data_combi [i] = {{(CFG_ENCODER_DATA_WIDTH - CFG_ECC_CODE_WIDTH){1'b0}}, encoder_input_data [(i + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_DATA_PER_WORD_WIDTH]}; + end + else + begin + assign int_encoder_input_data_combi [i] = encoder_input_data [(i + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_DATA_PER_WORD_WIDTH]; + end + assign int_encoder_input_addr_combi [i] = (CFG_ADDR_ENCODE_ENABLED == 1) ? {encoder_input_addr, i [LOG2_CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]} : {CFG_ENCODER_ADDR_WIDTH{1'b0}}; + assign int_encoder_input_ecc_code_combi [i] = encoder_input_ecc_code [(i + 1) * CFG_ECC_CODE_WIDTH - 1 : i * CFG_ECC_CODE_WIDTH ] ; + assign int_encoder_input_ecc_code_overwrite_combi [i] = encoder_input_ecc_code_overwrite [ i ] ; + + always @ (posedge ctl_clk) + begin + int_encoder_input_data [i] <= int_encoder_input_data_combi [i]; + int_encoder_input_addr [i] <= int_encoder_input_addr_combi [i]; + int_encoder_input_ecc_code [i] <= int_encoder_input_ecc_code_combi [i]; + int_encoder_input_ecc_code_overwrite [i] <= int_encoder_input_ecc_code_overwrite_combi [i]; + end + + fmiohmc_ecc_encoder # + ( + .CFG_ECC_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ), + .CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ), + .CFG_ADDR_WIDTH (CFG_ENCODER_ADDR_WIDTH ), + .CFG_PORT_WIDTH_DRAM_DATA_WIDTH (CFG_PORT_WIDTH_DRAM_DATA_WIDTH ), + .CFG_PORT_WIDTH_LOCAL_DATA_WIDTH (CFG_PORT_WIDTH_LOCAL_DATA_WIDTH ), + .CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ), + .CFG_ADDR_ENCODE_ENABLED (CFG_ADDR_ENCODE_ENABLED ) + ) + ecc_encoder_inst + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[10] ), + .cfg_local_data_width (cfg_local_data_width ), + .cfg_dram_data_width (cfg_dram_data_width ), + .cfg_enable_ecc (cfg_enable_ecc ), + .input_data (int_encoder_input_data [i]), + .input_addr (int_encoder_input_addr [i]), + .input_ecc_code (int_encoder_input_ecc_code [i]), + .input_ecc_code_overwrite (int_encoder_input_ecc_code_overwrite [i]), + .output_data (int_encoder_output_data [i]) + ); + + always @ (*) + begin + encoder_output_data [(i + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : i * CFG_ECC_DATA_PER_WORD_WIDTH] = {int_encoder_output_data [i][CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (int_encoder_output_data [i][1 : 0] ^ int_error_inject [1 : 0])}; + end + + always @ (*) + begin + if (cfg_enable_rmw) + begin + if (cfg_enable_dm) + begin + if (int_slave_wr_data_valid && int_slave_wr_data_ready) + begin + if (partial_write_be_all_ones[i]) + begin + encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = {CFG_ECC_BE_PER_WORD_WIDTH{1'b1}}; + end + else + begin + encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = {CFG_ECC_BE_PER_WORD_WIDTH{1'b0}}; + end + end + else + begin + encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = {CFG_ECC_BE_PER_WORD_WIDTH{1'b1}}; + end + end + else + begin + encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = {CFG_ECC_BE_PER_WORD_WIDTH{1'b1}}; + end + end + else + begin + encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] = int_encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH]; + end + end + + always @ (posedge ctl_clk) + begin + encoder_output_data_byte_enable [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH] <= encoder_output_data_byte_enable_combi [(i + 1) * CFG_ECC_BE_PER_WORD_WIDTH - 1 : i * CFG_ECC_BE_PER_WORD_WIDTH]; + end + end + endgenerate + + always @ (posedge ctl_clk) + begin + encoder_output_addr <= encoder_input_addr; + end + always @ (*) + begin + decoder_input_data = int_master_rd_data; + decoder_input_data_valid = normal_read_data_returned_combi; + + if (partial_read_data_returned_combi || empty_read_data_returned_combi) + begin + decoder_input_addr = partial_write_addr; + end + else + begin + decoder_input_addr = int_current_addr; + end + end + + always @ (*) + begin + decoder_output_data_id_combi = int_master_rd_data_id; + decoder_output_rd_data_type_combi = int_master_rd_data_info[CFG_LOCAL_DATA_INFO_WIDTH - 1]; + end + + generate + for (i = 0;i < CFG_ECC_MULTIPLE_INSTANCE;i = i + 1) + begin : decoder_instance_loop + if (CFG_DECODER_DATA_WIDTH > CFG_ECC_DATA_PER_WORD_WIDTH) + begin + assign int_decoder_input_data [i] = {{(CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH){1'b0}}, decoder_input_data [(i + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : i * CFG_ECC_DATA_PER_WORD_WIDTH]}; + end + else + begin + assign int_decoder_input_data [i] = decoder_input_data [(i + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : i * CFG_ECC_DATA_PER_WORD_WIDTH]; + end + + assign int_decoder_input_addr [i] = (CFG_ADDR_ENCODE_ENABLED == 1) ? {decoder_input_addr, i [LOG2_CFG_ECC_MULTIPLE_INSTANCE - 1 : 0]} : {CFG_DECODER_ADDR_WIDTH{1'b0}}; + assign int_decoder_input_data_valid [i] = decoder_input_data_valid; + + assign decoder_output_data_combi [(i + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : i * CFG_LOCAL_DATA_PER_WORD_WIDTH] = int_decoder_output_data [i][CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0]; + assign decoder_output_data_valid_combi [ i ] = int_decoder_output_data_valid [i]; + assign decoder_output_ecc_code_combi [(i + 1) * CFG_ECC_CODE_WIDTH - 1 : i * CFG_ECC_CODE_WIDTH ] = int_decoder_output_ecc_code [i]; + + fmiohmc_ecc_decoder # + ( + .CFG_ECC_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ), + .CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ), + .CFG_ADDR_WIDTH (CFG_DECODER_ADDR_WIDTH ), + .CFG_PORT_WIDTH_DRAM_DATA_WIDTH (CFG_PORT_WIDTH_DRAM_DATA_WIDTH ), + .CFG_PORT_WIDTH_LOCAL_DATA_WIDTH (CFG_PORT_WIDTH_LOCAL_DATA_WIDTH ), + .CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ), + .CFG_ADDR_ENCODE_ENABLED (CFG_ADDR_ENCODE_ENABLED ) + ) + ecc_decoder_inst + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[11] ), + .cfg_local_data_width (cfg_local_data_width ), + .cfg_dram_data_width (cfg_dram_data_width ), + .cfg_enable_ecc (cfg_enable_ecc ), + .input_data (int_decoder_input_data [i]), + .input_addr (int_decoder_input_addr [i]), + .input_data_valid (int_decoder_input_data_valid [i]), + .output_data (int_decoder_output_data [i]), + .output_data_valid (int_decoder_output_data_valid [i]), + .output_ecc_code (int_decoder_output_ecc_code [i]), + .err_corrected (int_decoder_output_err_corrected [i]), + .err_detected (int_decoder_output_err_detected [i]), + .err_fatal (int_decoder_output_err_fatal [i]), + .err_sbe (int_decoder_output_err_sbe [i]), + .err_addr_detected (int_decoder_output_err_addr_detected [i]), + .err_addr (int_decoder_output_err_addr [i]) + ); + + always @ (posedge ctl_clk) + begin + decoder_output_err_addr [(i + 1) * CFG_DECODER_ADDR_WIDTH - 1 : i * CFG_DECODER_ADDR_WIDTH] <= int_decoder_output_err_addr [i]; + end + + + + always @ (*) + begin + if (i < cfg_data_rate) + begin + if (int_decoder_output_err_detected [i] | int_decoder_output_err_sbe [i] | int_decoder_output_err_addr_detected [i]) + begin + if (int_decoder_output_err_addr_detected [i]) + begin + decoder_output_sbe_combi [i] = 1'b0; + decoder_output_dbe_combi [i] = 1'b1; + decoder_output_addrerr_combi [i] = 1'b1; + decoder_output_data_dbe_combi [i] = 1'b0; + end + else if (int_decoder_output_err_corrected [i] | int_decoder_output_err_sbe [i]) + begin + decoder_output_sbe_combi [i] = 1'b1; + decoder_output_dbe_combi [i] = 1'b0; + decoder_output_addrerr_combi [i] = 1'b0; + decoder_output_data_dbe_combi [i] = 1'b0; + end + else if (int_decoder_output_err_fatal [i]) + begin + decoder_output_sbe_combi [i] = 1'b0; + decoder_output_dbe_combi [i] = 1'b1; + decoder_output_addrerr_combi [i] = 1'b0; + decoder_output_data_dbe_combi [i] = 1'b1; + end + else + begin + decoder_output_sbe_combi [i] = 1'b0; + decoder_output_dbe_combi [i] = 1'b0; + decoder_output_addrerr_combi [i] = 1'b0; + decoder_output_data_dbe_combi [i] = 1'b0; + end + end + else + begin + decoder_output_sbe_combi [i] = 1'b0; + decoder_output_dbe_combi [i] = 1'b0; + decoder_output_addrerr_combi [i] = 1'b0; + decoder_output_data_dbe_combi [i] = 1'b0; + end + end + else + begin + decoder_output_sbe_combi [i] = 1'b0; + decoder_output_dbe_combi [i] = 1'b0; + decoder_output_addrerr_combi [i] = 1'b0; + decoder_output_data_dbe_combi [i] = 1'b0; + end + end + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[12]) + begin + decoder_output_data_valid_combi_r <= {CFG_ECC_MULTIPLE_INSTANCE{1'b0}}; + end + else + begin + decoder_output_data_valid_combi_r <= decoder_output_data_valid_combi; + end + end + + always @ (posedge ctl_clk) + begin + decoder_output_sbe_combi_r <= decoder_output_sbe_combi; + decoder_output_dbe_combi_r <= decoder_output_dbe_combi; + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[13]) + begin + decoder_output_data_valid <= {CFG_ECC_MULTIPLE_INSTANCE{1'b0}}; + end + else + begin + if (int_slave_rd_data_ready || partial_read_data_returned_combi || empty_read_data_returned_combi) + begin + decoder_output_data_valid <= decoder_output_data_valid_combi; + end + end + end + + always @ (posedge ctl_clk) + begin + if (int_slave_rd_data_ready || partial_read_data_returned_combi || empty_read_data_returned_combi) + begin + decoder_output_data <= decoder_output_data_combi; + decoder_output_addr <= decoder_input_addr; + decoder_output_ecc_code <= decoder_output_ecc_code_combi; + decoder_output_data_id <= decoder_output_data_id_combi; + decoder_output_sbe <= decoder_output_sbe_combi; + decoder_output_dbe <= decoder_output_dbe_combi; + decoder_output_data_dbe <= decoder_output_data_dbe_combi; + decoder_output_addrerr <= decoder_output_addrerr_combi; + decoder_output_rd_data_type <= decoder_output_rd_data_type_combi; + end + end + + + assign sts_current_addr = current_addr; + + assign sts_corr_dropped_valid = cfg_enable_auto_corr && push_to_error_address_fifo && error_address_fifo_full; + + endgenerate + + assign read_address_fifo_wr = int_slave_cmd_ready & int_slave_cmd_rd & int_slave_cmd_valid; + assign read_address_fifo_wr_data = {int_slave_cmd_size, int_slave_cmd_addr}; + assign read_address_fifo_rd = pop_from_read_address_fifo; + + assign {read_address_fifo_size, read_address_fifo_addr} = read_address_fifo_rd_data; + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (READ_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (READ_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (READ_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (READ_FIFO_SHOWAHEAD ) + ) + read_address_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[14] ), + .write_request (read_address_fifo_wr ), + .write_data (read_address_fifo_wr_data ), + .read_request (read_address_fifo_rd ), + .read_data (read_address_fifo_rd_data ), + .read_data_valid (read_address_fifo_rd_data_valid ), + .fifo_empty (read_address_fifo_empty ), + .fifo_full (read_address_fifo_full ) + ); + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[15]) begin + read_size_counter <= {CFG_LOCAL_SIZE_WIDTH{1'b0}}; + end else begin + if (pop_from_read_address_fifo) + begin + read_size_counter <= read_address_fifo_size; + end + else if (normal_read_data_returned_combi) + begin + read_size_counter <= read_size_counter - 1'b1; + end + end + end + + always @ (*) + begin + if (!read_address_fifo_empty && ((read_size_counter == 0) || last_read_data == 1'b1)) + begin + pop_from_read_address_fifo = 1'b1; + end + else + begin + pop_from_read_address_fifo = 1'b0; + end + end + + always @ (*) + begin + if (normal_read_data_returned_combi && read_size_counter == 1) + begin + last_read_data = 1'b1; + end + else + begin + last_read_data = 1'b0; + end + end + + always @ (posedge ctl_clk) + begin + if (pop_from_read_address_fifo) + begin + int_current_addr <= read_address_fifo_addr; + end + else if (normal_read_data_returned_combi) + begin + int_current_addr <= int_current_addr + 1'b1; + end + end + + always @ (posedge ctl_clk) + begin + current_addr <= int_current_addr; + end + + + assign error_address_fifo_wr = cfg_enable_auto_corr & push_to_error_address_fifo & ~error_address_fifo_full; + assign error_address_fifo_rd = pop_from_error_address_fifo; + + assign error_address_fifo_wr_data = (cfg_enable_dm == 1'b1 || cfg_data_rate == 4'd8) ? current_addr : {current_addr[CFG_LOCAL_ADDR_WIDTH - 1 : 1], 1'b0}; + assign error_cmd_size = (cfg_enable_dm == 1'b1 || cfg_data_rate == 4'd8) ? {{(CFG_LOCAL_SIZE_WIDTH - 1){1'b0}}, 1'b1} : {{(CFG_LOCAL_SIZE_WIDTH - 2){1'b0}}, 2'd2}; + + assign error_address_fifo_addr = error_address_fifo_rd_data; + + fmiohmc_fifo # + ( + .CFG_ADDR_WIDTH (ERROR_FIFO_ADDR_WIDTH ), + .CFG_DATA_WIDTH (ERROR_FIFO_DATA_WIDTH ), + .CFG_REGISTERED_OUTPUT (ERROR_FIFO_REGISTERED_OUTPUT ), + .CFG_SHOWAHEAD (ERROR_FIFO_SHOWAHEAD ) + ) + error_address_fifo + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[16] ), + .write_request (error_address_fifo_wr ), + .write_data (error_address_fifo_wr_data ), + .read_request (error_address_fifo_rd ), + .read_data (error_address_fifo_rd_data ), + .read_data_valid (error_address_fifo_rd_data_valid ), + .fifo_empty (error_address_fifo_empty ), + .fifo_full (error_address_fifo_full ) + ); + + always @ (*) + begin + if (|decoder_output_sbe && normal_read_data_returned) + begin + push_to_error_address_fifo = 1'b1; + end + else + begin + push_to_error_address_fifo = 1'b0; + end + end + + always @ (*) + begin + if ( + !error_address_fifo_empty && + !error_cmd_valid && + !error_wr_data_valid && + (pending_write_data_counter == {CFG_PENDING_WRITE_DATA_WIDTH{1'b0}}) && + !data_before_write_command + ) + begin + pop_from_error_address_fifo = 1'b1; + end + else + begin + pop_from_error_address_fifo = 1'b0; + end + end + + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[17]) + begin + pending_write_data_counter <= {CFG_PENDING_WRITE_DATA_WIDTH{1'b0}}; + pending_write_data_counter_underflow <= 1'b0; + end + else + begin + if (int_slave_cmd_ready && int_slave_cmd_valid && int_slave_cmd_wr) + begin + pending_write_data_counter_underflow <= 1'b0; + + if (int_slave_wr_data_ready && int_slave_wr_data_valid) + begin + pending_write_data_counter <= is_ast ? (pending_write_data_counter + int_slave_cmd_size - 1'b1) : (int_slave_cmd_size - 1'b1); + end + else + begin + pending_write_data_counter <= is_ast ? (pending_write_data_counter + int_slave_cmd_size) : int_slave_cmd_size; + end + end + else if (int_slave_wr_data_ready && int_slave_wr_data_valid) + begin + if (pending_write_data_counter == {CFG_PENDING_WRITE_DATA_WIDTH{1'b0}}) + begin + pending_write_data_counter_underflow <= 1'b1; + end + else + begin + pending_write_data_counter_underflow <= 1'b0; + end + + pending_write_data_counter <= pending_write_data_counter - 1'b1; + end + end + + end + + always @ (*) + begin + if (is_ast) + begin + if (pending_write_data_counter == {CFG_PENDING_WRITE_DATA_WIDTH{1'b0}} && int_slave_wr_data_ready && int_slave_wr_data_valid) + begin + data_before_write_command = 1'b1; + end + else + begin + data_before_write_command = pending_write_data_counter_underflow; + end + end + else + begin + data_before_write_command = 1'b0; + end + end + + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[18]) + begin + error_cmd_valid <= 1'b0; + end + else + begin + if (pop_from_error_address_fifo) + begin + error_cmd_valid <= 1'b1; + end + else + begin + if (internal_master_cmd_ready) + begin + error_cmd_valid <= 1'b0; + end + end + end + end + + always @ (posedge ctl_clk) + begin + if (pop_from_error_address_fifo) + begin + error_cmd_addr <= error_address_fifo_addr; + error_cmd_size_decrement <= error_cmd_size; + end + else + begin + if (issuing_dummy_write_data) + begin + error_cmd_size_decrement <= error_cmd_size_decrement - 1'b1; + end + end + end + + always @ (posedge ctl_clk) + begin + if (pop_from_error_address_fifo) + begin + error_wr_addr <= error_address_fifo_addr; + end + else if (issuing_dummy_write_data) + begin + error_wr_addr <= error_wr_addr + 1'b1; + end + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[19]) + begin + error_wr_data_valid <= 1'b0; + end + else + begin + if (pop_from_error_address_fifo) + begin + error_wr_data_valid <= 1'b1; + end + else if (int_master_wr_data_ready && !(partial_read_data_returned | empty_read_data_returned | (|pending_data_valid & ~load_pending_data)) && error_cmd_size_decrement == 1) + begin + error_wr_data_valid <= 1'b0; + end + end + end + + always @ (*) + begin + issuing_dummy_write_command = error_cmd_valid & internal_master_cmd_ready; + issuing_dummy_write_data_non_gated = error_wr_data_valid & ~(partial_read_data_returned | empty_read_data_returned | (|pending_data_valid & ~load_pending_data)); + issuing_dummy_write_data = issuing_dummy_write_data_non_gated & int_master_wr_data_ready; + end + + always @ (*) + begin + if (CFG_LOCAL_SIZE_WIDTH >= 8) begin + error_cmd_size_padded = error_cmd_size; + end else begin + error_cmd_size_padded = {{(8 - CFG_LOCAL_SIZE_WIDTH){1'b0}}, error_cmd_size}; + end + + if (CFG_LOCAL_ADDR_WIDTH >= 35) begin + error_cmd_addr_padded = error_cmd_addr; + end else begin + error_cmd_addr_padded = {{(35 - CFG_LOCAL_ADDR_WIDTH){1'b0}}, error_cmd_addr}; + end + + if (error_cmd_valid) + begin + int_cmd_data = { + {CFG_LOCAL_ID_WIDTH{1'b0}}, + 1'b0, + 1'b1, + 1'b0, + error_cmd_size_padded, + error_cmd_addr_padded, + 1'b1, + 1'b0 + }; + int_cmd_valid = 1'b1; + end + else + begin + int_cmd_data = int_slave_cmd_data; + int_cmd_valid = int_slave_cmd_valid & ~pop_from_error_address_fifo; + end + end + + always @ (posedge ctl_clk) + begin + if (!ctl_reset_n[20]) + begin + sts_ecc_intr <= {STS_PORT_WIDTH_ECC_INTR{1'b0}}; + sts_sbe_error <= {STS_PORT_WIDTH_SBE_ERROR{1'b0}}; + sts_dbe_error <= {STS_PORT_WIDTH_DBE_ERROR{1'b0}}; + sts_corr_dropped <= {STS_PORT_WIDTH_CORR_DROPPED{1'b0}}; + sts_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}}; + sts_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}}; + sts_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROPPED_COUNT{1'b0}}; + sts_err_addr <= {STS_PORT_WIDTH_ERR_ADDR{1'b0}}; + sts_corr_dropped_addr <= {STS_PORT_WIDTH_CORR_DROPPED_ADDR{1'b0}}; + sts_mr_rdata_valid <= 1'b0; + end + else + begin + if (cfg_enable_intr) + begin + if (cfg_clr_intr) + begin + sts_ecc_intr <= {STS_PORT_WIDTH_ECC_INTR{1'b0}}; + sts_sbe_error <= {STS_PORT_WIDTH_SBE_ERROR{1'b0}}; + sts_dbe_error <= {STS_PORT_WIDTH_DBE_ERROR{1'b0}}; + sts_corr_dropped <= {STS_PORT_WIDTH_CORR_DROPPED{1'b0}}; + sts_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}}; + sts_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}}; + sts_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROPPED_COUNT{1'b0}}; + sts_err_addr <= {STS_PORT_WIDTH_ERR_ADDR{1'b0}}; + sts_corr_dropped_addr <= {STS_PORT_WIDTH_CORR_DROPPED_ADDR{1'b0}}; + end + else + begin + if (|decoder_output_sbe_combi_r && |decoder_output_data_valid_combi_r) + begin + if (!cfg_mask_sbe_intr) + begin + sts_ecc_intr <= 1'b1; + end + + sts_sbe_error <= 1'b1; + sts_sbe_count <= sts_sbe_count + 1'b1; + sts_err_addr <= current_addr; + end + + if (|decoder_output_dbe_combi_r && |decoder_output_data_valid_combi_r) + begin + if (!cfg_mask_dbe_intr) + begin + sts_ecc_intr <= 1'b1; + end + + sts_dbe_error <= 1'b1; + sts_dbe_count <= sts_dbe_count + 1'b1; + sts_err_addr <= current_addr; + end + + if (cfg_enable_auto_corr && push_to_error_address_fifo && error_address_fifo_full) + begin + if (!cfg_mask_corr_dropped_intr) + begin + sts_ecc_intr <= 1'b1; + end + + sts_corr_dropped <= 1'b1; + sts_corr_dropped_count <= sts_corr_dropped_count + 1'b1; + sts_corr_dropped_addr <= current_addr; + end + + if (!cfg_mask_hmi_intr && hmi_interrupt) + begin + sts_ecc_intr <= 1'b1; + end + end + end + + if (cfg_clr_mr_rdata) + begin + sts_mr_rdata_valid <= 1'b0; + end + else + begin + if (cfg_clr_mr_rdata) + begin + sts_mr_rdata_valid <= 1'b0; + end + else if (cfg_data_rate == 4'd4 && int_master_rd_data_valid && int_master_rd_data_valid_r && int_master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 1]) + begin + sts_mr_rdata_valid <= 1'b1; + end + else if (cfg_data_rate == 4'd8 && int_master_rd_data_valid && !int_master_rd_data_valid_r && int_master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 1]) + begin + sts_mr_rdata_valid <= 1'b1; + end + end + end + end + + + always @ (posedge ctl_clk) + begin + if (cfg_clr_mr_rdata) + begin + sts_mr_rdata_0 <= {STS_PORT_WIDTH_MR_DATA{1'b0}}; + sts_mr_rdata_1 <= {STS_PORT_WIDTH_MR_DATA{1'b0}}; + end + else + begin + if (int_master_rd_data_valid && !int_master_rd_data_valid_r && int_master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 1]) + begin + sts_mr_rdata_0 <= int_master_rd_data; + end + + if (int_master_rd_data_valid && int_master_rd_data_valid_r && int_master_rd_data_info [CFG_LOCAL_DATA_INFO_WIDTH - 1] && cfg_data_rate == 4'd4) + begin + sts_mr_rdata_1 <= int_master_rd_data; + end + end + end + + always @ (posedge ctl_clk) + begin + int_master_rd_data_valid_r <= int_master_rd_data_valid; + end + + + always @ (*) + begin + user_interrupt = sts_ecc_intr; + end + +function integer log2; + input integer value; + begin + value = value - 'd1; + for (log2 = 'd0; value > 0; log2 = log2 + 'd1) + value = value >> 'd1; + end +endfunction + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EDwQqqnulK93JxlxKTd3IAVRwgCNLAKwQy/4fOvNVxW4/Qtn8GWqLYSwOTe1hVoXyIpoNZuZXW1w1aX/MToaLFPAbD8hSF3mPuh7bNBhKi4ftzFy3e1YXr3kW1SeKN6hJ3H+IcDwPGF1AIOFXiENRFi6g7leeZ34w2HjiJ1dm3su/j1D+peKKqLP4q7HXrTGHOnLZh4n/xlFGIXDHmkEfG4IhauGx7diDCE9ADgZzwbdQpiuOa7ce27UKOaRlT1/faARukrNZlHXAjhsozbfhItZsXD4gvZQBgCuR3H2DhtLh4yr7ML3q4u5haoMxH9deCh0xMA9Yt4klJ7Ogod9HY/f2BjLXAPuyfsSmLLsSWPAiFUeSj8HvQY4qAXejzecToswO9ynZYncE4+tKMypVC0YhincdWlNV5Ht8+l4iQmjuvi+aQImQl7FhFcm5T6kMdSUgDdTRx1sJ6UKN9ToMyMoL1pYaHm8IHOYNwL50TR8jlXn/mY+54GwlDgx4vgOuraPwCNGkwCyJx+Yix5DEl/lDk9TrNtlbWElvdL6IWuGjcuYZFcU6FV1o+x6FUaYOibBoxg+hQgQZZS7oNe6LK3Yo774x9QMS8e4O15b9DSjx1Bk/9FpiFD2XcAgrr+btbQ55+MEAoNfqI7883DVc3wDV7tUkPKirQA9Mt12V7b0R9ovkJ+tEaKY33yNUzh2k68wCEBPn8sJZpKAqPNOFFOa6YJ/kGuB604Hv1qs40Au1fsRxHmDTW7RFOYQcRY6KsixU3G21cORYBX7HL3/VYs" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_amm2ast.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_amm2ast.v new file mode 100644 index 0000000000..d089640bcc --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_amm2ast.v @@ -0,0 +1,181 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_amm2ast # + ( parameter + CFG_LOCAL_SIZE_WIDTH = 2 + ) + ( + clk, + reset_n, + amm_ready, + amm_cmd_size, + amm_cmd_wr, + amm_cmd_rd, + ast_cmd_ready, + ast_cmd_valid, + ast_wr_data_ready, + ast_wr_data_valid + ); + +localparam IDLE = 1'b0; +localparam GET_WDATA = 1'b1; + +input clk; +input reset_n; + +output amm_ready; +input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] amm_cmd_size; +input amm_cmd_wr; +input amm_cmd_rd; + +input ast_cmd_ready; +output ast_cmd_valid; +input ast_wr_data_ready; +output ast_wr_data_valid; + +reg int_amm_ready; +reg int_ast_wr_data_valid; +reg int_ast_cmd_valid; + +reg convert_state; +reg convert_state_nxt; +reg [CFG_LOCAL_SIZE_WIDTH - 1 : 0] count; +reg [CFG_LOCAL_SIZE_WIDTH - 1 : 0] count_nxt; + +wire ast_cmd_valid; +wire ast_wr_data_valid; +wire amm_ready; + + +always @(*) +begin + case (convert_state) + IDLE: + begin + int_amm_ready = ast_wr_data_ready & ast_cmd_ready; + int_ast_cmd_valid = (amm_cmd_wr | amm_cmd_rd) & ast_wr_data_ready & ast_cmd_ready; + + if (amm_cmd_wr) + begin + if (amm_cmd_size != {{(CFG_LOCAL_SIZE_WIDTH - 1){1'b0}},1'b1}) + begin + if (int_amm_ready == 1'b1) + begin + convert_state_nxt = GET_WDATA; + count_nxt = amm_cmd_size; + int_ast_wr_data_valid = 1'b1; + end + else + begin + convert_state_nxt = IDLE; + count_nxt = {CFG_LOCAL_SIZE_WIDTH{1'b0}}; + int_ast_wr_data_valid = 1'b0; + end + end + else + begin + count_nxt = {CFG_LOCAL_SIZE_WIDTH{1'b0}}; + convert_state_nxt = IDLE; + + if (int_amm_ready == 1'b1) + begin + int_ast_wr_data_valid = 1'b1; + end + else + begin + int_ast_wr_data_valid = 1'b0; + end + end + end + else + begin + if (amm_cmd_rd == 1'b1) + begin + int_ast_wr_data_valid = 1'b0; + count_nxt = {CFG_LOCAL_SIZE_WIDTH{1'b0}}; + convert_state_nxt = IDLE; + end + else + begin + int_ast_wr_data_valid = 1'b0; + count_nxt = {CFG_LOCAL_SIZE_WIDTH{1'b0}}; + convert_state_nxt = IDLE; + end + end + end + GET_WDATA: + begin + int_amm_ready = ast_wr_data_ready; + int_ast_cmd_valid = 1'b0; + + if (int_amm_ready == 1'b1) + begin + if (amm_cmd_wr) + begin + count_nxt = count - {{(CFG_LOCAL_SIZE_WIDTH - 1){1'b0}},1'b1}; + int_ast_wr_data_valid = 1'b1; + end + else + begin + count_nxt = count; + int_ast_wr_data_valid = 1'b0; + end + + if ((count == {{(CFG_LOCAL_SIZE_WIDTH-2){1'b0}},2'b10}) && (amm_cmd_wr == 1'b1)) + begin + convert_state_nxt = IDLE; + end + else + begin + convert_state_nxt = GET_WDATA; + end + end + else + begin + convert_state_nxt = GET_WDATA; + count_nxt = count; + int_ast_wr_data_valid = 1'b0; + end + end + endcase +end + +always @(posedge clk) +begin + if (!reset_n) + begin + convert_state <= IDLE; + end + else begin + convert_state <= convert_state_nxt; + end +end + +always @(posedge clk) +begin + count <= count_nxt; +end + + +assign amm_ready = int_amm_ready; +assign ast_wr_data_valid = int_ast_wr_data_valid; +assign ast_cmd_valid = int_ast_cmd_valid; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EDJKkf0NswlJB1vf587smpPbIBhSkXx1z3ffv5cRb9HXl9SopMPG9vpzWQo6XWMFLQ3uPpPv+jtNALNVw+JXfZ+1H3WW5mhsuFDl7ieIuSnGrSDMo3coAFqZN4Xi3FAZdVQycP3imHGPy7g3gYUqsqbrUKoYbvkFQ4ao5Itr6mIqeZVW5VATTjs0BYvGyI8b8G6IrS6AIWXRZB+Z9laPhvZsV816XG6M75XB8Kx9VNpgfVPXFdqhbLk0KblbB7SPM5DFn5we8bYA2bIPFZ2QQtPpawsCStHyaS7VFzARovJqXODZmqFTbuHSETSoWCydU3gGTLnXokjEDgr20Tu+LmwYefdCr8cecLT8xGVUWACyTIvnl2CpQ1J9YG/k8VUpFL2qh6Lobsp0J7F60z8JeyYjhemH1ZfTgy38vdYOS3TQijS9IddTzbJP9xlic12M3ZI6rn7WQkr2kkzJLrn6nQZoyTeW6glf92aLQ9ZJIlzC4W5ihe8uA/ojMhTxuf3I1a/SVIeS/gd5CQlmu0qhyWX4FipF9OB9j121OgZi9Nei0PK34ayrfAJfrP4HlBUdoea6qzn1+6quFVdNH/mu2VajDOyOvN2ewwkrq7LH+0NE7jDYtEjK3LN49S667PwFcmCtzVFD047++35n4iIApJCnQMW+nwrj4X1yS6LV+vJvijhZ4sO7oEV3G5cc+r02qgpr4TJgQ8XKWH9zn0Ix/k/LqL+i7bIfjZYyNpX9Msrg/iFmJUf9jtjJUWNLx+jBj0ReFTOjkbITQPhBB/8w/Fy" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_cb.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_cb.v new file mode 100644 index 0000000000..1fbff3d1b1 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_cb.v @@ -0,0 +1,31 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_cb +#(parameter DAT='d 8) ( + + input wire [DAT-1:0] di, + output wire dout + ); + + assign dout = ^di; +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EBb+GwNRZYJnVDIiruXV09Fs7UBAg5nhC5sN9VFWsWgS9dfRDj2wBpGRfwyj8zHzy6X6u5C5UJAFRGc7jFDI6rnoQmqYWZi06FmQQPfMI0O6Hfz3/iyjufPmNLu4SQ6xqT7cf66w17yqjnijDB1P83cIZrRkNAl4kPvU1s/MMcPWatQLZwcEwy3iQlNiCZy3KqnTom5EnueV5I2PEW7CoQU0Di1SA9Rjwtzb8PrbXF0Jtaf0mCyvb6vop9RgKk8HtUsXWWeaQ+fw+OeZmMGeOHFWw8oFc1ihkFba7xawoQQvlosZ8A6UvdZ9ggV0ILFlWiuFdaz3JBzXm1kNp2oCegZWeCDKZDueE4Ke+zzf6hrhNAs1M6upgpLco7jWnXKnf86KzwOGCpcSmT9MZIzuEl6Kel3NlJg2CengBGBV+9GadH65qKGjeXF1U4Nrff+0tRxKjCg2ySL4XmqbCZ1FiIPBZZn70+U7h7peCmGPGdcIjFeWzIbnGHV2xmoZTrBYRV4dvYECp6AsUGCQh6/EeM2wxjD6wSVxH4mNN/GtALbga4QacKyy0CDUXg20wVnYP5lRg2sHzAwTrIvg7h2aWQ0nu8Id0+JngU/uajgHHlF0P8Saf+IJJz7uWiOMsISVgIcRWTtA7+qPni3HHok/Cjqx9MmF7yHL3SHVMRR8gIkOCrXu2NgpKSAMrJAj7aVAU4WWrccsG8lR4SLYu4VH1/fnABmGTC4TNgJWLPN4qGLt+kBexTMYMWHXFq3/9HOyQhfUVBcHw/wSQBP5QecqdB6" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder.v new file mode 100644 index 0000000000..5035739c86 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder.v @@ -0,0 +1,256 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_decoder # + ( parameter + CFG_ECC_DATA_WIDTH = 72, + CFG_ECC_CODE_WIDTH = 8, + CFG_ADDR_WIDTH = 35, + + CFG_PORT_WIDTH_DRAM_DATA_WIDTH = 7, + CFG_PORT_WIDTH_LOCAL_DATA_WIDTH = 7, + CFG_PORT_WIDTH_ENABLE_ECC = 1, + + CFG_ADDR_ENCODE_ENABLED = 0 + ) + ( + ctl_clk, + ctl_reset_n, + + cfg_local_data_width, + cfg_dram_data_width, + cfg_enable_ecc, + + input_data, + input_addr, + input_data_valid, + output_data, + output_data_valid, + output_ecc_code, + + err_corrected, + err_detected, + err_fatal, + err_sbe, + err_addr_detected, + err_addr + ); + +localparam CFG_LOCAL_DATA_WIDTH = CFG_ECC_DATA_WIDTH - CFG_ECC_CODE_WIDTH; + +input ctl_clk; +input ctl_reset_n; + +input [CFG_PORT_WIDTH_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width; +input [CFG_PORT_WIDTH_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width; +input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc; + +input [CFG_ECC_DATA_WIDTH - 1 : 0] input_data; +input [CFG_ADDR_WIDTH - 1 : 0] input_addr; +input input_data_valid; + +output [CFG_ECC_DATA_WIDTH - 1 : 0] output_data; +output output_data_valid; +output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code; + +output err_corrected; +output err_detected; +output err_fatal; +output err_sbe; +output err_addr_detected; +output [CFG_ADDR_WIDTH - 1 : 0] err_addr; + + wire [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input; + + reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code; + + reg [CFG_ECC_DATA_WIDTH - 1 : 0] output_data; + reg output_data_valid; + reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code; + + reg err_corrected; + reg err_detected; + reg err_fatal; + reg err_sbe; + reg err_addr_detected; + reg [CFG_ADDR_WIDTH - 1 : 0] err_addr; + + wire int_err_corrected; + wire int_err_detected; + wire int_err_fatal; + wire int_err_sbe; + wire int_err_addr_detected; + wire [CFG_ADDR_WIDTH - 1 : 0] int_err_addr; + reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code; + + wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_input; + wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] decoder_output; + reg decoder_output_valid; + + wire [CFG_ADDR_WIDTH - 1 : 0] output_addr; + + genvar i; + + generate + for (i = 0;i < CFG_ECC_DATA_WIDTH;i = i + 1) + begin : decoder_input_per_data_width + always @ (*) + begin + if (i < cfg_local_data_width) + int_decoder_input_data [i] = input_data [i]; + else + int_decoder_input_data [i] = 1'b0; + end + + always @ (*) + begin + if (i >= cfg_local_data_width && i < cfg_dram_data_width) + int_decoder_input_ecc_code [i] = input_data [i]; + else + int_decoder_input_ecc_code [i] = 1'b0; + end + end + endgenerate + + always @ (*) + begin + or_int_decoder_input_ecc_code [CFG_ECC_CODE_WIDTH - 1 : 0] = int_decoder_input_ecc_code [CFG_ECC_CODE_WIDTH - 1 : 0]; + end + + generate + for (i = 1;i < 9;i = i + 1) + begin : ecc_code_per_code_width + always @ (*) + begin + or_int_decoder_input_ecc_code [(i + 1) * CFG_ECC_CODE_WIDTH - 1 : i * CFG_ECC_CODE_WIDTH ] = + int_decoder_input_ecc_code [(i + 1) * CFG_ECC_CODE_WIDTH - 1 : i * CFG_ECC_CODE_WIDTH ] | + or_int_decoder_input_ecc_code [i * CFG_ECC_CODE_WIDTH - 1 : (i - 1) * CFG_ECC_CODE_WIDTH]; + end + end + endgenerate + + generate + if (CFG_ECC_DATA_WIDTH > 72) + begin + assign int_decoder_input = {{(CFG_ECC_DATA_WIDTH - 72){1'b0}}, or_int_decoder_input_ecc_code [71 : 64], int_decoder_input_data [63 : 0]}; + end + else + begin + assign int_decoder_input = {or_int_decoder_input_ecc_code [71 : 64], int_decoder_input_data [63 : 0]}; + end + endgenerate + + assign decoder_input = int_decoder_input; + + always @ (*) + begin + decoder_output_valid = input_data_valid; + end + + always @ (*) + begin + if (cfg_enable_ecc) + int_output_ecc_code = or_int_decoder_input_ecc_code [71 : 64]; + else + int_output_ecc_code = {CFG_ECC_CODE_WIDTH{1'b0}}; + end + + always @ (*) + begin + if (cfg_enable_ecc) + begin + output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; + end + else + begin + output_data = int_decoder_input_data; + end + + if (cfg_enable_ecc) + begin + err_corrected = int_err_corrected; + err_detected = int_err_detected; + err_fatal = int_err_fatal; + err_sbe = int_err_sbe; + err_addr_detected = int_err_addr_detected; + err_addr = int_err_addr; + end + else + begin + err_corrected = 1'b0; + err_detected = 1'b0; + err_fatal = 1'b0; + err_sbe = 1'b0; + err_addr_detected = 1'b0; + err_addr = {CFG_ADDR_WIDTH{1'b0}}; + end + + output_data_valid = input_data_valid; + output_ecc_code = int_output_ecc_code; + end + + + + generate + if (CFG_LOCAL_DATA_WIDTH > 64) + begin + assign decoder_output [CFG_LOCAL_DATA_WIDTH - 1 : 64] = {(CFG_LOCAL_DATA_WIDTH - 64){1'b0}}; + end + endgenerate + + generate + if (CFG_ADDR_ENCODE_ENABLED == 1) + begin + fmiohmc_ecc_decoder_112 # + ( + .DI (72 + CFG_ADDR_WIDTH ), + .ADDR (CFG_ADDR_WIDTH ), + .DOUT (64 + CFG_ADDR_WIDTH ) + ) + decoder_inst + ( + .data ({decoder_input [72 - 1 : 64], input_addr, decoder_input [64 - 1 : 0]} ), + .err_corrected (int_err_corrected ), + .err_detected (int_err_detected ), + .err_fatal (int_err_fatal ), + .err_sbe (int_err_sbe ), + .err_addr_detected (int_err_addr_detected ), + .err_addr (int_err_addr ), + .q ({output_addr, decoder_output [64 - 1 : 0]} ) + ); + end + else + begin + fmiohmc_ecc_decoder_64 decoder_inst + ( + .data (decoder_input [72 - 1 : 0]), + .err_corrected (int_err_corrected ), + .err_detected (int_err_detected ), + .err_fatal (int_err_fatal ), + .err_sbe (int_err_sbe ), + .q (decoder_output [64 - 1 : 0]) + ); + + assign int_err_addr_detected = 1'b0; + assign int_err_addr = {CFG_ADDR_WIDTH{1'b0}}; + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EAWtIy3hGdLIc4uDo0lbyErkHSivqnASZaK3YwnZhsdx/KE00F8cAu051oZQG7NMqhpwPzgNxes2fNKDntOeA9SlW72axvrVepM/JwIBJUQCllWyr8Km2I6CYsHsHpph7ejHp9P8lI07/hPVVvWEaVzKLfH3LtvQ+N4KvZrweUF5mJKAIf8/L+J75HpEu1e8XguudS29QxKF8sf6p5GcYUxAUqPbYIZ/vMfevXL+WdoINbiimXq+PaDx/2RU+Q4MX/Hiq7IQR67eFuGTk23bXDmJ349NJBlFT+CxvO0dMWB0F9XM1BXBOS/3bD70Sn2t20wdseBO2f1rlj3xXlkbE5g3J487Ef/Eax4ec7/EncMmjszmIimQzXt2qo8MgXLHGnbQj47MCXtg/Ntkd44HyLXGUJY526uNqtGA04Sacwok5KpM6/XRYMUl2kRhwTDOxtmuV3lyfBC/o0Gp59C1s6s+gl0sLko+8xG0iAmZmMkQD2U92LJu/X9K7tpMJRCavnpts3VOaMZQFjRsdG0gn+8Lh6x7JBUfTU30AlgA8nSaQrU2J9Vsw7qFZIgM3nGq7v3JNVms3yGZVpQNijL/fBlnqEivtoHWjpcgT63Cw8QdnAoWtQuK9HN8qvMXdFJ46D7tpHHFcKFq3dPcy2OhPvVmGCAnr++6QRf+UlDFBQB/4BW9EQPmZ6kTLqnXis1bQySaRTrQuuGTG+Gaj63QXR2EtQ5W464m3vfbbicM8n9v33qAtalGU34JIc8+wZ471DCeQiQTlFM1BBv3Gil9m0m" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_112.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_112.v new file mode 100644 index 0000000000..9657dd7979 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_112.v @@ -0,0 +1,93 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_decoder_112 # +( parameter + DI = 106, + ADDR = 34, + DOUT = 98 +) +( + data, + err_corrected, + err_detected, + err_fatal, + err_sbe, + err_addr_detected, + err_addr, + q +); + +localparam PARITY = 8; +localparam CODE = 8; + +input [DI - 1 : 0] data; +output err_corrected; +output err_detected; +output err_fatal; +output err_sbe; +output err_addr_detected; +output [ADDR - 1 : 0] err_addr; +output [DOUT - 1 : 0] q; + +wire err_dbe; + + +wire [111 : 0] data_e; +wire [111 : 0] data_i; + +generate +if(DOUT==112) + assign data_e = data[DOUT-1:0]; +else + assign data_e = {{(112 - DOUT){1'b0}},data[DOUT-1:0]}; +endgenerate + +assign data_i = {data_e[111:PARITY],~data_e[PARITY-1],data_e[PARITY-2:1],~data_e[0]}; + +wire [PARITY - 1 : 0] parity_i; +assign parity_i = data[DI-1:DOUT]; + +wire [PARITY - 1 : 0] sb; + +fmiohmc_ecc_pcm_112 ecc_pcm ( + .di(data_i), + .sb(parity_i), + .dout(sb) +); + + + +wire [111:0] sv; + +fmiohmc_ecc_sv_112 svec (.di(sb), .dout(sv)); + +assign q = data[DOUT-1:0] ^ sv[DOUT-1:0]; + +assign err_sbe = |sb && ^sb; +assign err_dbe = |sb && ~^sb; + +assign err_detected = err_sbe || err_dbe; +assign err_corrected = err_sbe; +assign err_fatal = err_dbe; +assign err_addr_detected = err_sbe && |sv[DOUT-1:DOUT-ADDR]; +assign err_addr = data[DOUT-1:DOUT-ADDR] ^ sv[DOUT-1:DOUT-ADDR]; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EASexZBB37JqpNvLi4Wkp3MH+KkbcPA6dqOmY6A030D8x94gM/DpI2Q/D+lnCQc1HrwxZTGBhq1FkNH792u4KtulOdyoE69LiqHBnt3c9Zc77Y3gFKt6wovI7XsxQiA0WDqXE+ro+a9ScqcgB2jNkOhmcOVcGSsf4nJJSNG1exD+Qxu7013yzDNPGBQWc0BC5sfbQapEhFDOMgiD78RZo+qCra8hm8F2o8uXQgWq01YjCiKCkJWJzHObZ+7lve/AniYNScx//OlHmBto/YdV1Ea+2EDgfOv6O+oZA+fVE1XOh4JoQ//Ew+HUqWxYjz/cd0MBHO75+wdlQU8SD/VrQ8LrKqVAM1cMwk1lEKxWHS8EERT0mDxHEuSGEqQ9Bq+vLd7Ewaj5SQqynifCKf7WE2aY+RKlPmTgIJf5WZXkqNUUxcta+KjO6cXN4TbDjb+Pyb6NuEFH7i7uPPXFT8fwH1Z0y4FBgNNUchynY2xmflPBrHF3NOZiBv8QmGTgar/d5HB1h4Ll1RzKwlN1Bg+IX5uBeSwt8DAWLN5THW4x4be6rhvLzduJt1d2kNs5zx114H1LQQnOYfmssnGRUsThxyWL5XyRzH2vofon6GKL6VHKJNQVW6ieOnmeC5L8poCGne2Zy5XZC5PQONsAX84yCtyNACFRaUMe073Gn5bRxszwjj8QknP8CnwDTLxTRZtITHe0aVBavOSqRaSjGCuyP2JjPN+VFHEJiQWQ3eMNfsOzaYHXqkLOJ4UwcVihvVP9ISApQwJ1ilqy3B8JmnJeJ/I" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64.v new file mode 100644 index 0000000000..008b2d3660 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64.v @@ -0,0 +1,64 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + + + + +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +//altera message_off 10463 + + + + +`timescale 1 ps / 1 ps +module fmiohmc_ecc_decoder_64 ( + data, + err_corrected, + err_detected, + err_fatal, + err_sbe, + q)/* synthesis synthesis_clearbox = 1 */; + + input [71:0] data; + output err_corrected; + output err_detected; + output err_fatal; + output err_sbe; + output [63:0] q; + + wire sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire sub_wire4; + wire [63:0] sub_wire3; + wire err_detected = sub_wire0; + wire err_fatal = sub_wire1; + wire err_corrected = sub_wire2; + wire err_sbe = sub_wire4; + wire [63:0] q = sub_wire3[63:0]; + + fmiohmc_ecc_decoder_64_altecc_decoder iohmc_ecc_decoder_64_altecc_decoder_component ( + .data (data), + .err_detected (sub_wire0), + .err_fatal (sub_wire1), + .err_corrected (sub_wire2), + .err_sbe (sub_wire4), + .q (sub_wire3)); + +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EAUMKAt1mmYg3PY9ycWv2MGbuI4C+9okTgCG7iF5iEXDiJSguaAP/gcb2Pn1mwe+0dRPsDFFp5utgX18MMQ/MhLKFhVG1uUiWUJYyospLN0F5+8aM2y0XGia78C+Hzt1rH92rxquyAZUp09mUShEekbhtIPExUQkxWwq67M8hO4WgSF4Kqbkboc6+LjpubOrEAll2t4l8BVcI24HR5+4m+Hafb8Cx7khiX7xY0ExsA4SmkKOxs2xXuPWovA5xWyMeO9zfh+M1ie6LlVB6Qoo31qWBTMLds7dKOBxbAmcYF1Po//kQMDX8wB+me6FDLjvH3r25lTzQxLPdbaQ1s648p/KQIChW2+dYamQZGWPFHkb+tDLBPjeS2+VAnPkExAPcCU8aQPtVVuQgspZrRCOyiYlvpZJ+VDxD+MFDp98l014L1OuGfx7SpPT3lzaIfvwBVDKgASysKVwZwNswzV908eW5S2BXdTjc34oARt6YQdJss1HbUVBv9+D3OafIE7dwJhyBk8NV594PUZzhPg0u61rCuOU3CUR3UVwHTOSgKhsIgIz+RXTV3CGrAtcESmITRA9V7KSat/KmFFrG7/CjOywg392ljew6Fx3xRQvdqm9T7aXW39h1PyaQfgG2fAekfBq7g/35i4fz904VyQk9Qq7EfRhbzlx4nu9js1OL281F2yBmQ2pjDJNrsjpMancNwOw2Cy8npM0LtwPROWzwG8xMq2Wjc2nWMSsVrR/zSUwEzovUfmRDd1QTFNH0h3itCyA634CJuT9suCqz/TAmB9" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_altecc_decoder.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_altecc_decoder.v new file mode 100644 index 0000000000..f2204cbdd8 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_altecc_decoder.v @@ -0,0 +1,222 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// synthesis_resources = lut 144 mux21 64 +`timescale 1 ps / 1 ps +module fmiohmc_ecc_decoder_64_altecc_decoder + ( + data, + err_corrected, + err_detected, + err_fatal, + err_sbe, + q) /* synthesis synthesis_clearbox=1 */; + input [71:0] data; + output err_corrected; + output err_detected; + output err_fatal; + output err_sbe; + output [63:0] q; + + wire [127:0] wire_error_bit_decoder_eq; + wire wire_mux21_0_dataout; + wire wire_mux21_1_dataout; + wire wire_mux21_10_dataout; + wire wire_mux21_11_dataout; + wire wire_mux21_12_dataout; + wire wire_mux21_13_dataout; + wire wire_mux21_14_dataout; + wire wire_mux21_15_dataout; + wire wire_mux21_16_dataout; + wire wire_mux21_17_dataout; + wire wire_mux21_18_dataout; + wire wire_mux21_19_dataout; + wire wire_mux21_2_dataout; + wire wire_mux21_20_dataout; + wire wire_mux21_21_dataout; + wire wire_mux21_22_dataout; + wire wire_mux21_23_dataout; + wire wire_mux21_24_dataout; + wire wire_mux21_25_dataout; + wire wire_mux21_26_dataout; + wire wire_mux21_27_dataout; + wire wire_mux21_28_dataout; + wire wire_mux21_29_dataout; + wire wire_mux21_3_dataout; + wire wire_mux21_30_dataout; + wire wire_mux21_31_dataout; + wire wire_mux21_32_dataout; + wire wire_mux21_33_dataout; + wire wire_mux21_34_dataout; + wire wire_mux21_35_dataout; + wire wire_mux21_36_dataout; + wire wire_mux21_37_dataout; + wire wire_mux21_38_dataout; + wire wire_mux21_39_dataout; + wire wire_mux21_4_dataout; + wire wire_mux21_40_dataout; + wire wire_mux21_41_dataout; + wire wire_mux21_42_dataout; + wire wire_mux21_43_dataout; + wire wire_mux21_44_dataout; + wire wire_mux21_45_dataout; + wire wire_mux21_46_dataout; + wire wire_mux21_47_dataout; + wire wire_mux21_48_dataout; + wire wire_mux21_49_dataout; + wire wire_mux21_5_dataout; + wire wire_mux21_50_dataout; + wire wire_mux21_51_dataout; + wire wire_mux21_52_dataout; + wire wire_mux21_53_dataout; + wire wire_mux21_54_dataout; + wire wire_mux21_55_dataout; + wire wire_mux21_56_dataout; + wire wire_mux21_57_dataout; + wire wire_mux21_58_dataout; + wire wire_mux21_59_dataout; + wire wire_mux21_6_dataout; + wire wire_mux21_60_dataout; + wire wire_mux21_61_dataout; + wire wire_mux21_62_dataout; + wire wire_mux21_63_dataout; + wire wire_mux21_7_dataout; + wire wire_mux21_8_dataout; + wire wire_mux21_9_dataout; + wire data_bit; + wire [63:0] data_t; + wire [71:0] data_wire; + wire [127:0] decode_output; + wire err_corrected_wire; + wire err_detected_wire; + wire err_fatal_wire; + wire [35:0] parity_01_wire; + wire [17:0] parity_02_wire; + wire [8:0] parity_03_wire; + wire [3:0] parity_04_wire; + wire [1:0] parity_05_wire; + wire [30:0] parity_06_wire; + wire [6:0] parity_07_wire; + wire parity_bit; + wire [70:0] parity_final_wire; + wire [6:0] parity_t; + wire [63:0] q_wire; + wire syn_bit; + wire syn_e; + wire [5:0] syn_t; + wire [7:0] syndrome; + + fmiohmc_ecc_decoder_64_decode error_bit_decoder + ( + .data(syndrome[6:0]), + .eq(wire_error_bit_decoder_eq)); + assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0]; + assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1]; + assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10]; + assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11]; + assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12]; + assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13]; + assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14]; + assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15]; + assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16]; + assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17]; + assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18]; + assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19]; + assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2]; + assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20]; + assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21]; + assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22]; + assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23]; + assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24]; + assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25]; + assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26]; + assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27]; + assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28]; + assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29]; + assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3]; + assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30]; + assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31]; + assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_wire[32]) : data_wire[32]; + assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_wire[33]) : data_wire[33]; + assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_wire[34]) : data_wire[34]; + assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_wire[35]) : data_wire[35]; + assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_wire[36]) : data_wire[36]; + assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_wire[37]) : data_wire[37]; + assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_wire[38]) : data_wire[38]; + assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_wire[39]) : data_wire[39]; + assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4]; + assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_wire[40]) : data_wire[40]; + assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_wire[41]) : data_wire[41]; + assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_wire[42]) : data_wire[42]; + assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_wire[43]) : data_wire[43]; + assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_wire[44]) : data_wire[44]; + assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_wire[45]) : data_wire[45]; + assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_wire[46]) : data_wire[46]; + assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_wire[47]) : data_wire[47]; + assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_wire[48]) : data_wire[48]; + assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_wire[49]) : data_wire[49]; + assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5]; + assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_wire[50]) : data_wire[50]; + assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_wire[51]) : data_wire[51]; + assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_wire[52]) : data_wire[52]; + assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_wire[53]) : data_wire[53]; + assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_wire[54]) : data_wire[54]; + assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_wire[55]) : data_wire[55]; + assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_wire[56]) : data_wire[56]; + assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_wire[57]) : data_wire[57]; + assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_wire[58]) : data_wire[58]; + assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_wire[59]) : data_wire[59]; + assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6]; + assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_wire[60]) : data_wire[60]; + assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_wire[61]) : data_wire[61]; + assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_wire[62]) : data_wire[62]; + assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_wire[63]) : data_wire[63]; + assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7]; + assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8]; + assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9]; + assign + data_bit = data_t[63], + data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2] + | decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]}, + data_wire = data, + decode_output = wire_error_bit_decoder_eq, + err_corrected = err_corrected_wire, + err_corrected_wire = ((syn_bit & syn_e) & data_bit), + err_detected = err_detected_wire, + err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))), + err_fatal = err_fatal_wire, + err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)), + err_sbe = syn_e, + parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]}, + parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])}, + parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])}, + parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])}, + parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])}, + parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])}, + parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])}, + parity_bit = parity_t[6], + parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^ + parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])}, + parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]}, + q = q_wire, + q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout}, + syn_bit = syn_t[5], + syn_e = syndrome[7], + syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])}, + syndrome = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]}; +endmodule + + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EA73QiLCXgG0VHLIgrnIsEzGR4uJPhEW7R12DXbG11l/OuorSiIync0DJKc15XeAvkK4JvD/rDtt0gtd5NU7X8m9pryrQwQigZkDaPU3B0yNR4NXsQ1p1Jv4tIz4/BZPt9nw9+N7cB3CqfhBZK79r/BFe8xl2iFeeu5KH3AYOLb/CiSChpoSFaDkEXMk3WI5kQ1h7Iz7B6uWJQ+3TLblLgkALdK8UH79idI4I337luG09OzWrvwN/DIYy5IaZmXCx0jrQoSeNkDjZZKQn84tIXqWFYKU0D4vRazHQ0wMXgiKgJdYRVcBpFdlz0TZxwabIOHlyXsjnnjy33lAQCbOF8iyqoM3Ig6Wc7diFGor+qnJk1tDsxSi1pjD+YAdyAbntJnEdvgy6CusJmVnggBdSz6DyPdGUF0DJ797X83yVPXg2LKyEeeTFiJ9ZoOYprD/A4gFa8ud8JTRzkZN9IC5wmAx3iq3rkyMd50fDsjHVv9RIAinrlt/+J4FN+ZdiF2twE9apFvLD1oXaxcFP8cTjj7bvwqtvuk/zUCWZU+bvV2Sea3XFBwCuJ7EXW5qNnHBA3OBFI4ybmMiXWPhsVEmqGGj/z99gO1hnCopTN3d3yHXg4uc+ovMpB9lyfLTv3MoPHnbmZGSEu+mP2Hg9GpW68DZLgTyrTCzp8tay//yT43FU9SCFNz1g566gYpfuU69+u4nwfLvygtdELonmjM6JGRsDRUJs9mD7hLjLaDxJ+c/1IFXDqk2sMAZ0WuNKq8lYRI9jm7yNREB3ced/IVstrz" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_decode.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_decode.v new file mode 100644 index 0000000000..ca00d51202 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_decode.v @@ -0,0 +1,337 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// synthesis_resources = lut 144 +`timescale 1 ps / 1 ps +module fmiohmc_ecc_decoder_64_decode + ( + data, + eq) /* synthesis synthesis_clearbox=1 */; + input [6:0] data; + output [127:0] eq; +`ifndef ALTERA_RESERVED_QIS +`endif +`ifndef ALTERA_RESERVED_QIS +`endif + + wire [5:0] data_wire; + wire enable_wire1; + wire enable_wire2; + wire [127:0] eq_node; + wire [63:0] eq_wire1; + wire [63:0] eq_wire2; + wire [3:0] w_anode1006w; + wire [3:0] w_anode1018w; + wire [3:0] w_anode1029w; + wire [3:0] w_anode1040w; + wire [3:0] w_anode1050w; + wire [3:0] w_anode1060w; + wire [3:0] w_anode1070w; + wire [3:0] w_anode1080w; + wire [3:0] w_anode1090w; + wire [3:0] w_anode1100w; + wire [3:0] w_anode1111w; + wire [3:0] w_anode1122w; + wire [3:0] w_anode1133w; + wire [3:0] w_anode1143w; + wire [3:0] w_anode1153w; + wire [3:0] w_anode1163w; + wire [3:0] w_anode1173w; + wire [3:0] w_anode1183w; + wire [3:0] w_anode1193w; + wire [3:0] w_anode1204w; + wire [3:0] w_anode1215w; + wire [3:0] w_anode1226w; + wire [3:0] w_anode1236w; + wire [3:0] w_anode1246w; + wire [3:0] w_anode1256w; + wire [3:0] w_anode1266w; + wire [3:0] w_anode1276w; + wire [3:0] w_anode1286w; + wire [3:0] w_anode1297w; + wire [3:0] w_anode1308w; + wire [3:0] w_anode1319w; + wire [3:0] w_anode1329w; + wire [3:0] w_anode1339w; + wire [3:0] w_anode1349w; + wire [3:0] w_anode1359w; + wire [3:0] w_anode1369w; + wire [3:0] w_anode1379w; + wire [3:0] w_anode1390w; + wire [3:0] w_anode1401w; + wire [3:0] w_anode1412w; + wire [3:0] w_anode1422w; + wire [3:0] w_anode1432w; + wire [3:0] w_anode1442w; + wire [3:0] w_anode1452w; + wire [3:0] w_anode1462w; + wire [3:0] w_anode1472w; + wire [3:0] w_anode1483w; + wire [3:0] w_anode1494w; + wire [3:0] w_anode1505w; + wire [3:0] w_anode1515w; + wire [3:0] w_anode1525w; + wire [3:0] w_anode1535w; + wire [3:0] w_anode1545w; + wire [3:0] w_anode1555w; + wire [3:0] w_anode1565w; + wire [3:0] w_anode1576w; + wire [3:0] w_anode1587w; + wire [3:0] w_anode1598w; + wire [3:0] w_anode1608w; + wire [3:0] w_anode1618w; + wire [3:0] w_anode1628w; + wire [3:0] w_anode1638w; + wire [3:0] w_anode1648w; + wire [3:0] w_anode1658w; + wire [3:0] w_anode1670w; + wire [3:0] w_anode1681w; + wire [3:0] w_anode1698w; + wire [3:0] w_anode1708w; + wire [3:0] w_anode1718w; + wire [3:0] w_anode1728w; + wire [3:0] w_anode1738w; + wire [3:0] w_anode1748w; + wire [3:0] w_anode1758w; + wire [3:0] w_anode1770w; + wire [3:0] w_anode1781w; + wire [3:0] w_anode1792w; + wire [3:0] w_anode1802w; + wire [3:0] w_anode1812w; + wire [3:0] w_anode1822w; + wire [3:0] w_anode1832w; + wire [3:0] w_anode1842w; + wire [3:0] w_anode1852w; + wire [3:0] w_anode1863w; + wire [3:0] w_anode1874w; + wire [3:0] w_anode1885w; + wire [3:0] w_anode1895w; + wire [3:0] w_anode1905w; + wire [3:0] w_anode1915w; + wire [3:0] w_anode1925w; + wire [3:0] w_anode1935w; + wire [3:0] w_anode1945w; + wire [3:0] w_anode1956w; + wire [3:0] w_anode1967w; + wire [3:0] w_anode1978w; + wire [3:0] w_anode1988w; + wire [3:0] w_anode1998w; + wire [3:0] w_anode2008w; + wire [3:0] w_anode2018w; + wire [3:0] w_anode2028w; + wire [3:0] w_anode2038w; + wire [3:0] w_anode2049w; + wire [3:0] w_anode2060w; + wire [3:0] w_anode2071w; + wire [3:0] w_anode2081w; + wire [3:0] w_anode2091w; + wire [3:0] w_anode2101w; + wire [3:0] w_anode2111w; + wire [3:0] w_anode2121w; + wire [3:0] w_anode2131w; + wire [3:0] w_anode2142w; + wire [3:0] w_anode2153w; + wire [3:0] w_anode2164w; + wire [3:0] w_anode2174w; + wire [3:0] w_anode2184w; + wire [3:0] w_anode2194w; + wire [3:0] w_anode2204w; + wire [3:0] w_anode2214w; + wire [3:0] w_anode2224w; + wire [3:0] w_anode2235w; + wire [3:0] w_anode2246w; + wire [3:0] w_anode2257w; + wire [3:0] w_anode2267w; + wire [3:0] w_anode2277w; + wire [3:0] w_anode2287w; + wire [3:0] w_anode2297w; + wire [3:0] w_anode2307w; + wire [3:0] w_anode2317w; + wire [3:0] w_anode2328w; + wire [3:0] w_anode2339w; + wire [3:0] w_anode2350w; + wire [3:0] w_anode2360w; + wire [3:0] w_anode2370w; + wire [3:0] w_anode2380w; + wire [3:0] w_anode2390w; + wire [3:0] w_anode2400w; + wire [3:0] w_anode2410w; + wire [3:0] w_anode912w; + wire [3:0] w_anode929w; + wire [3:0] w_anode946w; + wire [3:0] w_anode956w; + wire [3:0] w_anode966w; + wire [3:0] w_anode976w; + wire [3:0] w_anode986w; + wire [3:0] w_anode996w; + wire [2:0] w_data1669w; + wire [2:0] w_data910w; + + assign + data_wire = data[5:0], + enable_wire1 = (~ data[6]), + enable_wire2 = data[6], + eq = eq_node, + eq_node = {eq_wire2[63:0], eq_wire1}, + eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}}, + eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}}, + w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]}, + w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1}, + w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]}, + w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]}, + w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]}, + w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]}, + w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]}, + w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]}, + w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]}, + w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]}, + w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1}, + w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]}, + w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]}, + w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]}, + w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]}, + w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]}, + w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]}, + w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]}, + w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]}, + w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1}, + w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]}, + w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]}, + w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]}, + w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]}, + w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]}, + w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]}, + w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]}, + w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]}, + w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1}, + w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]}, + w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]}, + w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]}, + w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]}, + w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]}, + w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]}, + w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]}, + w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]}, + w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1}, + w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]}, + w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]}, + w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]}, + w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]}, + w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]}, + w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]}, + w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]}, + w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]}, + w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1}, + w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]}, + w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]}, + w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]}, + w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]}, + w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]}, + w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]}, + w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]}, + w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]}, + w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1}, + w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]}, + w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]}, + w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]}, + w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]}, + w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]}, + w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]}, + w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]}, + w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]}, + w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2}, + w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]}, + w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]}, + w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]}, + w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]}, + w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]}, + w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]}, + w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]}, + w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]}, + w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2}, + w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]}, + w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]}, + w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]}, + w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]}, + w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]}, + w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]}, + w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]}, + w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]}, + w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2}, + w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]}, + w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]}, + w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]}, + w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]}, + w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]}, + w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]}, + w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]}, + w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]}, + w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2}, + w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]}, + w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]}, + w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]}, + w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]}, + w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]}, + w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]}, + w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]}, + w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]}, + w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2}, + w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]}, + w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]}, + w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]}, + w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]}, + w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]}, + w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]}, + w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]}, + w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]}, + w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2}, + w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]}, + w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]}, + w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]}, + w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]}, + w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]}, + w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]}, + w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]}, + w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]}, + w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2}, + w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]}, + w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]}, + w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]}, + w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]}, + w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]}, + w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]}, + w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]}, + w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]}, + w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2}, + w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]}, + w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]}, + w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]}, + w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]}, + w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]}, + w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]}, + w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]}, + w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]}, + w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1}, + w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]}, + w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]}, + w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]}, + w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]}, + w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]}, + w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]}, + w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]}, + w_data1669w = data_wire[2:0], + w_data910w = data_wire[2:0]; +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EDQ3V5dS+haV2o+7y3pkcZ84vOnh7eIuMPAAHx2IRU5qV/ure+8eKMDJURDpxTVVVF6EXaMED6dq1DoiAPXdmpFK5YM+6zqv5a29dSzCNtwRFTNA+gmVjFUjXk2WTce/cAihtcfy0Qaxoq2DzNKfJMoo9ZAwL3FgR6EdMW3OAY+o5LRNSgWt6unDPUtdw5YmTbLu1wKNbraH1EaNqhTnH1YviSLcGz+72vN/pmoXrRuwSrrkJiMtu2r8c/v1DYD1neUvRSw2slhTX/Wq4cB8od3bveWltCckWmFSQ9V4k8ECbS9XwYKGhDLFQT8r98+dFI261Z1HvOHGkm4hDPvgdmM1UsW9FJN05dXZffw71hPGNfGbfMPouWr4Dnmz1kMTJVdX30XcqeQyU3SL4HbsA0wrnL8E3S1zDLiUalYjUaT8G0JxoWGVqDEdr1iAh0UMQpNMiqtB/QvtnYi43iqiXUlhN7YnPBl2yIm1idpQVjGOrDGrQorq9cIiLgohD/pR4b1JgHFR5/AfNOkjOhin6b1Y+GBpNdSFm6cVf5xIIYcFzmXopJ5KCqz/XxCKRdnoy++BAMGW2Kkr80teVOb4I4RcSo/e8d3fUjna3kLyuLHx5hzHg5Do81OzM7LSDxJ0SUvHY0L3LXNdIszC7WHGjsmVbUXHq7az0PJwmwz3CMnK9cC0UQXOqMyru0PFyW/IyIA+NQm6+hl6Id7/4RAog4+W7ddt4dK50Mj/ldRdce8nEXeZsBxrgBP3VnyNm2EZtiNipdyBrm9wBGkO0p8MO6s" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder.v new file mode 100644 index 0000000000..02e91c7084 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder.v @@ -0,0 +1,160 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_encoder # + ( parameter + CFG_ECC_DATA_WIDTH = 72, + CFG_ECC_CODE_WIDTH = 8, + CFG_ADDR_WIDTH = 35, + + CFG_PORT_WIDTH_DRAM_DATA_WIDTH = 7, + CFG_PORT_WIDTH_LOCAL_DATA_WIDTH = 7, + CFG_PORT_WIDTH_ENABLE_ECC = 1, + + CFG_ADDR_ENCODE_ENABLED = 0 + ) + ( + ctl_clk, + ctl_reset_n, + + cfg_local_data_width, + cfg_dram_data_width, + cfg_enable_ecc, + + input_data, + input_addr, + input_ecc_code, + input_ecc_code_overwrite, + output_data + ); + +localparam CFG_LOCAL_DATA_WIDTH = CFG_ECC_DATA_WIDTH - CFG_ECC_CODE_WIDTH; + +input ctl_clk; +input ctl_reset_n; + +input [CFG_PORT_WIDTH_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width; +input [CFG_PORT_WIDTH_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width; +input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc; + +input [CFG_ECC_DATA_WIDTH - 1 : 0] input_data; +input [CFG_ADDR_WIDTH - 1 : 0] input_addr; +input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code; +input input_ecc_code_overwrite; + +output [CFG_ECC_DATA_WIDTH - 1 : 0] output_data; + + reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_input; + + reg [CFG_ECC_DATA_WIDTH - 1 : 0] output_data; + reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output; + + wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] encoder_input; + wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_output; + + wire [CFG_ADDR_WIDTH - 1 : 0] encoder_addr_output; + + genvar i; + + generate + for (i = 0;i < CFG_ECC_DATA_WIDTH;i = i + 1) + begin : encoder_input_per_data_width + always @ (*) + begin + if (i < cfg_local_data_width) + int_encoder_input [i] = input_data [i]; + else + int_encoder_input [i] = 1'b0; + end + end + endgenerate + + assign encoder_input = int_encoder_input [CFG_LOCAL_DATA_WIDTH - 1 : 0]; + + generate + for (i = 0;i < CFG_ECC_DATA_WIDTH;i = i + 1) + begin : encoder_output_per_data_width + always @ (*) + begin + if (i < cfg_local_data_width) + begin + int_encoder_output [i] = encoder_output [i]; + end + else if (i < cfg_dram_data_width) + begin + if (input_ecc_code_overwrite) + int_encoder_output [i] = input_ecc_code [(i % 8)]; + else + int_encoder_output [i] = encoder_output [(i % 8) + 64]; + end + else + begin + int_encoder_output [i] = 1'b0; + end + end + end + endgenerate + + always @ (*) + begin + if (cfg_enable_ecc) + begin + output_data = int_encoder_output; + end + else + begin + output_data = input_data; + end + end + + + + generate + if (CFG_ECC_DATA_WIDTH > 72) + begin + assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 72] = {(CFG_ECC_DATA_WIDTH - 72){1'b0}}; + end + endgenerate + + generate + if (CFG_ADDR_ENCODE_ENABLED == 1) + begin + fmiohmc_ecc_encoder_112 # + ( + .DI (64 + CFG_ADDR_WIDTH ), + .DOUT (72 + CFG_ADDR_WIDTH ) + ) + encoder_inst + ( + .data ({input_addr, encoder_input [64 - 1 : 0]} ), + .q ({encoder_output [72 - 1 : 64], encoder_addr_output, encoder_output [64 - 1 : 0]} ) + ); + end + else + begin + fmiohmc_ecc_encoder_64 encoder_inst + ( + .data (encoder_input [64 - 1 : 0]), + .q (encoder_output [72 - 1 : 0]) + ); + end + endgenerate + + + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EAzI8rcD4tgvZndNz7RuX51xHVL84bgInUobdAj4pcg8Bgtb+8A3SitQThO8I2z0jp7R5E+DLaTw6nzoNwbeUMhZ/yj3QSFHSSry3enTq0pMbz2m5E/9468zrjl2u0zi5nfFODm8osh0YQONzw0RD1XjvWA/oVjZeKvfBNzmhCuM7YAg1I3MhDJdWZekzadN/v31Myy32rO4pA0QBDjxZb7AbbREsolnYgWKSUK7JjxMbyNJAWUfYzBKyYPl+VsHk8tNWeasybQnT9DUQKFjXnoDNnvQVTyJzE4JXODx1ZgES5+UVc7u5s9qx1N4GdzYKdXgJHXwCsMaKsIOtO+czMqR//GHlUimmRVbeOxGHgTadwaSFKlQwVWN+rb730sHylieM7OprS6X4tcoYH66itX0s7y3tZvRsL332BijBnibE5nc+6x88b2RJIhfxeueXZvE7WFCpcxwi+Wb9FfO9hkKcZKy+ImKJekM3/+PDNsyySH+QIQXDX3rzYWQkp/4i8h2d7JUCdKopyQ62QzZrg5AIFqgt+bJxT45BF8MqcXpbB8EDxp4j2n0QnHNUfot/JNOvZCINR97b3nLiAz2VCxOxc7ShSshhaUqEfcDnYob+hsD/h959C8H0QtplMAtnHvO7duxdyAuDPj95R/PT0IeKKcgZ5vlyWzTDa3Wi852TJV7c0Vw8IgEtGyg8xImGtkhvWMnDf3HGLhmDVjTBurAvwk5WGEAXYs5lgFuxnETY46Y1PK331bGx5JVaGEfqsZgrJhzJz+vGKM+D4QMzcX" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_112.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_112.v new file mode 100644 index 0000000000..2a1a910104 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_112.v @@ -0,0 +1,57 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_encoder_112 +#( parameter + DI = 98, + DOUT = 106 +) + +( + data, + q +); + +localparam PARITY = 8; + +input [DI-1:0] data; +output [DOUT-1:0] q; + +wire [111:0] data_e; +wire [111:0] data_i; +generate + if(DI==112) + assign data_e = data; + else + assign data_e = {{(112-DI){1'b0}},data}; +endgenerate +assign data_i = {data_e[111:PARITY],~data_e[PARITY-1],data_e[PARITY-2:1],~data_e[0]}; + +wire [PARITY-1:0] sb; + +fmiohmc_ecc_pcm_112 ecc_pcm ( + .di(data_i), + .sb({PARITY{1'b0}}), + .dout(sb) +); + +assign q = {sb,data[DI-1:0]}; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EBvpnDJH3Gywd1hOtha9cNq6jTHNq1cG4iMFvZe5LZTx4C9k5in2kJ+b3axV7BL5A/eTPHrlSzF4zLvLBzOfE/WS+1SsRyLgUHzrcKkv0eBHxl2f6H+eXcMrOqaJXPASKbBVHLS2lC0e5WiM+GGZRh2o7O8hpOWfTvqf6fNoe5CG86kQSfiMvMipftTWImgpBPn8FdSNnX6uVLUpLAjAdyBg6kENT8cG5uy2/nw0JWbzHjVvI25TZnRV0At/Pta5ysaJGeq6aNC2pn1KmhzM7CJzduSefvnaxyz+qxDYdFD4rBcDMDDa6rginkgzKkZfO3mb505yC/4GFcpyD/ZrWViToZsbhiP8wAIi4ONDTkKNoyo7hg0NKG2ls5NwGJLM8GdTLTaZlsFDRNr9+TFWHBVXCsIxGYgi43ar1fX0/QBSBPpf4tyW9mT0uCyIAcY8JhtDgyubOazqTNntKgZB/0N2RcibFteqqD6FgYFpV9BJNqNN9hCO28SKGW7vHdTbj3J8lp2mXgk5enXtrVyJPLEk5KZng6hya1LhrcHfdqJzZPlvFpqw5Al/3i49pSfavpj+BVbtlpVaHMz4TVGwhOmsuVwY/bfJYJ85CbaHMciv7QKI0WyRrnFlMn0sEpepkBLJ+5dcNRWqkrgsa81+o/LdLSsOx0cwDBp9VAmkEE9g79iwIsTDSuDXNgEoGUSvtQhhs0uOpwF/1VAazmOYhto4xdi8k+S7pqRpGNaLdBAIR9BDsW6QXlRi7hWr7GvpqCjiUF6EyDkRma9uFffhqyJ" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64.v new file mode 100644 index 0000000000..b7c7c5b718 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64.v @@ -0,0 +1,41 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + + + + +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +//altera message_off 10463 + +`timescale 1 ps / 1 ps +module fmiohmc_ecc_encoder_64 ( + data, + q)/* synthesis synthesis_clearbox = 1 */; + + input [63:0] data; + output [71:0] q; + + wire [71:0] sub_wire0; + wire [71:0] q = sub_wire0[71:0]; + + fmiohmc_ecc_encoder_64_altecc_encoder iohmc_ecc_encoder_64_altecc_encoder_component ( + .data (data), + .q (sub_wire0)); + +endmodule + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EB4BzQn2Y/UVGf2tm8a1y+zV+7wYOuLc0X6EeJpoj9owEblMPnFgpIFh3WFhtS1aXJcuhevzxr/r2K3mwQ82wTAKzTedqM4sOJx5H69XsvpRRT1z+2G74hsVBDK1EqOTGFthnDZVJvCPbW/WB8Mp87nVMiM9fyUL5gvhZ37WOTI35KqYbJBESQPV3xbqsF7Y80W+LccFO9A6cL7LZglhWSPjGK2nJQxE0Utv6HAWwpk1ZU99IG2mr4Ab4Txo4fnbzWjmOUrAwe+FXwY53eXMsfpPUgPUjDq55mt72VoulZT+zyGgA/3rRmSPU+JEhRk6PMGo2m6bRNmoQ8gadPNgvu+Gok41+O9p0Kr3dEUR/u48mY2F07T+jQPXIoxBeslKe42//BDHXdKZFg/0V9Au9pJ7AdpNCDwWfJ08rTguD2N2EQQUlw3UuruA9aoAp8EpxkCW6R6grTXLixMPCp6y4q7mCDfuTWPzyepYP0Mv1ShHXtU+P4GMqhOGHw5sLLbvCmmmTuxwZaYEFZZh44G305hWGjRHQp0TsX42/8QktIklwizFcQ5KXxd0OE2AekuH7R/BK1/7s699AVMFYSlr7+bSLKroj2jn4XVFTKXl01btL0yAUq5e1CV2vMwlDv4AuyekLQik/g6VxXUWBfk4aQnpVLxC1yxAunh48PBu3u12pDLlPPg8aQxy9L1zWHf9OJYVRyfrjr+Ww+OZalRvqqYfD4CrQBSi9uQGPY3gqwO2pASgjUrF0s5PF4b71Bp0CbCV+8ow2X8oYk/2ZepvRee" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64_altecc_encoder.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64_altecc_encoder.v new file mode 100644 index 0000000000..da011574ef --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64_altecc_encoder.v @@ -0,0 +1,52 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// synthesis_resources = +`timescale 1 ps / 1 ps +module fmiohmc_ecc_encoder_64_altecc_encoder + ( + data, + q) /* synthesis synthesis_clearbox=1 */; + input [63:0] data; + output [71:0] q; + + wire [63:0] data_wire; + wire [34:0] parity_01_wire; + wire [17:0] parity_02_wire; + wire [8:0] parity_03_wire; + wire [3:0] parity_04_wire; + wire [1:0] parity_05_wire; + wire [30:0] parity_06_wire; + wire [6:0] parity_07_wire; + wire [70:0] parity_final_wire; + wire [71:0] q_wire; + + assign + data_wire = data, + parity_01_wire = {(data_wire[63] ^ parity_01_wire[33]), (data_wire[61] ^ parity_01_wire[32]), (data_wire[59] ^ parity_01_wire[31]), (data_wire[57] ^ parity_01_wire[30]), (data_wire[56] ^ parity_01_wire[29]), (data_wire[54] ^ parity_01_wire[28]), (data_wire[52] ^ parity_01_wire[27]), (data_wire[50] ^ parity_01_wire[26]), (data_wire[48] ^ parity_01_wire[25]), (data_wire[46] ^ parity_01_wire[24]), (data_wire[44] ^ parity_01_wire[23]), (data_wire[42] ^ parity_01_wire[22]), (data_wire[40] ^ parity_01_wire[21]), (data_wire[38] ^ parity_01_wire[20]), (data_wire[36] ^ parity_01_wire[19]), (data_wire[34] ^ parity_01_wire[18]), (data_wire[32] ^ parity_01_wire[17]), (data_wire[30] ^ parity_01_wire[16]), (data_wire[28] ^ parity_01_wire[15]), (data_wire[26] ^ parity_01_wire[14]), (data_wire[25] ^ parity_01_wire[13]), (data_wire[23] ^ parity_01_wire[12]), (data_wire[21] ^ parity_01_wire[11]), (data_wire[19] ^ parity_01_wire[10]), (data_wire[17] ^ parity_01_wire[9]), (data_wire[15] ^ parity_01_wire[8]), (data_wire[13] ^ parity_01_wire[7]), (data_wire[11] ^ parity_01_wire[6]), (data_wire[10] ^ parity_01_wire[5]), (data_wire[8] ^ parity_01_wire[4]), (data_wire[6] ^ parity_01_wire[3]), (data_wire[4] ^ parity_01_wire[2]), (data_wire[3] ^ parity_01_wire[1]), (data_wire[1] ^ parity_01_wire[0]), data_wire[0]}, + parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), data_wire[0]}, + parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), ((data_wire[1] ^ data_wire[2]) ^ data_wire[3])}, + parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])}, + parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), ((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])}, + parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), data_wire[26]}, + parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), data_wire[57]}, + parity_final_wire = {(q_wire[70] ^ parity_final_wire[69]), (q_wire[69] ^ parity_final_wire[68]), (q_wire[68] ^ parity_final_wire[67]), (q_wire[67] ^ parity_final_wire[66]), (q_wire[66] ^ parity_final_wire[65]), (q_wire[65] ^ parity_final_wire[64]), (q_wire[64] ^ parity_final_wire[63]), (q_wire[63] ^ parity_final_wire[62]), (q_wire[62] ^ parity_final_wire[61]), (q_wire[61] ^ parity_final_wire[60]), (q_wire[60] ^ parity_final_wire[59]), (q_wire[59] ^ parity_final_wire[58]), (q_wire[58] ^ parity_final_wire[57]), (q_wire[57] ^ parity_final_wire[56]), (q_wire[56] ^ parity_final_wire[55]), (q_wire[55] ^ parity_final_wire[54]), (q_wire[54] ^ parity_final_wire[53]), (q_wire[53] ^ parity_final_wire[52]), (q_wire[52] ^ parity_final_wire[51]), (q_wire[51] ^ parity_final_wire[50]), (q_wire[50] ^ parity_final_wire[49]), (q_wire[49] ^ parity_final_wire[48]), (q_wire[48] ^ parity_final_wire[47]), (q_wire[47] ^ parity_final_wire[46]), (q_wire[46] ^ parity_final_wire[45]), (q_wire[45] ^ parity_final_wire[44]), (q_wire[44] ^ parity_final_wire[43]), (q_wire[43] ^ parity_final_wire[42]), (q_wire[42] ^ parity_final_wire[41]), (q_wire[41] ^ parity_final_wire[40]), (q_wire[40] ^ parity_final_wire[39]), (q_wire[39] ^ parity_final_wire[38]), (q_wire[38] ^ parity_final_wire[37]), (q_wire[37] ^ parity_final_wire[36]), (q_wire[36] ^ parity_final_wire[35]), (q_wire[35] ^ parity_final_wire[34]), (q_wire[34] ^ parity_final_wire[33]), (q_wire[33] ^ parity_final_wire[32]), (q_wire[32] ^ parity_final_wire[31]), (q_wire[31] ^ parity_final_wire[30]), (q_wire[30] ^ parity_final_wire[29]), (q_wire[29] ^ parity_final_wire[28]), (q_wire[28] ^ parity_final_wire[27]), (q_wire[27] ^ parity_final_wire[26]), (q_wire[26] ^ parity_final_wire[25]), (q_wire[25] ^ parity_final_wire[24]), (q_wire[24] ^ parity_final_wire[23]), (q_wire[23] ^ parity_final_wire[22]), (q_wire[22] ^ parity_final_wire[21]), (q_wire[21] ^ parity_final_wire[20]), (q_wire[20] ^ parity_final_wire[19]), (q_wire[19] ^ parity_final_wire[18]), (q_wire[18] ^ parity_final_wire[17]), (q_wire[17] + ^ parity_final_wire[16]), (q_wire[16] ^ parity_final_wire[15]), (q_wire[15] ^ parity_final_wire[14]), (q_wire[14] ^ parity_final_wire[13]), (q_wire[13] ^ parity_final_wire[12]), (q_wire[12] ^ parity_final_wire[11]), (q_wire[11] ^ parity_final_wire[10]), (q_wire[10] ^ parity_final_wire[9]), (q_wire[9] ^ parity_final_wire[8]), (q_wire[8] ^ parity_final_wire[7]), (q_wire[7] ^ parity_final_wire[6]), (q_wire[6] ^ parity_final_wire[5]), (q_wire[5] ^ parity_final_wire[4]), (q_wire[4] ^ parity_final_wire[3]), (q_wire[3] ^ parity_final_wire[2]), (q_wire[2] ^ parity_final_wire[1]), (q_wire[1] ^ parity_final_wire[0]), q_wire[0]}, + q = q_wire, + q_wire = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[34], data_wire}; +endmodule + + +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EAg8LhADRK4uNRFgB/h7XKaIWHN6XWLH/tc3eAoC7Fun83Rtj3YiUQbjakI2aDSIpXnfD8lCnMZvFmeTAhuRfOY9MH4ZcFsNdGs/18/zxA77yfCSeMde0GNkjwK1wS4J34YW5sbO9pswVwuvTFl5fvJMZJTMkTouW3GF35n4OSR7KyKXgmogi9PNXIuMnB8K19QPLEA/UuJX7G2cTmXEQB7QD/mGLhe0gEAOGfC1k0GTIVnq+8bO5jsZUS+KSvWK/s6CoOLk2lcaHC3h9otrBarWI8CBreAoNTox4LUmjcS7XDNAmtmOFpGuBebDfML+hTQVMC3gnj061rlOOy+Q7l4bzzjQ5QNoaHg4kpgdIqBneyIgFNjmZIW8EHsnVqrevIQt73UJrxQ02jMLEt2FZHfS6SLR3vZfoQYnrQ2+nGwM68qArbZNF94GjmDEyrPirLP6SELOg8AAhUSiBpFQdm9IJQXYsHS3ZfIOby6Yv2G1oMRnbG+tQ2u2OFyrJy2uFNRo4mTqzdP+dkh0wZMN2Ezcmfyndi5yi/2wPOpLfzxVFogQVS9KHThiOVRH8CtlugPMrD5I2CAzt8OB4RENSH1KFYLuzVqb/FvW12pJuYqwgjkL6ZOyS0iP/OEtYiHUTA3FtES93XY4+SqDSORHPFDy1gCc9HLOSFAbWcbYweL8O+tbcIGdzAzHIhJbBtdfMDGP7ob2SRcDarjVyglnCgqZB9/7Em6TPSobMaQup6IFEBTda5r31T3SGBUgNMPvvLG5LbQ31Qy1Kra+9KBaolG" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_interface_fifo.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_interface_fifo.v new file mode 100644 index 0000000000..12cd229cbe --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_interface_fifo.v @@ -0,0 +1,122 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name AUTO_RAM_RECOGNITION OFF; -name INFER_RAMS_FROM_RAW_LOGIC OFF" *) +module fmiohmc_ecc_interface_fifo +#( + parameter DATA_WIDTH = 'd1, + parameter RESERVE_ENTRY = 0 +) +( + clk, + reset_n, + + in_ready, + in_valid, + in_data, + + out_ready, + out_valid, + out_data +); + +localparam ENTRY = 2 + RESERVE_ENTRY; +localparam PTR_WIDTH = (ENTRY > 8 && ENTRY <= 16) ? 4 : + (ENTRY > 4 && ENTRY <= 8) ? 3 : + (ENTRY > 2 && ENTRY <= 4) ? 2 : 1; +localparam COUNTER_WIDTH = PTR_WIDTH + 1; +localparam ENTRY_ALMOST_FULL = 2; + +input clk; +input reset_n; + +output in_ready; +input in_valid; +input [DATA_WIDTH - 1 : 0] in_data; + +input out_ready; +output out_valid; +output [DATA_WIDTH - 1 : 0] out_data; + +reg [DATA_WIDTH - 1 : 0] data_reg [ENTRY - 1 : 0]; + +(* altera_attribute = {"-name MAX_FANOUT 20"}*) reg [PTR_WIDTH - 1 : 0] write_ptr; +(* altera_attribute = {"-name MAX_FANOUT 20"}*) reg [PTR_WIDTH - 1 : 0] read_ptr; +(* altera_attribute = {"-name MAX_FANOUT 5"}*) reg [COUNTER_WIDTH - 1 : 0] counter; +(* altera_attribute = {"-name MAX_FANOUT 1"}*) reg empty; + +wire in_ready; +reg almost_full; +wire out_valid; +wire [DATA_WIDTH - 1 : 0] out_data; +wire read_en; +wire write_en; + +assign in_ready = ~almost_full; +assign read_en = ~empty && out_ready; +assign write_en = in_valid; +assign out_valid = ~empty; +assign out_data = data_reg [read_ptr]; + +always @(posedge clk) +begin + if (!reset_n) begin + write_ptr <= {PTR_WIDTH{1'b0}}; + read_ptr <= {PTR_WIDTH{1'b0}}; + counter <= {COUNTER_WIDTH{1'b0}}; + almost_full <= 1'b0; + empty <= 1'b1; + end + else begin + if (write_en) begin + if (write_ptr == ENTRY - 1) begin + write_ptr <= {PTR_WIDTH{1'b0}}; + end else begin + write_ptr <= write_ptr + 1'b1; + end + end + + if (read_en) begin + if (read_ptr == ENTRY - 1) begin + read_ptr <= {PTR_WIDTH{1'b0}}; + end else begin + read_ptr <= read_ptr + 1'b1; + end + end + + if (write_en && !read_en) begin + counter <= counter + 1'b1; + almost_full <= (counter >= (ENTRY_ALMOST_FULL - 1)); + empty <= 1'b0; + end + else if (read_en && !write_en) begin + counter <= counter - 1'b1; + almost_full <= (counter >= (ENTRY_ALMOST_FULL + 1)); + empty <= (counter == 1); + end + end +end + +always @(posedge clk) +begin + if (write_en) begin + data_reg[write_ptr] <= in_data; + end +end + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EBu/NhERVlw1qYxFwL6o/Utz+RvviJ8gIhcs4HnIyc+9DmBZYiVW2D5PJOrlmnhLombMsuOCwaGYpPI2vH9OGmAkdH77lAGl8Nya5VVRQQdqebpcH+qH1HhcFEGagJDVUNTMZAsy1Ldmqy3mSqREYgJO5DcNGlZANL2QL+KckqkV+jxM76A7wuoJ9iFDhWVEwuSxmo3lu2C6/WQvaJMeUf72EPnMljVZcdPssLE8GXOAdLpImks7JLTbaSyAQdU+f3TMw/NFAKXQRnaC/JhqNTuMcFCGQYFQ9tDDb1AOuMIBeAvoOkMaH0xoo+HFK7/oWVF1dHYdVnDmx3HMwRVlVp9JSOv2x90rhoACFvZxZIMzQrPzE6sjhXrXDnEYOSZJXEraZk7kRxH6O86ZIUxyIL48n7SgFWrN/G+vQcl9Yg3ggu3zhhvvgthj9Cd0nDuX5cCckoEkhRmWcS0zQg9AxR5u6lenh9MmoVlrujHOv7UI0Mh1DCs4hcEjYbhx0ITFTQMMfYEEG4k4+3uiWj7nBSpep+dlJNDritleLDiicR1jgvhd9I0bdRywz2wLXaSH3V3RspxcuiJCjXz0OiXjB5qe3Vdhe44303IWQOsh/KEs9qrELahq85MgJkNuGD1pSc1itOcPvnqSWF6DUcenq3ulknxGSadDQ09lwdD+tEJY3Q1Jho/1CEFrj3nZvZdio10/v4ZfRVG0rePUIxu3HTeQ5ZyvkgkQfv7WLUxakjRMO21KAVlfRP3uIPnoxwXFCdZxJPmU+VPtJrYsBOhdXTR" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_mmr.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_mmr.v new file mode 100644 index 0000000000..711c7a1911 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_mmr.v @@ -0,0 +1,637 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_mmr # + ( parameter + CFG_MMR_ADDR_WIDTH = 10, + CFG_MMR_DATA_WIDTH = 35, + CFG_MMR_BYTE_ENABLE_WIDTH = 4, + CFG_MMR_BURSTCOUNT_WIDTH = 2, + + CFG_DRAM_DATA_WIDTH = 0, + CFG_LOCAL_DATA_WIDTH = 0, + CFG_ADDR_WIDTH = 0, + CFG_DATA_RATE = 0, + CFG_ECC_IN_PROTOCOL = 0, + CFG_WRPATH_PIPELINE_EN = 0, + CFG_ENABLE_ECC = 0, + CFG_ENABLE_DM = 0, + CFG_ENABLE_RMW = 0, + CFG_ENABLE_AUTO_CORR = 0, + CFG_ECC_CODE_OVERWRITE = 0, + CFG_GEN_SBE = 0, + CFG_GEN_DBE = 0, + CFG_ENABLE_INTR = 0, + CFG_MASK_SBE_INTR = 0, + CFG_MASK_DBE_INTR = 0, + CFG_MASK_CORR_DROPPED_INTR = 0, + CFG_MASK_HMI_INTR = 0, + CFG_CLR_INTR = 0, + CFG_CLR_MR_RDATA = 0, + + CFG_PORT_WIDTH_DRAM_DATA_WIDTH = 8, + CFG_PORT_WIDTH_LOCAL_DATA_WIDTH = 8, + CFG_PORT_WIDTH_ADDR_WIDTH = 6, + CFG_PORT_WIDTH_DATA_RATE = 4, + CFG_PORT_WIDTH_ECC_IN_PROTOCOL = 1, + CFG_PORT_WIDTH_WRPATH_PIPELINE_EN = 1, + CFG_PORT_WIDTH_ENABLE_ECC = 1, + CFG_PORT_WIDTH_ENABLE_DM = 1, + CFG_PORT_WIDTH_ENABLE_RMW = 1, + CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1, + CFG_PORT_WIDTH_ECC_CODE_OVERWRITE = 1, + CFG_PORT_WIDTH_GEN_SBE = 1, + CFG_PORT_WIDTH_GEN_DBE = 1, + CFG_PORT_WIDTH_ENABLE_INTR = 1, + CFG_PORT_WIDTH_MASK_SBE_INTR = 1, + CFG_PORT_WIDTH_MASK_DBE_INTR = 1, + CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1, + CFG_PORT_WIDTH_MASK_HMI_INTR = 1, + CFG_PORT_WIDTH_CLR_INTR = 1, + CFG_PORT_WIDTH_CLR_MR_RDATA = 1, + ECC_MMR_READ_LATENCY = 2, + + STS_PORT_WIDTH_ECC_INTR = 1, + STS_PORT_WIDTH_SBE_ERROR = 1, + STS_PORT_WIDTH_DBE_ERROR = 1, + STS_PORT_WIDTH_CORR_DROPPED = 1, + STS_PORT_WIDTH_SBE_COUNT = 4, + STS_PORT_WIDTH_DBE_COUNT = 4, + STS_PORT_WIDTH_CORR_DROPPED_COUNT = 4, + STS_PORT_WIDTH_ERR_ADDR = 35, + STS_PORT_WIDTH_CORR_DROPPED_ADDR = 35, + STS_PORT_WIDTH_MR_DATA = 81*8, + STS_PORT_WIDTH_MR_DATA_VALID = 1 + ) + ( + ctl_clk, + ctl_reset_n, + + cfg_dram_data_width, + cfg_local_data_width, + cfg_addr_width, + cfg_data_rate, + cfg_ecc_in_protocol, + cfg_wrpath_pipeline_en, + cfg_enable_ecc, + cfg_enable_dm, + cfg_enable_rmw, + cfg_enable_auto_corr, + cfg_ecc_code_overwrite, + cfg_gen_sbe, + cfg_gen_dbe, + cfg_enable_intr, + cfg_mask_sbe_intr, + cfg_mask_dbe_intr, + cfg_mask_corr_dropped_intr, + cfg_mask_hmi_intr, + cfg_clr_intr, + cfg_clr_mr_rdata, + + sts_ecc_intr, + sts_sbe_error, + sts_dbe_error, + sts_corr_dropped, + sts_sbe_count, + sts_dbe_count, + sts_corr_dropped_count, + sts_err_addr, + sts_corr_dropped_addr, + sts_mr_rdata_0, + sts_mr_rdata_1, + sts_mr_rdata_valid, + + slave_ready, + slave_address, + slave_write, + slave_read, + slave_burstcount, + slave_begintransfer, + slave_wr_data, + slave_byte_enable, + slave_rd_data, + slave_rd_data_valid, + + master_ready, + master_address, + master_write, + master_read, + master_burstcount, + master_begintransfer, + master_wr_data, + master_byte_enable, + master_rd_data, + master_rd_data_valid + ); + +/* + For an MMR read between the ECC core and HMC (for addresses less than 0x7F), + the following latency is incurred: + ______________ _ ______________ + CMD -----> | | -----> | | -----> * -----> | | + | | |_| | | + | | | | + | ECC | _ | HMC | + READ <----- | | <----- | | <----- * <----- | 3 or 4 cycle | + DATA | | |_| | latency | + |______________| |______________| + + HMC_MMR_IF UFI + Signal names: + mmr_master_* slave_* master_* + + In the above diagram, the UFI command and read paths do not have any latency delays. + Typically, CFG_REGISTER_UFI_RDATA_PATH_NUM has 2 pipeline stages for Rev A boards + or 0 pipeline stages for Rev B boards + + There is a general exception to UFI Latency for MMR interfaces - whereas RevA in this exceptional case + does not incur an additional two cycle delay in either direction. However, for RevB2 boards with half rate + and a core clock >= 400 MHz, the 2 cycle UFI latency is applied in each direction. + + The calculation for ECC_MMR_READ_LATENCY is performed in ip_ecc/ip_core_fm/main.tcl and is dependent + on the IO Bank revision, whether or not rate conversion is on, and the core clock frequency. + + TODO: The IP can force the UFI latency via a diagnostic override (DIAG_EXTRA_CONFIGS: FORCE_L2_UFI=ON), + thus changing the FILTER_MASTER_RD_DATA_VALID_LATENCY value. Changes will have to be made + in the future to reflect that. + +*/ +localparam FILTER_MASTER_RD_DATA_VALID_LATENCY = ECC_MMR_READ_LATENCY; + +input ctl_clk; +input ctl_reset_n; + +output [CFG_PORT_WIDTH_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width; +output [CFG_PORT_WIDTH_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width; +output [CFG_PORT_WIDTH_ADDR_WIDTH - 1 : 0] cfg_addr_width; +output [CFG_PORT_WIDTH_DATA_RATE - 1 : 0] cfg_data_rate; +output [CFG_PORT_WIDTH_ECC_IN_PROTOCOL - 1 : 0] cfg_ecc_in_protocol; +output [CFG_PORT_WIDTH_WRPATH_PIPELINE_EN - 1 : 0] cfg_wrpath_pipeline_en; +output [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc; +output [CFG_PORT_WIDTH_ENABLE_DM - 1 : 0] cfg_enable_dm; +output [CFG_PORT_WIDTH_ENABLE_RMW - 1 : 0] cfg_enable_rmw; +output [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr; +output [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0] cfg_ecc_code_overwrite; +output [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe; +output [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe; +output [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr; +output [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr; +output [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr; +output [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr; +output [CFG_PORT_WIDTH_MASK_HMI_INTR - 1 : 0] cfg_mask_hmi_intr; +output [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr; +output [CFG_PORT_WIDTH_CLR_MR_RDATA - 1 : 0] cfg_clr_mr_rdata; + +input [STS_PORT_WIDTH_ECC_INTR - 1 : 0] sts_ecc_intr; +input [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error; +input [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error; +input [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] sts_corr_dropped; +input [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count; +input [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count; +input [STS_PORT_WIDTH_CORR_DROPPED_COUNT - 1 : 0] sts_corr_dropped_count; +input [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] sts_err_addr; +input [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] sts_corr_dropped_addr; +input [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_0; +input [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_1; +input [STS_PORT_WIDTH_MR_DATA_VALID - 1 : 0] sts_mr_rdata_valid; + +output slave_ready; +input [CFG_MMR_ADDR_WIDTH - 1 : 0] slave_address; +input slave_write; +input slave_read; +input [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] slave_burstcount; +input slave_begintransfer; +input [CFG_MMR_DATA_WIDTH - 1 : 0] slave_wr_data; +input [CFG_MMR_BYTE_ENABLE_WIDTH - 1 : 0] slave_byte_enable; +output [CFG_MMR_DATA_WIDTH - 1 : 0] slave_rd_data; +output slave_rd_data_valid; + +input master_ready; +output [CFG_MMR_ADDR_WIDTH - 1 : 0] master_address; +output master_write; +output master_read; +output [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] master_burstcount; +output master_begintransfer; +output [CFG_MMR_DATA_WIDTH - 1 : 0] master_wr_data; +output [CFG_MMR_BYTE_ENABLE_WIDTH - 1 : 0] master_byte_enable; +input [CFG_MMR_DATA_WIDTH - 1 : 0] master_rd_data; +input master_rd_data_valid; + + +reg [CFG_PORT_WIDTH_WRPATH_PIPELINE_EN - 1 : 0] reg_wrpath_pipeline_en; +reg [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] reg_enable_ecc; +reg [CFG_PORT_WIDTH_ENABLE_DM - 1 : 0] reg_enable_dm; +reg [CFG_PORT_WIDTH_ENABLE_RMW - 1 : 0] reg_enable_rmw; +reg [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] reg_enable_auto_corr; +reg [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0] reg_ecc_code_overwrite; +reg [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] reg_gen_sbe; +reg [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] reg_gen_dbe; +reg [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] reg_enable_intr; +reg [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] reg_mask_sbe_intr; +reg [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] reg_mask_dbe_intr; +reg [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] reg_mask_corr_dropped_intr; +reg [CFG_PORT_WIDTH_MASK_HMI_INTR - 1 : 0] reg_mask_hmi_intr; +reg [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] reg_clr_intr; +reg [CFG_PORT_WIDTH_CLR_MR_RDATA - 1 : 0] reg_clr_mr_rdata; +reg [STS_PORT_WIDTH_ECC_INTR - 1 : 0] reg_ecc_intr; +reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] reg_sbe_error; +reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] reg_dbe_error; +reg [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] reg_corr_dropped; +reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] reg_sbe_count; +reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] reg_dbe_count; +reg [STS_PORT_WIDTH_CORR_DROPPED_COUNT - 1 : 0] reg_corr_dropped_count; +reg [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] reg_err_addr; +reg [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] reg_corr_dropped_addr; +reg [STS_PORT_WIDTH_MR_DATA - 1 : 0] reg_mr_rdata_0; +reg [STS_PORT_WIDTH_MR_DATA - 1 : 0] reg_mr_rdata_1; +reg [STS_PORT_WIDTH_MR_DATA_VALID - 1 : 0] reg_mr_rdata_valid; + +wire slave_ready; +wire [CFG_MMR_DATA_WIDTH - 1 : 0] slave_rd_data; +wire slave_rd_data_valid; +wire [CFG_MMR_ADDR_WIDTH - 1 : 0] master_address; +wire master_write; +wire master_read; +wire [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] master_burstcount; +wire master_begintransfer; +wire [CFG_MMR_DATA_WIDTH - 1 : 0] master_wr_data; +wire [CFG_MMR_BYTE_ENABLE_WIDTH - 1 : 0] master_byte_enable; +wire [CFG_MMR_DATA_WIDTH - 1 : 0] master_rd_data; + +reg [CFG_MMR_ADDR_WIDTH - 1 : 0] int_slave_address_count; +reg [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] int_slave_burstcount_left; +reg int_slave_writing; + +reg int_slave_ready; +reg [CFG_MMR_ADDR_WIDTH - 1 : 0] int_slave_address; +reg int_slave_write; +reg int_slave_read; +reg [CFG_MMR_DATA_WIDTH - 1 : 0] int_slave_rd_data; +reg int_slave_rd_data_valid; + +reg filter_slave_rd_data_valid; +reg [FILTER_MASTER_RD_DATA_VALID_LATENCY - 1 : 0] filter_master_rd_data_valid; + +always @ (posedge ctl_clk) +begin + if (!ctl_reset_n) + begin + filter_slave_rd_data_valid <= 1'b0; + filter_master_rd_data_valid <= {FILTER_MASTER_RD_DATA_VALID_LATENCY{1'b0}}; + end + else + begin + filter_slave_rd_data_valid <= slave_ready & slave_read & !master_read; + filter_master_rd_data_valid <= {filter_master_rd_data_valid[FILTER_MASTER_RD_DATA_VALID_LATENCY - 2 : 0], (master_ready & master_read)}; + end +end +assign slave_ready = int_slave_ready & master_ready; +assign slave_rd_data = (int_slave_rd_data_valid == 1'b1) ? int_slave_rd_data : master_rd_data; +assign slave_rd_data_valid = (int_slave_rd_data_valid == 1'b1) ? (int_slave_rd_data_valid & filter_slave_rd_data_valid) + : (master_rd_data_valid & filter_master_rd_data_valid[FILTER_MASTER_RD_DATA_VALID_LATENCY - 1]); +assign master_address = slave_address; +assign master_write = slave_write && !(|slave_address [CFG_MMR_ADDR_WIDTH - 1 : 7]); +assign master_read = slave_read && !(|slave_address [CFG_MMR_ADDR_WIDTH - 1 : 7]); +assign master_burstcount = slave_burstcount; +assign master_begintransfer = slave_begintransfer; +assign master_wr_data = slave_wr_data; +assign master_byte_enable = slave_byte_enable; + +assign cfg_dram_data_width = CFG_DRAM_DATA_WIDTH [CFG_PORT_WIDTH_DRAM_DATA_WIDTH - 1 : 0]; +assign cfg_local_data_width = CFG_LOCAL_DATA_WIDTH [CFG_PORT_WIDTH_LOCAL_DATA_WIDTH - 1 : 0]; +assign cfg_addr_width = CFG_ADDR_WIDTH [CFG_PORT_WIDTH_ADDR_WIDTH - 1 : 0]; +assign cfg_data_rate = CFG_DATA_RATE [CFG_PORT_WIDTH_DATA_RATE - 1 : 0]; +assign cfg_ecc_in_protocol = CFG_ECC_IN_PROTOCOL [CFG_PORT_WIDTH_ECC_IN_PROTOCOL - 1 : 0]; +assign cfg_wrpath_pipeline_en = CFG_WRPATH_PIPELINE_EN [CFG_PORT_WIDTH_WRPATH_PIPELINE_EN - 1 : 0]; +assign cfg_enable_ecc = CFG_ENABLE_ECC [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0]; +assign cfg_enable_dm = CFG_ENABLE_DM [CFG_PORT_WIDTH_ENABLE_DM - 1 : 0]; +assign cfg_enable_rmw = CFG_ENABLE_RMW [CFG_PORT_WIDTH_ENABLE_RMW - 1 : 0]; +assign cfg_enable_auto_corr = CFG_ENABLE_AUTO_CORR [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0]; +assign cfg_ecc_code_overwrite = CFG_ECC_CODE_OVERWRITE [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0]; +assign cfg_gen_sbe = reg_gen_sbe; +assign cfg_gen_dbe = reg_gen_dbe; +assign cfg_enable_intr = CFG_ENABLE_INTR [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0]; +assign cfg_mask_sbe_intr = reg_mask_sbe_intr; +assign cfg_mask_dbe_intr = reg_mask_dbe_intr; +assign cfg_mask_corr_dropped_intr = reg_mask_corr_dropped_intr; +assign cfg_mask_hmi_intr = reg_mask_hmi_intr; +assign cfg_clr_intr = reg_clr_intr; +assign cfg_clr_mr_rdata = reg_clr_mr_rdata; + +always @ (*) +begin + int_slave_ready = (int_slave_burstcount_left == 0) ? 1'b1 : int_slave_writing; + int_slave_address = (int_slave_burstcount_left == 0) ? slave_address : int_slave_address_count; + int_slave_write = ( slave_write ) & master_ready; + int_slave_read = ((int_slave_burstcount_left == 0) ? slave_read : ~int_slave_writing) & master_ready; +end + +always @ (posedge ctl_clk) +begin + if (!ctl_reset_n) + begin + int_slave_address_count <= {CFG_MMR_ADDR_WIDTH{1'b0}}; + int_slave_burstcount_left <= {CFG_MMR_BURSTCOUNT_WIDTH{1'b0}}; + int_slave_writing <= 1'b0; + end + else + begin + if (master_ready && (slave_read || slave_write) && slave_begintransfer && slave_burstcount > 1'b1) + begin + int_slave_address_count <= slave_address + 1'b1; + int_slave_burstcount_left <= slave_burstcount - 1'b1; + int_slave_writing <= slave_write; + end + else if (int_slave_burstcount_left > 1'b1) + begin + if ((int_slave_writing && master_ready && slave_write) || !int_slave_writing) + begin + int_slave_address_count <= int_slave_address_count + 1'b1; + int_slave_burstcount_left <= int_slave_burstcount_left - 1'b1; + end + end + else + begin + int_slave_address_count <= {CFG_MMR_ADDR_WIDTH{1'b0}}; + int_slave_burstcount_left <= {CFG_MMR_BURSTCOUNT_WIDTH{1'b0}}; + int_slave_writing <= 1'b0; + end + end +end + +always @ (posedge ctl_clk) +begin + if (!ctl_reset_n) + begin + reg_wrpath_pipeline_en <= CFG_WRPATH_PIPELINE_EN [CFG_PORT_WIDTH_WRPATH_PIPELINE_EN - 1 : 0]; + reg_enable_ecc <= CFG_ENABLE_ECC [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0]; + reg_enable_dm <= CFG_ENABLE_DM [CFG_PORT_WIDTH_ENABLE_DM - 1 : 0]; + reg_enable_rmw <= CFG_ENABLE_RMW [CFG_PORT_WIDTH_ENABLE_RMW - 1 : 0]; + reg_enable_auto_corr <= CFG_ENABLE_AUTO_CORR [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0]; + reg_ecc_code_overwrite <= CFG_ECC_CODE_OVERWRITE [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0]; + reg_gen_sbe <= CFG_GEN_SBE [CFG_PORT_WIDTH_GEN_SBE - 1 : 0]; + reg_gen_dbe <= CFG_GEN_DBE [CFG_PORT_WIDTH_GEN_DBE - 1 : 0]; + reg_enable_intr <= CFG_ENABLE_INTR [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0]; + reg_mask_sbe_intr <= CFG_MASK_SBE_INTR [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0]; + reg_mask_dbe_intr <= CFG_MASK_DBE_INTR [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0]; + reg_mask_corr_dropped_intr <= CFG_MASK_CORR_DROPPED_INTR [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0]; + reg_mask_hmi_intr <= CFG_MASK_HMI_INTR [CFG_PORT_WIDTH_MASK_HMI_INTR - 1 : 0]; + reg_clr_intr <= CFG_CLR_INTR [CFG_PORT_WIDTH_CLR_INTR - 1 : 0]; + reg_clr_mr_rdata <= CFG_CLR_MR_RDATA [CFG_PORT_WIDTH_CLR_MR_RDATA - 1 : 0]; + reg_ecc_intr <= {STS_PORT_WIDTH_ECC_INTR {1'b0}}; + reg_sbe_error <= {STS_PORT_WIDTH_SBE_ERROR {1'b0}}; + reg_dbe_error <= {STS_PORT_WIDTH_DBE_ERROR {1'b0}}; + reg_corr_dropped <= {STS_PORT_WIDTH_CORR_DROPPED {1'b0}}; + reg_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT {1'b0}}; + reg_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT {1'b0}}; + reg_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROPPED_COUNT{1'b0}}; + reg_err_addr <= {STS_PORT_WIDTH_ERR_ADDR {1'b0}}; + reg_corr_dropped_addr <= {STS_PORT_WIDTH_CORR_DROPPED_ADDR {1'b0}}; + reg_mr_rdata_0 <= {STS_PORT_WIDTH_MR_DATA {1'b0}}; + reg_mr_rdata_1 <= {STS_PORT_WIDTH_MR_DATA {1'b0}}; + reg_mr_rdata_valid <= {STS_PORT_WIDTH_MR_DATA_VALID {1'b0}}; + + int_slave_rd_data <= {CFG_MMR_DATA_WIDTH {1'b0}}; + int_slave_rd_data_valid <= 1'b0; + end + else + begin + reg_ecc_intr <= sts_ecc_intr; + reg_sbe_error <= sts_sbe_error; + reg_dbe_error <= sts_dbe_error; + reg_corr_dropped <= sts_corr_dropped; + reg_sbe_count <= sts_sbe_count; + reg_dbe_count <= sts_dbe_count; + reg_corr_dropped_count <= sts_corr_dropped_count; + reg_err_addr <= sts_err_addr; + reg_corr_dropped_addr <= sts_corr_dropped_addr; + reg_mr_rdata_0 <= sts_mr_rdata_0; + reg_mr_rdata_1 <= sts_mr_rdata_1; + reg_mr_rdata_valid <= sts_mr_rdata_valid; + + case (int_slave_address) + 10'h080 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + if (int_slave_write) + begin + reg_wrpath_pipeline_en <= slave_wr_data [ 10] & slave_byte_enable [1]; + reg_ecc_code_overwrite <= slave_wr_data [ 9] & slave_byte_enable [1]; + reg_enable_auto_corr <= slave_wr_data [ 8] & slave_byte_enable [1]; + reg_enable_rmw <= slave_wr_data [ 2] & slave_byte_enable [0]; + reg_enable_dm <= slave_wr_data [ 1] & slave_byte_enable [0]; + reg_enable_ecc <= slave_wr_data [ 0] & slave_byte_enable [0]; + end + + if (int_slave_read) + begin + int_slave_rd_data <= { + {(CFG_MMR_DATA_WIDTH - 11){1'b0}}, + reg_wrpath_pipeline_en , + reg_ecc_code_overwrite , + reg_enable_auto_corr , + cfg_ecc_in_protocol , + cfg_data_rate , + reg_enable_rmw , + reg_enable_dm , + reg_enable_ecc + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h081 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + + if (int_slave_read) + begin + int_slave_rd_data <= { + {(CFG_MMR_DATA_WIDTH - 22){1'b0}}, + cfg_addr_width , + cfg_local_data_width , + cfg_dram_data_width + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h082 : + begin + if (int_slave_write) + begin + reg_clr_mr_rdata <= slave_wr_data [ 8] & slave_byte_enable [1]; + reg_clr_intr <= slave_wr_data [ 7] & slave_byte_enable [0]; + reg_mask_hmi_intr <= slave_wr_data [ 6] & slave_byte_enable [0]; + reg_mask_corr_dropped_intr <= slave_wr_data [ 5] & slave_byte_enable [0]; + reg_mask_dbe_intr <= slave_wr_data [ 4] & slave_byte_enable [0]; + reg_mask_sbe_intr <= slave_wr_data [ 3] & slave_byte_enable [0]; + reg_enable_intr <= slave_wr_data [ 2] & slave_byte_enable [0]; + reg_gen_dbe <= slave_wr_data [ 1] & slave_byte_enable [0]; + reg_gen_sbe <= slave_wr_data [ 0] & slave_byte_enable [0]; + end + else + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + end + + if (int_slave_read) + begin + int_slave_rd_data <= { + {(CFG_MMR_DATA_WIDTH - 9){1'b0}}, + reg_clr_mr_rdata , + reg_clr_intr , + reg_mask_hmi_intr , + reg_mask_corr_dropped_intr , + reg_mask_dbe_intr , + reg_mask_sbe_intr , + reg_enable_intr , + reg_gen_dbe , + reg_gen_sbe + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h090 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + if (int_slave_read) + begin + int_slave_rd_data <= { + {(CFG_MMR_DATA_WIDTH - 16){1'b0}}, + reg_corr_dropped_count , + reg_dbe_count , + reg_sbe_count , + reg_corr_dropped , + reg_dbe_error , + reg_sbe_error , + reg_ecc_intr + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h091 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + if (int_slave_read) + begin + int_slave_rd_data <= { + reg_err_addr [31 : 0] + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h092 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + if (int_slave_read) + begin + int_slave_rd_data <= { + reg_corr_dropped_addr [31 : 0] + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h093 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + if (int_slave_read) + begin + int_slave_rd_data <= { + {{(32 - (STS_PORT_WIDTH_ERR_ADDR - 32)){1'b0}}, reg_err_addr [STS_PORT_WIDTH_ERR_ADDR - 1 : 32]} + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + 10'h094 : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + if (int_slave_read) + begin + int_slave_rd_data <= { + {{(32 - (STS_PORT_WIDTH_CORR_DROPPED_ADDR - 32)){1'b0}}, reg_corr_dropped_addr [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 32]} + }; + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + default : + begin + reg_clr_intr <= 1'b0; + reg_clr_mr_rdata <= 1'b0; + + int_slave_rd_data <= {CFG_MMR_DATA_WIDTH{1'b0}}; + + if (int_slave_read) + begin + int_slave_rd_data_valid <= 1'b1; + end + else + begin + int_slave_rd_data_valid <= 1'b0; + end + end + endcase + end +end + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EC6BZU03E9XujYoOegoms/HKoZkTgEKH+H+1LaGQuI02/rKOrWOgIvS5S+SrJ/ns80Ht5Z659wxkjh80w1/sxXKGZgBW0GqFao4/FnSgRFLMpxvu2+d+Pl8BNjdbnA+fO5lry8cxEU8HhS77JzcyxvUSVXEk5FkmWTQpqQxKFUkn6uN6waeMLrkhPc7/orrbU0Z3bu66Ny3rAxrhcWwq4BLOw+PHRFz48U7MDx8QswunTH+nnmnOwIJ53au0ZTtJnhrWmv/DWeQuks9rwDbSSFZgU0XcaIviIBWnT54FnF658QbFAma8bFSzMBiDhacVGvwQeTpC7Sh59R9xrbOaQjnhwKfJYbGV2cA53IDjG65Onul0WPKI8CEB9B07KMfAGo4fQb7pGKAk/oOVkUAWFbiU8UegA8ri5XdEd6nfjy8DQvBGE2tX6zDTmUrb2arP6Fpi+f7Z3vyL2y3hHOGPByOCu/4YiLY/YpDIFqIB8UqUVVRJbESya0YZpLEJSejeDPTSNAUUqotTuH5MzOephIFr/LUJJXGY1dtgelEz0XerNl20372JT9y0GTlDN0cVO5SwMfQg0YgQrdzTik77nAMRkk1sy3X3N7GfZIsHejmERX27XF/ch+CfaG73mVaMqI6PQGuS0nDnxOR0YIv4owDVb5Bk5lklFkBRgwl5SPBokoJYmSc6MThUNj8qoo5IQR4omzKgVAPtu1J/9QPT4nNXQ/G6PZJc5H0nKQLeRtiUxlsFaSkdyWaqEunSZTwGSDqhsydSIeWtdEEFPjt09QY" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_pcm_112.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_pcm_112.v new file mode 100644 index 0000000000..a106bad1ee --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_pcm_112.v @@ -0,0 +1,39 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_pcm_112 ( + + input wire [111:0] di, + input wire [7 :0] sb, + output wire [7 :0] dout + ); + + +wire[111:0] din; + + fmiohmc_ecc_cb #(.DAT(57)) cb0 (.di({di[111],di[110],di[109],di[108],di[107],di[106],di[105],di[104],di[103],di[102],di[101],di[100],di[99],di[98],di[97],di[96],di[95],di[94],di[93],di[92],di[91],di[90],di[89],di[88],di[87],di[86],di[85],di[84],di[83],di[82],di[81],di[80],di[79],di[78],di[77],di[55],di[54],di[53],di[52],di[51],di[50],di[49],di[48],di[47],di[46],di[45],di[44],di[43],di[42],di[41],di[40],di[39],di[38],di[37],di[36],di[35],sb[0]}), .dout(dout[0])); + fmiohmc_ecc_cb #(.DAT(57)) cb1 (.di({di[111],di[110],di[109],di[108],di[107],di[106],di[105],di[104],di[103],di[102],di[101],di[100],di[99],di[98],di[97],di[96],di[95],di[94],di[93],di[92],di[76],di[75],di[74],di[73],di[72],di[71],di[70],di[69],di[68],di[67],di[66],di[65],di[64],di[63],di[62],di[55],di[54],di[53],di[52],di[51],di[50],di[34],di[33],di[32],di[31],di[30],di[29],di[28],di[27],di[26],di[25],di[24],di[23],di[22],di[21],di[20],sb[1]}), .dout(dout[1])); + fmiohmc_ecc_cb #(.DAT(57)) cb2 (.di({di[111],di[110],di[109],di[108],di[107],di[106],di[105],di[104],di[103],di[102],di[91],di[90],di[89],di[88],di[87],di[86],di[85],di[84],di[83],di[82],di[76],di[75],di[74],di[73],di[72],di[71],di[70],di[69],di[68],di[67],di[61],di[60],di[59],di[58],di[57],di[55],di[49],di[48],di[47],di[46],di[45],di[34],di[33],di[32],di[31],di[30],di[19],di[18],di[17],di[16],di[15],di[14],di[13],di[12],di[11],di[10],sb[2]}), .dout(dout[2])); + fmiohmc_ecc_cb #(.DAT(57)) cb3 (.di({di[111],di[110],di[109],di[108],di[101],di[100],di[99],di[98],di[97],di[96],di[91],di[90],di[89],di[88],di[87],di[86],di[81],di[80],di[79],di[78],di[76],di[75],di[74],di[73],di[72],di[71],di[66],di[65],di[64],di[63],di[61],di[60],di[59],di[58],di[56],di[54],di[49],di[44],di[43],di[42],di[41],di[34],di[29],di[28],di[27],di[26],di[19],di[18],di[17],di[16],di[9],di[8],di[7],di[6],di[5],di[4],sb[3]}), .dout(dout[3])); + fmiohmc_ecc_cb #(.DAT(57)) cb4 (.di({di[111],di[107],di[106],di[105],di[101],di[100],di[99],di[95],di[94],di[93],di[91],di[90],di[89],di[85],di[84],di[83],di[81],di[80],di[79],di[77],di[76],di[75],di[74],di[70],di[69],di[68],di[66],di[65],di[64],di[62],di[61],di[60],di[59],di[57],di[56],di[53],di[48],di[44],di[40],di[39],di[38],di[33],di[29],di[25],di[24],di[23],di[19],di[15],di[14],di[13],di[9],di[8],di[7],di[3],di[2],di[1],sb[4]}), .dout(dout[4])); + fmiohmc_ecc_cb #(.DAT(57)) cb5 (.di({di[110],di[107],di[104],di[103],di[101],di[98],di[97],di[95],di[94],di[92],di[91],di[88],di[87],di[85],di[84],di[82],di[81],di[80],di[78],di[77],di[76],di[73],di[72],di[70],di[69],di[67],di[66],di[65],di[63],di[62],di[61],di[60],di[58],di[57],di[56],di[52],di[47],di[43],di[40],di[37],di[36],di[32],di[28],di[25],di[22],di[21],di[18],di[15],di[12],di[11],di[9],di[6],di[5],di[3],di[2],di[0],sb[5]}), .dout(dout[5])); + fmiohmc_ecc_cb #(.DAT(57)) cb6 (.di({di[109],di[106],di[104],di[102],di[100],di[98],di[96],di[95],di[93],di[92],di[90],di[88],di[86],di[85],di[83],di[82],di[81],di[79],di[78],di[77],di[75],di[73],di[71],di[70],di[68],di[67],di[66],di[64],di[63],di[62],di[61],di[59],di[58],di[57],di[56],di[51],di[46],di[42],di[39],di[37],di[35],di[31],di[27],di[24],di[22],di[20],di[17],di[14],di[12],di[10],di[8],di[6],di[4],di[3],di[1],di[0],sb[6]}), .dout(dout[6])); + fmiohmc_ecc_cb #(.DAT(57)) cb7 (.di({di[108],di[105],di[103],di[102],di[99],di[97],di[96],di[94],di[93],di[92],di[89],di[87],di[86],di[84],di[83],di[82],di[80],di[79],di[78],di[77],di[74],di[72],di[71],di[69],di[68],di[67],di[65],di[64],di[63],di[62],di[60],di[59],di[58],di[57],di[56],di[50],di[45],di[41],di[38],di[36],di[35],di[30],di[26],di[23],di[21],di[20],di[16],di[13],di[11],di[10],di[7],di[5],di[4],di[2],di[1],di[0],sb[7]}), .dout(dout[7])); + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EBDSCNJSFcz15f84e4NsWbz107sdBGcWhLQV0Ft2ZdyzicBVXKFdbjAgBgiw4FypX/1FKdZYcvUJsS+w44c6tGaPCokgPdk0nmquTf1RXp0YHXVIHRHZ9+pFmIXYXbO5V/C5Fk2q3WXkRf3jaCNuBm7vX/CpJkUkUdfpHSx5zbyzPeLkQzdOQJ1ANb6OpMpuzSfmVWoG2ZI/XwpBO+J+UP74QWoxg9iKohMDyz79d6Q+iioHaxQqzA01s6wSIgM+wK9XL+YXchqw4kHBop5XVBV06a6kqMRRm7t8iAR+JgOefKUJv/pxEZsUuU3LHGVe9E39Bk2a07EhN7jmwXqDosDPZ3ErhKwNfALWPdEPGGgSNxgmS0u0WukrYYbVHdwI731W4BjQSwlQHN9Pyz/aFun0IZHuzTZNk1j7fSEWoYLYw/YkrMaPfaueSCcuavM8GMu316u7zeKDpBKgvGc0aI5mOJNO7hY/3DKiC6wBRc+6VStUFjAjUZwZnwjPjtVIv6fuI4mgqjyylZVmYez4zE903nAOjKOJ4CRFmT2y/GOhvzilXpTAqdD2jQsFEP+mDf4HV0iJ3YY1dN/oJpFFToaHz0PyeOI8MjeVO2Azwyiy4a/ZvP6M0Uzayl8WYQnSLXIqpqQsu2CZqQ2yFdZNTH1hD9A0q/hYgjAgRZmqzLQelEqoUfErC95RqHmoABV7WtF+Xt4QNTtOJap34TeewZIFhdSFnrgGyCy7vgmVDQiP6qqzHdgGJoe41RdorXqGi+O6GytViFeONxKLBiLJ84j" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_sv_112.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_sv_112.v new file mode 100644 index 0000000000..054b987b46 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_sv_112.v @@ -0,0 +1,145 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_sv_112 ( + input wire [7:0] di, + output reg [111:0] dout +); + +always @* + begin + case(di) + 8'b11100000 : dout = 112'h0000000000000000000000000001; + 8'b11010000 : dout = 112'h0000000000000000000000000002; + 8'b10110000 : dout = 112'h0000000000000000000000000004; + 8'b01110000 : dout = 112'h0000000000000000000000000008; + 8'b11001000 : dout = 112'h0000000000000000000000000010; + 8'b10101000 : dout = 112'h0000000000000000000000000020; + 8'b01101000 : dout = 112'h0000000000000000000000000040; + 8'b10011000 : dout = 112'h0000000000000000000000000080; + 8'b01011000 : dout = 112'h0000000000000000000000000100; + 8'b00111000 : dout = 112'h0000000000000000000000000200; + 8'b11000100 : dout = 112'h0000000000000000000000000400; + 8'b10100100 : dout = 112'h0000000000000000000000000800; + 8'b01100100 : dout = 112'h0000000000000000000000001000; + 8'b10010100 : dout = 112'h0000000000000000000000002000; + 8'b01010100 : dout = 112'h0000000000000000000000004000; + 8'b00110100 : dout = 112'h0000000000000000000000008000; + 8'b10001100 : dout = 112'h0000000000000000000000010000; + 8'b01001100 : dout = 112'h0000000000000000000000020000; + 8'b00101100 : dout = 112'h0000000000000000000000040000; + 8'b00011100 : dout = 112'h0000000000000000000000080000; + 8'b11000010 : dout = 112'h0000000000000000000000100000; + 8'b10100010 : dout = 112'h0000000000000000000000200000; + 8'b01100010 : dout = 112'h0000000000000000000000400000; + 8'b10010010 : dout = 112'h0000000000000000000000800000; + 8'b01010010 : dout = 112'h0000000000000000000001000000; + 8'b00110010 : dout = 112'h0000000000000000000002000000; + 8'b10001010 : dout = 112'h0000000000000000000004000000; + 8'b01001010 : dout = 112'h0000000000000000000008000000; + 8'b00101010 : dout = 112'h0000000000000000000010000000; + 8'b00011010 : dout = 112'h0000000000000000000020000000; + 8'b10000110 : dout = 112'h0000000000000000000040000000; + 8'b01000110 : dout = 112'h0000000000000000000080000000; + 8'b00100110 : dout = 112'h0000000000000000000100000000; + 8'b00010110 : dout = 112'h0000000000000000000200000000; + 8'b00001110 : dout = 112'h0000000000000000000400000000; + 8'b11000001 : dout = 112'h0000000000000000000800000000; + 8'b10100001 : dout = 112'h0000000000000000001000000000; + 8'b01100001 : dout = 112'h0000000000000000002000000000; + 8'b10010001 : dout = 112'h0000000000000000004000000000; + 8'b01010001 : dout = 112'h0000000000000000008000000000; + 8'b00110001 : dout = 112'h0000000000000000010000000000; + 8'b10001001 : dout = 112'h0000000000000000020000000000; + 8'b01001001 : dout = 112'h0000000000000000040000000000; + 8'b00101001 : dout = 112'h0000000000000000080000000000; + 8'b00011001 : dout = 112'h0000000000000000100000000000; + 8'b10000101 : dout = 112'h0000000000000000200000000000; + 8'b01000101 : dout = 112'h0000000000000000400000000000; + 8'b00100101 : dout = 112'h0000000000000000800000000000; + 8'b00010101 : dout = 112'h0000000000000001000000000000; + 8'b00001101 : dout = 112'h0000000000000002000000000000; + 8'b10000011 : dout = 112'h0000000000000004000000000000; + 8'b01000011 : dout = 112'h0000000000000008000000000000; + 8'b00100011 : dout = 112'h0000000000000010000000000000; + 8'b00010011 : dout = 112'h0000000000000020000000000000; + 8'b00001011 : dout = 112'h0000000000000040000000000000; + 8'b00000111 : dout = 112'h0000000000000080000000000000; + 8'b11111000 : dout = 112'h0000000000000100000000000000; + 8'b11110100 : dout = 112'h0000000000000200000000000000; + 8'b11101100 : dout = 112'h0000000000000400000000000000; + 8'b11011100 : dout = 112'h0000000000000800000000000000; + 8'b10111100 : dout = 112'h0000000000001000000000000000; + 8'b01111100 : dout = 112'h0000000000002000000000000000; + 8'b11110010 : dout = 112'h0000000000004000000000000000; + 8'b11101010 : dout = 112'h0000000000008000000000000000; + 8'b11011010 : dout = 112'h0000000000010000000000000000; + 8'b10111010 : dout = 112'h0000000000020000000000000000; + 8'b01111010 : dout = 112'h0000000000040000000000000000; + 8'b11100110 : dout = 112'h0000000000080000000000000000; + 8'b11010110 : dout = 112'h0000000000100000000000000000; + 8'b10110110 : dout = 112'h0000000000200000000000000000; + 8'b01110110 : dout = 112'h0000000000400000000000000000; + 8'b11001110 : dout = 112'h0000000000800000000000000000; + 8'b10101110 : dout = 112'h0000000001000000000000000000; + 8'b01101110 : dout = 112'h0000000002000000000000000000; + 8'b10011110 : dout = 112'h0000000004000000000000000000; + 8'b01011110 : dout = 112'h0000000008000000000000000000; + 8'b00111110 : dout = 112'h0000000010000000000000000000; + 8'b11110001 : dout = 112'h0000000020000000000000000000; + 8'b11101001 : dout = 112'h0000000040000000000000000000; + 8'b11011001 : dout = 112'h0000000080000000000000000000; + 8'b10111001 : dout = 112'h0000000100000000000000000000; + 8'b01111001 : dout = 112'h0000000200000000000000000000; + 8'b11100101 : dout = 112'h0000000400000000000000000000; + 8'b11010101 : dout = 112'h0000000800000000000000000000; + 8'b10110101 : dout = 112'h0000001000000000000000000000; + 8'b01110101 : dout = 112'h0000002000000000000000000000; + 8'b11001101 : dout = 112'h0000004000000000000000000000; + 8'b10101101 : dout = 112'h0000008000000000000000000000; + 8'b01101101 : dout = 112'h0000010000000000000000000000; + 8'b10011101 : dout = 112'h0000020000000000000000000000; + 8'b01011101 : dout = 112'h0000040000000000000000000000; + 8'b00111101 : dout = 112'h0000080000000000000000000000; + 8'b11100011 : dout = 112'h0000100000000000000000000000; + 8'b11010011 : dout = 112'h0000200000000000000000000000; + 8'b10110011 : dout = 112'h0000400000000000000000000000; + 8'b01110011 : dout = 112'h0000800000000000000000000000; + 8'b11001011 : dout = 112'h0001000000000000000000000000; + 8'b10101011 : dout = 112'h0002000000000000000000000000; + 8'b01101011 : dout = 112'h0004000000000000000000000000; + 8'b10011011 : dout = 112'h0008000000000000000000000000; + 8'b01011011 : dout = 112'h0010000000000000000000000000; + 8'b00111011 : dout = 112'h0020000000000000000000000000; + 8'b11000111 : dout = 112'h0040000000000000000000000000; + 8'b10100111 : dout = 112'h0080000000000000000000000000; + 8'b01100111 : dout = 112'h0100000000000000000000000000; + 8'b10010111 : dout = 112'h0200000000000000000000000000; + 8'b01010111 : dout = 112'h0400000000000000000000000000; + 8'b00110111 : dout = 112'h0800000000000000000000000000; + 8'b10001111 : dout = 112'h1000000000000000000000000000; + 8'b01001111 : dout = 112'h2000000000000000000000000000; + 8'b00101111 : dout = 112'h4000000000000000000000000000; + 8'b00011111 : dout = 112'h800000000000_0000_0000_0000_0000; + default: dout = 112'd0; + endcase + end +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EDL+Kx1GJswSvO1FgFTTjrA44zRAvW3/bEUybBOO+NfkRaG0GKBzL2u+ogyIoumTowmacKTR2HRLYTQe466P2Hgcau1jtQ6MJxXJ2UpsO+xMCjjdlBASlnmIu3qCugpXDlFRqIZ29TfArwtTw0sHh2dKobs9FzuIya12sMn7tOKm6aIPjqK7Qv74khUIaG8QRqnTyTpxAA+Fea26tX7MCNnvqim8dOsuxz4ODAM2TZjueBbkkiKo1r+iBLUwyPkZFvpzkFJloDgZCLexdVenh64OFCIAMVAFIRyHNbqmpFN5BnERRk3TXg0hhUORZV3RjY42/caeCnXa+vqFS8ZZeTePVPTsR1MV9h49lsitF8+A+urw/AF12N1qeum0bnawHm+BOHDA1z6IQCzi+1zLRXWXnWfxR+o1pWo/NPndibqKesfCXCK0Vbe/oarWWVqAoNxmpD1f1vA7KK7/8j4eR0uDngOLFixaCPcZlOaXbnxocYukqaWETf8uyPWq3iYvNqrEJAnA2A3+w9Pw9SFbsdH3Gx91eK1IuS2hVLErW/YhvfjdsfWzgMHMag1DOnvh1UTXslLxlFatlo81sbo0CsyoBWfwQLEVeyYI6m4xLm8T7VQyjZ66hh3WrmYlXHNOeCQk4j43muuPhOZINp7AmkmNxsrGVcjtWbv97aKdoYBV0/RL5LHZ1d7hzflVQo1c8r2S8un9Zay/jaNSQpJkfKOziUKRJh+ZyokBTeQFyx3lRjwETQV4xLU99ROBlHtk8d0agPOmZNbT/pnZ242EiaB" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_wrapper.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_wrapper.v new file mode 100644 index 0000000000..3adb68828e --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_ecc_wrapper.v @@ -0,0 +1,818 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module fmiohmc_ecc_wrapper # + ( parameter + CFG_LOCAL_CMD_WIDTH = 2, + CFG_LOCAL_ADDR_WIDTH = 35, + CFG_LOCAL_SIZE_WIDTH = 8, + CFG_LOCAL_ID_WIDTH = 13, + CFG_LOCAL_PRI_WIDTH = 1, + CFG_LOCAL_AP_WIDTH = 1, + CFG_LOCAL_MC_WIDTH = 1, + CFG_CMD_DATA_WIDTH = 61, + CFG_CMD_INFO_WIDTH = 3, + CFG_LOCAL_DATA_WIDTH = 81*8, + CFG_LOCAL_BE_WIDTH = 9*8, + CFG_LOCAL_DATA_INFO_WIDTH = 3, + CFG_LOCAL_DATA_PTR_WIDTH = 6*2, + CFG_ECC_DATA_WIDTH = 81*8, + CFG_ECC_BE_WIDTH = 9*8, + CFG_ECC_CODE_WIDTH = 8, + CFG_ECC_MULTIPLE_INSTANCE = 8, + + CFG_REGISTER_CMD_PATH = 0, + CFG_REGISTER_RDATA_PATH = 0, + CFG_REGISTER_RDATA_PATH_NUM = 0, + CFG_REGISTER_UFI_RDATA_PATH_NUM = 0, + CFG_REGISTER_WDATA_PATH = 0, + CFG_REGISTER_WDATA_PATH_NUM = 0, + CFG_REGISTER_ST_WDATA_RDY_LAT_PATH = 0, + CFG_REGISTER_ST_RDATA_RDY_LAT_PATH = 0, + CFG_REGISTER_ST_CMD_RDY_LAT_PATH = 0, + CORE_CMD_PIPELINE_WDATA = 0, + + CFG_MMR_ADDR_WIDTH = 10, + CFG_MMR_DATA_WIDTH = 32, + CFG_MMR_BYTE_ENABLE_WIDTH = 4, + CFG_MMR_BURSTCOUNT_WIDTH = 2, + + MMR_DRAM_DATA_WIDTH = 0, + MMR_LOCAL_DATA_WIDTH = 0, + MMR_ADDR_WIDTH = 0, + MMR_DATA_RATE = 0, + MMR_ECC_IN_PROTOCOL = 0, + MMR_WRPATH_PIPELINE_EN = 0, + MMR_ENABLE_ECC = 0, + MMR_ENABLE_DM = 0, + MMR_ENABLE_RMW = 0, + MMR_ENABLE_AUTO_CORR = 0, + MMR_ECC_CODE_OVERWRITE = 0, + MMR_GEN_SBE = 0, + MMR_GEN_DBE = 0, + MMR_ENABLE_INTR = 0, + MMR_MASK_SBE_INTR = 0, + MMR_MASK_DBE_INTR = 0, + MMR_MASK_CORR_DROPPED_INTR = 0, + MMR_MASK_HMI_INTR = 0, + MMR_CLR_INTR = 0, + MMR_CLR_MR_RDATA = 0, + ECC_MMR_READ_LATENCY = 2, + + CFG_WRBUFFER_ADDR_WIDTH = 4, + CFG_PORT_WIDTH_DRAM_DATA_WIDTH = 8, + CFG_PORT_WIDTH_LOCAL_DATA_WIDTH = 8, + CFG_PORT_WIDTH_ADDR_WIDTH = 6, + CFG_PORT_WIDTH_DATA_RATE = 4, + CFG_PORT_WIDTH_ECC_IN_PROTOCOL = 1, + CFG_PORT_WIDTH_WRPATH_PIPELINE_EN = 1, + CFG_PORT_WIDTH_ENABLE_ECC = 1, + CFG_PORT_WIDTH_ENABLE_DM = 1, + CFG_PORT_WIDTH_ENABLE_RMW = 1, + CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1, + CFG_PORT_WIDTH_ECC_CODE_OVERWRITE = 1, + CFG_PORT_WIDTH_GEN_SBE = 1, + CFG_PORT_WIDTH_GEN_DBE = 1, + CFG_PORT_WIDTH_ENABLE_INTR = 1, + CFG_PORT_WIDTH_MASK_SBE_INTR = 1, + CFG_PORT_WIDTH_MASK_DBE_INTR = 1, + CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1, + CFG_PORT_WIDTH_MASK_HMI_INTR = 1, + CFG_PORT_WIDTH_CLR_INTR = 1, + CFG_PORT_WIDTH_CLR_MR_RDATA = 1, + + STS_PORT_WIDTH_ECC_INTR = 1, + STS_PORT_WIDTH_SBE_ERROR = 1, + STS_PORT_WIDTH_DBE_ERROR = 1, + STS_PORT_WIDTH_CORR_DROPPED = 1, + STS_PORT_WIDTH_SBE_COUNT = 4, + STS_PORT_WIDTH_DBE_COUNT = 4, + STS_PORT_WIDTH_CORR_DROPPED_COUNT = 4, + STS_PORT_WIDTH_ERR_ADDR = 35, + STS_PORT_WIDTH_CORR_DROPPED_ADDR = 35, + STS_PORT_WIDTH_MR_DATA = 81*8, + STS_PORT_WIDTH_MR_DATA_VALID = 1 + ) + ( + ctl_clk, + ctl_reset_n_pre_reg, + + slave_mmr_ready, + slave_mmr_address, + slave_mmr_write, + slave_mmr_read, + slave_mmr_burstcount, + slave_mmr_begintransfer, + slave_mmr_wr_data, + slave_mmr_rd_data, + slave_mmr_rd_data_valid, + + master_mmr_ready, + master_mmr_address, + master_mmr_write, + master_mmr_read, + master_mmr_burstcount, + master_mmr_begintransfer, + master_mmr_wr_data, + master_mmr_rd_data, + master_mmr_rd_data_valid, + + slave_cmd_ready, + slave_cmd_data, + slave_cmd_valid, + slave_wr_data_ready, + slave_wr_data_byte_enable, + slave_wr_data, + slave_wr_data_id, + slave_wr_data_valid, + slave_rd_data_ready, + slave_rd_data, + slave_rd_data_id, + slave_rd_data_valid, + slave_rd_data_error, + slave_rd_data_type, + + sts_ecc_intr, + sts_sbe_error, + sts_dbe_error, + sts_corr_dropped, + sts_sbe_count, + sts_dbe_count, + sts_corr_dropped_count, + sts_err_addr, + sts_corr_dropped_addr, + + master_cmd_ready, + master_cmd_data, + master_cmd_valid, + master_cmd_data_combi, + master_cmd_valid_combi, + master_cmd_info, + master_wr_data_ready, + master_wr_data_byte_enable, + master_wr_data, + master_wr_data_id, + master_wr_data_info, + master_wr_data_ptr_in, + master_wr_data_ptr_out, + master_wr_data_valid, + master_rd_data_ready, + master_rd_data, + master_rd_data_id, + master_rd_data_info, + master_rd_data_valid, + master_rd_data_type, + + user_interrupt, + hmi_interrupt + ); + +localparam RD_FIFO_WIDTH = CFG_ECC_DATA_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_LOCAL_DATA_INFO_WIDTH + 1; + +input ctl_clk; +input ctl_reset_n_pre_reg; + +output slave_mmr_ready; +input [CFG_MMR_ADDR_WIDTH - 1 : 0] slave_mmr_address; +input slave_mmr_write; +input slave_mmr_read; +input [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] slave_mmr_burstcount; +input slave_mmr_begintransfer; +input [CFG_MMR_DATA_WIDTH - 1 : 0] slave_mmr_wr_data; +output [CFG_MMR_DATA_WIDTH - 1 : 0] slave_mmr_rd_data; +output slave_mmr_rd_data_valid; + +input master_mmr_ready; +output [CFG_MMR_ADDR_WIDTH - 1 : 0] master_mmr_address; +output master_mmr_write; +output master_mmr_read; +output [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] master_mmr_burstcount; +output master_mmr_begintransfer; +output [CFG_MMR_DATA_WIDTH - 1 : 0] master_mmr_wr_data; +input [CFG_MMR_DATA_WIDTH - 1 : 0] master_mmr_rd_data; +input master_mmr_rd_data_valid; + +output slave_cmd_ready; +input [CFG_CMD_DATA_WIDTH - 1 : 0] slave_cmd_data; +input slave_cmd_valid; +output slave_wr_data_ready; +input [CFG_LOCAL_BE_WIDTH - 1 : 0] slave_wr_data_byte_enable; +input [CFG_LOCAL_DATA_WIDTH - 1 : 0] slave_wr_data; +input [CFG_LOCAL_ID_WIDTH - 1 : 0] slave_wr_data_id; +input slave_wr_data_valid; +input slave_rd_data_ready; +output [CFG_LOCAL_DATA_WIDTH - 1 : 0] slave_rd_data; +output [CFG_LOCAL_ID_WIDTH - 1 : 0] slave_rd_data_id; +output slave_rd_data_valid; +output slave_rd_data_error; +output slave_rd_data_type; + +input master_cmd_ready; +output [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data; +output master_cmd_valid; +output [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data_combi; +output master_cmd_valid_combi; +input [CFG_CMD_INFO_WIDTH - 1 : 0] master_cmd_info; +input master_wr_data_ready; +output [CFG_ECC_BE_WIDTH - 1 : 0] master_wr_data_byte_enable; +output [CFG_ECC_DATA_WIDTH - 1 : 0] master_wr_data; +output [CFG_LOCAL_ID_WIDTH - 1 : 0] master_wr_data_id; +output [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info; +input [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] master_wr_data_ptr_in; +output [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] master_wr_data_ptr_out; +output master_wr_data_valid; +output master_rd_data_ready; +input [CFG_ECC_DATA_WIDTH - 1 : 0] master_rd_data; +input [CFG_LOCAL_ID_WIDTH - 1 : 0] master_rd_data_id; +input [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_rd_data_info; +input master_rd_data_valid; +input master_rd_data_type; + +output user_interrupt; +input hmi_interrupt; + + +output wire [STS_PORT_WIDTH_ECC_INTR - 1 : 0] sts_ecc_intr; +output wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error; +output wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error; +output wire [STS_PORT_WIDTH_CORR_DROPPED - 1 : 0] sts_corr_dropped; +output wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count; +output wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count; +output wire [STS_PORT_WIDTH_CORR_DROPPED_COUNT- 1 : 0] sts_corr_dropped_count; +output wire [STS_PORT_WIDTH_ERR_ADDR - 1 : 0] sts_err_addr; +output wire [STS_PORT_WIDTH_CORR_DROPPED_ADDR - 1 : 0] sts_corr_dropped_addr; + +wire [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_0; +wire [STS_PORT_WIDTH_MR_DATA - 1 : 0] sts_mr_rdata_1; +wire [STS_PORT_WIDTH_MR_DATA_VALID - 1 : 0] sts_mr_rdata_valid; +wire slave_cmd_ready; +wire slave_wr_data_ready; +wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] slave_rd_data; +wire [CFG_LOCAL_ID_WIDTH - 1 : 0] slave_rd_data_id; +wire slave_rd_data_valid; +wire slave_rd_data_error; +wire slave_rd_data_type; +wire [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data; +wire master_cmd_valid; +wire [CFG_CMD_DATA_WIDTH - 1 : 0] master_cmd_data_combi; +wire master_cmd_valid_combi; +wire [CFG_ECC_BE_WIDTH - 1 : 0] master_wr_data_byte_enable; +wire [CFG_ECC_DATA_WIDTH - 1 : 0] master_wr_data; +wire [CFG_LOCAL_ID_WIDTH - 1 : 0] master_wr_data_id; +wire [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_wr_data_info; +wire [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] master_wr_data_ptr_out; +wire master_wr_data_valid; +wire master_rd_data_ready; +wire user_interrupt; +wire [CFG_PORT_WIDTH_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width; +wire [CFG_PORT_WIDTH_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width; +wire [CFG_PORT_WIDTH_ADDR_WIDTH - 1 : 0] cfg_addr_width; +wire [CFG_PORT_WIDTH_DATA_RATE - 1 : 0] cfg_data_rate; +wire [CFG_PORT_WIDTH_ECC_IN_PROTOCOL - 1 : 0] cfg_ecc_in_protocol; +wire [CFG_PORT_WIDTH_WRPATH_PIPELINE_EN - 1 : 0] cfg_wrpath_pipeline_en; +wire [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc; +wire [CFG_PORT_WIDTH_ENABLE_DM - 1 : 0] cfg_enable_dm; +wire [CFG_PORT_WIDTH_ENABLE_RMW - 1 : 0] cfg_enable_rmw; +wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr; +wire [CFG_PORT_WIDTH_ECC_CODE_OVERWRITE - 1 : 0] cfg_ecc_code_overwrite; +wire [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe; +wire [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe; +wire [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr; +wire [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr; +wire [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr; +wire [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr; +wire [CFG_PORT_WIDTH_MASK_HMI_INTR - 1 : 0] cfg_mask_hmi_intr; +wire [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr; +wire [CFG_PORT_WIDTH_CLR_MR_RDATA - 1 : 0] cfg_clr_mr_rdata; +wire slave_mmr_ready; +wire [CFG_MMR_DATA_WIDTH - 1 : 0] slave_mmr_rd_data; +wire slave_mmr_rd_data_valid; +wire [CFG_MMR_ADDR_WIDTH - 1 : 0] master_mmr_address; +wire master_mmr_write; +wire master_mmr_read; +wire [CFG_MMR_BURSTCOUNT_WIDTH - 1 : 0] master_mmr_burstcount; +wire master_mmr_begintransfer; +wire [CFG_MMR_DATA_WIDTH - 1 : 0] master_mmr_wr_data; + +(* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) reg internal_master_wr_data_ready; +(* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) reg [CFG_ECC_BE_WIDTH - 1 : 0] internal_master_wr_data_byte_enable; +reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] internal_master_wr_data_info; +(* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] internal_master_wr_data_ptr_in; +reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] internal_master_wr_data_ptr_out; +reg internal_master_wr_data_valid; +reg internal_master_rd_data_ready; + +(* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) reg internal_master_cmd_ready; +reg [CFG_CMD_DATA_WIDTH - 1 : 0] internal_master_cmd_data; +(* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) reg internal_master_cmd_valid; +reg [CFG_CMD_INFO_WIDTH - 1 : 0] internal_master_cmd_info; + +wire int_master_cmd_ready; +wire [CFG_CMD_DATA_WIDTH - 1 : 0] int_master_cmd_data; +wire [CFG_CMD_INFO_WIDTH - 1 : 0] int_master_cmd_info; +wire int_master_cmd_valid; + +reg [CFG_ECC_DATA_WIDTH - 1 : 0] internal_master_wr_data; +reg [CFG_LOCAL_ID_WIDTH - 1 : 0] internal_master_wr_data_id; + +wire int_master_wr_data_ready; +wire [CFG_ECC_BE_WIDTH - 1 : 0] int_master_wr_data_byte_enable; +wire [CFG_ECC_DATA_WIDTH - 1 : 0] int_master_wr_data; +wire [CFG_LOCAL_ID_WIDTH - 1 : 0] int_master_wr_data_id; +wire [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] int_master_wr_data_info; +wire [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] int_master_wr_data_ptr_in; +wire [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] int_master_wr_data_ptr_out; +wire int_master_wr_data_valid; + +wire [CFG_ECC_DATA_WIDTH - 1 : 0] internal_master_rd_data; +wire [CFG_LOCAL_ID_WIDTH - 1 : 0] internal_master_rd_data_id; +wire [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] internal_master_rd_data_info; +wire internal_master_rd_data_valid; +wire internal_master_rd_data_type; + +wire int_master_rd_data_ready; +wire [CFG_ECC_DATA_WIDTH - 1 : 0] int_master_rd_data; +wire [CFG_LOCAL_ID_WIDTH - 1 : 0] int_master_rd_data_id; +wire [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] int_master_rd_data_info; +wire int_master_rd_data_valid; +wire int_master_rd_data_type; + +wire mux_master_cmd_ready; + +// Pipeline the input reset_n signal. +// Don't use input reset_n directly because if it is promoted to global, +// the insertion delay is big enough to cause downstream logic that uses the +// reset as comb input to fail setup timing. +reg [25:0] ctl_reset_n /* synthesis preserve_syn_only = 1 */; +always @(posedge ctl_clk or negedge ctl_reset_n_pre_reg) +begin + if (!ctl_reset_n_pre_reg) begin + ctl_reset_n[25:0] <= 26'b0; + end else begin + ctl_reset_n[25:0] <= {26{1'b1}}; + end +end + +always @ (posedge ctl_clk) +begin + internal_master_cmd_ready <= master_cmd_ready; +end + +always @ (posedge ctl_clk) +begin + internal_master_cmd_valid <= int_master_cmd_valid & mux_master_cmd_ready; +end + +always @ (posedge ctl_clk) +begin + internal_master_cmd_data <= int_master_cmd_data; + internal_master_cmd_info <= master_cmd_info; +end + +assign int_master_cmd_ready = (CFG_REGISTER_CMD_PATH == 1) ? internal_master_cmd_ready : master_cmd_ready; +assign int_master_cmd_info = (CFG_REGISTER_CMD_PATH == 1) ? internal_master_cmd_info : master_cmd_info; + +assign master_cmd_data = (CFG_REGISTER_CMD_PATH == 1) ? internal_master_cmd_data : int_master_cmd_data; +assign master_cmd_valid = (CFG_REGISTER_CMD_PATH == 1) ? internal_master_cmd_valid : (int_master_cmd_valid & mux_master_cmd_ready); + +reg [CFG_ECC_BE_WIDTH - 1 : 0] internal_master_wr_data_byte_enable_r [1:0]; +reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] internal_master_wr_data_info_r [1:0]; +reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] internal_master_wr_data_ptr_out_r [1:0]; +reg internal_master_wr_data_valid_r [1:0]; +reg [CFG_ECC_DATA_WIDTH - 1 : 0] internal_master_wr_data_r [1:0]; +reg [CFG_LOCAL_ID_WIDTH - 1 : 0] internal_master_wr_data_id_r [1:0]; +reg internal_master_wr_data_ready_r [1:0]; +reg [CFG_LOCAL_DATA_PTR_WIDTH - 1 : 0] internal_master_wr_data_ptr_in_r [1:0]; + +always @ (posedge ctl_clk) +begin + internal_master_wr_data_valid_r[0] <= int_master_wr_data_valid; + internal_master_wr_data_valid_r[1] <= internal_master_wr_data_valid_r[0]; + + internal_master_wr_data_r[0] <= int_master_wr_data; + internal_master_wr_data_r[1] <= internal_master_wr_data_r[0]; + internal_master_wr_data_byte_enable_r[0] <= int_master_wr_data_byte_enable; + internal_master_wr_data_byte_enable_r[1] <= internal_master_wr_data_byte_enable_r[0]; + internal_master_wr_data_id_r[0] <= int_master_wr_data_id; + internal_master_wr_data_id_r[1] <= internal_master_wr_data_id_r[0]; + internal_master_wr_data_info_r[0] <= int_master_wr_data_info; + internal_master_wr_data_info_r[1] <= internal_master_wr_data_info_r[0]; + internal_master_wr_data_ptr_out_r[0] <= int_master_wr_data_ptr_out; + internal_master_wr_data_ptr_out_r[1] <= internal_master_wr_data_ptr_out_r[0]; + + internal_master_wr_data_ptr_in_r[0] <= master_wr_data_ptr_in; + internal_master_wr_data_ptr_in_r[1] <= internal_master_wr_data_ptr_in_r[0]; + + internal_master_wr_data_ready_r[0] <= master_wr_data_ready; + internal_master_wr_data_ready_r[1] <= internal_master_wr_data_ready_r[0]; + + if (CFG_REGISTER_WDATA_PATH_NUM < 2) + begin + internal_master_wr_data_valid <= int_master_wr_data_valid; + internal_master_wr_data <= int_master_wr_data; + internal_master_wr_data_byte_enable <= int_master_wr_data_byte_enable; + internal_master_wr_data_id <= int_master_wr_data_id; + internal_master_wr_data_info <= int_master_wr_data_info; + internal_master_wr_data_ptr_out <= int_master_wr_data_ptr_out; + internal_master_wr_data_ready <= master_wr_data_ready; + internal_master_wr_data_ptr_in <= master_wr_data_ptr_in; + end + else if (CFG_REGISTER_WDATA_PATH_NUM == 2) + begin + internal_master_wr_data_valid <= internal_master_wr_data_valid_r [0]; + internal_master_wr_data <= internal_master_wr_data_r [0]; + internal_master_wr_data_byte_enable <= internal_master_wr_data_byte_enable_r [0]; + internal_master_wr_data_id <= internal_master_wr_data_id_r [0]; + internal_master_wr_data_info <= internal_master_wr_data_info_r [0]; + internal_master_wr_data_ptr_out <= internal_master_wr_data_ptr_out_r [0]; + internal_master_wr_data_ready <= internal_master_wr_data_ready_r [0]; + internal_master_wr_data_ptr_in <= internal_master_wr_data_ptr_in_r [0]; + end + else if (CFG_REGISTER_WDATA_PATH_NUM == 4) + begin + internal_master_wr_data_valid <= internal_master_wr_data_valid_r [1]; + internal_master_wr_data <= internal_master_wr_data_r [1]; + internal_master_wr_data_byte_enable <= internal_master_wr_data_byte_enable_r [1]; + internal_master_wr_data_id <= internal_master_wr_data_id_r [1]; + internal_master_wr_data_info <= internal_master_wr_data_info_r [1]; + internal_master_wr_data_ptr_out <= internal_master_wr_data_ptr_out_r [1]; + internal_master_wr_data_ready <= internal_master_wr_data_ready_r [1]; + internal_master_wr_data_ptr_in <= internal_master_wr_data_ptr_in_r [1]; + end +end + +assign int_master_wr_data_ready = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_ready : master_wr_data_ready; +assign int_master_wr_data_ptr_in = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_ptr_in : master_wr_data_ptr_in; + +assign master_wr_data_byte_enable = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_byte_enable : int_master_wr_data_byte_enable; +assign master_wr_data = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data : int_master_wr_data; +assign master_wr_data_id = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_id : int_master_wr_data_id; +assign master_wr_data_info = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_info : int_master_wr_data_info; +assign master_wr_data_ptr_out = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_ptr_out : int_master_wr_data_ptr_out; +assign master_wr_data_valid = (CFG_REGISTER_WDATA_PATH == 1) ? internal_master_wr_data_valid : int_master_wr_data_valid; + +assign master_rd_data_ready = (CFG_REGISTER_RDATA_PATH == 1) ? internal_master_rd_data_ready : int_master_rd_data_ready; + +assign int_master_rd_data = (CFG_REGISTER_RDATA_PATH == 1) ? internal_master_rd_data : master_rd_data; +assign int_master_rd_data_id = (CFG_REGISTER_RDATA_PATH == 1) ? internal_master_rd_data_id : master_rd_data_id; +assign int_master_rd_data_info = (CFG_REGISTER_RDATA_PATH == 1) ? internal_master_rd_data_info : master_rd_data_info; +assign int_master_rd_data_valid = (CFG_REGISTER_RDATA_PATH == 1) ? internal_master_rd_data_valid : master_rd_data_valid; +assign int_master_rd_data_type = (CFG_REGISTER_RDATA_PATH == 1) ? internal_master_rd_data_type : master_rd_data_type; + +generate + if (CFG_REGISTER_RDATA_PATH == 1) + begin + reg [CFG_ECC_DATA_WIDTH - 1 : 0] master_rd_data_r; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] master_rd_data_id_r; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_rd_data_info_r; + reg master_rd_data_valid_r; + reg master_rd_data_type_r; + + reg [CFG_ECC_DATA_WIDTH - 1 : 0] master_rd_data_pipe_out; + reg [CFG_LOCAL_ID_WIDTH - 1 : 0] master_rd_data_id_pipe_out; + reg [CFG_LOCAL_DATA_INFO_WIDTH - 1 : 0] master_rd_data_info_pipe_out; + reg master_rd_data_valid_pipe_out; + reg master_rd_data_type_pipe_out; + + wire [RD_FIFO_WIDTH - 1 : 0] rd_fifo_wr_data; + wire rd_fifo_wr_ready; + wire rd_fifo_wr_valid; + wire [RD_FIFO_WIDTH - 1 : 0] rd_fifo_rd_data; + wire rd_fifo_rd_ready; + wire rd_fifo_rd_valid; + + reg rd_fifo_wr_ready_r; + + assign rd_fifo_wr_data = {master_rd_data_pipe_out, master_rd_data_id_pipe_out, master_rd_data_info_pipe_out, master_rd_data_type_pipe_out}; + assign rd_fifo_wr_valid = master_rd_data_valid_pipe_out; + assign rd_fifo_rd_ready = int_master_rd_data_ready; + + assign {internal_master_rd_data, internal_master_rd_data_id, internal_master_rd_data_info, internal_master_rd_data_type} = rd_fifo_rd_data; + assign internal_master_rd_data_valid = rd_fifo_rd_valid; + + always @ (posedge ctl_clk) + begin + master_rd_data_valid_r <= master_rd_data_valid; + + master_rd_data_r <= master_rd_data; + master_rd_data_id_r <= master_rd_data_id; + master_rd_data_info_r <= master_rd_data_info; + master_rd_data_type_r <= master_rd_data_type; + + master_rd_data_pipe_out <= (CFG_REGISTER_RDATA_PATH_NUM == 2) ? master_rd_data_r : master_rd_data; + master_rd_data_id_pipe_out <= (CFG_REGISTER_RDATA_PATH_NUM == 2) ? master_rd_data_id_r : master_rd_data_id; + master_rd_data_info_pipe_out <= (CFG_REGISTER_RDATA_PATH_NUM == 2) ? master_rd_data_info_r : master_rd_data_info; + master_rd_data_type_pipe_out <= (CFG_REGISTER_RDATA_PATH_NUM == 2) ? master_rd_data_type_r : master_rd_data_type; + master_rd_data_valid_pipe_out <= (CFG_REGISTER_RDATA_PATH_NUM == 2) ? master_rd_data_valid_r : master_rd_data_valid; + end + + always @ (posedge ctl_clk) + begin + rd_fifo_wr_ready_r <= rd_fifo_wr_ready; + internal_master_rd_data_ready <= (CFG_REGISTER_RDATA_PATH_NUM == 2) ? rd_fifo_wr_ready_r : rd_fifo_wr_ready; + end + + (* altera_attribute = "-name AUTO_RAM_RECOGNITION OFF; -name INFER_RAMS_FROM_RAW_LOGIC OFF" *) + fmiohmc_ecc_interface_fifo + #( + .DATA_WIDTH (RD_FIFO_WIDTH ), + .RESERVE_ENTRY (2*(CFG_REGISTER_RDATA_PATH_NUM + CFG_REGISTER_UFI_RDATA_PATH_NUM)) + ) + iohmc_ecc_interface_fifo_inst + ( + .clk (ctl_clk ), + .reset_n (ctl_reset_n[0] ), + .in_ready (rd_fifo_wr_ready ), + .in_valid (rd_fifo_wr_valid ), + .in_data (rd_fifo_wr_data ), + .out_ready (rd_fifo_rd_ready ), + .out_valid (rd_fifo_rd_valid ), + .out_data (rd_fifo_rd_data ) + ); + end + else + begin + assign {internal_master_rd_data, internal_master_rd_data_id, internal_master_rd_data_info, internal_master_rd_data_type} = {RD_FIFO_WIDTH{1'b0}}; + assign internal_master_rd_data_valid = 1'b0; + end +endgenerate + +fmiohmc_ecc # + ( + .CFG_LOCAL_CMD_WIDTH (CFG_LOCAL_CMD_WIDTH ), + .CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ), + .CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ), + .CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ), + .CFG_LOCAL_PRI_WIDTH (CFG_LOCAL_PRI_WIDTH ), + .CFG_LOCAL_AP_WIDTH (CFG_LOCAL_AP_WIDTH ), + .CFG_LOCAL_MC_WIDTH (CFG_LOCAL_MC_WIDTH ), + .CFG_CMD_DATA_WIDTH (CFG_CMD_DATA_WIDTH ), + .CFG_CMD_INFO_WIDTH (CFG_CMD_INFO_WIDTH ), + .CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ), + .CFG_LOCAL_BE_WIDTH (CFG_LOCAL_BE_WIDTH ), + .CFG_LOCAL_DATA_INFO_WIDTH (CFG_LOCAL_DATA_INFO_WIDTH ), + .CFG_LOCAL_DATA_PTR_WIDTH (CFG_LOCAL_DATA_PTR_WIDTH ), + .CFG_ECC_DATA_WIDTH (CFG_ECC_DATA_WIDTH ), + .CFG_ECC_BE_WIDTH (CFG_ECC_BE_WIDTH ), + .CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ), + .CFG_ECC_MULTIPLE_INSTANCE (CFG_ECC_MULTIPLE_INSTANCE ), + .CFG_ECC_IN_PROTOCOL (MMR_ECC_IN_PROTOCOL ), + .CFG_REGISTER_RDATA_PATH (CFG_REGISTER_RDATA_PATH ), + .CFG_REGISTER_WDATA_PATH (CFG_REGISTER_WDATA_PATH ), + .CFG_REGISTER_WDATA_PATH_NUM (CFG_REGISTER_WDATA_PATH_NUM ), + .CFG_REGISTER_UFI_RDATA_PATH_NUM (CFG_REGISTER_UFI_RDATA_PATH_NUM ), + .CFG_REGISTER_ST_WDATA_RDY_LAT_PATH (CFG_REGISTER_ST_WDATA_RDY_LAT_PATH ), + .CFG_REGISTER_ST_RDATA_RDY_LAT_PATH (CFG_REGISTER_ST_RDATA_RDY_LAT_PATH ), + .CFG_REGISTER_ST_CMD_RDY_LAT_PATH (CFG_REGISTER_ST_CMD_RDY_LAT_PATH ), + .CORE_CMD_PIPELINE_WDATA (CORE_CMD_PIPELINE_WDATA ), + .CFG_WRBUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH ), + .CFG_PORT_WIDTH_DRAM_DATA_WIDTH (CFG_PORT_WIDTH_DRAM_DATA_WIDTH ), + .CFG_PORT_WIDTH_LOCAL_DATA_WIDTH (CFG_PORT_WIDTH_LOCAL_DATA_WIDTH ), + .CFG_PORT_WIDTH_ADDR_WIDTH (CFG_PORT_WIDTH_ADDR_WIDTH ), + .CFG_PORT_WIDTH_DATA_RATE (CFG_PORT_WIDTH_DATA_RATE ), + .CFG_PORT_WIDTH_ECC_IN_PROTOCOL (CFG_PORT_WIDTH_ECC_IN_PROTOCOL ), + .CFG_PORT_WIDTH_WRPATH_PIPELINE_EN (CFG_PORT_WIDTH_WRPATH_PIPELINE_EN ), + .CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ), + .CFG_PORT_WIDTH_ENABLE_DM (CFG_PORT_WIDTH_ENABLE_DM ), + .CFG_PORT_WIDTH_ENABLE_RMW (CFG_PORT_WIDTH_ENABLE_RMW ), + .CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ), + .CFG_PORT_WIDTH_ECC_CODE_OVERWRITE (CFG_PORT_WIDTH_ECC_CODE_OVERWRITE ), + .CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ), + .CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ), + .CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ), + .CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ), + .CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ), + .CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR ), + .CFG_PORT_WIDTH_MASK_HMI_INTR (CFG_PORT_WIDTH_MASK_HMI_INTR ), + .CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ), + .CFG_PORT_WIDTH_CLR_MR_RDATA (CFG_PORT_WIDTH_CLR_MR_RDATA ), + .STS_PORT_WIDTH_ECC_INTR (STS_PORT_WIDTH_ECC_INTR ), + .STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ), + .STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ), + .STS_PORT_WIDTH_CORR_DROPPED (STS_PORT_WIDTH_CORR_DROPPED ), + .STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ), + .STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ), + .STS_PORT_WIDTH_CORR_DROPPED_COUNT (STS_PORT_WIDTH_CORR_DROPPED_COUNT ), + .STS_PORT_WIDTH_ERR_ADDR (STS_PORT_WIDTH_ERR_ADDR ), + .STS_PORT_WIDTH_CORR_DROPPED_ADDR (STS_PORT_WIDTH_CORR_DROPPED_ADDR ), + .STS_PORT_WIDTH_MR_DATA (STS_PORT_WIDTH_MR_DATA ), + .STS_PORT_WIDTH_MR_DATA_VALID (STS_PORT_WIDTH_MR_DATA_VALID ) + ) +iohmc_ecc_inst + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[24:1] ), + .cfg_dram_data_width (cfg_dram_data_width ), + .cfg_local_data_width (cfg_local_data_width ), + .cfg_addr_width (cfg_addr_width ), + .cfg_data_rate (cfg_data_rate ), + .cfg_ecc_in_protocol (cfg_ecc_in_protocol ), + .cfg_wrpath_pipeline_en (cfg_wrpath_pipeline_en ), + .cfg_enable_ecc (cfg_enable_ecc ), + .cfg_enable_dm (cfg_enable_dm ), + .cfg_enable_rmw (cfg_enable_rmw ), + .cfg_enable_auto_corr (cfg_enable_auto_corr ), + .cfg_ecc_code_overwrite (cfg_ecc_code_overwrite ), + .cfg_gen_sbe (cfg_gen_sbe ), + .cfg_gen_dbe (cfg_gen_dbe ), + .cfg_enable_intr (cfg_enable_intr ), + .cfg_mask_sbe_intr (cfg_mask_sbe_intr ), + .cfg_mask_dbe_intr (cfg_mask_dbe_intr ), + .cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ), + .cfg_mask_hmi_intr (cfg_mask_hmi_intr ), + .cfg_clr_intr (cfg_clr_intr ), + .cfg_clr_mr_rdata (cfg_clr_mr_rdata ), + .sts_ecc_intr (sts_ecc_intr ), + .sts_sbe_error (sts_sbe_error ), + .sts_dbe_error (sts_dbe_error ), + .sts_corr_dropped (sts_corr_dropped ), + .sts_sbe_count (sts_sbe_count ), + .sts_dbe_count (sts_dbe_count ), + .sts_corr_dropped_count (sts_corr_dropped_count ), + .sts_err_addr (sts_err_addr ), + .sts_corr_dropped_addr (sts_corr_dropped_addr ), + .sts_mr_rdata_0 (sts_mr_rdata_0 ), + .sts_mr_rdata_1 (sts_mr_rdata_1 ), + .sts_mr_rdata_valid (sts_mr_rdata_valid ), + .sts_corr_dropped_valid ( ), + .sts_current_addr ( ), + .decoder_output_err_addr ( ), + .decoder_output_data_valid ( ), + .decoder_output_sbe ( ), + .decoder_output_dbe ( ), + .decoder_output_data_dbe ( ), + .decoder_output_addrerr ( ), + .slave_cmd_ready (slave_cmd_ready ), + .slave_cmd_data (slave_cmd_data ), + .slave_cmd_valid (slave_cmd_valid ), + .slave_wr_data_ready (slave_wr_data_ready ), + .slave_wr_data_byte_enable (slave_wr_data_byte_enable ), + .slave_wr_data (slave_wr_data ), + .slave_wr_data_id (slave_wr_data_id ), + .slave_wr_data_valid (slave_wr_data_valid ), + .slave_rd_data_ready (slave_rd_data_ready ), + .slave_rd_data (slave_rd_data ), + .slave_rd_data_id (slave_rd_data_id ), + .slave_rd_data_valid (slave_rd_data_valid ), + .slave_rd_data_error (slave_rd_data_error ), + .slave_rd_data_type (slave_rd_data_type ), + .master_cmd_ready (int_master_cmd_ready ), + .master_cmd_data (int_master_cmd_data ), + .master_cmd_valid (int_master_cmd_valid ), + .master_cmd_data_combi (master_cmd_data_combi ), + .master_cmd_valid_combi (master_cmd_valid_combi ), + .master_cmd_info (int_master_cmd_info ), + .master_wr_data_ready (int_master_wr_data_ready ), + .master_wr_data_byte_enable (int_master_wr_data_byte_enable ), + .master_wr_data (int_master_wr_data ), + .master_wr_data_id (int_master_wr_data_id ), + .master_wr_data_info (int_master_wr_data_info ), + .master_wr_data_ptr_in (int_master_wr_data_ptr_in ), + .master_wr_data_ptr_out (int_master_wr_data_ptr_out ), + .master_wr_data_valid (int_master_wr_data_valid ), + .master_rd_data_ready (int_master_rd_data_ready ), + .master_rd_data (int_master_rd_data ), + .master_rd_data_id (int_master_rd_data_id ), + .master_rd_data_info (int_master_rd_data_info ), + .master_rd_data_valid (int_master_rd_data_valid ), + .master_rd_data_type (int_master_rd_data_type ), + .mux_master_cmd_ready (mux_master_cmd_ready ), + .user_interrupt (user_interrupt ), + .hmi_interrupt (hmi_interrupt ), + .idle ( ), + .push_to_error_address_fifo ( ) + ); + +fmiohmc_ecc_mmr # + ( + .CFG_MMR_ADDR_WIDTH (CFG_MMR_ADDR_WIDTH ), + .CFG_MMR_DATA_WIDTH (CFG_MMR_DATA_WIDTH ), + .CFG_MMR_BYTE_ENABLE_WIDTH (CFG_MMR_BYTE_ENABLE_WIDTH ), + .CFG_MMR_BURSTCOUNT_WIDTH (CFG_MMR_BURSTCOUNT_WIDTH ), + .CFG_DRAM_DATA_WIDTH (MMR_DRAM_DATA_WIDTH ), + .CFG_LOCAL_DATA_WIDTH (MMR_LOCAL_DATA_WIDTH ), + .CFG_ADDR_WIDTH (MMR_ADDR_WIDTH ), + .CFG_DATA_RATE (MMR_DATA_RATE ), + .CFG_ECC_IN_PROTOCOL (MMR_ECC_IN_PROTOCOL ), + .CFG_WRPATH_PIPELINE_EN (MMR_WRPATH_PIPELINE_EN ), + .CFG_ENABLE_ECC (MMR_ENABLE_ECC ), + .CFG_ENABLE_DM (MMR_ENABLE_DM ), + .CFG_ENABLE_RMW (MMR_ENABLE_RMW ), + .CFG_ENABLE_AUTO_CORR (MMR_ENABLE_AUTO_CORR ), + .CFG_ECC_CODE_OVERWRITE (MMR_ECC_CODE_OVERWRITE ), + .CFG_GEN_SBE (MMR_GEN_SBE ), + .CFG_GEN_DBE (MMR_GEN_DBE ), + .CFG_ENABLE_INTR (MMR_ENABLE_INTR ), + .CFG_MASK_SBE_INTR (MMR_MASK_SBE_INTR ), + .CFG_MASK_DBE_INTR (MMR_MASK_DBE_INTR ), + .CFG_MASK_CORR_DROPPED_INTR (MMR_MASK_CORR_DROPPED_INTR ), + .CFG_MASK_HMI_INTR (MMR_MASK_HMI_INTR ), + .CFG_CLR_INTR (MMR_CLR_INTR ), + .CFG_CLR_MR_RDATA (MMR_CLR_MR_RDATA ), + .CFG_PORT_WIDTH_DRAM_DATA_WIDTH (CFG_PORT_WIDTH_DRAM_DATA_WIDTH ), + .CFG_PORT_WIDTH_LOCAL_DATA_WIDTH (CFG_PORT_WIDTH_LOCAL_DATA_WIDTH ), + .CFG_PORT_WIDTH_ADDR_WIDTH (CFG_PORT_WIDTH_ADDR_WIDTH ), + .CFG_PORT_WIDTH_DATA_RATE (CFG_PORT_WIDTH_DATA_RATE ), + .CFG_PORT_WIDTH_ECC_IN_PROTOCOL (CFG_PORT_WIDTH_ECC_IN_PROTOCOL ), + .CFG_PORT_WIDTH_WRPATH_PIPELINE_EN (CFG_PORT_WIDTH_WRPATH_PIPELINE_EN ), + .CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ), + .CFG_PORT_WIDTH_ENABLE_DM (CFG_PORT_WIDTH_ENABLE_DM ), + .CFG_PORT_WIDTH_ENABLE_RMW (CFG_PORT_WIDTH_ENABLE_RMW ), + .CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ), + .CFG_PORT_WIDTH_ECC_CODE_OVERWRITE (CFG_PORT_WIDTH_ECC_CODE_OVERWRITE ), + .CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ), + .CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ), + .CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ), + .CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ), + .CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ), + .CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR ), + .CFG_PORT_WIDTH_MASK_HMI_INTR (CFG_PORT_WIDTH_MASK_HMI_INTR ), + .CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ), + .CFG_PORT_WIDTH_CLR_MR_RDATA (CFG_PORT_WIDTH_CLR_MR_RDATA ), + .ECC_MMR_READ_LATENCY (ECC_MMR_READ_LATENCY ), + .STS_PORT_WIDTH_ECC_INTR (STS_PORT_WIDTH_ECC_INTR ), + .STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ), + .STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ), + .STS_PORT_WIDTH_CORR_DROPPED (STS_PORT_WIDTH_CORR_DROPPED ), + .STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ), + .STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ), + .STS_PORT_WIDTH_CORR_DROPPED_COUNT (STS_PORT_WIDTH_CORR_DROPPED_COUNT ), + .STS_PORT_WIDTH_ERR_ADDR (STS_PORT_WIDTH_ERR_ADDR ), + .STS_PORT_WIDTH_CORR_DROPPED_ADDR (STS_PORT_WIDTH_CORR_DROPPED_ADDR ), + .STS_PORT_WIDTH_MR_DATA (STS_PORT_WIDTH_MR_DATA ), + .STS_PORT_WIDTH_MR_DATA_VALID (STS_PORT_WIDTH_MR_DATA_VALID ) + ) +iohmc_ecc_mmr_inst + ( + .ctl_clk (ctl_clk ), + .ctl_reset_n (ctl_reset_n[25] ), + .cfg_dram_data_width (cfg_dram_data_width ), + .cfg_local_data_width (cfg_local_data_width ), + .cfg_addr_width (cfg_addr_width ), + .cfg_data_rate (cfg_data_rate ), + .cfg_ecc_in_protocol (cfg_ecc_in_protocol ), + .cfg_wrpath_pipeline_en (cfg_wrpath_pipeline_en ), + .cfg_enable_ecc (cfg_enable_ecc ), + .cfg_enable_dm (cfg_enable_dm ), + .cfg_enable_rmw (cfg_enable_rmw ), + .cfg_enable_auto_corr (cfg_enable_auto_corr ), + .cfg_ecc_code_overwrite (cfg_ecc_code_overwrite ), + .cfg_gen_sbe (cfg_gen_sbe ), + .cfg_gen_dbe (cfg_gen_dbe ), + .cfg_enable_intr (cfg_enable_intr ), + .cfg_mask_sbe_intr (cfg_mask_sbe_intr ), + .cfg_mask_dbe_intr (cfg_mask_dbe_intr ), + .cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ), + .cfg_mask_hmi_intr (cfg_mask_hmi_intr ), + .cfg_clr_intr (cfg_clr_intr ), + .cfg_clr_mr_rdata (cfg_clr_mr_rdata ), + .sts_ecc_intr (sts_ecc_intr ), + .sts_sbe_error (sts_sbe_error ), + .sts_dbe_error (sts_dbe_error ), + .sts_corr_dropped (sts_corr_dropped ), + .sts_sbe_count (sts_sbe_count ), + .sts_dbe_count (sts_dbe_count ), + .sts_corr_dropped_count (sts_corr_dropped_count ), + .sts_err_addr (sts_err_addr ), + .sts_corr_dropped_addr (sts_corr_dropped_addr ), + .sts_mr_rdata_0 (sts_mr_rdata_0 ), + .sts_mr_rdata_1 (sts_mr_rdata_1 ), + .sts_mr_rdata_valid (sts_mr_rdata_valid ), + .slave_ready (slave_mmr_ready ), + .slave_address (slave_mmr_address ), + .slave_write (slave_mmr_write ), + .slave_read (slave_mmr_read ), + .slave_burstcount (slave_mmr_burstcount ), + .slave_begintransfer (slave_mmr_begintransfer ), + .slave_wr_data (slave_mmr_wr_data ), + .slave_byte_enable ({CFG_MMR_BYTE_ENABLE_WIDTH{1'b1}} ), + .slave_rd_data (slave_mmr_rd_data ), + .slave_rd_data_valid (slave_mmr_rd_data_valid ), + .master_ready (master_mmr_ready ), + .master_address (master_mmr_address ), + .master_write (master_mmr_write ), + .master_read (master_mmr_read ), + .master_burstcount (master_mmr_burstcount ), + .master_begintransfer (master_mmr_begintransfer ), + .master_wr_data (master_mmr_wr_data ), + .master_byte_enable ( ), + .master_rd_data (master_mmr_rd_data ), + .master_rd_data_valid (master_mmr_rd_data_valid ) + ); + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EAZQO90Dgd3nOG9fz0cZkTU/GwE4wVUkuFaV7A9pMioWVcKxYeem7Kcqtc06fudP6NbZe2IwH31SXPkNsqeSigvGVzTswSNsC4uM4HA/+WdW8tImjaW+juss32WEaDcClstCUamM5jZSOHuSKQMoOXRKtTyCM04ijGqdSj9/c4WuK62TdxiVtCsMpQPMfKBt6w5HIUgiw/45AVlX+Axx/JapLZgvS1P98v4FXC5aCr6WpPQu+5UJ+GwEKUsR0bLK+7L+uFMs902Xt2xLgMI4nsIsXj8A/1hwJmzGaCxqc001L5WWVHcyDJAMDMYaIJ2SoR3ZpPA1mIEe4x1t7kaAMsnjEb3IPcm1tC9eoo30iz8p1ZrwRgbbKUgO9RW0/R2tMRX7YmwR830bT2qTF8GnSdURFDcri5gwjFcfTHU3strIdfQ0scFoxIdtt0Jjuc3GYyq76855NGls2SysVvZ8UedXJ/S+em+xD4ohSQr7sG4omSg6cM0Zg1m9ONsuXzy6KW10hAaMYZoYp4heTHUcRh+0+XFjpuANa6bP5vUhUvv3vDvASJwpl7BoUb83uggBsf7qzYFALRmfY2PonCmgSPzxUXFIAL7J7hJ4UDqiwDwTXORiQVv77Qs8D0NW8HdSrVgqH2UJYlq8B3TNNqWkG55kOFEgtgrnfBz4fxUWENBJYrqqAlLWztraLos9kruMskrCkl64O85dYPnJDkTBJtHclGvVI3PG94SUWE9kBWEEdzAlOrLPDqnk0WAI7S8O3OVDi3NBnPP9liL7+PdnqVg" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_fifo.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_fifo.v new file mode 100644 index 0000000000..6d61a54d68 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_ecc_fm_191/synth/fmiohmc_fifo.v @@ -0,0 +1,167 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module fmiohmc_fifo # + ( parameter + CFG_ADDR_WIDTH = 10, + CFG_DATA_WIDTH = 32, + CFG_REGISTERED_OUTPUT = 0, + CFG_SHOWAHEAD = 0, + CFG_USE_EAB = "ON", + CFG_REGISTERED_INPUT = 0 + ) + ( + ctl_clk, + ctl_reset_n, + write_request, + write_data, + read_request, + read_data, + read_data_valid, + fifo_empty, + fifo_full + ); + +localparam CFG_REGISTERED_INPUT_STAGES = (CFG_REGISTERED_INPUT == 0) ? 1 : CFG_REGISTERED_INPUT; +localparam ENTRIES_COUNTER_WIDTH = CFG_ADDR_WIDTH + 1; +localparam SCFIFO_DEPTH = 2 ** CFG_ADDR_WIDTH; +localparam SCFIFO_REGISTERED_OUTPUT = CFG_REGISTERED_OUTPUT ? "ON" : "OFF"; +localparam SCFIFO_SHOWAHEAD = CFG_SHOWAHEAD ? "ON" : "OFF"; + +input ctl_clk; +input ctl_reset_n; + +input write_request; +input [CFG_DATA_WIDTH - 1 : 0] write_data; + +input read_request; +output [CFG_DATA_WIDTH - 1 : 0] read_data; +output read_data_valid; + +output fifo_empty; +output fifo_full; + + wire [CFG_DATA_WIDTH - 1 : 0] read_data; + wire read_data_valid; + wire direct_fifo_empty; + wire fifo_empty; + wire fifo_full; + + +wire int_write_request; +wire [CFG_DATA_WIDTH - 1 : 0] int_write_data; + +generate + genvar stage; + + if (CFG_REGISTERED_INPUT == 0) begin: input_no_pipe + assign int_write_request = write_request; + assign int_write_data = write_data; + end + else begin : input_pipe + reg write_request_pipe [CFG_REGISTERED_INPUT_STAGES - 1 : 0]; + reg [CFG_DATA_WIDTH - 1 : 0] write_data_pipe [CFG_REGISTERED_INPUT_STAGES - 1 : 0]; + + assign int_write_request = write_request_pipe [CFG_REGISTERED_INPUT_STAGES - 1]; + assign int_write_data = write_data_pipe [CFG_REGISTERED_INPUT_STAGES - 1]; + + for (stage = 0; stage < CFG_REGISTERED_INPUT_STAGES; stage = stage + 1) + begin : stage_gen + always @(posedge ctl_clk) begin + write_request_pipe[stage] <= (stage == 0) ? write_request : write_request_pipe[stage-1]; + write_data_pipe [stage] <= (stage == 0) ? write_data : write_data_pipe [stage-1]; + end + end + end +endgenerate + + scfifo # + ( + .add_ram_output_register (SCFIFO_REGISTERED_OUTPUT ), + .enable_ecc ("FALSE" ), + .intended_device_family ("Stratix 10" ), + .lpm_numwords (SCFIFO_DEPTH ), + .lpm_showahead (SCFIFO_SHOWAHEAD ), + .lpm_type ("scfifo" ), + .lpm_width (CFG_DATA_WIDTH ), + .lpm_widthu (CFG_ADDR_WIDTH ), + .overflow_checking ("OFF" ), + .underflow_checking ("OFF" ), + .use_eab (CFG_USE_EAB ) + ) + scfifo_inst + ( + .aclr ( 1'b0 ), + .clock ( ctl_clk ), + .data ( int_write_data ), + .rdreq ( read_request ), + .wrreq ( int_write_request ), + .empty ( direct_fifo_empty ), + .full ( fifo_full ), + .q ( read_data ), + .almost_empty ( ), + .almost_full ( ), + .sclr ( ~ctl_reset_n ), + .usedw ( ) + ); + +generate + if (CFG_USE_EAB == "ON" && CFG_SHOWAHEAD != 0 && CFG_REGISTERED_OUTPUT != 0) begin : ext_empty_tracker + + reg pipe_wrreq_r /* synthesis preserve_syn_only = 1 */; + reg pipe_wrreq_rr /* synthesis preserve_syn_only = 1 */; + always @ (posedge ctl_clk) + begin + pipe_wrreq_r <= int_write_request; + pipe_wrreq_rr <= pipe_wrreq_r; + end + + reg [ENTRIES_COUNTER_WIDTH - 1 : 0] counter; + reg counter_is_zero; + reg counter_is_one; + + always @ (posedge ctl_clk) + begin + if (~ctl_reset_n) begin + counter <= {ENTRIES_COUNTER_WIDTH{1'b0}}; + counter_is_zero <= 1'b1; + counter_is_one <= 1'b0; + end else begin + if (pipe_wrreq_rr && ~read_request) begin + counter <= counter + 1'b1; + counter_is_zero <= 1'b0; + counter_is_one <= counter_is_zero; + end else if (~pipe_wrreq_rr && read_request) begin + counter <= counter - 1'b1; + counter_is_zero <= counter_is_one; + counter_is_one <= (counter == 2); + end + end + end + + assign fifo_empty = counter_is_zero; + assign read_data_valid = ~counter_is_zero; + end + else begin : use_scfifo_empty_tracker + assign fifo_empty = direct_fifo_empty; + assign read_data_valid = ~direct_fifo_empty; + end +endgenerate + + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EDOk9aHkqOWcF03Flz/QBMSreEuyWo4K6eyOsLyEFYN9On3eZk+elXPo7iY6i+PydkAYxVQfMayJZYIUU2CpWci6DeG5yvciiioyBM9C9TnfFLC35rbm/VIDkBNnR1HQE3A8qOYRXzX7DUX34pdVdNLZf/DYC82NZAuXBEYN0Tn1suTbo7kLNekmusWQQybRj8DarEH32vjE5ieLX7A1ImqW/UNVrjtKEWLBBA+v8CNFOSPeqLJ2J3keLErHE+4i9gAUOotRGIUZSCaHr3hvJowKMQjRFRaVYQBIYFg2QNqMUvB7xXD5D2IBGbggGU52F0AmaOtMX4wJjyZ744NmipE07D7XxvQyrtQ+1kaz0rTl6cDhKf8oFNu23cml5XDbha7Mmd1L2IdARpK5QJbwVDMVLEeb1fAVlPGbovTgwQwPZBeLLoSh32My/TM8GyRgEjWFSH6x4lqqBsG4QyOT3uSZJCy+88a+dbKDm7PMl46Vl7Hx2A5ZImDeYUsM7FmhARCDE76XVnmFD3sFz5wEJxNlix4ubvLd9ske6oYWmAuPnEXPYU9rssBwacS5uQ+4Ke/2e77aLfoNO1Zk9HmuJT/KTswqDbKQZosbw0Vqbo7fTkST2qOrlDM89ZQeA1znKsbV8y+mLy0cDWqj08IfCprwpuD7YTVe1HnIFeEJ4mazaE5bmrraHRmjypEtZXry4jTKEo9mWk/AJ7sFJwCVm//DgvNjNaJCZ0RLcSEjg7b8Ty1PQ1kvSGQ6m7dau//yso84+Q3HU01eiPQdbdPCVJi" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_fm_274/synth/ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_fm_274/synth/ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq.v new file mode 100644 index 0000000000..e4e69d03e2 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/altera_emif_fm_274/synth/ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq.v @@ -0,0 +1,2149 @@ +// ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq.v + +// This file was auto-generated from altera_emif_fm_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq ( + input wire local_reset_req, // local_reset_req.local_reset_req, Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. + output wire local_reset_done, // local_reset_status.local_reset_done, Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. + input wire pll_ref_clk, // pll_ref_clk.clk, PLL reference clock input + output wire pll_locked, // pll_locked.pll_locked, PLL lock signal to indicate whether the PLL has locked + input wire oct_rzqin, // oct.oct_rzqin, Calibrated On-Chip Termination (OCT) RZQ input pin + output wire [0:0] mem_ck, // mem.mem_ck, CK clock + output wire [0:0] mem_ck_n, // .mem_ck_n, CK clock (negative leg) + output wire [16:0] mem_a, // .mem_a, Address + output wire [0:0] mem_act_n, // .mem_act_n, Activation command + output wire [1:0] mem_ba, // .mem_ba, Bank address + output wire [1:0] mem_bg, // .mem_bg, Bank group + output wire [0:0] mem_cke, // .mem_cke, Clock enable + output wire [0:0] mem_cs_n, // .mem_cs_n, Chip select + output wire [0:0] mem_odt, // .mem_odt, On-die termination + output wire [0:0] mem_reset_n, // .mem_reset_n, Asynchronous reset + output wire [0:0] mem_par, // .mem_par, Command and address parity + input wire [0:0] mem_alert_n, // .mem_alert_n, Alert flag + inout wire [8:0] mem_dqs, // .mem_dqs, Data strobe + inout wire [8:0] mem_dqs_n, // .mem_dqs_n, Data strobe (negative leg) + inout wire [71:0] mem_dq, // .mem_dq, Read/write data + inout wire [8:0] mem_dbi_n, // .mem_dbi_n, Acts as either the data bus inversion pin, or the data mask pin, depending on configuration. + output wire local_cal_success, // status.local_cal_success, When high, indicates that PHY calibration was successful + output wire local_cal_fail, // .local_cal_fail, When high, indicates that PHY calibration failed + input wire calbus_read, // emif_calbus.calbus_read, EMIF Calibration component bus for read + input wire calbus_write, // .calbus_write, EMIF Calibration component bus for write + input wire [19:0] calbus_address, // .calbus_address, EMIF Calibration component bus for address + input wire [31:0] calbus_wdata, // .calbus_wdata, EMIF Calibration component bus for write data + output wire [31:0] calbus_rdata, // .calbus_rdata, EMIF Calibration component bus for read data + output wire [4095:0] calbus_seq_param_tbl, // .calbus_seq_param_tbl, EMIF Calibration component bus for parameter table data + input wire calbus_clk, // emif_calbus_clk.clk, EMIF Calibration component bus for the clock + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n, Reset for the user clock domain. Asynchronous assertion and synchronous deassertion + output wire emif_usr_clk, // emif_usr_clk.clk, User clock domain + output wire ctrl_ecc_user_interrupt_0, // ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt, Controller ECC user interrupt signal to determine whether there is a bit error + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n, Wait-request is asserted when controller is busy + input wire amm_read_0, // .read, Read request signal + input wire amm_write_0, // .write, Write request signal + input wire [26:0] amm_address_0, // .address, Address for the read/write request + output wire [511:0] amm_readdata_0, // .readdata, Read data + input wire [511:0] amm_writedata_0, // .writedata, Write data + input wire [6:0] amm_burstcount_0, // .burstcount, Number of transfers in each read/write burst + input wire [63:0] amm_byteenable_0, // .byteenable, Byte-enable for write data + output wire amm_readdatavalid_0 // .readdatavalid, Indicates whether read data is valid + ); + + wire arch_emif_usr_clk_clk; // arch:emif_usr_clk -> ecc_core:emif_usr_clk_in + wire arch_emif_usr_reset_n_reset; // arch:emif_usr_reset_n -> ecc_core:emif_usr_reset_n_in + wire [12:0] arch_ctrl_ecc_0_ctrl_ecc_rdata_id; // arch:ctrl_ecc_rdata_id_0 -> ecc_core:ctrl_ecc_rdata_id_0 + wire [2:0] arch_ctrl_ecc_0_ctrl_ecc_read_info; // arch:ctrl_ecc_read_info_0 -> ecc_core:ctrl_ecc_read_info_0 + wire [14:0] ecc_core_ctrl_ecc_0_ctrl_ecc_write_info; // ecc_core:ctrl_ecc_write_info_0 -> arch:ctrl_ecc_write_info_0 + wire arch_ctrl_ecc_0_ctrl_ecc_idle; // arch:ctrl_ecc_idle_0 -> ecc_core:ctrl_ecc_idle_0 + wire [11:0] arch_ctrl_ecc_0_ctrl_ecc_wr_pointer_info; // arch:ctrl_ecc_wr_pointer_info_0 -> ecc_core:ctrl_ecc_wr_pointer_info_0 + wire [2:0] arch_ctrl_ecc_0_ctrl_ecc_cmd_info; // arch:ctrl_ecc_cmd_info_0 -> ecc_core:ctrl_ecc_cmd_info_0 + wire ecc_core_ctrl_ast_cmd_0_valid; // ecc_core:ast_cmd_valid_0 -> arch:ast_cmd_valid_0 + wire [60:0] ecc_core_ctrl_ast_cmd_0_data; // ecc_core:ast_cmd_data_0 -> arch:ast_cmd_data_0 + wire ecc_core_ctrl_ast_cmd_0_ready; // arch:ast_cmd_ready_0 -> ecc_core:ast_cmd_ready_0 + wire ecc_core_ctrl_ast_wr_0_valid; // ecc_core:ast_wr_valid_0 -> arch:ast_wr_valid_0 + wire [647:0] ecc_core_ctrl_ast_wr_0_data; // ecc_core:ast_wr_data_0 -> arch:ast_wr_data_0 + wire ecc_core_ctrl_ast_wr_0_ready; // arch:ast_wr_ready_0 -> ecc_core:ast_wr_ready_0 + wire arch_ctrl_ast_rd_0_valid; // arch:ast_rd_valid_0 -> ecc_core:ast_rd_valid_0 + wire [575:0] arch_ctrl_ast_rd_0_data; // arch:ast_rd_data_0 -> ecc_core:ast_rd_data_0 + wire arch_ctrl_ast_rd_0_ready; // ecc_core:ast_rd_ready_0 -> arch:ast_rd_ready_0 + + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy #( + .PROTOCOL_ENUM ("PROTOCOL_DDR4"), + .PHY_TARGET_IS_ES (0), + .PHY_TARGET_IS_ES2 (0), + .PHY_TARGET_IS_PRODUCTION (0), + .PHY_CONFIG_ENUM ("CONFIG_PHY_AND_HARD_CTRL"), + .PHY_PING_PONG_EN (0), + .PHY_CORE_CLKS_SHARING_ENUM ("CORE_CLKS_SHARING_DISABLED"), + .PHY_CALIBRATED_OCT (1), + .PHY_AC_CALIBRATED_OCT (1), + .PHY_CK_CALIBRATED_OCT (1), + .PHY_DATA_CALIBRATED_OCT (1), + .PHY_MIMIC_HPS_EMIF (0), + .PLL_NUM_OF_EXTRA_CLKS (0), + .MEM_FORMAT_ENUM ("MEM_FORMAT_RDIMM"), + .MEM_BURST_LENGTH (8), + .MEM_DATA_MASK_EN (1), + .MEM_TTL_DATA_WIDTH (72), + .MEM_TTL_NUM_OF_READ_GROUPS (9), + .MEM_TTL_NUM_OF_WRITE_GROUPS (9), + .DIAG_SIM_REGTEST_MODE (0), + .DIAG_SYNTH_FOR_SIM (0), + .DIAG_SEQ_RESET_AUTO_RELEASE ("avl"), + .DIAG_DB_RESET_AUTO_RELEASE ("avl_release"), + .DIAG_ECLIPSE_DEBUG (0), + .DIAG_USE_ABSTRACT_PHY (0), + .DIAG_SIM_VERBOSE_LEVEL (5), + .DIAG_FAST_SIM (1), + .SILICON_REV ("14nm5"), + .IS_HPS (0), + .USER_CLK_RATIO (4), + .C2P_P2C_CLK_RATIO (4), + .PHY_HMC_CLK_RATIO (2), + .DIAG_ABSTRACT_PHY_WLAT (9), + .DIAG_ABSTRACT_PHY_RLAT (20), + .DIAG_CPA_OUT_1_EN (0), + .DIAG_USE_CPA_LOCK (1), + .DQS_BUS_MODE_ENUM ("DQS_BUS_MODE_X8_X9"), + .AC_PIN_MAP_SCHEME ("use_0_1_2_3_lane"), + .NUM_OF_HMC_PORTS (1), + .HMC_AVL_PROTOCOL_ENUM ("CTRL_AVL_PROTOCOL_ST"), + .HMC_READY_LATENCY (2), + .HMC_CTRL_DIMM_TYPE ("dimm_type_rdimm"), + .SEQ_PT_SYN_CONTENT ("00024c400000000000000201000927c001121708480909010102110902000101051401000904043400000000000000000d00c08100b0000000000000000000005066008000c4070c017000d80000012300001e780000015e00000000000000081c14040c0b0a0908030201001312111000000018000000060000000400020301000000002b2a290012111000161514131a1918172524231b0000272600380b0000000908000000003424140474645444251505846555453516068575564636260086766608030201100b0a0918131211201b1a1928232221302b2a2938333231403b3a3948434241504b4a4958535251605b5a5968636261706b6a6978737271807b7a7988838281008b8a890000087400010001000200280003040000040800000514600006080f0f5560000d40030b003900002000000000000000"), + .SEQ_PT_SIM_CONTENT ("00024c400000000000000201000927c001121708480909010102110902000101051401000904043400000000000000000d20e08100b0000000000000000000005077d58000c4070c017000d80000012300001e780000015e00000000000000081c14040c0b0a0908030201001312111000000018000000060000000400020301000000002b2a290012111000161514131a1918172524231b0000272600380b0000000908000000003424140474645444251505846555453516068575564636260086766608030201100b0a0918131211201b1a1928232221302b2a2938333231403b3a3948434241504b4a4958535251605b5a5968636261706b6a6978737271807b7a7988838281008b8a890000087400010001000200280003040000040800000514600006080f0f5560000d40030b003900002000000000000000"), + .REGISTER_AFI_C2P (1), + .REGISTER_AFI_P2C (1), + .REGISTER_AMM_P2C (1), + .REGISTER_AMM_C2P (1), + .NUM_OF_RTL_TILES (4), + .PRI_RDATA_TILE_INDEX (0), + .PRI_RDATA_LANE_INDEX (0), + .PRI_WDATA_TILE_INDEX (0), + .PRI_WDATA_LANE_INDEX (0), + .PRI_AC_TILE_INDEX (1), + .SEC_RDATA_TILE_INDEX (0), + .SEC_RDATA_LANE_INDEX (0), + .SEC_WDATA_TILE_INDEX (0), + .SEC_WDATA_LANE_INDEX (0), + .SEC_AC_TILE_INDEX (1), + .LANES_USAGE_0 (757373805), + .LANES_USAGE_1 (365), + .LANES_USAGE_2 (0), + .LANES_USAGE_3 (0), + .LANES_USAGE_AUTOGEN_WCNT (4), + .PINS_USAGE_0 (1073217407), + .PINS_USAGE_1 (763355133), + .PINS_USAGE_2 (15699967), + .PINS_USAGE_3 (1040179140), + .PINS_USAGE_4 (1073217407), + .PINS_USAGE_5 (61), + .PINS_USAGE_6 (0), + .PINS_USAGE_7 (0), + .PINS_USAGE_8 (0), + .PINS_USAGE_9 (0), + .PINS_USAGE_10 (0), + .PINS_USAGE_11 (0), + .PINS_USAGE_12 (0), + .PINS_USAGE_AUTOGEN_WCNT (13), + .LANE_PIN_USAGE_0 (20058385), + .LANE_PIN_USAGE_1 (71582788), + .LANE_PIN_USAGE_2 (286266145), + .LANE_PIN_USAGE_3 (209994820), + .LANE_PIN_USAGE_4 (286331137), + .LANE_PIN_USAGE_5 (67422276), + .LANE_PIN_USAGE_6 (71581969), + .LANE_PIN_USAGE_7 (269828353), + .LANE_PIN_USAGE_8 (71582788), + .LANE_PIN_USAGE_9 (69905), + .LANE_PIN_USAGE_10 (67388484), + .LANE_PIN_USAGE_11 (17), + .LANE_PIN_USAGE_12 (285213696), + .LANE_PIN_USAGE_13 (67422276), + .LANE_PIN_USAGE_14 (554766609), + .LANE_PIN_USAGE_15 (71581772), + .LANE_PIN_USAGE_16 (20058385), + .LANE_PIN_USAGE_17 (71582788), + .LANE_PIN_USAGE_18 (286266145), + .LANE_PIN_USAGE_19 (209994820), + .LANE_PIN_USAGE_20 (1118465), + .LANE_PIN_USAGE_21 (0), + .LANE_PIN_USAGE_22 (0), + .LANE_PIN_USAGE_23 (0), + .LANE_PIN_USAGE_24 (0), + .LANE_PIN_USAGE_25 (0), + .LANE_PIN_USAGE_26 (0), + .LANE_PIN_USAGE_27 (0), + .LANE_PIN_USAGE_28 (0), + .LANE_PIN_USAGE_29 (0), + .LANE_PIN_USAGE_30 (0), + .LANE_PIN_USAGE_31 (0), + .LANE_PIN_USAGE_32 (0), + .LANE_PIN_USAGE_33 (0), + .LANE_PIN_USAGE_34 (0), + .LANE_PIN_USAGE_35 (0), + .LANE_PIN_USAGE_36 (0), + .LANE_PIN_USAGE_37 (0), + .LANE_PIN_USAGE_38 (0), + .LANE_PIN_USAGE_39 (0), + .LANE_PIN_USAGE_40 (0), + .LANE_PIN_USAGE_41 (0), + .LANE_PIN_USAGE_42 (0), + .LANE_PIN_USAGE_43 (0), + .LANE_PIN_USAGE_44 (0), + .LANE_PIN_USAGE_45 (0), + .LANE_PIN_USAGE_46 (0), + .LANE_PIN_USAGE_47 (0), + .LANE_PIN_USAGE_48 (0), + .LANE_PIN_USAGE_49 (0), + .LANE_PIN_USAGE_50 (0), + .LANE_PIN_USAGE_51 (0), + .LANE_PIN_USAGE_AUTOGEN_WCNT (52), + .PINS_RATE_0 (0), + .PINS_RATE_1 (561774592), + .PINS_RATE_2 (15699967), + .PINS_RATE_3 (4), + .PINS_RATE_4 (0), + .PINS_RATE_5 (0), + .PINS_RATE_6 (0), + .PINS_RATE_7 (0), + .PINS_RATE_8 (0), + .PINS_RATE_9 (0), + .PINS_RATE_10 (0), + .PINS_RATE_11 (0), + .PINS_RATE_12 (0), + .PINS_RATE_AUTOGEN_WCNT (13), + .DB_PINS_PROC_MODE_0 (275876963), + .DB_PINS_PROC_MODE_1 (103911395), + .DB_PINS_PROC_MODE_2 (275876963), + .DB_PINS_PROC_MODE_3 (103911395), + .DB_PINS_PROC_MODE_4 (275876963), + .DB_PINS_PROC_MODE_5 (103911395), + .DB_PINS_PROC_MODE_6 (275876963), + .DB_PINS_PROC_MODE_7 (103911395), + .DB_PINS_PROC_MODE_8 (1041269793), + .DB_PINS_PROC_MODE_9 (66230241), + .DB_PINS_PROC_MODE_10 (34636833), + .DB_PINS_PROC_MODE_11 (34636833), + .DB_PINS_PROC_MODE_12 (34668543), + .DB_PINS_PROC_MODE_13 (34667553), + .DB_PINS_PROC_MODE_14 (1073741823), + .DB_PINS_PROC_MODE_15 (1073730559), + .DB_PINS_PROC_MODE_16 (275876963), + .DB_PINS_PROC_MODE_17 (103911395), + .DB_PINS_PROC_MODE_18 (275876963), + .DB_PINS_PROC_MODE_19 (103911395), + .DB_PINS_PROC_MODE_20 (275876963), + .DB_PINS_PROC_MODE_21 (103911395), + .DB_PINS_PROC_MODE_22 (275876963), + .DB_PINS_PROC_MODE_23 (103911395), + .DB_PINS_PROC_MODE_24 (275876963), + .DB_PINS_PROC_MODE_25 (103911395), + .DB_PINS_PROC_MODE_26 (1073741823), + .DB_PINS_PROC_MODE_27 (1073741823), + .DB_PINS_PROC_MODE_28 (1073741823), + .DB_PINS_PROC_MODE_29 (1073741823), + .DB_PINS_PROC_MODE_30 (1073741823), + .DB_PINS_PROC_MODE_31 (1073741823), + .DB_PINS_PROC_MODE_32 (0), + .DB_PINS_PROC_MODE_33 (0), + .DB_PINS_PROC_MODE_34 (0), + .DB_PINS_PROC_MODE_35 (0), + .DB_PINS_PROC_MODE_36 (0), + .DB_PINS_PROC_MODE_37 (0), + .DB_PINS_PROC_MODE_38 (0), + .DB_PINS_PROC_MODE_39 (0), + .DB_PINS_PROC_MODE_40 (0), + .DB_PINS_PROC_MODE_41 (0), + .DB_PINS_PROC_MODE_42 (0), + .DB_PINS_PROC_MODE_43 (0), + .DB_PINS_PROC_MODE_44 (0), + .DB_PINS_PROC_MODE_45 (0), + .DB_PINS_PROC_MODE_46 (0), + .DB_PINS_PROC_MODE_47 (0), + .DB_PINS_PROC_MODE_48 (0), + .DB_PINS_PROC_MODE_49 (0), + .DB_PINS_PROC_MODE_50 (0), + .DB_PINS_PROC_MODE_51 (0), + .DB_PINS_PROC_MODE_52 (0), + .DB_PINS_PROC_MODE_53 (0), + .DB_PINS_PROC_MODE_54 (0), + .DB_PINS_PROC_MODE_55 (0), + .DB_PINS_PROC_MODE_56 (0), + .DB_PINS_PROC_MODE_57 (0), + .DB_PINS_PROC_MODE_58 (0), + .DB_PINS_PROC_MODE_59 (0), + .DB_PINS_PROC_MODE_60 (0), + .DB_PINS_PROC_MODE_61 (0), + .DB_PINS_PROC_MODE_62 (0), + .DB_PINS_PROC_MODE_63 (0), + .DB_PINS_PROC_MODE_AUTOGEN_WCNT (64), + .PINS_DATA_IN_MODE_0 (151515721), + .PINS_DATA_IN_MODE_1 (33329737), + .PINS_DATA_IN_MODE_2 (1059361353), + .PINS_DATA_IN_MODE_3 (153391681), + .PINS_DATA_IN_MODE_4 (153391231), + .PINS_DATA_IN_MODE_5 (150736969), + .PINS_DATA_IN_MODE_6 (153391689), + .PINS_DATA_IN_MODE_7 (153387017), + .PINS_DATA_IN_MODE_8 (584), + .PINS_DATA_IN_MODE_9 (153354304), + .PINS_DATA_IN_MODE_10 (153391231), + .PINS_DATA_IN_MODE_11 (153362377), + .PINS_DATA_IN_MODE_12 (151515721), + .PINS_DATA_IN_MODE_13 (33329737), + .PINS_DATA_IN_MODE_14 (1059361353), + .PINS_DATA_IN_MODE_15 (37441), + .PINS_DATA_IN_MODE_16 (0), + .PINS_DATA_IN_MODE_17 (0), + .PINS_DATA_IN_MODE_18 (0), + .PINS_DATA_IN_MODE_19 (0), + .PINS_DATA_IN_MODE_20 (0), + .PINS_DATA_IN_MODE_21 (0), + .PINS_DATA_IN_MODE_22 (0), + .PINS_DATA_IN_MODE_23 (0), + .PINS_DATA_IN_MODE_24 (0), + .PINS_DATA_IN_MODE_25 (0), + .PINS_DATA_IN_MODE_26 (0), + .PINS_DATA_IN_MODE_27 (0), + .PINS_DATA_IN_MODE_28 (0), + .PINS_DATA_IN_MODE_29 (0), + .PINS_DATA_IN_MODE_30 (0), + .PINS_DATA_IN_MODE_31 (0), + .PINS_DATA_IN_MODE_32 (0), + .PINS_DATA_IN_MODE_33 (0), + .PINS_DATA_IN_MODE_34 (0), + .PINS_DATA_IN_MODE_35 (0), + .PINS_DATA_IN_MODE_36 (0), + .PINS_DATA_IN_MODE_37 (0), + .PINS_DATA_IN_MODE_38 (0), + .PINS_DATA_IN_MODE_AUTOGEN_WCNT (39), + .PINS_C2L_DRIVEN_0 (267714383), + .PINS_C2L_DRIVEN_1 (250877), + .PINS_C2L_DRIVEN_2 (0), + .PINS_C2L_DRIVEN_3 (1027593152), + .PINS_C2L_DRIVEN_4 (267714383), + .PINS_C2L_DRIVEN_5 (61), + .PINS_C2L_DRIVEN_6 (0), + .PINS_C2L_DRIVEN_7 (0), + .PINS_C2L_DRIVEN_8 (0), + .PINS_C2L_DRIVEN_9 (0), + .PINS_C2L_DRIVEN_10 (0), + .PINS_C2L_DRIVEN_11 (0), + .PINS_C2L_DRIVEN_12 (0), + .PINS_C2L_DRIVEN_AUTOGEN_WCNT (13), + .PINS_OCT_MODE_0 (1073217407), + .PINS_OCT_MODE_1 (253949), + .PINS_OCT_MODE_2 (0), + .PINS_OCT_MODE_3 (1040179136), + .PINS_OCT_MODE_4 (1073217407), + .PINS_OCT_MODE_5 (61), + .PINS_OCT_MODE_6 (0), + .PINS_OCT_MODE_7 (0), + .PINS_OCT_MODE_8 (0), + .PINS_OCT_MODE_9 (0), + .PINS_OCT_MODE_10 (0), + .PINS_OCT_MODE_11 (0), + .PINS_OCT_MODE_12 (0), + .PINS_OCT_MODE_AUTOGEN_WCNT (13), + .PINS_DCC_SPLIT_0 (805503024), + .PINS_DCC_SPLIT_1 (201329664), + .PINS_DCC_SPLIT_2 (0), + .PINS_DCC_SPLIT_3 (12585984), + .PINS_DCC_SPLIT_4 (805503024), + .PINS_DCC_SPLIT_5 (0), + .PINS_DCC_SPLIT_6 (0), + .PINS_DCC_SPLIT_7 (0), + .PINS_DCC_SPLIT_8 (0), + .PINS_DCC_SPLIT_9 (0), + .PINS_DCC_SPLIT_10 (0), + .PINS_DCC_SPLIT_11 (0), + .PINS_DCC_SPLIT_12 (0), + .PINS_DCC_SPLIT_AUTOGEN_WCNT (13), + .UNUSED_MEM_PINS_PINLOC_0 (199425087), + .UNUSED_MEM_PINS_PINLOC_1 (196276413), + .UNUSED_MEM_PINS_PINLOC_2 (193127610), + .UNUSED_MEM_PINS_PINLOC_3 (189978807), + .UNUSED_MEM_PINS_PINLOC_4 (186830004), + .UNUSED_MEM_PINS_PINLOC_5 (183681201), + .UNUSED_MEM_PINS_PINLOC_6 (180532398), + .UNUSED_MEM_PINS_PINLOC_7 (177383595), + .UNUSED_MEM_PINS_PINLOC_8 (174234792), + .UNUSED_MEM_PINS_PINLOC_9 (171085989), + .UNUSED_MEM_PINS_PINLOC_10 (167937186), + .UNUSED_MEM_PINS_PINLOC_11 (164788383), + .UNUSED_MEM_PINS_PINLOC_12 (145906844), + .UNUSED_MEM_PINS_PINLOC_13 (108121215), + .UNUSED_MEM_PINS_PINLOC_14 (97613919), + .UNUSED_MEM_PINS_PINLOC_15 (93415515), + .UNUSED_MEM_PINS_PINLOC_16 (90266712), + .UNUSED_MEM_PINS_PINLOC_17 (83972181), + .UNUSED_MEM_PINS_PINLOC_18 (75572298), + .UNUSED_MEM_PINS_PINLOC_19 (55630906), + .UNUSED_MEM_PINS_PINLOC_20 (19954731), + .UNUSED_MEM_PINS_PINLOC_21 (7), + .UNUSED_MEM_PINS_PINLOC_22 (0), + .UNUSED_MEM_PINS_PINLOC_23 (0), + .UNUSED_MEM_PINS_PINLOC_24 (0), + .UNUSED_MEM_PINS_PINLOC_25 (0), + .UNUSED_MEM_PINS_PINLOC_26 (0), + .UNUSED_MEM_PINS_PINLOC_27 (0), + .UNUSED_MEM_PINS_PINLOC_28 (0), + .UNUSED_MEM_PINS_PINLOC_29 (0), + .UNUSED_MEM_PINS_PINLOC_30 (0), + .UNUSED_MEM_PINS_PINLOC_31 (0), + .UNUSED_MEM_PINS_PINLOC_32 (0), + .UNUSED_MEM_PINS_PINLOC_33 (0), + .UNUSED_MEM_PINS_PINLOC_34 (0), + .UNUSED_MEM_PINS_PINLOC_35 (0), + .UNUSED_MEM_PINS_PINLOC_36 (0), + .UNUSED_MEM_PINS_PINLOC_37 (0), + .UNUSED_MEM_PINS_PINLOC_38 (0), + .UNUSED_MEM_PINS_PINLOC_39 (0), + .UNUSED_MEM_PINS_PINLOC_40 (0), + .UNUSED_MEM_PINS_PINLOC_41 (0), + .UNUSED_MEM_PINS_PINLOC_42 (0), + .UNUSED_MEM_PINS_PINLOC_43 (0), + .UNUSED_MEM_PINS_PINLOC_44 (0), + .UNUSED_MEM_PINS_PINLOC_45 (0), + .UNUSED_MEM_PINS_PINLOC_46 (0), + .UNUSED_MEM_PINS_PINLOC_47 (0), + .UNUSED_MEM_PINS_PINLOC_48 (0), + .UNUSED_MEM_PINS_PINLOC_49 (0), + .UNUSED_MEM_PINS_PINLOC_50 (0), + .UNUSED_MEM_PINS_PINLOC_51 (0), + .UNUSED_MEM_PINS_PINLOC_52 (0), + .UNUSED_MEM_PINS_PINLOC_53 (0), + .UNUSED_MEM_PINS_PINLOC_54 (0), + .UNUSED_MEM_PINS_PINLOC_55 (0), + .UNUSED_MEM_PINS_PINLOC_56 (0), + .UNUSED_MEM_PINS_PINLOC_57 (0), + .UNUSED_MEM_PINS_PINLOC_58 (0), + .UNUSED_MEM_PINS_PINLOC_59 (0), + .UNUSED_MEM_PINS_PINLOC_60 (0), + .UNUSED_MEM_PINS_PINLOC_61 (0), + .UNUSED_MEM_PINS_PINLOC_62 (0), + .UNUSED_MEM_PINS_PINLOC_63 (0), + .UNUSED_MEM_PINS_PINLOC_64 (0), + .UNUSED_MEM_PINS_PINLOC_65 (0), + .UNUSED_MEM_PINS_PINLOC_66 (0), + .UNUSED_MEM_PINS_PINLOC_67 (0), + .UNUSED_MEM_PINS_PINLOC_68 (0), + .UNUSED_MEM_PINS_PINLOC_69 (0), + .UNUSED_MEM_PINS_PINLOC_70 (0), + .UNUSED_MEM_PINS_PINLOC_71 (0), + .UNUSED_MEM_PINS_PINLOC_72 (0), + .UNUSED_MEM_PINS_PINLOC_73 (0), + .UNUSED_MEM_PINS_PINLOC_74 (0), + .UNUSED_MEM_PINS_PINLOC_75 (0), + .UNUSED_MEM_PINS_PINLOC_76 (0), + .UNUSED_MEM_PINS_PINLOC_77 (0), + .UNUSED_MEM_PINS_PINLOC_78 (0), + .UNUSED_MEM_PINS_PINLOC_79 (0), + .UNUSED_MEM_PINS_PINLOC_80 (0), + .UNUSED_MEM_PINS_PINLOC_81 (0), + .UNUSED_MEM_PINS_PINLOC_82 (0), + .UNUSED_MEM_PINS_PINLOC_83 (0), + .UNUSED_MEM_PINS_PINLOC_84 (0), + .UNUSED_MEM_PINS_PINLOC_85 (0), + .UNUSED_MEM_PINS_PINLOC_86 (0), + .UNUSED_MEM_PINS_PINLOC_87 (0), + .UNUSED_MEM_PINS_PINLOC_88 (0), + .UNUSED_MEM_PINS_PINLOC_89 (0), + .UNUSED_MEM_PINS_PINLOC_90 (0), + .UNUSED_MEM_PINS_PINLOC_91 (0), + .UNUSED_MEM_PINS_PINLOC_92 (0), + .UNUSED_MEM_PINS_PINLOC_93 (0), + .UNUSED_MEM_PINS_PINLOC_94 (0), + .UNUSED_MEM_PINS_PINLOC_95 (0), + .UNUSED_MEM_PINS_PINLOC_96 (0), + .UNUSED_MEM_PINS_PINLOC_97 (0), + .UNUSED_MEM_PINS_PINLOC_98 (0), + .UNUSED_MEM_PINS_PINLOC_99 (0), + .UNUSED_MEM_PINS_PINLOC_100 (0), + .UNUSED_MEM_PINS_PINLOC_101 (0), + .UNUSED_MEM_PINS_PINLOC_102 (0), + .UNUSED_MEM_PINS_PINLOC_103 (0), + .UNUSED_MEM_PINS_PINLOC_104 (0), + .UNUSED_MEM_PINS_PINLOC_105 (0), + .UNUSED_MEM_PINS_PINLOC_106 (0), + .UNUSED_MEM_PINS_PINLOC_107 (0), + .UNUSED_MEM_PINS_PINLOC_108 (0), + .UNUSED_MEM_PINS_PINLOC_109 (0), + .UNUSED_MEM_PINS_PINLOC_110 (0), + .UNUSED_MEM_PINS_PINLOC_111 (0), + .UNUSED_MEM_PINS_PINLOC_112 (0), + .UNUSED_MEM_PINS_PINLOC_113 (0), + .UNUSED_MEM_PINS_PINLOC_114 (0), + .UNUSED_MEM_PINS_PINLOC_115 (0), + .UNUSED_MEM_PINS_PINLOC_116 (0), + .UNUSED_MEM_PINS_PINLOC_117 (0), + .UNUSED_MEM_PINS_PINLOC_118 (0), + .UNUSED_MEM_PINS_PINLOC_119 (0), + .UNUSED_MEM_PINS_PINLOC_120 (0), + .UNUSED_MEM_PINS_PINLOC_121 (0), + .UNUSED_MEM_PINS_PINLOC_122 (0), + .UNUSED_MEM_PINS_PINLOC_123 (0), + .UNUSED_MEM_PINS_PINLOC_124 (0), + .UNUSED_MEM_PINS_PINLOC_125 (0), + .UNUSED_MEM_PINS_PINLOC_126 (0), + .UNUSED_MEM_PINS_PINLOC_127 (0), + .UNUSED_MEM_PINS_PINLOC_128 (0), + .UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT (129), + .UNUSED_DQS_BUSES_LANELOC_0 (14695431), + .UNUSED_DQS_BUSES_LANELOC_1 (6298637), + .UNUSED_DQS_BUSES_LANELOC_2 (4101), + .UNUSED_DQS_BUSES_LANELOC_3 (0), + .UNUSED_DQS_BUSES_LANELOC_4 (0), + .UNUSED_DQS_BUSES_LANELOC_5 (0), + .UNUSED_DQS_BUSES_LANELOC_6 (0), + .UNUSED_DQS_BUSES_LANELOC_7 (0), + .UNUSED_DQS_BUSES_LANELOC_8 (0), + .UNUSED_DQS_BUSES_LANELOC_9 (0), + .UNUSED_DQS_BUSES_LANELOC_10 (0), + .UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT (11), + .DBC_EXTRA_PIPE_STAGE_EN ("disable"), + .DBC_PIPE_LATS_0 (286335522), + .DBC_PIPE_LATS_1 (821384), + .DBC_PIPE_LATS_2 (0), + .DBC_PIPE_LATS_3 (0), + .DBC_PIPE_LATS_4 (0), + .DBC_PIPE_LATS_AUTOGEN_WCNT (5), + .DB_PTR_PIPELINE_DEPTHS_0 (286331153), + .DB_PTR_PIPELINE_DEPTHS_1 (17476), + .DB_PTR_PIPELINE_DEPTHS_2 (0), + .DB_PTR_PIPELINE_DEPTHS_3 (0), + .DB_PTR_PIPELINE_DEPTHS_4 (0), + .DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT (5), + .DB_SEQ_RD_EN_FULL_PIPELINES_0 (858993459), + .DB_SEQ_RD_EN_FULL_PIPELINES_1 (838860), + .DB_SEQ_RD_EN_FULL_PIPELINES_2 (0), + .DB_SEQ_RD_EN_FULL_PIPELINES_3 (0), + .DB_SEQ_RD_EN_FULL_PIPELINES_4 (0), + .DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT (5), + .CENTER_TIDS_0 (542119940), + .CENTER_TIDS_1 (3), + .CENTER_TIDS_2 (0), + .CENTER_TIDS_AUTOGEN_WCNT (3), + .HMC_TIDS_0 (676600325), + .HMC_TIDS_1 (3), + .HMC_TIDS_2 (0), + .HMC_TIDS_AUTOGEN_WCNT (3), + .LANE_TIDS_0 (403177984), + .LANE_TIDS_1 (168067584), + .LANE_TIDS_2 (35717208), + .LANE_TIDS_3 (140518930), + .LANE_TIDS_4 (886403), + .LANE_TIDS_5 (0), + .LANE_TIDS_6 (0), + .LANE_TIDS_7 (0), + .LANE_TIDS_8 (0), + .LANE_TIDS_9 (0), + .LANE_TIDS_AUTOGEN_WCNT (10), + .PREAMBLE_MODE ("preamble_one_cycle"), + .DBI_WR_ENABLE ("dbi_wr_dis"), + .DBI_RD_ENABLE ("dbi_rd_ena"), + .SWAP_DQS_A_B ("false"), + .DQS_PACK_MODE ("packed"), + .OCT_SIZE (3), + .DQSA_LGC_MODE ("dqs_diff_in_1_a"), + .DQSB_LGC_MODE ("dqs_constant_b"), + .DBC_WB_RESERVED_ENTRY (52), + .DLL_MODE ("dll_ctl_dynamic"), + .DLL_CODEWORD (0), + .ABPHY_WRITE_PROTOCOL (0), + .PHY_USERMODE_OCT (0), + .PHY_PERIODIC_OCT_RECAL (0), + .GENERATE_PHYLITE (0), + .HPRX_CTLE_EN ("on"), + .HPRX_OFFSET_CAL ("true"), + .CPA_FB_MUX_1_SEL ("local_p_clk"), + .ENABLE_RD_TYPE (0), + .AMM_C2P_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .AMM_P2C_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .MMR_C2P_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .MMR_P2C_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .SIDEBAND_C2P_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .SIDEBAND_P2C_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .SEQ_C2P_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .SEQ_P2C_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .ECC_C2P_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .ECC_P2C_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .LANE_C2P_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .LANE_P2C_UFI_MODE ("pin_ufi_use_in_direct_out_direct"), + .AMM_HIPI_DELAY (350), + .MMR_HIPI_DELAY (350), + .SIDEBAND_HIPI_DELAY (350), + .SEQ_HIPI_DELAY (350), + .ECC_HIPI_DELAY (350), + .LANE_HIPI_DELAY (350), + .PRI_HMC_CFG_PING_PONG_MODE ("pingpong_off"), + .PRI_HMC_CFG_CS_ADDR_WIDTH ("cs_width_0"), + .PRI_HMC_CFG_COL_ADDR_WIDTH ("col_width_10"), + .PRI_HMC_CFG_ROW_ADDR_WIDTH ("row_width_16"), + .PRI_HMC_CFG_BANK_ADDR_WIDTH ("bank_width_2"), + .PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH ("bank_group_width_2"), + .PRI_HMC_CFG_ADDR_ORDER ("addr_order_cs_row_ba_col"), + .PRI_HMC_CFG_ARBITER_TYPE ("arbiter_type_2t"), + .PRI_HMC_CFG_OPEN_PAGE_EN ("disable"), + .PRI_HMC_CFG_CTRL_ENABLE_RC ("enable"), + .PRI_HMC_CFG_DBC0_ENABLE_RC ("enable"), + .PRI_HMC_CFG_DBC1_ENABLE_RC ("enable"), + .PRI_HMC_CFG_DBC2_ENABLE_RC ("enable"), + .PRI_HMC_CFG_DBC3_ENABLE_RC ("enable"), + .PRI_HMC_CFG_CTRL_ENABLE_ECC ("enable"), + .PRI_HMC_CFG_DBC0_ENABLE_ECC ("enable"), + .PRI_HMC_CFG_DBC1_ENABLE_ECC ("enable"), + .PRI_HMC_CFG_DBC2_ENABLE_ECC ("enable"), + .PRI_HMC_CFG_DBC3_ENABLE_ECC ("enable"), + .PRI_HMC_CFG_REORDER_DATA ("enable"), + .PRI_HMC_CFG_REORDER_READ ("disable"), + .PRI_HMC_CFG_CTRL_REORDER_RDATA ("disable"), + .PRI_HMC_CFG_DBC0_REORDER_RDATA ("disable"), + .PRI_HMC_CFG_DBC1_REORDER_RDATA ("disable"), + .PRI_HMC_CFG_DBC2_REORDER_RDATA ("disable"), + .PRI_HMC_CFG_DBC3_REORDER_RDATA ("disable"), + .PRI_HMC_CFG_CTRL_SLOT_OFFSET (2), + .PRI_HMC_CFG_DBC0_SLOT_OFFSET (2), + .PRI_HMC_CFG_DBC1_SLOT_OFFSET (2), + .PRI_HMC_CFG_DBC2_SLOT_OFFSET (2), + .PRI_HMC_CFG_DBC3_SLOT_OFFSET (2), + .PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN ("ctrl_disable"), + .PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN ("dbc0_disable"), + .PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN ("dbc1_disable"), + .PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN ("dbc2_disable"), + .PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN ("dbc3_disable"), + .PRI_HMC_CFG_COL_CMD_SLOT (2), + .PRI_HMC_CFG_ROW_CMD_SLOT (1), + .PRI_HMC_CFG_ROW_TO_COL_OFFSET (-1), + .PRI_HMC_CFG_ROW_TO_ROW_OFFSET (0), + .PRI_HMC_CFG_COL_TO_COL_OFFSET (0), + .PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET (0), + .PRI_HMC_CFG_COL_TO_ROW_OFFSET (1), + .PRI_HMC_CFG_SIDEBAND_OFFSET (1), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (33825), + .PRI_HMC_CFG_CTL_ODT_ENABLED (1), + .PRI_HMC_CFG_RD_ODT_ON (4), + .PRI_HMC_CFG_RD_ODT_PERIOD (7), + .PRI_HMC_CFG_READ_ODT_CHIP (0), + .PRI_HMC_CFG_WR_ODT_ON (0), + .PRI_HMC_CFG_WR_ODT_PERIOD (6), + .PRI_HMC_CFG_WRITE_ODT_CHIP (0), + .PRI_HMC_CFG_CMD_FIFO_RESERVE_EN ("enable"), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (8), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (52), + .PRI_HMC_CFG_STARVE_LIMIT (10), + .PRI_HMC_CFG_PHY_DELAY_MISMATCH (0), + .PRI_HMC_CFG_DQSTRK_EN ("disable"), + .PRI_HMC_CFG_DQSTRK_TO_VALID (4), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (26), + .PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN (0), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ("disable"), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (0), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ("disable"), + .PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD (0), + .PRI_HMC_CFG_USER_RFSH_EN ("disable"), + .PRI_HMC_CFG_GEAR_DOWN_EN ("disable"), + .PRI_HMC_CFG_MEM_AUTO_PD_CYCLES (0), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (15), + .PRI_HMC_MEMCLKGATE_SETTING (0), + .PRI_HMC_CFG_TCL (21), + .PRI_HMC_CFG_16_ACT_TO_ACT (0), + .PRI_HMC_CFG_4_ACT_TO_ACT (12), + .PRI_HMC_MEM_IF_AL (0), + .PRI_HMC_MEM_IF_CS_PER_DIMM (0), + .PRI_HMC_MEM_IF_RD_PREAMBLE (0), + .PRI_HMC_MEM_IF_TCCD (0), + .PRI_HMC_MEM_IF_TCCD_S (0), + .PRI_HMC_MEM_IF_TCKESR (0), + .PRI_HMC_MEM_IF_TCKSRX (0), + .PRI_HMC_MEM_IF_TCL (0), + .PRI_HMC_MEM_IF_TCWL (0), + .PRI_HMC_MEM_IF_TDQSCKMAX (0), + .PRI_HMC_MEM_IF_TFAW (0), + .PRI_HMC_MEM_IF_TMOD (0), + .PRI_HMC_MEM_IF_TPL (0), + .PRI_HMC_MEM_IF_TRAS (0), + .PRI_HMC_MEM_IF_TRC (0), + .PRI_HMC_MEM_IF_TRCD (0), + .PRI_HMC_MEM_IF_TREFI (0), + .PRI_HMC_MEM_IF_TRFC (0), + .PRI_HMC_MEM_IF_TRP (0), + .PRI_HMC_MEM_IF_TRRD (0), + .PRI_HMC_MEM_IF_TRRD_S (0), + .PRI_HMC_MEM_IF_TRTP (0), + .PRI_HMC_MEM_IF_TWR (0), + .PRI_HMC_MEM_IF_TWR_CRC_DM (0), + .PRI_HMC_MEM_IF_TWTR (0), + .PRI_HMC_MEM_IF_TWTR_L_CRC_DM (0), + .PRI_HMC_MEM_IF_TWTR_S (0), + .PRI_HMC_MEM_IF_TWTR_S_CRC_DM (0), + .PRI_HMC_MEM_IF_TXP (0), + .PRI_HMC_MEM_IF_TXPDLL (0), + .PRI_HMC_MEM_IF_TXSR (0), + .PRI_HMC_MEM_IF_TZQCS (0), + .PRI_HMC_MEM_IF_TZQOPER (0), + .PRI_HMC_MEM_IF_WR_CRC (0), + .PRI_HMC_MEM_IF_WR_PREAMBLE (0), + .PRI_HMC_CFG_ACT_TO_ACT (28), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (3), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (2), + .PRI_HMC_CFG_ACT_TO_PCH (20), + .PRI_HMC_CFG_ACT_TO_RDWR (8), + .PRI_HMC_CFG_ARF_PERIOD (4681), + .PRI_HMC_CFG_ARF_TO_VALID (211), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (16), + .PRI_HMC_CFG_MPR_TO_VALID (16), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE ("disable"), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (6), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (5), + .PRI_HMC_CFG_MPS_TO_VALID (768), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE ("disable"), + .PRI_HMC_CFG_MRR_TO_VALID (0), + .PRI_HMC_CFG_MRS_TO_VALID (12), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (9), + .PRI_HMC_CFG_PCH_TO_VALID (9), + .PRI_HMC_CFG_PDN_PERIOD (0), + .PRI_HMC_CFG_PDN_TO_VALID (5), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (3), + .PRI_HMC_CFG_RD_AP_TO_VALID (14), + .PRI_HMC_CFG_RD_TO_PCH (5), + .PRI_HMC_CFG_RD_TO_RD (3), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (2), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (4), + .PRI_HMC_CFG_RD_TO_WR (10), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (10), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (10), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (0), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (0), + .PRI_HMC_CFG_SB_CG_DISABLE ("disable"), + .PRI_HMC_CFG_SB_DDR4_MR3 (197632), + .PRI_HMC_CFG_SB_DDR4_MR4 (264192), + .PRI_HMC_CFG_SB_DDR4_MR5 (5216), + .PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR ("disable"), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN ("disable"), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (0), + .PRI_HMC_CFG_SRF_TO_VALID (513), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (385), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE ("disable"), + .PRI_HMC_TEMP_4_ACT_TO_ACT (0), + .PRI_HMC_TEMP_RD_TO_RD_DIFF_BG (0), + .PRI_HMC_TEMP_WR_TO_RD (0), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_BG (0), + .PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP (0), + .PRI_HMC_TEMP_WR_TO_WR_DIFF_BG (0), + .PRI_HMC_CFG_WR_AP_TO_VALID (28), + .PRI_HMC_CFG_WR_TO_PCH (20), + .PRI_HMC_CFG_WR_TO_RD (19), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (17), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (15), + .PRI_HMC_CFG_WR_TO_WR (3), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (2), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (3), + .PRI_HMC_CFG_ZQCL_TO_VALID (257), + .PRI_HMC_CFG_ZQCS_TO_VALID (127), + .PRI_HMC_CHIP_ID (273), + .PRI_HMC_CID_ADDR_WIDTH (0), + .PRI_HMC_3DS_EN ("disable"), + .PRI_HMC_3DS_LR_NUM0 (0), + .PRI_HMC_3DS_LR_NUM1 (0), + .PRI_HMC_3DS_LR_NUM2 (0), + .PRI_HMC_3DS_LR_NUM3 (0), + .PRI_HMC_3DS_PR_STAG_ENABLE ("disable"), + .PRI_HMC_3DS_REF2REF_DLR (1), + .PRI_HMC_3DSREF_ACK_ON_DONE ("disable"), + .PRI_HMC_CFG_MAJOR_MODE_EN ("disable"), + .PRI_HMC_CFG_REFRESH_TYPE (0), + .PRI_HMC_CFG_PRE_REFRESH_EN ("disable"), + .PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (1), + .PRI_HMC_CFG_POST_REFRESH_EN ("enable"), + .PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT (0), + .PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT (2), + .SEC_HMC_CFG_PING_PONG_MODE ("pingpong_off"), + .SEC_HMC_CFG_CS_ADDR_WIDTH ("cs_width_0"), + .SEC_HMC_CFG_COL_ADDR_WIDTH ("col_width_10"), + .SEC_HMC_CFG_ROW_ADDR_WIDTH ("row_width_16"), + .SEC_HMC_CFG_BANK_ADDR_WIDTH ("bank_width_2"), + .SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH ("bank_group_width_2"), + .SEC_HMC_CFG_ADDR_ORDER ("addr_order_cs_row_ba_col"), + .SEC_HMC_CFG_ARBITER_TYPE ("arbiter_type_2t"), + .SEC_HMC_CFG_OPEN_PAGE_EN ("disable"), + .SEC_HMC_CFG_CTRL_ENABLE_RC ("enable"), + .SEC_HMC_CFG_DBC0_ENABLE_RC ("enable"), + .SEC_HMC_CFG_DBC1_ENABLE_RC ("enable"), + .SEC_HMC_CFG_DBC2_ENABLE_RC ("enable"), + .SEC_HMC_CFG_DBC3_ENABLE_RC ("enable"), + .SEC_HMC_CFG_CTRL_ENABLE_ECC ("enable"), + .SEC_HMC_CFG_DBC0_ENABLE_ECC ("enable"), + .SEC_HMC_CFG_DBC1_ENABLE_ECC ("enable"), + .SEC_HMC_CFG_DBC2_ENABLE_ECC ("enable"), + .SEC_HMC_CFG_DBC3_ENABLE_ECC ("enable"), + .SEC_HMC_CFG_REORDER_DATA ("enable"), + .SEC_HMC_CFG_REORDER_READ ("disable"), + .SEC_HMC_CFG_CTRL_REORDER_RDATA ("disable"), + .SEC_HMC_CFG_DBC0_REORDER_RDATA ("disable"), + .SEC_HMC_CFG_DBC1_REORDER_RDATA ("disable"), + .SEC_HMC_CFG_DBC2_REORDER_RDATA ("disable"), + .SEC_HMC_CFG_DBC3_REORDER_RDATA ("disable"), + .SEC_HMC_CFG_CTRL_SLOT_OFFSET (2), + .SEC_HMC_CFG_DBC0_SLOT_OFFSET (2), + .SEC_HMC_CFG_DBC1_SLOT_OFFSET (2), + .SEC_HMC_CFG_DBC2_SLOT_OFFSET (2), + .SEC_HMC_CFG_DBC3_SLOT_OFFSET (2), + .SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN ("ctrl_disable"), + .SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN ("dbc0_disable"), + .SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN ("dbc1_disable"), + .SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN ("dbc2_disable"), + .SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN ("dbc3_disable"), + .SEC_HMC_CFG_COL_CMD_SLOT (2), + .SEC_HMC_CFG_ROW_CMD_SLOT (1), + .SEC_HMC_CFG_ROW_TO_COL_OFFSET (-1), + .SEC_HMC_CFG_ROW_TO_ROW_OFFSET (0), + .SEC_HMC_CFG_COL_TO_COL_OFFSET (0), + .SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET (0), + .SEC_HMC_CFG_COL_TO_ROW_OFFSET (1), + .SEC_HMC_CFG_SIDEBAND_OFFSET (1), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (33825), + .SEC_HMC_CFG_CTL_ODT_ENABLED (1), + .SEC_HMC_CFG_RD_ODT_ON (4), + .SEC_HMC_CFG_RD_ODT_PERIOD (7), + .SEC_HMC_CFG_READ_ODT_CHIP (0), + .SEC_HMC_CFG_WR_ODT_ON (0), + .SEC_HMC_CFG_WR_ODT_PERIOD (6), + .SEC_HMC_CFG_WRITE_ODT_CHIP (0), + .SEC_HMC_CFG_CMD_FIFO_RESERVE_EN ("enable"), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (8), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (52), + .SEC_HMC_CFG_STARVE_LIMIT (10), + .SEC_HMC_CFG_PHY_DELAY_MISMATCH (0), + .SEC_HMC_CFG_DQSTRK_EN ("disable"), + .SEC_HMC_CFG_DQSTRK_TO_VALID (4), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (26), + .SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN (0), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ("disable"), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (0), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ("disable"), + .SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD (0), + .SEC_HMC_CFG_USER_RFSH_EN ("disable"), + .SEC_HMC_CFG_GEAR_DOWN_EN ("disable"), + .SEC_HMC_CFG_MEM_AUTO_PD_CYCLES (0), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (15), + .SEC_HMC_MEMCLKGATE_SETTING (0), + .SEC_HMC_CFG_TCL (21), + .SEC_HMC_CFG_16_ACT_TO_ACT (0), + .SEC_HMC_CFG_4_ACT_TO_ACT (12), + .SEC_HMC_MEM_IF_AL (0), + .SEC_HMC_MEM_IF_CS_PER_DIMM (0), + .SEC_HMC_MEM_IF_RD_PREAMBLE (0), + .SEC_HMC_MEM_IF_TCCD (0), + .SEC_HMC_MEM_IF_TCCD_S (0), + .SEC_HMC_MEM_IF_TCKESR (0), + .SEC_HMC_MEM_IF_TCKSRX (0), + .SEC_HMC_MEM_IF_TCL (0), + .SEC_HMC_MEM_IF_TCWL (0), + .SEC_HMC_MEM_IF_TDQSCKMAX (0), + .SEC_HMC_MEM_IF_TFAW (0), + .SEC_HMC_MEM_IF_TMOD (0), + .SEC_HMC_MEM_IF_TPL (0), + .SEC_HMC_MEM_IF_TRAS (0), + .SEC_HMC_MEM_IF_TRC (0), + .SEC_HMC_MEM_IF_TRCD (0), + .SEC_HMC_MEM_IF_TREFI (0), + .SEC_HMC_MEM_IF_TRFC (0), + .SEC_HMC_MEM_IF_TRP (0), + .SEC_HMC_MEM_IF_TRRD (0), + .SEC_HMC_MEM_IF_TRRD_S (0), + .SEC_HMC_MEM_IF_TRTP (0), + .SEC_HMC_MEM_IF_TWR (0), + .SEC_HMC_MEM_IF_TWR_CRC_DM (0), + .SEC_HMC_MEM_IF_TWTR (0), + .SEC_HMC_MEM_IF_TWTR_L_CRC_DM (0), + .SEC_HMC_MEM_IF_TWTR_S (0), + .SEC_HMC_MEM_IF_TWTR_S_CRC_DM (0), + .SEC_HMC_MEM_IF_TXP (0), + .SEC_HMC_MEM_IF_TXPDLL (0), + .SEC_HMC_MEM_IF_TXSR (0), + .SEC_HMC_MEM_IF_TZQCS (0), + .SEC_HMC_MEM_IF_TZQOPER (0), + .SEC_HMC_MEM_IF_WR_CRC (0), + .SEC_HMC_MEM_IF_WR_PREAMBLE (0), + .SEC_HMC_CFG_ACT_TO_ACT (28), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (3), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (2), + .SEC_HMC_CFG_ACT_TO_PCH (20), + .SEC_HMC_CFG_ACT_TO_RDWR (8), + .SEC_HMC_CFG_ARF_PERIOD (4681), + .SEC_HMC_CFG_ARF_TO_VALID (211), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (16), + .SEC_HMC_CFG_MPR_TO_VALID (16), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE ("disable"), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (6), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (5), + .SEC_HMC_CFG_MPS_TO_VALID (768), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE ("disable"), + .SEC_HMC_CFG_MRR_TO_VALID (0), + .SEC_HMC_CFG_MRS_TO_VALID (12), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (9), + .SEC_HMC_CFG_PCH_TO_VALID (9), + .SEC_HMC_CFG_PDN_PERIOD (0), + .SEC_HMC_CFG_PDN_TO_VALID (5), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (3), + .SEC_HMC_CFG_RD_AP_TO_VALID (14), + .SEC_HMC_CFG_RD_TO_PCH (5), + .SEC_HMC_CFG_RD_TO_RD (3), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (2), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (4), + .SEC_HMC_CFG_RD_TO_WR (10), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (10), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (10), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (0), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (0), + .SEC_HMC_CFG_SB_CG_DISABLE ("disable"), + .SEC_HMC_CFG_SB_DDR4_MR3 (197632), + .SEC_HMC_CFG_SB_DDR4_MR4 (264192), + .SEC_HMC_CFG_SB_DDR4_MR5 (5216), + .SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR ("disable"), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN ("disable"), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (0), + .SEC_HMC_CFG_SRF_TO_VALID (513), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (385), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE ("disable"), + .SEC_HMC_TEMP_4_ACT_TO_ACT (0), + .SEC_HMC_TEMP_RD_TO_RD_DIFF_BG (0), + .SEC_HMC_TEMP_WR_TO_RD (0), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_BG (0), + .SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP (0), + .SEC_HMC_TEMP_WR_TO_WR_DIFF_BG (0), + .SEC_HMC_CFG_WR_AP_TO_VALID (28), + .SEC_HMC_CFG_WR_TO_PCH (20), + .SEC_HMC_CFG_WR_TO_RD (19), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (17), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (15), + .SEC_HMC_CFG_WR_TO_WR (3), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (2), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (3), + .SEC_HMC_CFG_ZQCL_TO_VALID (257), + .SEC_HMC_CFG_ZQCS_TO_VALID (127), + .SEC_HMC_CHIP_ID (273), + .SEC_HMC_CID_ADDR_WIDTH (0), + .SEC_HMC_3DS_EN ("disable"), + .SEC_HMC_3DS_LR_NUM0 (0), + .SEC_HMC_3DS_LR_NUM1 (0), + .SEC_HMC_3DS_LR_NUM2 (0), + .SEC_HMC_3DS_LR_NUM3 (0), + .SEC_HMC_3DS_PR_STAG_ENABLE ("disable"), + .SEC_HMC_3DS_REF2REF_DLR (1), + .SEC_HMC_3DSREF_ACK_ON_DONE ("disable"), + .SEC_HMC_CFG_MAJOR_MODE_EN ("disable"), + .SEC_HMC_CFG_REFRESH_TYPE (0), + .SEC_HMC_CFG_PRE_REFRESH_EN ("disable"), + .SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT (1), + .SEC_HMC_CFG_POST_REFRESH_EN ("enable"), + .SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT (0), + .SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT (2), + .PINS_PER_LANE (12), + .LANES_PER_TILE (4), + .OCT_CONTROL_WIDTH (16), + .PORT_MEM_CK_WIDTH (1), + .PORT_MEM_CK_PINLOC_0 (57345), + .PORT_MEM_CK_PINLOC_1 (0), + .PORT_MEM_CK_PINLOC_2 (0), + .PORT_MEM_CK_PINLOC_3 (0), + .PORT_MEM_CK_PINLOC_4 (0), + .PORT_MEM_CK_PINLOC_5 (0), + .PORT_MEM_CK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CK_N_WIDTH (1), + .PORT_MEM_CK_N_PINLOC_0 (58369), + .PORT_MEM_CK_N_PINLOC_1 (0), + .PORT_MEM_CK_N_PINLOC_2 (0), + .PORT_MEM_CK_N_PINLOC_3 (0), + .PORT_MEM_CK_N_PINLOC_4 (0), + .PORT_MEM_CK_N_PINLOC_5 (0), + .PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CK_BIDIR_WIDTH (1), + .PORT_MEM_CK_BIDIR_PINLOC_0 (0), + .PORT_MEM_CK_BIDIR_PINLOC_1 (0), + .PORT_MEM_CK_BIDIR_PINLOC_2 (0), + .PORT_MEM_CK_BIDIR_PINLOC_3 (0), + .PORT_MEM_CK_BIDIR_PINLOC_4 (0), + .PORT_MEM_CK_BIDIR_PINLOC_5 (0), + .PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CK_BIDIR_N_WIDTH (1), + .PORT_MEM_CK_BIDIR_N_PINLOC_0 (0), + .PORT_MEM_CK_BIDIR_N_PINLOC_1 (0), + .PORT_MEM_CK_BIDIR_N_PINLOC_2 (0), + .PORT_MEM_CK_BIDIR_N_PINLOC_3 (0), + .PORT_MEM_CK_BIDIR_N_PINLOC_4 (0), + .PORT_MEM_CK_BIDIR_N_PINLOC_5 (0), + .PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DK_WIDTH (1), + .PORT_MEM_DK_PINLOC_0 (0), + .PORT_MEM_DK_PINLOC_1 (0), + .PORT_MEM_DK_PINLOC_2 (0), + .PORT_MEM_DK_PINLOC_3 (0), + .PORT_MEM_DK_PINLOC_4 (0), + .PORT_MEM_DK_PINLOC_5 (0), + .PORT_MEM_DK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DK_N_WIDTH (1), + .PORT_MEM_DK_N_PINLOC_0 (0), + .PORT_MEM_DK_N_PINLOC_1 (0), + .PORT_MEM_DK_N_PINLOC_2 (0), + .PORT_MEM_DK_N_PINLOC_3 (0), + .PORT_MEM_DK_N_PINLOC_4 (0), + .PORT_MEM_DK_N_PINLOC_5 (0), + .PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKA_WIDTH (1), + .PORT_MEM_DKA_PINLOC_0 (0), + .PORT_MEM_DKA_PINLOC_1 (0), + .PORT_MEM_DKA_PINLOC_2 (0), + .PORT_MEM_DKA_PINLOC_3 (0), + .PORT_MEM_DKA_PINLOC_4 (0), + .PORT_MEM_DKA_PINLOC_5 (0), + .PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKA_N_WIDTH (1), + .PORT_MEM_DKA_N_PINLOC_0 (0), + .PORT_MEM_DKA_N_PINLOC_1 (0), + .PORT_MEM_DKA_N_PINLOC_2 (0), + .PORT_MEM_DKA_N_PINLOC_3 (0), + .PORT_MEM_DKA_N_PINLOC_4 (0), + .PORT_MEM_DKA_N_PINLOC_5 (0), + .PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKB_WIDTH (1), + .PORT_MEM_DKB_PINLOC_0 (0), + .PORT_MEM_DKB_PINLOC_1 (0), + .PORT_MEM_DKB_PINLOC_2 (0), + .PORT_MEM_DKB_PINLOC_3 (0), + .PORT_MEM_DKB_PINLOC_4 (0), + .PORT_MEM_DKB_PINLOC_5 (0), + .PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKB_N_WIDTH (1), + .PORT_MEM_DKB_N_PINLOC_0 (0), + .PORT_MEM_DKB_N_PINLOC_1 (0), + .PORT_MEM_DKB_N_PINLOC_2 (0), + .PORT_MEM_DKB_N_PINLOC_3 (0), + .PORT_MEM_DKB_N_PINLOC_4 (0), + .PORT_MEM_DKB_N_PINLOC_5 (0), + .PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_K_WIDTH (1), + .PORT_MEM_K_PINLOC_0 (0), + .PORT_MEM_K_PINLOC_1 (0), + .PORT_MEM_K_PINLOC_2 (0), + .PORT_MEM_K_PINLOC_3 (0), + .PORT_MEM_K_PINLOC_4 (0), + .PORT_MEM_K_PINLOC_5 (0), + .PORT_MEM_K_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_K_N_WIDTH (1), + .PORT_MEM_K_N_PINLOC_0 (0), + .PORT_MEM_K_N_PINLOC_1 (0), + .PORT_MEM_K_N_PINLOC_2 (0), + .PORT_MEM_K_N_PINLOC_3 (0), + .PORT_MEM_K_N_PINLOC_4 (0), + .PORT_MEM_K_N_PINLOC_5 (0), + .PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_A_WIDTH (17), + .PORT_MEM_A_PINLOC_0 (64024593), + .PORT_MEM_A_PINLOC_1 (67173438), + .PORT_MEM_A_PINLOC_2 (70322241), + .PORT_MEM_A_PINLOC_3 (73471044), + .PORT_MEM_A_PINLOC_4 (79768647), + .PORT_MEM_A_PINLOC_5 (82917453), + .PORT_MEM_A_PINLOC_6 (0), + .PORT_MEM_A_PINLOC_7 (0), + .PORT_MEM_A_PINLOC_8 (0), + .PORT_MEM_A_PINLOC_9 (0), + .PORT_MEM_A_PINLOC_10 (0), + .PORT_MEM_A_PINLOC_11 (0), + .PORT_MEM_A_PINLOC_12 (0), + .PORT_MEM_A_PINLOC_13 (0), + .PORT_MEM_A_PINLOC_14 (0), + .PORT_MEM_A_PINLOC_15 (0), + .PORT_MEM_A_PINLOC_16 (0), + .PORT_MEM_A_PINLOC_AUTOGEN_WCNT (17), + .PORT_MEM_BA_WIDTH (2), + .PORT_MEM_BA_PINLOC_0 (86066178), + .PORT_MEM_BA_PINLOC_1 (0), + .PORT_MEM_BA_PINLOC_2 (0), + .PORT_MEM_BA_PINLOC_3 (0), + .PORT_MEM_BA_PINLOC_4 (0), + .PORT_MEM_BA_PINLOC_5 (0), + .PORT_MEM_BA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_BG_WIDTH (2), + .PORT_MEM_BG_PINLOC_0 (50416642), + .PORT_MEM_BG_PINLOC_1 (0), + .PORT_MEM_BG_PINLOC_2 (0), + .PORT_MEM_BG_PINLOC_3 (0), + .PORT_MEM_BG_PINLOC_4 (0), + .PORT_MEM_BG_PINLOC_5 (0), + .PORT_MEM_BG_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_C_WIDTH (1), + .PORT_MEM_C_PINLOC_0 (0), + .PORT_MEM_C_PINLOC_1 (0), + .PORT_MEM_C_PINLOC_2 (0), + .PORT_MEM_C_PINLOC_3 (0), + .PORT_MEM_C_PINLOC_4 (0), + .PORT_MEM_C_PINLOC_5 (0), + .PORT_MEM_C_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CKE_WIDTH (1), + .PORT_MEM_CKE_PINLOC_0 (55297), + .PORT_MEM_CKE_PINLOC_1 (0), + .PORT_MEM_CKE_PINLOC_2 (0), + .PORT_MEM_CKE_PINLOC_3 (0), + .PORT_MEM_CKE_PINLOC_4 (0), + .PORT_MEM_CKE_PINLOC_5 (0), + .PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CS_N_WIDTH (1), + .PORT_MEM_CS_N_PINLOC_0 (51201), + .PORT_MEM_CS_N_PINLOC_1 (0), + .PORT_MEM_CS_N_PINLOC_2 (0), + .PORT_MEM_CS_N_PINLOC_3 (0), + .PORT_MEM_CS_N_PINLOC_4 (0), + .PORT_MEM_CS_N_PINLOC_5 (0), + .PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_RM_WIDTH (1), + .PORT_MEM_RM_PINLOC_0 (0), + .PORT_MEM_RM_PINLOC_1 (0), + .PORT_MEM_RM_PINLOC_2 (0), + .PORT_MEM_RM_PINLOC_3 (0), + .PORT_MEM_RM_PINLOC_4 (0), + .PORT_MEM_RM_PINLOC_5 (0), + .PORT_MEM_RM_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_ODT_WIDTH (1), + .PORT_MEM_ODT_PINLOC_0 (53249), + .PORT_MEM_ODT_PINLOC_1 (0), + .PORT_MEM_ODT_PINLOC_2 (0), + .PORT_MEM_ODT_PINLOC_3 (0), + .PORT_MEM_ODT_PINLOC_4 (0), + .PORT_MEM_ODT_PINLOC_5 (0), + .PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_REQ_N_WIDTH (1), + .PORT_MEM_REQ_N_PINLOC_0 (0), + .PORT_MEM_REQ_N_PINLOC_1 (0), + .PORT_MEM_REQ_N_PINLOC_2 (0), + .PORT_MEM_REQ_N_PINLOC_3 (0), + .PORT_MEM_REQ_N_PINLOC_4 (0), + .PORT_MEM_REQ_N_PINLOC_5 (0), + .PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_GNT_N_WIDTH (1), + .PORT_MEM_GNT_N_PINLOC_0 (0), + .PORT_MEM_GNT_N_PINLOC_1 (0), + .PORT_MEM_GNT_N_PINLOC_2 (0), + .PORT_MEM_GNT_N_PINLOC_3 (0), + .PORT_MEM_GNT_N_PINLOC_4 (0), + .PORT_MEM_GNT_N_PINLOC_5 (0), + .PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_ERR_N_WIDTH (1), + .PORT_MEM_ERR_N_PINLOC_0 (0), + .PORT_MEM_ERR_N_PINLOC_1 (0), + .PORT_MEM_ERR_N_PINLOC_2 (0), + .PORT_MEM_ERR_N_PINLOC_3 (0), + .PORT_MEM_ERR_N_PINLOC_4 (0), + .PORT_MEM_ERR_N_PINLOC_5 (0), + .PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_RAS_N_WIDTH (1), + .PORT_MEM_RAS_N_PINLOC_0 (0), + .PORT_MEM_RAS_N_PINLOC_1 (0), + .PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CAS_N_WIDTH (1), + .PORT_MEM_CAS_N_PINLOC_0 (0), + .PORT_MEM_CAS_N_PINLOC_1 (0), + .PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_WE_N_WIDTH (1), + .PORT_MEM_WE_N_PINLOC_0 (0), + .PORT_MEM_WE_N_PINLOC_1 (0), + .PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_RESET_N_WIDTH (1), + .PORT_MEM_RESET_N_PINLOC_0 (50177), + .PORT_MEM_RESET_N_PINLOC_1 (0), + .PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_ACT_N_WIDTH (1), + .PORT_MEM_ACT_N_PINLOC_0 (52225), + .PORT_MEM_ACT_N_PINLOC_1 (0), + .PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_PAR_WIDTH (1), + .PORT_MEM_PAR_PINLOC_0 (60417), + .PORT_MEM_PAR_PINLOC_1 (0), + .PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CA_WIDTH (1), + .PORT_MEM_CA_PINLOC_0 (0), + .PORT_MEM_CA_PINLOC_1 (0), + .PORT_MEM_CA_PINLOC_2 (0), + .PORT_MEM_CA_PINLOC_3 (0), + .PORT_MEM_CA_PINLOC_4 (0), + .PORT_MEM_CA_PINLOC_5 (0), + .PORT_MEM_CA_PINLOC_6 (0), + .PORT_MEM_CA_PINLOC_7 (0), + .PORT_MEM_CA_PINLOC_8 (0), + .PORT_MEM_CA_PINLOC_9 (0), + .PORT_MEM_CA_PINLOC_10 (0), + .PORT_MEM_CA_PINLOC_11 (0), + .PORT_MEM_CA_PINLOC_12 (0), + .PORT_MEM_CA_PINLOC_13 (0), + .PORT_MEM_CA_PINLOC_14 (0), + .PORT_MEM_CA_PINLOC_15 (0), + .PORT_MEM_CA_PINLOC_16 (0), + .PORT_MEM_CA_PINLOC_AUTOGEN_WCNT (17), + .PORT_MEM_REF_N_WIDTH (1), + .PORT_MEM_REF_N_PINLOC_0 (0), + .PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_WPS_N_WIDTH (1), + .PORT_MEM_WPS_N_PINLOC_0 (0), + .PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RPS_N_WIDTH (1), + .PORT_MEM_RPS_N_PINLOC_0 (0), + .PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_DOFF_N_WIDTH (1), + .PORT_MEM_DOFF_N_PINLOC_0 (0), + .PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LDA_N_WIDTH (1), + .PORT_MEM_LDA_N_PINLOC_0 (0), + .PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LDB_N_WIDTH (1), + .PORT_MEM_LDB_N_PINLOC_0 (0), + .PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RWA_N_WIDTH (1), + .PORT_MEM_RWA_N_PINLOC_0 (0), + .PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RWB_N_WIDTH (1), + .PORT_MEM_RWB_N_PINLOC_0 (0), + .PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LBK0_N_WIDTH (1), + .PORT_MEM_LBK0_N_PINLOC_0 (0), + .PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LBK1_N_WIDTH (1), + .PORT_MEM_LBK1_N_PINLOC_0 (0), + .PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_CFG_N_WIDTH (1), + .PORT_MEM_CFG_N_PINLOC_0 (0), + .PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_AP_WIDTH (1), + .PORT_MEM_AP_PINLOC_0 (0), + .PORT_MEM_AP_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_AINV_WIDTH (1), + .PORT_MEM_AINV_PINLOC_0 (0), + .PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_DM_WIDTH (1), + .PORT_MEM_DM_PINLOC_0 (0), + .PORT_MEM_DM_PINLOC_1 (0), + .PORT_MEM_DM_PINLOC_2 (0), + .PORT_MEM_DM_PINLOC_3 (0), + .PORT_MEM_DM_PINLOC_4 (0), + .PORT_MEM_DM_PINLOC_5 (0), + .PORT_MEM_DM_PINLOC_6 (0), + .PORT_MEM_DM_PINLOC_7 (0), + .PORT_MEM_DM_PINLOC_8 (0), + .PORT_MEM_DM_PINLOC_9 (0), + .PORT_MEM_DM_PINLOC_10 (0), + .PORT_MEM_DM_PINLOC_11 (0), + .PORT_MEM_DM_PINLOC_12 (0), + .PORT_MEM_DM_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_BWS_N_WIDTH (1), + .PORT_MEM_BWS_N_PINLOC_0 (0), + .PORT_MEM_BWS_N_PINLOC_1 (0), + .PORT_MEM_BWS_N_PINLOC_2 (0), + .PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_D_WIDTH (1), + .PORT_MEM_D_PINLOC_0 (0), + .PORT_MEM_D_PINLOC_1 (0), + .PORT_MEM_D_PINLOC_2 (0), + .PORT_MEM_D_PINLOC_3 (0), + .PORT_MEM_D_PINLOC_4 (0), + .PORT_MEM_D_PINLOC_5 (0), + .PORT_MEM_D_PINLOC_6 (0), + .PORT_MEM_D_PINLOC_7 (0), + .PORT_MEM_D_PINLOC_8 (0), + .PORT_MEM_D_PINLOC_9 (0), + .PORT_MEM_D_PINLOC_10 (0), + .PORT_MEM_D_PINLOC_11 (0), + .PORT_MEM_D_PINLOC_12 (0), + .PORT_MEM_D_PINLOC_13 (0), + .PORT_MEM_D_PINLOC_14 (0), + .PORT_MEM_D_PINLOC_15 (0), + .PORT_MEM_D_PINLOC_16 (0), + .PORT_MEM_D_PINLOC_17 (0), + .PORT_MEM_D_PINLOC_18 (0), + .PORT_MEM_D_PINLOC_19 (0), + .PORT_MEM_D_PINLOC_20 (0), + .PORT_MEM_D_PINLOC_21 (0), + .PORT_MEM_D_PINLOC_22 (0), + .PORT_MEM_D_PINLOC_23 (0), + .PORT_MEM_D_PINLOC_24 (0), + .PORT_MEM_D_PINLOC_25 (0), + .PORT_MEM_D_PINLOC_26 (0), + .PORT_MEM_D_PINLOC_27 (0), + .PORT_MEM_D_PINLOC_28 (0), + .PORT_MEM_D_PINLOC_29 (0), + .PORT_MEM_D_PINLOC_30 (0), + .PORT_MEM_D_PINLOC_31 (0), + .PORT_MEM_D_PINLOC_32 (0), + .PORT_MEM_D_PINLOC_33 (0), + .PORT_MEM_D_PINLOC_34 (0), + .PORT_MEM_D_PINLOC_35 (0), + .PORT_MEM_D_PINLOC_36 (0), + .PORT_MEM_D_PINLOC_37 (0), + .PORT_MEM_D_PINLOC_38 (0), + .PORT_MEM_D_PINLOC_39 (0), + .PORT_MEM_D_PINLOC_40 (0), + .PORT_MEM_D_PINLOC_41 (0), + .PORT_MEM_D_PINLOC_42 (0), + .PORT_MEM_D_PINLOC_43 (0), + .PORT_MEM_D_PINLOC_44 (0), + .PORT_MEM_D_PINLOC_45 (0), + .PORT_MEM_D_PINLOC_46 (0), + .PORT_MEM_D_PINLOC_47 (0), + .PORT_MEM_D_PINLOC_48 (0), + .PORT_MEM_D_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQ_WIDTH (72), + .PORT_MEM_DQ_PINLOC_0 (1048648), + .PORT_MEM_DQ_PINLOC_1 (8391682), + .PORT_MEM_DQ_PINLOC_2 (11544585), + .PORT_MEM_DQ_PINLOC_3 (14693388), + .PORT_MEM_DQ_PINLOC_4 (22040591), + .PORT_MEM_DQ_PINLOC_5 (25189398), + .PORT_MEM_DQ_PINLOC_6 (28338201), + .PORT_MEM_DQ_PINLOC_7 (35685408), + .PORT_MEM_DQ_PINLOC_8 (38834211), + .PORT_MEM_DQ_PINLOC_9 (46177318), + .PORT_MEM_DQ_PINLOC_10 (49330221), + .PORT_MEM_DQ_PINLOC_11 (102859872), + .PORT_MEM_DQ_PINLOC_12 (110207075), + .PORT_MEM_DQ_PINLOC_13 (113355882), + .PORT_MEM_DQ_PINLOC_14 (116504685), + .PORT_MEM_DQ_PINLOC_15 (123851892), + .PORT_MEM_DQ_PINLOC_16 (127000695), + .PORT_MEM_DQ_PINLOC_17 (134343802), + .PORT_MEM_DQ_PINLOC_18 (137496705), + .PORT_MEM_DQ_PINLOC_19 (140645508), + .PORT_MEM_DQ_PINLOC_20 (147992711), + .PORT_MEM_DQ_PINLOC_21 (151141518), + .PORT_MEM_DQ_PINLOC_22 (154290321), + .PORT_MEM_DQ_PINLOC_23 (161637528), + .PORT_MEM_DQ_PINLOC_24 (155), + .PORT_MEM_DQ_PINLOC_25 (0), + .PORT_MEM_DQ_PINLOC_26 (0), + .PORT_MEM_DQ_PINLOC_27 (0), + .PORT_MEM_DQ_PINLOC_28 (0), + .PORT_MEM_DQ_PINLOC_29 (0), + .PORT_MEM_DQ_PINLOC_30 (0), + .PORT_MEM_DQ_PINLOC_31 (0), + .PORT_MEM_DQ_PINLOC_32 (0), + .PORT_MEM_DQ_PINLOC_33 (0), + .PORT_MEM_DQ_PINLOC_34 (0), + .PORT_MEM_DQ_PINLOC_35 (0), + .PORT_MEM_DQ_PINLOC_36 (0), + .PORT_MEM_DQ_PINLOC_37 (0), + .PORT_MEM_DQ_PINLOC_38 (0), + .PORT_MEM_DQ_PINLOC_39 (0), + .PORT_MEM_DQ_PINLOC_40 (0), + .PORT_MEM_DQ_PINLOC_41 (0), + .PORT_MEM_DQ_PINLOC_42 (0), + .PORT_MEM_DQ_PINLOC_43 (0), + .PORT_MEM_DQ_PINLOC_44 (0), + .PORT_MEM_DQ_PINLOC_45 (0), + .PORT_MEM_DQ_PINLOC_46 (0), + .PORT_MEM_DQ_PINLOC_47 (0), + .PORT_MEM_DQ_PINLOC_48 (0), + .PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DBI_N_WIDTH (9), + .PORT_MEM_DBI_N_PINLOC_0 (18880521), + .PORT_MEM_DBI_N_PINLOC_1 (106997790), + .PORT_MEM_DBI_N_PINLOC_2 (144832626), + .PORT_MEM_DBI_N_PINLOC_3 (150), + .PORT_MEM_DBI_N_PINLOC_4 (0), + .PORT_MEM_DBI_N_PINLOC_5 (0), + .PORT_MEM_DBI_N_PINLOC_6 (0), + .PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT (7), + .PORT_MEM_DQA_WIDTH (1), + .PORT_MEM_DQA_PINLOC_0 (0), + .PORT_MEM_DQA_PINLOC_1 (0), + .PORT_MEM_DQA_PINLOC_2 (0), + .PORT_MEM_DQA_PINLOC_3 (0), + .PORT_MEM_DQA_PINLOC_4 (0), + .PORT_MEM_DQA_PINLOC_5 (0), + .PORT_MEM_DQA_PINLOC_6 (0), + .PORT_MEM_DQA_PINLOC_7 (0), + .PORT_MEM_DQA_PINLOC_8 (0), + .PORT_MEM_DQA_PINLOC_9 (0), + .PORT_MEM_DQA_PINLOC_10 (0), + .PORT_MEM_DQA_PINLOC_11 (0), + .PORT_MEM_DQA_PINLOC_12 (0), + .PORT_MEM_DQA_PINLOC_13 (0), + .PORT_MEM_DQA_PINLOC_14 (0), + .PORT_MEM_DQA_PINLOC_15 (0), + .PORT_MEM_DQA_PINLOC_16 (0), + .PORT_MEM_DQA_PINLOC_17 (0), + .PORT_MEM_DQA_PINLOC_18 (0), + .PORT_MEM_DQA_PINLOC_19 (0), + .PORT_MEM_DQA_PINLOC_20 (0), + .PORT_MEM_DQA_PINLOC_21 (0), + .PORT_MEM_DQA_PINLOC_22 (0), + .PORT_MEM_DQA_PINLOC_23 (0), + .PORT_MEM_DQA_PINLOC_24 (0), + .PORT_MEM_DQA_PINLOC_25 (0), + .PORT_MEM_DQA_PINLOC_26 (0), + .PORT_MEM_DQA_PINLOC_27 (0), + .PORT_MEM_DQA_PINLOC_28 (0), + .PORT_MEM_DQA_PINLOC_29 (0), + .PORT_MEM_DQA_PINLOC_30 (0), + .PORT_MEM_DQA_PINLOC_31 (0), + .PORT_MEM_DQA_PINLOC_32 (0), + .PORT_MEM_DQA_PINLOC_33 (0), + .PORT_MEM_DQA_PINLOC_34 (0), + .PORT_MEM_DQA_PINLOC_35 (0), + .PORT_MEM_DQA_PINLOC_36 (0), + .PORT_MEM_DQA_PINLOC_37 (0), + .PORT_MEM_DQA_PINLOC_38 (0), + .PORT_MEM_DQA_PINLOC_39 (0), + .PORT_MEM_DQA_PINLOC_40 (0), + .PORT_MEM_DQA_PINLOC_41 (0), + .PORT_MEM_DQA_PINLOC_42 (0), + .PORT_MEM_DQA_PINLOC_43 (0), + .PORT_MEM_DQA_PINLOC_44 (0), + .PORT_MEM_DQA_PINLOC_45 (0), + .PORT_MEM_DQA_PINLOC_46 (0), + .PORT_MEM_DQA_PINLOC_47 (0), + .PORT_MEM_DQA_PINLOC_48 (0), + .PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQB_WIDTH (1), + .PORT_MEM_DQB_PINLOC_0 (0), + .PORT_MEM_DQB_PINLOC_1 (0), + .PORT_MEM_DQB_PINLOC_2 (0), + .PORT_MEM_DQB_PINLOC_3 (0), + .PORT_MEM_DQB_PINLOC_4 (0), + .PORT_MEM_DQB_PINLOC_5 (0), + .PORT_MEM_DQB_PINLOC_6 (0), + .PORT_MEM_DQB_PINLOC_7 (0), + .PORT_MEM_DQB_PINLOC_8 (0), + .PORT_MEM_DQB_PINLOC_9 (0), + .PORT_MEM_DQB_PINLOC_10 (0), + .PORT_MEM_DQB_PINLOC_11 (0), + .PORT_MEM_DQB_PINLOC_12 (0), + .PORT_MEM_DQB_PINLOC_13 (0), + .PORT_MEM_DQB_PINLOC_14 (0), + .PORT_MEM_DQB_PINLOC_15 (0), + .PORT_MEM_DQB_PINLOC_16 (0), + .PORT_MEM_DQB_PINLOC_17 (0), + .PORT_MEM_DQB_PINLOC_18 (0), + .PORT_MEM_DQB_PINLOC_19 (0), + .PORT_MEM_DQB_PINLOC_20 (0), + .PORT_MEM_DQB_PINLOC_21 (0), + .PORT_MEM_DQB_PINLOC_22 (0), + .PORT_MEM_DQB_PINLOC_23 (0), + .PORT_MEM_DQB_PINLOC_24 (0), + .PORT_MEM_DQB_PINLOC_25 (0), + .PORT_MEM_DQB_PINLOC_26 (0), + .PORT_MEM_DQB_PINLOC_27 (0), + .PORT_MEM_DQB_PINLOC_28 (0), + .PORT_MEM_DQB_PINLOC_29 (0), + .PORT_MEM_DQB_PINLOC_30 (0), + .PORT_MEM_DQB_PINLOC_31 (0), + .PORT_MEM_DQB_PINLOC_32 (0), + .PORT_MEM_DQB_PINLOC_33 (0), + .PORT_MEM_DQB_PINLOC_34 (0), + .PORT_MEM_DQB_PINLOC_35 (0), + .PORT_MEM_DQB_PINLOC_36 (0), + .PORT_MEM_DQB_PINLOC_37 (0), + .PORT_MEM_DQB_PINLOC_38 (0), + .PORT_MEM_DQB_PINLOC_39 (0), + .PORT_MEM_DQB_PINLOC_40 (0), + .PORT_MEM_DQB_PINLOC_41 (0), + .PORT_MEM_DQB_PINLOC_42 (0), + .PORT_MEM_DQB_PINLOC_43 (0), + .PORT_MEM_DQB_PINLOC_44 (0), + .PORT_MEM_DQB_PINLOC_45 (0), + .PORT_MEM_DQB_PINLOC_46 (0), + .PORT_MEM_DQB_PINLOC_47 (0), + .PORT_MEM_DQB_PINLOC_48 (0), + .PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DINVA_WIDTH (1), + .PORT_MEM_DINVA_PINLOC_0 (0), + .PORT_MEM_DINVA_PINLOC_1 (0), + .PORT_MEM_DINVA_PINLOC_2 (0), + .PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_DINVB_WIDTH (1), + .PORT_MEM_DINVB_PINLOC_0 (0), + .PORT_MEM_DINVB_PINLOC_1 (0), + .PORT_MEM_DINVB_PINLOC_2 (0), + .PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_Q_WIDTH (1), + .PORT_MEM_Q_PINLOC_0 (0), + .PORT_MEM_Q_PINLOC_1 (0), + .PORT_MEM_Q_PINLOC_2 (0), + .PORT_MEM_Q_PINLOC_3 (0), + .PORT_MEM_Q_PINLOC_4 (0), + .PORT_MEM_Q_PINLOC_5 (0), + .PORT_MEM_Q_PINLOC_6 (0), + .PORT_MEM_Q_PINLOC_7 (0), + .PORT_MEM_Q_PINLOC_8 (0), + .PORT_MEM_Q_PINLOC_9 (0), + .PORT_MEM_Q_PINLOC_10 (0), + .PORT_MEM_Q_PINLOC_11 (0), + .PORT_MEM_Q_PINLOC_12 (0), + .PORT_MEM_Q_PINLOC_13 (0), + .PORT_MEM_Q_PINLOC_14 (0), + .PORT_MEM_Q_PINLOC_15 (0), + .PORT_MEM_Q_PINLOC_16 (0), + .PORT_MEM_Q_PINLOC_17 (0), + .PORT_MEM_Q_PINLOC_18 (0), + .PORT_MEM_Q_PINLOC_19 (0), + .PORT_MEM_Q_PINLOC_20 (0), + .PORT_MEM_Q_PINLOC_21 (0), + .PORT_MEM_Q_PINLOC_22 (0), + .PORT_MEM_Q_PINLOC_23 (0), + .PORT_MEM_Q_PINLOC_24 (0), + .PORT_MEM_Q_PINLOC_25 (0), + .PORT_MEM_Q_PINLOC_26 (0), + .PORT_MEM_Q_PINLOC_27 (0), + .PORT_MEM_Q_PINLOC_28 (0), + .PORT_MEM_Q_PINLOC_29 (0), + .PORT_MEM_Q_PINLOC_30 (0), + .PORT_MEM_Q_PINLOC_31 (0), + .PORT_MEM_Q_PINLOC_32 (0), + .PORT_MEM_Q_PINLOC_33 (0), + .PORT_MEM_Q_PINLOC_34 (0), + .PORT_MEM_Q_PINLOC_35 (0), + .PORT_MEM_Q_PINLOC_36 (0), + .PORT_MEM_Q_PINLOC_37 (0), + .PORT_MEM_Q_PINLOC_38 (0), + .PORT_MEM_Q_PINLOC_39 (0), + .PORT_MEM_Q_PINLOC_40 (0), + .PORT_MEM_Q_PINLOC_41 (0), + .PORT_MEM_Q_PINLOC_42 (0), + .PORT_MEM_Q_PINLOC_43 (0), + .PORT_MEM_Q_PINLOC_44 (0), + .PORT_MEM_Q_PINLOC_45 (0), + .PORT_MEM_Q_PINLOC_46 (0), + .PORT_MEM_Q_PINLOC_47 (0), + .PORT_MEM_Q_PINLOC_48 (0), + .PORT_MEM_Q_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQS_WIDTH (9), + .PORT_MEM_DQS_PINLOC_0 (16781321), + .PORT_MEM_DQS_PINLOC_1 (104898588), + .PORT_MEM_DQS_PINLOC_2 (142733424), + .PORT_MEM_DQS_PINLOC_3 (148), + .PORT_MEM_DQS_PINLOC_4 (0), + .PORT_MEM_DQS_PINLOC_5 (0), + .PORT_MEM_DQS_PINLOC_6 (0), + .PORT_MEM_DQS_PINLOC_7 (0), + .PORT_MEM_DQS_PINLOC_8 (0), + .PORT_MEM_DQS_PINLOC_9 (0), + .PORT_MEM_DQS_PINLOC_10 (0), + .PORT_MEM_DQS_PINLOC_11 (0), + .PORT_MEM_DQS_PINLOC_12 (0), + .PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_DQS_N_WIDTH (9), + .PORT_MEM_DQS_N_PINLOC_0 (17830921), + .PORT_MEM_DQS_N_PINLOC_1 (105948189), + .PORT_MEM_DQS_N_PINLOC_2 (143783025), + .PORT_MEM_DQS_N_PINLOC_3 (149), + .PORT_MEM_DQS_N_PINLOC_4 (0), + .PORT_MEM_DQS_N_PINLOC_5 (0), + .PORT_MEM_DQS_N_PINLOC_6 (0), + .PORT_MEM_DQS_N_PINLOC_7 (0), + .PORT_MEM_DQS_N_PINLOC_8 (0), + .PORT_MEM_DQS_N_PINLOC_9 (0), + .PORT_MEM_DQS_N_PINLOC_10 (0), + .PORT_MEM_DQS_N_PINLOC_11 (0), + .PORT_MEM_DQS_N_PINLOC_12 (0), + .PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_QK_WIDTH (1), + .PORT_MEM_QK_PINLOC_0 (0), + .PORT_MEM_QK_PINLOC_1 (0), + .PORT_MEM_QK_PINLOC_2 (0), + .PORT_MEM_QK_PINLOC_3 (0), + .PORT_MEM_QK_PINLOC_4 (0), + .PORT_MEM_QK_PINLOC_5 (0), + .PORT_MEM_QK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QK_N_WIDTH (1), + .PORT_MEM_QK_N_PINLOC_0 (0), + .PORT_MEM_QK_N_PINLOC_1 (0), + .PORT_MEM_QK_N_PINLOC_2 (0), + .PORT_MEM_QK_N_PINLOC_3 (0), + .PORT_MEM_QK_N_PINLOC_4 (0), + .PORT_MEM_QK_N_PINLOC_5 (0), + .PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKA_WIDTH (1), + .PORT_MEM_QKA_PINLOC_0 (0), + .PORT_MEM_QKA_PINLOC_1 (0), + .PORT_MEM_QKA_PINLOC_2 (0), + .PORT_MEM_QKA_PINLOC_3 (0), + .PORT_MEM_QKA_PINLOC_4 (0), + .PORT_MEM_QKA_PINLOC_5 (0), + .PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKA_N_WIDTH (1), + .PORT_MEM_QKA_N_PINLOC_0 (0), + .PORT_MEM_QKA_N_PINLOC_1 (0), + .PORT_MEM_QKA_N_PINLOC_2 (0), + .PORT_MEM_QKA_N_PINLOC_3 (0), + .PORT_MEM_QKA_N_PINLOC_4 (0), + .PORT_MEM_QKA_N_PINLOC_5 (0), + .PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKB_WIDTH (1), + .PORT_MEM_QKB_PINLOC_0 (0), + .PORT_MEM_QKB_PINLOC_1 (0), + .PORT_MEM_QKB_PINLOC_2 (0), + .PORT_MEM_QKB_PINLOC_3 (0), + .PORT_MEM_QKB_PINLOC_4 (0), + .PORT_MEM_QKB_PINLOC_5 (0), + .PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKB_N_WIDTH (1), + .PORT_MEM_QKB_N_PINLOC_0 (0), + .PORT_MEM_QKB_N_PINLOC_1 (0), + .PORT_MEM_QKB_N_PINLOC_2 (0), + .PORT_MEM_QKB_N_PINLOC_3 (0), + .PORT_MEM_QKB_N_PINLOC_4 (0), + .PORT_MEM_QKB_N_PINLOC_5 (0), + .PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CQ_WIDTH (1), + .PORT_MEM_CQ_PINLOC_0 (0), + .PORT_MEM_CQ_PINLOC_1 (0), + .PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CQ_N_WIDTH (1), + .PORT_MEM_CQ_N_PINLOC_0 (0), + .PORT_MEM_CQ_N_PINLOC_1 (0), + .PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_ALERT_N_PINLOC_0 (94209), + .PORT_MEM_ALERT_N_PINLOC_1 (0), + .PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_PE_N_WIDTH (1), + .PORT_MEM_PE_N_PINLOC_0 (0), + .PORT_MEM_PE_N_PINLOC_1 (0), + .PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (32), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (32), + .PORT_CLKS_SHARING_SLAVE_OUT_WIDTH (32), + .PORT_AFI_RLAT_WIDTH (6), + .PORT_AFI_WLAT_WIDTH (6), + .PORT_AFI_SEQ_BUSY_WIDTH (4), + .PORT_AFI_ADDR_WIDTH (1), + .PORT_AFI_BA_WIDTH (1), + .PORT_AFI_BG_WIDTH (1), + .PORT_AFI_C_WIDTH (1), + .PORT_AFI_CKE_WIDTH (1), + .PORT_AFI_CS_N_WIDTH (1), + .PORT_AFI_RM_WIDTH (1), + .PORT_AFI_ODT_WIDTH (1), + .PORT_AFI_RAS_N_WIDTH (1), + .PORT_AFI_CAS_N_WIDTH (1), + .PORT_AFI_WE_N_WIDTH (1), + .PORT_AFI_RST_N_WIDTH (1), + .PORT_AFI_ACT_N_WIDTH (1), + .PORT_AFI_REQ_N_WIDTH (1), + .PORT_AFI_GNT_N_WIDTH (1), + .PORT_AFI_ERR_N_WIDTH (1), + .PORT_AFI_PAR_WIDTH (1), + .PORT_AFI_CA_WIDTH (1), + .PORT_AFI_REF_N_WIDTH (1), + .PORT_AFI_WPS_N_WIDTH (1), + .PORT_AFI_RPS_N_WIDTH (1), + .PORT_AFI_DOFF_N_WIDTH (1), + .PORT_AFI_LD_N_WIDTH (1), + .PORT_AFI_RW_N_WIDTH (1), + .PORT_AFI_LBK0_N_WIDTH (1), + .PORT_AFI_LBK1_N_WIDTH (1), + .PORT_AFI_CFG_N_WIDTH (1), + .PORT_AFI_AP_WIDTH (1), + .PORT_AFI_AINV_WIDTH (1), + .PORT_AFI_DM_WIDTH (1), + .PORT_AFI_DM_N_WIDTH (1), + .PORT_AFI_BWS_N_WIDTH (1), + .PORT_AFI_RDATA_DBI_N_WIDTH (1), + .PORT_AFI_WDATA_DBI_N_WIDTH (1), + .PORT_AFI_RDATA_DINV_WIDTH (1), + .PORT_AFI_WDATA_DINV_WIDTH (1), + .PORT_AFI_DQS_BURST_WIDTH (1), + .PORT_AFI_WDATA_VALID_WIDTH (1), + .PORT_AFI_WDATA_WIDTH (1), + .PORT_AFI_RDATA_EN_FULL_WIDTH (1), + .PORT_AFI_RDATA_WIDTH (1), + .PORT_AFI_RDATA_VALID_WIDTH (1), + .PORT_AFI_RRANK_WIDTH (1), + .PORT_AFI_WRANK_WIDTH (1), + .PORT_AFI_ALERT_N_WIDTH (1), + .PORT_AFI_PE_N_WIDTH (1), + .PORT_CTRL_AST_CMD_DATA_WIDTH (61), + .PORT_CTRL_AST_WR_DATA_WIDTH (648), + .PORT_CTRL_AST_RD_DATA_WIDTH (576), + .PORT_CTRL_AMM_ADDRESS_WIDTH (1), + .PORT_CTRL_AMM_RDATA_WIDTH (1), + .PORT_CTRL_AMM_WDATA_WIDTH (1), + .PORT_CTRL_AMM_BCOUNT_WIDTH (1), + .PORT_CTRL_AMM_BYTEEN_WIDTH (1), + .PORT_CTRL_STROBE_WIDTH (1), + .PORT_CTRL_STROBE_OE_WIDTH (1), + .PORT_CTRL_DATA_OE_WIDTH (1), + .PORT_CTRL_DATA_OUT_WIDTH (1), + .PORT_CTRL_DATA_IN_WIDTH (1), + .PORT_CTRL_RDATA_VALID_WIDTH (1), + .PORT_CTRL_LOCKED_WIDTH (1), + .PORT_CTRL_RDATA_ENABLE_WIDTH (1), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (4), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (16), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (4), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (15), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (13), + .PORT_CTRL_ECC_READ_INFO_WIDTH (3), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (3), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (12), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (10), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (2), + .PORT_HPS_EMIF_H2E_WIDTH (4096), + .PORT_HPS_EMIF_E2H_WIDTH (4096), + .PORT_HPS_EMIF_H2E_GP_WIDTH (2), + .PORT_HPS_EMIF_E2H_GP_WIDTH (1), + .PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH (9), + .PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH (8), + .PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH (8), + .PORT_DFT_ND_PLL_CNTSEL_WIDTH (4), + .PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH (3), + .PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH (4), + .PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH (2), + .PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH (2), + .PORT_CALBUS_ADDRESS_WIDTH (20), + .PORT_CALBUS_WDATA_WIDTH (32), + .PORT_CALBUS_RDATA_WIDTH (32), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (4096), + .PLL_VCO_FREQ_MHZ_INT (1200), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (1), + .PLL_MEM_CLK_FREQ_PS (834), + .PLL_PHY_CLK_VCO_PHASE (0), + .PLL_VCO_FREQ_PS_STR ("834 ps"), + .PLL_VCO_FREQ_MHZ_STR ("1200 MHz"), + .PLL_REF_CLK_FREQ_PS_STR ("30024 ps"), + .PLL_REF_CLK_FREQ_MHZ_STR ("33.333 MHz"), + .PLL_REF_CLK_FREQ_PS (30024), + .PLL_SIM_VCO_FREQ_PS (840), + .PLL_SIM_PHYCLK_0_FREQ_PS (1680), + .PLL_SIM_PHYCLK_1_FREQ_PS (3360), + .PLL_SIM_PHYCLK_FB_FREQ_PS (3360), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (0), + .PLL_M_CNT_HIGH (18), + .PLL_M_CNT_LOW (18), + .PLL_N_CNT_HIGH (256), + .PLL_N_CNT_LOW (256), + .PLL_M_CNT_BYPASS_EN ("false"), + .PLL_N_CNT_BYPASS_EN ("true"), + .PLL_M_CNT_EVEN_DUTY_EN ("false"), + .PLL_N_CNT_EVEN_DUTY_EN ("false"), + .PLL_FBCLK_MUX_1 ("pll_fbclk_mux_1_glb"), + .PLL_FBCLK_MUX_2 ("pll_fbclk_mux_2_m_cnt"), + .PLL_M_CNT_IN_SRC ("c_m_cnt_in_src_ph_mux_clk"), + .PLL_CP_SETTING ("pll_cp_setting12"), + .PLL_BW_CTRL ("pll_bw_res_setting4"), + .PLL_BW_SEL ("high"), + .PLL_C_CNT_HIGH_0 (2), + .PLL_C_CNT_LOW_0 (2), + .PLL_C_CNT_PRST_0 (1), + .PLL_C_CNT_PH_MUX_PRST_0 (0), + .PLL_C_CNT_BYPASS_EN_0 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_0 ("false"), + .PLL_C_CNT_FREQ_PS_STR_0 ("3336 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_0 ("300.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_0 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_0 (50), + .PLL_C_CNT_OUT_EN_0 ("true"), + .PLL_C_CNT_HIGH_1 (1), + .PLL_C_CNT_LOW_1 (1), + .PLL_C_CNT_PRST_1 (1), + .PLL_C_CNT_PH_MUX_PRST_1 (0), + .PLL_C_CNT_BYPASS_EN_1 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_1 ("false"), + .PLL_C_CNT_FREQ_PS_STR_1 ("1668 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_1 ("600.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_1 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_1 (50), + .PLL_C_CNT_OUT_EN_1 ("true"), + .PLL_C_CNT_HIGH_2 (2), + .PLL_C_CNT_LOW_2 (2), + .PLL_C_CNT_PRST_2 (1), + .PLL_C_CNT_PH_MUX_PRST_2 (0), + .PLL_C_CNT_BYPASS_EN_2 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_2 ("false"), + .PLL_C_CNT_FREQ_PS_STR_2 ("3336 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_2 ("300.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_2 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_2 (50), + .PLL_C_CNT_OUT_EN_2 ("true"), + .PLL_C_CNT_HIGH_3 (1), + .PLL_C_CNT_LOW_3 (1), + .PLL_C_CNT_PRST_3 (1), + .PLL_C_CNT_PH_MUX_PRST_3 (0), + .PLL_C_CNT_BYPASS_EN_3 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_3 ("false"), + .PLL_C_CNT_FREQ_PS_STR_3 ("1668 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_3 ("600.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_3 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_3 (50), + .PLL_C_CNT_OUT_EN_3 ("true"), + .PLL_C_CNT_HIGH_4 (2), + .PLL_C_CNT_LOW_4 (2), + .PLL_C_CNT_PRST_4 (1), + .PLL_C_CNT_PH_MUX_PRST_4 (0), + .PLL_C_CNT_BYPASS_EN_4 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_4 ("false"), + .PLL_C_CNT_FREQ_PS_STR_4 ("3336 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_4 ("300.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_4 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_4 (50), + .PLL_C_CNT_OUT_EN_4 ("true"), + .PLL_C_CNT_HIGH_5 (256), + .PLL_C_CNT_LOW_5 (256), + .PLL_C_CNT_PRST_5 (1), + .PLL_C_CNT_PH_MUX_PRST_5 (0), + .PLL_C_CNT_BYPASS_EN_5 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_5 ("false"), + .PLL_C_CNT_FREQ_PS_STR_5 ("0 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_5 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_5 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_5 (50), + .PLL_C_CNT_OUT_EN_5 ("false"), + .PLL_C_CNT_HIGH_6 (256), + .PLL_C_CNT_LOW_6 (256), + .PLL_C_CNT_PRST_6 (1), + .PLL_C_CNT_PH_MUX_PRST_6 (0), + .PLL_C_CNT_BYPASS_EN_6 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_6 ("false"), + .PLL_C_CNT_FREQ_PS_STR_6 ("0 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_6 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_6 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_6 (50), + .PLL_C_CNT_OUT_EN_6 ("false"), + .PLL_C_CNT_HIGH_7 (256), + .PLL_C_CNT_LOW_7 (256), + .PLL_C_CNT_PRST_7 (1), + .PLL_C_CNT_PH_MUX_PRST_7 (0), + .PLL_C_CNT_BYPASS_EN_7 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_7 ("false"), + .PLL_C_CNT_FREQ_PS_STR_7 ("0 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_7 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_7 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_7 (50), + .PLL_C_CNT_OUT_EN_7 ("false"), + .PLL_C_CNT_HIGH_8 (256), + .PLL_C_CNT_LOW_8 (256), + .PLL_C_CNT_PRST_8 (1), + .PLL_C_CNT_PH_MUX_PRST_8 (0), + .PLL_C_CNT_BYPASS_EN_8 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_8 ("false"), + .PLL_C_CNT_FREQ_PS_STR_8 ("0 ps"), + .PLL_C_CNT_FREQ_MHZ_STR_8 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_8 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_8 (50), + .PLL_C_CNT_OUT_EN_8 ("false") + ) arch ( + .local_reset_req (local_reset_req), // input, width = 1, local_reset_req.local_reset_req + .local_reset_done (local_reset_done), // output, width = 1, local_reset_status.local_reset_done + .pll_ref_clk (pll_ref_clk), // input, width = 1, pll_ref_clk.clk + .pll_locked (pll_locked), // output, width = 1, pll_locked.pll_locked + .oct_rzqin (oct_rzqin), // input, width = 1, oct.oct_rzqin + .mem_ck (mem_ck), // output, width = 1, mem.mem_ck + .mem_ck_n (mem_ck_n), // output, width = 1, .mem_ck_n + .mem_a (mem_a), // output, width = 17, .mem_a + .mem_act_n (mem_act_n), // output, width = 1, .mem_act_n + .mem_ba (mem_ba), // output, width = 2, .mem_ba + .mem_bg (mem_bg), // output, width = 2, .mem_bg + .mem_cke (mem_cke), // output, width = 1, .mem_cke + .mem_cs_n (mem_cs_n), // output, width = 1, .mem_cs_n + .mem_odt (mem_odt), // output, width = 1, .mem_odt + .mem_reset_n (mem_reset_n), // output, width = 1, .mem_reset_n + .mem_par (mem_par), // output, width = 1, .mem_par + .mem_alert_n (mem_alert_n), // input, width = 1, .mem_alert_n + .mem_dqs (mem_dqs), // inout, width = 9, .mem_dqs + .mem_dqs_n (mem_dqs_n), // inout, width = 9, .mem_dqs_n + .mem_dq (mem_dq), // inout, width = 72, .mem_dq + .mem_dbi_n (mem_dbi_n), // inout, width = 9, .mem_dbi_n + .local_cal_success (local_cal_success), // output, width = 1, status.local_cal_success + .local_cal_fail (local_cal_fail), // output, width = 1, .local_cal_fail + .emif_usr_reset_n (arch_emif_usr_reset_n_reset), // output, width = 1, emif_usr_reset_n.reset_n + .emif_usr_clk (arch_emif_usr_clk_clk), // output, width = 1, emif_usr_clk.clk + .ast_cmd_valid_0 (ecc_core_ctrl_ast_cmd_0_valid), // input, width = 1, ctrl_ast_cmd_0.valid + .ast_cmd_ready_0 (ecc_core_ctrl_ast_cmd_0_ready), // output, width = 1, .ready + .ast_cmd_data_0 (ecc_core_ctrl_ast_cmd_0_data), // input, width = 61, .data + .ast_wr_valid_0 (ecc_core_ctrl_ast_wr_0_valid), // input, width = 1, ctrl_ast_wr_0.valid + .ast_wr_ready_0 (ecc_core_ctrl_ast_wr_0_ready), // output, width = 1, .ready + .ast_wr_data_0 (ecc_core_ctrl_ast_wr_0_data), // input, width = 648, .data + .ast_rd_valid_0 (arch_ctrl_ast_rd_0_valid), // output, width = 1, ctrl_ast_rd_0.valid + .ast_rd_ready_0 (arch_ctrl_ast_rd_0_ready), // input, width = 1, .ready + .ast_rd_data_0 (arch_ctrl_ast_rd_0_data), // output, width = 576, .data + .ctrl_ecc_write_info_0 (ecc_core_ctrl_ecc_0_ctrl_ecc_write_info), // input, width = 15, ctrl_ecc_0.ctrl_ecc_write_info + .ctrl_ecc_rdata_id_0 (arch_ctrl_ecc_0_ctrl_ecc_rdata_id), // output, width = 13, .ctrl_ecc_rdata_id + .ctrl_ecc_read_info_0 (arch_ctrl_ecc_0_ctrl_ecc_read_info), // output, width = 3, .ctrl_ecc_read_info + .ctrl_ecc_cmd_info_0 (arch_ctrl_ecc_0_ctrl_ecc_cmd_info), // output, width = 3, .ctrl_ecc_cmd_info + .ctrl_ecc_idle_0 (arch_ctrl_ecc_0_ctrl_ecc_idle), // output, width = 1, .ctrl_ecc_idle + .ctrl_ecc_wr_pointer_info_0 (arch_ctrl_ecc_0_ctrl_ecc_wr_pointer_info), // output, width = 12, .ctrl_ecc_wr_pointer_info + .calbus_read (calbus_read), // input, width = 1, emif_calbus.calbus_read + .calbus_write (calbus_write), // input, width = 1, .calbus_write + .calbus_address (calbus_address), // input, width = 20, .calbus_address + .calbus_wdata (calbus_wdata), // input, width = 32, .calbus_wdata + .calbus_rdata (calbus_rdata), // output, width = 32, .calbus_rdata + .calbus_seq_param_tbl (calbus_seq_param_tbl), // output, width = 4096, .calbus_seq_param_tbl + .calbus_clk (calbus_clk), // input, width = 1, emif_calbus_clk.clk + .pll_ref_clk_out (), // (terminated), + .pll_extra_clk_0 (), // (terminated), + .pll_extra_clk_1 (), // (terminated), + .pll_extra_clk_2 (), // (terminated), + .pll_extra_clk_3 (), // (terminated), + .ac_parity_err (), // (terminated), + .mem_c (), // (terminated), + .mem_rm (), // (terminated), + .mem_ck_bidir (), // (terminated), + .mem_ck_bidir_n (), // (terminated), + .mem_dk (), // (terminated), + .mem_dk_n (), // (terminated), + .mem_dka (), // (terminated), + .mem_dka_n (), // (terminated), + .mem_dkb (), // (terminated), + .mem_dkb_n (), // (terminated), + .mem_k (), // (terminated), + .mem_k_n (), // (terminated), + .mem_req_n (1'b0), // (terminated), + .mem_gnt_n (), // (terminated), + .mem_err_n (1'b0), // (terminated), + .mem_ras_n (), // (terminated), + .mem_cas_n (), // (terminated), + .mem_we_n (), // (terminated), + .mem_ca (), // (terminated), + .mem_ref_n (), // (terminated), + .mem_wps_n (), // (terminated), + .mem_rps_n (), // (terminated), + .mem_doff_n (), // (terminated), + .mem_lda_n (), // (terminated), + .mem_ldb_n (), // (terminated), + .mem_rwa_n (), // (terminated), + .mem_rwb_n (), // (terminated), + .mem_lbk0_n (), // (terminated), + .mem_lbk1_n (), // (terminated), + .mem_cfg_n (), // (terminated), + .mem_ap (), // (terminated), + .mem_ainv (), // (terminated), + .mem_dm (), // (terminated), + .mem_bws_n (), // (terminated), + .mem_d (), // (terminated), + .mem_dqa (), // (terminated), + .mem_dqb (), // (terminated), + .mem_dinva (), // (terminated), + .mem_dinvb (), // (terminated), + .mem_q (1'b0), // (terminated), + .mem_qk (1'b0), // (terminated), + .mem_qk_n (1'b0), // (terminated), + .mem_qka (1'b0), // (terminated), + .mem_qka_n (1'b0), // (terminated), + .mem_qkb (1'b0), // (terminated), + .mem_qkb_n (1'b0), // (terminated), + .mem_cq (1'b0), // (terminated), + .mem_cq_n (1'b0), // (terminated), + .mem_pe_n (1'b0), // (terminated), + .afi_reset_n (), // (terminated), + .afi_clk (), // (terminated), + .afi_half_clk (), // (terminated), + .emif_usr_half_clk (), // (terminated), + .emif_usr_reset_n_sec (), // (terminated), + .emif_usr_clk_sec (), // (terminated), + .emif_usr_half_clk_sec (), // (terminated), + .clks_sharing_master_out (), // (terminated), + .clks_sharing_slave_in (32'b00000000000000000000000000000000), // (terminated), + .clks_sharing_slave_out (), // (terminated), + .afi_cal_success (), // (terminated), + .afi_cal_fail (), // (terminated), + .afi_cal_req (1'b0), // (terminated), + .afi_rlat (), // (terminated), + .afi_wlat (), // (terminated), + .afi_seq_busy (), // (terminated), + .afi_ctl_refresh_done (1'b0), // (terminated), + .afi_ctl_long_idle (1'b0), // (terminated), + .afi_mps_req (1'b0), // (terminated), + .afi_mps_ack (), // (terminated), + .afi_addr (1'b0), // (terminated), + .afi_ba (1'b0), // (terminated), + .afi_bg (1'b0), // (terminated), + .afi_c (1'b0), // (terminated), + .afi_cke (1'b0), // (terminated), + .afi_cs_n (1'b0), // (terminated), + .afi_rm (1'b0), // (terminated), + .afi_odt (1'b0), // (terminated), + .afi_ras_n (1'b0), // (terminated), + .afi_cas_n (1'b0), // (terminated), + .afi_we_n (1'b0), // (terminated), + .afi_rst_n (1'b0), // (terminated), + .afi_act_n (1'b0), // (terminated), + .afi_req_n (), // (terminated), + .afi_gnt_n (1'b0), // (terminated), + .afi_err_n (), // (terminated), + .afi_par (1'b0), // (terminated), + .afi_ca (1'b0), // (terminated), + .afi_ref_n (1'b0), // (terminated), + .afi_wps_n (1'b0), // (terminated), + .afi_rps_n (1'b0), // (terminated), + .afi_doff_n (1'b0), // (terminated), + .afi_ld_n (1'b0), // (terminated), + .afi_rw_n (1'b0), // (terminated), + .afi_lbk0_n (1'b0), // (terminated), + .afi_lbk1_n (1'b0), // (terminated), + .afi_cfg_n (1'b0), // (terminated), + .afi_ap (1'b0), // (terminated), + .afi_ainv (1'b0), // (terminated), + .afi_dm (1'b0), // (terminated), + .afi_dm_n (1'b0), // (terminated), + .afi_bws_n (1'b0), // (terminated), + .afi_rdata_dbi_n (), // (terminated), + .afi_wdata_dbi_n (1'b0), // (terminated), + .afi_rdata_dinv (), // (terminated), + .afi_wdata_dinv (1'b0), // (terminated), + .afi_dqs_burst (1'b0), // (terminated), + .afi_wdata_valid (1'b0), // (terminated), + .afi_wdata (1'b0), // (terminated), + .afi_rdata_en_full (1'b0), // (terminated), + .afi_rdata (), // (terminated), + .afi_rdata_valid (), // (terminated), + .afi_rrank (1'b0), // (terminated), + .afi_wrank (1'b0), // (terminated), + .afi_alert_n (), // (terminated), + .afi_pe_n (), // (terminated), + .amm_ready_0 (), // (terminated), + .amm_read_0 (1'b0), // (terminated), + .amm_write_0 (1'b0), // (terminated), + .amm_address_0 (1'b0), // (terminated), + .amm_readdata_0 (), // (terminated), + .amm_writedata_0 (1'b0), // (terminated), + .amm_burstcount_0 (1'b0), // (terminated), + .amm_byteenable_0 (1'b0), // (terminated), + .amm_beginbursttransfer_0 (1'b0), // (terminated), + .amm_readdatavalid_0 (), // (terminated), + .amm_ready_1 (), // (terminated), + .amm_read_1 (1'b0), // (terminated), + .amm_write_1 (1'b0), // (terminated), + .amm_address_1 (1'b0), // (terminated), + .amm_readdata_1 (), // (terminated), + .amm_writedata_1 (1'b0), // (terminated), + .amm_burstcount_1 (1'b0), // (terminated), + .amm_byteenable_1 (1'b0), // (terminated), + .amm_beginbursttransfer_1 (1'b0), // (terminated), + .amm_readdatavalid_1 (), // (terminated), + .amm_early_ready_0 (), // (terminated), + .amm_early_ready_1 (), // (terminated), + .amm_rd_type_0 (), // (terminated), + .amm_rd_type_1 (), // (terminated), + .phylite_strobe (1'b0), // (terminated), + .phylite_strobe_oe (1'b0), // (terminated), + .phylite_data_oe (1'b0), // (terminated), + .phylite_data_from_core (1'b0), // (terminated), + .phylite_data_to_core (), // (terminated), + .phylite_rdata_valid (), // (terminated), + .phylite_interface_locked (), // (terminated), + .phylite_rdata_en (1'b0), // (terminated), + .ctrl_user_priority_hi_0 (1'b0), // (terminated), + .ctrl_user_priority_hi_1 (1'b0), // (terminated), + .ctrl_auto_precharge_req_0 (1'b0), // (terminated), + .ctrl_auto_precharge_req_1 (1'b0), // (terminated), + .ctrl_user_refresh_req (4'b0000), // (terminated), + .ctrl_user_refresh_bank (16'b0000000000000000), // (terminated), + .ctrl_user_refresh_ack (), // (terminated), + .ctrl_self_refresh_req (4'b0000), // (terminated), + .ctrl_self_refresh_ack (), // (terminated), + .ctrl_will_refresh (), // (terminated), + .ctrl_deep_power_down_req (1'b0), // (terminated), + .ctrl_deep_power_down_ack (), // (terminated), + .ctrl_power_down_ack (), // (terminated), + .ctrl_zq_cal_long_req (1'b0), // (terminated), + .ctrl_zq_cal_short_req (1'b0), // (terminated), + .ctrl_zq_cal_ack (), // (terminated), + .mmr_slave_waitrequest_0 (), // (terminated), + .mmr_slave_read_0 (1'b0), // (terminated), + .mmr_slave_write_0 (1'b0), // (terminated), + .mmr_slave_address_0 (10'b0000000000), // (terminated), + .mmr_slave_readdata_0 (), // (terminated), + .mmr_slave_writedata_0 (32'b00000000000000000000000000000000), // (terminated), + .mmr_slave_burstcount_0 (2'b00), // (terminated), + .mmr_slave_beginbursttransfer_0 (1'b0), // (terminated), + .mmr_slave_readdatavalid_0 (), // (terminated), + .mmr_slave_waitrequest_1 (), // (terminated), + .mmr_slave_read_1 (1'b0), // (terminated), + .mmr_slave_write_1 (1'b0), // (terminated), + .mmr_slave_address_1 (10'b0000000000), // (terminated), + .mmr_slave_readdata_1 (), // (terminated), + .mmr_slave_writedata_1 (32'b00000000000000000000000000000000), // (terminated), + .mmr_slave_burstcount_1 (2'b00), // (terminated), + .mmr_slave_beginbursttransfer_1 (1'b0), // (terminated), + .mmr_slave_readdatavalid_1 (), // (terminated), + .hps_to_emif (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .emif_to_hps (), // (terminated), + .hps_to_emif_gp (2'b00), // (terminated), + .emif_to_hps_gp (), // (terminated), + .pa_dprio_clk (1'b0), // (terminated), + .pa_dprio_read (1'b0), // (terminated), + .pa_dprio_reg_addr (9'b000000000), // (terminated), + .pa_dprio_rst_n (1'b0), // (terminated), + .pa_dprio_write (1'b0), // (terminated), + .pa_dprio_writedata (8'b00000000), // (terminated), + .pa_dprio_block_select (), // (terminated), + .pa_dprio_readdata (), // (terminated), + .pll_phase_en (1'b0), // (terminated), + .pll_up_dn (1'b0), // (terminated), + .pll_cnt_sel (4'b0000), // (terminated), + .pll_num_phase_shifts (3'b000), // (terminated), + .pll_phase_done (), // (terminated), + .pll_core_refclk (4'b0000), // (terminated), + .dft_core_clk_buf_out (), // (terminated), + .dft_core_clk_locked (), // (terminated), + .ast_cmd_valid_1 (1'b0), // (terminated), + .ast_cmd_ready_1 (), // (terminated), + .ast_cmd_data_1 (61'b0000000000000000000000000000000000000000000000000000000000000), // (terminated), + .ast_wr_valid_1 (1'b0), // (terminated), + .ast_wr_ready_1 (), // (terminated), + .ast_wr_data_1 (648'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .ast_rd_valid_1 (), // (terminated), + .ast_rd_ready_1 (1'b0), // (terminated), + .ast_rd_data_1 (), // (terminated), + .ctrl_ecc_write_info_1 (15'b000000000000000), // (terminated), + .ctrl_ecc_rdata_id_1 (), // (terminated), + .ctrl_ecc_read_info_1 (), // (terminated), + .ctrl_ecc_cmd_info_1 (), // (terminated), + .ctrl_ecc_idle_1 (), // (terminated), + .ctrl_ecc_wr_pointer_info_1 () // (terminated), + ); + + ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq ecc_core ( + .emif_usr_reset_n (emif_usr_reset_n), // output, width = 1, emif_usr_reset_n.reset_n + .emif_usr_clk (emif_usr_clk), // output, width = 1, emif_usr_clk.clk + .emif_usr_reset_n_in (arch_emif_usr_reset_n_reset), // input, width = 1, emif_usr_reset_n_in.reset_n + .emif_usr_clk_in (arch_emif_usr_clk_clk), // input, width = 1, emif_usr_clk_in.clk + .ctrl_ecc_write_info_0 (ecc_core_ctrl_ecc_0_ctrl_ecc_write_info), // output, width = 15, ctrl_ecc_0.ctrl_ecc_write_info + .ctrl_ecc_rdata_id_0 (arch_ctrl_ecc_0_ctrl_ecc_rdata_id), // input, width = 13, .ctrl_ecc_rdata_id + .ctrl_ecc_read_info_0 (arch_ctrl_ecc_0_ctrl_ecc_read_info), // input, width = 3, .ctrl_ecc_read_info + .ctrl_ecc_cmd_info_0 (arch_ctrl_ecc_0_ctrl_ecc_cmd_info), // input, width = 3, .ctrl_ecc_cmd_info + .ctrl_ecc_idle_0 (arch_ctrl_ecc_0_ctrl_ecc_idle), // input, width = 1, .ctrl_ecc_idle + .ctrl_ecc_wr_pointer_info_0 (arch_ctrl_ecc_0_ctrl_ecc_wr_pointer_info), // input, width = 12, .ctrl_ecc_wr_pointer_info + .ctrl_ecc_user_interrupt_0 (ctrl_ecc_user_interrupt_0), // output, width = 1, ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt + .ast_cmd_valid_0 (ecc_core_ctrl_ast_cmd_0_valid), // output, width = 1, ctrl_ast_cmd_0.valid + .ast_cmd_ready_0 (ecc_core_ctrl_ast_cmd_0_ready), // input, width = 1, .ready + .ast_cmd_data_0 (ecc_core_ctrl_ast_cmd_0_data), // output, width = 61, .data + .ast_wr_valid_0 (ecc_core_ctrl_ast_wr_0_valid), // output, width = 1, ctrl_ast_wr_0.valid + .ast_wr_ready_0 (ecc_core_ctrl_ast_wr_0_ready), // input, width = 1, .ready + .ast_wr_data_0 (ecc_core_ctrl_ast_wr_0_data), // output, width = 648, .data + .ast_rd_valid_0 (arch_ctrl_ast_rd_0_valid), // input, width = 1, ctrl_ast_rd_0.valid + .ast_rd_ready_0 (arch_ctrl_ast_rd_0_ready), // output, width = 1, .ready + .ast_rd_data_0 (arch_ctrl_ast_rd_0_data), // input, width = 576, .data + .amm_ready_0 (amm_ready_0), // output, width = 1, ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // input, width = 1, .read + .amm_write_0 (amm_write_0), // input, width = 1, .write + .amm_address_0 (amm_address_0), // input, width = 27, .address + .amm_readdata_0 (amm_readdata_0), // output, width = 512, .readdata + .amm_writedata_0 (amm_writedata_0), // input, width = 512, .writedata + .amm_burstcount_0 (amm_burstcount_0), // input, width = 7, .burstcount + .amm_byteenable_0 (amm_byteenable_0), // input, width = 64, .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0) // output, width = 1, .readdatavalid + ); + +endmodule diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.bsf b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.bsf new file mode 100644 index 0000000000..49dc2b2ff3 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.bsf @@ -0,0 +1,413 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the Intel FPGA Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 488 1336) + (text "ed_synth_emif_fm_0" (rect 175 0 264 12)(font "SansSerif" (font_size 11))) + (text "inst" (rect 8 1320 20 1332)(font "Arial" )) + (port + (pt 0 76) + (input) + (text "local_reset_req" (rect 0 0 61 12)(font "SansSerif" (font_size 8))) + (text "local_reset_req" (rect 4 65 94 76)(font "SansSerif" (font_size 8))) + (line (pt 0 76)(pt 170 76)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "pll_ref_clk" (rect 0 0 41 12)(font "SansSerif" (font_size 8))) + (text "pll_ref_clk" (rect 4 165 70 176)(font "SansSerif" (font_size 8))) + (line (pt 0 176)(pt 170 176)(line_width 1)) + ) + (port + (pt 0 276) + (input) + (text "oct_rzqin" (rect 0 0 35 12)(font "SansSerif" (font_size 8))) + (text "oct_rzqin" (rect 4 265 58 276)(font "SansSerif" (font_size 8))) + (line (pt 0 276)(pt 170 276)(line_width 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(pt 170 1326)(pt 323 1326)(line_width 1)) + (line (pt 170 34)(pt 170 1326)(line_width 1)) + (line (pt 171 55)(pt 171 80)(line_width 1)) + (line (pt 172 55)(pt 172 80)(line_width 1)) + (line (pt 171 105)(pt 171 130)(line_width 1)) + (line (pt 172 105)(pt 172 130)(line_width 1)) + (line (pt 171 155)(pt 171 180)(line_width 1)) + (line (pt 172 155)(pt 172 180)(line_width 1)) + (line (pt 488 226)(pt 170 226)(line_width 1)) + (line (pt 171 205)(pt 171 230)(line_width 1)) + (line (pt 172 205)(pt 172 230)(line_width 1)) + (line (pt 171 255)(pt 171 280)(line_width 1)) + (line (pt 172 255)(pt 172 280)(line_width 1)) + (line (pt 488 326)(pt 170 326)(line_width 1)) + (line (pt 488 351)(pt 170 351)(line_width 1)) + (line (pt 488 376)(pt 170 376)(line_width 3)) + (line (pt 488 401)(pt 170 401)(line_width 1)) + (line (pt 488 426)(pt 170 426)(line_width 3)) + (line (pt 488 451)(pt 170 451)(line_width 3)) + (line (pt 488 476)(pt 170 476)(line_width 1)) + (line (pt 488 501)(pt 170 501)(line_width 1)) + (line (pt 488 526)(pt 170 526)(line_width 1)) + (line (pt 488 551)(pt 170 551)(line_width 1)) + (line (pt 488 576)(pt 170 576)(line_width 1)) + (line (pt 171 305)(pt 171 705)(line_width 1)) + (line (pt 172 305)(pt 172 705)(line_width 1)) + (line (pt 488 751)(pt 170 751)(line_width 1)) + (line (pt 488 776)(pt 170 776)(line_width 1)) + (line (pt 171 730)(pt 171 780)(line_width 1)) + (line (pt 172 730)(pt 172 780)(line_width 1)) + (line (pt 488 926)(pt 170 926)(line_width 3)) + (line (pt 488 951)(pt 170 951)(line_width 3)) + (line (pt 171 805)(pt 171 955)(line_width 1)) + (line (pt 172 805)(pt 172 955)(line_width 1)) + (line (pt 171 980)(pt 171 1005)(line_width 1)) + (line (pt 172 980)(pt 172 1005)(line_width 1)) + (line (pt 322 55)(pt 322 80)(line_width 1)) + (line (pt 321 55)(pt 321 80)(line_width 1)) + (line (pt 488 126)(pt 323 126)(line_width 1)) + (line (pt 322 105)(pt 322 130)(line_width 1)) + (line (pt 321 105)(pt 321 130)(line_width 1)) + (line (pt 488 1051)(pt 170 1051)(line_width 1)) + (line (pt 171 1030)(pt 171 1055)(line_width 1)) + (line (pt 172 1030)(pt 172 1055)(line_width 1)) + (line (pt 488 1101)(pt 170 1101)(line_width 1)) + (line (pt 488 1201)(pt 170 1201)(line_width 3)) + (line (pt 488 1301)(pt 170 1301)(line_width 1)) + (line (pt 171 1080)(pt 171 1305)(line_width 1)) + (line (pt 172 1080)(pt 172 1305)(line_width 1)) + (line (pt 0 0)(pt 488 0)(line_width 1)) + (line (pt 488 0)(pt 488 1343)(line_width 1)) + (line (pt 0 1343)(pt 488 1343)(line_width 1)) + (line (pt 0 0)(pt 0 1343)(line_width 1)) + ) +) diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.cmp b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.cmp new file mode 100644 index 0000000000..3ae9f003cd --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.cmp @@ -0,0 +1,47 @@ + component ed_synth_emif_fm_0 is + port ( + local_reset_req : in std_logic := 'X'; -- local_reset_req + local_reset_done : out std_logic; -- local_reset_done + pll_ref_clk : in std_logic := 'X'; -- clk + pll_locked : out std_logic; -- pll_locked + oct_rzqin : in std_logic := 'X'; -- oct_rzqin + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_a : out std_logic_vector(16 downto 0); -- mem_a + mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n + mem_ba : out std_logic_vector(1 downto 0); -- mem_ba + mem_bg : out std_logic_vector(1 downto 0); -- mem_bg + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n + mem_par : out std_logic_vector(0 downto 0); -- mem_par + mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n + mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n + mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq + mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + calbus_read : in std_logic := 'X'; -- calbus_read + calbus_write : in std_logic := 'X'; -- calbus_write + calbus_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- calbus_address + calbus_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_wdata + calbus_rdata : out std_logic_vector(31 downto 0); -- calbus_rdata + calbus_seq_param_tbl : out std_logic_vector(4095 downto 0); -- calbus_seq_param_tbl + calbus_clk : in std_logic := 'X'; -- clk + emif_usr_reset_n : out std_logic; -- reset_n + emif_usr_clk : out std_logic; -- clk + ctrl_ecc_user_interrupt_0 : out std_logic; -- ctrl_ecc_user_interrupt + amm_ready_0 : out std_logic; -- waitrequest_n + amm_read_0 : in std_logic := 'X'; -- read + amm_write_0 : in std_logic := 'X'; -- write + amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address + amm_readdata_0 : out std_logic_vector(511 downto 0); -- readdata + amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata + amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount + amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable + amm_readdatavalid_0 : out std_logic -- readdatavalid + ); + end component ed_synth_emif_fm_0; + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.html b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.html new file mode 100644 index 0000000000..8b08495db7 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.html @@ -0,0 +1,8057 @@ + + + + + datasheet for ed_synth_emif_fm_0 + + + + + + + + +
ed_synth_emif_fm_0 +
+
+
+ + + + + +
2024.07.03.12:58:29Datasheet
+
+
Overview
+ +
+
Memory Map
+ + + + + + + + + + + + + + + + +
  + emif_fm_0 + +
ctrl_amm_0 
  + emif_fm_0_ecc_core + +
ctrl_amm_0 
+ +
+
+

emif_fm_0

altera_emif_fm v2.7.4 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PROTOCOL_ENUMPROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUIE2V (ES3) - change device under 'View'->'Device Family'
PHY_RZQ240
PLL_ADD_EXTRA_CLKSfalse
PHY_DDR4_CONFIG_ENUMCONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_MEM_CLK_FREQ_MHZ1200.0
PHY_DDR4_DEFAULT_REF_CLK_FREQfalse
PHY_DDR4_USER_REF_CLK_FREQ_MHZ33.333
PHY_DDR4_REF_CLK_JITTER_PS10.0
PHY_DDR4_RATE_ENUMRATE_QUARTER
PHY_DDR4_IO_VOLTAGE1.2
PHY_DDR4_DEFAULT_IOfalse
PHY_DDR4_MIMIC_HPS_EMIFfalse
PHY_DDR4_CLAMSHELL_ENfalse
PHY_DDR4_USER_AC_IO_STD_ENUMIO_STD_SSTL_12
PHY_DDR4_USER_AC_MODE_ENUMOUT_OCT_40_CAL
PHY_DDR4_USER_AC_SLEW_RATE_ENUMunset
PHY_DDR4_USER_AC_DEEMPHASIS_ENUMunset
PHY_DDR4_USER_CK_IO_STD_ENUMIO_STD_SSTL_12
PHY_DDR4_USER_CK_MODE_ENUMOUT_OCT_40_CAL
PHY_DDR4_USER_CK_SLEW_RATE_ENUMunset
PHY_DDR4_USER_CK_DEEMPHASIS_ENUMunset
PHY_DDR4_USER_DATA_IO_STD_ENUMIO_STD_POD_12
PHY_DDR4_USER_DATA_OUT_MODE_ENUMOUT_OCT_40_CAL
PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUMunset
PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUMunset
PHY_DDR4_USER_DATA_IN_MODE_ENUMIN_OCT_60_CAL
PHY_DDR4_USER_AUTO_STARTING_VREFIN_ENtrue
PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUMIO_STD_TRUE_DIFF_SIGNALING
PHY_DDR4_USER_RZQ_IO_STD_ENUMIO_STD_CMOS_12
PHY_DDR4_STARTING_VREFIN68.0
MEM_DDR4_FORMAT_ENUMMEM_FORMAT_RDIMM
MEM_DDR4_DQ_WIDTH72
MEM_DDR4_DQ_PER_DQS8
MEM_DDR4_NUM_OF_DIMMS1
MEM_DDR4_CHIP_ID_WIDTH0
MEM_DDR4_RANKS_PER_DIMM1
MEM_DDR4_CK_WIDTH1
MEM_DDR4_ROW_ADDR_WIDTH16
MEM_DDR4_COL_ADDR_WIDTH10
MEM_DDR4_BANK_ADDR_WIDTH2
MEM_DDR4_BANK_GROUP_WIDTH2
MEM_DDR4_DM_ENtrue
MEM_DDR4_ALERT_N_PLACEMENT_ENUMDDR4_ALERT_N_PLACEMENT_FM_LANE3
MEM_DDR4_INTEL_DEFAULT_TERMtrue
MEM_DDR4_TCL21
MEM_DDR4_ATCL_ENUMDDR4_ATCL_DISABLED
MEM_DDR4_WTCL16
MEM_DDR4_FINE_GRANULARITY_REFRESHDDR4_FINE_REFRESH_FIXED_1X
MEM_DDR4_AC_PARITY_LATENCYDDR4_AC_PARITY_LATENCY_DISABLE
MEM_DDR4_WRITE_DBIfalse
MEM_DDR4_READ_DBItrue
MEM_DDR4_DEFAULT_VREFOUTtrue
MEM_DDR4_RCD_CA_IBT_ENUMDDR4_RCD_CA_IBT_100
MEM_DDR4_RCD_CS_IBT_ENUMDDR4_RCD_CS_IBT_100
MEM_DDR4_RCD_CKE_IBT_ENUMDDR4_RCD_CKE_IBT_100
MEM_DDR4_RCD_ODT_IBT_ENUMDDR4_RCD_ODT_IBT_100
MEM_DDR4_SPD_137_RCD_CA_DRV101
MEM_DDR4_SPD_138_RCD_CK_DRV5
MEM_DDR4_DQS_WIDTH9
MEM_DDR4_CS_PER_DIMM1
MEM_DDR4_VREFDQ_TRAINING_VALUE70.0
MEM_DDR4_VREFDQ_TRAINING_RANGE_DISPRange 1 - 60% to 92.5%
MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISPRZQ/7 (34 Ohm)
MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISPDynamic ODT off
MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISPODT Disabled
MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISPRZQ/4 (60 Ohm)
MEM_DDR4_USE_DEFAULT_ODTtrue
MEM_DDR4_R_ODTN_1X1Rank 0
MEM_DDR4_R_ODT0_1X1off
MEM_DDR4_W_ODTN_1X1Rank 0
MEM_DDR4_W_ODT0_1X1on
MEM_DDR4_R_ODTN_2X2Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2off,off
MEM_DDR4_R_ODT1_2X2off,off
MEM_DDR4_W_ODTN_2X2Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2on,off
MEM_DDR4_W_ODT1_2X2off,on
MEM_DDR4_R_ODTN_4X2Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2off,off,on,on
MEM_DDR4_R_ODT1_4X2on,on,off,off
MEM_DDR4_W_ODTN_4X2Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2off,off,on,on
MEM_DDR4_W_ODT1_4X2on,on,off,off
MEM_DDR4_R_ODTN_4X4Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4off,off,on,off
MEM_DDR4_R_ODT1_4X4off,off,off,on
MEM_DDR4_R_ODT2_4X4on,off,off,off
MEM_DDR4_R_ODT3_4X4off,on,off,off
MEM_DDR4_W_ODTN_4X4Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4on,off,on,off
MEM_DDR4_W_ODT1_4X4off,on,off,on
MEM_DDR4_W_ODT2_4X4on,off,on,off
MEM_DDR4_W_ODT3_4X4off,on,off,on
MEM_DDR4_R_DERIVED_ODTNRank 0,-,-,-
MEM_DDR4_R_DERIVED_ODT0(Drive) RZQ/7 (34 Ohm),-,-,-
MEM_DDR4_R_DERIVED_ODT1-,-,-,-
MEM_DDR4_R_DERIVED_ODT2-,-,-,-
MEM_DDR4_R_DERIVED_ODT3-,-,-,-
MEM_DDR4_R_DERIVED_BODTN
MEM_DDR4_R_DERIVED_BODT0
MEM_DDR4_R_DERIVED_BODT1
MEM_DDR4_W_DERIVED_ODTNRank 0,-,-,-
MEM_DDR4_W_DERIVED_ODT0(Park) RZQ/4 (60 Ohm),-,-,-
MEM_DDR4_W_DERIVED_ODT1-,-,-,-
MEM_DDR4_W_DERIVED_ODT2-,-,-,-
MEM_DDR4_W_DERIVED_ODT3-,-,-,-
MEM_DDR4_W_DERIVED_BODTN
MEM_DDR4_W_DERIVED_BODT0
MEM_DDR4_W_DERIVED_BODT1
MEM_DDR4_SPEEDBIN_ENUMDDR4_SPEEDBIN_2666
MEM_DDR4_TIS_PS62
MEM_DDR4_TIS_AC_MV100
MEM_DDR4_TIH_PS87
MEM_DDR4_TIH_DC_MV75
MEM_DDR4_TDIVW_TOTAL_UI0.2
MEM_DDR4_VDIVW_TOTAL130
MEM_DDR4_TDQSQ_UI0.14
MEM_DDR4_TQH_UI0.74
MEM_DDR4_TDVWP_UI0.72
MEM_DDR4_TDQSCK_PS175
MEM_DDR4_TDQSS_CYC0.27
MEM_DDR4_TQSH_CYC0.4
MEM_DDR4_TDSH_CYC0.18
MEM_DDR4_TDSS_CYC0.18
MEM_DDR4_TWLS_CYC0.13
MEM_DDR4_TWLH_CYC0.13
MEM_DDR4_TINIT_US500
MEM_DDR4_TMRD_CK_CYC8
MEM_DDR4_TRAS_NS32.0
MEM_DDR4_TRCD_NS14.16
MEM_DDR4_TRP_NS14.16
MEM_DDR4_TREFI_US7.8
MEM_DDR4_TRFC_NS350.0
MEM_DDR4_TWR_NS15.0
MEM_DDR4_TWTR_L_CYC9
MEM_DDR4_TWTR_S_CYC3
MEM_DDR4_TFAW_NS21.0
MEM_DDR4_TRRD_L_CYC6
MEM_DDR4_TRRD_S_CYC4
MEM_DDR4_TCCD_L_CYC6
MEM_DDR4_TCCD_S_CYC4
CTRL_DDR4_AUTO_POWER_DOWN_ENfalse
CTRL_DDR4_AUTO_POWER_DOWN_CYCS32
CTRL_DDR4_USER_REFRESH_ENfalse
CTRL_DDR4_USER_PRIORITY_ENfalse
CTRL_DDR4_AUTO_PRECHARGE_ENfalse
CTRL_DDR4_ADDR_ORDER_ENUMDDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_ENtrue
CTRL_DDR4_ECC_AUTO_CORRECTION_ENfalse
CTRL_DDR4_ECC_READDATAERROR_ENfalse
CTRL_DDR4_ECC_STATUS_ENfalse
CTRL_DDR4_REORDER_ENtrue
CTRL_DDR4_STARVE_LIMIT10
CTRL_DDR4_MMR_ENfalse
CTRL_DDR4_MAJOR_MODE_ENfalse
CTRL_DDR4_POST_REFRESH_ENtrue
CTRL_DDR4_POST_REFRESH_LOWER_LIMIT0
CTRL_DDR4_POST_REFRESH_UPPER_LIMIT2
CTRL_DDR4_PRE_REFRESH_ENfalse
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS0
DIAG_EXPORT_PLL_LOCKEDtrue
DIAG_DDR4_SIM_CAL_MODE_ENUMSIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVECAL_DEBUG_EXPORT_MODE_JTAG
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES1
DIAG_DDR4_EX_DESIGN_ISSP_ENtrue
DIAG_DDR4_EFFICIENCY_MONITOREFFMON_MODE_DISABLED
DIAG_DDR4_USE_TG_AVL_2false
DIAG_DDR4_ENABLE_DEFAULT_MODEfalse
DIAG_DDR4_ENABLE_USER_MODEtrue
DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVETG_CFG_AMM_EXPORT_MODE_EXPORT
DIAG_DDR4_TG2_TEST_DURATIONSHORT
DIAG_DDR4_AC_PARITY_ERRfalse
DIAG_DDR4_SKIP_AC_PARITY_CHECKfalse
NUM_IPS1
EX_DESIGN_GUI_DDR4_GEN_SIMtrue
EX_DESIGN_GUI_DDR4_GEN_SYNTHtrue
EX_DESIGN_GUI_DDR4_GEN_BSIfalse
EX_DESIGN_GUI_DDR4_GEN_CDCfalse
EX_DESIGN_GUI_DDR4_HDL_FORMATHDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KITTARGET_DEV_KIT_NONE
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

emif_fm_0_arch

altera_emif_arch_fm v19.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ emif_fm_0_ecc_core + ctrl_ecc_0  emif_fm_0_arch
  ctrl_ecc_0
ctrl_ast_cmd_0  
  ctrl_ast_cmd_0
ctrl_ast_wr_0  
  ctrl_ast_wr_0
emif_usr_clk   + emif_fm_0_ecc_core +
  emif_usr_clk_in
emif_usr_reset_n  
  emif_usr_reset_n_in
ctrl_ast_rd_0  
  ctrl_ast_rd_0
+
+
+
+ + + + +
+

Parameters

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LANE_PIN_USAGE_171582788
LANE_PIN_USAGE_2286266145
LANE_PIN_USAGE_3209994820
LANE_PIN_USAGE_4286331137
LANE_PIN_USAGE_567422276
LANE_PIN_USAGE_671581969
LANE_PIN_USAGE_7269828353
LANE_PIN_USAGE_871582788
LANE_PIN_USAGE_969905
LANE_PIN_USAGE_1067388484
LANE_PIN_USAGE_1117
LANE_PIN_USAGE_12285213696
LANE_PIN_USAGE_1367422276
LANE_PIN_USAGE_14554766609
LANE_PIN_USAGE_1571581772
LANE_PIN_USAGE_1620058385
LANE_PIN_USAGE_1771582788
LANE_PIN_USAGE_18286266145
LANE_PIN_USAGE_19209994820
LANE_PIN_USAGE_201118465
LANE_PIN_USAGE_210
LANE_PIN_USAGE_220
LANE_PIN_USAGE_230
LANE_PIN_USAGE_240
LANE_PIN_USAGE_250
LANE_PIN_USAGE_260
LANE_PIN_USAGE_270
LANE_PIN_USAGE_280
LANE_PIN_USAGE_290
LANE_PIN_USAGE_300
LANE_PIN_USAGE_310
LANE_PIN_USAGE_320
LANE_PIN_USAGE_330
LANE_PIN_USAGE_340
LANE_PIN_USAGE_350
LANE_PIN_USAGE_360
LANE_PIN_USAGE_370
LANE_PIN_USAGE_380
LANE_PIN_USAGE_390
LANE_PIN_USAGE_400
LANE_PIN_USAGE_410
LANE_PIN_USAGE_420
LANE_PIN_USAGE_430
LANE_PIN_USAGE_440
LANE_PIN_USAGE_450
LANE_PIN_USAGE_460
LANE_PIN_USAGE_470
LANE_PIN_USAGE_480
LANE_PIN_USAGE_490
LANE_PIN_USAGE_500
LANE_PIN_USAGE_510
LANE_PIN_USAGE_AUTOGEN_WCNT52
PINS_RATE_00
PINS_RATE_1561774592
PINS_RATE_215699967
PINS_RATE_34
PINS_RATE_40
PINS_RATE_50
PINS_RATE_60
PINS_RATE_70
PINS_RATE_80
PINS_RATE_90
PINS_RATE_100
PINS_RATE_110
PINS_RATE_120
PINS_RATE_AUTOGEN_WCNT13
DB_PINS_PROC_MODE_0275876963
DB_PINS_PROC_MODE_1103911395
DB_PINS_PROC_MODE_2275876963
DB_PINS_PROC_MODE_3103911395
DB_PINS_PROC_MODE_4275876963
DB_PINS_PROC_MODE_5103911395
DB_PINS_PROC_MODE_6275876963
DB_PINS_PROC_MODE_7103911395
DB_PINS_PROC_MODE_81041269793
DB_PINS_PROC_MODE_966230241
DB_PINS_PROC_MODE_1034636833
DB_PINS_PROC_MODE_1134636833
DB_PINS_PROC_MODE_1234668543
DB_PINS_PROC_MODE_1334667553
DB_PINS_PROC_MODE_141073741823
DB_PINS_PROC_MODE_151073730559
DB_PINS_PROC_MODE_16275876963
DB_PINS_PROC_MODE_17103911395
DB_PINS_PROC_MODE_18275876963
DB_PINS_PROC_MODE_19103911395
DB_PINS_PROC_MODE_20275876963
DB_PINS_PROC_MODE_21103911395
DB_PINS_PROC_MODE_22275876963
DB_PINS_PROC_MODE_23103911395
DB_PINS_PROC_MODE_24275876963
DB_PINS_PROC_MODE_25103911395
DB_PINS_PROC_MODE_261073741823
DB_PINS_PROC_MODE_271073741823
DB_PINS_PROC_MODE_281073741823
DB_PINS_PROC_MODE_291073741823
DB_PINS_PROC_MODE_301073741823
DB_PINS_PROC_MODE_311073741823
DB_PINS_PROC_MODE_320
DB_PINS_PROC_MODE_330
DB_PINS_PROC_MODE_340
DB_PINS_PROC_MODE_350
DB_PINS_PROC_MODE_360
DB_PINS_PROC_MODE_370
DB_PINS_PROC_MODE_380
DB_PINS_PROC_MODE_390
DB_PINS_PROC_MODE_400
DB_PINS_PROC_MODE_410
DB_PINS_PROC_MODE_420
DB_PINS_PROC_MODE_430
DB_PINS_PROC_MODE_440
DB_PINS_PROC_MODE_450
DB_PINS_PROC_MODE_460
DB_PINS_PROC_MODE_470
DB_PINS_PROC_MODE_480
DB_PINS_PROC_MODE_490
DB_PINS_PROC_MODE_500
DB_PINS_PROC_MODE_510
DB_PINS_PROC_MODE_520
DB_PINS_PROC_MODE_530
DB_PINS_PROC_MODE_540
DB_PINS_PROC_MODE_550
DB_PINS_PROC_MODE_560
DB_PINS_PROC_MODE_570
DB_PINS_PROC_MODE_580
DB_PINS_PROC_MODE_590
DB_PINS_PROC_MODE_600
DB_PINS_PROC_MODE_610
DB_PINS_PROC_MODE_620
DB_PINS_PROC_MODE_630
DB_PINS_PROC_MODE_AUTOGEN_WCNT64
PINS_DATA_IN_MODE_0151515721
PINS_DATA_IN_MODE_133329737
PINS_DATA_IN_MODE_21059361353
PINS_DATA_IN_MODE_3153391681
PINS_DATA_IN_MODE_4153391231
PINS_DATA_IN_MODE_5150736969
PINS_DATA_IN_MODE_6153391689
PINS_DATA_IN_MODE_7153387017
PINS_DATA_IN_MODE_8584
PINS_DATA_IN_MODE_9153354304
PINS_DATA_IN_MODE_10153391231
PINS_DATA_IN_MODE_11153362377
PINS_DATA_IN_MODE_12151515721
PINS_DATA_IN_MODE_1333329737
PINS_DATA_IN_MODE_141059361353
PINS_DATA_IN_MODE_1537441
PINS_DATA_IN_MODE_160
PINS_DATA_IN_MODE_170
PINS_DATA_IN_MODE_180
PINS_DATA_IN_MODE_190
PINS_DATA_IN_MODE_200
PINS_DATA_IN_MODE_210
PINS_DATA_IN_MODE_220
PINS_DATA_IN_MODE_230
PINS_DATA_IN_MODE_240
PINS_DATA_IN_MODE_250
PINS_DATA_IN_MODE_260
PINS_DATA_IN_MODE_270
PINS_DATA_IN_MODE_280
PINS_DATA_IN_MODE_290
PINS_DATA_IN_MODE_300
PINS_DATA_IN_MODE_310
PINS_DATA_IN_MODE_320
PINS_DATA_IN_MODE_330
PINS_DATA_IN_MODE_340
PINS_DATA_IN_MODE_350
PINS_DATA_IN_MODE_360
PINS_DATA_IN_MODE_370
PINS_DATA_IN_MODE_380
PINS_DATA_IN_MODE_AUTOGEN_WCNT39
PINS_C2L_DRIVEN_0267714383
PINS_C2L_DRIVEN_1250877
PINS_C2L_DRIVEN_20
PINS_C2L_DRIVEN_31027593152
PINS_C2L_DRIVEN_4267714383
PINS_C2L_DRIVEN_561
PINS_C2L_DRIVEN_60
PINS_C2L_DRIVEN_70
PINS_C2L_DRIVEN_80
PINS_C2L_DRIVEN_90
PINS_C2L_DRIVEN_100
PINS_C2L_DRIVEN_110
PINS_C2L_DRIVEN_120
PINS_C2L_DRIVEN_AUTOGEN_WCNT13
PINS_OCT_MODE_01073217407
PINS_OCT_MODE_1253949
PINS_OCT_MODE_20
PINS_OCT_MODE_31040179136
PINS_OCT_MODE_41073217407
PINS_OCT_MODE_561
PINS_OCT_MODE_60
PINS_OCT_MODE_70
PINS_OCT_MODE_80
PINS_OCT_MODE_90
PINS_OCT_MODE_100
PINS_OCT_MODE_110
PINS_OCT_MODE_120
PINS_OCT_MODE_AUTOGEN_WCNT13
PINS_DCC_SPLIT_0805503024
PINS_DCC_SPLIT_1201329664
PINS_DCC_SPLIT_20
PINS_DCC_SPLIT_312585984
PINS_DCC_SPLIT_4805503024
PINS_DCC_SPLIT_50
PINS_DCC_SPLIT_60
PINS_DCC_SPLIT_70
PINS_DCC_SPLIT_80
PINS_DCC_SPLIT_90
PINS_DCC_SPLIT_100
PINS_DCC_SPLIT_110
PINS_DCC_SPLIT_120
PINS_DCC_SPLIT_AUTOGEN_WCNT13
UNUSED_MEM_PINS_PINLOC_0199425087
UNUSED_MEM_PINS_PINLOC_1196276413
UNUSED_MEM_PINS_PINLOC_2193127610
UNUSED_MEM_PINS_PINLOC_3189978807
UNUSED_MEM_PINS_PINLOC_4186830004
UNUSED_MEM_PINS_PINLOC_5183681201
UNUSED_MEM_PINS_PINLOC_6180532398
UNUSED_MEM_PINS_PINLOC_7177383595
UNUSED_MEM_PINS_PINLOC_8174234792
UNUSED_MEM_PINS_PINLOC_9171085989
UNUSED_MEM_PINS_PINLOC_10167937186
UNUSED_MEM_PINS_PINLOC_11164788383
UNUSED_MEM_PINS_PINLOC_12145906844
UNUSED_MEM_PINS_PINLOC_13108121215
UNUSED_MEM_PINS_PINLOC_1497613919
UNUSED_MEM_PINS_PINLOC_1593415515
UNUSED_MEM_PINS_PINLOC_1690266712
UNUSED_MEM_PINS_PINLOC_1783972181
UNUSED_MEM_PINS_PINLOC_1875572298
UNUSED_MEM_PINS_PINLOC_1955630906
UNUSED_MEM_PINS_PINLOC_2019954731
UNUSED_MEM_PINS_PINLOC_217
UNUSED_MEM_PINS_PINLOC_220
UNUSED_MEM_PINS_PINLOC_230
UNUSED_MEM_PINS_PINLOC_240
UNUSED_MEM_PINS_PINLOC_250
UNUSED_MEM_PINS_PINLOC_260
UNUSED_MEM_PINS_PINLOC_270
UNUSED_MEM_PINS_PINLOC_280
UNUSED_MEM_PINS_PINLOC_290
UNUSED_MEM_PINS_PINLOC_300
UNUSED_MEM_PINS_PINLOC_310
UNUSED_MEM_PINS_PINLOC_320
UNUSED_MEM_PINS_PINLOC_330
UNUSED_MEM_PINS_PINLOC_340
UNUSED_MEM_PINS_PINLOC_350
UNUSED_MEM_PINS_PINLOC_360
UNUSED_MEM_PINS_PINLOC_370
UNUSED_MEM_PINS_PINLOC_380
UNUSED_MEM_PINS_PINLOC_390
UNUSED_MEM_PINS_PINLOC_400
UNUSED_MEM_PINS_PINLOC_410
UNUSED_MEM_PINS_PINLOC_420
UNUSED_MEM_PINS_PINLOC_430
UNUSED_MEM_PINS_PINLOC_440
UNUSED_MEM_PINS_PINLOC_450
UNUSED_MEM_PINS_PINLOC_460
UNUSED_MEM_PINS_PINLOC_470
UNUSED_MEM_PINS_PINLOC_480
UNUSED_MEM_PINS_PINLOC_490
UNUSED_MEM_PINS_PINLOC_500
UNUSED_MEM_PINS_PINLOC_510
UNUSED_MEM_PINS_PINLOC_520
UNUSED_MEM_PINS_PINLOC_530
UNUSED_MEM_PINS_PINLOC_540
UNUSED_MEM_PINS_PINLOC_550
UNUSED_MEM_PINS_PINLOC_560
UNUSED_MEM_PINS_PINLOC_570
UNUSED_MEM_PINS_PINLOC_580
UNUSED_MEM_PINS_PINLOC_590
UNUSED_MEM_PINS_PINLOC_600
UNUSED_MEM_PINS_PINLOC_610
UNUSED_MEM_PINS_PINLOC_620
UNUSED_MEM_PINS_PINLOC_630
UNUSED_MEM_PINS_PINLOC_640
UNUSED_MEM_PINS_PINLOC_650
UNUSED_MEM_PINS_PINLOC_660
UNUSED_MEM_PINS_PINLOC_670
UNUSED_MEM_PINS_PINLOC_680
UNUSED_MEM_PINS_PINLOC_690
UNUSED_MEM_PINS_PINLOC_700
UNUSED_MEM_PINS_PINLOC_710
UNUSED_MEM_PINS_PINLOC_720
UNUSED_MEM_PINS_PINLOC_730
UNUSED_MEM_PINS_PINLOC_740
UNUSED_MEM_PINS_PINLOC_750
UNUSED_MEM_PINS_PINLOC_760
UNUSED_MEM_PINS_PINLOC_770
UNUSED_MEM_PINS_PINLOC_780
UNUSED_MEM_PINS_PINLOC_790
UNUSED_MEM_PINS_PINLOC_800
UNUSED_MEM_PINS_PINLOC_810
UNUSED_MEM_PINS_PINLOC_820
UNUSED_MEM_PINS_PINLOC_830
UNUSED_MEM_PINS_PINLOC_840
UNUSED_MEM_PINS_PINLOC_850
UNUSED_MEM_PINS_PINLOC_860
UNUSED_MEM_PINS_PINLOC_870
UNUSED_MEM_PINS_PINLOC_880
UNUSED_MEM_PINS_PINLOC_890
UNUSED_MEM_PINS_PINLOC_900
UNUSED_MEM_PINS_PINLOC_910
UNUSED_MEM_PINS_PINLOC_920
UNUSED_MEM_PINS_PINLOC_930
UNUSED_MEM_PINS_PINLOC_940
UNUSED_MEM_PINS_PINLOC_950
UNUSED_MEM_PINS_PINLOC_960
UNUSED_MEM_PINS_PINLOC_970
UNUSED_MEM_PINS_PINLOC_980
UNUSED_MEM_PINS_PINLOC_990
UNUSED_MEM_PINS_PINLOC_1000
UNUSED_MEM_PINS_PINLOC_1010
UNUSED_MEM_PINS_PINLOC_1020
UNUSED_MEM_PINS_PINLOC_1030
UNUSED_MEM_PINS_PINLOC_1040
UNUSED_MEM_PINS_PINLOC_1050
UNUSED_MEM_PINS_PINLOC_1060
UNUSED_MEM_PINS_PINLOC_1070
UNUSED_MEM_PINS_PINLOC_1080
UNUSED_MEM_PINS_PINLOC_1090
UNUSED_MEM_PINS_PINLOC_1100
UNUSED_MEM_PINS_PINLOC_1110
UNUSED_MEM_PINS_PINLOC_1120
UNUSED_MEM_PINS_PINLOC_1130
UNUSED_MEM_PINS_PINLOC_1140
UNUSED_MEM_PINS_PINLOC_1150
UNUSED_MEM_PINS_PINLOC_1160
UNUSED_MEM_PINS_PINLOC_1170
UNUSED_MEM_PINS_PINLOC_1180
UNUSED_MEM_PINS_PINLOC_1190
UNUSED_MEM_PINS_PINLOC_1200
UNUSED_MEM_PINS_PINLOC_1210
UNUSED_MEM_PINS_PINLOC_1220
UNUSED_MEM_PINS_PINLOC_1230
UNUSED_MEM_PINS_PINLOC_1240
UNUSED_MEM_PINS_PINLOC_1250
UNUSED_MEM_PINS_PINLOC_1260
UNUSED_MEM_PINS_PINLOC_1270
UNUSED_MEM_PINS_PINLOC_1280
UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT129
UNUSED_DQS_BUSES_LANELOC_014695431
UNUSED_DQS_BUSES_LANELOC_16298637
UNUSED_DQS_BUSES_LANELOC_24101
UNUSED_DQS_BUSES_LANELOC_30
UNUSED_DQS_BUSES_LANELOC_40
UNUSED_DQS_BUSES_LANELOC_50
UNUSED_DQS_BUSES_LANELOC_60
UNUSED_DQS_BUSES_LANELOC_70
UNUSED_DQS_BUSES_LANELOC_80
UNUSED_DQS_BUSES_LANELOC_90
UNUSED_DQS_BUSES_LANELOC_100
UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT11
DBC_EXTRA_PIPE_STAGE_ENdisable
DBC_PIPE_LATS_0286335522
DBC_PIPE_LATS_1821384
DBC_PIPE_LATS_20
DBC_PIPE_LATS_30
DBC_PIPE_LATS_40
DBC_PIPE_LATS_AUTOGEN_WCNT5
DB_PTR_PIPELINE_DEPTHS_0286331153
DB_PTR_PIPELINE_DEPTHS_117476
DB_PTR_PIPELINE_DEPTHS_20
DB_PTR_PIPELINE_DEPTHS_30
DB_PTR_PIPELINE_DEPTHS_40
DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT5
DB_SEQ_RD_EN_FULL_PIPELINES_0858993459
DB_SEQ_RD_EN_FULL_PIPELINES_1838860
DB_SEQ_RD_EN_FULL_PIPELINES_20
DB_SEQ_RD_EN_FULL_PIPELINES_30
DB_SEQ_RD_EN_FULL_PIPELINES_40
DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT5
CENTER_TIDS_0542119940
CENTER_TIDS_13
CENTER_TIDS_20
CENTER_TIDS_AUTOGEN_WCNT3
HMC_TIDS_0676600325
HMC_TIDS_13
HMC_TIDS_20
HMC_TIDS_AUTOGEN_WCNT3
LANE_TIDS_0403177984
LANE_TIDS_1168067584
LANE_TIDS_235717208
LANE_TIDS_3140518930
LANE_TIDS_4886403
LANE_TIDS_50
LANE_TIDS_60
LANE_TIDS_70
LANE_TIDS_80
LANE_TIDS_90
LANE_TIDS_AUTOGEN_WCNT10
PREAMBLE_MODEpreamble_one_cycle
DBI_WR_ENABLEdbi_wr_dis
DBI_RD_ENABLEdbi_rd_ena
SWAP_DQS_A_Bfalse
DQS_PACK_MODEpacked
OCT_SIZE3
DQSA_LGC_MODEdqs_diff_in_1_a
DQSB_LGC_MODEdqs_constant_b
DBC_WB_RESERVED_ENTRY52
DLL_MODEdll_ctl_dynamic
DLL_CODEWORD0
ABPHY_WRITE_PROTOCOL0
PHY_USERMODE_OCTfalse
PHY_PERIODIC_OCT_RECALfalse
GENERATE_PHYLITEfalse
HPRX_CTLE_ENon
HPRX_OFFSET_CALtrue
CPA_FB_MUX_1_SELlocal_p_clk
ENABLE_RD_TYPEfalse
AMM_C2P_UFI_MODEpin_ufi_use_in_direct_out_direct
AMM_P2C_UFI_MODEpin_ufi_use_in_direct_out_direct
MMR_C2P_UFI_MODEpin_ufi_use_in_direct_out_direct
MMR_P2C_UFI_MODEpin_ufi_use_in_direct_out_direct
SIDEBAND_C2P_UFI_MODEpin_ufi_use_in_direct_out_direct
SIDEBAND_P2C_UFI_MODEpin_ufi_use_in_direct_out_direct
SEQ_C2P_UFI_MODEpin_ufi_use_in_direct_out_direct
SEQ_P2C_UFI_MODEpin_ufi_use_in_direct_out_direct
ECC_C2P_UFI_MODEpin_ufi_use_in_direct_out_direct
ECC_P2C_UFI_MODEpin_ufi_use_in_direct_out_direct
LANE_C2P_UFI_MODEpin_ufi_use_in_direct_out_direct
LANE_P2C_UFI_MODEpin_ufi_use_in_direct_out_direct
AMM_HIPI_DELAY350
MMR_HIPI_DELAY350
SIDEBAND_HIPI_DELAY350
SEQ_HIPI_DELAY350
ECC_HIPI_DELAY350
LANE_HIPI_DELAY350
PRI_HMC_CFG_PING_PONG_MODEpingpong_off
PRI_HMC_CFG_CS_ADDR_WIDTHcs_width_0
PRI_HMC_CFG_COL_ADDR_WIDTHcol_width_10
PRI_HMC_CFG_ROW_ADDR_WIDTHrow_width_16
PRI_HMC_CFG_BANK_ADDR_WIDTHbank_width_2
PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTHbank_group_width_2
PRI_HMC_CFG_ADDR_ORDERaddr_order_cs_row_ba_col
PRI_HMC_CFG_ARBITER_TYPEarbiter_type_2t
PRI_HMC_CFG_OPEN_PAGE_ENdisable
PRI_HMC_CFG_CTRL_ENABLE_RCenable
PRI_HMC_CFG_DBC0_ENABLE_RCenable
PRI_HMC_CFG_DBC1_ENABLE_RCenable
PRI_HMC_CFG_DBC2_ENABLE_RCenable
PRI_HMC_CFG_DBC3_ENABLE_RCenable
PRI_HMC_CFG_CTRL_ENABLE_ECCenable
PRI_HMC_CFG_DBC0_ENABLE_ECCenable
PRI_HMC_CFG_DBC1_ENABLE_ECCenable
PRI_HMC_CFG_DBC2_ENABLE_ECCenable
PRI_HMC_CFG_DBC3_ENABLE_ECCenable
PRI_HMC_CFG_REORDER_DATAenable
PRI_HMC_CFG_REORDER_READdisable
PRI_HMC_CFG_CTRL_REORDER_RDATAdisable
PRI_HMC_CFG_DBC0_REORDER_RDATAdisable
PRI_HMC_CFG_DBC1_REORDER_RDATAdisable
PRI_HMC_CFG_DBC2_REORDER_RDATAdisable
PRI_HMC_CFG_DBC3_REORDER_RDATAdisable
PRI_HMC_CFG_CTRL_SLOT_OFFSET2
PRI_HMC_CFG_DBC0_SLOT_OFFSET2
PRI_HMC_CFG_DBC1_SLOT_OFFSET2
PRI_HMC_CFG_DBC2_SLOT_OFFSET2
PRI_HMC_CFG_DBC3_SLOT_OFFSET2
PRI_HMC_CFG_CTRL_SLOT_ROTATE_ENctrl_disable
PRI_HMC_CFG_DBC0_SLOT_ROTATE_ENdbc0_disable
PRI_HMC_CFG_DBC1_SLOT_ROTATE_ENdbc1_disable
PRI_HMC_CFG_DBC2_SLOT_ROTATE_ENdbc2_disable
PRI_HMC_CFG_DBC3_SLOT_ROTATE_ENdbc3_disable
PRI_HMC_CFG_COL_CMD_SLOT2
PRI_HMC_CFG_ROW_CMD_SLOT1
PRI_HMC_CFG_ROW_TO_COL_OFFSET-1
PRI_HMC_CFG_ROW_TO_ROW_OFFSET0
PRI_HMC_CFG_COL_TO_COL_OFFSET0
PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET0
PRI_HMC_CFG_COL_TO_ROW_OFFSET1
PRI_HMC_CFG_SIDEBAND_OFFSET1
PRI_HMC_CFG_CS_TO_CHIP_MAPPING33825
PRI_HMC_CFG_CTL_ODT_ENABLED1
PRI_HMC_CFG_RD_ODT_ON4
PRI_HMC_CFG_RD_ODT_PERIOD7
PRI_HMC_CFG_READ_ODT_CHIP0
PRI_HMC_CFG_WR_ODT_ON0
PRI_HMC_CFG_WR_ODT_PERIOD6
PRI_HMC_CFG_WRITE_ODT_CHIP0
PRI_HMC_CFG_CMD_FIFO_RESERVE_ENenable
PRI_HMC_CFG_RB_RESERVED_ENTRY8
PRI_HMC_CFG_WB_RESERVED_ENTRY52
PRI_HMC_CFG_STARVE_LIMIT10
PRI_HMC_CFG_PHY_DELAY_MISMATCH0
PRI_HMC_CFG_DQSTRK_ENdisable
PRI_HMC_CFG_DQSTRK_TO_VALID4
PRI_HMC_CFG_DQSTRK_TO_VALID_LAST26
PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN0
PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_ENdisable
PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL0
PRI_HMC_CFG_SHORT_DQSTRK_CTRL_ENdisable
PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD0
PRI_HMC_CFG_USER_RFSH_ENdisable
PRI_HMC_CFG_GEAR_DOWN_ENdisable
PRI_HMC_CFG_MEM_AUTO_PD_CYCLES0
PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC15
PRI_HMC_MEMCLKGATE_SETTING0
PRI_HMC_CFG_TCL21
PRI_HMC_CFG_16_ACT_TO_ACT0
PRI_HMC_CFG_4_ACT_TO_ACT12
PRI_HMC_MEM_IF_AL0
PRI_HMC_MEM_IF_CS_PER_DIMM0
PRI_HMC_MEM_IF_RD_PREAMBLE0
PRI_HMC_MEM_IF_TCCD0
PRI_HMC_MEM_IF_TCCD_S0
PRI_HMC_MEM_IF_TCKESR0
PRI_HMC_MEM_IF_TCKSRX0
PRI_HMC_MEM_IF_TCL0
PRI_HMC_MEM_IF_TCWL0
PRI_HMC_MEM_IF_TDQSCKMAX0
PRI_HMC_MEM_IF_TFAW0
PRI_HMC_MEM_IF_TMOD0
PRI_HMC_MEM_IF_TPL0
PRI_HMC_MEM_IF_TRAS0
PRI_HMC_MEM_IF_TRC0
PRI_HMC_MEM_IF_TRCD0
PRI_HMC_MEM_IF_TREFI0
PRI_HMC_MEM_IF_TRFC0
PRI_HMC_MEM_IF_TRP0
PRI_HMC_MEM_IF_TRRD0
PRI_HMC_MEM_IF_TRRD_S0
PRI_HMC_MEM_IF_TRTP0
PRI_HMC_MEM_IF_TWR0
PRI_HMC_MEM_IF_TWR_CRC_DM0
PRI_HMC_MEM_IF_TWTR0
PRI_HMC_MEM_IF_TWTR_L_CRC_DM0
PRI_HMC_MEM_IF_TWTR_S0
PRI_HMC_MEM_IF_TWTR_S_CRC_DM0
PRI_HMC_MEM_IF_TXP0
PRI_HMC_MEM_IF_TXPDLL0
PRI_HMC_MEM_IF_TXSR0
PRI_HMC_MEM_IF_TZQCS0
PRI_HMC_MEM_IF_TZQOPER0
PRI_HMC_MEM_IF_WR_CRC0
PRI_HMC_MEM_IF_WR_PREAMBLE0
PRI_HMC_CFG_ACT_TO_ACT28
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK3
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG2
PRI_HMC_CFG_ACT_TO_PCH20
PRI_HMC_CFG_ACT_TO_RDWR8
PRI_HMC_CFG_ARF_PERIOD4681
PRI_HMC_CFG_ARF_TO_VALID211
PRI_HMC_CFG_MMR_CMD_TO_VALID16
PRI_HMC_CFG_MPR_TO_VALID16
PRI_HMC_CFG_MPS_DQSTRK_DISABLEdisable
PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS6
PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE5
PRI_HMC_CFG_MPS_TO_VALID768
PRI_HMC_CFG_MPS_ZQCAL_DISABLEdisable
PRI_HMC_CFG_MRR_TO_VALID0
PRI_HMC_CFG_MRS_TO_VALID12
PRI_HMC_CFG_PCH_ALL_TO_VALID9
PRI_HMC_CFG_PCH_TO_VALID9
PRI_HMC_CFG_PDN_PERIOD0
PRI_HMC_CFG_PDN_TO_VALID5
PRI_HMC_CFG_POWER_SAVING_EXIT_CYC3
PRI_HMC_CFG_RD_AP_TO_VALID14
PRI_HMC_CFG_RD_TO_PCH5
PRI_HMC_CFG_RD_TO_RD3
PRI_HMC_CFG_RD_TO_RD_DIFF_BG2
PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP4
PRI_HMC_CFG_RD_TO_WR10
PRI_HMC_CFG_RD_TO_WR_DIFF_BG10
PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP10
PRI_HMC_CFG_RFSH_WARN_THRESHOLD0
PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY0
PRI_HMC_CFG_RLD3_REFRESH_SEQ00
PRI_HMC_CFG_RLD3_REFRESH_SEQ10
PRI_HMC_CFG_RLD3_REFRESH_SEQ20
PRI_HMC_CFG_RLD3_REFRESH_SEQ30
PRI_HMC_CFG_SB_CG_DISABLEdisable
PRI_HMC_CFG_SB_DDR4_MR3197632
PRI_HMC_CFG_SB_DDR4_MR4264192
PRI_HMC_CFG_SB_DDR4_MR55216
PRI_HMC_CFG_DDR4_MPS_ADDRMIRRORdisable
PRI_HMC_CFG_SRF_AUTOEXIT_ENdisable
PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK0
PRI_HMC_CFG_SRF_TO_VALID513
PRI_HMC_CFG_SRF_TO_ZQ_CAL385
PRI_HMC_CFG_SRF_ZQCAL_DISABLEdisable
PRI_HMC_TEMP_4_ACT_TO_ACT0
PRI_HMC_TEMP_RD_TO_RD_DIFF_BG0
PRI_HMC_TEMP_WR_TO_RD0
PRI_HMC_TEMP_WR_TO_RD_DIFF_BG0
PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP0
PRI_HMC_TEMP_WR_TO_WR_DIFF_BG0
PRI_HMC_CFG_WR_AP_TO_VALID28
PRI_HMC_CFG_WR_TO_PCH20
PRI_HMC_CFG_WR_TO_RD19
PRI_HMC_CFG_WR_TO_RD_DIFF_BG17
PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP15
PRI_HMC_CFG_WR_TO_WR3
PRI_HMC_CFG_WR_TO_WR_DIFF_BG2
PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP3
PRI_HMC_CFG_ZQCL_TO_VALID257
PRI_HMC_CFG_ZQCS_TO_VALID127
PRI_HMC_CHIP_ID273
PRI_HMC_CID_ADDR_WIDTH0
PRI_HMC_3DS_ENdisable
PRI_HMC_3DS_LR_NUM00
PRI_HMC_3DS_LR_NUM10
PRI_HMC_3DS_LR_NUM20
PRI_HMC_3DS_LR_NUM30
PRI_HMC_3DS_PR_STAG_ENABLEdisable
PRI_HMC_3DS_REF2REF_DLR1
PRI_HMC_3DSREF_ACK_ON_DONEdisable
PRI_HMC_CFG_MAJOR_MODE_ENdisable
PRI_HMC_CFG_REFRESH_TYPE0
PRI_HMC_CFG_PRE_REFRESH_ENdisable
PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT1
PRI_HMC_CFG_POST_REFRESH_ENenable
PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT0
PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT2
SEC_HMC_CFG_PING_PONG_MODEpingpong_off
SEC_HMC_CFG_CS_ADDR_WIDTHcs_width_0
SEC_HMC_CFG_COL_ADDR_WIDTHcol_width_10
SEC_HMC_CFG_ROW_ADDR_WIDTHrow_width_16
SEC_HMC_CFG_BANK_ADDR_WIDTHbank_width_2
SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTHbank_group_width_2
SEC_HMC_CFG_ADDR_ORDERaddr_order_cs_row_ba_col
SEC_HMC_CFG_ARBITER_TYPEarbiter_type_2t
SEC_HMC_CFG_OPEN_PAGE_ENdisable
SEC_HMC_CFG_CTRL_ENABLE_RCenable
SEC_HMC_CFG_DBC0_ENABLE_RCenable
SEC_HMC_CFG_DBC1_ENABLE_RCenable
SEC_HMC_CFG_DBC2_ENABLE_RCenable
SEC_HMC_CFG_DBC3_ENABLE_RCenable
SEC_HMC_CFG_CTRL_ENABLE_ECCenable
SEC_HMC_CFG_DBC0_ENABLE_ECCenable
SEC_HMC_CFG_DBC1_ENABLE_ECCenable
SEC_HMC_CFG_DBC2_ENABLE_ECCenable
SEC_HMC_CFG_DBC3_ENABLE_ECCenable
SEC_HMC_CFG_REORDER_DATAenable
SEC_HMC_CFG_REORDER_READdisable
SEC_HMC_CFG_CTRL_REORDER_RDATAdisable
SEC_HMC_CFG_DBC0_REORDER_RDATAdisable
SEC_HMC_CFG_DBC1_REORDER_RDATAdisable
SEC_HMC_CFG_DBC2_REORDER_RDATAdisable
SEC_HMC_CFG_DBC3_REORDER_RDATAdisable
SEC_HMC_CFG_CTRL_SLOT_OFFSET2
SEC_HMC_CFG_DBC0_SLOT_OFFSET2
SEC_HMC_CFG_DBC1_SLOT_OFFSET2
SEC_HMC_CFG_DBC2_SLOT_OFFSET2
SEC_HMC_CFG_DBC3_SLOT_OFFSET2
SEC_HMC_CFG_CTRL_SLOT_ROTATE_ENctrl_disable
SEC_HMC_CFG_DBC0_SLOT_ROTATE_ENdbc0_disable
SEC_HMC_CFG_DBC1_SLOT_ROTATE_ENdbc1_disable
SEC_HMC_CFG_DBC2_SLOT_ROTATE_ENdbc2_disable
SEC_HMC_CFG_DBC3_SLOT_ROTATE_ENdbc3_disable
SEC_HMC_CFG_COL_CMD_SLOT2
SEC_HMC_CFG_ROW_CMD_SLOT1
SEC_HMC_CFG_ROW_TO_COL_OFFSET-1
SEC_HMC_CFG_ROW_TO_ROW_OFFSET0
SEC_HMC_CFG_COL_TO_COL_OFFSET0
SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET0
SEC_HMC_CFG_COL_TO_ROW_OFFSET1
SEC_HMC_CFG_SIDEBAND_OFFSET1
SEC_HMC_CFG_CS_TO_CHIP_MAPPING33825
SEC_HMC_CFG_CTL_ODT_ENABLED1
SEC_HMC_CFG_RD_ODT_ON4
SEC_HMC_CFG_RD_ODT_PERIOD7
SEC_HMC_CFG_READ_ODT_CHIP0
SEC_HMC_CFG_WR_ODT_ON0
SEC_HMC_CFG_WR_ODT_PERIOD6
SEC_HMC_CFG_WRITE_ODT_CHIP0
SEC_HMC_CFG_CMD_FIFO_RESERVE_ENenable
SEC_HMC_CFG_RB_RESERVED_ENTRY8
SEC_HMC_CFG_WB_RESERVED_ENTRY52
SEC_HMC_CFG_STARVE_LIMIT10
SEC_HMC_CFG_PHY_DELAY_MISMATCH0
SEC_HMC_CFG_DQSTRK_ENdisable
SEC_HMC_CFG_DQSTRK_TO_VALID4
SEC_HMC_CFG_DQSTRK_TO_VALID_LAST26
SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN0
SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_ENdisable
SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL0
SEC_HMC_CFG_SHORT_DQSTRK_CTRL_ENdisable
SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD0
SEC_HMC_CFG_USER_RFSH_ENdisable
SEC_HMC_CFG_GEAR_DOWN_ENdisable
SEC_HMC_CFG_MEM_AUTO_PD_CYCLES0
SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC15
SEC_HMC_MEMCLKGATE_SETTING0
SEC_HMC_CFG_TCL21
SEC_HMC_CFG_16_ACT_TO_ACT0
SEC_HMC_CFG_4_ACT_TO_ACT12
SEC_HMC_MEM_IF_AL0
SEC_HMC_MEM_IF_CS_PER_DIMM0
SEC_HMC_MEM_IF_RD_PREAMBLE0
SEC_HMC_MEM_IF_TCCD0
SEC_HMC_MEM_IF_TCCD_S0
SEC_HMC_MEM_IF_TCKESR0
SEC_HMC_MEM_IF_TCKSRX0
SEC_HMC_MEM_IF_TCL0
SEC_HMC_MEM_IF_TCWL0
SEC_HMC_MEM_IF_TDQSCKMAX0
SEC_HMC_MEM_IF_TFAW0
SEC_HMC_MEM_IF_TMOD0
SEC_HMC_MEM_IF_TPL0
SEC_HMC_MEM_IF_TRAS0
SEC_HMC_MEM_IF_TRC0
SEC_HMC_MEM_IF_TRCD0
SEC_HMC_MEM_IF_TREFI0
SEC_HMC_MEM_IF_TRFC0
SEC_HMC_MEM_IF_TRP0
SEC_HMC_MEM_IF_TRRD0
SEC_HMC_MEM_IF_TRRD_S0
SEC_HMC_MEM_IF_TRTP0
SEC_HMC_MEM_IF_TWR0
SEC_HMC_MEM_IF_TWR_CRC_DM0
SEC_HMC_MEM_IF_TWTR0
SEC_HMC_MEM_IF_TWTR_L_CRC_DM0
SEC_HMC_MEM_IF_TWTR_S0
SEC_HMC_MEM_IF_TWTR_S_CRC_DM0
SEC_HMC_MEM_IF_TXP0
SEC_HMC_MEM_IF_TXPDLL0
SEC_HMC_MEM_IF_TXSR0
SEC_HMC_MEM_IF_TZQCS0
SEC_HMC_MEM_IF_TZQOPER0
SEC_HMC_MEM_IF_WR_CRC0
SEC_HMC_MEM_IF_WR_PREAMBLE0
SEC_HMC_CFG_ACT_TO_ACT28
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK3
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG2
SEC_HMC_CFG_ACT_TO_PCH20
SEC_HMC_CFG_ACT_TO_RDWR8
SEC_HMC_CFG_ARF_PERIOD4681
SEC_HMC_CFG_ARF_TO_VALID211
SEC_HMC_CFG_MMR_CMD_TO_VALID16
SEC_HMC_CFG_MPR_TO_VALID16
SEC_HMC_CFG_MPS_DQSTRK_DISABLEdisable
SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS6
SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE5
SEC_HMC_CFG_MPS_TO_VALID768
SEC_HMC_CFG_MPS_ZQCAL_DISABLEdisable
SEC_HMC_CFG_MRR_TO_VALID0
SEC_HMC_CFG_MRS_TO_VALID12
SEC_HMC_CFG_PCH_ALL_TO_VALID9
SEC_HMC_CFG_PCH_TO_VALID9
SEC_HMC_CFG_PDN_PERIOD0
SEC_HMC_CFG_PDN_TO_VALID5
SEC_HMC_CFG_POWER_SAVING_EXIT_CYC3
SEC_HMC_CFG_RD_AP_TO_VALID14
SEC_HMC_CFG_RD_TO_PCH5
SEC_HMC_CFG_RD_TO_RD3
SEC_HMC_CFG_RD_TO_RD_DIFF_BG2
SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP4
SEC_HMC_CFG_RD_TO_WR10
SEC_HMC_CFG_RD_TO_WR_DIFF_BG10
SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP10
SEC_HMC_CFG_RFSH_WARN_THRESHOLD0
SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY0
SEC_HMC_CFG_RLD3_REFRESH_SEQ00
SEC_HMC_CFG_RLD3_REFRESH_SEQ10
SEC_HMC_CFG_RLD3_REFRESH_SEQ20
SEC_HMC_CFG_RLD3_REFRESH_SEQ30
SEC_HMC_CFG_SB_CG_DISABLEdisable
SEC_HMC_CFG_SB_DDR4_MR3197632
SEC_HMC_CFG_SB_DDR4_MR4264192
SEC_HMC_CFG_SB_DDR4_MR55216
SEC_HMC_CFG_DDR4_MPS_ADDRMIRRORdisable
SEC_HMC_CFG_SRF_AUTOEXIT_ENdisable
SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK0
SEC_HMC_CFG_SRF_TO_VALID513
SEC_HMC_CFG_SRF_TO_ZQ_CAL385
SEC_HMC_CFG_SRF_ZQCAL_DISABLEdisable
SEC_HMC_TEMP_4_ACT_TO_ACT0
SEC_HMC_TEMP_RD_TO_RD_DIFF_BG0
SEC_HMC_TEMP_WR_TO_RD0
SEC_HMC_TEMP_WR_TO_RD_DIFF_BG0
SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP0
SEC_HMC_TEMP_WR_TO_WR_DIFF_BG0
SEC_HMC_CFG_WR_AP_TO_VALID28
SEC_HMC_CFG_WR_TO_PCH20
SEC_HMC_CFG_WR_TO_RD19
SEC_HMC_CFG_WR_TO_RD_DIFF_BG17
SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP15
SEC_HMC_CFG_WR_TO_WR3
SEC_HMC_CFG_WR_TO_WR_DIFF_BG2
SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP3
SEC_HMC_CFG_ZQCL_TO_VALID257
SEC_HMC_CFG_ZQCS_TO_VALID127
SEC_HMC_CHIP_ID273
SEC_HMC_CID_ADDR_WIDTH0
SEC_HMC_3DS_ENdisable
SEC_HMC_3DS_LR_NUM00
SEC_HMC_3DS_LR_NUM10
SEC_HMC_3DS_LR_NUM20
SEC_HMC_3DS_LR_NUM30
SEC_HMC_3DS_PR_STAG_ENABLEdisable
SEC_HMC_3DS_REF2REF_DLR1
SEC_HMC_3DSREF_ACK_ON_DONEdisable
SEC_HMC_CFG_MAJOR_MODE_ENdisable
SEC_HMC_CFG_REFRESH_TYPE0
SEC_HMC_CFG_PRE_REFRESH_ENdisable
SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT1
SEC_HMC_CFG_POST_REFRESH_ENenable
SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT0
SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT2
PINS_PER_LANE12
LANES_PER_TILE4
OCT_CONTROL_WIDTH16
PORT_MEM_CK_WIDTH1
PORT_MEM_CK_PINLOC_057345
PORT_MEM_CK_PINLOC_10
PORT_MEM_CK_PINLOC_20
PORT_MEM_CK_PINLOC_30
PORT_MEM_CK_PINLOC_40
PORT_MEM_CK_PINLOC_50
PORT_MEM_CK_PINLOC_AUTOGEN_WCNT6
PORT_MEM_CK_N_WIDTH1
PORT_MEM_CK_N_PINLOC_058369
PORT_MEM_CK_N_PINLOC_10
PORT_MEM_CK_N_PINLOC_20
PORT_MEM_CK_N_PINLOC_30
PORT_MEM_CK_N_PINLOC_40
PORT_MEM_CK_N_PINLOC_50
PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_CK_BIDIR_WIDTH1
PORT_MEM_CK_BIDIR_PINLOC_00
PORT_MEM_CK_BIDIR_PINLOC_10
PORT_MEM_CK_BIDIR_PINLOC_20
PORT_MEM_CK_BIDIR_PINLOC_30
PORT_MEM_CK_BIDIR_PINLOC_40
PORT_MEM_CK_BIDIR_PINLOC_50
PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT6
PORT_MEM_CK_BIDIR_N_WIDTH1
PORT_MEM_CK_BIDIR_N_PINLOC_00
PORT_MEM_CK_BIDIR_N_PINLOC_10
PORT_MEM_CK_BIDIR_N_PINLOC_20
PORT_MEM_CK_BIDIR_N_PINLOC_30
PORT_MEM_CK_BIDIR_N_PINLOC_40
PORT_MEM_CK_BIDIR_N_PINLOC_50
PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_DK_WIDTH1
PORT_MEM_DK_PINLOC_00
PORT_MEM_DK_PINLOC_10
PORT_MEM_DK_PINLOC_20
PORT_MEM_DK_PINLOC_30
PORT_MEM_DK_PINLOC_40
PORT_MEM_DK_PINLOC_50
PORT_MEM_DK_PINLOC_AUTOGEN_WCNT6
PORT_MEM_DK_N_WIDTH1
PORT_MEM_DK_N_PINLOC_00
PORT_MEM_DK_N_PINLOC_10
PORT_MEM_DK_N_PINLOC_20
PORT_MEM_DK_N_PINLOC_30
PORT_MEM_DK_N_PINLOC_40
PORT_MEM_DK_N_PINLOC_50
PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_DKA_WIDTH1
PORT_MEM_DKA_PINLOC_00
PORT_MEM_DKA_PINLOC_10
PORT_MEM_DKA_PINLOC_20
PORT_MEM_DKA_PINLOC_30
PORT_MEM_DKA_PINLOC_40
PORT_MEM_DKA_PINLOC_50
PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT6
PORT_MEM_DKA_N_WIDTH1
PORT_MEM_DKA_N_PINLOC_00
PORT_MEM_DKA_N_PINLOC_10
PORT_MEM_DKA_N_PINLOC_20
PORT_MEM_DKA_N_PINLOC_30
PORT_MEM_DKA_N_PINLOC_40
PORT_MEM_DKA_N_PINLOC_50
PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_DKB_WIDTH1
PORT_MEM_DKB_PINLOC_00
PORT_MEM_DKB_PINLOC_10
PORT_MEM_DKB_PINLOC_20
PORT_MEM_DKB_PINLOC_30
PORT_MEM_DKB_PINLOC_40
PORT_MEM_DKB_PINLOC_50
PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT6
PORT_MEM_DKB_N_WIDTH1
PORT_MEM_DKB_N_PINLOC_00
PORT_MEM_DKB_N_PINLOC_10
PORT_MEM_DKB_N_PINLOC_20
PORT_MEM_DKB_N_PINLOC_30
PORT_MEM_DKB_N_PINLOC_40
PORT_MEM_DKB_N_PINLOC_50
PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_K_WIDTH1
PORT_MEM_K_PINLOC_00
PORT_MEM_K_PINLOC_10
PORT_MEM_K_PINLOC_20
PORT_MEM_K_PINLOC_30
PORT_MEM_K_PINLOC_40
PORT_MEM_K_PINLOC_50
PORT_MEM_K_PINLOC_AUTOGEN_WCNT6
PORT_MEM_K_N_WIDTH1
PORT_MEM_K_N_PINLOC_00
PORT_MEM_K_N_PINLOC_10
PORT_MEM_K_N_PINLOC_20
PORT_MEM_K_N_PINLOC_30
PORT_MEM_K_N_PINLOC_40
PORT_MEM_K_N_PINLOC_50
PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_A_WIDTH17
PORT_MEM_A_PINLOC_064024593
PORT_MEM_A_PINLOC_167173438
PORT_MEM_A_PINLOC_270322241
PORT_MEM_A_PINLOC_373471044
PORT_MEM_A_PINLOC_479768647
PORT_MEM_A_PINLOC_582917453
PORT_MEM_A_PINLOC_60
PORT_MEM_A_PINLOC_70
PORT_MEM_A_PINLOC_80
PORT_MEM_A_PINLOC_90
PORT_MEM_A_PINLOC_100
PORT_MEM_A_PINLOC_110
PORT_MEM_A_PINLOC_120
PORT_MEM_A_PINLOC_130
PORT_MEM_A_PINLOC_140
PORT_MEM_A_PINLOC_150
PORT_MEM_A_PINLOC_160
PORT_MEM_A_PINLOC_AUTOGEN_WCNT17
PORT_MEM_BA_WIDTH2
PORT_MEM_BA_PINLOC_086066178
PORT_MEM_BA_PINLOC_10
PORT_MEM_BA_PINLOC_20
PORT_MEM_BA_PINLOC_30
PORT_MEM_BA_PINLOC_40
PORT_MEM_BA_PINLOC_50
PORT_MEM_BA_PINLOC_AUTOGEN_WCNT6
PORT_MEM_BG_WIDTH2
PORT_MEM_BG_PINLOC_050416642
PORT_MEM_BG_PINLOC_10
PORT_MEM_BG_PINLOC_20
PORT_MEM_BG_PINLOC_30
PORT_MEM_BG_PINLOC_40
PORT_MEM_BG_PINLOC_50
PORT_MEM_BG_PINLOC_AUTOGEN_WCNT6
PORT_MEM_C_WIDTH1
PORT_MEM_C_PINLOC_00
PORT_MEM_C_PINLOC_10
PORT_MEM_C_PINLOC_20
PORT_MEM_C_PINLOC_30
PORT_MEM_C_PINLOC_40
PORT_MEM_C_PINLOC_50
PORT_MEM_C_PINLOC_AUTOGEN_WCNT6
PORT_MEM_CKE_WIDTH1
PORT_MEM_CKE_PINLOC_055297
PORT_MEM_CKE_PINLOC_10
PORT_MEM_CKE_PINLOC_20
PORT_MEM_CKE_PINLOC_30
PORT_MEM_CKE_PINLOC_40
PORT_MEM_CKE_PINLOC_50
PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT6
PORT_MEM_CS_N_WIDTH1
PORT_MEM_CS_N_PINLOC_051201
PORT_MEM_CS_N_PINLOC_10
PORT_MEM_CS_N_PINLOC_20
PORT_MEM_CS_N_PINLOC_30
PORT_MEM_CS_N_PINLOC_40
PORT_MEM_CS_N_PINLOC_50
PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_RM_WIDTH1
PORT_MEM_RM_PINLOC_00
PORT_MEM_RM_PINLOC_10
PORT_MEM_RM_PINLOC_20
PORT_MEM_RM_PINLOC_30
PORT_MEM_RM_PINLOC_40
PORT_MEM_RM_PINLOC_50
PORT_MEM_RM_PINLOC_AUTOGEN_WCNT6
PORT_MEM_ODT_WIDTH1
PORT_MEM_ODT_PINLOC_053249
PORT_MEM_ODT_PINLOC_10
PORT_MEM_ODT_PINLOC_20
PORT_MEM_ODT_PINLOC_30
PORT_MEM_ODT_PINLOC_40
PORT_MEM_ODT_PINLOC_50
PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT6
PORT_MEM_REQ_N_WIDTH1
PORT_MEM_REQ_N_PINLOC_00
PORT_MEM_REQ_N_PINLOC_10
PORT_MEM_REQ_N_PINLOC_20
PORT_MEM_REQ_N_PINLOC_30
PORT_MEM_REQ_N_PINLOC_40
PORT_MEM_REQ_N_PINLOC_50
PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_GNT_N_WIDTH1
PORT_MEM_GNT_N_PINLOC_00
PORT_MEM_GNT_N_PINLOC_10
PORT_MEM_GNT_N_PINLOC_20
PORT_MEM_GNT_N_PINLOC_30
PORT_MEM_GNT_N_PINLOC_40
PORT_MEM_GNT_N_PINLOC_50
PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_ERR_N_WIDTH1
PORT_MEM_ERR_N_PINLOC_00
PORT_MEM_ERR_N_PINLOC_10
PORT_MEM_ERR_N_PINLOC_20
PORT_MEM_ERR_N_PINLOC_30
PORT_MEM_ERR_N_PINLOC_40
PORT_MEM_ERR_N_PINLOC_50
PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_RAS_N_WIDTH1
PORT_MEM_RAS_N_PINLOC_00
PORT_MEM_RAS_N_PINLOC_10
PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_CAS_N_WIDTH1
PORT_MEM_CAS_N_PINLOC_00
PORT_MEM_CAS_N_PINLOC_10
PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_WE_N_WIDTH1
PORT_MEM_WE_N_PINLOC_00
PORT_MEM_WE_N_PINLOC_10
PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_RESET_N_WIDTH1
PORT_MEM_RESET_N_PINLOC_050177
PORT_MEM_RESET_N_PINLOC_10
PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_ACT_N_WIDTH1
PORT_MEM_ACT_N_PINLOC_052225
PORT_MEM_ACT_N_PINLOC_10
PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_PAR_WIDTH1
PORT_MEM_PAR_PINLOC_060417
PORT_MEM_PAR_PINLOC_10
PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT2
PORT_MEM_CA_WIDTH1
PORT_MEM_CA_PINLOC_00
PORT_MEM_CA_PINLOC_10
PORT_MEM_CA_PINLOC_20
PORT_MEM_CA_PINLOC_30
PORT_MEM_CA_PINLOC_40
PORT_MEM_CA_PINLOC_50
PORT_MEM_CA_PINLOC_60
PORT_MEM_CA_PINLOC_70
PORT_MEM_CA_PINLOC_80
PORT_MEM_CA_PINLOC_90
PORT_MEM_CA_PINLOC_100
PORT_MEM_CA_PINLOC_110
PORT_MEM_CA_PINLOC_120
PORT_MEM_CA_PINLOC_130
PORT_MEM_CA_PINLOC_140
PORT_MEM_CA_PINLOC_150
PORT_MEM_CA_PINLOC_160
PORT_MEM_CA_PINLOC_AUTOGEN_WCNT17
PORT_MEM_REF_N_WIDTH1
PORT_MEM_REF_N_PINLOC_00
PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_WPS_N_WIDTH1
PORT_MEM_WPS_N_PINLOC_00
PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_RPS_N_WIDTH1
PORT_MEM_RPS_N_PINLOC_00
PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_DOFF_N_WIDTH1
PORT_MEM_DOFF_N_PINLOC_00
PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_LDA_N_WIDTH1
PORT_MEM_LDA_N_PINLOC_00
PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_LDB_N_WIDTH1
PORT_MEM_LDB_N_PINLOC_00
PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_RWA_N_WIDTH1
PORT_MEM_RWA_N_PINLOC_00
PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_RWB_N_WIDTH1
PORT_MEM_RWB_N_PINLOC_00
PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_LBK0_N_WIDTH1
PORT_MEM_LBK0_N_PINLOC_00
PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_LBK1_N_WIDTH1
PORT_MEM_LBK1_N_PINLOC_00
PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_CFG_N_WIDTH1
PORT_MEM_CFG_N_PINLOC_00
PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT1
PORT_MEM_AP_WIDTH1
PORT_MEM_AP_PINLOC_00
PORT_MEM_AP_PINLOC_AUTOGEN_WCNT1
PORT_MEM_AINV_WIDTH1
PORT_MEM_AINV_PINLOC_00
PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT1
PORT_MEM_DM_WIDTH1
PORT_MEM_DM_PINLOC_00
PORT_MEM_DM_PINLOC_10
PORT_MEM_DM_PINLOC_20
PORT_MEM_DM_PINLOC_30
PORT_MEM_DM_PINLOC_40
PORT_MEM_DM_PINLOC_50
PORT_MEM_DM_PINLOC_60
PORT_MEM_DM_PINLOC_70
PORT_MEM_DM_PINLOC_80
PORT_MEM_DM_PINLOC_90
PORT_MEM_DM_PINLOC_100
PORT_MEM_DM_PINLOC_110
PORT_MEM_DM_PINLOC_120
PORT_MEM_DM_PINLOC_AUTOGEN_WCNT13
PORT_MEM_BWS_N_WIDTH1
PORT_MEM_BWS_N_PINLOC_00
PORT_MEM_BWS_N_PINLOC_10
PORT_MEM_BWS_N_PINLOC_20
PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT3
PORT_MEM_D_WIDTH1
PORT_MEM_D_PINLOC_00
PORT_MEM_D_PINLOC_10
PORT_MEM_D_PINLOC_20
PORT_MEM_D_PINLOC_30
PORT_MEM_D_PINLOC_40
PORT_MEM_D_PINLOC_50
PORT_MEM_D_PINLOC_60
PORT_MEM_D_PINLOC_70
PORT_MEM_D_PINLOC_80
PORT_MEM_D_PINLOC_90
PORT_MEM_D_PINLOC_100
PORT_MEM_D_PINLOC_110
PORT_MEM_D_PINLOC_120
PORT_MEM_D_PINLOC_130
PORT_MEM_D_PINLOC_140
PORT_MEM_D_PINLOC_150
PORT_MEM_D_PINLOC_160
PORT_MEM_D_PINLOC_170
PORT_MEM_D_PINLOC_180
PORT_MEM_D_PINLOC_190
PORT_MEM_D_PINLOC_200
PORT_MEM_D_PINLOC_210
PORT_MEM_D_PINLOC_220
PORT_MEM_D_PINLOC_230
PORT_MEM_D_PINLOC_240
PORT_MEM_D_PINLOC_250
PORT_MEM_D_PINLOC_260
PORT_MEM_D_PINLOC_270
PORT_MEM_D_PINLOC_280
PORT_MEM_D_PINLOC_290
PORT_MEM_D_PINLOC_300
PORT_MEM_D_PINLOC_310
PORT_MEM_D_PINLOC_320
PORT_MEM_D_PINLOC_330
PORT_MEM_D_PINLOC_340
PORT_MEM_D_PINLOC_350
PORT_MEM_D_PINLOC_360
PORT_MEM_D_PINLOC_370
PORT_MEM_D_PINLOC_380
PORT_MEM_D_PINLOC_390
PORT_MEM_D_PINLOC_400
PORT_MEM_D_PINLOC_410
PORT_MEM_D_PINLOC_420
PORT_MEM_D_PINLOC_430
PORT_MEM_D_PINLOC_440
PORT_MEM_D_PINLOC_450
PORT_MEM_D_PINLOC_460
PORT_MEM_D_PINLOC_470
PORT_MEM_D_PINLOC_480
PORT_MEM_D_PINLOC_AUTOGEN_WCNT49
PORT_MEM_DQ_WIDTH72
PORT_MEM_DQ_PINLOC_01048648
PORT_MEM_DQ_PINLOC_18391682
PORT_MEM_DQ_PINLOC_211544585
PORT_MEM_DQ_PINLOC_314693388
PORT_MEM_DQ_PINLOC_422040591
PORT_MEM_DQ_PINLOC_525189398
PORT_MEM_DQ_PINLOC_628338201
PORT_MEM_DQ_PINLOC_735685408
PORT_MEM_DQ_PINLOC_838834211
PORT_MEM_DQ_PINLOC_946177318
PORT_MEM_DQ_PINLOC_1049330221
PORT_MEM_DQ_PINLOC_11102859872
PORT_MEM_DQ_PINLOC_12110207075
PORT_MEM_DQ_PINLOC_13113355882
PORT_MEM_DQ_PINLOC_14116504685
PORT_MEM_DQ_PINLOC_15123851892
PORT_MEM_DQ_PINLOC_16127000695
PORT_MEM_DQ_PINLOC_17134343802
PORT_MEM_DQ_PINLOC_18137496705
PORT_MEM_DQ_PINLOC_19140645508
PORT_MEM_DQ_PINLOC_20147992711
PORT_MEM_DQ_PINLOC_21151141518
PORT_MEM_DQ_PINLOC_22154290321
PORT_MEM_DQ_PINLOC_23161637528
PORT_MEM_DQ_PINLOC_24155
PORT_MEM_DQ_PINLOC_250
PORT_MEM_DQ_PINLOC_260
PORT_MEM_DQ_PINLOC_270
PORT_MEM_DQ_PINLOC_280
PORT_MEM_DQ_PINLOC_290
PORT_MEM_DQ_PINLOC_300
PORT_MEM_DQ_PINLOC_310
PORT_MEM_DQ_PINLOC_320
PORT_MEM_DQ_PINLOC_330
PORT_MEM_DQ_PINLOC_340
PORT_MEM_DQ_PINLOC_350
PORT_MEM_DQ_PINLOC_360
PORT_MEM_DQ_PINLOC_370
PORT_MEM_DQ_PINLOC_380
PORT_MEM_DQ_PINLOC_390
PORT_MEM_DQ_PINLOC_400
PORT_MEM_DQ_PINLOC_410
PORT_MEM_DQ_PINLOC_420
PORT_MEM_DQ_PINLOC_430
PORT_MEM_DQ_PINLOC_440
PORT_MEM_DQ_PINLOC_450
PORT_MEM_DQ_PINLOC_460
PORT_MEM_DQ_PINLOC_470
PORT_MEM_DQ_PINLOC_480
PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT49
PORT_MEM_DBI_N_WIDTH9
PORT_MEM_DBI_N_PINLOC_018880521
PORT_MEM_DBI_N_PINLOC_1106997790
PORT_MEM_DBI_N_PINLOC_2144832626
PORT_MEM_DBI_N_PINLOC_3150
PORT_MEM_DBI_N_PINLOC_40
PORT_MEM_DBI_N_PINLOC_50
PORT_MEM_DBI_N_PINLOC_60
PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT7
PORT_MEM_DQA_WIDTH1
PORT_MEM_DQA_PINLOC_00
PORT_MEM_DQA_PINLOC_10
PORT_MEM_DQA_PINLOC_20
PORT_MEM_DQA_PINLOC_30
PORT_MEM_DQA_PINLOC_40
PORT_MEM_DQA_PINLOC_50
PORT_MEM_DQA_PINLOC_60
PORT_MEM_DQA_PINLOC_70
PORT_MEM_DQA_PINLOC_80
PORT_MEM_DQA_PINLOC_90
PORT_MEM_DQA_PINLOC_100
PORT_MEM_DQA_PINLOC_110
PORT_MEM_DQA_PINLOC_120
PORT_MEM_DQA_PINLOC_130
PORT_MEM_DQA_PINLOC_140
PORT_MEM_DQA_PINLOC_150
PORT_MEM_DQA_PINLOC_160
PORT_MEM_DQA_PINLOC_170
PORT_MEM_DQA_PINLOC_180
PORT_MEM_DQA_PINLOC_190
PORT_MEM_DQA_PINLOC_200
PORT_MEM_DQA_PINLOC_210
PORT_MEM_DQA_PINLOC_220
PORT_MEM_DQA_PINLOC_230
PORT_MEM_DQA_PINLOC_240
PORT_MEM_DQA_PINLOC_250
PORT_MEM_DQA_PINLOC_260
PORT_MEM_DQA_PINLOC_270
PORT_MEM_DQA_PINLOC_280
PORT_MEM_DQA_PINLOC_290
PORT_MEM_DQA_PINLOC_300
PORT_MEM_DQA_PINLOC_310
PORT_MEM_DQA_PINLOC_320
PORT_MEM_DQA_PINLOC_330
PORT_MEM_DQA_PINLOC_340
PORT_MEM_DQA_PINLOC_350
PORT_MEM_DQA_PINLOC_360
PORT_MEM_DQA_PINLOC_370
PORT_MEM_DQA_PINLOC_380
PORT_MEM_DQA_PINLOC_390
PORT_MEM_DQA_PINLOC_400
PORT_MEM_DQA_PINLOC_410
PORT_MEM_DQA_PINLOC_420
PORT_MEM_DQA_PINLOC_430
PORT_MEM_DQA_PINLOC_440
PORT_MEM_DQA_PINLOC_450
PORT_MEM_DQA_PINLOC_460
PORT_MEM_DQA_PINLOC_470
PORT_MEM_DQA_PINLOC_480
PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT49
PORT_MEM_DQB_WIDTH1
PORT_MEM_DQB_PINLOC_00
PORT_MEM_DQB_PINLOC_10
PORT_MEM_DQB_PINLOC_20
PORT_MEM_DQB_PINLOC_30
PORT_MEM_DQB_PINLOC_40
PORT_MEM_DQB_PINLOC_50
PORT_MEM_DQB_PINLOC_60
PORT_MEM_DQB_PINLOC_70
PORT_MEM_DQB_PINLOC_80
PORT_MEM_DQB_PINLOC_90
PORT_MEM_DQB_PINLOC_100
PORT_MEM_DQB_PINLOC_110
PORT_MEM_DQB_PINLOC_120
PORT_MEM_DQB_PINLOC_130
PORT_MEM_DQB_PINLOC_140
PORT_MEM_DQB_PINLOC_150
PORT_MEM_DQB_PINLOC_160
PORT_MEM_DQB_PINLOC_170
PORT_MEM_DQB_PINLOC_180
PORT_MEM_DQB_PINLOC_190
PORT_MEM_DQB_PINLOC_200
PORT_MEM_DQB_PINLOC_210
PORT_MEM_DQB_PINLOC_220
PORT_MEM_DQB_PINLOC_230
PORT_MEM_DQB_PINLOC_240
PORT_MEM_DQB_PINLOC_250
PORT_MEM_DQB_PINLOC_260
PORT_MEM_DQB_PINLOC_270
PORT_MEM_DQB_PINLOC_280
PORT_MEM_DQB_PINLOC_290
PORT_MEM_DQB_PINLOC_300
PORT_MEM_DQB_PINLOC_310
PORT_MEM_DQB_PINLOC_320
PORT_MEM_DQB_PINLOC_330
PORT_MEM_DQB_PINLOC_340
PORT_MEM_DQB_PINLOC_350
PORT_MEM_DQB_PINLOC_360
PORT_MEM_DQB_PINLOC_370
PORT_MEM_DQB_PINLOC_380
PORT_MEM_DQB_PINLOC_390
PORT_MEM_DQB_PINLOC_400
PORT_MEM_DQB_PINLOC_410
PORT_MEM_DQB_PINLOC_420
PORT_MEM_DQB_PINLOC_430
PORT_MEM_DQB_PINLOC_440
PORT_MEM_DQB_PINLOC_450
PORT_MEM_DQB_PINLOC_460
PORT_MEM_DQB_PINLOC_470
PORT_MEM_DQB_PINLOC_480
PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT49
PORT_MEM_DINVA_WIDTH1
PORT_MEM_DINVA_PINLOC_00
PORT_MEM_DINVA_PINLOC_10
PORT_MEM_DINVA_PINLOC_20
PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT3
PORT_MEM_DINVB_WIDTH1
PORT_MEM_DINVB_PINLOC_00
PORT_MEM_DINVB_PINLOC_10
PORT_MEM_DINVB_PINLOC_20
PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT3
PORT_MEM_Q_WIDTH1
PORT_MEM_Q_PINLOC_00
PORT_MEM_Q_PINLOC_10
PORT_MEM_Q_PINLOC_20
PORT_MEM_Q_PINLOC_30
PORT_MEM_Q_PINLOC_40
PORT_MEM_Q_PINLOC_50
PORT_MEM_Q_PINLOC_60
PORT_MEM_Q_PINLOC_70
PORT_MEM_Q_PINLOC_80
PORT_MEM_Q_PINLOC_90
PORT_MEM_Q_PINLOC_100
PORT_MEM_Q_PINLOC_110
PORT_MEM_Q_PINLOC_120
PORT_MEM_Q_PINLOC_130
PORT_MEM_Q_PINLOC_140
PORT_MEM_Q_PINLOC_150
PORT_MEM_Q_PINLOC_160
PORT_MEM_Q_PINLOC_170
PORT_MEM_Q_PINLOC_180
PORT_MEM_Q_PINLOC_190
PORT_MEM_Q_PINLOC_200
PORT_MEM_Q_PINLOC_210
PORT_MEM_Q_PINLOC_220
PORT_MEM_Q_PINLOC_230
PORT_MEM_Q_PINLOC_240
PORT_MEM_Q_PINLOC_250
PORT_MEM_Q_PINLOC_260
PORT_MEM_Q_PINLOC_270
PORT_MEM_Q_PINLOC_280
PORT_MEM_Q_PINLOC_290
PORT_MEM_Q_PINLOC_300
PORT_MEM_Q_PINLOC_310
PORT_MEM_Q_PINLOC_320
PORT_MEM_Q_PINLOC_330
PORT_MEM_Q_PINLOC_340
PORT_MEM_Q_PINLOC_350
PORT_MEM_Q_PINLOC_360
PORT_MEM_Q_PINLOC_370
PORT_MEM_Q_PINLOC_380
PORT_MEM_Q_PINLOC_390
PORT_MEM_Q_PINLOC_400
PORT_MEM_Q_PINLOC_410
PORT_MEM_Q_PINLOC_420
PORT_MEM_Q_PINLOC_430
PORT_MEM_Q_PINLOC_440
PORT_MEM_Q_PINLOC_450
PORT_MEM_Q_PINLOC_460
PORT_MEM_Q_PINLOC_470
PORT_MEM_Q_PINLOC_480
PORT_MEM_Q_PINLOC_AUTOGEN_WCNT49
PORT_MEM_DQS_WIDTH9
PORT_MEM_DQS_PINLOC_016781321
PORT_MEM_DQS_PINLOC_1104898588
PORT_MEM_DQS_PINLOC_2142733424
PORT_MEM_DQS_PINLOC_3148
PORT_MEM_DQS_PINLOC_40
PORT_MEM_DQS_PINLOC_50
PORT_MEM_DQS_PINLOC_60
PORT_MEM_DQS_PINLOC_70
PORT_MEM_DQS_PINLOC_80
PORT_MEM_DQS_PINLOC_90
PORT_MEM_DQS_PINLOC_100
PORT_MEM_DQS_PINLOC_110
PORT_MEM_DQS_PINLOC_120
PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT13
PORT_MEM_DQS_N_WIDTH9
PORT_MEM_DQS_N_PINLOC_017830921
PORT_MEM_DQS_N_PINLOC_1105948189
PORT_MEM_DQS_N_PINLOC_2143783025
PORT_MEM_DQS_N_PINLOC_3149
PORT_MEM_DQS_N_PINLOC_40
PORT_MEM_DQS_N_PINLOC_50
PORT_MEM_DQS_N_PINLOC_60
PORT_MEM_DQS_N_PINLOC_70
PORT_MEM_DQS_N_PINLOC_80
PORT_MEM_DQS_N_PINLOC_90
PORT_MEM_DQS_N_PINLOC_100
PORT_MEM_DQS_N_PINLOC_110
PORT_MEM_DQS_N_PINLOC_120
PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT13
PORT_MEM_QK_WIDTH1
PORT_MEM_QK_PINLOC_00
PORT_MEM_QK_PINLOC_10
PORT_MEM_QK_PINLOC_20
PORT_MEM_QK_PINLOC_30
PORT_MEM_QK_PINLOC_40
PORT_MEM_QK_PINLOC_50
PORT_MEM_QK_PINLOC_AUTOGEN_WCNT6
PORT_MEM_QK_N_WIDTH1
PORT_MEM_QK_N_PINLOC_00
PORT_MEM_QK_N_PINLOC_10
PORT_MEM_QK_N_PINLOC_20
PORT_MEM_QK_N_PINLOC_30
PORT_MEM_QK_N_PINLOC_40
PORT_MEM_QK_N_PINLOC_50
PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_QKA_WIDTH1
PORT_MEM_QKA_PINLOC_00
PORT_MEM_QKA_PINLOC_10
PORT_MEM_QKA_PINLOC_20
PORT_MEM_QKA_PINLOC_30
PORT_MEM_QKA_PINLOC_40
PORT_MEM_QKA_PINLOC_50
PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT6
PORT_MEM_QKA_N_WIDTH1
PORT_MEM_QKA_N_PINLOC_00
PORT_MEM_QKA_N_PINLOC_10
PORT_MEM_QKA_N_PINLOC_20
PORT_MEM_QKA_N_PINLOC_30
PORT_MEM_QKA_N_PINLOC_40
PORT_MEM_QKA_N_PINLOC_50
PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_QKB_WIDTH1
PORT_MEM_QKB_PINLOC_00
PORT_MEM_QKB_PINLOC_10
PORT_MEM_QKB_PINLOC_20
PORT_MEM_QKB_PINLOC_30
PORT_MEM_QKB_PINLOC_40
PORT_MEM_QKB_PINLOC_50
PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT6
PORT_MEM_QKB_N_WIDTH1
PORT_MEM_QKB_N_PINLOC_00
PORT_MEM_QKB_N_PINLOC_10
PORT_MEM_QKB_N_PINLOC_20
PORT_MEM_QKB_N_PINLOC_30
PORT_MEM_QKB_N_PINLOC_40
PORT_MEM_QKB_N_PINLOC_50
PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT6
PORT_MEM_CQ_WIDTH1
PORT_MEM_CQ_PINLOC_00
PORT_MEM_CQ_PINLOC_10
PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT2
PORT_MEM_CQ_N_WIDTH1
PORT_MEM_CQ_N_PINLOC_00
PORT_MEM_CQ_N_PINLOC_10
PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_ALERT_N_WIDTH1
PORT_MEM_ALERT_N_PINLOC_094209
PORT_MEM_ALERT_N_PINLOC_10
PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT2
PORT_MEM_PE_N_WIDTH1
PORT_MEM_PE_N_PINLOC_00
PORT_MEM_PE_N_PINLOC_10
PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT2
PORT_CLKS_SHARING_MASTER_OUT_WIDTH32
PORT_CLKS_SHARING_SLAVE_IN_WIDTH32
PORT_CLKS_SHARING_SLAVE_OUT_WIDTH32
PORT_AFI_RLAT_WIDTH6
PORT_AFI_WLAT_WIDTH6
PORT_AFI_SEQ_BUSY_WIDTH4
PORT_AFI_ADDR_WIDTH1
PORT_AFI_BA_WIDTH1
PORT_AFI_BG_WIDTH1
PORT_AFI_C_WIDTH1
PORT_AFI_CKE_WIDTH1
PORT_AFI_CS_N_WIDTH1
PORT_AFI_RM_WIDTH1
PORT_AFI_ODT_WIDTH1
PORT_AFI_RAS_N_WIDTH1
PORT_AFI_CAS_N_WIDTH1
PORT_AFI_WE_N_WIDTH1
PORT_AFI_RST_N_WIDTH1
PORT_AFI_ACT_N_WIDTH1
PORT_AFI_REQ_N_WIDTH1
PORT_AFI_GNT_N_WIDTH1
PORT_AFI_ERR_N_WIDTH1
PORT_AFI_PAR_WIDTH1
PORT_AFI_CA_WIDTH1
PORT_AFI_REF_N_WIDTH1
PORT_AFI_WPS_N_WIDTH1
PORT_AFI_RPS_N_WIDTH1
PORT_AFI_DOFF_N_WIDTH1
PORT_AFI_LD_N_WIDTH1
PORT_AFI_RW_N_WIDTH1
PORT_AFI_LBK0_N_WIDTH1
PORT_AFI_LBK1_N_WIDTH1
PORT_AFI_CFG_N_WIDTH1
PORT_AFI_AP_WIDTH1
PORT_AFI_AINV_WIDTH1
PORT_AFI_DM_WIDTH1
PORT_AFI_DM_N_WIDTH1
PORT_AFI_BWS_N_WIDTH1
PORT_AFI_RDATA_DBI_N_WIDTH1
PORT_AFI_WDATA_DBI_N_WIDTH1
PORT_AFI_RDATA_DINV_WIDTH1
PORT_AFI_WDATA_DINV_WIDTH1
PORT_AFI_DQS_BURST_WIDTH1
PORT_AFI_WDATA_VALID_WIDTH1
PORT_AFI_WDATA_WIDTH1
PORT_AFI_RDATA_EN_FULL_WIDTH1
PORT_AFI_RDATA_WIDTH1
PORT_AFI_RDATA_VALID_WIDTH1
PORT_AFI_RRANK_WIDTH1
PORT_AFI_WRANK_WIDTH1
PORT_AFI_ALERT_N_WIDTH1
PORT_AFI_PE_N_WIDTH1
PORT_CTRL_AST_CMD_DATA_WIDTH61
PORT_CTRL_AST_WR_DATA_WIDTH648
PORT_CTRL_AST_RD_DATA_WIDTH576
PORT_CTRL_AMM_ADDRESS_WIDTH1
PORT_CTRL_AMM_RDATA_WIDTH1
PORT_CTRL_AMM_WDATA_WIDTH1
PORT_CTRL_AMM_BCOUNT_WIDTH1
PORT_CTRL_AMM_BYTEEN_WIDTH1
PORT_CTRL_STROBE_WIDTH1
PORT_CTRL_STROBE_OE_WIDTH1
PORT_CTRL_DATA_OE_WIDTH1
PORT_CTRL_DATA_OUT_WIDTH1
PORT_CTRL_DATA_IN_WIDTH1
PORT_CTRL_RDATA_VALID_WIDTH1
PORT_CTRL_LOCKED_WIDTH1
PORT_CTRL_RDATA_ENABLE_WIDTH1
PORT_CTRL_USER_REFRESH_REQ_WIDTH4
PORT_CTRL_USER_REFRESH_BANK_WIDTH16
PORT_CTRL_SELF_REFRESH_REQ_WIDTH4
PORT_CTRL_ECC_WRITE_INFO_WIDTH15
PORT_CTRL_ECC_RDATA_ID_WIDTH13
PORT_CTRL_ECC_READ_INFO_WIDTH3
PORT_CTRL_ECC_CMD_INFO_WIDTH3
PORT_CTRL_ECC_WB_POINTER_WIDTH12
PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH10
PORT_CTRL_MMR_SLAVE_RDATA_WIDTH32
PORT_CTRL_MMR_SLAVE_WDATA_WIDTH32
PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH2
PORT_HPS_EMIF_H2E_WIDTH4096
PORT_HPS_EMIF_E2H_WIDTH4096
PORT_HPS_EMIF_H2E_GP_WIDTH2
PORT_HPS_EMIF_E2H_GP_WIDTH1
PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH9
PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH8
PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH8
PORT_DFT_ND_PLL_CNTSEL_WIDTH4
PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH3
PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH4
PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH2
PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH2
PORT_CALBUS_ADDRESS_WIDTH20
PORT_CALBUS_WDATA_WIDTH32
PORT_CALBUS_RDATA_WIDTH32
PORT_CALBUS_SEQ_PARAM_TBL_WIDTH4096
PLL_VCO_FREQ_MHZ_INT1200
PLL_VCO_TO_MEM_CLK_FREQ_RATIO1
PLL_MEM_CLK_FREQ_PS834
PLL_PHY_CLK_VCO_PHASE0
PLL_VCO_FREQ_PS_STR834 ps
PLL_VCO_FREQ_MHZ_STR1200 MHz
PLL_REF_CLK_FREQ_PS_STR30024 ps
PLL_REF_CLK_FREQ_MHZ_STR33.333 MHz
PLL_REF_CLK_FREQ_PS30024
PLL_SIM_VCO_FREQ_PS840
PLL_SIM_PHYCLK_0_FREQ_PS1680
PLL_SIM_PHYCLK_1_FREQ_PS3360
PLL_SIM_PHYCLK_FB_FREQ_PS3360
PLL_SIM_PHY_CLK_VCO_PHASE_PS0
PLL_M_CNT_HIGH18
PLL_M_CNT_LOW18
PLL_N_CNT_HIGH256
PLL_N_CNT_LOW256
PLL_M_CNT_BYPASS_ENfalse
PLL_N_CNT_BYPASS_ENtrue
PLL_M_CNT_EVEN_DUTY_ENfalse
PLL_N_CNT_EVEN_DUTY_ENfalse
PLL_FBCLK_MUX_1pll_fbclk_mux_1_glb
PLL_FBCLK_MUX_2pll_fbclk_mux_2_m_cnt
PLL_M_CNT_IN_SRCc_m_cnt_in_src_ph_mux_clk
PLL_CP_SETTINGpll_cp_setting12
PLL_BW_CTRLpll_bw_res_setting4
PLL_BW_SELhigh
PLL_C_CNT_HIGH_02
PLL_C_CNT_LOW_02
PLL_C_CNT_PRST_01
PLL_C_CNT_PH_MUX_PRST_00
PLL_C_CNT_BYPASS_EN_0false
PLL_C_CNT_EVEN_DUTY_EN_0false
PLL_C_CNT_FREQ_PS_STR_03336 ps
PLL_C_CNT_FREQ_MHZ_STR_0300.0 MHz
PLL_C_CNT_PHASE_PS_STR_00 ps
PLL_C_CNT_DUTY_CYCLE_050
PLL_C_CNT_OUT_EN_0true
PLL_C_CNT_HIGH_11
PLL_C_CNT_LOW_11
PLL_C_CNT_PRST_11
PLL_C_CNT_PH_MUX_PRST_10
PLL_C_CNT_BYPASS_EN_1false
PLL_C_CNT_EVEN_DUTY_EN_1false
PLL_C_CNT_FREQ_PS_STR_11668 ps
PLL_C_CNT_FREQ_MHZ_STR_1600.0 MHz
PLL_C_CNT_PHASE_PS_STR_10 ps
PLL_C_CNT_DUTY_CYCLE_150
PLL_C_CNT_OUT_EN_1true
PLL_C_CNT_HIGH_22
PLL_C_CNT_LOW_22
PLL_C_CNT_PRST_21
PLL_C_CNT_PH_MUX_PRST_20
PLL_C_CNT_BYPASS_EN_2false
PLL_C_CNT_EVEN_DUTY_EN_2false
PLL_C_CNT_FREQ_PS_STR_23336 ps
PLL_C_CNT_FREQ_MHZ_STR_2300.0 MHz
PLL_C_CNT_PHASE_PS_STR_20 ps
PLL_C_CNT_DUTY_CYCLE_250
PLL_C_CNT_OUT_EN_2true
PLL_C_CNT_HIGH_31
PLL_C_CNT_LOW_31
PLL_C_CNT_PRST_31
PLL_C_CNT_PH_MUX_PRST_30
PLL_C_CNT_BYPASS_EN_3false
PLL_C_CNT_EVEN_DUTY_EN_3false
PLL_C_CNT_FREQ_PS_STR_31668 ps
PLL_C_CNT_FREQ_MHZ_STR_3600.0 MHz
PLL_C_CNT_PHASE_PS_STR_30 ps
PLL_C_CNT_DUTY_CYCLE_350
PLL_C_CNT_OUT_EN_3true
PLL_C_CNT_HIGH_42
PLL_C_CNT_LOW_42
PLL_C_CNT_PRST_41
PLL_C_CNT_PH_MUX_PRST_40
PLL_C_CNT_BYPASS_EN_4false
PLL_C_CNT_EVEN_DUTY_EN_4false
PLL_C_CNT_FREQ_PS_STR_43336 ps
PLL_C_CNT_FREQ_MHZ_STR_4300.0 MHz
PLL_C_CNT_PHASE_PS_STR_40 ps
PLL_C_CNT_DUTY_CYCLE_450
PLL_C_CNT_OUT_EN_4true
PLL_C_CNT_HIGH_5256
PLL_C_CNT_LOW_5256
PLL_C_CNT_PRST_51
PLL_C_CNT_PH_MUX_PRST_50
PLL_C_CNT_BYPASS_EN_5true
PLL_C_CNT_EVEN_DUTY_EN_5false
PLL_C_CNT_FREQ_PS_STR_50 ps
PLL_C_CNT_FREQ_MHZ_STR_50.0 MHz
PLL_C_CNT_PHASE_PS_STR_50 ps
PLL_C_CNT_DUTY_CYCLE_550
PLL_C_CNT_OUT_EN_5false
PLL_C_CNT_HIGH_6256
PLL_C_CNT_LOW_6256
PLL_C_CNT_PRST_61
PLL_C_CNT_PH_MUX_PRST_60
PLL_C_CNT_BYPASS_EN_6true
PLL_C_CNT_EVEN_DUTY_EN_6false
PLL_C_CNT_FREQ_PS_STR_60 ps
PLL_C_CNT_FREQ_MHZ_STR_60.0 MHz
PLL_C_CNT_PHASE_PS_STR_60 ps
PLL_C_CNT_DUTY_CYCLE_650
PLL_C_CNT_OUT_EN_6false
PLL_C_CNT_HIGH_7256
PLL_C_CNT_LOW_7256
PLL_C_CNT_PRST_71
PLL_C_CNT_PH_MUX_PRST_70
PLL_C_CNT_BYPASS_EN_7true
PLL_C_CNT_EVEN_DUTY_EN_7false
PLL_C_CNT_FREQ_PS_STR_70 ps
PLL_C_CNT_FREQ_MHZ_STR_70.0 MHz
PLL_C_CNT_PHASE_PS_STR_70 ps
PLL_C_CNT_DUTY_CYCLE_750
PLL_C_CNT_OUT_EN_7false
PLL_C_CNT_HIGH_8256
PLL_C_CNT_LOW_8256
PLL_C_CNT_PRST_81
PLL_C_CNT_PH_MUX_PRST_80
PLL_C_CNT_BYPASS_EN_8true
PLL_C_CNT_EVEN_DUTY_EN_8false
PLL_C_CNT_FREQ_PS_STR_80 ps
PLL_C_CNT_FREQ_MHZ_STR_80.0 MHz
PLL_C_CNT_PHASE_PS_STR_80 ps
PLL_C_CNT_DUTY_CYCLE_850
PLL_C_CNT_OUT_EN_8false
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

emif_fm_0_ecc_core

altera_emif_ecc v19.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ emif_fm_0_arch + emif_usr_clk  emif_fm_0_ecc_core
  emif_usr_clk_in
emif_usr_reset_n  
  emif_usr_reset_n_in
ctrl_ast_rd_0  
  ctrl_ast_rd_0
ctrl_ecc_0   + emif_fm_0_arch +
  ctrl_ecc_0
ctrl_ast_cmd_0  
  ctrl_ast_cmd_0
ctrl_ast_wr_0  
  ctrl_ast_wr_0
+
+
+
+ + + + +
+

Parameters

+ + + + + +
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.05 seconds
+ + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.qgsynthc b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.qgsynthc new file mode 100644 index 0000000000..c3bd6d398b --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.qgsynthc @@ -0,0 +1,45277 @@ + + + ed_synth_emif_fm_0 + + + + ed_synth_emif_fm_0 + 1.0 + ed_synth_emif_fm_0 + ed_synth_emif_fm_0 + 0 + + + + + emif_fm_0 + + + + BOARD_DDR3_AC_ISI_NS + 0.0 + + + BOARD_DDR3_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_DDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDR3_TDH_DERATING_PS + 0 + + + BOARD_DDR3_TDS_DERATING_PS + 0 + + + BOARD_DDR3_TIH_DERATING_PS + 0 + + + BOARD_DDR3_TIS_DERATING_PS + 0 + + + BOARD_DDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR3_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_ISI_NS + 0.15 + + + BOARD_DDR4_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_RCLK_ISI_NS + 0.15 + + + BOARD_DDR4_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_RDATA_ISI_NS + 0.12 + + + BOARD_DDR4_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR4_SKEW_WITHIN_AC_NS + 0.18 + + + BOARD_DDR4_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_TIH_DERATING_PS + 0 + + + BOARD_DDR4_TIS_DERATING_PS + 0 + + + BOARD_DDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR4_WCLK_ISI_NS + 0.06 + + + BOARD_DDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_WDATA_ISI_NS + 0.13 + + + BOARD_DDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_ISI_NS + 0.0 + + + BOARD_DDRT_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDRT_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDRT_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDRT_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDRT_TIH_DERATING_PS + 0 + + + BOARD_DDRT_TIS_DERATING_PS + 0 + + + BOARD_DDRT_USER_AC_ISI_NS + 0.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDRT_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_LPDDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_LPDDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_LPDDR3_TDH_DERATING_PS + 0 + + + BOARD_LPDDR3_TDS_DERATING_PS + 0 + + + BOARD_LPDDR3_TIH_DERATING_PS + 0 + + + BOARD_LPDDR3_TIS_DERATING_PS + 0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_LPDDR3_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_ISI_NS + 0.0 + + + BOARD_QDR2_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + 0.0 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + false + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + false + + + BOARD_QDR2_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + 0.6 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_D_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_Q_NS + 0.0 + + + BOARD_QDR2_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR2_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_ISI_NS + 0.0 + + + BOARD_QDR4_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + true + + + BOARD_QDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + 0.6 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_QDR4_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR4_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_QDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR4_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_ISI_NS + 0.0 + + + BOARD_RLD3_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + false + + + BOARD_RLD3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + 0.6 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_RLD3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_RLD3_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_RLD3_TDH_DERATING_PS + 0 + + + BOARD_RLD3_TDS_DERATING_PS + 0 + + + BOARD_RLD3_TIH_DERATING_PS + 0 + + + BOARD_RLD3_TIS_DERATING_PS + 0 + + + BOARD_RLD3_USER_AC_ISI_NS + 0.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_RLD3_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_WDATA_SLEW_RATE + 2.0 + + + CAL_DEBUG_CLOCK_FREQUENCY + 50000000 + + + CTRL_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR3_ECC_EN + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + true + + + CTRL_DDR3_ECC_STATUS_EN + false + + + CTRL_DDR3_MMR_EN + false + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_REORDER_EN + true + + + CTRL_DDR3_SELF_REFRESH_EN + false + + + CTRL_DDR3_STARVE_LIMIT + 10 + + + CTRL_DDR3_USER_PRIORITY_EN + false + + + CTRL_DDR3_USER_REFRESH_EN + false + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_ADDR_ORDER_ENUM + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + false + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR4_ECC_EN + true + + + CTRL_DDR4_ECC_READDATAERROR_EN + false + + + CTRL_DDR4_ECC_STATUS_EN + false + + + CTRL_DDR4_MAJOR_MODE_EN + false + + + CTRL_DDR4_MMR_EN + false + + + CTRL_DDR4_POST_REFRESH_EN + true + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + 1 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_REORDER_EN + true + + + CTRL_DDR4_SELF_REFRESH_EN + false + + + CTRL_DDR4_STARVE_LIMIT + 10 + + + CTRL_DDR4_USER_PRIORITY_EN + false + + + CTRL_DDR4_USER_REFRESH_EN + false + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ADDR_INTERLEAVING + COARSE + + + CTRL_DDRT_ADDR_ORDER_ENUM + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + false + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_AXIS_DATA_WIDTH + 512 + + + CTRL_DDRT_DIMM_DENSITY + 128 + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + false + + + CTRL_DDRT_DRIVER_MARGINING_EN + 0 + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDRT_ECC_EN + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + true + + + CTRL_DDRT_ECC_STATUS_EN + true + + + CTRL_DDRT_ERR_INJECT_EN + false + + + CTRL_DDRT_ERR_REPLAY_EN + false + + + CTRL_DDRT_EXT_ERR_INJECT_EN + false + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + false + + + CTRL_DDRT_MMR_EN + false + + + CTRL_DDRT_NUM_OF_AXIS_ID + 1 + + + CTRL_DDRT_PARITY_CMD_EN + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + false + + + CTRL_DDRT_POISON_DETECTION_EN + false + + + CTRL_DDRT_PORT_AFI_C_WIDTH + 2 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_REORDER_EN + true + + + CTRL_DDRT_SELF_REFRESH_EN + false + + + CTRL_DDRT_STARVE_LIMIT + 10 + + + CTRL_DDRT_UPI_EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + 8 + + + CTRL_DDRT_USER_PRIORITY_EN + false + + + CTRL_DDRT_USER_REFRESH_EN + false + + + CTRL_DDRT_WR_ACK_POLICY + POSTED + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ZQ_INTERVAL_MS + 3 + + + CTRL_ECC_EN + true + + + CTRL_ECC_READDATAERROR_EN + false + + + CTRL_ECC_STATUS_EN + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + false + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_MMR_EN + false + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_REORDER_EN + true + + + CTRL_LPDDR3_SELF_REFRESH_EN + false + + + CTRL_LPDDR3_STARVE_LIMIT + 10 + + + CTRL_LPDDR3_USER_PRIORITY_EN + false + + + CTRL_LPDDR3_USER_REFRESH_EN + false + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_MMR_EN + false + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC + 11 + + + CTRL_REORDER_EN + true + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_USER_PRIORITY_EN + false + + + DIAG_AC_PARITY_ERR + false + + + DIAG_ADD_READY_PIPELINE + true + + + DIAG_BOARD_DELAY_CONFIG_STR + + + + DIAG_DB_RESET_AUTO_RELEASE + avl_release + + + DIAG_DDR3_ABSTRACT_PHY + false + + + DIAG_DDR3_AC_PARITY_ERR + false + + + DIAG_DDR3_CAL_ADDR0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + 8 + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + false + + + DIAG_DDR3_CAL_ENABLE_NON_DES + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR3_CA_DESKEW_EN + true + + + DIAG_DDR3_CA_LEVEL_EN + true + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR3_ENABLE_USER_MODE + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR3_INTERFACE_ID + 0 + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR3_SIM_VERBOSE + true + + + DIAG_DDR3_TG2_TEST_DURATION + SHORT + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR3_USE_TG_AVL_2 + false + + + DIAG_DDR3_USE_TG_HBM + false + + + DIAG_DDR4_ABSTRACT_PHY + false + + + DIAG_DDR4_AC_PARITY_ERR + false + + + DIAG_DDR4_CAL_ADDR0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR4_ENABLE_USER_MODE + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR4_INTERFACE_ID + 0 + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR4_SIM_VERBOSE + true + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + false + + + DIAG_DDR4_SKIP_CA_DESKEW + false + + + DIAG_DDR4_SKIP_CA_LEVEL + false + + + DIAG_DDR4_SKIP_VREF_CAL + false + + + DIAG_DDR4_TG2_TEST_DURATION + SHORT + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR4_USE_TG_AVL_2 + false + + + DIAG_DDR4_USE_TG_HBM + false + + + DIAG_DDRT_ABSTRACT_PHY + false + + + DIAG_DDRT_AC_PARITY_ERR + false + + + DIAG_DDRT_CAL_ADDR0 + 0 + + + DIAG_DDRT_CAL_ADDR1 + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDRT_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDRT_EFF_TEST + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + false + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + false + + + DIAG_DDRT_ENABLE_USER_MODE + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDRT_INTERFACE_ID + 0 + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDRT_SIM_VERBOSE + true + + + DIAG_DDRT_SKIP_CA_DESKEW + false + + + DIAG_DDRT_SKIP_CA_LEVEL + false + + + DIAG_DDRT_SKIP_VREF_CAL + false + + + DIAG_DDRT_TG2_TEST_DURATION + SHORT + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + false + + + DIAG_DDRT_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDRT_USE_TG_AVL_2 + true + + + DIAG_DDRT_USE_TG_HBM + false + + + DIAG_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_ECLIPSE_DEBUG + false + + + DIAG_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_ENABLE_DEFAULT_MODE + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + false + + + DIAG_ENABLE_JTAG_UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + false + + + DIAG_ENABLE_SOFT_M20K + false + + + DIAG_ENABLE_USER_MODE + true + + + DIAG_EXPORT_PLL_LOCKED + true + + + DIAG_EXPORT_PLL_REF_CLK_OUT + false + + + DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_EXPORT_VJI + false + + + DIAG_EXPOSE_DFT_SIGNALS + false + + + DIAG_EXPOSE_EARLY_READY + false + + + DIAG_EXPOSE_RD_TYPE + false + + + DIAG_EXTRA_CONFIGS + + + + DIAG_EXT_DOCS + false + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + + + + DIAG_EX_DESIGN_ISSP_EN + true + + + DIAG_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_EX_DESIGN_SEPARATE_RESETS + false + + + DIAG_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_FAST_SIM + true + + + DIAG_FAST_SIM_OVERRIDE + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_HMC_HRC + auto + + + DIAG_INTERFACE_ID + 0 + + + DIAG_LPDDR3_ABSTRACT_PHY + false + + + DIAG_LPDDR3_AC_PARITY_ERR + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_LPDDR3_INTERFACE_ID + 0 + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_LPDDR3_SIM_VERBOSE + true + + + DIAG_LPDDR3_SKIP_CA_DESKEW + false + + + DIAG_LPDDR3_SKIP_CA_LEVEL + false + + + DIAG_LPDDR3_TG2_TEST_DURATION + SHORT + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_LPDDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_LPDDR3_USE_TG_AVL_2 + false + + + DIAG_LPDDR3_USE_TG_HBM + false + + + DIAG_QDR2_ABSTRACT_PHY + false + + + DIAG_QDR2_AC_PARITY_ERR + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR2_ENABLE_USER_MODE + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR2_INTERFACE_ID + 0 + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR2_SIM_VERBOSE + true + + + DIAG_QDR2_TG2_TEST_DURATION + SHORT + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR2_USE_TG_AVL_2 + false + + + DIAG_QDR2_USE_TG_HBM + false + + + DIAG_QDR4_ABSTRACT_PHY + false + + + DIAG_QDR4_AC_PARITY_ERR + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR4_ENABLE_USER_MODE + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR4_INTERFACE_ID + 0 + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR4_SIM_VERBOSE + true + + + DIAG_QDR4_SKIP_VREF_CAL + false + + + DIAG_QDR4_TG2_TEST_DURATION + SHORT + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR4_USE_TG_AVL_2 + false + + + DIAG_QDR4_USE_TG_HBM + false + + + DIAG_RLD2_ABSTRACT_PHY + false + + + DIAG_RLD2_AC_PARITY_ERR + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD2_ENABLE_USER_MODE + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD2_INTERFACE_ID + 0 + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD2_SIM_VERBOSE + true + + + DIAG_RLD2_TG2_TEST_DURATION + SHORT + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD2_USE_TG_AVL_2 + false + + + DIAG_RLD2_USE_TG_HBM + false + + + DIAG_RLD3_ABSTRACT_PHY + false + + + DIAG_RLD3_AC_PARITY_ERR + false + + + DIAG_RLD3_CA_DESKEW_EN + true + + + DIAG_RLD3_CA_LEVEL_EN + true + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD3_ENABLE_USER_MODE + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD3_INTERFACE_ID + 0 + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD3_SIM_VERBOSE + true + + + DIAG_RLD3_TG2_TEST_DURATION + SHORT + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD3_USE_TG_AVL_2 + false + + + DIAG_RLD3_USE_TG_HBM + false + + + DIAG_RS232_UART_BAUDRATE + 57600 + + + DIAG_SEQ_RESET_AUTO_RELEASE + avl + + + DIAG_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_SIM_CHECKER_SKIP_TG + false + + + DIAG_SIM_MEMORY_PRELOAD + false + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE + + + + DIAG_SIM_REGTEST_MODE + false + + + DIAG_SIM_VERBOSE_LEVEL + 5 + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + 100 + + + DIAG_SOFT_NIOS_MODE + SOFT_NIOS_MODE_DISABLED + + + DIAG_SYNTH_FOR_SIM + false + + + DIAG_TG2_TEST_DURATION + SHORT + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + 0 + + + DIAG_TIMING_REGTEST_MODE + false + + + DIAG_USE_ABSTRACT_PHY + false + + + DIAG_USE_BOARD_DELAY_MODEL + false + + + DIAG_USE_NEW_EFFMON_S10 + false + + + DIAG_USE_RS232_UART + false + + + DIAG_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_USE_TG_AVL_2 + false + + + DIAG_USE_TG_HBM + false + + + DIAG_VERBOSE_IOAUX + false + + + EMIF_0_CONN_TO_CALIP + CALIP_0 + + + EMIF_0_REF_CLK_SHARING + EXPORTED + + + EMIF_0_STORED_PARAM + + + + EMIF_10_CONN_TO_CALIP + CALIP_0 + + + EMIF_10_REF_CLK_SHARING + EXPORTED + + + EMIF_10_STORED_PARAM + + + + EMIF_11_CONN_TO_CALIP + CALIP_0 + + + EMIF_11_REF_CLK_SHARING + EXPORTED + + + EMIF_11_STORED_PARAM + + + + EMIF_12_CONN_TO_CALIP + CALIP_0 + + + EMIF_12_REF_CLK_SHARING + EXPORTED + + + EMIF_12_STORED_PARAM + + + + EMIF_13_CONN_TO_CALIP + CALIP_0 + + + EMIF_13_REF_CLK_SHARING + EXPORTED + + + EMIF_13_STORED_PARAM + + + + EMIF_14_CONN_TO_CALIP + CALIP_0 + + + EMIF_14_REF_CLK_SHARING + EXPORTED + + + EMIF_14_STORED_PARAM + + + + EMIF_15_CONN_TO_CALIP + CALIP_0 + + + EMIF_15_REF_CLK_SHARING + EXPORTED + + + EMIF_15_STORED_PARAM + + + + EMIF_1_CONN_TO_CALIP + CALIP_0 + + + EMIF_1_REF_CLK_SHARING + EXPORTED + + + EMIF_1_STORED_PARAM + + + + EMIF_2_CONN_TO_CALIP + CALIP_0 + + + EMIF_2_REF_CLK_SHARING + EXPORTED + + + EMIF_2_STORED_PARAM + + + + EMIF_3_CONN_TO_CALIP + CALIP_0 + + + EMIF_3_REF_CLK_SHARING + EXPORTED + + + EMIF_3_STORED_PARAM + + + + EMIF_4_CONN_TO_CALIP + CALIP_0 + + + EMIF_4_REF_CLK_SHARING + EXPORTED + + + EMIF_4_STORED_PARAM + + + + EMIF_5_CONN_TO_CALIP + CALIP_0 + + + EMIF_5_REF_CLK_SHARING + EXPORTED + + + EMIF_5_STORED_PARAM + + + + EMIF_6_CONN_TO_CALIP + CALIP_0 + + + EMIF_6_REF_CLK_SHARING + EXPORTED + + + EMIF_6_STORED_PARAM + + + + EMIF_7_CONN_TO_CALIP + CALIP_0 + + + EMIF_7_REF_CLK_SHARING + EXPORTED + + + EMIF_7_STORED_PARAM + + + + EMIF_8_CONN_TO_CALIP + CALIP_0 + + + EMIF_8_REF_CLK_SHARING + EXPORTED + + + EMIF_8_STORED_PARAM + + + + EMIF_9_CONN_TO_CALIP + CALIP_0 + + + EMIF_9_REF_CLK_SHARING + EXPORTED + + + EMIF_9_STORED_PARAM + + + + EX_DESIGN_GUI_DDR3_GEN_BSI + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + false + + + EX_DESIGN_GUI_DDR3_GEN_SIM + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_GEN_BSI + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + false + + + EX_DESIGN_GUI_DDR4_GEN_SIM + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_GEN_BSI + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + false + + + EX_DESIGN_GUI_DDRT_GEN_SIM + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_GEN_BSI + false + + + EX_DESIGN_GUI_GEN_CDC + false + + + EX_DESIGN_GUI_GEN_SIM + true + + + EX_DESIGN_GUI_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + false + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_GEN_BSI + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + false + + + EX_DESIGN_GUI_QDR2_GEN_SIM + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_GEN_BSI + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + false + + + EX_DESIGN_GUI_QDR4_GEN_SIM + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_GEN_BSI + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + false + + + EX_DESIGN_GUI_RLD2_GEN_SIM + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_GEN_BSI + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + false + + + EX_DESIGN_GUI_RLD3_GEN_SIM + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + FAMILY_ENUM + FAMILY_AGILEX + + + INTERNAL_TESTING_MODE + false + + + IS_ED_SLAVE + false + + + MEM_BURST_LENGTH + 8 + + + MEM_DATA_MASK_EN + true + + + MEM_DDR3_AC_PAR_EN + false + + + MEM_DDR3_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR3_ADDR_WIDTH + 1 + + + MEM_DDR3_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ASR_ENUM + DDR3_ASR_MANUAL + + + MEM_DDR3_ATCL_ENUM + DDR3_ATCL_DISABLED + + + MEM_DDR3_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_BL_ENUM + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_CFG_GEN_DBE + false + + + MEM_DDR3_CFG_GEN_SBE + false + + + MEM_DDR3_CKE_PER_DIMM + 1 + + + MEM_DDR3_CKE_WIDTH + 1 + + + MEM_DDR3_CK_WIDTH + 1 + + + MEM_DDR3_COL_ADDR_WIDTH + 10 + + + MEM_DDR3_CS_PER_DIMM + 1 + + + MEM_DDR3_CS_WIDTH + 1 + + + MEM_DDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR3_DLL_EN + true + + + MEM_DDR3_DM_EN + true + + + MEM_DDR3_DM_WIDTH + 1 + + + MEM_DDR3_DQS_WIDTH + 8 + + + MEM_DDR3_DQ_PER_DQS + 8 + + + MEM_DDR3_DQ_WIDTH + 72 + + + MEM_DDR3_DRV_STR_ENUM + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_FORMAT_ENUM + MEM_FORMAT_UDIMM + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + 000000000000000000 + + + MEM_DDR3_MIRROR_ADDRESSING_EN + true + + + MEM_DDR3_MR0 + 0 + + + MEM_DDR3_MR1 + 0 + + + MEM_DDR3_MR2 + 0 + + + MEM_DDR3_MR3 + 0 + + + MEM_DDR3_NUM_OF_DIMMS + 1 + + + MEM_DDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_ODT_WIDTH + 1 + + + MEM_DDR3_PD_ENUM + DDR3_PD_OFF + + + MEM_DDR3_RANKS_PER_DIMM + 1 + + + MEM_DDR3_RDIMM_CONFIG + 0000000000000000 + + + MEM_DDR3_RM_WIDTH + 0 + + + MEM_DDR3_ROW_ADDR_WIDTH + 15 + + + MEM_DDR3_RTT_NOM_ENUM + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_R_DERIVED_ODT0 + ,, + + + MEM_DDR3_R_DERIVED_ODT1 + ,, + + + MEM_DDR3_R_DERIVED_ODT2 + ,, + + + MEM_DDR3_R_DERIVED_ODT3 + ,, + + + MEM_DDR3_R_DERIVED_ODTN + ,, + + + MEM_DDR3_R_ODT0_1X1 + off + + + MEM_DDR3_R_ODT0_2X2 + off,off + + + MEM_DDR3_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR3_R_ODT1_2X2 + off,off + + + MEM_DDR3_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR3_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR3_R_ODTN_1X1 + Rank 0 + + + MEM_DDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR3_SPEEDBIN_ENUM + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_SRT_ENUM + DDR3_SRT_NORMAL + + + MEM_DDR3_TCL + 14 + + + MEM_DDR3_TDH_DC_MV + 100 + + + MEM_DDR3_TDH_PS + 55 + + + MEM_DDR3_TDQSCKDL + 1200 + + + MEM_DDR3_TDQSCKDM + 900 + + + MEM_DDR3_TDQSCKDS + 450 + + + MEM_DDR3_TDQSCK_DERV_PS + 2 + + + MEM_DDR3_TDQSCK_PS + 180 + + + MEM_DDR3_TDQSQ_PS + 75 + + + MEM_DDR3_TDQSS_CYC + 0.27 + + + MEM_DDR3_TDSH_CYC + 0.18 + + + MEM_DDR3_TDSS_CYC + 0.18 + + + MEM_DDR3_TDS_AC_MV + 135 + + + MEM_DDR3_TDS_PS + 53 + + + MEM_DDR3_TFAW_CYC + 27 + + + MEM_DDR3_TFAW_NS + 25.0 + + + MEM_DDR3_TIH_DC_MV + 100 + + + MEM_DDR3_TIH_PS + 95 + + + MEM_DDR3_TINIT_CK + 499 + + + MEM_DDR3_TINIT_US + 500 + + + MEM_DDR3_TIS_AC_MV + 135 + + + MEM_DDR3_TIS_PS + 60 + + + MEM_DDR3_TMRD_CK_CYC + 4 + + + MEM_DDR3_TQH_CYC + 0.38 + + + MEM_DDR3_TQSH_CYC + 0.4 + + + MEM_DDR3_TRAS_CYC + 36 + + + MEM_DDR3_TRAS_NS + 33.0 + + + MEM_DDR3_TRCD_CYC + 14 + + + MEM_DDR3_TRCD_NS + 13.09 + + + MEM_DDR3_TREFI_CYC + 8320 + + + MEM_DDR3_TREFI_US + 7.8 + + + MEM_DDR3_TRFC_CYC + 171 + + + MEM_DDR3_TRFC_NS + 160.0 + + + MEM_DDR3_TRP_CYC + 14 + + + MEM_DDR3_TRP_NS + 13.09 + + + MEM_DDR3_TRRD_CYC + 6 + + + MEM_DDR3_TRTP_CYC + 8 + + + MEM_DDR3_TTL_ADDR_WIDTH + 1 + + + MEM_DDR3_TTL_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_TTL_CKE_WIDTH + 1 + + + MEM_DDR3_TTL_CK_WIDTH + 1 + + + MEM_DDR3_TTL_CS_WIDTH + 1 + + + MEM_DDR3_TTL_DM_WIDTH + 1 + + + MEM_DDR3_TTL_DQS_WIDTH + 8 + + + MEM_DDR3_TTL_DQ_WIDTH + 72 + + + MEM_DDR3_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_TTL_ODT_WIDTH + 1 + + + MEM_DDR3_TTL_RM_WIDTH + 0 + + + MEM_DDR3_TWLH_PS + 125.0 + + + MEM_DDR3_TWLS_PS + 125.0 + + + MEM_DDR3_TWR_CYC + 16 + + + MEM_DDR3_TWR_NS + 15.0 + + + MEM_DDR3_TWTR_CYC + 8 + + + MEM_DDR3_USE_DEFAULT_ODT + true + + + MEM_DDR3_WTCL + 10 + + + MEM_DDR3_W_DERIVED_ODT0 + ,, + + + MEM_DDR3_W_DERIVED_ODT1 + ,, + + + MEM_DDR3_W_DERIVED_ODT2 + ,, + + + MEM_DDR3_W_DERIVED_ODT3 + ,, + + + MEM_DDR3_W_DERIVED_ODTN + ,, + + + MEM_DDR3_W_ODT0_1X1 + on + + + MEM_DDR3_W_ODT0_2X2 + on,off + + + MEM_DDR3_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT1_2X2 + off,on + + + MEM_DDR3_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR3_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR3_W_ODTN_1X1 + Rank 0 + + + MEM_DDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_AC_PARITY_LATENCY + DDR4_AC_PARITY_LATENCY_DISABLE + + + MEM_DDR4_AC_PERSISTENT_ERROR + false + + + MEM_DDR4_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR4_ADDR_WIDTH + 17 + + + MEM_DDR4_ALERT_N_AC_LANE + 3 + + + MEM_DDR4_ALERT_N_AC_PIN + 8 + + + MEM_DDR4_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + + + MEM_DDR4_ALERT_PAR_EN + true + + + MEM_DDR4_ASR_ENUM + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_ATCL_ENUM + DDR4_ATCL_DISABLED + + + MEM_DDR4_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_BL_ENUM + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_CAL_MODE + 0 + + + MEM_DDR4_CFG_GEN_DBE + false + + + MEM_DDR4_CFG_GEN_SBE + false + + + MEM_DDR4_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_CKE_PER_DIMM + 1 + + + MEM_DDR4_CKE_WIDTH + 1 + + + MEM_DDR4_CK_WIDTH + 1 + + + MEM_DDR4_COL_ADDR_WIDTH + 10 + + + MEM_DDR4_CS_PER_DIMM + 1 + + + MEM_DDR4_CS_WIDTH + 1 + + + MEM_DDR4_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR4_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DEFAULT_VREFOUT + true + + + MEM_DDR4_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR4_DLL_EN + true + + + MEM_DDR4_DM_EN + true + + + MEM_DDR4_DQS_WIDTH + 9 + + + MEM_DDR4_DQ_PER_DQS + 8 + + + MEM_DDR4_DQ_WIDTH + 72 + + + MEM_DDR4_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_DDR4_GEARDOWN + DDR4_GEARDOWN_HR + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR4_IDEAL_VREF_IN_PCT + 68.0 + + + MEM_DDR4_IDEAL_VREF_OUT_PCT + 70.0 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP + RTT_NOM disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP + RTT_PARK disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP + RZQ/3 (80 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM + DDR4_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP + ODT Disabled + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM + DDR4_RTT_PARK_RZQ_4 + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP + RZQ/4 (60 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP + Dynamic ODT off + + + MEM_DDR4_INTEL_DEFAULT_TERM + true + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDR4_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + + + + MEM_DDR4_MAX_POWERDOWN + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + true + + + MEM_DDR4_MPR_READ_FORMAT + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MR0 + 2164 + + + MEM_DDR4_MR1 + 65537 + + + MEM_DDR4_MR2 + 131112 + + + MEM_DDR4_MR3 + 197632 + + + MEM_DDR4_MR4 + 264192 + + + MEM_DDR4_MR5 + 332896 + + + MEM_DDR4_MR6 + 395279 + + + MEM_DDR4_NUM_OF_DIMMS + 1 + + + MEM_DDR4_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_ODT_IN_POWERDOWN + true + + + MEM_DDR4_ODT_WIDTH + 1 + + + MEM_DDR4_PER_DRAM_ADDR + false + + + MEM_DDR4_RANKS_PER_DIMM + 1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_COMMAND_LATENCY + 1 + + + MEM_DDR4_RCD_CS_IBT_ENUM + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_RCD_PARITY_CONTROL_WORD + 13 + + + MEM_DDR4_RDIMM_CONFIG + 00000020000000003900000D40030B0F556000 + + + MEM_DDR4_READ_DBI + true + + + MEM_DDR4_READ_PREAMBLE + 2 + + + MEM_DDR4_READ_PREAMBLE_TRAINING + false + + + MEM_DDR4_RM_WIDTH + 0 + + + MEM_DDR4_ROW_ADDR_WIDTH + 16 + + + MEM_DDR4_RTT_NOM_ENUM + DDR4_RTT_NOM_RZQ_4 + + + MEM_DDR4_RTT_PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_R_DERIVED_BODT0 + + + + MEM_DDR4_R_DERIVED_BODT1 + + + + MEM_DDR4_R_DERIVED_BODTN + + + + MEM_DDR4_R_DERIVED_ODT0 + (Drive) RZQ/7 (34 Ohm),-,-,- + + + MEM_DDR4_R_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_R_ODT0_1X1 + off + + + MEM_DDR4_R_ODT0_2X2 + off,off + + + MEM_DDR4_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR4_R_ODT1_2X2 + off,off + + + MEM_DDR4_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR4_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR4_R_ODTN_1X1 + Rank 0 + + + MEM_DDR4_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_SELF_RFSH_ABORT + false + + + MEM_DDR4_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR4_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDR4_SPD_135_RCD_REV + 0 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + 101 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDR4_SPD_139_DB_REV + 0 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + 0 + + + MEM_DDR4_SPEEDBIN_ENUM + DDR4_SPEEDBIN_2666 + + + MEM_DDR4_TCCD_L_CYC + 6 + + + MEM_DDR4_TCCD_S_CYC + 4 + + + MEM_DDR4_TCL + 21 + + + MEM_DDR4_TDIVW_DJ_CYC + 0.1 + + + MEM_DDR4_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDR4_TDQSCKDL + 1200 + + + MEM_DDR4_TDQSCKDM + 900 + + + MEM_DDR4_TDQSCKDS + 450 + + + MEM_DDR4_TDQSCK_DERV_PS + 2 + + + MEM_DDR4_TDQSCK_PS + 175 + + + MEM_DDR4_TDQSQ_PS + 66 + + + MEM_DDR4_TDQSQ_UI + 0.14 + + + MEM_DDR4_TDQSS_CYC + 0.27 + + + MEM_DDR4_TDSH_CYC + 0.18 + + + MEM_DDR4_TDSS_CYC + 0.18 + + + MEM_DDR4_TDVWP_UI + 0.72 + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_SENSOR_READOUT + false + + + MEM_DDR4_TFAW_CYC + 26 + + + MEM_DDR4_TFAW_DLR_CYC + 16 + + + MEM_DDR4_TFAW_NS + 21.0 + + + MEM_DDR4_TIH_DC_MV + 75 + + + MEM_DDR4_TIH_PS + 87 + + + MEM_DDR4_TINIT_CK + 600000 + + + MEM_DDR4_TINIT_US + 500 + + + MEM_DDR4_TIS_AC_MV + 100 + + + MEM_DDR4_TIS_PS + 62 + + + MEM_DDR4_TMRD_CK_CYC + 8 + + + MEM_DDR4_TQH_CYC + 0.38 + + + MEM_DDR4_TQH_UI + 0.74 + + + MEM_DDR4_TQSH_CYC + 0.4 + + + MEM_DDR4_TRAS_CYC + 39 + + + MEM_DDR4_TRAS_NS + 32.0 + + + MEM_DDR4_TRCD_CYC + 17 + + + MEM_DDR4_TRCD_NS + 14.16 + + + MEM_DDR4_TREFI_CYC + 9360 + + + MEM_DDR4_TREFI_US + 7.8 + + + MEM_DDR4_TRFC_CYC + 420 + + + MEM_DDR4_TRFC_DLR_CYC + 108 + + + MEM_DDR4_TRFC_DLR_NS + 90.0 + + + MEM_DDR4_TRFC_NS + 350.0 + + + MEM_DDR4_TRP_CYC + 17 + + + MEM_DDR4_TRP_NS + 14.16 + + + MEM_DDR4_TRRD_DLR_CYC + 4 + + + MEM_DDR4_TRRD_L_CYC + 6 + + + MEM_DDR4_TRRD_S_CYC + 4 + + + MEM_DDR4_TRTP_CYC + 9 + + + MEM_DDR4_TTL_ADDR_WIDTH + 17 + + + MEM_DDR4_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_TTL_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_TTL_CKE_WIDTH + 1 + + + MEM_DDR4_TTL_CK_WIDTH + 1 + + + MEM_DDR4_TTL_CS_WIDTH + 1 + + + MEM_DDR4_TTL_DQS_WIDTH + 9 + + + MEM_DDR4_TTL_DQ_WIDTH + 72 + + + MEM_DDR4_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_TTL_ODT_WIDTH + 1 + + + MEM_DDR4_TTL_RM_WIDTH + 0 + + + MEM_DDR4_TWLH_CYC + 0.13 + + + MEM_DDR4_TWLH_PS + 0.0 + + + MEM_DDR4_TWLS_CYC + 0.13 + + + MEM_DDR4_TWLS_PS + 0.0 + + + MEM_DDR4_TWR_CYC + 18 + + + MEM_DDR4_TWR_NS + 15.0 + + + MEM_DDR4_TWTR_L_CYC + 9 + + + MEM_DDR4_TWTR_S_CYC + 3 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDR4_USE_DEFAULT_ODT + true + + + MEM_DDR4_VDIVW_TOTAL + 130 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_0 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP + Range 1 - 60% to 92.5% + + + MEM_DDR4_VREFDQ_TRAINING_VALUE + 70.0 + + + MEM_DDR4_WRITE_CMD_LATENCY + 6 + + + MEM_DDR4_WRITE_CRC + false + + + MEM_DDR4_WRITE_DBI + false + + + MEM_DDR4_WRITE_PREAMBLE + 1 + + + MEM_DDR4_WTCL + 16 + + + MEM_DDR4_W_DERIVED_BODT0 + + + + MEM_DDR4_W_DERIVED_BODT1 + + + + MEM_DDR4_W_DERIVED_BODTN + + + + MEM_DDR4_W_DERIVED_ODT0 + (Park) RZQ/4 (60 Ohm),-,-,- + + + MEM_DDR4_W_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_W_ODT0_1X1 + on + + + MEM_DDR4_W_ODT0_2X2 + on,off + + + MEM_DDR4_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT1_2X2 + off,on + + + MEM_DDR4_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR4_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR4_W_ODTN_1X1 + Rank 0 + + + MEM_DDR4_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_AC_PARITY_LATENCY + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_AC_PERSISTENT_ERROR + false + + + MEM_DDRT_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDRT_ADDR_WIDTH + 1 + + + MEM_DDRT_ALERT_N_AC_LANE + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + 0 + + + MEM_DDRT_ALERT_N_DQS_GROUP + 0 + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_PAR_EN + true + + + MEM_DDRT_ASR_ENUM + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_ATCL_ENUM + DDRT_ATCL_DISABLED + + + MEM_DDRT_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_BL_ENUM + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_CAL_MODE + 0 + + + MEM_DDRT_CFG_GEN_DBE + false + + + MEM_DDRT_CFG_GEN_SBE + false + + + MEM_DDRT_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_CKE_PER_DIMM + 1 + + + MEM_DDRT_CKE_WIDTH + 1 + + + MEM_DDRT_CK_WIDTH + 1 + + + MEM_DDRT_COL_ADDR_WIDTH + 10 + + + MEM_DDRT_CS_PER_DIMM + 1 + + + MEM_DDRT_CS_WIDTH + 1 + + + MEM_DDRT_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDRT_DB_DQ_DRV_ENUM + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_PARK_ENUM + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + true + + + MEM_DDRT_DEFAULT_PREAMBLE + true + + + MEM_DDRT_DEFAULT_VREFOUT + true + + + MEM_DDRT_DISCRETE_CS_WIDTH + 1 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDRT_DLL_EN + true + + + MEM_DDRT_DM_EN + false + + + MEM_DDRT_DQS_WIDTH + 8 + + + MEM_DDRT_DQ_PER_DQS + 4 + + + MEM_DDRT_DQ_WIDTH + 72 + + + MEM_DDRT_DRV_STR_ENUM + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ERID_WIDTH + 2 + + + MEM_DDRT_ERR_N_WIDTH + 1 + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_FORMAT_ENUM + MEM_FORMAT_LRDIMM + + + MEM_DDRT_GEARDOWN + DDRT_GEARDOWN_HR + + + MEM_DDRT_GNT_N_WIDTH + 1 + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + true + + + MEM_DDRT_I2C_DIMM_0_SA + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + 3 + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDRT_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + + + + MEM_DDRT_MAX_POWERDOWN + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + true + + + MEM_DDRT_MPR_READ_FORMAT + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MR0 + 0 + + + MEM_DDRT_MR1 + 0 + + + MEM_DDRT_MR2 + 0 + + + MEM_DDRT_MR3 + 0 + + + MEM_DDRT_MR4 + 0 + + + MEM_DDRT_MR5 + 0 + + + MEM_DDRT_MR6 + 0 + + + MEM_DDRT_NUM_OF_DIMMS + 1 + + + MEM_DDRT_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_ODT_IN_POWERDOWN + true + + + MEM_DDRT_ODT_WIDTH + 1 + + + MEM_DDRT_PARTIAL_WRITES + false + + + MEM_DDRT_PERSISTENT_MODE + 1 + + + MEM_DDRT_PER_DRAM_ADDR + false + + + MEM_DDRT_PWR_MODE + DDRT_PWR_MODE_12W + + + MEM_DDRT_RANKS_PER_DIMM + 1 + + + MEM_DDRT_RCD_CA_IBT_ENUM + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_COMMAND_LATENCY + 1 + + + MEM_DDRT_RCD_CS_IBT_ENUM + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_RCD_PARITY_CONTROL_WORD + 1 + + + MEM_DDRT_RDIMM_CONFIG + + + + MEM_DDRT_READ_DBI + false + + + MEM_DDRT_READ_PREAMBLE + 1 + + + MEM_DDRT_READ_PREAMBLE_TRAINING + false + + + MEM_DDRT_REQ_N_WIDTH + 1 + + + MEM_DDRT_RM_WIDTH + 0 + + + MEM_DDRT_ROW_ADDR_WIDTH + 18 + + + MEM_DDRT_RTT_NOM_ENUM + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_RTT_PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_RTT_WR_ENUM + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_R_DERIVED_BODT0 + + + + MEM_DDRT_R_DERIVED_BODT1 + + + + MEM_DDRT_R_DERIVED_BODTN + + + + MEM_DDRT_R_DERIVED_ODT0 + ,, + + + MEM_DDRT_R_DERIVED_ODT1 + ,, + + + MEM_DDRT_R_DERIVED_ODT2 + ,, + + + MEM_DDRT_R_DERIVED_ODT3 + ,, + + + MEM_DDRT_R_DERIVED_ODTN + ,, + + + MEM_DDRT_R_ODT0_1X1 + off + + + MEM_DDRT_R_ODT0_2X2 + off,off + + + MEM_DDRT_R_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_R_ODT0_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT1_2X2 + off,off + + + MEM_DDRT_R_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_R_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_R_ODTN_1X1 + Rank 0 + + + MEM_DDRT_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_SELF_RFSH_ABORT + false + + + MEM_DDRT_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDRT_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDRT_SPD_135_RCD_REV + 0 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDRT_SPD_139_DB_REV + 0 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDRT_SPEEDBIN_ENUM + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TCCD_L_CYC + 6 + + + MEM_DDRT_TCCD_S_CYC + 4 + + + MEM_DDRT_TCL + 15 + + + MEM_DDRT_TCL_ADDED + -1 + + + MEM_DDRT_TDIVW_DJ_CYC + 0.1 + + + MEM_DDRT_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDRT_TDQSCKDL + 1200 + + + MEM_DDRT_TDQSCKDM + 900 + + + MEM_DDRT_TDQSCKDS + 450 + + + MEM_DDRT_TDQSCK_DERV_PS + 2 + + + MEM_DDRT_TDQSCK_PS + 165 + + + MEM_DDRT_TDQSQ_PS + 66 + + + MEM_DDRT_TDQSQ_UI + 0.16 + + + MEM_DDRT_TDQSS_CYC + 0.27 + + + MEM_DDRT_TDSH_CYC + 0.18 + + + MEM_DDRT_TDSS_CYC + 0.18 + + + MEM_DDRT_TDVWP_UI + 0.72 + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_SENSOR_READOUT + false + + + MEM_DDRT_TFAW_CYC + 27 + + + MEM_DDRT_TFAW_DLR_CYC + 16 + + + MEM_DDRT_TFAW_NS + 21.0 + + + MEM_DDRT_TIH_DC_MV + 75 + + + MEM_DDRT_TIH_PS + 95 + + + MEM_DDRT_TINIT_CK + 499 + + + MEM_DDRT_TINIT_US + 500 + + + MEM_DDRT_TIS_AC_MV + 100 + + + MEM_DDRT_TIS_PS + 60 + + + MEM_DDRT_TMRD_CK_CYC + 8 + + + MEM_DDRT_TQH_CYC + 0.38 + + + MEM_DDRT_TQH_UI + 0.76 + + + MEM_DDRT_TQSH_CYC + 0.38 + + + MEM_DDRT_TRAS_CYC + 36 + + + MEM_DDRT_TRAS_NS + 32.0 + + + MEM_DDRT_TRCD_CYC + 14 + + + MEM_DDRT_TRCD_NS + 15.0 + + + MEM_DDRT_TREFI_CYC + 8320 + + + MEM_DDRT_TREFI_US + 7.8 + + + MEM_DDRT_TRFC_CYC + 171 + + + MEM_DDRT_TRFC_DLR_CYC + 109 + + + MEM_DDRT_TRFC_DLR_NS + 90.0 + + + MEM_DDRT_TRFC_NS + 260.0 + + + MEM_DDRT_TRP_CYC + 14 + + + MEM_DDRT_TRP_NS + 15.0 + + + MEM_DDRT_TRRD_DLR_CYC + 4 + + + MEM_DDRT_TRRD_L_CYC + 6 + + + MEM_DDRT_TRRD_S_CYC + 4 + + + MEM_DDRT_TRTP_CYC + 9 + + + MEM_DDRT_TTL_ADDR_WIDTH + 1 + + + MEM_DDRT_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_TTL_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_TTL_CKE_WIDTH + 1 + + + MEM_DDRT_TTL_CK_WIDTH + 1 + + + MEM_DDRT_TTL_CS_WIDTH + 1 + + + MEM_DDRT_TTL_DQS_WIDTH + 8 + + + MEM_DDRT_TTL_DQ_WIDTH + 72 + + + MEM_DDRT_TTL_ERID_WIDTH + 2 + + + MEM_DDRT_TTL_ERR_N_WIDTH + 1 + + + MEM_DDRT_TTL_GNT_N_WIDTH + 1 + + + MEM_DDRT_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDRT_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_TTL_ODT_WIDTH + 1 + + + MEM_DDRT_TTL_REQ_N_WIDTH + 1 + + + MEM_DDRT_TTL_RM_WIDTH + 0 + + + MEM_DDRT_TWLH_CYC + 0.13 + + + MEM_DDRT_TWLH_PS + 0.0 + + + MEM_DDRT_TWLS_CYC + 0.13 + + + MEM_DDRT_TWLS_PS + 0.0 + + + MEM_DDRT_TWR_CYC + 18 + + + MEM_DDRT_TWR_NS + 15.0 + + + MEM_DDRT_TWTR_L_CYC + 9 + + + MEM_DDRT_TWTR_S_CYC + 3 + + + MEM_DDRT_USER_READ_PREAMBLE + 1 + + + MEM_DDRT_USER_TCL_ADDED + 0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_USER_WRITE_PREAMBLE + 1 + + + MEM_DDRT_USER_WTCL_ADDED + 6 + + + MEM_DDRT_USE_DEFAULT_ODT + true + + + MEM_DDRT_VDIVW_TOTAL + 136 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE_DISP + Range 2 - 45% to 77.5% + + + MEM_DDRT_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_WRITE_CMD_LATENCY + 5 + + + MEM_DDRT_WRITE_CRC + false + + + MEM_DDRT_WRITE_DBI + false + + + MEM_DDRT_WRITE_PREAMBLE + 1 + + + MEM_DDRT_WTCL + 18 + + + MEM_DDRT_WTCL_ADDED + -1 + + + MEM_DDRT_W_DERIVED_BODT0 + + + + MEM_DDRT_W_DERIVED_BODT1 + + + + MEM_DDRT_W_DERIVED_BODTN + + + + MEM_DDRT_W_DERIVED_ODT0 + ,, + + + MEM_DDRT_W_DERIVED_ODT1 + ,, + + + MEM_DDRT_W_DERIVED_ODT2 + ,, + + + MEM_DDRT_W_DERIVED_ODT3 + ,, + + + MEM_DDRT_W_DERIVED_ODTN + ,, + + + MEM_DDRT_W_ODT0_1X1 + on + + + MEM_DDRT_W_ODT0_2X2 + on,off + + + MEM_DDRT_W_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_W_ODT0_4X4 + on,on,off,off + + + MEM_DDRT_W_ODT1_2X2 + off,on + + + MEM_DDRT_W_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_W_ODTN_1X1 + Rank 0 + + + MEM_DDRT_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_HAS_BSI_SUPPORT + true + + + MEM_HAS_SIM_SUPPORT + true + + + MEM_LPDDR3_ADDR_WIDTH + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + 3 + + + MEM_LPDDR3_BL + LPDDR3_BL_BL8 + + + MEM_LPDDR3_CKE_WIDTH + 1 + + + MEM_LPDDR3_CK_WIDTH + 1 + + + MEM_LPDDR3_COL_ADDR_WIDTH + 10 + + + MEM_LPDDR3_CS_WIDTH + 1 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_LPDDR3_DATA_LATENCY + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_LPDDR3_DM_EN + true + + + MEM_LPDDR3_DM_WIDTH + 1 + + + MEM_LPDDR3_DQODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_DQS_WIDTH + 1 + + + MEM_LPDDR3_DQ_PER_DQS + 8 + + + MEM_LPDDR3_DQ_WIDTH + 32 + + + MEM_LPDDR3_DRV_STR + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_LPDDR3_MR1 + 0 + + + MEM_LPDDR3_MR11 + 0 + + + MEM_LPDDR3_MR2 + 0 + + + MEM_LPDDR3_MR3 + 0 + + + MEM_LPDDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_LPDDR3_NWR + LPDDR3_NWR_NWR12 + + + MEM_LPDDR3_ODT_WIDTH + 1 + + + MEM_LPDDR3_PDODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_ROW_ADDR_WIDTH + 15 + + + MEM_LPDDR3_R_DERIVED_ODT0 + ,, + + + MEM_LPDDR3_R_DERIVED_ODT1 + ,, + + + MEM_LPDDR3_R_DERIVED_ODT2 + ,, + + + MEM_LPDDR3_R_DERIVED_ODT3 + ,, + + + MEM_LPDDR3_R_DERIVED_ODTN + ,, + + + MEM_LPDDR3_R_ODT0_1X1 + off + + + MEM_LPDDR3_R_ODT0_2X2 + off,off + + + MEM_LPDDR3_R_ODT0_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_2X2 + off,off + + + MEM_LPDDR3_R_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_LPDDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_LPDDR3_SPEEDBIN_ENUM + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TDH_DC_MV + 100 + + + MEM_LPDDR3_TDH_PS + 100 + + + MEM_LPDDR3_TDQSCKDL + 614 + + + MEM_LPDDR3_TDQSCKDM + 511 + + + MEM_LPDDR3_TDQSCKDS + 220 + + + MEM_LPDDR3_TDQSCK_DERV_PS + 2 + + + MEM_LPDDR3_TDQSCK_PS + 5500 + + + MEM_LPDDR3_TDQSQ_PS + 135 + + + MEM_LPDDR3_TDQSS_CYC + 1.25 + + + MEM_LPDDR3_TDSH_CYC + 0.2 + + + MEM_LPDDR3_TDSS_CYC + 0.2 + + + MEM_LPDDR3_TDS_AC_MV + 150 + + + MEM_LPDDR3_TDS_PS + 75 + + + MEM_LPDDR3_TFAW_CYC + 40 + + + MEM_LPDDR3_TFAW_NS + 50.0 + + + MEM_LPDDR3_TIH_DC_MV + 100 + + + MEM_LPDDR3_TIH_PS + 100 + + + MEM_LPDDR3_TINIT_CK + 499 + + + MEM_LPDDR3_TINIT_US + 500 + + + MEM_LPDDR3_TIS_AC_MV + 150 + + + MEM_LPDDR3_TIS_PS + 75 + + + MEM_LPDDR3_TMRR_CK_CYC + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + 10 + + + MEM_LPDDR3_TQH_CYC + 0.38 + + + MEM_LPDDR3_TQSH_CYC + 0.38 + + + MEM_LPDDR3_TRAS_CYC + 34 + + + MEM_LPDDR3_TRAS_NS + 42.5 + + + MEM_LPDDR3_TRCD_CYC + 17 + + + MEM_LPDDR3_TRCD_NS + 18.0 + + + MEM_LPDDR3_TREFI_CYC + 3120 + + + MEM_LPDDR3_TREFI_US + 3.9 + + + MEM_LPDDR3_TRFC_CYC + 168 + + + MEM_LPDDR3_TRFC_NS + 210.0 + + + MEM_LPDDR3_TRL_CYC + 10 + + + MEM_LPDDR3_TRP_CYC + 17 + + + MEM_LPDDR3_TRP_NS + 18.0 + + + MEM_LPDDR3_TRRD_CYC + 8 + + + MEM_LPDDR3_TRTP_CYC + 6 + + + MEM_LPDDR3_TWLH_PS + 175.0 + + + MEM_LPDDR3_TWLS_PS + 175.0 + + + MEM_LPDDR3_TWL_CYC + 6 + + + MEM_LPDDR3_TWR_CYC + 12 + + + MEM_LPDDR3_TWR_NS + 15.0 + + + MEM_LPDDR3_TWTR_CYC + 6 + + + MEM_LPDDR3_USE_DEFAULT_ODT + true + + + MEM_LPDDR3_WLSELECT + Set A + + + MEM_LPDDR3_W_DERIVED_ODT0 + ,, + + + MEM_LPDDR3_W_DERIVED_ODT1 + ,, + + + MEM_LPDDR3_W_DERIVED_ODT2 + ,, + + + MEM_LPDDR3_W_DERIVED_ODT3 + ,, + + + MEM_LPDDR3_W_DERIVED_ODTN + ,, + + + MEM_LPDDR3_W_ODT0_1X1 + on + + + MEM_LPDDR3_W_ODT0_2X2 + on,on + + + MEM_LPDDR3_W_ODT0_4X4 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_2X2 + off,off + + + MEM_LPDDR3_W_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_NUM_OF_DATA_ENDPOINTS + 1 + + + MEM_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_QDR2_ADDR_WIDTH + 19 + + + MEM_QDR2_BL + 4 + + + MEM_QDR2_BWS_EN + true + + + MEM_QDR2_BWS_N_PER_DEVICE + 4 + + + MEM_QDR2_BWS_N_WIDTH + 4 + + + MEM_QDR2_CQ_WIDTH + 1 + + + MEM_QDR2_DATA_PER_DEVICE + 36 + + + MEM_QDR2_DATA_WIDTH + 36 + + + MEM_QDR2_DEVICE_WIDTH + 1 + + + MEM_QDR2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR2_INTERNAL_JITTER_NS + 0.08 + + + MEM_QDR2_K_WIDTH + 1 + + + MEM_QDR2_SPEEDBIN_ENUM + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TCCQO_NS + 0.45 + + + MEM_QDR2_TCQDOH_NS + -0.09 + + + MEM_QDR2_TCQD_NS + 0.09 + + + MEM_QDR2_TCQH_NS + 0.71 + + + MEM_QDR2_THA_NS + 0.18 + + + MEM_QDR2_THD_NS + 0.18 + + + MEM_QDR2_TRL_CYC + 2.5 + + + MEM_QDR2_TSA_NS + 0.23 + + + MEM_QDR2_TSD_NS + 0.23 + + + MEM_QDR2_TWL_CYC + 1 + + + MEM_QDR2_WIDTH_EXPANDED + false + + + MEM_QDR4_AC_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_ADDR_INV_ENA + false + + + MEM_QDR4_ADDR_WIDTH + 21 + + + MEM_QDR4_AVL_CHNLS + 8 + + + MEM_QDR4_BL + 2 + + + MEM_QDR4_CK_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_CR0 + 0 + + + MEM_QDR4_CR1 + 0 + + + MEM_QDR4_CR2 + 0 + + + MEM_QDR4_DATA_INV_ENA + true + + + MEM_QDR4_DATA_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_DEVICE_DEPTH + 1 + + + MEM_QDR4_DEVICE_WIDTH + 1 + + + MEM_QDR4_DINV_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DINV_WIDTH + 4 + + + MEM_QDR4_DK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DK_WIDTH + 4 + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + 36 + + + MEM_QDR4_DQ_PER_PORT_WIDTH + 36 + + + MEM_QDR4_DQ_PER_RD_GROUP + 18 + + + MEM_QDR4_DQ_PER_WR_GROUP + 18 + + + MEM_QDR4_DQ_WIDTH + 72 + + + MEM_QDR4_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR4_MEM_TYPE_ENUM + MEM_XP + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_QK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_QK_WIDTH + 4 + + + MEM_QDR4_SKIP_ODT_SWEEPING + true + + + MEM_QDR4_SPEEDBIN_ENUM + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TASH_PS + 170 + + + MEM_QDR4_TCKDK_MAX_PS + 150 + + + MEM_QDR4_TCKDK_MIN_PS + -150 + + + MEM_QDR4_TCKQK_MAX_PS + 225 + + + MEM_QDR4_TCSH_PS + 170 + + + MEM_QDR4_TISH_PS + 150 + + + MEM_QDR4_TQH_CYC + 0.4 + + + MEM_QDR4_TQKQ_MAX_PS + 75 + + + MEM_QDR4_TRL_CYC + 8 + + + MEM_QDR4_TWL_CYC + 5 + + + MEM_QDR4_USE_ADDR_PARITY + false + + + MEM_QDR4_WIDTH_EXPANDED + false + + + MEM_READ_LATENCY + 23.0 + + + MEM_RLD2_ADDR_WIDTH + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + 3 + + + MEM_RLD2_BL + 4 + + + MEM_RLD2_CONFIG_ENUM + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_CS_WIDTH + 1 + + + MEM_RLD2_DEVICE_DEPTH + 1 + + + MEM_RLD2_DEVICE_WIDTH + 1 + + + MEM_RLD2_DK_WIDTH + 1 + + + MEM_RLD2_DM_EN + true + + + MEM_RLD2_DM_WIDTH + 1 + + + MEM_RLD2_DQ_PER_DEVICE + 9 + + + MEM_RLD2_DQ_PER_RD_GROUP + 9 + + + MEM_RLD2_DQ_PER_WR_GROUP + 9 + + + MEM_RLD2_DQ_WIDTH + 9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD2_MR + 0 + + + MEM_RLD2_ODT_MODE_ENUM + RLD2_ODT_ON + + + MEM_RLD2_QK_WIDTH + 1 + + + MEM_RLD2_REFRESH_INTERVAL_US + 0.24 + + + MEM_RLD2_SPEEDBIN_ENUM + RLD2_SPEEDBIN_18 + + + MEM_RLD2_TAH_NS + 0.3 + + + MEM_RLD2_TAS_NS + 0.3 + + + MEM_RLD2_TCKDK_MAX_NS + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + -0.3 + + + MEM_RLD2_TCKH_CYC + 0.45 + + + MEM_RLD2_TCKQK_MAX_NS + 0.2 + + + MEM_RLD2_TDH_NS + 0.17 + + + MEM_RLD2_TDS_NS + 0.17 + + + MEM_RLD2_TQKH_HCYC + 0.9 + + + MEM_RLD2_TQKQ_MAX_NS + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + -0.12 + + + MEM_RLD2_TRC + 8 + + + MEM_RLD2_TRL + 8 + + + MEM_RLD2_TWL + 9 + + + MEM_RLD2_WIDTH_EXPANDED + false + + + MEM_RLD3_ADDR_WIDTH + 20 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + RLD3_AREF_BAC + + + MEM_RLD3_BANK_ADDR_WIDTH + 4 + + + MEM_RLD3_BL + 2 + + + MEM_RLD3_CS_WIDTH + 1 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + RLD3_DL_RL16_WL17 + + + MEM_RLD3_DEPTH_EXPANDED + false + + + MEM_RLD3_DEVICE_DEPTH + 1 + + + MEM_RLD3_DEVICE_WIDTH + 1 + + + MEM_RLD3_DK_WIDTH + 2 + + + MEM_RLD3_DM_EN + true + + + MEM_RLD3_DM_WIDTH + 2 + + + MEM_RLD3_DQ_PER_DEVICE + 36 + + + MEM_RLD3_DQ_PER_RD_GROUP + 9 + + + MEM_RLD3_DQ_PER_WR_GROUP + 18 + + + MEM_RLD3_DQ_WIDTH + 36 + + + MEM_RLD3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD3_MR0 + 0 + + + MEM_RLD3_MR1 + 0 + + + MEM_RLD3_MR2 + 0 + + + MEM_RLD3_ODT_MODE_ENUM + RLD3_ODT_40 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_QK_WIDTH + 4 + + + MEM_RLD3_SPEEDBIN_ENUM + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TCKDK_MAX_CYC + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + 135 + + + MEM_RLD3_TDH_DC_MV + 100 + + + MEM_RLD3_TDH_PS + 5 + + + MEM_RLD3_TDS_AC_MV + 150 + + + MEM_RLD3_TDS_PS + -30 + + + MEM_RLD3_TIH_DC_MV + 100 + + + MEM_RLD3_TIH_PS + 65 + + + MEM_RLD3_TIS_AC_MV + 150 + + + MEM_RLD3_TIS_PS + 85 + + + MEM_RLD3_TQH_CYC + 0.38 + + + MEM_RLD3_TQKQ_MAX_PS + 75 + + + MEM_RLD3_T_RC_MODE_ENUM + RLD3_TRC_9 + + + MEM_RLD3_WIDTH_EXPANDED + false + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + RLD3_WRITE_1BANK + + + MEM_TTL_DATA_WIDTH + 72 + + + MEM_TTL_NUM_OF_READ_GROUPS + 9 + + + MEM_TTL_NUM_OF_WRITE_GROUPS + 9 + + + MEM_WRITE_LATENCY + 18 + + + NUM_IPS + 1 + + + NUM_IPS_SAVED + 0 + + + PHY_AC_CALIBRATED_OCT + true + + + PHY_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CALIBRATED_OCT + true + + + PHY_CK_CALIBRATED_OCT + true + + + PHY_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CLAMSHELL_EN + false + + + PHY_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DATA_CALIBRATED_OCT + true + + + PHY_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DATA_OUT_SLEW_RATE_ENUM + + + + PHY_DDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_AC_IO_STD_ENUM + unset + + + PHY_DDR3_AC_MODE_ENUM + unset + + + PHY_DDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_CAL_ADDR0 + 0 + + + PHY_DDR3_CAL_ADDR1 + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + false + + + PHY_DDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_CK_IO_STD_ENUM + unset + + + PHY_DDR3_CK_MODE_ENUM + unset + + + PHY_DDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR3_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_DEFAULT_IO + true + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR3_IO_VOLTAGE + 1.5 + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_DDR3_MIMIC_HPS_EMIF + false + + + PHY_DDR3_PING_PONG_EN + false + + + PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_RATE_ENUM + RATE_QUARTER + + + PHY_DDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR3_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_STARTING_VREFIN + 70.0 + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_PING_PONG_EN + false + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_DDR4_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_AC_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_ALLOW_72_DQ_WIDTH + false + + + PHY_DDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_CK_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_CLAMSHELL_EN + false + + + PHY_DDR4_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR4_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DDR4_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_DEFAULT_IO + false + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR4_IO_VOLTAGE + 1.2 + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDR4_MIMIC_HPS_EMIF + false + + + PHY_DDR4_PING_PONG_EN + false + + + PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_RATE_ENUM + RATE_QUARTER + + + PHY_DDR4_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR4_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_STARTING_VREFIN + 68.0 + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_CLAMSHELL_EN + false + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_USER_PING_PONG_EN + false + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_2CH_EN + false + + + PHY_DDRT_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_AC_IO_STD_ENUM + unset + + + PHY_DDRT_AC_MODE_ENUM + unset + + + PHY_DDRT_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_CK_IO_STD_ENUM + unset + + + PHY_DDRT_CK_MODE_ENUM + unset + + + PHY_DDRT_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDRT_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_DEFAULT_IO + true + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDRT_EXPORT_CLK_STP_IF + false + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDRT_I2C_USE_SMC + false + + + PHY_DDRT_IC_EN + true + + + PHY_DDRT_IO_VOLTAGE + 1.2 + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDRT_MIMIC_HPS_EMIF + false + + + PHY_DDRT_PING_PONG_EN + false + + + PHY_DDRT_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_RATE_ENUM + RATE_QUARTER + + + PHY_DDRT_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDRT_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_IO_STD_ENUM + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_USER_PING_PONG_EN + false + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + false + + + PHY_DLL_CORE_UPDN_EN + false + + + PHY_FPGA_SPEEDGRADE_GUI + E2V (ES3) - change device under 'View'->'Device Family' + + + PHY_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_AC_MODE_ENUM + unset + + + PHY_LPDDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_CK_MODE_ENUM + unset + + + PHY_LPDDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_LPDDR3_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_DEFAULT_IO + true + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_IO_VOLTAGE + 1.2 + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + 800.0 + + + PHY_LPDDR3_MIMIC_HPS_EMIF + false + + + PHY_LPDDR3_PING_PONG_EN + false + + + PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_RATE_ENUM + RATE_QUARTER + + + PHY_LPDDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_LPDDR3_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_STARTING_VREFIN + 70.0 + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_PING_PONG_EN + false + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_MIMIC_HPS_EMIF + false + + + PHY_PING_PONG_EN + false + + + PHY_QDR2_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_AC_IO_STD_ENUM + unset + + + PHY_QDR2_AC_MODE_ENUM + unset + + + PHY_QDR2_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_CK_IO_STD_ENUM + unset + + + PHY_QDR2_CK_MODE_ENUM + unset + + + PHY_QDR2_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR2_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_DEFAULT_IO + true + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR2_IO_VOLTAGE + 1.5 + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + 633.333 + + + PHY_QDR2_MIMIC_HPS_EMIF + false + + + PHY_QDR2_PING_PONG_EN + false + + + PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_RATE_ENUM + RATE_HALF + + + PHY_QDR2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR2_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_STARTING_VREFIN + 70.0 + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_PING_PONG_EN + false + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_USER_STARTING_VREFIN + 70.0 + + + PHY_QDR4_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_AC_IO_STD_ENUM + unset + + + PHY_QDR4_AC_MODE_ENUM + unset + + + PHY_QDR4_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_CK_IO_STD_ENUM + unset + + + PHY_QDR4_CK_MODE_ENUM + unset + + + PHY_QDR4_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR4_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_DEFAULT_IO + true + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR4_IO_VOLTAGE + 1.2 + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_QDR4_MIMIC_HPS_EMIF + false + + + PHY_QDR4_PING_PONG_EN + false + + + PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_RATE_ENUM + RATE_QUARTER + + + PHY_QDR4_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR4_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_STARTING_VREFIN + 70.0 + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_PING_PONG_EN + false + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_RATE_ENUM + RATE_QUARTER + + + PHY_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_AC_IO_STD_ENUM + unset + + + PHY_RLD2_AC_MODE_ENUM + unset + + + PHY_RLD2_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_CK_IO_STD_ENUM + unset + + + PHY_RLD2_CK_MODE_ENUM + unset + + + PHY_RLD2_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD2_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_DEFAULT_IO + true + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD2_IO_VOLTAGE + 1.8 + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + 533.333 + + + PHY_RLD2_MIMIC_HPS_EMIF + false + + + PHY_RLD2_PING_PONG_EN + false + + + PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_RATE_ENUM + RATE_HALF + + + PHY_RLD2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_STARTING_VREFIN + 70.0 + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_PING_PONG_EN + false + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_USER_STARTING_VREFIN + 70.0 + + + PHY_RLD3_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_AC_IO_STD_ENUM + unset + + + PHY_RLD3_AC_MODE_ENUM + unset + + + PHY_RLD3_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_CK_IO_STD_ENUM + unset + + + PHY_RLD3_CK_MODE_ENUM + unset + + + PHY_RLD3_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_CONFIG_ENUM + CONFIG_PHY_ONLY + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD3_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_DEFAULT_IO + true + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD3_IO_VOLTAGE + 1.2 + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_RLD3_MIMIC_HPS_EMIF + false + + + PHY_RLD3_PING_PONG_EN + false + + + PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_RATE_ENUM + RATE_QUARTER + + + PHY_RLD3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD3_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_STARTING_VREFIN + 70.0 + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_PING_PONG_EN + false + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_USER_STARTING_VREFIN + 70.0 + + + PHY_RZQ + 240 + + + PHY_TARGET_IS_ES + false + + + PHY_TARGET_IS_ES2 + false + + + PHY_TARGET_IS_ES3 + true + + + PHY_TARGET_IS_PRODUCTION + false + + + PHY_TARGET_SPEEDGRADE + E2V + + + PHY_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PLL_ADD_EXTRA_CLKS + false + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + ps + + + PLL_NUM_OF_EXTRA_CLKS + 0 + + + PLL_USER_NUM_OF_EXTRA_CLKS + 0 + + + PLL_VCO_CLK_FREQ_MHZ + 1200.0 + + + PREV_PROTOCOL_ENUM + PROTOCOL_DDR4 + + + PROTOCOL_ENUM + PROTOCOL_DDR4 + + + SHORT_QSYS_INTERFACE_NAMES + true + + + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_DEVICE_DIE_REVISIONS + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + + + SYS_INFO_DEVICE_FAMILY + Agilex 7 + + + SYS_INFO_DEVICE_POWER_MODEL + STANDARD_POWER + + + SYS_INFO_DEVICE_SPEEDGRADE + 2 + + + SYS_INFO_DEVICE_TEMPERATURE_GRADE + EXTENDED + + + SYS_INFO_UNIQUE_ID + ed_synth_emif_fm_0_emif_fm_0 + + + TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + TRAIT_SUPPORTS_VID + 1 + + + + altera_emif_fm + 2.7.4 + emif_fm_0 + ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq + 0 + + ed_synth_emif_fm_0.emif_fm_0 + + + + arch + + + + ABPHY_WRITE_PROTOCOL + 0 + + + AC_PIN_MAP_SCHEME + use_0_1_2_3_lane + + + AMM_C2P_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + AMM_HIPI_DELAY + 350 + + + AMM_P2C_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + BOARD_DDR3_AC_ISI_NS + 0.0 + + + BOARD_DDR3_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_DDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDR3_TDH_DERATING_PS + 0 + + + BOARD_DDR3_TDS_DERATING_PS + 0 + + + BOARD_DDR3_TIH_DERATING_PS + 0 + + + BOARD_DDR3_TIS_DERATING_PS + 0 + + + BOARD_DDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR3_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_ISI_NS + 0.15 + + + BOARD_DDR4_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_RCLK_ISI_NS + 0.15 + + + BOARD_DDR4_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_RDATA_ISI_NS + 0.12 + + + BOARD_DDR4_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR4_SKEW_WITHIN_AC_NS + 0.18 + + + BOARD_DDR4_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_TIH_DERATING_PS + 0 + + + BOARD_DDR4_TIS_DERATING_PS + 0 + + + BOARD_DDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR4_WCLK_ISI_NS + 0.06 + + + BOARD_DDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_WDATA_ISI_NS + 0.13 + + + BOARD_DDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_ISI_NS + 0.0 + + + BOARD_DDRT_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDRT_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDRT_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDRT_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDRT_TIH_DERATING_PS + 0 + + + BOARD_DDRT_TIS_DERATING_PS + 0 + + + BOARD_DDRT_USER_AC_ISI_NS + 0.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDRT_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_LPDDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_LPDDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_LPDDR3_TDH_DERATING_PS + 0 + + + BOARD_LPDDR3_TDS_DERATING_PS + 0 + + + BOARD_LPDDR3_TIH_DERATING_PS + 0 + + + BOARD_LPDDR3_TIS_DERATING_PS + 0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_LPDDR3_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_ISI_NS + 0.0 + + + BOARD_QDR2_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + 0.0 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + false + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + false + + + BOARD_QDR2_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + 0.6 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_D_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_Q_NS + 0.0 + + + BOARD_QDR2_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR2_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_ISI_NS + 0.0 + + + BOARD_QDR4_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + true + + + BOARD_QDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + 0.6 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_QDR4_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR4_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_QDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR4_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_ISI_NS + 0.0 + + + BOARD_RLD3_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + false + + + BOARD_RLD3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + 0.6 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_RLD3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_RLD3_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_RLD3_TDH_DERATING_PS + 0 + + + BOARD_RLD3_TDS_DERATING_PS + 0 + + + BOARD_RLD3_TIH_DERATING_PS + 0 + + + BOARD_RLD3_TIS_DERATING_PS + 0 + + + BOARD_RLD3_USER_AC_ISI_NS + 0.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_RLD3_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_WDATA_SLEW_RATE + 2.0 + + + C2P_P2C_CLK_RATIO + 4 + + + CAL_DEBUG_CLOCK_FREQUENCY + 50000000 + + + CENTER_TIDS_0 + 542119940 + + + CENTER_TIDS_1 + 3 + + + CENTER_TIDS_2 + 0 + + + CENTER_TIDS_AUTOGEN_WCNT + 3 + + + CPA_FB_MUX_1_SEL + local_p_clk + + + CTRL_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR3_ECC_EN + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + true + + + CTRL_DDR3_ECC_STATUS_EN + false + + + CTRL_DDR3_MMR_EN + false + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_REORDER_EN + true + + + CTRL_DDR3_SELF_REFRESH_EN + false + + + CTRL_DDR3_STARVE_LIMIT + 10 + + + CTRL_DDR3_USER_PRIORITY_EN + false + + + CTRL_DDR3_USER_REFRESH_EN + false + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_ADDR_ORDER_ENUM + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + false + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR4_ECC_EN + true + + + CTRL_DDR4_ECC_READDATAERROR_EN + false + + + CTRL_DDR4_ECC_STATUS_EN + false + + + CTRL_DDR4_MAJOR_MODE_EN + false + + + CTRL_DDR4_MMR_EN + false + + + CTRL_DDR4_POST_REFRESH_EN + true + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + 1 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_REORDER_EN + true + + + CTRL_DDR4_SELF_REFRESH_EN + false + + + CTRL_DDR4_STARVE_LIMIT + 10 + + + CTRL_DDR4_USER_PRIORITY_EN + false + + + CTRL_DDR4_USER_REFRESH_EN + false + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ADDR_INTERLEAVING + COARSE + + + CTRL_DDRT_ADDR_ORDER_ENUM + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + false + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_AXIS_DATA_WIDTH + 512 + + + CTRL_DDRT_DIMM_DENSITY + 128 + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + false + + + CTRL_DDRT_DRIVER_MARGINING_EN + 0 + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDRT_ECC_EN + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + true + + + CTRL_DDRT_ECC_STATUS_EN + true + + + CTRL_DDRT_ERR_INJECT_EN + false + + + CTRL_DDRT_ERR_REPLAY_EN + false + + + CTRL_DDRT_EXT_ERR_INJECT_EN + false + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + false + + + CTRL_DDRT_MMR_EN + false + + + CTRL_DDRT_NUM_OF_AXIS_ID + 1 + + + CTRL_DDRT_PARITY_CMD_EN + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + false + + + CTRL_DDRT_POISON_DETECTION_EN + false + + + CTRL_DDRT_PORT_AFI_C_WIDTH + 2 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_REORDER_EN + true + + + CTRL_DDRT_SELF_REFRESH_EN + false + + + CTRL_DDRT_STARVE_LIMIT + 10 + + + CTRL_DDRT_UPI_EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + 8 + + + CTRL_DDRT_USER_PRIORITY_EN + false + + + CTRL_DDRT_USER_REFRESH_EN + false + + + CTRL_DDRT_WR_ACK_POLICY + POSTED + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ZQ_INTERVAL_MS + 3 + + + CTRL_ECC_EN + true + + + CTRL_ECC_READDATAERROR_EN + false + + + CTRL_ECC_STATUS_EN + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + false + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_MMR_EN + false + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_REORDER_EN + true + + + CTRL_LPDDR3_SELF_REFRESH_EN + false + + + CTRL_LPDDR3_STARVE_LIMIT + 10 + + + CTRL_LPDDR3_USER_PRIORITY_EN + false + + + CTRL_LPDDR3_USER_REFRESH_EN + false + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_MMR_EN + false + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC + 11 + + + CTRL_REORDER_EN + true + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_USER_PRIORITY_EN + false + + + DBC_EXTRA_PIPE_STAGE_EN + disable + + + DBC_PIPE_LATS_0 + 286335522 + + + DBC_PIPE_LATS_1 + 821384 + + + DBC_PIPE_LATS_2 + 0 + + + DBC_PIPE_LATS_3 + 0 + + + DBC_PIPE_LATS_4 + 0 + + + DBC_PIPE_LATS_AUTOGEN_WCNT + 5 + + + DBC_WB_RESERVED_ENTRY + 52 + + + DBI_RD_ENABLE + dbi_rd_ena + + + DBI_WR_ENABLE + dbi_wr_dis + + + DB_PINS_PROC_MODE_0 + 275876963 + + + DB_PINS_PROC_MODE_1 + 103911395 + + + DB_PINS_PROC_MODE_10 + 34636833 + + + DB_PINS_PROC_MODE_11 + 34636833 + + + DB_PINS_PROC_MODE_12 + 34668543 + + + DB_PINS_PROC_MODE_13 + 34667553 + + + DB_PINS_PROC_MODE_14 + 1073741823 + + + DB_PINS_PROC_MODE_15 + 1073730559 + + + DB_PINS_PROC_MODE_16 + 275876963 + + + DB_PINS_PROC_MODE_17 + 103911395 + + + DB_PINS_PROC_MODE_18 + 275876963 + + + DB_PINS_PROC_MODE_19 + 103911395 + + + DB_PINS_PROC_MODE_2 + 275876963 + + + DB_PINS_PROC_MODE_20 + 275876963 + + + DB_PINS_PROC_MODE_21 + 103911395 + + + DB_PINS_PROC_MODE_22 + 275876963 + + + DB_PINS_PROC_MODE_23 + 103911395 + + + DB_PINS_PROC_MODE_24 + 275876963 + + + DB_PINS_PROC_MODE_25 + 103911395 + + + DB_PINS_PROC_MODE_26 + 1073741823 + + + DB_PINS_PROC_MODE_27 + 1073741823 + + + DB_PINS_PROC_MODE_28 + 1073741823 + + + DB_PINS_PROC_MODE_29 + 1073741823 + + + DB_PINS_PROC_MODE_3 + 103911395 + + + DB_PINS_PROC_MODE_30 + 1073741823 + + + DB_PINS_PROC_MODE_31 + 1073741823 + + + DB_PINS_PROC_MODE_32 + 0 + + + DB_PINS_PROC_MODE_33 + 0 + + + DB_PINS_PROC_MODE_34 + 0 + + + DB_PINS_PROC_MODE_35 + 0 + + + DB_PINS_PROC_MODE_36 + 0 + + + DB_PINS_PROC_MODE_37 + 0 + + + DB_PINS_PROC_MODE_38 + 0 + + + DB_PINS_PROC_MODE_39 + 0 + + + DB_PINS_PROC_MODE_4 + 275876963 + + + DB_PINS_PROC_MODE_40 + 0 + + + DB_PINS_PROC_MODE_41 + 0 + + + DB_PINS_PROC_MODE_42 + 0 + + + DB_PINS_PROC_MODE_43 + 0 + + + DB_PINS_PROC_MODE_44 + 0 + + + DB_PINS_PROC_MODE_45 + 0 + + + DB_PINS_PROC_MODE_46 + 0 + + + DB_PINS_PROC_MODE_47 + 0 + + + DB_PINS_PROC_MODE_48 + 0 + + + DB_PINS_PROC_MODE_49 + 0 + + + DB_PINS_PROC_MODE_5 + 103911395 + + + DB_PINS_PROC_MODE_50 + 0 + + + DB_PINS_PROC_MODE_51 + 0 + + + DB_PINS_PROC_MODE_52 + 0 + + + DB_PINS_PROC_MODE_53 + 0 + + + DB_PINS_PROC_MODE_54 + 0 + + + DB_PINS_PROC_MODE_55 + 0 + + + DB_PINS_PROC_MODE_56 + 0 + + + DB_PINS_PROC_MODE_57 + 0 + + + DB_PINS_PROC_MODE_58 + 0 + + + DB_PINS_PROC_MODE_59 + 0 + + + DB_PINS_PROC_MODE_6 + 275876963 + + + DB_PINS_PROC_MODE_60 + 0 + + + DB_PINS_PROC_MODE_61 + 0 + + + DB_PINS_PROC_MODE_62 + 0 + + + DB_PINS_PROC_MODE_63 + 0 + + + DB_PINS_PROC_MODE_7 + 103911395 + + + DB_PINS_PROC_MODE_8 + 1041269793 + + + DB_PINS_PROC_MODE_9 + 66230241 + + + DB_PINS_PROC_MODE_AUTOGEN_WCNT + 64 + + + DB_PTR_PIPELINE_DEPTHS_0 + 286331153 + + + DB_PTR_PIPELINE_DEPTHS_1 + 17476 + + + DB_PTR_PIPELINE_DEPTHS_2 + 0 + + + DB_PTR_PIPELINE_DEPTHS_3 + 0 + + + DB_PTR_PIPELINE_DEPTHS_4 + 0 + + + DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT + 5 + + + DB_SEQ_RD_EN_FULL_PIPELINES_0 + 858993459 + + + DB_SEQ_RD_EN_FULL_PIPELINES_1 + 838860 + + + DB_SEQ_RD_EN_FULL_PIPELINES_2 + 0 + + + DB_SEQ_RD_EN_FULL_PIPELINES_3 + 0 + + + DB_SEQ_RD_EN_FULL_PIPELINES_4 + 0 + + + DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT + 5 + + + DIAG_ABSTRACT_PHY_RLAT + 20 + + + DIAG_ABSTRACT_PHY_WLAT + 9 + + + DIAG_AC_PARITY_ERR + false + + + DIAG_ADD_READY_PIPELINE + true + + + DIAG_BOARD_DELAY_CONFIG_STR + + + + DIAG_CPA_OUT_1_EN + false + + + DIAG_DB_RESET_AUTO_RELEASE + avl_release + + + DIAG_DDR3_ABSTRACT_PHY + false + + + DIAG_DDR3_AC_PARITY_ERR + false + + + DIAG_DDR3_CAL_ADDR0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + 8 + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + false + + + DIAG_DDR3_CAL_ENABLE_NON_DES + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR3_CA_DESKEW_EN + true + + + DIAG_DDR3_CA_LEVEL_EN + true + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR3_ENABLE_USER_MODE + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR3_INTERFACE_ID + 0 + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR3_SIM_VERBOSE + true + + + DIAG_DDR3_TG2_TEST_DURATION + SHORT + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR3_USE_TG_AVL_2 + false + + + DIAG_DDR3_USE_TG_HBM + false + + + DIAG_DDR4_ABSTRACT_PHY + false + + + DIAG_DDR4_AC_PARITY_ERR + false + + + DIAG_DDR4_CAL_ADDR0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR4_ENABLE_USER_MODE + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR4_INTERFACE_ID + 0 + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR4_SIM_VERBOSE + true + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + false + + + DIAG_DDR4_SKIP_CA_DESKEW + false + + + DIAG_DDR4_SKIP_CA_LEVEL + false + + + DIAG_DDR4_SKIP_VREF_CAL + false + + + DIAG_DDR4_TG2_TEST_DURATION + SHORT + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR4_USE_TG_AVL_2 + false + + + DIAG_DDR4_USE_TG_HBM + false + + + DIAG_DDRT_ABSTRACT_PHY + false + + + DIAG_DDRT_AC_PARITY_ERR + false + + + DIAG_DDRT_CAL_ADDR0 + 0 + + + DIAG_DDRT_CAL_ADDR1 + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDRT_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDRT_EFF_TEST + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + false + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + false + + + DIAG_DDRT_ENABLE_USER_MODE + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDRT_INTERFACE_ID + 0 + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDRT_SIM_VERBOSE + true + + + DIAG_DDRT_SKIP_CA_DESKEW + false + + + DIAG_DDRT_SKIP_CA_LEVEL + false + + + DIAG_DDRT_SKIP_VREF_CAL + false + + + DIAG_DDRT_TG2_TEST_DURATION + SHORT + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + false + + + DIAG_DDRT_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDRT_USE_TG_AVL_2 + true + + + DIAG_DDRT_USE_TG_HBM + false + + + DIAG_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_ECLIPSE_DEBUG + false + + + DIAG_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_ENABLE_DEFAULT_MODE + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + false + + + DIAG_ENABLE_JTAG_UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + false + + + DIAG_ENABLE_SOFT_M20K + false + + + DIAG_ENABLE_USER_MODE + true + + + DIAG_EXPORT_PLL_LOCKED + true + + + DIAG_EXPORT_PLL_REF_CLK_OUT + false + + + DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_EXPORT_VJI + false + + + DIAG_EXPOSE_DFT_SIGNALS + false + + + DIAG_EXPOSE_EARLY_READY + false + + + DIAG_EXPOSE_RD_TYPE + false + + + DIAG_EXTRA_CONFIGS + + + + DIAG_EXT_DOCS + false + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + + + + DIAG_EX_DESIGN_ISSP_EN + true + + + DIAG_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_EX_DESIGN_SEPARATE_RESETS + false + + + DIAG_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_FAST_SIM + true + + + DIAG_FAST_SIM_OVERRIDE + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_HMC_HRC + auto + + + DIAG_INTERFACE_ID + 0 + + + DIAG_LPDDR3_ABSTRACT_PHY + false + + + DIAG_LPDDR3_AC_PARITY_ERR + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_LPDDR3_INTERFACE_ID + 0 + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_LPDDR3_SIM_VERBOSE + true + + + DIAG_LPDDR3_SKIP_CA_DESKEW + false + + + DIAG_LPDDR3_SKIP_CA_LEVEL + false + + + DIAG_LPDDR3_TG2_TEST_DURATION + SHORT + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_LPDDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_LPDDR3_USE_TG_AVL_2 + false + + + DIAG_LPDDR3_USE_TG_HBM + false + + + DIAG_QDR2_ABSTRACT_PHY + false + + + DIAG_QDR2_AC_PARITY_ERR + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR2_ENABLE_USER_MODE + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR2_INTERFACE_ID + 0 + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR2_SIM_VERBOSE + true + + + DIAG_QDR2_TG2_TEST_DURATION + SHORT + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR2_USE_TG_AVL_2 + false + + + DIAG_QDR2_USE_TG_HBM + false + + + DIAG_QDR4_ABSTRACT_PHY + false + + + DIAG_QDR4_AC_PARITY_ERR + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR4_ENABLE_USER_MODE + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR4_INTERFACE_ID + 0 + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR4_SIM_VERBOSE + true + + + DIAG_QDR4_SKIP_VREF_CAL + false + + + DIAG_QDR4_TG2_TEST_DURATION + SHORT + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR4_USE_TG_AVL_2 + false + + + DIAG_QDR4_USE_TG_HBM + false + + + DIAG_RLD2_ABSTRACT_PHY + false + + + DIAG_RLD2_AC_PARITY_ERR + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD2_ENABLE_USER_MODE + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD2_INTERFACE_ID + 0 + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD2_SIM_VERBOSE + true + + + DIAG_RLD2_TG2_TEST_DURATION + SHORT + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD2_USE_TG_AVL_2 + false + + + DIAG_RLD2_USE_TG_HBM + false + + + DIAG_RLD3_ABSTRACT_PHY + false + + + DIAG_RLD3_AC_PARITY_ERR + false + + + DIAG_RLD3_CA_DESKEW_EN + true + + + DIAG_RLD3_CA_LEVEL_EN + true + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD3_ENABLE_USER_MODE + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD3_INTERFACE_ID + 0 + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD3_SIM_VERBOSE + true + + + DIAG_RLD3_TG2_TEST_DURATION + SHORT + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD3_USE_TG_AVL_2 + false + + + DIAG_RLD3_USE_TG_HBM + false + + + DIAG_RS232_UART_BAUDRATE + 57600 + + + DIAG_SEQ_RESET_AUTO_RELEASE + avl + + + DIAG_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_SIM_CHECKER_SKIP_TG + false + + + DIAG_SIM_MEMORY_PRELOAD + false + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE + + + + DIAG_SIM_REGTEST_MODE + false + + + DIAG_SIM_VERBOSE_LEVEL + 5 + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + 100 + + + DIAG_SOFT_NIOS_MODE + SOFT_NIOS_MODE_DISABLED + + + DIAG_SYNTH_FOR_SIM + false + + + DIAG_TG2_TEST_DURATION + SHORT + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + 0 + + + DIAG_TIMING_REGTEST_MODE + false + + + DIAG_USE_ABSTRACT_PHY + false + + + DIAG_USE_BOARD_DELAY_MODEL + false + + + DIAG_USE_CPA_LOCK + true + + + DIAG_USE_NEW_EFFMON_S10 + false + + + DIAG_USE_RS232_UART + false + + + DIAG_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_USE_TG_AVL_2 + false + + + DIAG_USE_TG_HBM + false + + + DIAG_VERBOSE_IOAUX + false + + + DLL_CODEWORD + 0 + + + DLL_MODE + dll_ctl_dynamic + + + DQSA_LGC_MODE + dqs_diff_in_1_a + + + DQSB_LGC_MODE + dqs_constant_b + + + DQS_BUS_MODE_ENUM + DQS_BUS_MODE_X8_X9 + + + DQS_PACK_MODE + packed + + + ECC_C2P_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + ECC_HIPI_DELAY + 350 + + + ECC_P2C_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + EMIF_0_CONN_TO_CALIP + CALIP_0 + + + EMIF_0_REF_CLK_SHARING + EXPORTED + + + EMIF_0_STORED_PARAM + + + + EMIF_10_CONN_TO_CALIP + CALIP_0 + + + EMIF_10_REF_CLK_SHARING + EXPORTED + + + EMIF_10_STORED_PARAM + + + + EMIF_11_CONN_TO_CALIP + CALIP_0 + + + EMIF_11_REF_CLK_SHARING + EXPORTED + + + EMIF_11_STORED_PARAM + + + + EMIF_12_CONN_TO_CALIP + CALIP_0 + + + EMIF_12_REF_CLK_SHARING + EXPORTED + + + EMIF_12_STORED_PARAM + + + + EMIF_13_CONN_TO_CALIP + CALIP_0 + + + EMIF_13_REF_CLK_SHARING + EXPORTED + + + EMIF_13_STORED_PARAM + + + + EMIF_14_CONN_TO_CALIP + CALIP_0 + + + EMIF_14_REF_CLK_SHARING + EXPORTED + + + EMIF_14_STORED_PARAM + + + + EMIF_15_CONN_TO_CALIP + CALIP_0 + + + EMIF_15_REF_CLK_SHARING + EXPORTED + + + EMIF_15_STORED_PARAM + + + + EMIF_1_CONN_TO_CALIP + CALIP_0 + + + EMIF_1_REF_CLK_SHARING + EXPORTED + + + EMIF_1_STORED_PARAM + + + + EMIF_2_CONN_TO_CALIP + CALIP_0 + + + EMIF_2_REF_CLK_SHARING + EXPORTED + + + EMIF_2_STORED_PARAM + + + + EMIF_3_CONN_TO_CALIP + CALIP_0 + + + EMIF_3_REF_CLK_SHARING + EXPORTED + + + EMIF_3_STORED_PARAM + + + + EMIF_4_CONN_TO_CALIP + CALIP_0 + + + EMIF_4_REF_CLK_SHARING + EXPORTED + + + EMIF_4_STORED_PARAM + + + + EMIF_5_CONN_TO_CALIP + CALIP_0 + + + EMIF_5_REF_CLK_SHARING + EXPORTED + + + EMIF_5_STORED_PARAM + + + + EMIF_6_CONN_TO_CALIP + CALIP_0 + + + EMIF_6_REF_CLK_SHARING + EXPORTED + + + EMIF_6_STORED_PARAM + + + + EMIF_7_CONN_TO_CALIP + CALIP_0 + + + EMIF_7_REF_CLK_SHARING + EXPORTED + + + EMIF_7_STORED_PARAM + + + + EMIF_8_CONN_TO_CALIP + CALIP_0 + + + EMIF_8_REF_CLK_SHARING + EXPORTED + + + EMIF_8_STORED_PARAM + + + + EMIF_9_CONN_TO_CALIP + CALIP_0 + + + EMIF_9_REF_CLK_SHARING + EXPORTED + + + EMIF_9_STORED_PARAM + + + + ENABLE_RD_TYPE + false + + + EX_DESIGN_GUI_DDR3_GEN_BSI + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + false + + + EX_DESIGN_GUI_DDR3_GEN_SIM + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_GEN_BSI + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + false + + + EX_DESIGN_GUI_DDR4_GEN_SIM + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_GEN_BSI + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + false + + + EX_DESIGN_GUI_DDRT_GEN_SIM + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_GEN_BSI + false + + + EX_DESIGN_GUI_GEN_CDC + false + + + EX_DESIGN_GUI_GEN_SIM + true + + + EX_DESIGN_GUI_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + false + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_GEN_BSI + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + false + + + EX_DESIGN_GUI_QDR2_GEN_SIM + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_GEN_BSI + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + false + + + EX_DESIGN_GUI_QDR4_GEN_SIM + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_GEN_BSI + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + false + + + EX_DESIGN_GUI_RLD2_GEN_SIM + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_GEN_BSI + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + false + + + EX_DESIGN_GUI_RLD3_GEN_SIM + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + FAMILY_ENUM + FAMILY_AGILEX + + + GENERATE_PHYLITE + false + + + HMC_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_ST + + + HMC_CTRL_DIMM_TYPE + dimm_type_rdimm + + + HMC_READY_LATENCY + 2 + + + HMC_TIDS_0 + 676600325 + + + HMC_TIDS_1 + 3 + + + HMC_TIDS_2 + 0 + + + HMC_TIDS_AUTOGEN_WCNT + 3 + + + HPRX_CTLE_EN + on + + + HPRX_OFFSET_CAL + true + + + INTERNAL_TESTING_MODE + false + + + IS_ED_SLAVE + false + + + IS_HPS + false + + + LANES_PER_TILE + 4 + + + LANES_USAGE_0 + 757373805 + + + LANES_USAGE_1 + 365 + + + LANES_USAGE_2 + 0 + + + LANES_USAGE_3 + 0 + + + LANES_USAGE_AUTOGEN_WCNT + 4 + + + LANE_C2P_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + LANE_HIPI_DELAY + 350 + + + LANE_P2C_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + LANE_PIN_USAGE_0 + 20058385 + + + LANE_PIN_USAGE_1 + 71582788 + + + LANE_PIN_USAGE_10 + 67388484 + + + LANE_PIN_USAGE_11 + 17 + + + LANE_PIN_USAGE_12 + 285213696 + + + LANE_PIN_USAGE_13 + 67422276 + + + LANE_PIN_USAGE_14 + 554766609 + + + LANE_PIN_USAGE_15 + 71581772 + + + LANE_PIN_USAGE_16 + 20058385 + + + LANE_PIN_USAGE_17 + 71582788 + + + LANE_PIN_USAGE_18 + 286266145 + + + LANE_PIN_USAGE_19 + 209994820 + + + LANE_PIN_USAGE_2 + 286266145 + + + LANE_PIN_USAGE_20 + 1118465 + + + LANE_PIN_USAGE_21 + 0 + + + LANE_PIN_USAGE_22 + 0 + + + LANE_PIN_USAGE_23 + 0 + + + LANE_PIN_USAGE_24 + 0 + + + LANE_PIN_USAGE_25 + 0 + + + LANE_PIN_USAGE_26 + 0 + + + LANE_PIN_USAGE_27 + 0 + + + LANE_PIN_USAGE_28 + 0 + + + LANE_PIN_USAGE_29 + 0 + + + LANE_PIN_USAGE_3 + 209994820 + + + LANE_PIN_USAGE_30 + 0 + + + LANE_PIN_USAGE_31 + 0 + + + LANE_PIN_USAGE_32 + 0 + + + LANE_PIN_USAGE_33 + 0 + + + LANE_PIN_USAGE_34 + 0 + + + LANE_PIN_USAGE_35 + 0 + + + LANE_PIN_USAGE_36 + 0 + + + LANE_PIN_USAGE_37 + 0 + + + LANE_PIN_USAGE_38 + 0 + + + LANE_PIN_USAGE_39 + 0 + + + LANE_PIN_USAGE_4 + 286331137 + + + LANE_PIN_USAGE_40 + 0 + + + LANE_PIN_USAGE_41 + 0 + + + LANE_PIN_USAGE_42 + 0 + + + LANE_PIN_USAGE_43 + 0 + + + LANE_PIN_USAGE_44 + 0 + + + LANE_PIN_USAGE_45 + 0 + + + LANE_PIN_USAGE_46 + 0 + + + LANE_PIN_USAGE_47 + 0 + + + LANE_PIN_USAGE_48 + 0 + + + LANE_PIN_USAGE_49 + 0 + + + LANE_PIN_USAGE_5 + 67422276 + + + LANE_PIN_USAGE_50 + 0 + + + LANE_PIN_USAGE_51 + 0 + + + LANE_PIN_USAGE_6 + 71581969 + + + LANE_PIN_USAGE_7 + 269828353 + + + LANE_PIN_USAGE_8 + 71582788 + + + LANE_PIN_USAGE_9 + 69905 + + + LANE_PIN_USAGE_AUTOGEN_WCNT + 52 + + + LANE_TIDS_0 + 403177984 + + + LANE_TIDS_1 + 168067584 + + + LANE_TIDS_2 + 35717208 + + + LANE_TIDS_3 + 140518930 + + + LANE_TIDS_4 + 886403 + + + LANE_TIDS_5 + 0 + + + LANE_TIDS_6 + 0 + + + LANE_TIDS_7 + 0 + + + LANE_TIDS_8 + 0 + + + LANE_TIDS_9 + 0 + + + LANE_TIDS_AUTOGEN_WCNT + 10 + + + MEM_BURST_LENGTH + 8 + + + MEM_DATA_MASK_EN + true + + + MEM_DDR3_AC_PAR_EN + false + + + MEM_DDR3_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR3_ADDR_WIDTH + 1 + + + MEM_DDR3_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ASR_ENUM + DDR3_ASR_MANUAL + + + MEM_DDR3_ATCL_ENUM + DDR3_ATCL_DISABLED + + + MEM_DDR3_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_BL_ENUM + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_CFG_GEN_DBE + false + + + MEM_DDR3_CFG_GEN_SBE + false + + + MEM_DDR3_CKE_PER_DIMM + 1 + + + MEM_DDR3_CKE_WIDTH + 1 + + + MEM_DDR3_CK_WIDTH + 1 + + + MEM_DDR3_COL_ADDR_WIDTH + 10 + + + MEM_DDR3_CS_PER_DIMM + 1 + + + MEM_DDR3_CS_WIDTH + 1 + + + MEM_DDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR3_DLL_EN + true + + + MEM_DDR3_DM_EN + true + + + MEM_DDR3_DM_WIDTH + 1 + + + MEM_DDR3_DQS_WIDTH + 8 + + + MEM_DDR3_DQ_PER_DQS + 8 + + + MEM_DDR3_DQ_WIDTH + 72 + + + MEM_DDR3_DRV_STR_ENUM + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_FORMAT_ENUM + MEM_FORMAT_UDIMM + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + 000000000000000000 + + + MEM_DDR3_MIRROR_ADDRESSING_EN + true + + + MEM_DDR3_MR0 + 0 + + + MEM_DDR3_MR1 + 0 + + + MEM_DDR3_MR2 + 0 + + + MEM_DDR3_MR3 + 0 + + + MEM_DDR3_NUM_OF_DIMMS + 1 + + + MEM_DDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_ODT_WIDTH + 1 + + + MEM_DDR3_PD_ENUM + DDR3_PD_OFF + + + MEM_DDR3_RANKS_PER_DIMM + 1 + + + MEM_DDR3_RDIMM_CONFIG + 0000000000000000 + + + MEM_DDR3_RM_WIDTH + 0 + + + MEM_DDR3_ROW_ADDR_WIDTH + 15 + + + MEM_DDR3_RTT_NOM_ENUM + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_R_DERIVED_ODT0 + , + + + MEM_DDR3_R_DERIVED_ODT1 + , + + + MEM_DDR3_R_DERIVED_ODT2 + , + + + MEM_DDR3_R_DERIVED_ODT3 + , + + + MEM_DDR3_R_DERIVED_ODTN + , + + + MEM_DDR3_R_ODT0_1X1 + off + + + MEM_DDR3_R_ODT0_2X2 + off,off + + + MEM_DDR3_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR3_R_ODT1_2X2 + off,off + + + MEM_DDR3_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR3_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR3_R_ODTN_1X1 + Rank 0 + + + MEM_DDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR3_SPEEDBIN_ENUM + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_SRT_ENUM + DDR3_SRT_NORMAL + + + MEM_DDR3_TCL + 14 + + + MEM_DDR3_TDH_DC_MV + 100 + + + MEM_DDR3_TDH_PS + 55 + + + MEM_DDR3_TDQSCKDL + 1200 + + + MEM_DDR3_TDQSCKDM + 900 + + + MEM_DDR3_TDQSCKDS + 450 + + + MEM_DDR3_TDQSCK_DERV_PS + 2 + + + MEM_DDR3_TDQSCK_PS + 180 + + + MEM_DDR3_TDQSQ_PS + 75 + + + MEM_DDR3_TDQSS_CYC + 0.27 + + + MEM_DDR3_TDSH_CYC + 0.18 + + + MEM_DDR3_TDSS_CYC + 0.18 + + + MEM_DDR3_TDS_AC_MV + 135 + + + MEM_DDR3_TDS_PS + 53 + + + MEM_DDR3_TFAW_CYC + 27 + + + MEM_DDR3_TFAW_NS + 25.0 + + + MEM_DDR3_TIH_DC_MV + 100 + + + MEM_DDR3_TIH_PS + 95 + + + MEM_DDR3_TINIT_CK + 499 + + + MEM_DDR3_TINIT_US + 500 + + + MEM_DDR3_TIS_AC_MV + 135 + + + MEM_DDR3_TIS_PS + 60 + + + MEM_DDR3_TMRD_CK_CYC + 4 + + + MEM_DDR3_TQH_CYC + 0.38 + + + MEM_DDR3_TQSH_CYC + 0.4 + + + MEM_DDR3_TRAS_CYC + 36 + + + MEM_DDR3_TRAS_NS + 33.0 + + + MEM_DDR3_TRCD_CYC + 14 + + + MEM_DDR3_TRCD_NS + 13.09 + + + MEM_DDR3_TREFI_CYC + 8320 + + + MEM_DDR3_TREFI_US + 7.8 + + + MEM_DDR3_TRFC_CYC + 171 + + + MEM_DDR3_TRFC_NS + 160.0 + + + MEM_DDR3_TRP_CYC + 14 + + + MEM_DDR3_TRP_NS + 13.09 + + + MEM_DDR3_TRRD_CYC + 6 + + + MEM_DDR3_TRTP_CYC + 8 + + + MEM_DDR3_TTL_ADDR_WIDTH + 1 + + + MEM_DDR3_TTL_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_TTL_CKE_WIDTH + 1 + + + MEM_DDR3_TTL_CK_WIDTH + 1 + + + MEM_DDR3_TTL_CS_WIDTH + 1 + + + MEM_DDR3_TTL_DM_WIDTH + 1 + + + MEM_DDR3_TTL_DQS_WIDTH + 8 + + + MEM_DDR3_TTL_DQ_WIDTH + 72 + + + MEM_DDR3_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_TTL_ODT_WIDTH + 1 + + + MEM_DDR3_TTL_RM_WIDTH + 0 + + + MEM_DDR3_TWLH_PS + 125.0 + + + MEM_DDR3_TWLS_PS + 125.0 + + + MEM_DDR3_TWR_CYC + 16 + + + MEM_DDR3_TWR_NS + 15.0 + + + MEM_DDR3_TWTR_CYC + 8 + + + MEM_DDR3_USE_DEFAULT_ODT + true + + + MEM_DDR3_WTCL + 10 + + + MEM_DDR3_W_DERIVED_ODT0 + , + + + MEM_DDR3_W_DERIVED_ODT1 + , + + + MEM_DDR3_W_DERIVED_ODT2 + , + + + MEM_DDR3_W_DERIVED_ODT3 + , + + + MEM_DDR3_W_DERIVED_ODTN + , + + + MEM_DDR3_W_ODT0_1X1 + on + + + MEM_DDR3_W_ODT0_2X2 + on,off + + + MEM_DDR3_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT1_2X2 + off,on + + + MEM_DDR3_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR3_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR3_W_ODTN_1X1 + Rank 0 + + + MEM_DDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_AC_PARITY_LATENCY + DDR4_AC_PARITY_LATENCY_DISABLE + + + MEM_DDR4_AC_PERSISTENT_ERROR + false + + + MEM_DDR4_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR4_ADDR_WIDTH + 17 + + + MEM_DDR4_ALERT_N_AC_LANE + 3 + + + MEM_DDR4_ALERT_N_AC_PIN + 8 + + + MEM_DDR4_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + + + MEM_DDR4_ALERT_PAR_EN + true + + + MEM_DDR4_ASR_ENUM + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_ATCL_ENUM + DDR4_ATCL_DISABLED + + + MEM_DDR4_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_BL_ENUM + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_CAL_MODE + 0 + + + MEM_DDR4_CFG_GEN_DBE + false + + + MEM_DDR4_CFG_GEN_SBE + false + + + MEM_DDR4_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_CKE_PER_DIMM + 1 + + + MEM_DDR4_CKE_WIDTH + 1 + + + MEM_DDR4_CK_WIDTH + 1 + + + MEM_DDR4_COL_ADDR_WIDTH + 10 + + + MEM_DDR4_CS_PER_DIMM + 1 + + + MEM_DDR4_CS_WIDTH + 1 + + + MEM_DDR4_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR4_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DEFAULT_VREFOUT + true + + + MEM_DDR4_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR4_DLL_EN + true + + + MEM_DDR4_DM_EN + true + + + MEM_DDR4_DQS_WIDTH + 9 + + + MEM_DDR4_DQ_PER_DQS + 8 + + + MEM_DDR4_DQ_WIDTH + 72 + + + MEM_DDR4_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_DDR4_GEARDOWN + DDR4_GEARDOWN_HR + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR4_IDEAL_VREF_IN_PCT + 68.0 + + + MEM_DDR4_IDEAL_VREF_OUT_PCT + 70.0 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP + RTT_NOM disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP + RTT_PARK disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP + RZQ/3 (80 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM + DDR4_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP + ODT Disabled + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM + DDR4_RTT_PARK_RZQ_4 + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP + RZQ/4 (60 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP + Dynamic ODT off + + + MEM_DDR4_INTEL_DEFAULT_TERM + true + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDR4_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + + + + MEM_DDR4_MAX_POWERDOWN + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + true + + + MEM_DDR4_MPR_READ_FORMAT + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MR0 + 2164 + + + MEM_DDR4_MR1 + 65537 + + + MEM_DDR4_MR2 + 131112 + + + MEM_DDR4_MR3 + 197632 + + + MEM_DDR4_MR4 + 264192 + + + MEM_DDR4_MR5 + 332896 + + + MEM_DDR4_MR6 + 395279 + + + MEM_DDR4_NUM_OF_DIMMS + 1 + + + MEM_DDR4_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_ODT_IN_POWERDOWN + true + + + MEM_DDR4_ODT_WIDTH + 1 + + + MEM_DDR4_PER_DRAM_ADDR + false + + + MEM_DDR4_RANKS_PER_DIMM + 1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_COMMAND_LATENCY + 1 + + + MEM_DDR4_RCD_CS_IBT_ENUM + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_RCD_PARITY_CONTROL_WORD + 13 + + + MEM_DDR4_RDIMM_CONFIG + 00000020000000003900000D40030B0F556000 + + + MEM_DDR4_READ_DBI + true + + + MEM_DDR4_READ_PREAMBLE + 2 + + + MEM_DDR4_READ_PREAMBLE_TRAINING + false + + + MEM_DDR4_RM_WIDTH + 0 + + + MEM_DDR4_ROW_ADDR_WIDTH + 16 + + + MEM_DDR4_RTT_NOM_ENUM + DDR4_RTT_NOM_RZQ_4 + + + MEM_DDR4_RTT_PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_R_DERIVED_BODT0 + + + + MEM_DDR4_R_DERIVED_BODT1 + + + + MEM_DDR4_R_DERIVED_BODTN + + + + MEM_DDR4_R_DERIVED_ODT0 + (Drive) RZQ/7 (34 Ohm),-,-,- + + + MEM_DDR4_R_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_R_ODT0_1X1 + off + + + MEM_DDR4_R_ODT0_2X2 + off,off + + + MEM_DDR4_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR4_R_ODT1_2X2 + off,off + + + MEM_DDR4_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR4_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR4_R_ODTN_1X1 + Rank 0 + + + MEM_DDR4_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_SELF_RFSH_ABORT + false + + + MEM_DDR4_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR4_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDR4_SPD_135_RCD_REV + 0 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + 101 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDR4_SPD_139_DB_REV + 0 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + 0 + + + MEM_DDR4_SPEEDBIN_ENUM + DDR4_SPEEDBIN_2666 + + + MEM_DDR4_TCCD_L_CYC + 6 + + + MEM_DDR4_TCCD_S_CYC + 4 + + + MEM_DDR4_TCL + 21 + + + MEM_DDR4_TDIVW_DJ_CYC + 0.1 + + + MEM_DDR4_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDR4_TDQSCKDL + 1200 + + + MEM_DDR4_TDQSCKDM + 900 + + + MEM_DDR4_TDQSCKDS + 450 + + + MEM_DDR4_TDQSCK_DERV_PS + 2 + + + MEM_DDR4_TDQSCK_PS + 175 + + + MEM_DDR4_TDQSQ_PS + 66 + + + MEM_DDR4_TDQSQ_UI + 0.14 + + + MEM_DDR4_TDQSS_CYC + 0.27 + + + MEM_DDR4_TDSH_CYC + 0.18 + + + MEM_DDR4_TDSS_CYC + 0.18 + + + MEM_DDR4_TDVWP_UI + 0.72 + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_SENSOR_READOUT + false + + + MEM_DDR4_TFAW_CYC + 26 + + + MEM_DDR4_TFAW_DLR_CYC + 16 + + + MEM_DDR4_TFAW_NS + 21.0 + + + MEM_DDR4_TIH_DC_MV + 75 + + + MEM_DDR4_TIH_PS + 87 + + + MEM_DDR4_TINIT_CK + 600000 + + + MEM_DDR4_TINIT_US + 500 + + + MEM_DDR4_TIS_AC_MV + 100 + + + MEM_DDR4_TIS_PS + 62 + + + MEM_DDR4_TMRD_CK_CYC + 8 + + + MEM_DDR4_TQH_CYC + 0.38 + + + MEM_DDR4_TQH_UI + 0.74 + + + MEM_DDR4_TQSH_CYC + 0.4 + + + MEM_DDR4_TRAS_CYC + 39 + + + MEM_DDR4_TRAS_NS + 32.0 + + + MEM_DDR4_TRCD_CYC + 17 + + + MEM_DDR4_TRCD_NS + 14.16 + + + MEM_DDR4_TREFI_CYC + 9360 + + + MEM_DDR4_TREFI_US + 7.8 + + + MEM_DDR4_TRFC_CYC + 420 + + + MEM_DDR4_TRFC_DLR_CYC + 108 + + + MEM_DDR4_TRFC_DLR_NS + 90.0 + + + MEM_DDR4_TRFC_NS + 350.0 + + + MEM_DDR4_TRP_CYC + 17 + + + MEM_DDR4_TRP_NS + 14.16 + + + MEM_DDR4_TRRD_DLR_CYC + 4 + + + MEM_DDR4_TRRD_L_CYC + 6 + + + MEM_DDR4_TRRD_S_CYC + 4 + + + MEM_DDR4_TRTP_CYC + 9 + + + MEM_DDR4_TTL_ADDR_WIDTH + 17 + + + MEM_DDR4_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_TTL_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_TTL_CKE_WIDTH + 1 + + + MEM_DDR4_TTL_CK_WIDTH + 1 + + + MEM_DDR4_TTL_CS_WIDTH + 1 + + + MEM_DDR4_TTL_DQS_WIDTH + 9 + + + MEM_DDR4_TTL_DQ_WIDTH + 72 + + + MEM_DDR4_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_TTL_ODT_WIDTH + 1 + + + MEM_DDR4_TTL_RM_WIDTH + 0 + + + MEM_DDR4_TWLH_CYC + 0.13 + + + MEM_DDR4_TWLH_PS + 0.0 + + + MEM_DDR4_TWLS_CYC + 0.13 + + + MEM_DDR4_TWLS_PS + 0.0 + + + MEM_DDR4_TWR_CYC + 18 + + + MEM_DDR4_TWR_NS + 15.0 + + + MEM_DDR4_TWTR_L_CYC + 9 + + + MEM_DDR4_TWTR_S_CYC + 3 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDR4_USE_DEFAULT_ODT + true + + + MEM_DDR4_VDIVW_TOTAL + 130 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_0 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP + Range 1 - 60% to 92.5% + + + MEM_DDR4_VREFDQ_TRAINING_VALUE + 70.0 + + + MEM_DDR4_WRITE_CMD_LATENCY + 6 + + + MEM_DDR4_WRITE_CRC + false + + + MEM_DDR4_WRITE_DBI + false + + + MEM_DDR4_WRITE_PREAMBLE + 1 + + + MEM_DDR4_WTCL + 16 + + + MEM_DDR4_W_DERIVED_BODT0 + + + + MEM_DDR4_W_DERIVED_BODT1 + + + + MEM_DDR4_W_DERIVED_BODTN + + + + MEM_DDR4_W_DERIVED_ODT0 + (Park) RZQ/4 (60 Ohm),-,-,- + + + MEM_DDR4_W_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_W_ODT0_1X1 + on + + + MEM_DDR4_W_ODT0_2X2 + on,off + + + MEM_DDR4_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT1_2X2 + off,on + + + MEM_DDR4_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR4_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR4_W_ODTN_1X1 + Rank 0 + + + MEM_DDR4_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_AC_PARITY_LATENCY + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_AC_PERSISTENT_ERROR + false + + + MEM_DDRT_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDRT_ADDR_WIDTH + 1 + + + MEM_DDRT_ALERT_N_AC_LANE + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + 0 + + + MEM_DDRT_ALERT_N_DQS_GROUP + 0 + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_PAR_EN + true + + + MEM_DDRT_ASR_ENUM + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_ATCL_ENUM + DDRT_ATCL_DISABLED + + + MEM_DDRT_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_BL_ENUM + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_CAL_MODE + 0 + + + MEM_DDRT_CFG_GEN_DBE + false + + + MEM_DDRT_CFG_GEN_SBE + false + + + MEM_DDRT_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_CKE_PER_DIMM + 1 + + + MEM_DDRT_CKE_WIDTH + 1 + + + MEM_DDRT_CK_WIDTH + 1 + + + MEM_DDRT_COL_ADDR_WIDTH + 10 + + + MEM_DDRT_CS_PER_DIMM + 1 + + + MEM_DDRT_CS_WIDTH + 1 + + + MEM_DDRT_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDRT_DB_DQ_DRV_ENUM + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_PARK_ENUM + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + true + + + MEM_DDRT_DEFAULT_PREAMBLE + true + + + MEM_DDRT_DEFAULT_VREFOUT + true + + + MEM_DDRT_DISCRETE_CS_WIDTH + 1 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDRT_DLL_EN + true + + + MEM_DDRT_DM_EN + false + + + MEM_DDRT_DQS_WIDTH + 8 + + + MEM_DDRT_DQ_PER_DQS + 4 + + + MEM_DDRT_DQ_WIDTH + 72 + + + MEM_DDRT_DRV_STR_ENUM + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ERID_WIDTH + 2 + + + MEM_DDRT_ERR_N_WIDTH + 1 + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_FORMAT_ENUM + MEM_FORMAT_LRDIMM + + + MEM_DDRT_GEARDOWN + DDRT_GEARDOWN_HR + + + MEM_DDRT_GNT_N_WIDTH + 1 + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + true + + + MEM_DDRT_I2C_DIMM_0_SA + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + 3 + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDRT_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + + + + MEM_DDRT_MAX_POWERDOWN + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + true + + + MEM_DDRT_MPR_READ_FORMAT + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MR0 + 0 + + + MEM_DDRT_MR1 + 0 + + + MEM_DDRT_MR2 + 0 + + + MEM_DDRT_MR3 + 0 + + + MEM_DDRT_MR4 + 0 + + + MEM_DDRT_MR5 + 0 + + + MEM_DDRT_MR6 + 0 + + + MEM_DDRT_NUM_OF_DIMMS + 1 + + + MEM_DDRT_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_ODT_IN_POWERDOWN + true + + + MEM_DDRT_ODT_WIDTH + 1 + + + MEM_DDRT_PARTIAL_WRITES + false + + + MEM_DDRT_PERSISTENT_MODE + 1 + + + MEM_DDRT_PER_DRAM_ADDR + false + + + MEM_DDRT_PWR_MODE + DDRT_PWR_MODE_12W + + + MEM_DDRT_RANKS_PER_DIMM + 1 + + + MEM_DDRT_RCD_CA_IBT_ENUM + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_COMMAND_LATENCY + 1 + + + MEM_DDRT_RCD_CS_IBT_ENUM + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_RCD_PARITY_CONTROL_WORD + 1 + + + MEM_DDRT_RDIMM_CONFIG + + + + MEM_DDRT_READ_DBI + false + + + MEM_DDRT_READ_PREAMBLE + 1 + + + MEM_DDRT_READ_PREAMBLE_TRAINING + false + + + MEM_DDRT_REQ_N_WIDTH + 1 + + + MEM_DDRT_RM_WIDTH + 0 + + + MEM_DDRT_ROW_ADDR_WIDTH + 18 + + + MEM_DDRT_RTT_NOM_ENUM + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_RTT_PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_RTT_WR_ENUM + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_R_DERIVED_BODT0 + + + + MEM_DDRT_R_DERIVED_BODT1 + + + + MEM_DDRT_R_DERIVED_BODTN + + + + MEM_DDRT_R_DERIVED_ODT0 + , + + + MEM_DDRT_R_DERIVED_ODT1 + , + + + MEM_DDRT_R_DERIVED_ODT2 + , + + + MEM_DDRT_R_DERIVED_ODT3 + , + + + MEM_DDRT_R_DERIVED_ODTN + , + + + MEM_DDRT_R_ODT0_1X1 + off + + + MEM_DDRT_R_ODT0_2X2 + off,off + + + MEM_DDRT_R_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_R_ODT0_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT1_2X2 + off,off + + + MEM_DDRT_R_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_R_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_R_ODTN_1X1 + Rank 0 + + + MEM_DDRT_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_SELF_RFSH_ABORT + false + + + MEM_DDRT_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDRT_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDRT_SPD_135_RCD_REV + 0 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDRT_SPD_139_DB_REV + 0 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDRT_SPEEDBIN_ENUM + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TCCD_L_CYC + 6 + + + MEM_DDRT_TCCD_S_CYC + 4 + + + MEM_DDRT_TCL + 15 + + + MEM_DDRT_TCL_ADDED + -1 + + + MEM_DDRT_TDIVW_DJ_CYC + 0.1 + + + MEM_DDRT_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDRT_TDQSCKDL + 1200 + + + MEM_DDRT_TDQSCKDM + 900 + + + MEM_DDRT_TDQSCKDS + 450 + + + MEM_DDRT_TDQSCK_DERV_PS + 2 + + + MEM_DDRT_TDQSCK_PS + 165 + + + MEM_DDRT_TDQSQ_PS + 66 + + + MEM_DDRT_TDQSQ_UI + 0.16 + + + MEM_DDRT_TDQSS_CYC + 0.27 + + + MEM_DDRT_TDSH_CYC + 0.18 + + + MEM_DDRT_TDSS_CYC + 0.18 + + + MEM_DDRT_TDVWP_UI + 0.72 + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_SENSOR_READOUT + false + + + MEM_DDRT_TFAW_CYC + 27 + + + MEM_DDRT_TFAW_DLR_CYC + 16 + + + MEM_DDRT_TFAW_NS + 21.0 + + + MEM_DDRT_TIH_DC_MV + 75 + + + MEM_DDRT_TIH_PS + 95 + + + MEM_DDRT_TINIT_CK + 499 + + + MEM_DDRT_TINIT_US + 500 + + + MEM_DDRT_TIS_AC_MV + 100 + + + MEM_DDRT_TIS_PS + 60 + + + MEM_DDRT_TMRD_CK_CYC + 8 + + + MEM_DDRT_TQH_CYC + 0.38 + + + MEM_DDRT_TQH_UI + 0.76 + + + MEM_DDRT_TQSH_CYC + 0.38 + + + MEM_DDRT_TRAS_CYC + 36 + + + MEM_DDRT_TRAS_NS + 32.0 + + + MEM_DDRT_TRCD_CYC + 14 + + + MEM_DDRT_TRCD_NS + 15.0 + + + MEM_DDRT_TREFI_CYC + 8320 + + + MEM_DDRT_TREFI_US + 7.8 + + + MEM_DDRT_TRFC_CYC + 171 + + + MEM_DDRT_TRFC_DLR_CYC + 109 + + + MEM_DDRT_TRFC_DLR_NS + 90.0 + + + MEM_DDRT_TRFC_NS + 260.0 + + + MEM_DDRT_TRP_CYC + 14 + + + MEM_DDRT_TRP_NS + 15.0 + + + MEM_DDRT_TRRD_DLR_CYC + 4 + + + MEM_DDRT_TRRD_L_CYC + 6 + + + MEM_DDRT_TRRD_S_CYC + 4 + + + MEM_DDRT_TRTP_CYC + 9 + + + MEM_DDRT_TTL_ADDR_WIDTH + 1 + + + MEM_DDRT_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_TTL_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_TTL_CKE_WIDTH + 1 + + + MEM_DDRT_TTL_CK_WIDTH + 1 + + + MEM_DDRT_TTL_CS_WIDTH + 1 + + + MEM_DDRT_TTL_DQS_WIDTH + 8 + + + MEM_DDRT_TTL_DQ_WIDTH + 72 + + + MEM_DDRT_TTL_ERID_WIDTH + 2 + + + MEM_DDRT_TTL_ERR_N_WIDTH + 1 + + + MEM_DDRT_TTL_GNT_N_WIDTH + 1 + + + MEM_DDRT_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDRT_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_TTL_ODT_WIDTH + 1 + + + MEM_DDRT_TTL_REQ_N_WIDTH + 1 + + + MEM_DDRT_TTL_RM_WIDTH + 0 + + + MEM_DDRT_TWLH_CYC + 0.13 + + + MEM_DDRT_TWLH_PS + 0.0 + + + MEM_DDRT_TWLS_CYC + 0.13 + + + MEM_DDRT_TWLS_PS + 0.0 + + + MEM_DDRT_TWR_CYC + 18 + + + MEM_DDRT_TWR_NS + 15.0 + + + MEM_DDRT_TWTR_L_CYC + 9 + + + MEM_DDRT_TWTR_S_CYC + 3 + + + MEM_DDRT_USER_READ_PREAMBLE + 1 + + + MEM_DDRT_USER_TCL_ADDED + 0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_USER_WRITE_PREAMBLE + 1 + + + MEM_DDRT_USER_WTCL_ADDED + 6 + + + MEM_DDRT_USE_DEFAULT_ODT + true + + + MEM_DDRT_VDIVW_TOTAL + 136 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE_DISP + Range 2 - 45% to 77.5% + + + MEM_DDRT_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_WRITE_CMD_LATENCY + 5 + + + MEM_DDRT_WRITE_CRC + false + + + MEM_DDRT_WRITE_DBI + false + + + MEM_DDRT_WRITE_PREAMBLE + 1 + + + MEM_DDRT_WTCL + 18 + + + MEM_DDRT_WTCL_ADDED + -1 + + + MEM_DDRT_W_DERIVED_BODT0 + + + + MEM_DDRT_W_DERIVED_BODT1 + + + + MEM_DDRT_W_DERIVED_BODTN + + + + MEM_DDRT_W_DERIVED_ODT0 + , + + + MEM_DDRT_W_DERIVED_ODT1 + , + + + MEM_DDRT_W_DERIVED_ODT2 + , + + + MEM_DDRT_W_DERIVED_ODT3 + , + + + MEM_DDRT_W_DERIVED_ODTN + , + + + MEM_DDRT_W_ODT0_1X1 + on + + + MEM_DDRT_W_ODT0_2X2 + on,off + + + MEM_DDRT_W_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_W_ODT0_4X4 + on,on,off,off + + + MEM_DDRT_W_ODT1_2X2 + off,on + + + MEM_DDRT_W_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_W_ODTN_1X1 + Rank 0 + + + MEM_DDRT_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_HAS_BSI_SUPPORT + true + + + MEM_HAS_SIM_SUPPORT + true + + + MEM_LPDDR3_ADDR_WIDTH + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + 3 + + + MEM_LPDDR3_BL + LPDDR3_BL_BL8 + + + MEM_LPDDR3_CKE_WIDTH + 1 + + + MEM_LPDDR3_CK_WIDTH + 1 + + + MEM_LPDDR3_COL_ADDR_WIDTH + 10 + + + MEM_LPDDR3_CS_WIDTH + 1 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_LPDDR3_DATA_LATENCY + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_LPDDR3_DM_EN + true + + + MEM_LPDDR3_DM_WIDTH + 1 + + + MEM_LPDDR3_DQODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_DQS_WIDTH + 1 + + + MEM_LPDDR3_DQ_PER_DQS + 8 + + + MEM_LPDDR3_DQ_WIDTH + 32 + + + MEM_LPDDR3_DRV_STR + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_LPDDR3_MR1 + 0 + + + MEM_LPDDR3_MR11 + 0 + + + MEM_LPDDR3_MR2 + 0 + + + MEM_LPDDR3_MR3 + 0 + + + MEM_LPDDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_LPDDR3_NWR + LPDDR3_NWR_NWR12 + + + MEM_LPDDR3_ODT_WIDTH + 1 + + + MEM_LPDDR3_PDODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_ROW_ADDR_WIDTH + 15 + + + MEM_LPDDR3_R_DERIVED_ODT0 + , + + + MEM_LPDDR3_R_DERIVED_ODT1 + , + + + MEM_LPDDR3_R_DERIVED_ODT2 + , + + + MEM_LPDDR3_R_DERIVED_ODT3 + , + + + MEM_LPDDR3_R_DERIVED_ODTN + , + + + MEM_LPDDR3_R_ODT0_1X1 + off + + + MEM_LPDDR3_R_ODT0_2X2 + off,off + + + MEM_LPDDR3_R_ODT0_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_2X2 + off,off + + + MEM_LPDDR3_R_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_LPDDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_LPDDR3_SPEEDBIN_ENUM + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TDH_DC_MV + 100 + + + MEM_LPDDR3_TDH_PS + 100 + + + MEM_LPDDR3_TDQSCKDL + 614 + + + MEM_LPDDR3_TDQSCKDM + 511 + + + MEM_LPDDR3_TDQSCKDS + 220 + + + MEM_LPDDR3_TDQSCK_DERV_PS + 2 + + + MEM_LPDDR3_TDQSCK_PS + 5500 + + + MEM_LPDDR3_TDQSQ_PS + 135 + + + MEM_LPDDR3_TDQSS_CYC + 1.25 + + + MEM_LPDDR3_TDSH_CYC + 0.2 + + + MEM_LPDDR3_TDSS_CYC + 0.2 + + + MEM_LPDDR3_TDS_AC_MV + 150 + + + MEM_LPDDR3_TDS_PS + 75 + + + MEM_LPDDR3_TFAW_CYC + 40 + + + MEM_LPDDR3_TFAW_NS + 50.0 + + + MEM_LPDDR3_TIH_DC_MV + 100 + + + MEM_LPDDR3_TIH_PS + 100 + + + MEM_LPDDR3_TINIT_CK + 499 + + + MEM_LPDDR3_TINIT_US + 500 + + + MEM_LPDDR3_TIS_AC_MV + 150 + + + MEM_LPDDR3_TIS_PS + 75 + + + MEM_LPDDR3_TMRR_CK_CYC + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + 10 + + + MEM_LPDDR3_TQH_CYC + 0.38 + + + MEM_LPDDR3_TQSH_CYC + 0.38 + + + MEM_LPDDR3_TRAS_CYC + 34 + + + MEM_LPDDR3_TRAS_NS + 42.5 + + + MEM_LPDDR3_TRCD_CYC + 17 + + + MEM_LPDDR3_TRCD_NS + 18.0 + + + MEM_LPDDR3_TREFI_CYC + 3120 + + + MEM_LPDDR3_TREFI_US + 3.9 + + + MEM_LPDDR3_TRFC_CYC + 168 + + + MEM_LPDDR3_TRFC_NS + 210.0 + + + MEM_LPDDR3_TRL_CYC + 10 + + + MEM_LPDDR3_TRP_CYC + 17 + + + MEM_LPDDR3_TRP_NS + 18.0 + + + MEM_LPDDR3_TRRD_CYC + 8 + + + MEM_LPDDR3_TRTP_CYC + 6 + + + MEM_LPDDR3_TWLH_PS + 175.0 + + + MEM_LPDDR3_TWLS_PS + 175.0 + + + MEM_LPDDR3_TWL_CYC + 6 + + + MEM_LPDDR3_TWR_CYC + 12 + + + MEM_LPDDR3_TWR_NS + 15.0 + + + MEM_LPDDR3_TWTR_CYC + 6 + + + MEM_LPDDR3_USE_DEFAULT_ODT + true + + + MEM_LPDDR3_WLSELECT + Set A + + + MEM_LPDDR3_W_DERIVED_ODT0 + , + + + MEM_LPDDR3_W_DERIVED_ODT1 + , + + + MEM_LPDDR3_W_DERIVED_ODT2 + , + + + MEM_LPDDR3_W_DERIVED_ODT3 + , + + + MEM_LPDDR3_W_DERIVED_ODTN + , + + + MEM_LPDDR3_W_ODT0_1X1 + on + + + MEM_LPDDR3_W_ODT0_2X2 + on,on + + + MEM_LPDDR3_W_ODT0_4X4 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_2X2 + off,off + + + MEM_LPDDR3_W_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_NUM_OF_DATA_ENDPOINTS + 1 + + + MEM_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_QDR2_ADDR_WIDTH + 19 + + + MEM_QDR2_BL + 4 + + + MEM_QDR2_BWS_EN + true + + + MEM_QDR2_BWS_N_PER_DEVICE + 4 + + + MEM_QDR2_BWS_N_WIDTH + 4 + + + MEM_QDR2_CQ_WIDTH + 1 + + + MEM_QDR2_DATA_PER_DEVICE + 36 + + + MEM_QDR2_DATA_WIDTH + 36 + + + MEM_QDR2_DEVICE_WIDTH + 1 + + + MEM_QDR2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR2_INTERNAL_JITTER_NS + 0.08 + + + MEM_QDR2_K_WIDTH + 1 + + + MEM_QDR2_SPEEDBIN_ENUM + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TCCQO_NS + 0.45 + + + MEM_QDR2_TCQDOH_NS + -0.09 + + + MEM_QDR2_TCQD_NS + 0.09 + + + MEM_QDR2_TCQH_NS + 0.71 + + + MEM_QDR2_THA_NS + 0.18 + + + MEM_QDR2_THD_NS + 0.18 + + + MEM_QDR2_TRL_CYC + 2.5 + + + MEM_QDR2_TSA_NS + 0.23 + + + MEM_QDR2_TSD_NS + 0.23 + + + MEM_QDR2_TWL_CYC + 1 + + + MEM_QDR2_WIDTH_EXPANDED + false + + + MEM_QDR4_AC_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_ADDR_INV_ENA + false + + + MEM_QDR4_ADDR_WIDTH + 21 + + + MEM_QDR4_AVL_CHNLS + 8 + + + MEM_QDR4_BL + 2 + + + MEM_QDR4_CK_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_CR0 + 0 + + + MEM_QDR4_CR1 + 0 + + + MEM_QDR4_CR2 + 0 + + + MEM_QDR4_DATA_INV_ENA + true + + + MEM_QDR4_DATA_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_DEVICE_DEPTH + 1 + + + MEM_QDR4_DEVICE_WIDTH + 1 + + + MEM_QDR4_DINV_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DINV_WIDTH + 4 + + + MEM_QDR4_DK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DK_WIDTH + 4 + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + 36 + + + MEM_QDR4_DQ_PER_PORT_WIDTH + 36 + + + MEM_QDR4_DQ_PER_RD_GROUP + 18 + + + MEM_QDR4_DQ_PER_WR_GROUP + 18 + + + MEM_QDR4_DQ_WIDTH + 72 + + + MEM_QDR4_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR4_MEM_TYPE_ENUM + MEM_XP + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_QK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_QK_WIDTH + 4 + + + MEM_QDR4_SKIP_ODT_SWEEPING + true + + + MEM_QDR4_SPEEDBIN_ENUM + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TASH_PS + 170 + + + MEM_QDR4_TCKDK_MAX_PS + 150 + + + MEM_QDR4_TCKDK_MIN_PS + -150 + + + MEM_QDR4_TCKQK_MAX_PS + 225 + + + MEM_QDR4_TCSH_PS + 170 + + + MEM_QDR4_TISH_PS + 150 + + + MEM_QDR4_TQH_CYC + 0.4 + + + MEM_QDR4_TQKQ_MAX_PS + 75 + + + MEM_QDR4_TRL_CYC + 8 + + + MEM_QDR4_TWL_CYC + 5 + + + MEM_QDR4_USE_ADDR_PARITY + false + + + MEM_QDR4_WIDTH_EXPANDED + false + + + MEM_READ_LATENCY + 23.0 + + + MEM_RLD2_ADDR_WIDTH + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + 3 + + + MEM_RLD2_BL + 4 + + + MEM_RLD2_CONFIG_ENUM + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_CS_WIDTH + 1 + + + MEM_RLD2_DEVICE_DEPTH + 1 + + + MEM_RLD2_DEVICE_WIDTH + 1 + + + MEM_RLD2_DK_WIDTH + 1 + + + MEM_RLD2_DM_EN + true + + + MEM_RLD2_DM_WIDTH + 1 + + + MEM_RLD2_DQ_PER_DEVICE + 9 + + + MEM_RLD2_DQ_PER_RD_GROUP + 9 + + + MEM_RLD2_DQ_PER_WR_GROUP + 9 + + + MEM_RLD2_DQ_WIDTH + 9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD2_MR + 0 + + + MEM_RLD2_ODT_MODE_ENUM + RLD2_ODT_ON + + + MEM_RLD2_QK_WIDTH + 1 + + + MEM_RLD2_REFRESH_INTERVAL_US + 0.24 + + + MEM_RLD2_SPEEDBIN_ENUM + RLD2_SPEEDBIN_18 + + + MEM_RLD2_TAH_NS + 0.3 + + + MEM_RLD2_TAS_NS + 0.3 + + + MEM_RLD2_TCKDK_MAX_NS + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + -0.3 + + + MEM_RLD2_TCKH_CYC + 0.45 + + + MEM_RLD2_TCKQK_MAX_NS + 0.2 + + + MEM_RLD2_TDH_NS + 0.17 + + + MEM_RLD2_TDS_NS + 0.17 + + + MEM_RLD2_TQKH_HCYC + 0.9 + + + MEM_RLD2_TQKQ_MAX_NS + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + -0.12 + + + MEM_RLD2_TRC + 8 + + + MEM_RLD2_TRL + 8 + + + MEM_RLD2_TWL + 9 + + + MEM_RLD2_WIDTH_EXPANDED + false + + + MEM_RLD3_ADDR_WIDTH + 20 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + RLD3_AREF_BAC + + + MEM_RLD3_BANK_ADDR_WIDTH + 4 + + + MEM_RLD3_BL + 2 + + + MEM_RLD3_CS_WIDTH + 1 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + RLD3_DL_RL16_WL17 + + + MEM_RLD3_DEPTH_EXPANDED + false + + + MEM_RLD3_DEVICE_DEPTH + 1 + + + MEM_RLD3_DEVICE_WIDTH + 1 + + + MEM_RLD3_DK_WIDTH + 2 + + + MEM_RLD3_DM_EN + true + + + MEM_RLD3_DM_WIDTH + 2 + + + MEM_RLD3_DQ_PER_DEVICE + 36 + + + MEM_RLD3_DQ_PER_RD_GROUP + 9 + + + MEM_RLD3_DQ_PER_WR_GROUP + 18 + + + MEM_RLD3_DQ_WIDTH + 36 + + + MEM_RLD3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD3_MR0 + 0 + + + MEM_RLD3_MR1 + 0 + + + MEM_RLD3_MR2 + 0 + + + MEM_RLD3_ODT_MODE_ENUM + RLD3_ODT_40 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_QK_WIDTH + 4 + + + MEM_RLD3_SPEEDBIN_ENUM + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TCKDK_MAX_CYC + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + 135 + + + MEM_RLD3_TDH_DC_MV + 100 + + + MEM_RLD3_TDH_PS + 5 + + + MEM_RLD3_TDS_AC_MV + 150 + + + MEM_RLD3_TDS_PS + -30 + + + MEM_RLD3_TIH_DC_MV + 100 + + + MEM_RLD3_TIH_PS + 65 + + + MEM_RLD3_TIS_AC_MV + 150 + + + MEM_RLD3_TIS_PS + 85 + + + MEM_RLD3_TQH_CYC + 0.38 + + + MEM_RLD3_TQKQ_MAX_PS + 75 + + + MEM_RLD3_T_RC_MODE_ENUM + RLD3_TRC_9 + + + MEM_RLD3_WIDTH_EXPANDED + false + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + RLD3_WRITE_1BANK + + + MEM_TTL_DATA_WIDTH + 72 + + + MEM_TTL_NUM_OF_READ_GROUPS + 9 + + + MEM_TTL_NUM_OF_WRITE_GROUPS + 9 + + + MEM_WRITE_LATENCY + 18 + + + MMR_C2P_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + MMR_HIPI_DELAY + 350 + + + MMR_P2C_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + NUM_IPS + 1 + + + NUM_IPS_SAVED + 0 + + + NUM_OF_HMC_PORTS + 1 + + + NUM_OF_RTL_TILES + 4 + + + OCT_CONTROL_WIDTH + 16 + + + OCT_SIZE + 3 + + + PHY_AC_CALIBRATED_OCT + true + + + PHY_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CALIBRATED_OCT + true + + + PHY_CK_CALIBRATED_OCT + true + + + PHY_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CLAMSHELL_EN + false + + + PHY_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DATA_CALIBRATED_OCT + true + + + PHY_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DATA_OUT_SLEW_RATE_ENUM + + + + PHY_DDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_AC_IO_STD_ENUM + unset + + + PHY_DDR3_AC_MODE_ENUM + unset + + + PHY_DDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_CAL_ADDR0 + 0 + + + PHY_DDR3_CAL_ADDR1 + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + false + + + PHY_DDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_CK_IO_STD_ENUM + unset + + + PHY_DDR3_CK_MODE_ENUM + unset + + + PHY_DDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR3_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_DEFAULT_IO + true + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR3_IO_VOLTAGE + 1.5 + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_DDR3_MIMIC_HPS_EMIF + false + + + PHY_DDR3_PING_PONG_EN + false + + + PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_RATE_ENUM + RATE_QUARTER + + + PHY_DDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR3_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_STARTING_VREFIN + 70.0 + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_PING_PONG_EN + false + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_DDR4_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_AC_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_ALLOW_72_DQ_WIDTH + false + + + PHY_DDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_CK_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_CLAMSHELL_EN + false + + + PHY_DDR4_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR4_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DDR4_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_DEFAULT_IO + false + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR4_IO_VOLTAGE + 1.2 + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDR4_MIMIC_HPS_EMIF + false + + + PHY_DDR4_PING_PONG_EN + false + + + PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_RATE_ENUM + RATE_QUARTER + + + PHY_DDR4_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR4_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_STARTING_VREFIN + 68.0 + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_CLAMSHELL_EN + false + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_USER_PING_PONG_EN + false + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_2CH_EN + false + + + PHY_DDRT_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_AC_IO_STD_ENUM + unset + + + PHY_DDRT_AC_MODE_ENUM + unset + + + PHY_DDRT_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_CK_IO_STD_ENUM + unset + + + PHY_DDRT_CK_MODE_ENUM + unset + + + PHY_DDRT_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDRT_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_DEFAULT_IO + true + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDRT_EXPORT_CLK_STP_IF + false + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDRT_I2C_USE_SMC + false + + + PHY_DDRT_IC_EN + true + + + PHY_DDRT_IO_VOLTAGE + 1.2 + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDRT_MIMIC_HPS_EMIF + false + + + PHY_DDRT_PING_PONG_EN + false + + + PHY_DDRT_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_RATE_ENUM + RATE_QUARTER + + + PHY_DDRT_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDRT_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_IO_STD_ENUM + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_USER_PING_PONG_EN + false + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + false + + + PHY_DLL_CORE_UPDN_EN + false + + + PHY_FPGA_SPEEDGRADE_GUI + E2V (ES3) - change device under 'View'->'Device Family' + + + PHY_HMC_CLK_RATIO + 2 + + + PHY_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_AC_MODE_ENUM + unset + + + PHY_LPDDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_CK_MODE_ENUM + unset + + + PHY_LPDDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_LPDDR3_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_DEFAULT_IO + true + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_IO_VOLTAGE + 1.2 + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + 800.0 + + + PHY_LPDDR3_MIMIC_HPS_EMIF + false + + + PHY_LPDDR3_PING_PONG_EN + false + + + PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_RATE_ENUM + RATE_QUARTER + + + PHY_LPDDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_LPDDR3_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_STARTING_VREFIN + 70.0 + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_PING_PONG_EN + false + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_MIMIC_HPS_EMIF + false + + + PHY_PERIODIC_OCT_RECAL + false + + + PHY_PING_PONG_EN + false + + + PHY_QDR2_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_AC_IO_STD_ENUM + unset + + + PHY_QDR2_AC_MODE_ENUM + unset + + + PHY_QDR2_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_CK_IO_STD_ENUM + unset + + + PHY_QDR2_CK_MODE_ENUM + unset + + + PHY_QDR2_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR2_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_DEFAULT_IO + true + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR2_IO_VOLTAGE + 1.5 + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + 633.333 + + + PHY_QDR2_MIMIC_HPS_EMIF + false + + + PHY_QDR2_PING_PONG_EN + false + + + PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_RATE_ENUM + RATE_HALF + + + PHY_QDR2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR2_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_STARTING_VREFIN + 70.0 + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_PING_PONG_EN + false + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_USER_STARTING_VREFIN + 70.0 + + + PHY_QDR4_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_AC_IO_STD_ENUM + unset + + + PHY_QDR4_AC_MODE_ENUM + unset + + + PHY_QDR4_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_CK_IO_STD_ENUM + unset + + + PHY_QDR4_CK_MODE_ENUM + unset + + + PHY_QDR4_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR4_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_DEFAULT_IO + true + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR4_IO_VOLTAGE + 1.2 + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_QDR4_MIMIC_HPS_EMIF + false + + + PHY_QDR4_PING_PONG_EN + false + + + PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_RATE_ENUM + RATE_QUARTER + + + PHY_QDR4_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR4_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_STARTING_VREFIN + 70.0 + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_PING_PONG_EN + false + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_RATE_ENUM + RATE_QUARTER + + + PHY_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_AC_IO_STD_ENUM + unset + + + PHY_RLD2_AC_MODE_ENUM + unset + + + PHY_RLD2_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_CK_IO_STD_ENUM + unset + + + PHY_RLD2_CK_MODE_ENUM + unset + + + PHY_RLD2_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD2_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_DEFAULT_IO + true + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD2_IO_VOLTAGE + 1.8 + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + 533.333 + + + PHY_RLD2_MIMIC_HPS_EMIF + false + + + PHY_RLD2_PING_PONG_EN + false + + + PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_RATE_ENUM + RATE_HALF + + + PHY_RLD2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_STARTING_VREFIN + 70.0 + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_PING_PONG_EN + false + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_USER_STARTING_VREFIN + 70.0 + + + PHY_RLD3_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_AC_IO_STD_ENUM + unset + + + PHY_RLD3_AC_MODE_ENUM + unset + + + PHY_RLD3_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_CK_IO_STD_ENUM + unset + + + PHY_RLD3_CK_MODE_ENUM + unset + + + PHY_RLD3_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_CONFIG_ENUM + CONFIG_PHY_ONLY + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD3_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_DEFAULT_IO + true + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD3_IO_VOLTAGE + 1.2 + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_RLD3_MIMIC_HPS_EMIF + false + + + PHY_RLD3_PING_PONG_EN + false + + + PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_RATE_ENUM + RATE_QUARTER + + + PHY_RLD3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD3_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_STARTING_VREFIN + 70.0 + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_PING_PONG_EN + false + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_USER_STARTING_VREFIN + 70.0 + + + PHY_RZQ + 240 + + + PHY_TARGET_IS_ES + false + + + PHY_TARGET_IS_ES2 + false + + + PHY_TARGET_IS_ES3 + true + + + PHY_TARGET_IS_PRODUCTION + false + + + PHY_TARGET_SPEEDGRADE + E2V + + + PHY_USERMODE_OCT + false + + + PHY_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PINS_C2L_DRIVEN_0 + 267714383 + + + PINS_C2L_DRIVEN_1 + 250877 + + + PINS_C2L_DRIVEN_10 + 0 + + + PINS_C2L_DRIVEN_11 + 0 + + + PINS_C2L_DRIVEN_12 + 0 + + + PINS_C2L_DRIVEN_2 + 0 + + + PINS_C2L_DRIVEN_3 + 1027593152 + + + PINS_C2L_DRIVEN_4 + 267714383 + + + PINS_C2L_DRIVEN_5 + 61 + + + PINS_C2L_DRIVEN_6 + 0 + + + PINS_C2L_DRIVEN_7 + 0 + + + PINS_C2L_DRIVEN_8 + 0 + + + PINS_C2L_DRIVEN_9 + 0 + + + PINS_C2L_DRIVEN_AUTOGEN_WCNT + 13 + + + PINS_DATA_IN_MODE_0 + 151515721 + + + PINS_DATA_IN_MODE_1 + 33329737 + + + PINS_DATA_IN_MODE_10 + 153391231 + + + PINS_DATA_IN_MODE_11 + 153362377 + + + PINS_DATA_IN_MODE_12 + 151515721 + + + PINS_DATA_IN_MODE_13 + 33329737 + + + PINS_DATA_IN_MODE_14 + 1059361353 + + + PINS_DATA_IN_MODE_15 + 37441 + + + PINS_DATA_IN_MODE_16 + 0 + + + PINS_DATA_IN_MODE_17 + 0 + + + PINS_DATA_IN_MODE_18 + 0 + + + PINS_DATA_IN_MODE_19 + 0 + + + PINS_DATA_IN_MODE_2 + 1059361353 + + + PINS_DATA_IN_MODE_20 + 0 + + + PINS_DATA_IN_MODE_21 + 0 + + + PINS_DATA_IN_MODE_22 + 0 + + + PINS_DATA_IN_MODE_23 + 0 + + + PINS_DATA_IN_MODE_24 + 0 + + + PINS_DATA_IN_MODE_25 + 0 + + + PINS_DATA_IN_MODE_26 + 0 + + + PINS_DATA_IN_MODE_27 + 0 + + + PINS_DATA_IN_MODE_28 + 0 + + + PINS_DATA_IN_MODE_29 + 0 + + + PINS_DATA_IN_MODE_3 + 153391681 + + + PINS_DATA_IN_MODE_30 + 0 + + + PINS_DATA_IN_MODE_31 + 0 + + + PINS_DATA_IN_MODE_32 + 0 + + + PINS_DATA_IN_MODE_33 + 0 + + + PINS_DATA_IN_MODE_34 + 0 + + + PINS_DATA_IN_MODE_35 + 0 + + + PINS_DATA_IN_MODE_36 + 0 + + + PINS_DATA_IN_MODE_37 + 0 + + + PINS_DATA_IN_MODE_38 + 0 + + + PINS_DATA_IN_MODE_4 + 153391231 + + + PINS_DATA_IN_MODE_5 + 150736969 + + + PINS_DATA_IN_MODE_6 + 153391689 + + + PINS_DATA_IN_MODE_7 + 153387017 + + + PINS_DATA_IN_MODE_8 + 584 + + + PINS_DATA_IN_MODE_9 + 153354304 + + + PINS_DATA_IN_MODE_AUTOGEN_WCNT + 39 + + + PINS_DCC_SPLIT_0 + 805503024 + + + PINS_DCC_SPLIT_1 + 201329664 + + + PINS_DCC_SPLIT_10 + 0 + + + PINS_DCC_SPLIT_11 + 0 + + + PINS_DCC_SPLIT_12 + 0 + + + PINS_DCC_SPLIT_2 + 0 + + + PINS_DCC_SPLIT_3 + 12585984 + + + PINS_DCC_SPLIT_4 + 805503024 + + + PINS_DCC_SPLIT_5 + 0 + + + PINS_DCC_SPLIT_6 + 0 + + + PINS_DCC_SPLIT_7 + 0 + + + PINS_DCC_SPLIT_8 + 0 + + + PINS_DCC_SPLIT_9 + 0 + + + PINS_DCC_SPLIT_AUTOGEN_WCNT + 13 + + + PINS_OCT_MODE_0 + 1073217407 + + + PINS_OCT_MODE_1 + 253949 + + + PINS_OCT_MODE_10 + 0 + + + PINS_OCT_MODE_11 + 0 + + + PINS_OCT_MODE_12 + 0 + + + PINS_OCT_MODE_2 + 0 + + + PINS_OCT_MODE_3 + 1040179136 + + + PINS_OCT_MODE_4 + 1073217407 + + + PINS_OCT_MODE_5 + 61 + + + PINS_OCT_MODE_6 + 0 + + + PINS_OCT_MODE_7 + 0 + + + PINS_OCT_MODE_8 + 0 + + + PINS_OCT_MODE_9 + 0 + + + PINS_OCT_MODE_AUTOGEN_WCNT + 13 + + + PINS_PER_LANE + 12 + + + PINS_RATE_0 + 0 + + + PINS_RATE_1 + 561774592 + + + PINS_RATE_10 + 0 + + + PINS_RATE_11 + 0 + + + PINS_RATE_12 + 0 + + + PINS_RATE_2 + 15699967 + + + PINS_RATE_3 + 4 + + + PINS_RATE_4 + 0 + + + PINS_RATE_5 + 0 + + + PINS_RATE_6 + 0 + + + PINS_RATE_7 + 0 + + + PINS_RATE_8 + 0 + + + PINS_RATE_9 + 0 + + + PINS_RATE_AUTOGEN_WCNT + 13 + + + PINS_USAGE_0 + 1073217407 + + + PINS_USAGE_1 + 763355133 + + + PINS_USAGE_10 + 0 + + + PINS_USAGE_11 + 0 + + + PINS_USAGE_12 + 0 + + + PINS_USAGE_2 + 15699967 + + + PINS_USAGE_3 + 1040179140 + + + PINS_USAGE_4 + 1073217407 + + + PINS_USAGE_5 + 61 + + + PINS_USAGE_6 + 0 + + + PINS_USAGE_7 + 0 + + + PINS_USAGE_8 + 0 + + + PINS_USAGE_9 + 0 + + + PINS_USAGE_AUTOGEN_WCNT + 13 + + + PLL_ADD_EXTRA_CLKS + false + + + PLL_BW_CTRL + pll_bw_res_setting4 + + + PLL_BW_SEL + high + + + PLL_CP_SETTING + pll_cp_setting12 + + + PLL_C_CNT_BYPASS_EN_0 + false + + + PLL_C_CNT_BYPASS_EN_1 + false + + + PLL_C_CNT_BYPASS_EN_2 + false + + + PLL_C_CNT_BYPASS_EN_3 + false + + + PLL_C_CNT_BYPASS_EN_4 + false + + + PLL_C_CNT_BYPASS_EN_5 + true + + + PLL_C_CNT_BYPASS_EN_6 + true + + + PLL_C_CNT_BYPASS_EN_7 + true + + + PLL_C_CNT_BYPASS_EN_8 + true + + + PLL_C_CNT_DUTY_CYCLE_0 + 50 + + + PLL_C_CNT_DUTY_CYCLE_1 + 50 + + + PLL_C_CNT_DUTY_CYCLE_2 + 50 + + + PLL_C_CNT_DUTY_CYCLE_3 + 50 + + + PLL_C_CNT_DUTY_CYCLE_4 + 50 + + + PLL_C_CNT_DUTY_CYCLE_5 + 50 + + + PLL_C_CNT_DUTY_CYCLE_6 + 50 + + + PLL_C_CNT_DUTY_CYCLE_7 + 50 + + + PLL_C_CNT_DUTY_CYCLE_8 + 50 + + + PLL_C_CNT_EVEN_DUTY_EN_0 + false + + + PLL_C_CNT_EVEN_DUTY_EN_1 + false + + + PLL_C_CNT_EVEN_DUTY_EN_2 + false + + + PLL_C_CNT_EVEN_DUTY_EN_3 + false + + + PLL_C_CNT_EVEN_DUTY_EN_4 + false + + + PLL_C_CNT_EVEN_DUTY_EN_5 + false + + + PLL_C_CNT_EVEN_DUTY_EN_6 + false + + + PLL_C_CNT_EVEN_DUTY_EN_7 + false + + + PLL_C_CNT_EVEN_DUTY_EN_8 + false + + + PLL_C_CNT_FREQ_MHZ_STR_0 + 300.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_1 + 600.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_2 + 300.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_3 + 600.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_4 + 300.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_5 + 0.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_6 + 0.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_7 + 0.0 MHz + + + PLL_C_CNT_FREQ_MHZ_STR_8 + 0.0 MHz + + + PLL_C_CNT_FREQ_PS_STR_0 + 3336 ps + + + PLL_C_CNT_FREQ_PS_STR_1 + 1668 ps + + + PLL_C_CNT_FREQ_PS_STR_2 + 3336 ps + + + PLL_C_CNT_FREQ_PS_STR_3 + 1668 ps + + + PLL_C_CNT_FREQ_PS_STR_4 + 3336 ps + + + PLL_C_CNT_FREQ_PS_STR_5 + 0 ps + + + PLL_C_CNT_FREQ_PS_STR_6 + 0 ps + + + PLL_C_CNT_FREQ_PS_STR_7 + 0 ps + + + PLL_C_CNT_FREQ_PS_STR_8 + 0 ps + + + PLL_C_CNT_HIGH_0 + 2 + + + PLL_C_CNT_HIGH_1 + 1 + + + PLL_C_CNT_HIGH_2 + 2 + + + PLL_C_CNT_HIGH_3 + 1 + + + PLL_C_CNT_HIGH_4 + 2 + + + PLL_C_CNT_HIGH_5 + 256 + + + PLL_C_CNT_HIGH_6 + 256 + + + PLL_C_CNT_HIGH_7 + 256 + + + PLL_C_CNT_HIGH_8 + 256 + + + PLL_C_CNT_LOW_0 + 2 + + + PLL_C_CNT_LOW_1 + 1 + + + PLL_C_CNT_LOW_2 + 2 + + + PLL_C_CNT_LOW_3 + 1 + + + PLL_C_CNT_LOW_4 + 2 + + + PLL_C_CNT_LOW_5 + 256 + + + PLL_C_CNT_LOW_6 + 256 + + + PLL_C_CNT_LOW_7 + 256 + + + PLL_C_CNT_LOW_8 + 256 + + + PLL_C_CNT_OUT_EN_0 + true + + + PLL_C_CNT_OUT_EN_1 + true + + + PLL_C_CNT_OUT_EN_2 + true + + + PLL_C_CNT_OUT_EN_3 + true + + + PLL_C_CNT_OUT_EN_4 + true + + + PLL_C_CNT_OUT_EN_5 + false + + + PLL_C_CNT_OUT_EN_6 + false + + + PLL_C_CNT_OUT_EN_7 + false + + + PLL_C_CNT_OUT_EN_8 + false + + + PLL_C_CNT_PHASE_PS_STR_0 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_1 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_2 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_3 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_4 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_5 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_6 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_7 + 0 ps + + + PLL_C_CNT_PHASE_PS_STR_8 + 0 ps + + + PLL_C_CNT_PH_MUX_PRST_0 + 0 + + + PLL_C_CNT_PH_MUX_PRST_1 + 0 + + + PLL_C_CNT_PH_MUX_PRST_2 + 0 + + + PLL_C_CNT_PH_MUX_PRST_3 + 0 + + + PLL_C_CNT_PH_MUX_PRST_4 + 0 + + + PLL_C_CNT_PH_MUX_PRST_5 + 0 + + + PLL_C_CNT_PH_MUX_PRST_6 + 0 + + + PLL_C_CNT_PH_MUX_PRST_7 + 0 + + + PLL_C_CNT_PH_MUX_PRST_8 + 0 + + + PLL_C_CNT_PRST_0 + 1 + + + PLL_C_CNT_PRST_1 + 1 + + + PLL_C_CNT_PRST_2 + 1 + + + PLL_C_CNT_PRST_3 + 1 + + + PLL_C_CNT_PRST_4 + 1 + + + PLL_C_CNT_PRST_5 + 1 + + + PLL_C_CNT_PRST_6 + 1 + + + PLL_C_CNT_PRST_7 + 1 + + + PLL_C_CNT_PRST_8 + 1 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + ps + + + PLL_FBCLK_MUX_1 + pll_fbclk_mux_1_glb + + + PLL_FBCLK_MUX_2 + pll_fbclk_mux_2_m_cnt + + + PLL_MEM_CLK_FREQ_PS + 834 + + + PLL_M_CNT_BYPASS_EN + false + + + PLL_M_CNT_EVEN_DUTY_EN + false + + + PLL_M_CNT_HIGH + 18 + + + PLL_M_CNT_IN_SRC + c_m_cnt_in_src_ph_mux_clk + + + PLL_M_CNT_LOW + 18 + + + PLL_NUM_OF_EXTRA_CLKS + 0 + + + PLL_N_CNT_BYPASS_EN + true + + + PLL_N_CNT_EVEN_DUTY_EN + false + + + PLL_N_CNT_HIGH + 256 + + + PLL_N_CNT_LOW + 256 + + + PLL_PHY_CLK_VCO_PHASE + 0 + + + PLL_REF_CLK_FREQ_MHZ_STR + 33.333 MHz + + + PLL_REF_CLK_FREQ_PS + 30024 + + + PLL_REF_CLK_FREQ_PS_STR + 30024 ps + + + PLL_SIM_PHYCLK_0_FREQ_PS + 1680 + + + PLL_SIM_PHYCLK_1_FREQ_PS + 3360 + + + PLL_SIM_PHYCLK_FB_FREQ_PS + 3360 + + + PLL_SIM_PHY_CLK_VCO_PHASE_PS + 0 + + + PLL_SIM_VCO_FREQ_PS + 840 + + + PLL_USER_NUM_OF_EXTRA_CLKS + 0 + + + PLL_VCO_CLK_FREQ_MHZ + 1200.0 + + + PLL_VCO_FREQ_MHZ_INT + 1200 + + + PLL_VCO_FREQ_MHZ_STR + 1200 MHz + + + PLL_VCO_FREQ_PS_STR + 834 ps + + + PLL_VCO_TO_MEM_CLK_FREQ_RATIO + 1 + + + PORT_AFI_ACT_N_WIDTH + 1 + + + PORT_AFI_ADDR_WIDTH + 1 + + + PORT_AFI_AINV_WIDTH + 1 + + + PORT_AFI_ALERT_N_WIDTH + 1 + + + PORT_AFI_AP_WIDTH + 1 + + + PORT_AFI_BA_WIDTH + 1 + + + PORT_AFI_BG_WIDTH + 1 + + + PORT_AFI_BWS_N_WIDTH + 1 + + + PORT_AFI_CAS_N_WIDTH + 1 + + + PORT_AFI_CA_WIDTH + 1 + + + PORT_AFI_CFG_N_WIDTH + 1 + + + PORT_AFI_CKE_WIDTH + 1 + + + PORT_AFI_CS_N_WIDTH + 1 + + + PORT_AFI_C_WIDTH + 1 + + + PORT_AFI_DM_N_WIDTH + 1 + + + PORT_AFI_DM_WIDTH + 1 + + + PORT_AFI_DOFF_N_WIDTH + 1 + + + PORT_AFI_DQS_BURST_WIDTH + 1 + + + PORT_AFI_ERR_N_WIDTH + 1 + + + PORT_AFI_GNT_N_WIDTH + 1 + + + PORT_AFI_LBK0_N_WIDTH + 1 + + + PORT_AFI_LBK1_N_WIDTH + 1 + + + PORT_AFI_LD_N_WIDTH + 1 + + + PORT_AFI_ODT_WIDTH + 1 + + + PORT_AFI_PAR_WIDTH + 1 + + + PORT_AFI_PE_N_WIDTH + 1 + + + PORT_AFI_RAS_N_WIDTH + 1 + + + PORT_AFI_RDATA_DBI_N_WIDTH + 1 + + + PORT_AFI_RDATA_DINV_WIDTH + 1 + + + PORT_AFI_RDATA_EN_FULL_WIDTH + 1 + + + PORT_AFI_RDATA_VALID_WIDTH + 1 + + + PORT_AFI_RDATA_WIDTH + 1 + + + PORT_AFI_REF_N_WIDTH + 1 + + + PORT_AFI_REQ_N_WIDTH + 1 + + + PORT_AFI_RLAT_WIDTH + 6 + + + PORT_AFI_RM_WIDTH + 1 + + + PORT_AFI_RPS_N_WIDTH + 1 + + + PORT_AFI_RRANK_WIDTH + 1 + + + PORT_AFI_RST_N_WIDTH + 1 + + + PORT_AFI_RW_N_WIDTH + 1 + + + PORT_AFI_SEQ_BUSY_WIDTH + 4 + + + PORT_AFI_WDATA_DBI_N_WIDTH + 1 + + + PORT_AFI_WDATA_DINV_WIDTH + 1 + + + PORT_AFI_WDATA_VALID_WIDTH + 1 + + + PORT_AFI_WDATA_WIDTH + 1 + + + PORT_AFI_WE_N_WIDTH + 1 + + + PORT_AFI_WLAT_WIDTH + 6 + + + PORT_AFI_WPS_N_WIDTH + 1 + + + PORT_AFI_WRANK_WIDTH + 1 + + + PORT_CALBUS_ADDRESS_WIDTH + 20 + + + PORT_CALBUS_RDATA_WIDTH + 32 + + + PORT_CALBUS_SEQ_PARAM_TBL_WIDTH + 4096 + + + PORT_CALBUS_WDATA_WIDTH + 32 + + + PORT_CLKS_SHARING_MASTER_OUT_WIDTH + 32 + + + PORT_CLKS_SHARING_SLAVE_IN_WIDTH + 32 + + + PORT_CLKS_SHARING_SLAVE_OUT_WIDTH + 32 + + + PORT_CTRL_AMM_ADDRESS_WIDTH + 1 + + + PORT_CTRL_AMM_BCOUNT_WIDTH + 1 + + + PORT_CTRL_AMM_BYTEEN_WIDTH + 1 + + + PORT_CTRL_AMM_RDATA_WIDTH + 1 + + + PORT_CTRL_AMM_WDATA_WIDTH + 1 + + + PORT_CTRL_AST_CMD_DATA_WIDTH + 61 + + + PORT_CTRL_AST_RD_DATA_WIDTH + 576 + + + PORT_CTRL_AST_WR_DATA_WIDTH + 648 + + + PORT_CTRL_DATA_IN_WIDTH + 1 + + + PORT_CTRL_DATA_OE_WIDTH + 1 + + + PORT_CTRL_DATA_OUT_WIDTH + 1 + + + PORT_CTRL_ECC_CMD_INFO_WIDTH + 3 + + + PORT_CTRL_ECC_RDATA_ID_WIDTH + 13 + + + PORT_CTRL_ECC_READ_INFO_WIDTH + 3 + + + PORT_CTRL_ECC_WB_POINTER_WIDTH + 12 + + + PORT_CTRL_ECC_WRITE_INFO_WIDTH + 15 + + + PORT_CTRL_LOCKED_WIDTH + 1 + + + PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH + 10 + + + PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH + 2 + + + PORT_CTRL_MMR_SLAVE_RDATA_WIDTH + 32 + + + PORT_CTRL_MMR_SLAVE_WDATA_WIDTH + 32 + + + PORT_CTRL_RDATA_ENABLE_WIDTH + 1 + + + PORT_CTRL_RDATA_VALID_WIDTH + 1 + + + PORT_CTRL_SELF_REFRESH_REQ_WIDTH + 4 + + + PORT_CTRL_STROBE_OE_WIDTH + 1 + + + PORT_CTRL_STROBE_WIDTH + 1 + + + PORT_CTRL_USER_REFRESH_BANK_WIDTH + 16 + + + PORT_CTRL_USER_REFRESH_REQ_WIDTH + 4 + + + PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH + 2 + + + PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH + 2 + + + PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH + 8 + + + PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH + 9 + + + PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH + 8 + + + PORT_DFT_ND_PLL_CNTSEL_WIDTH + 4 + + + PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH + 4 + + + PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH + 3 + + + PORT_HPS_EMIF_E2H_GP_WIDTH + 1 + + + PORT_HPS_EMIF_E2H_WIDTH + 4096 + + + PORT_HPS_EMIF_H2E_GP_WIDTH + 2 + + + PORT_HPS_EMIF_H2E_WIDTH + 4096 + + + PORT_MEM_ACT_N_PINLOC_0 + 52225 + + + PORT_MEM_ACT_N_PINLOC_1 + 0 + + + PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_ACT_N_WIDTH + 1 + + + PORT_MEM_AINV_PINLOC_0 + 0 + + + PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_AINV_WIDTH + 1 + + + PORT_MEM_ALERT_N_PINLOC_0 + 94209 + + + PORT_MEM_ALERT_N_PINLOC_1 + 0 + + + PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_ALERT_N_WIDTH + 1 + + + PORT_MEM_AP_PINLOC_0 + 0 + + + PORT_MEM_AP_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_AP_WIDTH + 1 + + + PORT_MEM_A_PINLOC_0 + 64024593 + + + PORT_MEM_A_PINLOC_1 + 67173438 + + + PORT_MEM_A_PINLOC_10 + 0 + + + PORT_MEM_A_PINLOC_11 + 0 + + + PORT_MEM_A_PINLOC_12 + 0 + + + PORT_MEM_A_PINLOC_13 + 0 + + + PORT_MEM_A_PINLOC_14 + 0 + + + PORT_MEM_A_PINLOC_15 + 0 + + + PORT_MEM_A_PINLOC_16 + 0 + + + PORT_MEM_A_PINLOC_2 + 70322241 + + + PORT_MEM_A_PINLOC_3 + 73471044 + + + PORT_MEM_A_PINLOC_4 + 79768647 + + + PORT_MEM_A_PINLOC_5 + 82917453 + + + PORT_MEM_A_PINLOC_6 + 0 + + + PORT_MEM_A_PINLOC_7 + 0 + + + PORT_MEM_A_PINLOC_8 + 0 + + + PORT_MEM_A_PINLOC_9 + 0 + + + PORT_MEM_A_PINLOC_AUTOGEN_WCNT + 17 + + + PORT_MEM_A_WIDTH + 17 + + + PORT_MEM_BA_PINLOC_0 + 86066178 + + + PORT_MEM_BA_PINLOC_1 + 0 + + + PORT_MEM_BA_PINLOC_2 + 0 + + + PORT_MEM_BA_PINLOC_3 + 0 + + + PORT_MEM_BA_PINLOC_4 + 0 + + + PORT_MEM_BA_PINLOC_5 + 0 + + + PORT_MEM_BA_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_BA_WIDTH + 2 + + + PORT_MEM_BG_PINLOC_0 + 50416642 + + + PORT_MEM_BG_PINLOC_1 + 0 + + + PORT_MEM_BG_PINLOC_2 + 0 + + + PORT_MEM_BG_PINLOC_3 + 0 + + + PORT_MEM_BG_PINLOC_4 + 0 + + + PORT_MEM_BG_PINLOC_5 + 0 + + + PORT_MEM_BG_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_BG_WIDTH + 2 + + + PORT_MEM_BWS_N_PINLOC_0 + 0 + + + PORT_MEM_BWS_N_PINLOC_1 + 0 + + + PORT_MEM_BWS_N_PINLOC_2 + 0 + + + PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT + 3 + + + PORT_MEM_BWS_N_WIDTH + 1 + + + PORT_MEM_CAS_N_PINLOC_0 + 0 + + + PORT_MEM_CAS_N_PINLOC_1 + 0 + + + PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_CAS_N_WIDTH + 1 + + + PORT_MEM_CA_PINLOC_0 + 0 + + + PORT_MEM_CA_PINLOC_1 + 0 + + + PORT_MEM_CA_PINLOC_10 + 0 + + + PORT_MEM_CA_PINLOC_11 + 0 + + + PORT_MEM_CA_PINLOC_12 + 0 + + + PORT_MEM_CA_PINLOC_13 + 0 + + + PORT_MEM_CA_PINLOC_14 + 0 + + + PORT_MEM_CA_PINLOC_15 + 0 + + + PORT_MEM_CA_PINLOC_16 + 0 + + + PORT_MEM_CA_PINLOC_2 + 0 + + + PORT_MEM_CA_PINLOC_3 + 0 + + + PORT_MEM_CA_PINLOC_4 + 0 + + + PORT_MEM_CA_PINLOC_5 + 0 + + + PORT_MEM_CA_PINLOC_6 + 0 + + + PORT_MEM_CA_PINLOC_7 + 0 + + + PORT_MEM_CA_PINLOC_8 + 0 + + + PORT_MEM_CA_PINLOC_9 + 0 + + + PORT_MEM_CA_PINLOC_AUTOGEN_WCNT + 17 + + + PORT_MEM_CA_WIDTH + 1 + + + PORT_MEM_CFG_N_PINLOC_0 + 0 + + + PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_CFG_N_WIDTH + 1 + + + PORT_MEM_CKE_PINLOC_0 + 55297 + + + PORT_MEM_CKE_PINLOC_1 + 0 + + + PORT_MEM_CKE_PINLOC_2 + 0 + + + PORT_MEM_CKE_PINLOC_3 + 0 + + + PORT_MEM_CKE_PINLOC_4 + 0 + + + PORT_MEM_CKE_PINLOC_5 + 0 + + + PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_CKE_WIDTH + 1 + + + PORT_MEM_CK_BIDIR_N_PINLOC_0 + 0 + + + PORT_MEM_CK_BIDIR_N_PINLOC_1 + 0 + + + PORT_MEM_CK_BIDIR_N_PINLOC_2 + 0 + + + PORT_MEM_CK_BIDIR_N_PINLOC_3 + 0 + + + PORT_MEM_CK_BIDIR_N_PINLOC_4 + 0 + + + PORT_MEM_CK_BIDIR_N_PINLOC_5 + 0 + + + PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_CK_BIDIR_N_WIDTH + 1 + + + PORT_MEM_CK_BIDIR_PINLOC_0 + 0 + + + PORT_MEM_CK_BIDIR_PINLOC_1 + 0 + + + PORT_MEM_CK_BIDIR_PINLOC_2 + 0 + + + PORT_MEM_CK_BIDIR_PINLOC_3 + 0 + + + PORT_MEM_CK_BIDIR_PINLOC_4 + 0 + + + PORT_MEM_CK_BIDIR_PINLOC_5 + 0 + + + PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_CK_BIDIR_WIDTH + 1 + + + PORT_MEM_CK_N_PINLOC_0 + 58369 + + + PORT_MEM_CK_N_PINLOC_1 + 0 + + + PORT_MEM_CK_N_PINLOC_2 + 0 + + + PORT_MEM_CK_N_PINLOC_3 + 0 + + + PORT_MEM_CK_N_PINLOC_4 + 0 + + + PORT_MEM_CK_N_PINLOC_5 + 0 + + + PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_CK_N_WIDTH + 1 + + + PORT_MEM_CK_PINLOC_0 + 57345 + + + PORT_MEM_CK_PINLOC_1 + 0 + + + PORT_MEM_CK_PINLOC_2 + 0 + + + PORT_MEM_CK_PINLOC_3 + 0 + + + PORT_MEM_CK_PINLOC_4 + 0 + + + PORT_MEM_CK_PINLOC_5 + 0 + + + PORT_MEM_CK_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_CK_WIDTH + 1 + + + PORT_MEM_CQ_N_PINLOC_0 + 0 + + + PORT_MEM_CQ_N_PINLOC_1 + 0 + + + PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_CQ_N_WIDTH + 1 + + + PORT_MEM_CQ_PINLOC_0 + 0 + + + PORT_MEM_CQ_PINLOC_1 + 0 + + + PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_CQ_WIDTH + 1 + + + PORT_MEM_CS_N_PINLOC_0 + 51201 + + + PORT_MEM_CS_N_PINLOC_1 + 0 + + + PORT_MEM_CS_N_PINLOC_2 + 0 + + + PORT_MEM_CS_N_PINLOC_3 + 0 + + + PORT_MEM_CS_N_PINLOC_4 + 0 + + + PORT_MEM_CS_N_PINLOC_5 + 0 + + + PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_CS_N_WIDTH + 1 + + + PORT_MEM_C_PINLOC_0 + 0 + + + PORT_MEM_C_PINLOC_1 + 0 + + + PORT_MEM_C_PINLOC_2 + 0 + + + PORT_MEM_C_PINLOC_3 + 0 + + + PORT_MEM_C_PINLOC_4 + 0 + + + PORT_MEM_C_PINLOC_5 + 0 + + + PORT_MEM_C_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_C_WIDTH + 1 + + + PORT_MEM_DBI_N_PINLOC_0 + 18880521 + + + PORT_MEM_DBI_N_PINLOC_1 + 106997790 + + + PORT_MEM_DBI_N_PINLOC_2 + 144832626 + + + PORT_MEM_DBI_N_PINLOC_3 + 150 + + + PORT_MEM_DBI_N_PINLOC_4 + 0 + + + PORT_MEM_DBI_N_PINLOC_5 + 0 + + + PORT_MEM_DBI_N_PINLOC_6 + 0 + + + PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT + 7 + + + PORT_MEM_DBI_N_WIDTH + 9 + + + PORT_MEM_DINVA_PINLOC_0 + 0 + + + PORT_MEM_DINVA_PINLOC_1 + 0 + + + PORT_MEM_DINVA_PINLOC_2 + 0 + + + PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT + 3 + + + PORT_MEM_DINVA_WIDTH + 1 + + + PORT_MEM_DINVB_PINLOC_0 + 0 + + + PORT_MEM_DINVB_PINLOC_1 + 0 + + + PORT_MEM_DINVB_PINLOC_2 + 0 + + + PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT + 3 + + + PORT_MEM_DINVB_WIDTH + 1 + + + PORT_MEM_DKA_N_PINLOC_0 + 0 + + + PORT_MEM_DKA_N_PINLOC_1 + 0 + + + PORT_MEM_DKA_N_PINLOC_2 + 0 + + + PORT_MEM_DKA_N_PINLOC_3 + 0 + + + PORT_MEM_DKA_N_PINLOC_4 + 0 + + + PORT_MEM_DKA_N_PINLOC_5 + 0 + + + PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_DKA_N_WIDTH + 1 + + + PORT_MEM_DKA_PINLOC_0 + 0 + + + PORT_MEM_DKA_PINLOC_1 + 0 + + + PORT_MEM_DKA_PINLOC_2 + 0 + + + PORT_MEM_DKA_PINLOC_3 + 0 + + + PORT_MEM_DKA_PINLOC_4 + 0 + + + PORT_MEM_DKA_PINLOC_5 + 0 + + + PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_DKA_WIDTH + 1 + + + PORT_MEM_DKB_N_PINLOC_0 + 0 + + + PORT_MEM_DKB_N_PINLOC_1 + 0 + + + PORT_MEM_DKB_N_PINLOC_2 + 0 + + + PORT_MEM_DKB_N_PINLOC_3 + 0 + + + PORT_MEM_DKB_N_PINLOC_4 + 0 + + + PORT_MEM_DKB_N_PINLOC_5 + 0 + + + PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_DKB_N_WIDTH + 1 + + + PORT_MEM_DKB_PINLOC_0 + 0 + + + PORT_MEM_DKB_PINLOC_1 + 0 + + + PORT_MEM_DKB_PINLOC_2 + 0 + + + PORT_MEM_DKB_PINLOC_3 + 0 + + + PORT_MEM_DKB_PINLOC_4 + 0 + + + PORT_MEM_DKB_PINLOC_5 + 0 + + + PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_DKB_WIDTH + 1 + + + PORT_MEM_DK_N_PINLOC_0 + 0 + + + PORT_MEM_DK_N_PINLOC_1 + 0 + + + PORT_MEM_DK_N_PINLOC_2 + 0 + + + PORT_MEM_DK_N_PINLOC_3 + 0 + + + PORT_MEM_DK_N_PINLOC_4 + 0 + + + PORT_MEM_DK_N_PINLOC_5 + 0 + + + PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_DK_N_WIDTH + 1 + + + PORT_MEM_DK_PINLOC_0 + 0 + + + PORT_MEM_DK_PINLOC_1 + 0 + + + PORT_MEM_DK_PINLOC_2 + 0 + + + PORT_MEM_DK_PINLOC_3 + 0 + + + PORT_MEM_DK_PINLOC_4 + 0 + + + PORT_MEM_DK_PINLOC_5 + 0 + + + PORT_MEM_DK_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_DK_WIDTH + 1 + + + PORT_MEM_DM_PINLOC_0 + 0 + + + PORT_MEM_DM_PINLOC_1 + 0 + + + PORT_MEM_DM_PINLOC_10 + 0 + + + PORT_MEM_DM_PINLOC_11 + 0 + + + PORT_MEM_DM_PINLOC_12 + 0 + + + PORT_MEM_DM_PINLOC_2 + 0 + + + PORT_MEM_DM_PINLOC_3 + 0 + + + PORT_MEM_DM_PINLOC_4 + 0 + + + PORT_MEM_DM_PINLOC_5 + 0 + + + PORT_MEM_DM_PINLOC_6 + 0 + + + PORT_MEM_DM_PINLOC_7 + 0 + + + PORT_MEM_DM_PINLOC_8 + 0 + + + PORT_MEM_DM_PINLOC_9 + 0 + + + PORT_MEM_DM_PINLOC_AUTOGEN_WCNT + 13 + + + PORT_MEM_DM_WIDTH + 1 + + + PORT_MEM_DOFF_N_PINLOC_0 + 0 + + + PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_DOFF_N_WIDTH + 1 + + + PORT_MEM_DQA_PINLOC_0 + 0 + + + PORT_MEM_DQA_PINLOC_1 + 0 + + + PORT_MEM_DQA_PINLOC_10 + 0 + + + PORT_MEM_DQA_PINLOC_11 + 0 + + + PORT_MEM_DQA_PINLOC_12 + 0 + + + PORT_MEM_DQA_PINLOC_13 + 0 + + + PORT_MEM_DQA_PINLOC_14 + 0 + + + PORT_MEM_DQA_PINLOC_15 + 0 + + + PORT_MEM_DQA_PINLOC_16 + 0 + + + PORT_MEM_DQA_PINLOC_17 + 0 + + + PORT_MEM_DQA_PINLOC_18 + 0 + + + PORT_MEM_DQA_PINLOC_19 + 0 + + + PORT_MEM_DQA_PINLOC_2 + 0 + + + PORT_MEM_DQA_PINLOC_20 + 0 + + + PORT_MEM_DQA_PINLOC_21 + 0 + + + PORT_MEM_DQA_PINLOC_22 + 0 + + + PORT_MEM_DQA_PINLOC_23 + 0 + + + PORT_MEM_DQA_PINLOC_24 + 0 + + + PORT_MEM_DQA_PINLOC_25 + 0 + + + PORT_MEM_DQA_PINLOC_26 + 0 + + + PORT_MEM_DQA_PINLOC_27 + 0 + + + PORT_MEM_DQA_PINLOC_28 + 0 + + + PORT_MEM_DQA_PINLOC_29 + 0 + + + PORT_MEM_DQA_PINLOC_3 + 0 + + + PORT_MEM_DQA_PINLOC_30 + 0 + + + PORT_MEM_DQA_PINLOC_31 + 0 + + + PORT_MEM_DQA_PINLOC_32 + 0 + + + PORT_MEM_DQA_PINLOC_33 + 0 + + + PORT_MEM_DQA_PINLOC_34 + 0 + + + PORT_MEM_DQA_PINLOC_35 + 0 + + + PORT_MEM_DQA_PINLOC_36 + 0 + + + PORT_MEM_DQA_PINLOC_37 + 0 + + + PORT_MEM_DQA_PINLOC_38 + 0 + + + PORT_MEM_DQA_PINLOC_39 + 0 + + + PORT_MEM_DQA_PINLOC_4 + 0 + + + PORT_MEM_DQA_PINLOC_40 + 0 + + + PORT_MEM_DQA_PINLOC_41 + 0 + + + PORT_MEM_DQA_PINLOC_42 + 0 + + + PORT_MEM_DQA_PINLOC_43 + 0 + + + PORT_MEM_DQA_PINLOC_44 + 0 + + + PORT_MEM_DQA_PINLOC_45 + 0 + + + PORT_MEM_DQA_PINLOC_46 + 0 + + + PORT_MEM_DQA_PINLOC_47 + 0 + + + PORT_MEM_DQA_PINLOC_48 + 0 + + + PORT_MEM_DQA_PINLOC_5 + 0 + + + PORT_MEM_DQA_PINLOC_6 + 0 + + + PORT_MEM_DQA_PINLOC_7 + 0 + + + PORT_MEM_DQA_PINLOC_8 + 0 + + + PORT_MEM_DQA_PINLOC_9 + 0 + + + PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT + 49 + + + PORT_MEM_DQA_WIDTH + 1 + + + PORT_MEM_DQB_PINLOC_0 + 0 + + + PORT_MEM_DQB_PINLOC_1 + 0 + + + PORT_MEM_DQB_PINLOC_10 + 0 + + + PORT_MEM_DQB_PINLOC_11 + 0 + + + PORT_MEM_DQB_PINLOC_12 + 0 + + + PORT_MEM_DQB_PINLOC_13 + 0 + + + PORT_MEM_DQB_PINLOC_14 + 0 + + + PORT_MEM_DQB_PINLOC_15 + 0 + + + PORT_MEM_DQB_PINLOC_16 + 0 + + + PORT_MEM_DQB_PINLOC_17 + 0 + + + PORT_MEM_DQB_PINLOC_18 + 0 + + + PORT_MEM_DQB_PINLOC_19 + 0 + + + PORT_MEM_DQB_PINLOC_2 + 0 + + + PORT_MEM_DQB_PINLOC_20 + 0 + + + PORT_MEM_DQB_PINLOC_21 + 0 + + + PORT_MEM_DQB_PINLOC_22 + 0 + + + PORT_MEM_DQB_PINLOC_23 + 0 + + + PORT_MEM_DQB_PINLOC_24 + 0 + + + PORT_MEM_DQB_PINLOC_25 + 0 + + + PORT_MEM_DQB_PINLOC_26 + 0 + + + PORT_MEM_DQB_PINLOC_27 + 0 + + + PORT_MEM_DQB_PINLOC_28 + 0 + + + PORT_MEM_DQB_PINLOC_29 + 0 + + + PORT_MEM_DQB_PINLOC_3 + 0 + + + PORT_MEM_DQB_PINLOC_30 + 0 + + + PORT_MEM_DQB_PINLOC_31 + 0 + + + PORT_MEM_DQB_PINLOC_32 + 0 + + + PORT_MEM_DQB_PINLOC_33 + 0 + + + PORT_MEM_DQB_PINLOC_34 + 0 + + + PORT_MEM_DQB_PINLOC_35 + 0 + + + PORT_MEM_DQB_PINLOC_36 + 0 + + + PORT_MEM_DQB_PINLOC_37 + 0 + + + PORT_MEM_DQB_PINLOC_38 + 0 + + + PORT_MEM_DQB_PINLOC_39 + 0 + + + PORT_MEM_DQB_PINLOC_4 + 0 + + + PORT_MEM_DQB_PINLOC_40 + 0 + + + PORT_MEM_DQB_PINLOC_41 + 0 + + + PORT_MEM_DQB_PINLOC_42 + 0 + + + PORT_MEM_DQB_PINLOC_43 + 0 + + + PORT_MEM_DQB_PINLOC_44 + 0 + + + PORT_MEM_DQB_PINLOC_45 + 0 + + + PORT_MEM_DQB_PINLOC_46 + 0 + + + PORT_MEM_DQB_PINLOC_47 + 0 + + + PORT_MEM_DQB_PINLOC_48 + 0 + + + PORT_MEM_DQB_PINLOC_5 + 0 + + + PORT_MEM_DQB_PINLOC_6 + 0 + + + PORT_MEM_DQB_PINLOC_7 + 0 + + + PORT_MEM_DQB_PINLOC_8 + 0 + + + PORT_MEM_DQB_PINLOC_9 + 0 + + + PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT + 49 + + + PORT_MEM_DQB_WIDTH + 1 + + + PORT_MEM_DQS_N_PINLOC_0 + 17830921 + + + PORT_MEM_DQS_N_PINLOC_1 + 105948189 + + + PORT_MEM_DQS_N_PINLOC_10 + 0 + + + PORT_MEM_DQS_N_PINLOC_11 + 0 + + + PORT_MEM_DQS_N_PINLOC_12 + 0 + + + PORT_MEM_DQS_N_PINLOC_2 + 143783025 + + + PORT_MEM_DQS_N_PINLOC_3 + 149 + + + PORT_MEM_DQS_N_PINLOC_4 + 0 + + + PORT_MEM_DQS_N_PINLOC_5 + 0 + + + PORT_MEM_DQS_N_PINLOC_6 + 0 + + + PORT_MEM_DQS_N_PINLOC_7 + 0 + + + PORT_MEM_DQS_N_PINLOC_8 + 0 + + + PORT_MEM_DQS_N_PINLOC_9 + 0 + + + PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT + 13 + + + PORT_MEM_DQS_N_WIDTH + 9 + + + PORT_MEM_DQS_PINLOC_0 + 16781321 + + + PORT_MEM_DQS_PINLOC_1 + 104898588 + + + PORT_MEM_DQS_PINLOC_10 + 0 + + + PORT_MEM_DQS_PINLOC_11 + 0 + + + PORT_MEM_DQS_PINLOC_12 + 0 + + + PORT_MEM_DQS_PINLOC_2 + 142733424 + + + PORT_MEM_DQS_PINLOC_3 + 148 + + + PORT_MEM_DQS_PINLOC_4 + 0 + + + PORT_MEM_DQS_PINLOC_5 + 0 + + + PORT_MEM_DQS_PINLOC_6 + 0 + + + PORT_MEM_DQS_PINLOC_7 + 0 + + + PORT_MEM_DQS_PINLOC_8 + 0 + + + PORT_MEM_DQS_PINLOC_9 + 0 + + + PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT + 13 + + + PORT_MEM_DQS_WIDTH + 9 + + + PORT_MEM_DQ_PINLOC_0 + 1048648 + + + PORT_MEM_DQ_PINLOC_1 + 8391682 + + + PORT_MEM_DQ_PINLOC_10 + 49330221 + + + PORT_MEM_DQ_PINLOC_11 + 102859872 + + + PORT_MEM_DQ_PINLOC_12 + 110207075 + + + PORT_MEM_DQ_PINLOC_13 + 113355882 + + + PORT_MEM_DQ_PINLOC_14 + 116504685 + + + PORT_MEM_DQ_PINLOC_15 + 123851892 + + + PORT_MEM_DQ_PINLOC_16 + 127000695 + + + PORT_MEM_DQ_PINLOC_17 + 134343802 + + + PORT_MEM_DQ_PINLOC_18 + 137496705 + + + PORT_MEM_DQ_PINLOC_19 + 140645508 + + + PORT_MEM_DQ_PINLOC_2 + 11544585 + + + PORT_MEM_DQ_PINLOC_20 + 147992711 + + + PORT_MEM_DQ_PINLOC_21 + 151141518 + + + PORT_MEM_DQ_PINLOC_22 + 154290321 + + + PORT_MEM_DQ_PINLOC_23 + 161637528 + + + PORT_MEM_DQ_PINLOC_24 + 155 + + + PORT_MEM_DQ_PINLOC_25 + 0 + + + PORT_MEM_DQ_PINLOC_26 + 0 + + + PORT_MEM_DQ_PINLOC_27 + 0 + + + PORT_MEM_DQ_PINLOC_28 + 0 + + + PORT_MEM_DQ_PINLOC_29 + 0 + + + PORT_MEM_DQ_PINLOC_3 + 14693388 + + + PORT_MEM_DQ_PINLOC_30 + 0 + + + PORT_MEM_DQ_PINLOC_31 + 0 + + + PORT_MEM_DQ_PINLOC_32 + 0 + + + PORT_MEM_DQ_PINLOC_33 + 0 + + + PORT_MEM_DQ_PINLOC_34 + 0 + + + PORT_MEM_DQ_PINLOC_35 + 0 + + + PORT_MEM_DQ_PINLOC_36 + 0 + + + PORT_MEM_DQ_PINLOC_37 + 0 + + + PORT_MEM_DQ_PINLOC_38 + 0 + + + PORT_MEM_DQ_PINLOC_39 + 0 + + + PORT_MEM_DQ_PINLOC_4 + 22040591 + + + PORT_MEM_DQ_PINLOC_40 + 0 + + + PORT_MEM_DQ_PINLOC_41 + 0 + + + PORT_MEM_DQ_PINLOC_42 + 0 + + + PORT_MEM_DQ_PINLOC_43 + 0 + + + PORT_MEM_DQ_PINLOC_44 + 0 + + + PORT_MEM_DQ_PINLOC_45 + 0 + + + PORT_MEM_DQ_PINLOC_46 + 0 + + + PORT_MEM_DQ_PINLOC_47 + 0 + + + PORT_MEM_DQ_PINLOC_48 + 0 + + + PORT_MEM_DQ_PINLOC_5 + 25189398 + + + PORT_MEM_DQ_PINLOC_6 + 28338201 + + + PORT_MEM_DQ_PINLOC_7 + 35685408 + + + PORT_MEM_DQ_PINLOC_8 + 38834211 + + + PORT_MEM_DQ_PINLOC_9 + 46177318 + + + PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT + 49 + + + PORT_MEM_DQ_WIDTH + 72 + + + PORT_MEM_D_PINLOC_0 + 0 + + + PORT_MEM_D_PINLOC_1 + 0 + + + PORT_MEM_D_PINLOC_10 + 0 + + + PORT_MEM_D_PINLOC_11 + 0 + + + PORT_MEM_D_PINLOC_12 + 0 + + + PORT_MEM_D_PINLOC_13 + 0 + + + PORT_MEM_D_PINLOC_14 + 0 + + + PORT_MEM_D_PINLOC_15 + 0 + + + PORT_MEM_D_PINLOC_16 + 0 + + + PORT_MEM_D_PINLOC_17 + 0 + + + PORT_MEM_D_PINLOC_18 + 0 + + + PORT_MEM_D_PINLOC_19 + 0 + + + PORT_MEM_D_PINLOC_2 + 0 + + + PORT_MEM_D_PINLOC_20 + 0 + + + PORT_MEM_D_PINLOC_21 + 0 + + + PORT_MEM_D_PINLOC_22 + 0 + + + PORT_MEM_D_PINLOC_23 + 0 + + + PORT_MEM_D_PINLOC_24 + 0 + + + PORT_MEM_D_PINLOC_25 + 0 + + + PORT_MEM_D_PINLOC_26 + 0 + + + PORT_MEM_D_PINLOC_27 + 0 + + + PORT_MEM_D_PINLOC_28 + 0 + + + PORT_MEM_D_PINLOC_29 + 0 + + + PORT_MEM_D_PINLOC_3 + 0 + + + PORT_MEM_D_PINLOC_30 + 0 + + + PORT_MEM_D_PINLOC_31 + 0 + + + PORT_MEM_D_PINLOC_32 + 0 + + + PORT_MEM_D_PINLOC_33 + 0 + + + PORT_MEM_D_PINLOC_34 + 0 + + + PORT_MEM_D_PINLOC_35 + 0 + + + PORT_MEM_D_PINLOC_36 + 0 + + + PORT_MEM_D_PINLOC_37 + 0 + + + PORT_MEM_D_PINLOC_38 + 0 + + + PORT_MEM_D_PINLOC_39 + 0 + + + PORT_MEM_D_PINLOC_4 + 0 + + + PORT_MEM_D_PINLOC_40 + 0 + + + PORT_MEM_D_PINLOC_41 + 0 + + + PORT_MEM_D_PINLOC_42 + 0 + + + PORT_MEM_D_PINLOC_43 + 0 + + + PORT_MEM_D_PINLOC_44 + 0 + + + PORT_MEM_D_PINLOC_45 + 0 + + + PORT_MEM_D_PINLOC_46 + 0 + + + PORT_MEM_D_PINLOC_47 + 0 + + + PORT_MEM_D_PINLOC_48 + 0 + + + PORT_MEM_D_PINLOC_5 + 0 + + + PORT_MEM_D_PINLOC_6 + 0 + + + PORT_MEM_D_PINLOC_7 + 0 + + + PORT_MEM_D_PINLOC_8 + 0 + + + PORT_MEM_D_PINLOC_9 + 0 + + + PORT_MEM_D_PINLOC_AUTOGEN_WCNT + 49 + + + PORT_MEM_D_WIDTH + 1 + + + PORT_MEM_ERR_N_PINLOC_0 + 0 + + + PORT_MEM_ERR_N_PINLOC_1 + 0 + + + PORT_MEM_ERR_N_PINLOC_2 + 0 + + + PORT_MEM_ERR_N_PINLOC_3 + 0 + + + PORT_MEM_ERR_N_PINLOC_4 + 0 + + + PORT_MEM_ERR_N_PINLOC_5 + 0 + + + PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_ERR_N_WIDTH + 1 + + + PORT_MEM_GNT_N_PINLOC_0 + 0 + + + PORT_MEM_GNT_N_PINLOC_1 + 0 + + + PORT_MEM_GNT_N_PINLOC_2 + 0 + + + PORT_MEM_GNT_N_PINLOC_3 + 0 + + + PORT_MEM_GNT_N_PINLOC_4 + 0 + + + PORT_MEM_GNT_N_PINLOC_5 + 0 + + + PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_GNT_N_WIDTH + 1 + + + PORT_MEM_K_N_PINLOC_0 + 0 + + + PORT_MEM_K_N_PINLOC_1 + 0 + + + PORT_MEM_K_N_PINLOC_2 + 0 + + + PORT_MEM_K_N_PINLOC_3 + 0 + + + PORT_MEM_K_N_PINLOC_4 + 0 + + + PORT_MEM_K_N_PINLOC_5 + 0 + + + PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_K_N_WIDTH + 1 + + + PORT_MEM_K_PINLOC_0 + 0 + + + PORT_MEM_K_PINLOC_1 + 0 + + + PORT_MEM_K_PINLOC_2 + 0 + + + PORT_MEM_K_PINLOC_3 + 0 + + + PORT_MEM_K_PINLOC_4 + 0 + + + PORT_MEM_K_PINLOC_5 + 0 + + + PORT_MEM_K_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_K_WIDTH + 1 + + + PORT_MEM_LBK0_N_PINLOC_0 + 0 + + + PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_LBK0_N_WIDTH + 1 + + + PORT_MEM_LBK1_N_PINLOC_0 + 0 + + + PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_LBK1_N_WIDTH + 1 + + + PORT_MEM_LDA_N_PINLOC_0 + 0 + + + PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_LDA_N_WIDTH + 1 + + + PORT_MEM_LDB_N_PINLOC_0 + 0 + + + PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_LDB_N_WIDTH + 1 + + + PORT_MEM_ODT_PINLOC_0 + 53249 + + + PORT_MEM_ODT_PINLOC_1 + 0 + + + PORT_MEM_ODT_PINLOC_2 + 0 + + + PORT_MEM_ODT_PINLOC_3 + 0 + + + PORT_MEM_ODT_PINLOC_4 + 0 + + + PORT_MEM_ODT_PINLOC_5 + 0 + + + PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_ODT_WIDTH + 1 + + + PORT_MEM_PAR_PINLOC_0 + 60417 + + + PORT_MEM_PAR_PINLOC_1 + 0 + + + PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_PAR_WIDTH + 1 + + + PORT_MEM_PE_N_PINLOC_0 + 0 + + + PORT_MEM_PE_N_PINLOC_1 + 0 + + + PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_PE_N_WIDTH + 1 + + + PORT_MEM_QKA_N_PINLOC_0 + 0 + + + PORT_MEM_QKA_N_PINLOC_1 + 0 + + + PORT_MEM_QKA_N_PINLOC_2 + 0 + + + PORT_MEM_QKA_N_PINLOC_3 + 0 + + + PORT_MEM_QKA_N_PINLOC_4 + 0 + + + PORT_MEM_QKA_N_PINLOC_5 + 0 + + + PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_QKA_N_WIDTH + 1 + + + PORT_MEM_QKA_PINLOC_0 + 0 + + + PORT_MEM_QKA_PINLOC_1 + 0 + + + PORT_MEM_QKA_PINLOC_2 + 0 + + + PORT_MEM_QKA_PINLOC_3 + 0 + + + PORT_MEM_QKA_PINLOC_4 + 0 + + + PORT_MEM_QKA_PINLOC_5 + 0 + + + PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_QKA_WIDTH + 1 + + + PORT_MEM_QKB_N_PINLOC_0 + 0 + + + PORT_MEM_QKB_N_PINLOC_1 + 0 + + + PORT_MEM_QKB_N_PINLOC_2 + 0 + + + PORT_MEM_QKB_N_PINLOC_3 + 0 + + + PORT_MEM_QKB_N_PINLOC_4 + 0 + + + PORT_MEM_QKB_N_PINLOC_5 + 0 + + + PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_QKB_N_WIDTH + 1 + + + PORT_MEM_QKB_PINLOC_0 + 0 + + + PORT_MEM_QKB_PINLOC_1 + 0 + + + PORT_MEM_QKB_PINLOC_2 + 0 + + + PORT_MEM_QKB_PINLOC_3 + 0 + + + PORT_MEM_QKB_PINLOC_4 + 0 + + + PORT_MEM_QKB_PINLOC_5 + 0 + + + PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_QKB_WIDTH + 1 + + + PORT_MEM_QK_N_PINLOC_0 + 0 + + + PORT_MEM_QK_N_PINLOC_1 + 0 + + + PORT_MEM_QK_N_PINLOC_2 + 0 + + + PORT_MEM_QK_N_PINLOC_3 + 0 + + + PORT_MEM_QK_N_PINLOC_4 + 0 + + + PORT_MEM_QK_N_PINLOC_5 + 0 + + + PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_QK_N_WIDTH + 1 + + + PORT_MEM_QK_PINLOC_0 + 0 + + + PORT_MEM_QK_PINLOC_1 + 0 + + + PORT_MEM_QK_PINLOC_2 + 0 + + + PORT_MEM_QK_PINLOC_3 + 0 + + + PORT_MEM_QK_PINLOC_4 + 0 + + + PORT_MEM_QK_PINLOC_5 + 0 + + + PORT_MEM_QK_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_QK_WIDTH + 1 + + + PORT_MEM_Q_PINLOC_0 + 0 + + + PORT_MEM_Q_PINLOC_1 + 0 + + + PORT_MEM_Q_PINLOC_10 + 0 + + + PORT_MEM_Q_PINLOC_11 + 0 + + + PORT_MEM_Q_PINLOC_12 + 0 + + + PORT_MEM_Q_PINLOC_13 + 0 + + + PORT_MEM_Q_PINLOC_14 + 0 + + + PORT_MEM_Q_PINLOC_15 + 0 + + + PORT_MEM_Q_PINLOC_16 + 0 + + + PORT_MEM_Q_PINLOC_17 + 0 + + + PORT_MEM_Q_PINLOC_18 + 0 + + + PORT_MEM_Q_PINLOC_19 + 0 + + + PORT_MEM_Q_PINLOC_2 + 0 + + + PORT_MEM_Q_PINLOC_20 + 0 + + + PORT_MEM_Q_PINLOC_21 + 0 + + + PORT_MEM_Q_PINLOC_22 + 0 + + + PORT_MEM_Q_PINLOC_23 + 0 + + + PORT_MEM_Q_PINLOC_24 + 0 + + + PORT_MEM_Q_PINLOC_25 + 0 + + + PORT_MEM_Q_PINLOC_26 + 0 + + + PORT_MEM_Q_PINLOC_27 + 0 + + + PORT_MEM_Q_PINLOC_28 + 0 + + + PORT_MEM_Q_PINLOC_29 + 0 + + + PORT_MEM_Q_PINLOC_3 + 0 + + + PORT_MEM_Q_PINLOC_30 + 0 + + + PORT_MEM_Q_PINLOC_31 + 0 + + + PORT_MEM_Q_PINLOC_32 + 0 + + + PORT_MEM_Q_PINLOC_33 + 0 + + + PORT_MEM_Q_PINLOC_34 + 0 + + + PORT_MEM_Q_PINLOC_35 + 0 + + + PORT_MEM_Q_PINLOC_36 + 0 + + + PORT_MEM_Q_PINLOC_37 + 0 + + + PORT_MEM_Q_PINLOC_38 + 0 + + + PORT_MEM_Q_PINLOC_39 + 0 + + + PORT_MEM_Q_PINLOC_4 + 0 + + + PORT_MEM_Q_PINLOC_40 + 0 + + + PORT_MEM_Q_PINLOC_41 + 0 + + + PORT_MEM_Q_PINLOC_42 + 0 + + + PORT_MEM_Q_PINLOC_43 + 0 + + + PORT_MEM_Q_PINLOC_44 + 0 + + + PORT_MEM_Q_PINLOC_45 + 0 + + + PORT_MEM_Q_PINLOC_46 + 0 + + + PORT_MEM_Q_PINLOC_47 + 0 + + + PORT_MEM_Q_PINLOC_48 + 0 + + + PORT_MEM_Q_PINLOC_5 + 0 + + + PORT_MEM_Q_PINLOC_6 + 0 + + + PORT_MEM_Q_PINLOC_7 + 0 + + + PORT_MEM_Q_PINLOC_8 + 0 + + + PORT_MEM_Q_PINLOC_9 + 0 + + + PORT_MEM_Q_PINLOC_AUTOGEN_WCNT + 49 + + + PORT_MEM_Q_WIDTH + 1 + + + PORT_MEM_RAS_N_PINLOC_0 + 0 + + + PORT_MEM_RAS_N_PINLOC_1 + 0 + + + PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_RAS_N_WIDTH + 1 + + + PORT_MEM_REF_N_PINLOC_0 + 0 + + + PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_REF_N_WIDTH + 1 + + + PORT_MEM_REQ_N_PINLOC_0 + 0 + + + PORT_MEM_REQ_N_PINLOC_1 + 0 + + + PORT_MEM_REQ_N_PINLOC_2 + 0 + + + PORT_MEM_REQ_N_PINLOC_3 + 0 + + + PORT_MEM_REQ_N_PINLOC_4 + 0 + + + PORT_MEM_REQ_N_PINLOC_5 + 0 + + + PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_REQ_N_WIDTH + 1 + + + PORT_MEM_RESET_N_PINLOC_0 + 50177 + + + PORT_MEM_RESET_N_PINLOC_1 + 0 + + + PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_RESET_N_WIDTH + 1 + + + PORT_MEM_RM_PINLOC_0 + 0 + + + PORT_MEM_RM_PINLOC_1 + 0 + + + PORT_MEM_RM_PINLOC_2 + 0 + + + PORT_MEM_RM_PINLOC_3 + 0 + + + PORT_MEM_RM_PINLOC_4 + 0 + + + PORT_MEM_RM_PINLOC_5 + 0 + + + PORT_MEM_RM_PINLOC_AUTOGEN_WCNT + 6 + + + PORT_MEM_RM_WIDTH + 1 + + + PORT_MEM_RPS_N_PINLOC_0 + 0 + + + PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_RPS_N_WIDTH + 1 + + + PORT_MEM_RWA_N_PINLOC_0 + 0 + + + PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_RWA_N_WIDTH + 1 + + + PORT_MEM_RWB_N_PINLOC_0 + 0 + + + PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_RWB_N_WIDTH + 1 + + + PORT_MEM_WE_N_PINLOC_0 + 0 + + + PORT_MEM_WE_N_PINLOC_1 + 0 + + + PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT + 2 + + + PORT_MEM_WE_N_WIDTH + 1 + + + PORT_MEM_WPS_N_PINLOC_0 + 0 + + + PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT + 1 + + + PORT_MEM_WPS_N_WIDTH + 1 + + + PREAMBLE_MODE + preamble_one_cycle + + + PREV_PROTOCOL_ENUM + PROTOCOL_DDR4 + + + PRI_AC_TILE_INDEX + 1 + + + PRI_HMC_3DSREF_ACK_ON_DONE + disable + + + PRI_HMC_3DS_EN + disable + + + PRI_HMC_3DS_LR_NUM0 + 0 + + + PRI_HMC_3DS_LR_NUM1 + 0 + + + PRI_HMC_3DS_LR_NUM2 + 0 + + + PRI_HMC_3DS_LR_NUM3 + 0 + + + PRI_HMC_3DS_PR_STAG_ENABLE + disable + + + PRI_HMC_3DS_REF2REF_DLR + 1 + + + PRI_HMC_CFG_16_ACT_TO_ACT + 0 + + + PRI_HMC_CFG_4_ACT_TO_ACT + 12 + + + PRI_HMC_CFG_ACT_TO_ACT + 28 + + + PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK + 3 + + + PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG + 2 + + + PRI_HMC_CFG_ACT_TO_PCH + 20 + + + PRI_HMC_CFG_ACT_TO_RDWR + 8 + + + PRI_HMC_CFG_ADDR_ORDER + addr_order_cs_row_ba_col + + + PRI_HMC_CFG_ARBITER_TYPE + arbiter_type_2t + + + PRI_HMC_CFG_ARF_PERIOD + 4681 + + + PRI_HMC_CFG_ARF_TO_VALID + 211 + + + PRI_HMC_CFG_BANK_ADDR_WIDTH + bank_width_2 + + + PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH + bank_group_width_2 + + + PRI_HMC_CFG_CMD_FIFO_RESERVE_EN + enable + + + PRI_HMC_CFG_COL_ADDR_WIDTH + col_width_10 + + + PRI_HMC_CFG_COL_CMD_SLOT + 2 + + + PRI_HMC_CFG_COL_TO_COL_OFFSET + 0 + + + PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET + 0 + + + PRI_HMC_CFG_COL_TO_ROW_OFFSET + 1 + + + PRI_HMC_CFG_CS_ADDR_WIDTH + cs_width_0 + + + PRI_HMC_CFG_CS_TO_CHIP_MAPPING + 33825 + + + PRI_HMC_CFG_CTL_ODT_ENABLED + 1 + + + PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN + 0 + + + PRI_HMC_CFG_CTRL_ENABLE_ECC + enable + + + PRI_HMC_CFG_CTRL_ENABLE_RC + enable + + + PRI_HMC_CFG_CTRL_REORDER_RDATA + disable + + + PRI_HMC_CFG_CTRL_SLOT_OFFSET + 2 + + + PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN + ctrl_disable + + + PRI_HMC_CFG_DBC0_ENABLE_ECC + enable + + + PRI_HMC_CFG_DBC0_ENABLE_RC + enable + + + PRI_HMC_CFG_DBC0_REORDER_RDATA + disable + + + PRI_HMC_CFG_DBC0_SLOT_OFFSET + 2 + + + PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN + dbc0_disable + + + PRI_HMC_CFG_DBC1_ENABLE_ECC + enable + + + PRI_HMC_CFG_DBC1_ENABLE_RC + enable + + + PRI_HMC_CFG_DBC1_REORDER_RDATA + disable + + + PRI_HMC_CFG_DBC1_SLOT_OFFSET + 2 + + + PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN + dbc1_disable + + + PRI_HMC_CFG_DBC2_ENABLE_ECC + enable + + + PRI_HMC_CFG_DBC2_ENABLE_RC + enable + + + PRI_HMC_CFG_DBC2_REORDER_RDATA + disable + + + PRI_HMC_CFG_DBC2_SLOT_OFFSET + 2 + + + PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN + dbc2_disable + + + PRI_HMC_CFG_DBC3_ENABLE_ECC + enable + + + PRI_HMC_CFG_DBC3_ENABLE_RC + enable + + + PRI_HMC_CFG_DBC3_REORDER_RDATA + disable + + + PRI_HMC_CFG_DBC3_SLOT_OFFSET + 2 + + + PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN + dbc3_disable + + + PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR + disable + + + PRI_HMC_CFG_DQSTRK_EN + disable + + + PRI_HMC_CFG_DQSTRK_TO_VALID + 4 + + + PRI_HMC_CFG_DQSTRK_TO_VALID_LAST + 26 + + + PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD + 0 + + + PRI_HMC_CFG_GEAR_DOWN_EN + disable + + + PRI_HMC_CFG_MAJOR_MODE_EN + disable + + + PRI_HMC_CFG_MEM_AUTO_PD_CYCLES + 0 + + + PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC + 15 + + + PRI_HMC_CFG_MMR_CMD_TO_VALID + 16 + + + PRI_HMC_CFG_MPR_TO_VALID + 16 + + + PRI_HMC_CFG_MPS_DQSTRK_DISABLE + disable + + + PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS + 6 + + + PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE + 5 + + + PRI_HMC_CFG_MPS_TO_VALID + 768 + + + PRI_HMC_CFG_MPS_ZQCAL_DISABLE + disable + + + PRI_HMC_CFG_MRR_TO_VALID + 0 + + + PRI_HMC_CFG_MRS_TO_VALID + 12 + + + PRI_HMC_CFG_OPEN_PAGE_EN + disable + + + PRI_HMC_CFG_PCH_ALL_TO_VALID + 9 + + + PRI_HMC_CFG_PCH_TO_VALID + 9 + + + PRI_HMC_CFG_PDN_PERIOD + 0 + + + PRI_HMC_CFG_PDN_TO_VALID + 5 + + + PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN + disable + + + PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL + 0 + + + PRI_HMC_CFG_PHY_DELAY_MISMATCH + 0 + + + PRI_HMC_CFG_PING_PONG_MODE + pingpong_off + + + PRI_HMC_CFG_POST_REFRESH_EN + enable + + + PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT + 0 + + + PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT + 2 + + + PRI_HMC_CFG_POWER_SAVING_EXIT_CYC + 3 + + + PRI_HMC_CFG_PRE_REFRESH_EN + disable + + + PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT + 1 + + + PRI_HMC_CFG_RB_RESERVED_ENTRY + 8 + + + PRI_HMC_CFG_RD_AP_TO_VALID + 14 + + + PRI_HMC_CFG_RD_ODT_ON + 4 + + + PRI_HMC_CFG_RD_ODT_PERIOD + 7 + + + PRI_HMC_CFG_RD_TO_PCH + 5 + + + PRI_HMC_CFG_RD_TO_RD + 3 + + + PRI_HMC_CFG_RD_TO_RD_DIFF_BG + 2 + + + PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP + 4 + + + PRI_HMC_CFG_RD_TO_WR + 10 + + + PRI_HMC_CFG_RD_TO_WR_DIFF_BG + 10 + + + PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP + 10 + + + PRI_HMC_CFG_READ_ODT_CHIP + 0 + + + PRI_HMC_CFG_REFRESH_TYPE + 0 + + + PRI_HMC_CFG_REORDER_DATA + enable + + + PRI_HMC_CFG_REORDER_READ + disable + + + PRI_HMC_CFG_RFSH_WARN_THRESHOLD + 0 + + + PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY + 0 + + + PRI_HMC_CFG_RLD3_REFRESH_SEQ0 + 0 + + + PRI_HMC_CFG_RLD3_REFRESH_SEQ1 + 0 + + + PRI_HMC_CFG_RLD3_REFRESH_SEQ2 + 0 + + + PRI_HMC_CFG_RLD3_REFRESH_SEQ3 + 0 + + + PRI_HMC_CFG_ROW_ADDR_WIDTH + row_width_16 + + + PRI_HMC_CFG_ROW_CMD_SLOT + 1 + + + PRI_HMC_CFG_ROW_TO_COL_OFFSET + -1 + + + PRI_HMC_CFG_ROW_TO_ROW_OFFSET + 0 + + + PRI_HMC_CFG_SB_CG_DISABLE + disable + + + PRI_HMC_CFG_SB_DDR4_MR3 + 197632 + + + PRI_HMC_CFG_SB_DDR4_MR4 + 264192 + + + PRI_HMC_CFG_SB_DDR4_MR5 + 5216 + + + PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN + disable + + + PRI_HMC_CFG_SIDEBAND_OFFSET + 1 + + + PRI_HMC_CFG_SRF_AUTOEXIT_EN + disable + + + PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK + 0 + + + PRI_HMC_CFG_SRF_TO_VALID + 513 + + + PRI_HMC_CFG_SRF_TO_ZQ_CAL + 385 + + + PRI_HMC_CFG_SRF_ZQCAL_DISABLE + disable + + + PRI_HMC_CFG_STARVE_LIMIT + 10 + + + PRI_HMC_CFG_TCL + 21 + + + PRI_HMC_CFG_USER_RFSH_EN + disable + + + PRI_HMC_CFG_WB_RESERVED_ENTRY + 52 + + + PRI_HMC_CFG_WRITE_ODT_CHIP + 0 + + + PRI_HMC_CFG_WR_AP_TO_VALID + 28 + + + PRI_HMC_CFG_WR_ODT_ON + 0 + + + PRI_HMC_CFG_WR_ODT_PERIOD + 6 + + + PRI_HMC_CFG_WR_TO_PCH + 20 + + + PRI_HMC_CFG_WR_TO_RD + 19 + + + PRI_HMC_CFG_WR_TO_RD_DIFF_BG + 17 + + + PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP + 15 + + + PRI_HMC_CFG_WR_TO_WR + 3 + + + PRI_HMC_CFG_WR_TO_WR_DIFF_BG + 2 + + + PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP + 3 + + + PRI_HMC_CFG_ZQCL_TO_VALID + 257 + + + PRI_HMC_CFG_ZQCS_TO_VALID + 127 + + + PRI_HMC_CHIP_ID + 273 + + + PRI_HMC_CID_ADDR_WIDTH + 0 + + + PRI_HMC_MEMCLKGATE_SETTING + 0 + + + PRI_HMC_MEM_IF_AL + 0 + + + PRI_HMC_MEM_IF_CS_PER_DIMM + 0 + + + PRI_HMC_MEM_IF_RD_PREAMBLE + 0 + + + PRI_HMC_MEM_IF_TCCD + 0 + + + PRI_HMC_MEM_IF_TCCD_S + 0 + + + PRI_HMC_MEM_IF_TCKESR + 0 + + + PRI_HMC_MEM_IF_TCKSRX + 0 + + + PRI_HMC_MEM_IF_TCL + 0 + + + PRI_HMC_MEM_IF_TCWL + 0 + + + PRI_HMC_MEM_IF_TDQSCKMAX + 0 + + + PRI_HMC_MEM_IF_TFAW + 0 + + + PRI_HMC_MEM_IF_TMOD + 0 + + + PRI_HMC_MEM_IF_TPL + 0 + + + PRI_HMC_MEM_IF_TRAS + 0 + + + PRI_HMC_MEM_IF_TRC + 0 + + + PRI_HMC_MEM_IF_TRCD + 0 + + + PRI_HMC_MEM_IF_TREFI + 0 + + + PRI_HMC_MEM_IF_TRFC + 0 + + + PRI_HMC_MEM_IF_TRP + 0 + + + PRI_HMC_MEM_IF_TRRD + 0 + + + PRI_HMC_MEM_IF_TRRD_S + 0 + + + PRI_HMC_MEM_IF_TRTP + 0 + + + PRI_HMC_MEM_IF_TWR + 0 + + + PRI_HMC_MEM_IF_TWR_CRC_DM + 0 + + + PRI_HMC_MEM_IF_TWTR + 0 + + + PRI_HMC_MEM_IF_TWTR_L_CRC_DM + 0 + + + PRI_HMC_MEM_IF_TWTR_S + 0 + + + PRI_HMC_MEM_IF_TWTR_S_CRC_DM + 0 + + + PRI_HMC_MEM_IF_TXP + 0 + + + PRI_HMC_MEM_IF_TXPDLL + 0 + + + PRI_HMC_MEM_IF_TXSR + 0 + + + PRI_HMC_MEM_IF_TZQCS + 0 + + + PRI_HMC_MEM_IF_TZQOPER + 0 + + + PRI_HMC_MEM_IF_WR_CRC + 0 + + + PRI_HMC_MEM_IF_WR_PREAMBLE + 0 + + + PRI_HMC_TEMP_4_ACT_TO_ACT + 0 + + + PRI_HMC_TEMP_RD_TO_RD_DIFF_BG + 0 + + + PRI_HMC_TEMP_WR_TO_RD + 0 + + + PRI_HMC_TEMP_WR_TO_RD_DIFF_BG + 0 + + + PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP + 0 + + + PRI_HMC_TEMP_WR_TO_WR_DIFF_BG + 0 + + + PRI_RDATA_LANE_INDEX + 0 + + + PRI_RDATA_TILE_INDEX + 0 + + + PRI_WDATA_LANE_INDEX + 0 + + + PRI_WDATA_TILE_INDEX + 0 + + + PROTOCOL_ENUM + PROTOCOL_DDR4 + + + REGISTER_AFI_C2P + 1 + + + REGISTER_AFI_P2C + 1 + + + REGISTER_AMM_C2P + 1 + + + REGISTER_AMM_P2C + 1 + + + SEC_AC_TILE_INDEX + 1 + + + SEC_HMC_3DSREF_ACK_ON_DONE + disable + + + SEC_HMC_3DS_EN + disable + + + SEC_HMC_3DS_LR_NUM0 + 0 + + + SEC_HMC_3DS_LR_NUM1 + 0 + + + SEC_HMC_3DS_LR_NUM2 + 0 + + + SEC_HMC_3DS_LR_NUM3 + 0 + + + SEC_HMC_3DS_PR_STAG_ENABLE + disable + + + SEC_HMC_3DS_REF2REF_DLR + 1 + + + SEC_HMC_CFG_16_ACT_TO_ACT + 0 + + + SEC_HMC_CFG_4_ACT_TO_ACT + 12 + + + SEC_HMC_CFG_ACT_TO_ACT + 28 + + + SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK + 3 + + + SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG + 2 + + + SEC_HMC_CFG_ACT_TO_PCH + 20 + + + SEC_HMC_CFG_ACT_TO_RDWR + 8 + + + SEC_HMC_CFG_ADDR_ORDER + addr_order_cs_row_ba_col + + + SEC_HMC_CFG_ARBITER_TYPE + arbiter_type_2t + + + SEC_HMC_CFG_ARF_PERIOD + 4681 + + + SEC_HMC_CFG_ARF_TO_VALID + 211 + + + SEC_HMC_CFG_BANK_ADDR_WIDTH + bank_width_2 + + + SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH + bank_group_width_2 + + + SEC_HMC_CFG_CMD_FIFO_RESERVE_EN + enable + + + SEC_HMC_CFG_COL_ADDR_WIDTH + col_width_10 + + + SEC_HMC_CFG_COL_CMD_SLOT + 2 + + + SEC_HMC_CFG_COL_TO_COL_OFFSET + 0 + + + SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET + 0 + + + SEC_HMC_CFG_COL_TO_ROW_OFFSET + 1 + + + SEC_HMC_CFG_CS_ADDR_WIDTH + cs_width_0 + + + SEC_HMC_CFG_CS_TO_CHIP_MAPPING + 33825 + + + SEC_HMC_CFG_CTL_ODT_ENABLED + 1 + + + SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN + 0 + + + SEC_HMC_CFG_CTRL_ENABLE_ECC + enable + + + SEC_HMC_CFG_CTRL_ENABLE_RC + enable + + + SEC_HMC_CFG_CTRL_REORDER_RDATA + disable + + + SEC_HMC_CFG_CTRL_SLOT_OFFSET + 2 + + + SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN + ctrl_disable + + + SEC_HMC_CFG_DBC0_ENABLE_ECC + enable + + + SEC_HMC_CFG_DBC0_ENABLE_RC + enable + + + SEC_HMC_CFG_DBC0_REORDER_RDATA + disable + + + SEC_HMC_CFG_DBC0_SLOT_OFFSET + 2 + + + SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN + dbc0_disable + + + SEC_HMC_CFG_DBC1_ENABLE_ECC + enable + + + SEC_HMC_CFG_DBC1_ENABLE_RC + enable + + + SEC_HMC_CFG_DBC1_REORDER_RDATA + disable + + + SEC_HMC_CFG_DBC1_SLOT_OFFSET + 2 + + + SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN + dbc1_disable + + + SEC_HMC_CFG_DBC2_ENABLE_ECC + enable + + + SEC_HMC_CFG_DBC2_ENABLE_RC + enable + + + SEC_HMC_CFG_DBC2_REORDER_RDATA + disable + + + SEC_HMC_CFG_DBC2_SLOT_OFFSET + 2 + + + SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN + dbc2_disable + + + SEC_HMC_CFG_DBC3_ENABLE_ECC + enable + + + SEC_HMC_CFG_DBC3_ENABLE_RC + enable + + + SEC_HMC_CFG_DBC3_REORDER_RDATA + disable + + + SEC_HMC_CFG_DBC3_SLOT_OFFSET + 2 + + + SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN + dbc3_disable + + + SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR + disable + + + SEC_HMC_CFG_DQSTRK_EN + disable + + + SEC_HMC_CFG_DQSTRK_TO_VALID + 4 + + + SEC_HMC_CFG_DQSTRK_TO_VALID_LAST + 26 + + + SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD + 0 + + + SEC_HMC_CFG_GEAR_DOWN_EN + disable + + + SEC_HMC_CFG_MAJOR_MODE_EN + disable + + + SEC_HMC_CFG_MEM_AUTO_PD_CYCLES + 0 + + + SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC + 15 + + + SEC_HMC_CFG_MMR_CMD_TO_VALID + 16 + + + SEC_HMC_CFG_MPR_TO_VALID + 16 + + + SEC_HMC_CFG_MPS_DQSTRK_DISABLE + disable + + + SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS + 6 + + + SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE + 5 + + + SEC_HMC_CFG_MPS_TO_VALID + 768 + + + SEC_HMC_CFG_MPS_ZQCAL_DISABLE + disable + + + SEC_HMC_CFG_MRR_TO_VALID + 0 + + + SEC_HMC_CFG_MRS_TO_VALID + 12 + + + SEC_HMC_CFG_OPEN_PAGE_EN + disable + + + SEC_HMC_CFG_PCH_ALL_TO_VALID + 9 + + + SEC_HMC_CFG_PCH_TO_VALID + 9 + + + SEC_HMC_CFG_PDN_PERIOD + 0 + + + SEC_HMC_CFG_PDN_TO_VALID + 5 + + + SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN + disable + + + SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL + 0 + + + SEC_HMC_CFG_PHY_DELAY_MISMATCH + 0 + + + SEC_HMC_CFG_PING_PONG_MODE + pingpong_off + + + SEC_HMC_CFG_POST_REFRESH_EN + enable + + + SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT + 0 + + + SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT + 2 + + + SEC_HMC_CFG_POWER_SAVING_EXIT_CYC + 3 + + + SEC_HMC_CFG_PRE_REFRESH_EN + disable + + + SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT + 1 + + + SEC_HMC_CFG_RB_RESERVED_ENTRY + 8 + + + SEC_HMC_CFG_RD_AP_TO_VALID + 14 + + + SEC_HMC_CFG_RD_ODT_ON + 4 + + + SEC_HMC_CFG_RD_ODT_PERIOD + 7 + + + SEC_HMC_CFG_RD_TO_PCH + 5 + + + SEC_HMC_CFG_RD_TO_RD + 3 + + + SEC_HMC_CFG_RD_TO_RD_DIFF_BG + 2 + + + SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP + 4 + + + SEC_HMC_CFG_RD_TO_WR + 10 + + + SEC_HMC_CFG_RD_TO_WR_DIFF_BG + 10 + + + SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP + 10 + + + SEC_HMC_CFG_READ_ODT_CHIP + 0 + + + SEC_HMC_CFG_REFRESH_TYPE + 0 + + + SEC_HMC_CFG_REORDER_DATA + enable + + + SEC_HMC_CFG_REORDER_READ + disable + + + SEC_HMC_CFG_RFSH_WARN_THRESHOLD + 0 + + + SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY + 0 + + + SEC_HMC_CFG_RLD3_REFRESH_SEQ0 + 0 + + + SEC_HMC_CFG_RLD3_REFRESH_SEQ1 + 0 + + + SEC_HMC_CFG_RLD3_REFRESH_SEQ2 + 0 + + + SEC_HMC_CFG_RLD3_REFRESH_SEQ3 + 0 + + + SEC_HMC_CFG_ROW_ADDR_WIDTH + row_width_16 + + + SEC_HMC_CFG_ROW_CMD_SLOT + 1 + + + SEC_HMC_CFG_ROW_TO_COL_OFFSET + -1 + + + SEC_HMC_CFG_ROW_TO_ROW_OFFSET + 0 + + + SEC_HMC_CFG_SB_CG_DISABLE + disable + + + SEC_HMC_CFG_SB_DDR4_MR3 + 197632 + + + SEC_HMC_CFG_SB_DDR4_MR4 + 264192 + + + SEC_HMC_CFG_SB_DDR4_MR5 + 5216 + + + SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN + disable + + + SEC_HMC_CFG_SIDEBAND_OFFSET + 1 + + + SEC_HMC_CFG_SRF_AUTOEXIT_EN + disable + + + SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK + 0 + + + SEC_HMC_CFG_SRF_TO_VALID + 513 + + + SEC_HMC_CFG_SRF_TO_ZQ_CAL + 385 + + + SEC_HMC_CFG_SRF_ZQCAL_DISABLE + disable + + + SEC_HMC_CFG_STARVE_LIMIT + 10 + + + SEC_HMC_CFG_TCL + 21 + + + SEC_HMC_CFG_USER_RFSH_EN + disable + + + SEC_HMC_CFG_WB_RESERVED_ENTRY + 52 + + + SEC_HMC_CFG_WRITE_ODT_CHIP + 0 + + + SEC_HMC_CFG_WR_AP_TO_VALID + 28 + + + SEC_HMC_CFG_WR_ODT_ON + 0 + + + SEC_HMC_CFG_WR_ODT_PERIOD + 6 + + + SEC_HMC_CFG_WR_TO_PCH + 20 + + + SEC_HMC_CFG_WR_TO_RD + 19 + + + SEC_HMC_CFG_WR_TO_RD_DIFF_BG + 17 + + + SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP + 15 + + + SEC_HMC_CFG_WR_TO_WR + 3 + + + SEC_HMC_CFG_WR_TO_WR_DIFF_BG + 2 + + + SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP + 3 + + + SEC_HMC_CFG_ZQCL_TO_VALID + 257 + + + SEC_HMC_CFG_ZQCS_TO_VALID + 127 + + + SEC_HMC_CHIP_ID + 273 + + + SEC_HMC_CID_ADDR_WIDTH + 0 + + + SEC_HMC_MEMCLKGATE_SETTING + 0 + + + SEC_HMC_MEM_IF_AL + 0 + + + SEC_HMC_MEM_IF_CS_PER_DIMM + 0 + + + SEC_HMC_MEM_IF_RD_PREAMBLE + 0 + + + SEC_HMC_MEM_IF_TCCD + 0 + + + SEC_HMC_MEM_IF_TCCD_S + 0 + + + SEC_HMC_MEM_IF_TCKESR + 0 + + + SEC_HMC_MEM_IF_TCKSRX + 0 + + + SEC_HMC_MEM_IF_TCL + 0 + + + SEC_HMC_MEM_IF_TCWL + 0 + + + SEC_HMC_MEM_IF_TDQSCKMAX + 0 + + + SEC_HMC_MEM_IF_TFAW + 0 + + + SEC_HMC_MEM_IF_TMOD + 0 + + + SEC_HMC_MEM_IF_TPL + 0 + + + SEC_HMC_MEM_IF_TRAS + 0 + + + SEC_HMC_MEM_IF_TRC + 0 + + + SEC_HMC_MEM_IF_TRCD + 0 + + + SEC_HMC_MEM_IF_TREFI + 0 + + + SEC_HMC_MEM_IF_TRFC + 0 + + + SEC_HMC_MEM_IF_TRP + 0 + + + SEC_HMC_MEM_IF_TRRD + 0 + + + SEC_HMC_MEM_IF_TRRD_S + 0 + + + SEC_HMC_MEM_IF_TRTP + 0 + + + SEC_HMC_MEM_IF_TWR + 0 + + + SEC_HMC_MEM_IF_TWR_CRC_DM + 0 + + + SEC_HMC_MEM_IF_TWTR + 0 + + + SEC_HMC_MEM_IF_TWTR_L_CRC_DM + 0 + + + SEC_HMC_MEM_IF_TWTR_S + 0 + + + SEC_HMC_MEM_IF_TWTR_S_CRC_DM + 0 + + + SEC_HMC_MEM_IF_TXP + 0 + + + SEC_HMC_MEM_IF_TXPDLL + 0 + + + SEC_HMC_MEM_IF_TXSR + 0 + + + SEC_HMC_MEM_IF_TZQCS + 0 + + + SEC_HMC_MEM_IF_TZQOPER + 0 + + + SEC_HMC_MEM_IF_WR_CRC + 0 + + + SEC_HMC_MEM_IF_WR_PREAMBLE + 0 + + + SEC_HMC_TEMP_4_ACT_TO_ACT + 0 + + + SEC_HMC_TEMP_RD_TO_RD_DIFF_BG + 0 + + + SEC_HMC_TEMP_WR_TO_RD + 0 + + + SEC_HMC_TEMP_WR_TO_RD_DIFF_BG + 0 + + + SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP + 0 + + + SEC_HMC_TEMP_WR_TO_WR_DIFF_BG + 0 + + + SEC_RDATA_LANE_INDEX + 0 + + + SEC_RDATA_TILE_INDEX + 0 + + + SEC_WDATA_LANE_INDEX + 0 + + + SEC_WDATA_TILE_INDEX + 0 + + + SEQ_C2P_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + SEQ_HIPI_DELAY + 350 + + + SEQ_P2C_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + SEQ_PT_SIM_CONTENT + 00024c400000000000000201000927c001121708480909010102110902000101051401000904043400000000000000000d20e08100b0000000000000000000005077d58000c4070c017000d80000012300001e780000015e00000000000000081c14040c0b0a0908030201001312111000000018000000060000000400020301000000002b2a290012111000161514131a1918172524231b0000272600380b0000000908000000003424140474645444251505846555453516068575564636260086766608030201100b0a0918131211201b1a1928232221302b2a2938333231403b3a3948434241504b4a4958535251605b5a5968636261706b6a6978737271807b7a7988838281008b8a890000087400010001000200280003040000040800000514600006080f0f5560000d40030b003900002000000000000000 + + + SEQ_PT_SYN_CONTENT + 00024c400000000000000201000927c001121708480909010102110902000101051401000904043400000000000000000d00c08100b0000000000000000000005066008000c4070c017000d80000012300001e780000015e00000000000000081c14040c0b0a0908030201001312111000000018000000060000000400020301000000002b2a290012111000161514131a1918172524231b0000272600380b0000000908000000003424140474645444251505846555453516068575564636260086766608030201100b0a0918131211201b1a1928232221302b2a2938333231403b3a3948434241504b4a4958535251605b5a5968636261706b6a6978737271807b7a7988838281008b8a890000087400010001000200280003040000040800000514600006080f0f5560000d40030b003900002000000000000000 + + + SHORT_QSYS_INTERFACE_NAMES + true + + + SIDEBAND_C2P_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + SIDEBAND_HIPI_DELAY + 350 + + + SIDEBAND_P2C_UFI_MODE + pin_ufi_use_in_direct_out_direct + + + SILICON_REV + 14nm5 + + + SWAP_DQS_A_B + false + + + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_DEVICE_DIE_REVISIONS + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + + + SYS_INFO_DEVICE_FAMILY + Agilex 7 + + + SYS_INFO_DEVICE_POWER_MODEL + STANDARD_POWER + + + SYS_INFO_DEVICE_SPEEDGRADE + 2 + + + SYS_INFO_DEVICE_TEMPERATURE_GRADE + EXTENDED + + + SYS_INFO_UNIQUE_ID + ed_synth_emif_fm_0_emif_fm_0 + + + TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + TRAIT_SUPPORTS_VID + 1 + + + UNUSED_DQS_BUSES_LANELOC_0 + 14695431 + + + UNUSED_DQS_BUSES_LANELOC_1 + 6298637 + + + UNUSED_DQS_BUSES_LANELOC_10 + 0 + + + UNUSED_DQS_BUSES_LANELOC_2 + 4101 + + + UNUSED_DQS_BUSES_LANELOC_3 + 0 + + + UNUSED_DQS_BUSES_LANELOC_4 + 0 + + + UNUSED_DQS_BUSES_LANELOC_5 + 0 + + + UNUSED_DQS_BUSES_LANELOC_6 + 0 + + + UNUSED_DQS_BUSES_LANELOC_7 + 0 + + + UNUSED_DQS_BUSES_LANELOC_8 + 0 + + + UNUSED_DQS_BUSES_LANELOC_9 + 0 + + + UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT + 11 + + + UNUSED_MEM_PINS_PINLOC_0 + 199425087 + + + UNUSED_MEM_PINS_PINLOC_1 + 196276413 + + + UNUSED_MEM_PINS_PINLOC_10 + 167937186 + + + UNUSED_MEM_PINS_PINLOC_100 + 0 + + + UNUSED_MEM_PINS_PINLOC_101 + 0 + + + UNUSED_MEM_PINS_PINLOC_102 + 0 + + + UNUSED_MEM_PINS_PINLOC_103 + 0 + + + UNUSED_MEM_PINS_PINLOC_104 + 0 + + + UNUSED_MEM_PINS_PINLOC_105 + 0 + + + UNUSED_MEM_PINS_PINLOC_106 + 0 + + + UNUSED_MEM_PINS_PINLOC_107 + 0 + + + UNUSED_MEM_PINS_PINLOC_108 + 0 + + + UNUSED_MEM_PINS_PINLOC_109 + 0 + + + UNUSED_MEM_PINS_PINLOC_11 + 164788383 + + + UNUSED_MEM_PINS_PINLOC_110 + 0 + + + UNUSED_MEM_PINS_PINLOC_111 + 0 + + + UNUSED_MEM_PINS_PINLOC_112 + 0 + + + UNUSED_MEM_PINS_PINLOC_113 + 0 + + + UNUSED_MEM_PINS_PINLOC_114 + 0 + + + UNUSED_MEM_PINS_PINLOC_115 + 0 + + + UNUSED_MEM_PINS_PINLOC_116 + 0 + + + UNUSED_MEM_PINS_PINLOC_117 + 0 + + + UNUSED_MEM_PINS_PINLOC_118 + 0 + + + UNUSED_MEM_PINS_PINLOC_119 + 0 + + + UNUSED_MEM_PINS_PINLOC_12 + 145906844 + + + UNUSED_MEM_PINS_PINLOC_120 + 0 + + + UNUSED_MEM_PINS_PINLOC_121 + 0 + + + UNUSED_MEM_PINS_PINLOC_122 + 0 + + + UNUSED_MEM_PINS_PINLOC_123 + 0 + + + UNUSED_MEM_PINS_PINLOC_124 + 0 + + + UNUSED_MEM_PINS_PINLOC_125 + 0 + + + UNUSED_MEM_PINS_PINLOC_126 + 0 + + + UNUSED_MEM_PINS_PINLOC_127 + 0 + + + UNUSED_MEM_PINS_PINLOC_128 + 0 + + + UNUSED_MEM_PINS_PINLOC_13 + 108121215 + + + UNUSED_MEM_PINS_PINLOC_14 + 97613919 + + + UNUSED_MEM_PINS_PINLOC_15 + 93415515 + + + UNUSED_MEM_PINS_PINLOC_16 + 90266712 + + + UNUSED_MEM_PINS_PINLOC_17 + 83972181 + + + UNUSED_MEM_PINS_PINLOC_18 + 75572298 + + + UNUSED_MEM_PINS_PINLOC_19 + 55630906 + + + UNUSED_MEM_PINS_PINLOC_2 + 193127610 + + + UNUSED_MEM_PINS_PINLOC_20 + 19954731 + + + UNUSED_MEM_PINS_PINLOC_21 + 7 + + + UNUSED_MEM_PINS_PINLOC_22 + 0 + + + UNUSED_MEM_PINS_PINLOC_23 + 0 + + + UNUSED_MEM_PINS_PINLOC_24 + 0 + + + UNUSED_MEM_PINS_PINLOC_25 + 0 + + + UNUSED_MEM_PINS_PINLOC_26 + 0 + + + UNUSED_MEM_PINS_PINLOC_27 + 0 + + + UNUSED_MEM_PINS_PINLOC_28 + 0 + + + UNUSED_MEM_PINS_PINLOC_29 + 0 + + + UNUSED_MEM_PINS_PINLOC_3 + 189978807 + + + UNUSED_MEM_PINS_PINLOC_30 + 0 + + + UNUSED_MEM_PINS_PINLOC_31 + 0 + + + UNUSED_MEM_PINS_PINLOC_32 + 0 + + + UNUSED_MEM_PINS_PINLOC_33 + 0 + + + UNUSED_MEM_PINS_PINLOC_34 + 0 + + + UNUSED_MEM_PINS_PINLOC_35 + 0 + + + UNUSED_MEM_PINS_PINLOC_36 + 0 + + + UNUSED_MEM_PINS_PINLOC_37 + 0 + + + UNUSED_MEM_PINS_PINLOC_38 + 0 + + + UNUSED_MEM_PINS_PINLOC_39 + 0 + + + UNUSED_MEM_PINS_PINLOC_4 + 186830004 + + + UNUSED_MEM_PINS_PINLOC_40 + 0 + + + UNUSED_MEM_PINS_PINLOC_41 + 0 + + + UNUSED_MEM_PINS_PINLOC_42 + 0 + + + UNUSED_MEM_PINS_PINLOC_43 + 0 + + + UNUSED_MEM_PINS_PINLOC_44 + 0 + + + UNUSED_MEM_PINS_PINLOC_45 + 0 + + + UNUSED_MEM_PINS_PINLOC_46 + 0 + + + UNUSED_MEM_PINS_PINLOC_47 + 0 + + + UNUSED_MEM_PINS_PINLOC_48 + 0 + + + UNUSED_MEM_PINS_PINLOC_49 + 0 + + + UNUSED_MEM_PINS_PINLOC_5 + 183681201 + + + UNUSED_MEM_PINS_PINLOC_50 + 0 + + + UNUSED_MEM_PINS_PINLOC_51 + 0 + + + UNUSED_MEM_PINS_PINLOC_52 + 0 + + + UNUSED_MEM_PINS_PINLOC_53 + 0 + + + UNUSED_MEM_PINS_PINLOC_54 + 0 + + + UNUSED_MEM_PINS_PINLOC_55 + 0 + + + UNUSED_MEM_PINS_PINLOC_56 + 0 + + + UNUSED_MEM_PINS_PINLOC_57 + 0 + + + UNUSED_MEM_PINS_PINLOC_58 + 0 + + + UNUSED_MEM_PINS_PINLOC_59 + 0 + + + UNUSED_MEM_PINS_PINLOC_6 + 180532398 + + + UNUSED_MEM_PINS_PINLOC_60 + 0 + + + UNUSED_MEM_PINS_PINLOC_61 + 0 + + + UNUSED_MEM_PINS_PINLOC_62 + 0 + + + UNUSED_MEM_PINS_PINLOC_63 + 0 + + + UNUSED_MEM_PINS_PINLOC_64 + 0 + + + UNUSED_MEM_PINS_PINLOC_65 + 0 + + + UNUSED_MEM_PINS_PINLOC_66 + 0 + + + UNUSED_MEM_PINS_PINLOC_67 + 0 + + + UNUSED_MEM_PINS_PINLOC_68 + 0 + + + UNUSED_MEM_PINS_PINLOC_69 + 0 + + + UNUSED_MEM_PINS_PINLOC_7 + 177383595 + + + UNUSED_MEM_PINS_PINLOC_70 + 0 + + + UNUSED_MEM_PINS_PINLOC_71 + 0 + + + UNUSED_MEM_PINS_PINLOC_72 + 0 + + + UNUSED_MEM_PINS_PINLOC_73 + 0 + + + UNUSED_MEM_PINS_PINLOC_74 + 0 + + + UNUSED_MEM_PINS_PINLOC_75 + 0 + + + UNUSED_MEM_PINS_PINLOC_76 + 0 + + + UNUSED_MEM_PINS_PINLOC_77 + 0 + + + UNUSED_MEM_PINS_PINLOC_78 + 0 + + + UNUSED_MEM_PINS_PINLOC_79 + 0 + + + UNUSED_MEM_PINS_PINLOC_8 + 174234792 + + + UNUSED_MEM_PINS_PINLOC_80 + 0 + + + UNUSED_MEM_PINS_PINLOC_81 + 0 + + + UNUSED_MEM_PINS_PINLOC_82 + 0 + + + UNUSED_MEM_PINS_PINLOC_83 + 0 + + + UNUSED_MEM_PINS_PINLOC_84 + 0 + + + UNUSED_MEM_PINS_PINLOC_85 + 0 + + + UNUSED_MEM_PINS_PINLOC_86 + 0 + + + UNUSED_MEM_PINS_PINLOC_87 + 0 + + + UNUSED_MEM_PINS_PINLOC_88 + 0 + + + UNUSED_MEM_PINS_PINLOC_89 + 0 + + + UNUSED_MEM_PINS_PINLOC_9 + 171085989 + + + UNUSED_MEM_PINS_PINLOC_90 + 0 + + + UNUSED_MEM_PINS_PINLOC_91 + 0 + + + UNUSED_MEM_PINS_PINLOC_92 + 0 + + + UNUSED_MEM_PINS_PINLOC_93 + 0 + + + UNUSED_MEM_PINS_PINLOC_94 + 0 + + + UNUSED_MEM_PINS_PINLOC_95 + 0 + + + UNUSED_MEM_PINS_PINLOC_96 + 0 + + + UNUSED_MEM_PINS_PINLOC_97 + 0 + + + UNUSED_MEM_PINS_PINLOC_98 + 0 + + + UNUSED_MEM_PINS_PINLOC_99 + 0 + + + UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT + 129 + + + USER_CLK_RATIO + 4 + + + + altera_emif_arch_fm + 19.1 + arch + ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy + 0 + + + + + qsys_mm.piplineType + PIPELINE_STAGE + + + qsys_mm.insertDefaultSlave + FALSE + + + qsys_mm.enableOutOfOrderSupport + FALSE + + + qsys_mm.enableInstrumentation + FALSE + + + qsys_mm.widthAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.interconnectResetSource + DEFAULT + + + qsys_mm.burstAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.optimizeRdFifoSize + FALSE + + + qsys_mm.responseFifoType + REGISTER_BASED + + + qsys_mm.clockCrossingAdapter + HANDSHAKE + + + qsys_mm.maxAdditionalLatency + 1 + + + qsys_mm.syncResets + FALSE + + + qsys_mm.enableAllPipelines + FALSE + + + qsys_mm.enableEccProtection + FALSE + + + qsys_mm.interconnectType + STANDARD + + + + avalon_streaming + 24.1 + arch.ctrl_ast_rd_0/ecc_core.ctrl_ast_rd_0 + ecc_core/ctrl_ast_rd_0 + arch/ctrl_ast_rd_0 + + + + + resetDomainSysInfo + -1 + + + clockDomainSysInfo + -1 + + + clockResetSysInfo + + + + clockRateSysInfo + -1 + + + + clock + 24.1 + arch.emif_usr_clk/ecc_core.emif_usr_clk_in + ecc_core/emif_usr_clk_in + arch/emif_usr_clk + + + + + resetDomainSysInfo + -1 + + + clockDomainSysInfo + -1 + + + clockResetSysInfo + + + + + reset + 24.1 + arch.emif_usr_reset_n/ecc_core.emif_usr_reset_n_in + ecc_core/emif_usr_reset_n_in + arch/emif_usr_reset_n + + + + + qsys_mm.piplineType + PIPELINE_STAGE + + + qsys_mm.insertDefaultSlave + FALSE + + + qsys_mm.enableOutOfOrderSupport + FALSE + + + qsys_mm.enableInstrumentation + FALSE + + + qsys_mm.widthAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.interconnectResetSource + DEFAULT + + + qsys_mm.burstAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.optimizeRdFifoSize + FALSE + + + qsys_mm.responseFifoType + REGISTER_BASED + + + qsys_mm.clockCrossingAdapter + HANDSHAKE + + + qsys_mm.maxAdditionalLatency + 1 + + + qsys_mm.syncResets + FALSE + + + qsys_mm.enableAllPipelines + FALSE + + + qsys_mm.enableEccProtection + FALSE + + + qsys_mm.interconnectType + STANDARD + + + + avalon_streaming + 24.1 + ecc_core.ctrl_ast_cmd_0/arch.ctrl_ast_cmd_0 + arch/ctrl_ast_cmd_0 + ecc_core/ctrl_ast_cmd_0 + + + + + qsys_mm.piplineType + PIPELINE_STAGE + + + qsys_mm.insertDefaultSlave + FALSE + + + qsys_mm.enableOutOfOrderSupport + FALSE + + + qsys_mm.enableInstrumentation + FALSE + + + qsys_mm.widthAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.interconnectResetSource + DEFAULT + + + qsys_mm.burstAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.optimizeRdFifoSize + FALSE + + + qsys_mm.responseFifoType + REGISTER_BASED + + + qsys_mm.clockCrossingAdapter + HANDSHAKE + + + qsys_mm.maxAdditionalLatency + 1 + + + qsys_mm.syncResets + FALSE + + + qsys_mm.enableAllPipelines + FALSE + + + qsys_mm.enableEccProtection + FALSE + + + qsys_mm.interconnectType + STANDARD + + + + avalon_streaming + 24.1 + ecc_core.ctrl_ast_wr_0/arch.ctrl_ast_wr_0 + arch/ctrl_ast_wr_0 + ecc_core/ctrl_ast_wr_0 + + + + + startPortLSB + 0 + + + endPort + + + + endPortLSB + 0 + + + startPort + + + + width + 0 + + + + conduit + 24.1 + ecc_core.ctrl_ecc_0/arch.ctrl_ecc_0 + arch/ctrl_ecc_0 + ecc_core/ctrl_ecc_0 + + + ed_synth_emif_fm_0.emif_fm_0.arch + + + + + ecc_core + + + + BOARD_DDR3_AC_ISI_NS + 0.0 + + + BOARD_DDR3_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_DDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDR3_TDH_DERATING_PS + 0 + + + BOARD_DDR3_TDS_DERATING_PS + 0 + + + BOARD_DDR3_TIH_DERATING_PS + 0 + + + BOARD_DDR3_TIS_DERATING_PS + 0 + + + BOARD_DDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR3_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_ISI_NS + 0.15 + + + BOARD_DDR4_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_RCLK_ISI_NS + 0.15 + + + BOARD_DDR4_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_RDATA_ISI_NS + 0.12 + + + BOARD_DDR4_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR4_SKEW_WITHIN_AC_NS + 0.18 + + + BOARD_DDR4_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_TIH_DERATING_PS + 0 + + + BOARD_DDR4_TIS_DERATING_PS + 0 + + + BOARD_DDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR4_WCLK_ISI_NS + 0.06 + + + BOARD_DDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_WDATA_ISI_NS + 0.13 + + + BOARD_DDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_ISI_NS + 0.0 + + + BOARD_DDRT_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDRT_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDRT_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDRT_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDRT_TIH_DERATING_PS + 0 + + + BOARD_DDRT_TIS_DERATING_PS + 0 + + + BOARD_DDRT_USER_AC_ISI_NS + 0.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDRT_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_LPDDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_LPDDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_LPDDR3_TDH_DERATING_PS + 0 + + + BOARD_LPDDR3_TDS_DERATING_PS + 0 + + + BOARD_LPDDR3_TIH_DERATING_PS + 0 + + + BOARD_LPDDR3_TIS_DERATING_PS + 0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_LPDDR3_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_ISI_NS + 0.0 + + + BOARD_QDR2_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + 0.0 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + false + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + false + + + BOARD_QDR2_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + 0.6 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_D_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_Q_NS + 0.0 + + + BOARD_QDR2_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR2_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_ISI_NS + 0.0 + + + BOARD_QDR4_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + true + + + BOARD_QDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + 0.6 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_QDR4_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR4_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_QDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR4_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_ISI_NS + 0.0 + + + BOARD_RLD3_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + false + + + BOARD_RLD3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + 0.6 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_RLD3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_RLD3_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_RLD3_TDH_DERATING_PS + 0 + + + BOARD_RLD3_TDS_DERATING_PS + 0 + + + BOARD_RLD3_TIH_DERATING_PS + 0 + + + BOARD_RLD3_TIS_DERATING_PS + 0 + + + BOARD_RLD3_USER_AC_ISI_NS + 0.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_RLD3_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_WDATA_SLEW_RATE + 2.0 + + + CAL_DEBUG_CLOCK_FREQUENCY + 50000000 + + + CTRL_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR3_ECC_EN + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + true + + + CTRL_DDR3_ECC_STATUS_EN + false + + + CTRL_DDR3_MMR_EN + false + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_REORDER_EN + true + + + CTRL_DDR3_SELF_REFRESH_EN + false + + + CTRL_DDR3_STARVE_LIMIT + 10 + + + CTRL_DDR3_USER_PRIORITY_EN + false + + + CTRL_DDR3_USER_REFRESH_EN + false + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_ADDR_ORDER_ENUM + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + false + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR4_ECC_EN + true + + + CTRL_DDR4_ECC_READDATAERROR_EN + false + + + CTRL_DDR4_ECC_STATUS_EN + false + + + CTRL_DDR4_MAJOR_MODE_EN + false + + + CTRL_DDR4_MMR_EN + false + + + CTRL_DDR4_POST_REFRESH_EN + true + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + 1 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_REORDER_EN + true + + + CTRL_DDR4_SELF_REFRESH_EN + false + + + CTRL_DDR4_STARVE_LIMIT + 10 + + + CTRL_DDR4_USER_PRIORITY_EN + false + + + CTRL_DDR4_USER_REFRESH_EN + false + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ADDR_INTERLEAVING + COARSE + + + CTRL_DDRT_ADDR_ORDER_ENUM + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + false + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_AXIS_DATA_WIDTH + 512 + + + CTRL_DDRT_DIMM_DENSITY + 128 + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + false + + + CTRL_DDRT_DRIVER_MARGINING_EN + 0 + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDRT_ECC_EN + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + true + + + CTRL_DDRT_ECC_STATUS_EN + true + + + CTRL_DDRT_ERR_INJECT_EN + false + + + CTRL_DDRT_ERR_REPLAY_EN + false + + + CTRL_DDRT_EXT_ERR_INJECT_EN + false + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + false + + + CTRL_DDRT_MMR_EN + false + + + CTRL_DDRT_NUM_OF_AXIS_ID + 1 + + + CTRL_DDRT_PARITY_CMD_EN + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + false + + + CTRL_DDRT_POISON_DETECTION_EN + false + + + CTRL_DDRT_PORT_AFI_C_WIDTH + 2 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_REORDER_EN + true + + + CTRL_DDRT_SELF_REFRESH_EN + false + + + CTRL_DDRT_STARVE_LIMIT + 10 + + + CTRL_DDRT_UPI_EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + 8 + + + CTRL_DDRT_USER_PRIORITY_EN + false + + + CTRL_DDRT_USER_REFRESH_EN + false + + + CTRL_DDRT_WR_ACK_POLICY + POSTED + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ZQ_INTERVAL_MS + 3 + + + CTRL_ECC_EN + true + + + CTRL_ECC_READDATAERROR_EN + false + + + CTRL_ECC_STATUS_EN + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + false + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_MMR_EN + false + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_REORDER_EN + true + + + CTRL_LPDDR3_SELF_REFRESH_EN + false + + + CTRL_LPDDR3_STARVE_LIMIT + 10 + + + CTRL_LPDDR3_USER_PRIORITY_EN + false + + + CTRL_LPDDR3_USER_REFRESH_EN + false + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_MMR_EN + false + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC + 11 + + + CTRL_REORDER_EN + true + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_USER_PRIORITY_EN + false + + + DIAG_AC_PARITY_ERR + false + + + DIAG_ADD_READY_PIPELINE + true + + + DIAG_BOARD_DELAY_CONFIG_STR + + + + DIAG_DB_RESET_AUTO_RELEASE + avl_release + + + DIAG_DDR3_ABSTRACT_PHY + false + + + DIAG_DDR3_AC_PARITY_ERR + false + + + DIAG_DDR3_CAL_ADDR0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + 8 + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + false + + + DIAG_DDR3_CAL_ENABLE_NON_DES + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR3_CA_DESKEW_EN + true + + + DIAG_DDR3_CA_LEVEL_EN + true + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR3_ENABLE_USER_MODE + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR3_INTERFACE_ID + 0 + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR3_SIM_VERBOSE + true + + + DIAG_DDR3_TG2_TEST_DURATION + SHORT + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR3_USE_TG_AVL_2 + false + + + DIAG_DDR3_USE_TG_HBM + false + + + DIAG_DDR4_ABSTRACT_PHY + false + + + DIAG_DDR4_AC_PARITY_ERR + false + + + DIAG_DDR4_CAL_ADDR0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR4_ENABLE_USER_MODE + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR4_INTERFACE_ID + 0 + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR4_SIM_VERBOSE + true + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + false + + + DIAG_DDR4_SKIP_CA_DESKEW + false + + + DIAG_DDR4_SKIP_CA_LEVEL + false + + + DIAG_DDR4_SKIP_VREF_CAL + false + + + DIAG_DDR4_TG2_TEST_DURATION + SHORT + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR4_USE_TG_AVL_2 + false + + + DIAG_DDR4_USE_TG_HBM + false + + + DIAG_DDRT_ABSTRACT_PHY + false + + + DIAG_DDRT_AC_PARITY_ERR + false + + + DIAG_DDRT_CAL_ADDR0 + 0 + + + DIAG_DDRT_CAL_ADDR1 + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDRT_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDRT_EFF_TEST + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + false + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + false + + + DIAG_DDRT_ENABLE_USER_MODE + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDRT_INTERFACE_ID + 0 + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDRT_SIM_VERBOSE + true + + + DIAG_DDRT_SKIP_CA_DESKEW + false + + + DIAG_DDRT_SKIP_CA_LEVEL + false + + + DIAG_DDRT_SKIP_VREF_CAL + false + + + DIAG_DDRT_TG2_TEST_DURATION + SHORT + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + false + + + DIAG_DDRT_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDRT_USE_TG_AVL_2 + true + + + DIAG_DDRT_USE_TG_HBM + false + + + DIAG_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_ECLIPSE_DEBUG + false + + + DIAG_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_ENABLE_DEFAULT_MODE + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + false + + + DIAG_ENABLE_JTAG_UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + false + + + DIAG_ENABLE_SOFT_M20K + false + + + DIAG_ENABLE_USER_MODE + true + + + DIAG_EXPORT_PLL_LOCKED + true + + + DIAG_EXPORT_PLL_REF_CLK_OUT + false + + + DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_EXPORT_VJI + false + + + DIAG_EXPOSE_DFT_SIGNALS + false + + + DIAG_EXPOSE_EARLY_READY + false + + + DIAG_EXPOSE_RD_TYPE + false + + + DIAG_EXTRA_CONFIGS + + + + DIAG_EXT_DOCS + false + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + + + + DIAG_EX_DESIGN_ISSP_EN + true + + + DIAG_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_EX_DESIGN_SEPARATE_RESETS + false + + + DIAG_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_FAST_SIM + true + + + DIAG_FAST_SIM_OVERRIDE + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_HMC_HRC + auto + + + DIAG_INTERFACE_ID + 0 + + + DIAG_LPDDR3_ABSTRACT_PHY + false + + + DIAG_LPDDR3_AC_PARITY_ERR + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_LPDDR3_INTERFACE_ID + 0 + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_LPDDR3_SIM_VERBOSE + true + + + DIAG_LPDDR3_SKIP_CA_DESKEW + false + + + DIAG_LPDDR3_SKIP_CA_LEVEL + false + + + DIAG_LPDDR3_TG2_TEST_DURATION + SHORT + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_LPDDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_LPDDR3_USE_TG_AVL_2 + false + + + DIAG_LPDDR3_USE_TG_HBM + false + + + DIAG_QDR2_ABSTRACT_PHY + false + + + DIAG_QDR2_AC_PARITY_ERR + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR2_ENABLE_USER_MODE + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR2_INTERFACE_ID + 0 + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR2_SIM_VERBOSE + true + + + DIAG_QDR2_TG2_TEST_DURATION + SHORT + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR2_USE_TG_AVL_2 + false + + + DIAG_QDR2_USE_TG_HBM + false + + + DIAG_QDR4_ABSTRACT_PHY + false + + + DIAG_QDR4_AC_PARITY_ERR + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR4_ENABLE_USER_MODE + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR4_INTERFACE_ID + 0 + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR4_SIM_VERBOSE + true + + + DIAG_QDR4_SKIP_VREF_CAL + false + + + DIAG_QDR4_TG2_TEST_DURATION + SHORT + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR4_USE_TG_AVL_2 + false + + + DIAG_QDR4_USE_TG_HBM + false + + + DIAG_RLD2_ABSTRACT_PHY + false + + + DIAG_RLD2_AC_PARITY_ERR + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD2_ENABLE_USER_MODE + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD2_INTERFACE_ID + 0 + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD2_SIM_VERBOSE + true + + + DIAG_RLD2_TG2_TEST_DURATION + SHORT + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD2_USE_TG_AVL_2 + false + + + DIAG_RLD2_USE_TG_HBM + false + + + DIAG_RLD3_ABSTRACT_PHY + false + + + DIAG_RLD3_AC_PARITY_ERR + false + + + DIAG_RLD3_CA_DESKEW_EN + true + + + DIAG_RLD3_CA_LEVEL_EN + true + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD3_ENABLE_USER_MODE + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD3_INTERFACE_ID + 0 + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD3_SIM_VERBOSE + true + + + DIAG_RLD3_TG2_TEST_DURATION + SHORT + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD3_USE_TG_AVL_2 + false + + + DIAG_RLD3_USE_TG_HBM + false + + + DIAG_RS232_UART_BAUDRATE + 57600 + + + DIAG_SEQ_RESET_AUTO_RELEASE + avl + + + DIAG_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_SIM_CHECKER_SKIP_TG + false + + + DIAG_SIM_MEMORY_PRELOAD + false + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE + + + + DIAG_SIM_REGTEST_MODE + false + + + DIAG_SIM_VERBOSE_LEVEL + 5 + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + 100 + + + DIAG_SOFT_NIOS_MODE + SOFT_NIOS_MODE_DISABLED + + + DIAG_SYNTH_FOR_SIM + false + + + DIAG_TG2_TEST_DURATION + SHORT + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + 0 + + + DIAG_TIMING_REGTEST_MODE + false + + + DIAG_USE_ABSTRACT_PHY + false + + + DIAG_USE_BOARD_DELAY_MODEL + false + + + DIAG_USE_NEW_EFFMON_S10 + false + + + DIAG_USE_RS232_UART + false + + + DIAG_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_USE_TG_AVL_2 + false + + + DIAG_USE_TG_HBM + false + + + DIAG_VERBOSE_IOAUX + false + + + EMIF_0_CONN_TO_CALIP + CALIP_0 + + + EMIF_0_REF_CLK_SHARING + EXPORTED + + + EMIF_0_STORED_PARAM + + + + EMIF_10_CONN_TO_CALIP + CALIP_0 + + + EMIF_10_REF_CLK_SHARING + EXPORTED + + + EMIF_10_STORED_PARAM + + + + EMIF_11_CONN_TO_CALIP + CALIP_0 + + + EMIF_11_REF_CLK_SHARING + EXPORTED + + + EMIF_11_STORED_PARAM + + + + EMIF_12_CONN_TO_CALIP + CALIP_0 + + + EMIF_12_REF_CLK_SHARING + EXPORTED + + + EMIF_12_STORED_PARAM + + + + EMIF_13_CONN_TO_CALIP + CALIP_0 + + + EMIF_13_REF_CLK_SHARING + EXPORTED + + + EMIF_13_STORED_PARAM + + + + EMIF_14_CONN_TO_CALIP + CALIP_0 + + + EMIF_14_REF_CLK_SHARING + EXPORTED + + + EMIF_14_STORED_PARAM + + + + EMIF_15_CONN_TO_CALIP + CALIP_0 + + + EMIF_15_REF_CLK_SHARING + EXPORTED + + + EMIF_15_STORED_PARAM + + + + EMIF_1_CONN_TO_CALIP + CALIP_0 + + + EMIF_1_REF_CLK_SHARING + EXPORTED + + + EMIF_1_STORED_PARAM + + + + EMIF_2_CONN_TO_CALIP + CALIP_0 + + + EMIF_2_REF_CLK_SHARING + EXPORTED + + + EMIF_2_STORED_PARAM + + + + EMIF_3_CONN_TO_CALIP + CALIP_0 + + + EMIF_3_REF_CLK_SHARING + EXPORTED + + + EMIF_3_STORED_PARAM + + + + EMIF_4_CONN_TO_CALIP + CALIP_0 + + + EMIF_4_REF_CLK_SHARING + EXPORTED + + + EMIF_4_STORED_PARAM + + + + EMIF_5_CONN_TO_CALIP + CALIP_0 + + + EMIF_5_REF_CLK_SHARING + EXPORTED + + + EMIF_5_STORED_PARAM + + + + EMIF_6_CONN_TO_CALIP + CALIP_0 + + + EMIF_6_REF_CLK_SHARING + EXPORTED + + + EMIF_6_STORED_PARAM + + + + EMIF_7_CONN_TO_CALIP + CALIP_0 + + + EMIF_7_REF_CLK_SHARING + EXPORTED + + + EMIF_7_STORED_PARAM + + + + EMIF_8_CONN_TO_CALIP + CALIP_0 + + + EMIF_8_REF_CLK_SHARING + EXPORTED + + + EMIF_8_STORED_PARAM + + + + EMIF_9_CONN_TO_CALIP + CALIP_0 + + + EMIF_9_REF_CLK_SHARING + EXPORTED + + + EMIF_9_STORED_PARAM + + + + EX_DESIGN_GUI_DDR3_GEN_BSI + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + false + + + EX_DESIGN_GUI_DDR3_GEN_SIM + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_GEN_BSI + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + false + + + EX_DESIGN_GUI_DDR4_GEN_SIM + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_GEN_BSI + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + false + + + EX_DESIGN_GUI_DDRT_GEN_SIM + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_GEN_BSI + false + + + EX_DESIGN_GUI_GEN_CDC + false + + + EX_DESIGN_GUI_GEN_SIM + true + + + EX_DESIGN_GUI_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + false + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_GEN_BSI + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + false + + + EX_DESIGN_GUI_QDR2_GEN_SIM + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_GEN_BSI + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + false + + + EX_DESIGN_GUI_QDR4_GEN_SIM + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_GEN_BSI + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + false + + + EX_DESIGN_GUI_RLD2_GEN_SIM + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_GEN_BSI + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + false + + + EX_DESIGN_GUI_RLD3_GEN_SIM + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + FAMILY_ENUM + FAMILY_AGILEX + + + INTERNAL_TESTING_MODE + false + + + IS_ED_SLAVE + false + + + MEM_BURST_LENGTH + 8 + + + MEM_DATA_MASK_EN + true + + + MEM_DDR3_AC_PAR_EN + false + + + MEM_DDR3_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR3_ADDR_WIDTH + 1 + + + MEM_DDR3_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ASR_ENUM + DDR3_ASR_MANUAL + + + MEM_DDR3_ATCL_ENUM + DDR3_ATCL_DISABLED + + + MEM_DDR3_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_BL_ENUM + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_CFG_GEN_DBE + false + + + MEM_DDR3_CFG_GEN_SBE + false + + + MEM_DDR3_CKE_PER_DIMM + 1 + + + MEM_DDR3_CKE_WIDTH + 1 + + + MEM_DDR3_CK_WIDTH + 1 + + + MEM_DDR3_COL_ADDR_WIDTH + 10 + + + MEM_DDR3_CS_PER_DIMM + 1 + + + MEM_DDR3_CS_WIDTH + 1 + + + MEM_DDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR3_DLL_EN + true + + + MEM_DDR3_DM_EN + true + + + MEM_DDR3_DM_WIDTH + 1 + + + MEM_DDR3_DQS_WIDTH + 8 + + + MEM_DDR3_DQ_PER_DQS + 8 + + + MEM_DDR3_DQ_WIDTH + 72 + + + MEM_DDR3_DRV_STR_ENUM + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_FORMAT_ENUM + MEM_FORMAT_UDIMM + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + 000000000000000000 + + + MEM_DDR3_MIRROR_ADDRESSING_EN + true + + + MEM_DDR3_MR0 + 0 + + + MEM_DDR3_MR1 + 0 + + + MEM_DDR3_MR2 + 0 + + + MEM_DDR3_MR3 + 0 + + + MEM_DDR3_NUM_OF_DIMMS + 1 + + + MEM_DDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_ODT_WIDTH + 1 + + + MEM_DDR3_PD_ENUM + DDR3_PD_OFF + + + MEM_DDR3_RANKS_PER_DIMM + 1 + + + MEM_DDR3_RDIMM_CONFIG + 0000000000000000 + + + MEM_DDR3_RM_WIDTH + 0 + + + MEM_DDR3_ROW_ADDR_WIDTH + 15 + + + MEM_DDR3_RTT_NOM_ENUM + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_R_DERIVED_ODT0 + , + + + MEM_DDR3_R_DERIVED_ODT1 + , + + + MEM_DDR3_R_DERIVED_ODT2 + , + + + MEM_DDR3_R_DERIVED_ODT3 + , + + + MEM_DDR3_R_DERIVED_ODTN + , + + + MEM_DDR3_R_ODT0_1X1 + off + + + MEM_DDR3_R_ODT0_2X2 + off,off + + + MEM_DDR3_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR3_R_ODT1_2X2 + off,off + + + MEM_DDR3_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR3_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR3_R_ODTN_1X1 + Rank 0 + + + MEM_DDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR3_SPEEDBIN_ENUM + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_SRT_ENUM + DDR3_SRT_NORMAL + + + MEM_DDR3_TCL + 14 + + + MEM_DDR3_TDH_DC_MV + 100 + + + MEM_DDR3_TDH_PS + 55 + + + MEM_DDR3_TDQSCKDL + 1200 + + + MEM_DDR3_TDQSCKDM + 900 + + + MEM_DDR3_TDQSCKDS + 450 + + + MEM_DDR3_TDQSCK_DERV_PS + 2 + + + MEM_DDR3_TDQSCK_PS + 180 + + + MEM_DDR3_TDQSQ_PS + 75 + + + MEM_DDR3_TDQSS_CYC + 0.27 + + + MEM_DDR3_TDSH_CYC + 0.18 + + + MEM_DDR3_TDSS_CYC + 0.18 + + + MEM_DDR3_TDS_AC_MV + 135 + + + MEM_DDR3_TDS_PS + 53 + + + MEM_DDR3_TFAW_CYC + 27 + + + MEM_DDR3_TFAW_NS + 25.0 + + + MEM_DDR3_TIH_DC_MV + 100 + + + MEM_DDR3_TIH_PS + 95 + + + MEM_DDR3_TINIT_CK + 499 + + + MEM_DDR3_TINIT_US + 500 + + + MEM_DDR3_TIS_AC_MV + 135 + + + MEM_DDR3_TIS_PS + 60 + + + MEM_DDR3_TMRD_CK_CYC + 4 + + + MEM_DDR3_TQH_CYC + 0.38 + + + MEM_DDR3_TQSH_CYC + 0.4 + + + MEM_DDR3_TRAS_CYC + 36 + + + MEM_DDR3_TRAS_NS + 33.0 + + + MEM_DDR3_TRCD_CYC + 14 + + + MEM_DDR3_TRCD_NS + 13.09 + + + MEM_DDR3_TREFI_CYC + 8320 + + + MEM_DDR3_TREFI_US + 7.8 + + + MEM_DDR3_TRFC_CYC + 171 + + + MEM_DDR3_TRFC_NS + 160.0 + + + MEM_DDR3_TRP_CYC + 14 + + + MEM_DDR3_TRP_NS + 13.09 + + + MEM_DDR3_TRRD_CYC + 6 + + + MEM_DDR3_TRTP_CYC + 8 + + + MEM_DDR3_TTL_ADDR_WIDTH + 1 + + + MEM_DDR3_TTL_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_TTL_CKE_WIDTH + 1 + + + MEM_DDR3_TTL_CK_WIDTH + 1 + + + MEM_DDR3_TTL_CS_WIDTH + 1 + + + MEM_DDR3_TTL_DM_WIDTH + 1 + + + MEM_DDR3_TTL_DQS_WIDTH + 8 + + + MEM_DDR3_TTL_DQ_WIDTH + 72 + + + MEM_DDR3_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_TTL_ODT_WIDTH + 1 + + + MEM_DDR3_TTL_RM_WIDTH + 0 + + + MEM_DDR3_TWLH_PS + 125.0 + + + MEM_DDR3_TWLS_PS + 125.0 + + + MEM_DDR3_TWR_CYC + 16 + + + MEM_DDR3_TWR_NS + 15.0 + + + MEM_DDR3_TWTR_CYC + 8 + + + MEM_DDR3_USE_DEFAULT_ODT + true + + + MEM_DDR3_WTCL + 10 + + + MEM_DDR3_W_DERIVED_ODT0 + , + + + MEM_DDR3_W_DERIVED_ODT1 + , + + + MEM_DDR3_W_DERIVED_ODT2 + , + + + MEM_DDR3_W_DERIVED_ODT3 + , + + + MEM_DDR3_W_DERIVED_ODTN + , + + + MEM_DDR3_W_ODT0_1X1 + on + + + MEM_DDR3_W_ODT0_2X2 + on,off + + + MEM_DDR3_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT1_2X2 + off,on + + + MEM_DDR3_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR3_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR3_W_ODTN_1X1 + Rank 0 + + + MEM_DDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_AC_PARITY_LATENCY + DDR4_AC_PARITY_LATENCY_DISABLE + + + MEM_DDR4_AC_PERSISTENT_ERROR + false + + + MEM_DDR4_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR4_ADDR_WIDTH + 17 + + + MEM_DDR4_ALERT_N_AC_LANE + 3 + + + MEM_DDR4_ALERT_N_AC_PIN + 8 + + + MEM_DDR4_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + + + MEM_DDR4_ALERT_PAR_EN + true + + + MEM_DDR4_ASR_ENUM + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_ATCL_ENUM + DDR4_ATCL_DISABLED + + + MEM_DDR4_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_BL_ENUM + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_CAL_MODE + 0 + + + MEM_DDR4_CFG_GEN_DBE + false + + + MEM_DDR4_CFG_GEN_SBE + false + + + MEM_DDR4_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_CKE_PER_DIMM + 1 + + + MEM_DDR4_CKE_WIDTH + 1 + + + MEM_DDR4_CK_WIDTH + 1 + + + MEM_DDR4_COL_ADDR_WIDTH + 10 + + + MEM_DDR4_CS_PER_DIMM + 1 + + + MEM_DDR4_CS_WIDTH + 1 + + + MEM_DDR4_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR4_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DEFAULT_VREFOUT + true + + + MEM_DDR4_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR4_DLL_EN + true + + + MEM_DDR4_DM_EN + true + + + MEM_DDR4_DQS_WIDTH + 9 + + + MEM_DDR4_DQ_PER_DQS + 8 + + + MEM_DDR4_DQ_WIDTH + 72 + + + MEM_DDR4_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_DDR4_GEARDOWN + DDR4_GEARDOWN_HR + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR4_IDEAL_VREF_IN_PCT + 68.0 + + + MEM_DDR4_IDEAL_VREF_OUT_PCT + 70.0 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP + RTT_NOM disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP + RTT_PARK disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP + RZQ/3 (80 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM + DDR4_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP + ODT Disabled + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM + DDR4_RTT_PARK_RZQ_4 + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP + RZQ/4 (60 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP + Dynamic ODT off + + + MEM_DDR4_INTEL_DEFAULT_TERM + true + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDR4_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + + + + MEM_DDR4_MAX_POWERDOWN + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + true + + + MEM_DDR4_MPR_READ_FORMAT + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MR0 + 2164 + + + MEM_DDR4_MR1 + 65537 + + + MEM_DDR4_MR2 + 131112 + + + MEM_DDR4_MR3 + 197632 + + + MEM_DDR4_MR4 + 264192 + + + MEM_DDR4_MR5 + 332896 + + + MEM_DDR4_MR6 + 395279 + + + MEM_DDR4_NUM_OF_DIMMS + 1 + + + MEM_DDR4_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_ODT_IN_POWERDOWN + true + + + MEM_DDR4_ODT_WIDTH + 1 + + + MEM_DDR4_PER_DRAM_ADDR + false + + + MEM_DDR4_RANKS_PER_DIMM + 1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_COMMAND_LATENCY + 1 + + + MEM_DDR4_RCD_CS_IBT_ENUM + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_RCD_PARITY_CONTROL_WORD + 13 + + + MEM_DDR4_RDIMM_CONFIG + 00000020000000003900000D40030B0F556000 + + + MEM_DDR4_READ_DBI + true + + + MEM_DDR4_READ_PREAMBLE + 2 + + + MEM_DDR4_READ_PREAMBLE_TRAINING + false + + + MEM_DDR4_RM_WIDTH + 0 + + + MEM_DDR4_ROW_ADDR_WIDTH + 16 + + + MEM_DDR4_RTT_NOM_ENUM + DDR4_RTT_NOM_RZQ_4 + + + MEM_DDR4_RTT_PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_R_DERIVED_BODT0 + + + + MEM_DDR4_R_DERIVED_BODT1 + + + + MEM_DDR4_R_DERIVED_BODTN + + + + MEM_DDR4_R_DERIVED_ODT0 + (Drive) RZQ/7 (34 Ohm),-,-,- + + + MEM_DDR4_R_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_R_ODT0_1X1 + off + + + MEM_DDR4_R_ODT0_2X2 + off,off + + + MEM_DDR4_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR4_R_ODT1_2X2 + off,off + + + MEM_DDR4_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR4_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR4_R_ODTN_1X1 + Rank 0 + + + MEM_DDR4_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_SELF_RFSH_ABORT + false + + + MEM_DDR4_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR4_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDR4_SPD_135_RCD_REV + 0 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + 101 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDR4_SPD_139_DB_REV + 0 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + 0 + + + MEM_DDR4_SPEEDBIN_ENUM + DDR4_SPEEDBIN_2666 + + + MEM_DDR4_TCCD_L_CYC + 6 + + + MEM_DDR4_TCCD_S_CYC + 4 + + + MEM_DDR4_TCL + 21 + + + MEM_DDR4_TDIVW_DJ_CYC + 0.1 + + + MEM_DDR4_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDR4_TDQSCKDL + 1200 + + + MEM_DDR4_TDQSCKDM + 900 + + + MEM_DDR4_TDQSCKDS + 450 + + + MEM_DDR4_TDQSCK_DERV_PS + 2 + + + MEM_DDR4_TDQSCK_PS + 175 + + + MEM_DDR4_TDQSQ_PS + 66 + + + MEM_DDR4_TDQSQ_UI + 0.14 + + + MEM_DDR4_TDQSS_CYC + 0.27 + + + MEM_DDR4_TDSH_CYC + 0.18 + + + MEM_DDR4_TDSS_CYC + 0.18 + + + MEM_DDR4_TDVWP_UI + 0.72 + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_SENSOR_READOUT + false + + + MEM_DDR4_TFAW_CYC + 26 + + + MEM_DDR4_TFAW_DLR_CYC + 16 + + + MEM_DDR4_TFAW_NS + 21.0 + + + MEM_DDR4_TIH_DC_MV + 75 + + + MEM_DDR4_TIH_PS + 87 + + + MEM_DDR4_TINIT_CK + 600000 + + + MEM_DDR4_TINIT_US + 500 + + + MEM_DDR4_TIS_AC_MV + 100 + + + MEM_DDR4_TIS_PS + 62 + + + MEM_DDR4_TMRD_CK_CYC + 8 + + + MEM_DDR4_TQH_CYC + 0.38 + + + MEM_DDR4_TQH_UI + 0.74 + + + MEM_DDR4_TQSH_CYC + 0.4 + + + MEM_DDR4_TRAS_CYC + 39 + + + MEM_DDR4_TRAS_NS + 32.0 + + + MEM_DDR4_TRCD_CYC + 17 + + + MEM_DDR4_TRCD_NS + 14.16 + + + MEM_DDR4_TREFI_CYC + 9360 + + + MEM_DDR4_TREFI_US + 7.8 + + + MEM_DDR4_TRFC_CYC + 420 + + + MEM_DDR4_TRFC_DLR_CYC + 108 + + + MEM_DDR4_TRFC_DLR_NS + 90.0 + + + MEM_DDR4_TRFC_NS + 350.0 + + + MEM_DDR4_TRP_CYC + 17 + + + MEM_DDR4_TRP_NS + 14.16 + + + MEM_DDR4_TRRD_DLR_CYC + 4 + + + MEM_DDR4_TRRD_L_CYC + 6 + + + MEM_DDR4_TRRD_S_CYC + 4 + + + MEM_DDR4_TRTP_CYC + 9 + + + MEM_DDR4_TTL_ADDR_WIDTH + 17 + + + MEM_DDR4_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_TTL_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_TTL_CKE_WIDTH + 1 + + + MEM_DDR4_TTL_CK_WIDTH + 1 + + + MEM_DDR4_TTL_CS_WIDTH + 1 + + + MEM_DDR4_TTL_DQS_WIDTH + 9 + + + MEM_DDR4_TTL_DQ_WIDTH + 72 + + + MEM_DDR4_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_TTL_ODT_WIDTH + 1 + + + MEM_DDR4_TTL_RM_WIDTH + 0 + + + MEM_DDR4_TWLH_CYC + 0.13 + + + MEM_DDR4_TWLH_PS + 0.0 + + + MEM_DDR4_TWLS_CYC + 0.13 + + + MEM_DDR4_TWLS_PS + 0.0 + + + MEM_DDR4_TWR_CYC + 18 + + + MEM_DDR4_TWR_NS + 15.0 + + + MEM_DDR4_TWTR_L_CYC + 9 + + + MEM_DDR4_TWTR_S_CYC + 3 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDR4_USE_DEFAULT_ODT + true + + + MEM_DDR4_VDIVW_TOTAL + 130 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_0 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP + Range 1 - 60% to 92.5% + + + MEM_DDR4_VREFDQ_TRAINING_VALUE + 70.0 + + + MEM_DDR4_WRITE_CMD_LATENCY + 6 + + + MEM_DDR4_WRITE_CRC + false + + + MEM_DDR4_WRITE_DBI + false + + + MEM_DDR4_WRITE_PREAMBLE + 1 + + + MEM_DDR4_WTCL + 16 + + + MEM_DDR4_W_DERIVED_BODT0 + + + + MEM_DDR4_W_DERIVED_BODT1 + + + + MEM_DDR4_W_DERIVED_BODTN + + + + MEM_DDR4_W_DERIVED_ODT0 + (Park) RZQ/4 (60 Ohm),-,-,- + + + MEM_DDR4_W_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_W_ODT0_1X1 + on + + + MEM_DDR4_W_ODT0_2X2 + on,off + + + MEM_DDR4_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT1_2X2 + off,on + + + MEM_DDR4_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR4_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR4_W_ODTN_1X1 + Rank 0 + + + MEM_DDR4_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_AC_PARITY_LATENCY + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_AC_PERSISTENT_ERROR + false + + + MEM_DDRT_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDRT_ADDR_WIDTH + 1 + + + MEM_DDRT_ALERT_N_AC_LANE + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + 0 + + + MEM_DDRT_ALERT_N_DQS_GROUP + 0 + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_PAR_EN + true + + + MEM_DDRT_ASR_ENUM + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_ATCL_ENUM + DDRT_ATCL_DISABLED + + + MEM_DDRT_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_BL_ENUM + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_CAL_MODE + 0 + + + MEM_DDRT_CFG_GEN_DBE + false + + + MEM_DDRT_CFG_GEN_SBE + false + + + MEM_DDRT_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_CKE_PER_DIMM + 1 + + + MEM_DDRT_CKE_WIDTH + 1 + + + MEM_DDRT_CK_WIDTH + 1 + + + MEM_DDRT_COL_ADDR_WIDTH + 10 + + + MEM_DDRT_CS_PER_DIMM + 1 + + + MEM_DDRT_CS_WIDTH + 1 + + + MEM_DDRT_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDRT_DB_DQ_DRV_ENUM + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_PARK_ENUM + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + true + + + MEM_DDRT_DEFAULT_PREAMBLE + true + + + MEM_DDRT_DEFAULT_VREFOUT + true + + + MEM_DDRT_DISCRETE_CS_WIDTH + 1 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDRT_DLL_EN + true + + + MEM_DDRT_DM_EN + false + + + MEM_DDRT_DQS_WIDTH + 8 + + + MEM_DDRT_DQ_PER_DQS + 4 + + + MEM_DDRT_DQ_WIDTH + 72 + + + MEM_DDRT_DRV_STR_ENUM + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ERID_WIDTH + 2 + + + MEM_DDRT_ERR_N_WIDTH + 1 + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_FORMAT_ENUM + MEM_FORMAT_LRDIMM + + + MEM_DDRT_GEARDOWN + DDRT_GEARDOWN_HR + + + MEM_DDRT_GNT_N_WIDTH + 1 + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + true + + + MEM_DDRT_I2C_DIMM_0_SA + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + 3 + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDRT_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + + + + MEM_DDRT_MAX_POWERDOWN + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + true + + + MEM_DDRT_MPR_READ_FORMAT + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MR0 + 0 + + + MEM_DDRT_MR1 + 0 + + + MEM_DDRT_MR2 + 0 + + + MEM_DDRT_MR3 + 0 + + + MEM_DDRT_MR4 + 0 + + + MEM_DDRT_MR5 + 0 + + + MEM_DDRT_MR6 + 0 + + + MEM_DDRT_NUM_OF_DIMMS + 1 + + + MEM_DDRT_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_ODT_IN_POWERDOWN + true + + + MEM_DDRT_ODT_WIDTH + 1 + + + MEM_DDRT_PARTIAL_WRITES + false + + + MEM_DDRT_PERSISTENT_MODE + 1 + + + MEM_DDRT_PER_DRAM_ADDR + false + + + MEM_DDRT_PWR_MODE + DDRT_PWR_MODE_12W + + + MEM_DDRT_RANKS_PER_DIMM + 1 + + + MEM_DDRT_RCD_CA_IBT_ENUM + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_COMMAND_LATENCY + 1 + + + MEM_DDRT_RCD_CS_IBT_ENUM + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_RCD_PARITY_CONTROL_WORD + 1 + + + MEM_DDRT_RDIMM_CONFIG + + + + MEM_DDRT_READ_DBI + false + + + MEM_DDRT_READ_PREAMBLE + 1 + + + MEM_DDRT_READ_PREAMBLE_TRAINING + false + + + MEM_DDRT_REQ_N_WIDTH + 1 + + + MEM_DDRT_RM_WIDTH + 0 + + + MEM_DDRT_ROW_ADDR_WIDTH + 18 + + + MEM_DDRT_RTT_NOM_ENUM + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_RTT_PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_RTT_WR_ENUM + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_R_DERIVED_BODT0 + + + + MEM_DDRT_R_DERIVED_BODT1 + + + + MEM_DDRT_R_DERIVED_BODTN + + + + MEM_DDRT_R_DERIVED_ODT0 + , + + + MEM_DDRT_R_DERIVED_ODT1 + , + + + MEM_DDRT_R_DERIVED_ODT2 + , + + + MEM_DDRT_R_DERIVED_ODT3 + , + + + MEM_DDRT_R_DERIVED_ODTN + , + + + MEM_DDRT_R_ODT0_1X1 + off + + + MEM_DDRT_R_ODT0_2X2 + off,off + + + MEM_DDRT_R_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_R_ODT0_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT1_2X2 + off,off + + + MEM_DDRT_R_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_R_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_R_ODTN_1X1 + Rank 0 + + + MEM_DDRT_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_SELF_RFSH_ABORT + false + + + MEM_DDRT_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDRT_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDRT_SPD_135_RCD_REV + 0 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDRT_SPD_139_DB_REV + 0 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDRT_SPEEDBIN_ENUM + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TCCD_L_CYC + 6 + + + MEM_DDRT_TCCD_S_CYC + 4 + + + MEM_DDRT_TCL + 15 + + + MEM_DDRT_TCL_ADDED + -1 + + + MEM_DDRT_TDIVW_DJ_CYC + 0.1 + + + MEM_DDRT_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDRT_TDQSCKDL + 1200 + + + MEM_DDRT_TDQSCKDM + 900 + + + MEM_DDRT_TDQSCKDS + 450 + + + MEM_DDRT_TDQSCK_DERV_PS + 2 + + + MEM_DDRT_TDQSCK_PS + 165 + + + MEM_DDRT_TDQSQ_PS + 66 + + + MEM_DDRT_TDQSQ_UI + 0.16 + + + MEM_DDRT_TDQSS_CYC + 0.27 + + + MEM_DDRT_TDSH_CYC + 0.18 + + + MEM_DDRT_TDSS_CYC + 0.18 + + + MEM_DDRT_TDVWP_UI + 0.72 + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_SENSOR_READOUT + false + + + MEM_DDRT_TFAW_CYC + 27 + + + MEM_DDRT_TFAW_DLR_CYC + 16 + + + MEM_DDRT_TFAW_NS + 21.0 + + + MEM_DDRT_TIH_DC_MV + 75 + + + MEM_DDRT_TIH_PS + 95 + + + MEM_DDRT_TINIT_CK + 499 + + + MEM_DDRT_TINIT_US + 500 + + + MEM_DDRT_TIS_AC_MV + 100 + + + MEM_DDRT_TIS_PS + 60 + + + MEM_DDRT_TMRD_CK_CYC + 8 + + + MEM_DDRT_TQH_CYC + 0.38 + + + MEM_DDRT_TQH_UI + 0.76 + + + MEM_DDRT_TQSH_CYC + 0.38 + + + MEM_DDRT_TRAS_CYC + 36 + + + MEM_DDRT_TRAS_NS + 32.0 + + + MEM_DDRT_TRCD_CYC + 14 + + + MEM_DDRT_TRCD_NS + 15.0 + + + MEM_DDRT_TREFI_CYC + 8320 + + + MEM_DDRT_TREFI_US + 7.8 + + + MEM_DDRT_TRFC_CYC + 171 + + + MEM_DDRT_TRFC_DLR_CYC + 109 + + + MEM_DDRT_TRFC_DLR_NS + 90.0 + + + MEM_DDRT_TRFC_NS + 260.0 + + + MEM_DDRT_TRP_CYC + 14 + + + MEM_DDRT_TRP_NS + 15.0 + + + MEM_DDRT_TRRD_DLR_CYC + 4 + + + MEM_DDRT_TRRD_L_CYC + 6 + + + MEM_DDRT_TRRD_S_CYC + 4 + + + MEM_DDRT_TRTP_CYC + 9 + + + MEM_DDRT_TTL_ADDR_WIDTH + 1 + + + MEM_DDRT_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_TTL_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_TTL_CKE_WIDTH + 1 + + + MEM_DDRT_TTL_CK_WIDTH + 1 + + + MEM_DDRT_TTL_CS_WIDTH + 1 + + + MEM_DDRT_TTL_DQS_WIDTH + 8 + + + MEM_DDRT_TTL_DQ_WIDTH + 72 + + + MEM_DDRT_TTL_ERID_WIDTH + 2 + + + MEM_DDRT_TTL_ERR_N_WIDTH + 1 + + + MEM_DDRT_TTL_GNT_N_WIDTH + 1 + + + MEM_DDRT_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDRT_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_TTL_ODT_WIDTH + 1 + + + MEM_DDRT_TTL_REQ_N_WIDTH + 1 + + + MEM_DDRT_TTL_RM_WIDTH + 0 + + + MEM_DDRT_TWLH_CYC + 0.13 + + + MEM_DDRT_TWLH_PS + 0.0 + + + MEM_DDRT_TWLS_CYC + 0.13 + + + MEM_DDRT_TWLS_PS + 0.0 + + + MEM_DDRT_TWR_CYC + 18 + + + MEM_DDRT_TWR_NS + 15.0 + + + MEM_DDRT_TWTR_L_CYC + 9 + + + MEM_DDRT_TWTR_S_CYC + 3 + + + MEM_DDRT_USER_READ_PREAMBLE + 1 + + + MEM_DDRT_USER_TCL_ADDED + 0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_USER_WRITE_PREAMBLE + 1 + + + MEM_DDRT_USER_WTCL_ADDED + 6 + + + MEM_DDRT_USE_DEFAULT_ODT + true + + + MEM_DDRT_VDIVW_TOTAL + 136 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE_DISP + Range 2 - 45% to 77.5% + + + MEM_DDRT_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_WRITE_CMD_LATENCY + 5 + + + MEM_DDRT_WRITE_CRC + false + + + MEM_DDRT_WRITE_DBI + false + + + MEM_DDRT_WRITE_PREAMBLE + 1 + + + MEM_DDRT_WTCL + 18 + + + MEM_DDRT_WTCL_ADDED + -1 + + + MEM_DDRT_W_DERIVED_BODT0 + + + + MEM_DDRT_W_DERIVED_BODT1 + + + + MEM_DDRT_W_DERIVED_BODTN + + + + MEM_DDRT_W_DERIVED_ODT0 + , + + + MEM_DDRT_W_DERIVED_ODT1 + , + + + MEM_DDRT_W_DERIVED_ODT2 + , + + + MEM_DDRT_W_DERIVED_ODT3 + , + + + MEM_DDRT_W_DERIVED_ODTN + , + + + MEM_DDRT_W_ODT0_1X1 + on + + + MEM_DDRT_W_ODT0_2X2 + on,off + + + MEM_DDRT_W_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_W_ODT0_4X4 + on,on,off,off + + + MEM_DDRT_W_ODT1_2X2 + off,on + + + MEM_DDRT_W_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_W_ODTN_1X1 + Rank 0 + + + MEM_DDRT_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_HAS_BSI_SUPPORT + true + + + MEM_HAS_SIM_SUPPORT + true + + + MEM_LPDDR3_ADDR_WIDTH + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + 3 + + + MEM_LPDDR3_BL + LPDDR3_BL_BL8 + + + MEM_LPDDR3_CKE_WIDTH + 1 + + + MEM_LPDDR3_CK_WIDTH + 1 + + + MEM_LPDDR3_COL_ADDR_WIDTH + 10 + + + MEM_LPDDR3_CS_WIDTH + 1 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_LPDDR3_DATA_LATENCY + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_LPDDR3_DM_EN + true + + + MEM_LPDDR3_DM_WIDTH + 1 + + + MEM_LPDDR3_DQODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_DQS_WIDTH + 1 + + + MEM_LPDDR3_DQ_PER_DQS + 8 + + + MEM_LPDDR3_DQ_WIDTH + 32 + + + MEM_LPDDR3_DRV_STR + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_LPDDR3_MR1 + 0 + + + MEM_LPDDR3_MR11 + 0 + + + MEM_LPDDR3_MR2 + 0 + + + MEM_LPDDR3_MR3 + 0 + + + MEM_LPDDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_LPDDR3_NWR + LPDDR3_NWR_NWR12 + + + MEM_LPDDR3_ODT_WIDTH + 1 + + + MEM_LPDDR3_PDODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_ROW_ADDR_WIDTH + 15 + + + MEM_LPDDR3_R_DERIVED_ODT0 + , + + + MEM_LPDDR3_R_DERIVED_ODT1 + , + + + MEM_LPDDR3_R_DERIVED_ODT2 + , + + + MEM_LPDDR3_R_DERIVED_ODT3 + , + + + MEM_LPDDR3_R_DERIVED_ODTN + , + + + MEM_LPDDR3_R_ODT0_1X1 + off + + + MEM_LPDDR3_R_ODT0_2X2 + off,off + + + MEM_LPDDR3_R_ODT0_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_2X2 + off,off + + + MEM_LPDDR3_R_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_LPDDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_LPDDR3_SPEEDBIN_ENUM + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TDH_DC_MV + 100 + + + MEM_LPDDR3_TDH_PS + 100 + + + MEM_LPDDR3_TDQSCKDL + 614 + + + MEM_LPDDR3_TDQSCKDM + 511 + + + MEM_LPDDR3_TDQSCKDS + 220 + + + MEM_LPDDR3_TDQSCK_DERV_PS + 2 + + + MEM_LPDDR3_TDQSCK_PS + 5500 + + + MEM_LPDDR3_TDQSQ_PS + 135 + + + MEM_LPDDR3_TDQSS_CYC + 1.25 + + + MEM_LPDDR3_TDSH_CYC + 0.2 + + + MEM_LPDDR3_TDSS_CYC + 0.2 + + + MEM_LPDDR3_TDS_AC_MV + 150 + + + MEM_LPDDR3_TDS_PS + 75 + + + MEM_LPDDR3_TFAW_CYC + 40 + + + MEM_LPDDR3_TFAW_NS + 50.0 + + + MEM_LPDDR3_TIH_DC_MV + 100 + + + MEM_LPDDR3_TIH_PS + 100 + + + MEM_LPDDR3_TINIT_CK + 499 + + + MEM_LPDDR3_TINIT_US + 500 + + + MEM_LPDDR3_TIS_AC_MV + 150 + + + MEM_LPDDR3_TIS_PS + 75 + + + MEM_LPDDR3_TMRR_CK_CYC + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + 10 + + + MEM_LPDDR3_TQH_CYC + 0.38 + + + MEM_LPDDR3_TQSH_CYC + 0.38 + + + MEM_LPDDR3_TRAS_CYC + 34 + + + MEM_LPDDR3_TRAS_NS + 42.5 + + + MEM_LPDDR3_TRCD_CYC + 17 + + + MEM_LPDDR3_TRCD_NS + 18.0 + + + MEM_LPDDR3_TREFI_CYC + 3120 + + + MEM_LPDDR3_TREFI_US + 3.9 + + + MEM_LPDDR3_TRFC_CYC + 168 + + + MEM_LPDDR3_TRFC_NS + 210.0 + + + MEM_LPDDR3_TRL_CYC + 10 + + + MEM_LPDDR3_TRP_CYC + 17 + + + MEM_LPDDR3_TRP_NS + 18.0 + + + MEM_LPDDR3_TRRD_CYC + 8 + + + MEM_LPDDR3_TRTP_CYC + 6 + + + MEM_LPDDR3_TWLH_PS + 175.0 + + + MEM_LPDDR3_TWLS_PS + 175.0 + + + MEM_LPDDR3_TWL_CYC + 6 + + + MEM_LPDDR3_TWR_CYC + 12 + + + MEM_LPDDR3_TWR_NS + 15.0 + + + MEM_LPDDR3_TWTR_CYC + 6 + + + MEM_LPDDR3_USE_DEFAULT_ODT + true + + + MEM_LPDDR3_WLSELECT + Set A + + + MEM_LPDDR3_W_DERIVED_ODT0 + , + + + MEM_LPDDR3_W_DERIVED_ODT1 + , + + + MEM_LPDDR3_W_DERIVED_ODT2 + , + + + MEM_LPDDR3_W_DERIVED_ODT3 + , + + + MEM_LPDDR3_W_DERIVED_ODTN + , + + + MEM_LPDDR3_W_ODT0_1X1 + on + + + MEM_LPDDR3_W_ODT0_2X2 + on,on + + + MEM_LPDDR3_W_ODT0_4X4 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_2X2 + off,off + + + MEM_LPDDR3_W_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_NUM_OF_DATA_ENDPOINTS + 1 + + + MEM_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_QDR2_ADDR_WIDTH + 19 + + + MEM_QDR2_BL + 4 + + + MEM_QDR2_BWS_EN + true + + + MEM_QDR2_BWS_N_PER_DEVICE + 4 + + + MEM_QDR2_BWS_N_WIDTH + 4 + + + MEM_QDR2_CQ_WIDTH + 1 + + + MEM_QDR2_DATA_PER_DEVICE + 36 + + + MEM_QDR2_DATA_WIDTH + 36 + + + MEM_QDR2_DEVICE_WIDTH + 1 + + + MEM_QDR2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR2_INTERNAL_JITTER_NS + 0.08 + + + MEM_QDR2_K_WIDTH + 1 + + + MEM_QDR2_SPEEDBIN_ENUM + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TCCQO_NS + 0.45 + + + MEM_QDR2_TCQDOH_NS + -0.09 + + + MEM_QDR2_TCQD_NS + 0.09 + + + MEM_QDR2_TCQH_NS + 0.71 + + + MEM_QDR2_THA_NS + 0.18 + + + MEM_QDR2_THD_NS + 0.18 + + + MEM_QDR2_TRL_CYC + 2.5 + + + MEM_QDR2_TSA_NS + 0.23 + + + MEM_QDR2_TSD_NS + 0.23 + + + MEM_QDR2_TWL_CYC + 1 + + + MEM_QDR2_WIDTH_EXPANDED + false + + + MEM_QDR4_AC_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_ADDR_INV_ENA + false + + + MEM_QDR4_ADDR_WIDTH + 21 + + + MEM_QDR4_AVL_CHNLS + 8 + + + MEM_QDR4_BL + 2 + + + MEM_QDR4_CK_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_CR0 + 0 + + + MEM_QDR4_CR1 + 0 + + + MEM_QDR4_CR2 + 0 + + + MEM_QDR4_DATA_INV_ENA + true + + + MEM_QDR4_DATA_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_DEVICE_DEPTH + 1 + + + MEM_QDR4_DEVICE_WIDTH + 1 + + + MEM_QDR4_DINV_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DINV_WIDTH + 4 + + + MEM_QDR4_DK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DK_WIDTH + 4 + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + 36 + + + MEM_QDR4_DQ_PER_PORT_WIDTH + 36 + + + MEM_QDR4_DQ_PER_RD_GROUP + 18 + + + MEM_QDR4_DQ_PER_WR_GROUP + 18 + + + MEM_QDR4_DQ_WIDTH + 72 + + + MEM_QDR4_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR4_MEM_TYPE_ENUM + MEM_XP + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_QK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_QK_WIDTH + 4 + + + MEM_QDR4_SKIP_ODT_SWEEPING + true + + + MEM_QDR4_SPEEDBIN_ENUM + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TASH_PS + 170 + + + MEM_QDR4_TCKDK_MAX_PS + 150 + + + MEM_QDR4_TCKDK_MIN_PS + -150 + + + MEM_QDR4_TCKQK_MAX_PS + 225 + + + MEM_QDR4_TCSH_PS + 170 + + + MEM_QDR4_TISH_PS + 150 + + + MEM_QDR4_TQH_CYC + 0.4 + + + MEM_QDR4_TQKQ_MAX_PS + 75 + + + MEM_QDR4_TRL_CYC + 8 + + + MEM_QDR4_TWL_CYC + 5 + + + MEM_QDR4_USE_ADDR_PARITY + false + + + MEM_QDR4_WIDTH_EXPANDED + false + + + MEM_READ_LATENCY + 23.0 + + + MEM_RLD2_ADDR_WIDTH + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + 3 + + + MEM_RLD2_BL + 4 + + + MEM_RLD2_CONFIG_ENUM + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_CS_WIDTH + 1 + + + MEM_RLD2_DEVICE_DEPTH + 1 + + + MEM_RLD2_DEVICE_WIDTH + 1 + + + MEM_RLD2_DK_WIDTH + 1 + + + MEM_RLD2_DM_EN + true + + + MEM_RLD2_DM_WIDTH + 1 + + + MEM_RLD2_DQ_PER_DEVICE + 9 + + + MEM_RLD2_DQ_PER_RD_GROUP + 9 + + + MEM_RLD2_DQ_PER_WR_GROUP + 9 + + + MEM_RLD2_DQ_WIDTH + 9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD2_MR + 0 + + + MEM_RLD2_ODT_MODE_ENUM + RLD2_ODT_ON + + + MEM_RLD2_QK_WIDTH + 1 + + + MEM_RLD2_REFRESH_INTERVAL_US + 0.24 + + + MEM_RLD2_SPEEDBIN_ENUM + RLD2_SPEEDBIN_18 + + + MEM_RLD2_TAH_NS + 0.3 + + + MEM_RLD2_TAS_NS + 0.3 + + + MEM_RLD2_TCKDK_MAX_NS + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + -0.3 + + + MEM_RLD2_TCKH_CYC + 0.45 + + + MEM_RLD2_TCKQK_MAX_NS + 0.2 + + + MEM_RLD2_TDH_NS + 0.17 + + + MEM_RLD2_TDS_NS + 0.17 + + + MEM_RLD2_TQKH_HCYC + 0.9 + + + MEM_RLD2_TQKQ_MAX_NS + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + -0.12 + + + MEM_RLD2_TRC + 8 + + + MEM_RLD2_TRL + 8 + + + MEM_RLD2_TWL + 9 + + + MEM_RLD2_WIDTH_EXPANDED + false + + + MEM_RLD3_ADDR_WIDTH + 20 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + RLD3_AREF_BAC + + + MEM_RLD3_BANK_ADDR_WIDTH + 4 + + + MEM_RLD3_BL + 2 + + + MEM_RLD3_CS_WIDTH + 1 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + RLD3_DL_RL16_WL17 + + + MEM_RLD3_DEPTH_EXPANDED + false + + + MEM_RLD3_DEVICE_DEPTH + 1 + + + MEM_RLD3_DEVICE_WIDTH + 1 + + + MEM_RLD3_DK_WIDTH + 2 + + + MEM_RLD3_DM_EN + true + + + MEM_RLD3_DM_WIDTH + 2 + + + MEM_RLD3_DQ_PER_DEVICE + 36 + + + MEM_RLD3_DQ_PER_RD_GROUP + 9 + + + MEM_RLD3_DQ_PER_WR_GROUP + 18 + + + MEM_RLD3_DQ_WIDTH + 36 + + + MEM_RLD3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD3_MR0 + 0 + + + MEM_RLD3_MR1 + 0 + + + MEM_RLD3_MR2 + 0 + + + MEM_RLD3_ODT_MODE_ENUM + RLD3_ODT_40 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_QK_WIDTH + 4 + + + MEM_RLD3_SPEEDBIN_ENUM + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TCKDK_MAX_CYC + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + 135 + + + MEM_RLD3_TDH_DC_MV + 100 + + + MEM_RLD3_TDH_PS + 5 + + + MEM_RLD3_TDS_AC_MV + 150 + + + MEM_RLD3_TDS_PS + -30 + + + MEM_RLD3_TIH_DC_MV + 100 + + + MEM_RLD3_TIH_PS + 65 + + + MEM_RLD3_TIS_AC_MV + 150 + + + MEM_RLD3_TIS_PS + 85 + + + MEM_RLD3_TQH_CYC + 0.38 + + + MEM_RLD3_TQKQ_MAX_PS + 75 + + + MEM_RLD3_T_RC_MODE_ENUM + RLD3_TRC_9 + + + MEM_RLD3_WIDTH_EXPANDED + false + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + RLD3_WRITE_1BANK + + + MEM_TTL_DATA_WIDTH + 72 + + + MEM_TTL_NUM_OF_READ_GROUPS + 9 + + + MEM_TTL_NUM_OF_WRITE_GROUPS + 9 + + + MEM_WRITE_LATENCY + 18 + + + NUM_IPS + 1 + + + NUM_IPS_SAVED + 0 + + + PHY_AC_CALIBRATED_OCT + true + + + PHY_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CALIBRATED_OCT + true + + + PHY_CK_CALIBRATED_OCT + true + + + PHY_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CLAMSHELL_EN + false + + + PHY_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DATA_CALIBRATED_OCT + true + + + PHY_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DATA_OUT_SLEW_RATE_ENUM + + + + PHY_DDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_AC_IO_STD_ENUM + unset + + + PHY_DDR3_AC_MODE_ENUM + unset + + + PHY_DDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_CAL_ADDR0 + 0 + + + PHY_DDR3_CAL_ADDR1 + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + false + + + PHY_DDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_CK_IO_STD_ENUM + unset + + + PHY_DDR3_CK_MODE_ENUM + unset + + + PHY_DDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR3_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_DEFAULT_IO + true + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR3_IO_VOLTAGE + 1.5 + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_DDR3_MIMIC_HPS_EMIF + false + + + PHY_DDR3_PING_PONG_EN + false + + + PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_RATE_ENUM + RATE_QUARTER + + + PHY_DDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR3_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_STARTING_VREFIN + 70.0 + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_PING_PONG_EN + false + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_DDR4_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_AC_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_ALLOW_72_DQ_WIDTH + false + + + PHY_DDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_CK_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_CLAMSHELL_EN + false + + + PHY_DDR4_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR4_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DDR4_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_DEFAULT_IO + false + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR4_IO_VOLTAGE + 1.2 + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDR4_MIMIC_HPS_EMIF + false + + + PHY_DDR4_PING_PONG_EN + false + + + PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_RATE_ENUM + RATE_QUARTER + + + PHY_DDR4_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR4_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_STARTING_VREFIN + 68.0 + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_CLAMSHELL_EN + false + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_USER_PING_PONG_EN + false + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_2CH_EN + false + + + PHY_DDRT_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_AC_IO_STD_ENUM + unset + + + PHY_DDRT_AC_MODE_ENUM + unset + + + PHY_DDRT_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_CK_IO_STD_ENUM + unset + + + PHY_DDRT_CK_MODE_ENUM + unset + + + PHY_DDRT_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDRT_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_DEFAULT_IO + true + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDRT_EXPORT_CLK_STP_IF + false + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDRT_I2C_USE_SMC + false + + + PHY_DDRT_IC_EN + true + + + PHY_DDRT_IO_VOLTAGE + 1.2 + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDRT_MIMIC_HPS_EMIF + false + + + PHY_DDRT_PING_PONG_EN + false + + + PHY_DDRT_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_RATE_ENUM + RATE_QUARTER + + + PHY_DDRT_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDRT_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_IO_STD_ENUM + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_USER_PING_PONG_EN + false + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + false + + + PHY_DLL_CORE_UPDN_EN + false + + + PHY_FPGA_SPEEDGRADE_GUI + E2V (ES3) - change device under 'View'->'Device Family' + + + PHY_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_AC_MODE_ENUM + unset + + + PHY_LPDDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_CK_MODE_ENUM + unset + + + PHY_LPDDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_LPDDR3_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_DEFAULT_IO + true + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_IO_VOLTAGE + 1.2 + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + 800.0 + + + PHY_LPDDR3_MIMIC_HPS_EMIF + false + + + PHY_LPDDR3_PING_PONG_EN + false + + + PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_RATE_ENUM + RATE_QUARTER + + + PHY_LPDDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_LPDDR3_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_STARTING_VREFIN + 70.0 + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_PING_PONG_EN + false + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_MIMIC_HPS_EMIF + false + + + PHY_PING_PONG_EN + false + + + PHY_QDR2_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_AC_IO_STD_ENUM + unset + + + PHY_QDR2_AC_MODE_ENUM + unset + + + PHY_QDR2_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_CK_IO_STD_ENUM + unset + + + PHY_QDR2_CK_MODE_ENUM + unset + + + PHY_QDR2_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR2_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_DEFAULT_IO + true + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR2_IO_VOLTAGE + 1.5 + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + 633.333 + + + PHY_QDR2_MIMIC_HPS_EMIF + false + + + PHY_QDR2_PING_PONG_EN + false + + + PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_RATE_ENUM + RATE_HALF + + + PHY_QDR2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR2_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_STARTING_VREFIN + 70.0 + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_PING_PONG_EN + false + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_USER_STARTING_VREFIN + 70.0 + + + PHY_QDR4_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_AC_IO_STD_ENUM + unset + + + PHY_QDR4_AC_MODE_ENUM + unset + + + PHY_QDR4_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_CK_IO_STD_ENUM + unset + + + PHY_QDR4_CK_MODE_ENUM + unset + + + PHY_QDR4_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR4_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_DEFAULT_IO + true + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR4_IO_VOLTAGE + 1.2 + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_QDR4_MIMIC_HPS_EMIF + false + + + PHY_QDR4_PING_PONG_EN + false + + + PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_RATE_ENUM + RATE_QUARTER + + + PHY_QDR4_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR4_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_STARTING_VREFIN + 70.0 + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_PING_PONG_EN + false + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_RATE_ENUM + RATE_QUARTER + + + PHY_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_AC_IO_STD_ENUM + unset + + + PHY_RLD2_AC_MODE_ENUM + unset + + + PHY_RLD2_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_CK_IO_STD_ENUM + unset + + + PHY_RLD2_CK_MODE_ENUM + unset + + + PHY_RLD2_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD2_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_DEFAULT_IO + true + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD2_IO_VOLTAGE + 1.8 + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + 533.333 + + + PHY_RLD2_MIMIC_HPS_EMIF + false + + + PHY_RLD2_PING_PONG_EN + false + + + PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_RATE_ENUM + RATE_HALF + + + PHY_RLD2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_STARTING_VREFIN + 70.0 + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_PING_PONG_EN + false + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_USER_STARTING_VREFIN + 70.0 + + + PHY_RLD3_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_AC_IO_STD_ENUM + unset + + + PHY_RLD3_AC_MODE_ENUM + unset + + + PHY_RLD3_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_CK_IO_STD_ENUM + unset + + + PHY_RLD3_CK_MODE_ENUM + unset + + + PHY_RLD3_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_CONFIG_ENUM + CONFIG_PHY_ONLY + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD3_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_DEFAULT_IO + true + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD3_IO_VOLTAGE + 1.2 + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_RLD3_MIMIC_HPS_EMIF + false + + + PHY_RLD3_PING_PONG_EN + false + + + PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_RATE_ENUM + RATE_QUARTER + + + PHY_RLD3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD3_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_STARTING_VREFIN + 70.0 + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_PING_PONG_EN + false + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_USER_STARTING_VREFIN + 70.0 + + + PHY_RZQ + 240 + + + PHY_TARGET_IS_ES + false + + + PHY_TARGET_IS_ES2 + false + + + PHY_TARGET_IS_ES3 + true + + + PHY_TARGET_IS_PRODUCTION + false + + + PHY_TARGET_SPEEDGRADE + E2V + + + PHY_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PLL_ADD_EXTRA_CLKS + false + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + ps + + + PLL_NUM_OF_EXTRA_CLKS + 0 + + + PLL_USER_NUM_OF_EXTRA_CLKS + 0 + + + PLL_VCO_CLK_FREQ_MHZ + 1200.0 + + + PREV_PROTOCOL_ENUM + PROTOCOL_DDR4 + + + PROTOCOL_ENUM + PROTOCOL_DDR4 + + + SHORT_QSYS_INTERFACE_NAMES + true + + + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_DEVICE_DIE_REVISIONS + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + + + SYS_INFO_DEVICE_FAMILY + Agilex 7 + + + SYS_INFO_DEVICE_POWER_MODEL + STANDARD_POWER + + + SYS_INFO_DEVICE_SPEEDGRADE + 2 + + + SYS_INFO_DEVICE_TEMPERATURE_GRADE + EXTENDED + + + SYS_INFO_UNIQUE_ID + ed_synth_emif_fm_0_emif_fm_0 + + + TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + TRAIT_SUPPORTS_VID + 1 + + + + altera_emif_ecc + 19.1 + ecc_core + ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq + 0 + + + + + qsys_mm.piplineType + PIPELINE_STAGE + + + qsys_mm.insertDefaultSlave + FALSE + + + qsys_mm.enableOutOfOrderSupport + FALSE + + + qsys_mm.enableInstrumentation + FALSE + + + qsys_mm.widthAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.interconnectResetSource + DEFAULT + + + qsys_mm.burstAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.optimizeRdFifoSize + FALSE + + + qsys_mm.responseFifoType + REGISTER_BASED + + + qsys_mm.clockCrossingAdapter + HANDSHAKE + + + qsys_mm.maxAdditionalLatency + 1 + + + qsys_mm.syncResets + FALSE + + + qsys_mm.enableAllPipelines + FALSE + + + qsys_mm.enableEccProtection + FALSE + + + qsys_mm.interconnectType + STANDARD + + + + avalon_streaming + 24.1 + arch.ctrl_ast_rd_0/ecc_core.ctrl_ast_rd_0 + ecc_core/ctrl_ast_rd_0 + arch/ctrl_ast_rd_0 + + + + + resetDomainSysInfo + -1 + + + clockDomainSysInfo + -1 + + + clockResetSysInfo + + + + clockRateSysInfo + -1 + + + + clock + 24.1 + arch.emif_usr_clk/ecc_core.emif_usr_clk_in + ecc_core/emif_usr_clk_in + arch/emif_usr_clk + + + + + resetDomainSysInfo + -1 + + + clockDomainSysInfo + -1 + + + clockResetSysInfo + + + + + reset + 24.1 + arch.emif_usr_reset_n/ecc_core.emif_usr_reset_n_in + ecc_core/emif_usr_reset_n_in + arch/emif_usr_reset_n + + + + + qsys_mm.piplineType + PIPELINE_STAGE + + + qsys_mm.insertDefaultSlave + FALSE + + + qsys_mm.enableOutOfOrderSupport + FALSE + + + qsys_mm.enableInstrumentation + FALSE + + + qsys_mm.widthAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.interconnectResetSource + DEFAULT + + + qsys_mm.burstAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.optimizeRdFifoSize + FALSE + + + qsys_mm.responseFifoType + REGISTER_BASED + + + qsys_mm.clockCrossingAdapter + HANDSHAKE + + + qsys_mm.maxAdditionalLatency + 1 + + + qsys_mm.syncResets + FALSE + + + qsys_mm.enableAllPipelines + FALSE + + + qsys_mm.enableEccProtection + FALSE + + + qsys_mm.interconnectType + STANDARD + + + + avalon_streaming + 24.1 + ecc_core.ctrl_ast_cmd_0/arch.ctrl_ast_cmd_0 + arch/ctrl_ast_cmd_0 + ecc_core/ctrl_ast_cmd_0 + + + + + qsys_mm.piplineType + PIPELINE_STAGE + + + qsys_mm.insertDefaultSlave + FALSE + + + qsys_mm.enableOutOfOrderSupport + FALSE + + + qsys_mm.enableInstrumentation + FALSE + + + qsys_mm.widthAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.interconnectResetSource + DEFAULT + + + qsys_mm.burstAdapterImplementation + GENERIC_CONVERTER + + + qsys_mm.optimizeRdFifoSize + FALSE + + + qsys_mm.responseFifoType + REGISTER_BASED + + + qsys_mm.clockCrossingAdapter + HANDSHAKE + + + qsys_mm.maxAdditionalLatency + 1 + + + qsys_mm.syncResets + FALSE + + + qsys_mm.enableAllPipelines + FALSE + + + qsys_mm.enableEccProtection + FALSE + + + qsys_mm.interconnectType + STANDARD + + + + avalon_streaming + 24.1 + ecc_core.ctrl_ast_wr_0/arch.ctrl_ast_wr_0 + arch/ctrl_ast_wr_0 + ecc_core/ctrl_ast_wr_0 + + + + + startPortLSB + 0 + + + endPort + + + + endPortLSB + 0 + + + startPort + + + + width + 0 + + + + conduit + 24.1 + ecc_core.ctrl_ecc_0/arch.ctrl_ecc_0 + arch/ctrl_ecc_0 + ecc_core/ctrl_ecc_0 + + + ed_synth_emif_fm_0.emif_fm_0.ecc_core + + + + core + + + + BOARD_DDR3_AC_ISI_NS + 0.0 + + + BOARD_DDR3_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_DDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR3_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDR3_TDH_DERATING_PS + 0 + + + BOARD_DDR3_TDS_DERATING_PS + 0 + + + BOARD_DDR3_TIH_DERATING_PS + 0 + + + BOARD_DDR3_TIS_DERATING_PS + 0 + + + BOARD_DDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_DDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR3_WCLK_ISI_NS + 0.0 + + + BOARD_DDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR3_WDATA_ISI_NS + 0.0 + + + BOARD_DDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_ISI_NS + 0.15 + + + BOARD_DDR4_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_RCLK_ISI_NS + 0.15 + + + BOARD_DDR4_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_RDATA_ISI_NS + 0.12 + + + BOARD_DDR4_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDR4_SKEW_WITHIN_AC_NS + 0.18 + + + BOARD_DDR4_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDR4_TIH_DERATING_PS + 0 + + + BOARD_DDR4_TIS_DERATING_PS + 0 + + + BOARD_DDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDR4_WCLK_ISI_NS + 0.06 + + + BOARD_DDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDR4_WDATA_ISI_NS + 0.13 + + + BOARD_DDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_ISI_NS + 0.0 + + + BOARD_DDRT_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + false + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + true + + + BOARD_DDRT_MAX_CK_DELAY_NS + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_DDRT_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_DDRT_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_DDRT_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_DDRT_TIH_DERATING_PS + 0 + + + BOARD_DDRT_TIS_DERATING_PS + 0 + + + BOARD_DDRT_USER_AC_ISI_NS + 0.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + 2.0 + + + BOARD_DDRT_USER_CK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + 8.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + true + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + true + + + BOARD_DDRT_WCLK_ISI_NS + 0.0 + + + BOARD_DDRT_WCLK_SLEW_RATE + 4.0 + + + BOARD_DDRT_WDATA_ISI_NS + 0.0 + + + BOARD_DDRT_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + false + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + 0.6 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + 0.02 + + + BOARD_LPDDR3_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + 0.02 + + + BOARD_LPDDR3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_LPDDR3_SKEW_WITHIN_DQS_NS + 0.0 + + + BOARD_LPDDR3_TDH_DERATING_PS + 0 + + + BOARD_LPDDR3_TDS_DERATING_PS + 0 + + + BOARD_LPDDR3_TIH_DERATING_PS + 0 + + + BOARD_LPDDR3_TIS_DERATING_PS + 0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_LPDDR3_WCLK_ISI_NS + 0.0 + + + BOARD_LPDDR3_WCLK_SLEW_RATE + 4.0 + + + BOARD_LPDDR3_WDATA_ISI_NS + 0.0 + + + BOARD_LPDDR3_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_ISI_NS + 0.0 + + + BOARD_QDR2_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + 0.0 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + false + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + false + + + BOARD_QDR2_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + 0.6 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + 0.02 + + + BOARD_QDR2_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_D_NS + 0.0 + + + BOARD_QDR2_SKEW_WITHIN_Q_NS + 0.0 + + + BOARD_QDR2_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_K_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR2_WCLK_ISI_NS + 0.0 + + + BOARD_QDR2_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR2_WDATA_ISI_NS + 0.0 + + + BOARD_QDR2_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_ISI_NS + 0.0 + + + BOARD_QDR4_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + true + + + BOARD_QDR4_MAX_CK_DELAY_NS + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + 0.6 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_QDR4_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_QDR4_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_QDR4_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_QDR4_USER_AC_ISI_NS + 0.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + 2.0 + + + BOARD_QDR4_USER_CK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + 5.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + 2.5 + + + BOARD_QDR4_USER_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + true + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + true + + + BOARD_QDR4_WCLK_ISI_NS + 0.0 + + + BOARD_QDR4_WCLK_SLEW_RATE + 4.0 + + + BOARD_QDR4_WDATA_ISI_NS + 0.0 + + + BOARD_QDR4_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_ISI_NS + 0.0 + + + BOARD_RLD3_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + 0.0 + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + -0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + true + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + false + + + BOARD_RLD3_MAX_CK_DELAY_NS + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + 0.6 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + 0.02 + + + BOARD_RLD3_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + 0.02 + + + BOARD_RLD3_SKEW_WITHIN_AC_NS + 0.0 + + + BOARD_RLD3_SKEW_WITHIN_QK_NS + 0.0 + + + BOARD_RLD3_TDH_DERATING_PS + 0 + + + BOARD_RLD3_TDS_DERATING_PS + 0 + + + BOARD_RLD3_TIH_DERATING_PS + 0 + + + BOARD_RLD3_TIS_DERATING_PS + 0 + + + BOARD_RLD3_USER_AC_ISI_NS + 0.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + 2.0 + + + BOARD_RLD3_USER_CK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + 7.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + 3.5 + + + BOARD_RLD3_USER_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + 2.0 + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + true + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + true + + + BOARD_RLD3_WCLK_ISI_NS + 0.0 + + + BOARD_RLD3_WCLK_SLEW_RATE + 4.0 + + + BOARD_RLD3_WDATA_ISI_NS + 0.0 + + + BOARD_RLD3_WDATA_SLEW_RATE + 2.0 + + + C2P_P2C_CLK_RATIO + 4 + + + CAL_DEBUG_CLOCK_FREQUENCY + 50000000 + + + CTRL_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + false + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR3_ECC_EN + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + true + + + CTRL_DDR3_ECC_STATUS_EN + false + + + CTRL_DDR3_MMR_EN + false + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_REORDER_EN + true + + + CTRL_DDR3_SELF_REFRESH_EN + false + + + CTRL_DDR3_STARVE_LIMIT + 10 + + + CTRL_DDR3_USER_PRIORITY_EN + false + + + CTRL_DDR3_USER_REFRESH_EN + false + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_ADDR_ORDER_ENUM + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + false + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDR4_ECC_EN + true + + + CTRL_DDR4_ECC_READDATAERROR_EN + false + + + CTRL_DDR4_ECC_STATUS_EN + false + + + CTRL_DDR4_MAJOR_MODE_EN + false + + + CTRL_DDR4_MMR_EN + false + + + CTRL_DDR4_POST_REFRESH_EN + true + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + 1 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_REORDER_EN + true + + + CTRL_DDR4_SELF_REFRESH_EN + false + + + CTRL_DDR4_STARVE_LIMIT + 10 + + + CTRL_DDR4_USER_PRIORITY_EN + false + + + CTRL_DDR4_USER_REFRESH_EN + false + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ADDR_INTERLEAVING + COARSE + + + CTRL_DDRT_ADDR_ORDER_ENUM + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + false + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_AXIS_DATA_WIDTH + 512 + + + CTRL_DDRT_DIMM_DENSITY + 128 + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + false + + + CTRL_DDRT_DRIVER_MARGINING_EN + 0 + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + false + + + CTRL_DDRT_ECC_EN + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + true + + + CTRL_DDRT_ECC_STATUS_EN + true + + + CTRL_DDRT_ERR_INJECT_EN + false + + + CTRL_DDRT_ERR_REPLAY_EN + false + + + CTRL_DDRT_EXT_ERR_INJECT_EN + false + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + 1 + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + false + + + CTRL_DDRT_MMR_EN + false + + + CTRL_DDRT_NUM_OF_AXIS_ID + 1 + + + CTRL_DDRT_PARITY_CMD_EN + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + false + + + CTRL_DDRT_POISON_DETECTION_EN + false + + + CTRL_DDRT_PORT_AFI_C_WIDTH + 2 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_REORDER_EN + true + + + CTRL_DDRT_SELF_REFRESH_EN + false + + + CTRL_DDRT_STARVE_LIMIT + 10 + + + CTRL_DDRT_UPI_EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + 8 + + + CTRL_DDRT_USER_PRIORITY_EN + false + + + CTRL_DDRT_USER_REFRESH_EN + false + + + CTRL_DDRT_WR_ACK_POLICY + POSTED + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_DDRT_ZQ_INTERVAL_MS + 3 + + + CTRL_ECC_EN + true + + + CTRL_ECC_READDATAERROR_EN + false + + + CTRL_ECC_STATUS_EN + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + 32 + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + false + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_MMR_EN + false + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_REORDER_EN + true + + + CTRL_LPDDR3_SELF_REFRESH_EN + false + + + CTRL_LPDDR3_STARVE_LIMIT + 10 + + + CTRL_LPDDR3_USER_PRIORITY_EN + false + + + CTRL_LPDDR3_USER_REFRESH_EN + false + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + 0 + + + CTRL_MMR_EN + false + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + 0 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + false + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + 4 + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_SYMBOL_WIDTH + 9 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC + 4 + + + CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC + 11 + + + CTRL_REORDER_EN + true + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + CTRL_AVL_PROTOCOL_MM + + + CTRL_USER_PRIORITY_EN + false + + + DIAG_AC_PARITY_ERR + false + + + DIAG_ADD_READY_PIPELINE + true + + + DIAG_BOARD_DELAY_CONFIG_STR + + + + DIAG_DB_RESET_AUTO_RELEASE + avl_release + + + DIAG_DDR3_ABSTRACT_PHY + false + + + DIAG_DDR3_AC_PARITY_ERR + false + + + DIAG_DDR3_CAL_ADDR0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + 8 + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + false + + + DIAG_DDR3_CAL_ENABLE_NON_DES + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR3_CA_DESKEW_EN + true + + + DIAG_DDR3_CA_LEVEL_EN + true + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR3_ENABLE_USER_MODE + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR3_INTERFACE_ID + 0 + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR3_SIM_VERBOSE + true + + + DIAG_DDR3_TG2_TEST_DURATION + SHORT + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR3_USE_TG_AVL_2 + false + + + DIAG_DDR3_USE_TG_HBM + false + + + DIAG_DDR4_ABSTRACT_PHY + false + + + DIAG_DDR4_AC_PARITY_ERR + false + + + DIAG_DDR4_CAL_ADDR0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_DDR4_ENABLE_USER_MODE + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDR4_INTERFACE_ID + 0 + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDR4_SIM_VERBOSE + true + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + false + + + DIAG_DDR4_SKIP_CA_DESKEW + false + + + DIAG_DDR4_SKIP_CA_LEVEL + false + + + DIAG_DDR4_SKIP_VREF_CAL + false + + + DIAG_DDR4_TG2_TEST_DURATION + SHORT + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDR4_USE_TG_AVL_2 + false + + + DIAG_DDR4_USE_TG_HBM + false + + + DIAG_DDRT_ABSTRACT_PHY + false + + + DIAG_DDRT_AC_PARITY_ERR + false + + + DIAG_DDRT_CAL_ADDR0 + 0 + + + DIAG_DDRT_CAL_ADDR1 + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + true + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_DDRT_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_DDRT_EFF_TEST + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + false + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + false + + + DIAG_DDRT_ENABLE_USER_MODE + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_DDRT_INTERFACE_ID + 0 + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_DDRT_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_DDRT_SIM_VERBOSE + true + + + DIAG_DDRT_SKIP_CA_DESKEW + false + + + DIAG_DDRT_SKIP_CA_LEVEL + false + + + DIAG_DDRT_SKIP_VREF_CAL + false + + + DIAG_DDRT_TG2_TEST_DURATION + SHORT + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + false + + + DIAG_DDRT_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_DDRT_USE_TG_AVL_2 + true + + + DIAG_DDRT_USE_TG_HBM + false + + + DIAG_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_ECLIPSE_DEBUG + false + + + DIAG_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_ENABLE_DEFAULT_MODE + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + false + + + DIAG_ENABLE_JTAG_UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + false + + + DIAG_ENABLE_SOFT_M20K + false + + + DIAG_ENABLE_USER_MODE + true + + + DIAG_EXPORT_PLL_LOCKED + true + + + DIAG_EXPORT_PLL_REF_CLK_OUT + false + + + DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_JTAG + + + DIAG_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_EXPORT_VJI + false + + + DIAG_EXPOSE_DFT_SIGNALS + false + + + DIAG_EXPOSE_EARLY_READY + false + + + DIAG_EXPOSE_RD_TYPE + false + + + DIAG_EXTRA_CONFIGS + + + + DIAG_EXT_DOCS + false + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + + + + DIAG_EX_DESIGN_ISSP_EN + true + + + DIAG_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_EX_DESIGN_SEPARATE_RESETS + false + + + DIAG_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_FAST_SIM + true + + + DIAG_FAST_SIM_OVERRIDE + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_HMC_HRC + auto + + + DIAG_INTERFACE_ID + 0 + + + DIAG_LPDDR3_ABSTRACT_PHY + false + + + DIAG_LPDDR3_AC_PARITY_ERR + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_LPDDR3_INTERFACE_ID + 0 + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_LPDDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_LPDDR3_SIM_VERBOSE + true + + + DIAG_LPDDR3_SKIP_CA_DESKEW + false + + + DIAG_LPDDR3_SKIP_CA_LEVEL + false + + + DIAG_LPDDR3_TG2_TEST_DURATION + SHORT + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + false + + + DIAG_LPDDR3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_LPDDR3_USE_TG_AVL_2 + false + + + DIAG_LPDDR3_USE_TG_HBM + false + + + DIAG_QDR2_ABSTRACT_PHY + false + + + DIAG_QDR2_AC_PARITY_ERR + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR2_ENABLE_USER_MODE + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR2_INTERFACE_ID + 0 + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR2_SIM_VERBOSE + true + + + DIAG_QDR2_TG2_TEST_DURATION + SHORT + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR2_USE_TG_AVL_2 + false + + + DIAG_QDR2_USE_TG_HBM + false + + + DIAG_QDR4_ABSTRACT_PHY + false + + + DIAG_QDR4_AC_PARITY_ERR + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_QDR4_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + false + + + DIAG_QDR4_ENABLE_USER_MODE + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_QDR4_INTERFACE_ID + 0 + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_QDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_QDR4_SIM_VERBOSE + true + + + DIAG_QDR4_SKIP_VREF_CAL + false + + + DIAG_QDR4_TG2_TEST_DURATION + SHORT + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + false + + + DIAG_QDR4_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_QDR4_USE_TG_AVL_2 + false + + + DIAG_QDR4_USE_TG_HBM + false + + + DIAG_RLD2_ABSTRACT_PHY + false + + + DIAG_RLD2_AC_PARITY_ERR + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD2_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD2_ENABLE_USER_MODE + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD2_INTERFACE_ID + 0 + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD2_SIM_VERBOSE + true + + + DIAG_RLD2_TG2_TEST_DURATION + SHORT + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD2_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD2_USE_TG_AVL_2 + false + + + DIAG_RLD2_USE_TG_HBM + false + + + DIAG_RLD3_ABSTRACT_PHY + false + + + DIAG_RLD3_AC_PARITY_ERR + false + + + DIAG_RLD3_CA_DESKEW_EN + true + + + DIAG_RLD3_CA_LEVEL_EN + true + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + false + + + DIAG_RLD3_EFFICIENCY_MONITOR + EFFMON_MODE_DISABLED + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + false + + + DIAG_RLD3_ENABLE_USER_MODE + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + true + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG_CFG_AMM_EXPORT_MODE_EXPORT + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + 1 + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + true + + + DIAG_RLD3_INTERFACE_ID + 0 + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + false + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_RLD3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_RLD3_SIM_VERBOSE + true + + + DIAG_RLD3_TG2_TEST_DURATION + SHORT + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + true + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + false + + + DIAG_RLD3_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_RLD3_USE_TG_AVL_2 + false + + + DIAG_RLD3_USE_TG_HBM + false + + + DIAG_RS232_UART_BAUDRATE + 57600 + + + DIAG_SEQ_RESET_AUTO_RELEASE + avl + + + DIAG_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_SIM_CHECKER_SKIP_TG + false + + + DIAG_SIM_MEMORY_PRELOAD + false + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + + + + DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE + + + + DIAG_SIM_REGTEST_MODE + false + + + DIAG_SIM_VERBOSE_LEVEL + 5 + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + 100 + + + DIAG_SOFT_NIOS_MODE + SOFT_NIOS_MODE_DISABLED + + + DIAG_SYNTH_FOR_SIM + false + + + DIAG_TG2_TEST_DURATION + SHORT + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + 0 + + + DIAG_TIMING_REGTEST_MODE + false + + + DIAG_USE_ABSTRACT_PHY + false + + + DIAG_USE_BOARD_DELAY_MODEL + false + + + DIAG_USE_NEW_EFFMON_S10 + false + + + DIAG_USE_RS232_UART + false + + + DIAG_USE_SIM_MEMORY_VALIDATION_TG + false + + + DIAG_USE_TG_AVL_2 + false + + + DIAG_USE_TG_HBM + false + + + DIAG_VERBOSE_IOAUX + false + + + ECC_MMR_READ_LATENCY + 5 + + + EMIF_0_CONN_TO_CALIP + CALIP_0 + + + EMIF_0_REF_CLK_SHARING + EXPORTED + + + EMIF_0_STORED_PARAM + + + + EMIF_10_CONN_TO_CALIP + CALIP_0 + + + EMIF_10_REF_CLK_SHARING + EXPORTED + + + EMIF_10_STORED_PARAM + + + + EMIF_11_CONN_TO_CALIP + CALIP_0 + + + EMIF_11_REF_CLK_SHARING + EXPORTED + + + EMIF_11_STORED_PARAM + + + + EMIF_12_CONN_TO_CALIP + CALIP_0 + + + EMIF_12_REF_CLK_SHARING + EXPORTED + + + EMIF_12_STORED_PARAM + + + + EMIF_13_CONN_TO_CALIP + CALIP_0 + + + EMIF_13_REF_CLK_SHARING + EXPORTED + + + EMIF_13_STORED_PARAM + + + + EMIF_14_CONN_TO_CALIP + CALIP_0 + + + EMIF_14_REF_CLK_SHARING + EXPORTED + + + EMIF_14_STORED_PARAM + + + + EMIF_15_CONN_TO_CALIP + CALIP_0 + + + EMIF_15_REF_CLK_SHARING + EXPORTED + + + EMIF_15_STORED_PARAM + + + + EMIF_1_CONN_TO_CALIP + CALIP_0 + + + EMIF_1_REF_CLK_SHARING + EXPORTED + + + EMIF_1_STORED_PARAM + + + + EMIF_2_CONN_TO_CALIP + CALIP_0 + + + EMIF_2_REF_CLK_SHARING + EXPORTED + + + EMIF_2_STORED_PARAM + + + + EMIF_3_CONN_TO_CALIP + CALIP_0 + + + EMIF_3_REF_CLK_SHARING + EXPORTED + + + EMIF_3_STORED_PARAM + + + + EMIF_4_CONN_TO_CALIP + CALIP_0 + + + EMIF_4_REF_CLK_SHARING + EXPORTED + + + EMIF_4_STORED_PARAM + + + + EMIF_5_CONN_TO_CALIP + CALIP_0 + + + EMIF_5_REF_CLK_SHARING + EXPORTED + + + EMIF_5_STORED_PARAM + + + + EMIF_6_CONN_TO_CALIP + CALIP_0 + + + EMIF_6_REF_CLK_SHARING + EXPORTED + + + EMIF_6_STORED_PARAM + + + + EMIF_7_CONN_TO_CALIP + CALIP_0 + + + EMIF_7_REF_CLK_SHARING + EXPORTED + + + EMIF_7_STORED_PARAM + + + + EMIF_8_CONN_TO_CALIP + CALIP_0 + + + EMIF_8_REF_CLK_SHARING + EXPORTED + + + EMIF_8_STORED_PARAM + + + + EMIF_9_CONN_TO_CALIP + CALIP_0 + + + EMIF_9_REF_CLK_SHARING + EXPORTED + + + EMIF_9_STORED_PARAM + + + + ENABLE_ECC + 1 + + + ENABLE_ECC_AUTO_CORRECTION + 0 + + + EX_DESIGN_GUI_DDR3_GEN_BSI + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + false + + + EX_DESIGN_GUI_DDR3_GEN_SIM + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_GEN_BSI + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + false + + + EX_DESIGN_GUI_DDR4_GEN_SIM + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_GEN_BSI + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + false + + + EX_DESIGN_GUI_DDRT_GEN_SIM + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + true + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_GEN_BSI + false + + + EX_DESIGN_GUI_GEN_CDC + false + + + EX_DESIGN_GUI_GEN_SIM + true + + + EX_DESIGN_GUI_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + false + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + true + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_GEN_BSI + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + false + + + EX_DESIGN_GUI_QDR2_GEN_SIM + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_GEN_BSI + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + false + + + EX_DESIGN_GUI_QDR4_GEN_SIM + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + true + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_GEN_BSI + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + false + + + EX_DESIGN_GUI_RLD2_GEN_SIM + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_GEN_BSI + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + false + + + EX_DESIGN_GUI_RLD3_GEN_SIM + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + true + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_TARGET_DEV_KIT + TARGET_DEV_KIT_NONE + + + FAMILY_ENUM + FAMILY_AGILEX + + + INTERNAL_TESTING_MODE + false + + + IS_ED_SLAVE + false + + + MEM_BURST_LENGTH + 8 + + + MEM_DATA_MASK_EN + true + + + MEM_DDR3_AC_PAR_EN + false + + + MEM_DDR3_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR3_ADDR_WIDTH + 1 + + + MEM_DDR3_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ASR_ENUM + DDR3_ASR_MANUAL + + + MEM_DDR3_ATCL_ENUM + DDR3_ATCL_DISABLED + + + MEM_DDR3_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_BL_ENUM + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_CFG_GEN_DBE + false + + + MEM_DDR3_CFG_GEN_SBE + false + + + MEM_DDR3_CKE_PER_DIMM + 1 + + + MEM_DDR3_CKE_WIDTH + 1 + + + MEM_DDR3_CK_WIDTH + 1 + + + MEM_DDR3_COL_ADDR_WIDTH + 10 + + + MEM_DDR3_CS_PER_DIMM + 1 + + + MEM_DDR3_CS_WIDTH + 1 + + + MEM_DDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR3_DLL_EN + true + + + MEM_DDR3_DM_EN + true + + + MEM_DDR3_DM_WIDTH + 1 + + + MEM_DDR3_DQS_WIDTH + 8 + + + MEM_DDR3_DQ_PER_DQS + 8 + + + MEM_DDR3_DQ_WIDTH + 72 + + + MEM_DDR3_DRV_STR_ENUM + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_FORMAT_ENUM + MEM_FORMAT_UDIMM + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + 000000000000000000 + + + MEM_DDR3_MIRROR_ADDRESSING_EN + true + + + MEM_DDR3_MR0 + 0 + + + MEM_DDR3_MR1 + 0 + + + MEM_DDR3_MR2 + 0 + + + MEM_DDR3_MR3 + 0 + + + MEM_DDR3_NUM_OF_DIMMS + 1 + + + MEM_DDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_ODT_WIDTH + 1 + + + MEM_DDR3_PD_ENUM + DDR3_PD_OFF + + + MEM_DDR3_RANKS_PER_DIMM + 1 + + + MEM_DDR3_RDIMM_CONFIG + 0000000000000000 + + + MEM_DDR3_RM_WIDTH + 0 + + + MEM_DDR3_ROW_ADDR_WIDTH + 15 + + + MEM_DDR3_RTT_NOM_ENUM + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_R_DERIVED_ODT0 + + + + MEM_DDR3_R_DERIVED_ODT1 + + + + MEM_DDR3_R_DERIVED_ODT2 + + + + MEM_DDR3_R_DERIVED_ODT3 + + + + MEM_DDR3_R_DERIVED_ODTN + + + + MEM_DDR3_R_ODT0_1X1 + off + + + MEM_DDR3_R_ODT0_2X2 + off,off + + + MEM_DDR3_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR3_R_ODT1_2X2 + off,off + + + MEM_DDR3_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR3_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR3_R_ODTN_1X1 + Rank 0 + + + MEM_DDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR3_SPEEDBIN_ENUM + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_SRT_ENUM + DDR3_SRT_NORMAL + + + MEM_DDR3_TCL + 14 + + + MEM_DDR3_TDH_DC_MV + 100 + + + MEM_DDR3_TDH_PS + 55 + + + MEM_DDR3_TDQSCKDL + 1200 + + + MEM_DDR3_TDQSCKDM + 900 + + + MEM_DDR3_TDQSCKDS + 450 + + + MEM_DDR3_TDQSCK_DERV_PS + 2 + + + MEM_DDR3_TDQSCK_PS + 180 + + + MEM_DDR3_TDQSQ_PS + 75 + + + MEM_DDR3_TDQSS_CYC + 0.27 + + + MEM_DDR3_TDSH_CYC + 0.18 + + + MEM_DDR3_TDSS_CYC + 0.18 + + + MEM_DDR3_TDS_AC_MV + 135 + + + MEM_DDR3_TDS_PS + 53 + + + MEM_DDR3_TFAW_CYC + 27 + + + MEM_DDR3_TFAW_NS + 25.0 + + + MEM_DDR3_TIH_DC_MV + 100 + + + MEM_DDR3_TIH_PS + 95 + + + MEM_DDR3_TINIT_CK + 499 + + + MEM_DDR3_TINIT_US + 500 + + + MEM_DDR3_TIS_AC_MV + 135 + + + MEM_DDR3_TIS_PS + 60 + + + MEM_DDR3_TMRD_CK_CYC + 4 + + + MEM_DDR3_TQH_CYC + 0.38 + + + MEM_DDR3_TQSH_CYC + 0.4 + + + MEM_DDR3_TRAS_CYC + 36 + + + MEM_DDR3_TRAS_NS + 33.0 + + + MEM_DDR3_TRCD_CYC + 14 + + + MEM_DDR3_TRCD_NS + 13.09 + + + MEM_DDR3_TREFI_CYC + 8320 + + + MEM_DDR3_TREFI_US + 7.8 + + + MEM_DDR3_TRFC_CYC + 171 + + + MEM_DDR3_TRFC_NS + 160.0 + + + MEM_DDR3_TRP_CYC + 14 + + + MEM_DDR3_TRP_NS + 13.09 + + + MEM_DDR3_TRRD_CYC + 6 + + + MEM_DDR3_TRTP_CYC + 8 + + + MEM_DDR3_TTL_ADDR_WIDTH + 1 + + + MEM_DDR3_TTL_BANK_ADDR_WIDTH + 3 + + + MEM_DDR3_TTL_CKE_WIDTH + 1 + + + MEM_DDR3_TTL_CK_WIDTH + 1 + + + MEM_DDR3_TTL_CS_WIDTH + 1 + + + MEM_DDR3_TTL_DM_WIDTH + 1 + + + MEM_DDR3_TTL_DQS_WIDTH + 8 + + + MEM_DDR3_TTL_DQ_WIDTH + 72 + + + MEM_DDR3_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR3_TTL_ODT_WIDTH + 1 + + + MEM_DDR3_TTL_RM_WIDTH + 0 + + + MEM_DDR3_TWLH_PS + 125.0 + + + MEM_DDR3_TWLS_PS + 125.0 + + + MEM_DDR3_TWR_CYC + 16 + + + MEM_DDR3_TWR_NS + 15.0 + + + MEM_DDR3_TWTR_CYC + 8 + + + MEM_DDR3_USE_DEFAULT_ODT + true + + + MEM_DDR3_WTCL + 10 + + + MEM_DDR3_W_DERIVED_ODT0 + + + + MEM_DDR3_W_DERIVED_ODT1 + + + + MEM_DDR3_W_DERIVED_ODT2 + + + + MEM_DDR3_W_DERIVED_ODT3 + + + + MEM_DDR3_W_DERIVED_ODTN + + + + MEM_DDR3_W_ODT0_1X1 + on + + + MEM_DDR3_W_ODT0_2X2 + on,off + + + MEM_DDR3_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR3_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT1_2X2 + off,on + + + MEM_DDR3_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR3_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR3_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR3_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR3_W_ODTN_1X1 + Rank 0 + + + MEM_DDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR3_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_AC_PARITY_LATENCY + DDR4_AC_PARITY_LATENCY_DISABLE + + + MEM_DDR4_AC_PERSISTENT_ERROR + false + + + MEM_DDR4_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDR4_ADDR_WIDTH + 17 + + + MEM_DDR4_ALERT_N_AC_LANE + 3 + + + MEM_DDR4_ALERT_N_AC_PIN + 8 + + + MEM_DDR4_ALERT_N_DQS_GROUP + 0 + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + + + MEM_DDR4_ALERT_PAR_EN + true + + + MEM_DDR4_ASR_ENUM + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_ATCL_ENUM + DDR4_ATCL_DISABLED + + + MEM_DDR4_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_BL_ENUM + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_CAL_MODE + 0 + + + MEM_DDR4_CFG_GEN_DBE + false + + + MEM_DDR4_CFG_GEN_SBE + false + + + MEM_DDR4_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_CKE_PER_DIMM + 1 + + + MEM_DDR4_CKE_WIDTH + 1 + + + MEM_DDR4_CK_WIDTH + 1 + + + MEM_DDR4_COL_ADDR_WIDTH + 10 + + + MEM_DDR4_CS_PER_DIMM + 1 + + + MEM_DDR4_CS_WIDTH + 1 + + + MEM_DDR4_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDR4_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DEFAULT_VREFOUT + true + + + MEM_DDR4_DISCRETE_CS_WIDTH + 1 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDR4_DLL_EN + true + + + MEM_DDR4_DM_EN + true + + + MEM_DDR4_DQS_WIDTH + 9 + + + MEM_DDR4_DQ_PER_DQS + 8 + + + MEM_DDR4_DQ_WIDTH + 72 + + + MEM_DDR4_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_DDR4_GEARDOWN + DDR4_GEARDOWN_HR + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDR4_IDEAL_VREF_IN_PCT + 68.0 + + + MEM_DDR4_IDEAL_VREF_OUT_PCT + 70.0 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP + RTT_NOM disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP + RTT_PARK disabled + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP + RZQ/3 (80 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP + RZQ/7 (34 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM + DDR4_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP + ODT Disabled + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM + DDR4_RTT_PARK_RZQ_4 + + + MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP + RZQ/4 (60 Ohm) + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP + Dynamic ODT off + + + MEM_DDR4_INTEL_DEFAULT_TERM + true + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDR4_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + + + + MEM_DDR4_MAX_POWERDOWN + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + true + + + MEM_DDR4_MPR_READ_FORMAT + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MR0 + 2164 + + + MEM_DDR4_MR1 + 65537 + + + MEM_DDR4_MR2 + 131112 + + + MEM_DDR4_MR3 + 197632 + + + MEM_DDR4_MR4 + 264192 + + + MEM_DDR4_MR5 + 332896 + + + MEM_DDR4_MR6 + 395279 + + + MEM_DDR4_NUM_OF_DIMMS + 1 + + + MEM_DDR4_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_ODT_IN_POWERDOWN + true + + + MEM_DDR4_ODT_WIDTH + 1 + + + MEM_DDR4_PER_DRAM_ADDR + false + + + MEM_DDR4_RANKS_PER_DIMM + 1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_COMMAND_LATENCY + 1 + + + MEM_DDR4_RCD_CS_IBT_ENUM + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_RCD_PARITY_CONTROL_WORD + 13 + + + MEM_DDR4_RDIMM_CONFIG + 00000020000000003900000D40030B0F556000 + + + MEM_DDR4_READ_DBI + true + + + MEM_DDR4_READ_PREAMBLE + 2 + + + MEM_DDR4_READ_PREAMBLE_TRAINING + false + + + MEM_DDR4_RM_WIDTH + 0 + + + MEM_DDR4_ROW_ADDR_WIDTH + 16 + + + MEM_DDR4_RTT_NOM_ENUM + DDR4_RTT_NOM_RZQ_4 + + + MEM_DDR4_RTT_PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_RTT_WR_ENUM + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_R_DERIVED_BODT0 + + + + MEM_DDR4_R_DERIVED_BODT1 + + + + MEM_DDR4_R_DERIVED_BODTN + + + + MEM_DDR4_R_DERIVED_ODT0 + (Drive) RZQ/7 (34 Ohm),-,-,- + + + MEM_DDR4_R_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_R_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_R_ODT0_1X1 + off + + + MEM_DDR4_R_ODT0_2X2 + off,off + + + MEM_DDR4_R_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_R_ODT0_4X4 + off,off,on,off + + + MEM_DDR4_R_ODT1_2X2 + off,off + + + MEM_DDR4_R_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_R_ODT1_4X4 + off,off,off,on + + + MEM_DDR4_R_ODT2_4X4 + on,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + off,on,off,off + + + MEM_DDR4_R_ODTN_1X1 + Rank 0 + + + MEM_DDR4_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_SELF_RFSH_ABORT + false + + + MEM_DDR4_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDR4_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDR4_SPD_135_RCD_REV + 0 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + 101 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDR4_SPD_139_DB_REV + 0 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + 0 + + + MEM_DDR4_SPEEDBIN_ENUM + DDR4_SPEEDBIN_2666 + + + MEM_DDR4_TCCD_L_CYC + 6 + + + MEM_DDR4_TCCD_S_CYC + 4 + + + MEM_DDR4_TCL + 21 + + + MEM_DDR4_TDIVW_DJ_CYC + 0.1 + + + MEM_DDR4_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDR4_TDQSCKDL + 1200 + + + MEM_DDR4_TDQSCKDM + 900 + + + MEM_DDR4_TDQSCKDS + 450 + + + MEM_DDR4_TDQSCK_DERV_PS + 2 + + + MEM_DDR4_TDQSCK_PS + 175 + + + MEM_DDR4_TDQSQ_PS + 66 + + + MEM_DDR4_TDQSQ_UI + 0.14 + + + MEM_DDR4_TDQSS_CYC + 0.27 + + + MEM_DDR4_TDSH_CYC + 0.18 + + + MEM_DDR4_TDSS_CYC + 0.18 + + + MEM_DDR4_TDVWP_UI + 0.72 + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_SENSOR_READOUT + false + + + MEM_DDR4_TFAW_CYC + 26 + + + MEM_DDR4_TFAW_DLR_CYC + 16 + + + MEM_DDR4_TFAW_NS + 21.0 + + + MEM_DDR4_TIH_DC_MV + 75 + + + MEM_DDR4_TIH_PS + 87 + + + MEM_DDR4_TINIT_CK + 600000 + + + MEM_DDR4_TINIT_US + 500 + + + MEM_DDR4_TIS_AC_MV + 100 + + + MEM_DDR4_TIS_PS + 62 + + + MEM_DDR4_TMRD_CK_CYC + 8 + + + MEM_DDR4_TQH_CYC + 0.38 + + + MEM_DDR4_TQH_UI + 0.74 + + + MEM_DDR4_TQSH_CYC + 0.4 + + + MEM_DDR4_TRAS_CYC + 39 + + + MEM_DDR4_TRAS_NS + 32.0 + + + MEM_DDR4_TRCD_CYC + 17 + + + MEM_DDR4_TRCD_NS + 14.16 + + + MEM_DDR4_TREFI_CYC + 9360 + + + MEM_DDR4_TREFI_US + 7.8 + + + MEM_DDR4_TRFC_CYC + 420 + + + MEM_DDR4_TRFC_DLR_CYC + 108 + + + MEM_DDR4_TRFC_DLR_NS + 90.0 + + + MEM_DDR4_TRFC_NS + 350.0 + + + MEM_DDR4_TRP_CYC + 17 + + + MEM_DDR4_TRP_NS + 14.16 + + + MEM_DDR4_TRRD_DLR_CYC + 4 + + + MEM_DDR4_TRRD_L_CYC + 6 + + + MEM_DDR4_TRRD_S_CYC + 4 + + + MEM_DDR4_TRTP_CYC + 9 + + + MEM_DDR4_TTL_ADDR_WIDTH + 17 + + + MEM_DDR4_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDR4_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDR4_TTL_CHIP_ID_WIDTH + 0 + + + MEM_DDR4_TTL_CKE_WIDTH + 1 + + + MEM_DDR4_TTL_CK_WIDTH + 1 + + + MEM_DDR4_TTL_CS_WIDTH + 1 + + + MEM_DDR4_TTL_DQS_WIDTH + 9 + + + MEM_DDR4_TTL_DQ_WIDTH + 72 + + + MEM_DDR4_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDR4_TTL_ODT_WIDTH + 1 + + + MEM_DDR4_TTL_RM_WIDTH + 0 + + + MEM_DDR4_TWLH_CYC + 0.13 + + + MEM_DDR4_TWLH_PS + 0.0 + + + MEM_DDR4_TWLS_CYC + 0.13 + + + MEM_DDR4_TWLS_PS + 0.0 + + + MEM_DDR4_TWR_CYC + 18 + + + MEM_DDR4_TWR_NS + 15.0 + + + MEM_DDR4_TWTR_L_CYC + 9 + + + MEM_DDR4_TWTR_S_CYC + 3 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDR4_USE_DEFAULT_ODT + true + + + MEM_DDR4_VDIVW_TOTAL + 130 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE + DDR4_VREFDQ_TRAINING_RANGE_0 + + + MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP + Range 1 - 60% to 92.5% + + + MEM_DDR4_VREFDQ_TRAINING_VALUE + 70.0 + + + MEM_DDR4_WRITE_CMD_LATENCY + 6 + + + MEM_DDR4_WRITE_CRC + false + + + MEM_DDR4_WRITE_DBI + false + + + MEM_DDR4_WRITE_PREAMBLE + 1 + + + MEM_DDR4_WTCL + 16 + + + MEM_DDR4_W_DERIVED_BODT0 + + + + MEM_DDR4_W_DERIVED_BODT1 + + + + MEM_DDR4_W_DERIVED_BODTN + + + + MEM_DDR4_W_DERIVED_ODT0 + (Park) RZQ/4 (60 Ohm),-,-,- + + + MEM_DDR4_W_DERIVED_ODT1 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT2 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODT3 + -,-,-,- + + + MEM_DDR4_W_DERIVED_ODTN + Rank 0,-,-,- + + + MEM_DDR4_W_ODT0_1X1 + on + + + MEM_DDR4_W_ODT0_2X2 + on,off + + + MEM_DDR4_W_ODT0_4X2 + off,off,on,on + + + MEM_DDR4_W_ODT0_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT1_2X2 + off,on + + + MEM_DDR4_W_ODT1_4X2 + on,on,off,off + + + MEM_DDR4_W_ODT1_4X4 + off,on,off,on + + + MEM_DDR4_W_ODT2_4X4 + on,off,on,off + + + MEM_DDR4_W_ODT3_4X4 + off,on,off,on + + + MEM_DDR4_W_ODTN_1X1 + Rank 0 + + + MEM_DDR4_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDR4_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_AC_PARITY_LATENCY + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_AC_PERSISTENT_ERROR + false + + + MEM_DDRT_ADDRESS_MIRROR_BITVEC + 0 + + + MEM_DDRT_ADDR_WIDTH + 1 + + + MEM_DDRT_ALERT_N_AC_LANE + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + 0 + + + MEM_DDRT_ALERT_N_DQS_GROUP + 0 + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_PAR_EN + true + + + MEM_DDRT_ASR_ENUM + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_ATCL_ENUM + DDRT_ATCL_DISABLED + + + MEM_DDRT_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_BL_ENUM + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_CAL_MODE + 0 + + + MEM_DDRT_CFG_GEN_DBE + false + + + MEM_DDRT_CFG_GEN_SBE + false + + + MEM_DDRT_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_CKE_PER_DIMM + 1 + + + MEM_DDRT_CKE_WIDTH + 1 + + + MEM_DDRT_CK_WIDTH + 1 + + + MEM_DDRT_COL_ADDR_WIDTH + 10 + + + MEM_DDRT_CS_PER_DIMM + 1 + + + MEM_DDRT_CS_WIDTH + 1 + + + MEM_DDRT_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_DDRT_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_DDRT_DB_DQ_DRV_ENUM + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_PARK_ENUM + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + true + + + MEM_DDRT_DEFAULT_PREAMBLE + true + + + MEM_DDRT_DEFAULT_VREFOUT + true + + + MEM_DDRT_DISCRETE_CS_WIDTH + 1 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + false + + + MEM_DDRT_DLL_EN + true + + + MEM_DDRT_DM_EN + false + + + MEM_DDRT_DQS_WIDTH + 8 + + + MEM_DDRT_DQ_PER_DQS + 4 + + + MEM_DDRT_DQ_WIDTH + 72 + + + MEM_DDRT_DRV_STR_ENUM + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ERID_WIDTH + 2 + + + MEM_DDRT_ERR_N_WIDTH + 1 + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_FORMAT_ENUM + MEM_FORMAT_LRDIMM + + + MEM_DDRT_GEARDOWN + DDRT_GEARDOWN_HR + + + MEM_DDRT_GNT_N_WIDTH + 1 + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + true + + + MEM_DDRT_I2C_DIMM_0_SA + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + 3 + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + false + + + MEM_DDRT_LRDIMM_EXTENDED_CONFIG + + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + 240 + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + + + + MEM_DDRT_MAX_POWERDOWN + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + true + + + MEM_DDRT_MPR_READ_FORMAT + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MR0 + 0 + + + MEM_DDRT_MR1 + 0 + + + MEM_DDRT_MR2 + 0 + + + MEM_DDRT_MR3 + 0 + + + MEM_DDRT_MR4 + 0 + + + MEM_DDRT_MR5 + 0 + + + MEM_DDRT_MR6 + 0 + + + MEM_DDRT_NUM_OF_DIMMS + 1 + + + MEM_DDRT_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_ODT_IN_POWERDOWN + true + + + MEM_DDRT_ODT_WIDTH + 1 + + + MEM_DDRT_PARTIAL_WRITES + false + + + MEM_DDRT_PERSISTENT_MODE + 1 + + + MEM_DDRT_PER_DRAM_ADDR + false + + + MEM_DDRT_PWR_MODE + DDRT_PWR_MODE_12W + + + MEM_DDRT_RANKS_PER_DIMM + 1 + + + MEM_DDRT_RCD_CA_IBT_ENUM + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_COMMAND_LATENCY + 1 + + + MEM_DDRT_RCD_CS_IBT_ENUM + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_RCD_PARITY_CONTROL_WORD + 1 + + + MEM_DDRT_RDIMM_CONFIG + + + + MEM_DDRT_READ_DBI + false + + + MEM_DDRT_READ_PREAMBLE + 1 + + + MEM_DDRT_READ_PREAMBLE_TRAINING + false + + + MEM_DDRT_REQ_N_WIDTH + 1 + + + MEM_DDRT_RM_WIDTH + 0 + + + MEM_DDRT_ROW_ADDR_WIDTH + 18 + + + MEM_DDRT_RTT_NOM_ENUM + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_RTT_PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_RTT_WR_ENUM + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_R_DERIVED_BODT0 + + + + MEM_DDRT_R_DERIVED_BODT1 + + + + MEM_DDRT_R_DERIVED_BODTN + + + + MEM_DDRT_R_DERIVED_ODT0 + + + + MEM_DDRT_R_DERIVED_ODT1 + + + + MEM_DDRT_R_DERIVED_ODT2 + + + + MEM_DDRT_R_DERIVED_ODT3 + + + + MEM_DDRT_R_DERIVED_ODTN + + + + MEM_DDRT_R_ODT0_1X1 + off + + + MEM_DDRT_R_ODT0_2X2 + off,off + + + MEM_DDRT_R_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_R_ODT0_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT1_2X2 + off,off + + + MEM_DDRT_R_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_R_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_R_ODTN_1X1 + Rank 0 + + + MEM_DDRT_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_R_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_SELF_RFSH_ABORT + false + + + MEM_DDRT_SEQ_ODT_TABLE_HI + 0 + + + MEM_DDRT_SEQ_ODT_TABLE_LO + 0 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + 0 + + + MEM_DDRT_SPD_135_RCD_REV + 0 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + 5 + + + MEM_DDRT_SPD_139_DB_REV + 0 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + 39 + + + MEM_DDRT_SPEEDBIN_ENUM + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TCCD_L_CYC + 6 + + + MEM_DDRT_TCCD_S_CYC + 4 + + + MEM_DDRT_TCL + 15 + + + MEM_DDRT_TCL_ADDED + -1 + + + MEM_DDRT_TDIVW_DJ_CYC + 0.1 + + + MEM_DDRT_TDIVW_TOTAL_UI + 0.2 + + + MEM_DDRT_TDQSCKDL + 1200 + + + MEM_DDRT_TDQSCKDM + 900 + + + MEM_DDRT_TDQSCKDS + 450 + + + MEM_DDRT_TDQSCK_DERV_PS + 2 + + + MEM_DDRT_TDQSCK_PS + 165 + + + MEM_DDRT_TDQSQ_PS + 66 + + + MEM_DDRT_TDQSQ_UI + 0.16 + + + MEM_DDRT_TDQSS_CYC + 0.27 + + + MEM_DDRT_TDSH_CYC + 0.18 + + + MEM_DDRT_TDSS_CYC + 0.18 + + + MEM_DDRT_TDVWP_UI + 0.72 + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_SENSOR_READOUT + false + + + MEM_DDRT_TFAW_CYC + 27 + + + MEM_DDRT_TFAW_DLR_CYC + 16 + + + MEM_DDRT_TFAW_NS + 21.0 + + + MEM_DDRT_TIH_DC_MV + 75 + + + MEM_DDRT_TIH_PS + 95 + + + MEM_DDRT_TINIT_CK + 499 + + + MEM_DDRT_TINIT_US + 500 + + + MEM_DDRT_TIS_AC_MV + 100 + + + MEM_DDRT_TIS_PS + 60 + + + MEM_DDRT_TMRD_CK_CYC + 8 + + + MEM_DDRT_TQH_CYC + 0.38 + + + MEM_DDRT_TQH_UI + 0.76 + + + MEM_DDRT_TQSH_CYC + 0.38 + + + MEM_DDRT_TRAS_CYC + 36 + + + MEM_DDRT_TRAS_NS + 32.0 + + + MEM_DDRT_TRCD_CYC + 14 + + + MEM_DDRT_TRCD_NS + 15.0 + + + MEM_DDRT_TREFI_CYC + 8320 + + + MEM_DDRT_TREFI_US + 7.8 + + + MEM_DDRT_TRFC_CYC + 171 + + + MEM_DDRT_TRFC_DLR_CYC + 109 + + + MEM_DDRT_TRFC_DLR_NS + 90.0 + + + MEM_DDRT_TRFC_NS + 260.0 + + + MEM_DDRT_TRP_CYC + 14 + + + MEM_DDRT_TRP_NS + 15.0 + + + MEM_DDRT_TRRD_DLR_CYC + 4 + + + MEM_DDRT_TRRD_L_CYC + 6 + + + MEM_DDRT_TRRD_S_CYC + 4 + + + MEM_DDRT_TRTP_CYC + 9 + + + MEM_DDRT_TTL_ADDR_WIDTH + 1 + + + MEM_DDRT_TTL_BANK_ADDR_WIDTH + 2 + + + MEM_DDRT_TTL_BANK_GROUP_WIDTH + 2 + + + MEM_DDRT_TTL_CHIP_ID_WIDTH + 2 + + + MEM_DDRT_TTL_CKE_WIDTH + 1 + + + MEM_DDRT_TTL_CK_WIDTH + 1 + + + MEM_DDRT_TTL_CS_WIDTH + 1 + + + MEM_DDRT_TTL_DQS_WIDTH + 8 + + + MEM_DDRT_TTL_DQ_WIDTH + 72 + + + MEM_DDRT_TTL_ERID_WIDTH + 2 + + + MEM_DDRT_TTL_ERR_N_WIDTH + 1 + + + MEM_DDRT_TTL_GNT_N_WIDTH + 1 + + + MEM_DDRT_TTL_NUM_OF_DIMMS + 1 + + + MEM_DDRT_TTL_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_DDRT_TTL_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_DDRT_TTL_ODT_WIDTH + 1 + + + MEM_DDRT_TTL_REQ_N_WIDTH + 1 + + + MEM_DDRT_TTL_RM_WIDTH + 0 + + + MEM_DDRT_TWLH_CYC + 0.13 + + + MEM_DDRT_TWLH_PS + 0.0 + + + MEM_DDRT_TWLS_CYC + 0.13 + + + MEM_DDRT_TWLS_PS + 0.0 + + + MEM_DDRT_TWR_CYC + 18 + + + MEM_DDRT_TWR_NS + 15.0 + + + MEM_DDRT_TWTR_L_CYC + 9 + + + MEM_DDRT_TWTR_S_CYC + 3 + + + MEM_DDRT_USER_READ_PREAMBLE + 1 + + + MEM_DDRT_USER_TCL_ADDED + 0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_USER_WRITE_PREAMBLE + 1 + + + MEM_DDRT_USER_WTCL_ADDED + 6 + + + MEM_DDRT_USE_DEFAULT_ODT + true + + + MEM_DDRT_VDIVW_TOTAL + 136 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_VREFDQ_TRAINING_RANGE_DISP + Range 2 - 45% to 77.5% + + + MEM_DDRT_VREFDQ_TRAINING_VALUE + 56.0 + + + MEM_DDRT_WRITE_CMD_LATENCY + 5 + + + MEM_DDRT_WRITE_CRC + false + + + MEM_DDRT_WRITE_DBI + false + + + MEM_DDRT_WRITE_PREAMBLE + 1 + + + MEM_DDRT_WTCL + 18 + + + MEM_DDRT_WTCL_ADDED + -1 + + + MEM_DDRT_W_DERIVED_BODT0 + + + + MEM_DDRT_W_DERIVED_BODT1 + + + + MEM_DDRT_W_DERIVED_BODTN + + + + MEM_DDRT_W_DERIVED_ODT0 + + + + MEM_DDRT_W_DERIVED_ODT1 + + + + MEM_DDRT_W_DERIVED_ODT2 + + + + MEM_DDRT_W_DERIVED_ODT3 + + + + MEM_DDRT_W_DERIVED_ODTN + + + + MEM_DDRT_W_ODT0_1X1 + on + + + MEM_DDRT_W_ODT0_2X2 + on,off + + + MEM_DDRT_W_ODT0_4X2 + off,off,on,on + + + MEM_DDRT_W_ODT0_4X4 + on,on,off,off + + + MEM_DDRT_W_ODT1_2X2 + off,on + + + MEM_DDRT_W_ODT1_4X2 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + on,on,off,off + + + MEM_DDRT_W_ODTN_1X1 + Rank 0 + + + MEM_DDRT_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_DDRT_W_ODTN_4X2 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DQ_WIDTH + 72 + + + MEM_FORMAT_ENUM + MEM_FORMAT_RDIMM + + + MEM_HAS_BSI_SUPPORT + true + + + MEM_HAS_SIM_SUPPORT + true + + + MEM_LPDDR3_ADDR_WIDTH + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + 3 + + + MEM_LPDDR3_BL + LPDDR3_BL_BL8 + + + MEM_LPDDR3_CKE_WIDTH + 1 + + + MEM_LPDDR3_CK_WIDTH + 1 + + + MEM_LPDDR3_COL_ADDR_WIDTH + 10 + + + MEM_LPDDR3_CS_WIDTH + 1 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP + 0 + + + MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK + 0 + + + MEM_LPDDR3_DATA_LATENCY + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + 1 + + + MEM_LPDDR3_DM_EN + true + + + MEM_LPDDR3_DM_WIDTH + 1 + + + MEM_LPDDR3_DQODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_DQS_WIDTH + 1 + + + MEM_LPDDR3_DQ_PER_DQS + 8 + + + MEM_LPDDR3_DQ_WIDTH + 32 + + + MEM_LPDDR3_DRV_STR + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_LPDDR3_MR1 + 0 + + + MEM_LPDDR3_MR11 + 0 + + + MEM_LPDDR3_MR2 + 0 + + + MEM_LPDDR3_MR3 + 0 + + + MEM_LPDDR3_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_LPDDR3_NWR + LPDDR3_NWR_NWR12 + + + MEM_LPDDR3_ODT_WIDTH + 1 + + + MEM_LPDDR3_PDODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_ROW_ADDR_WIDTH + 15 + + + MEM_LPDDR3_R_DERIVED_ODT0 + + + + MEM_LPDDR3_R_DERIVED_ODT1 + + + + MEM_LPDDR3_R_DERIVED_ODT2 + + + + MEM_LPDDR3_R_DERIVED_ODT3 + + + + MEM_LPDDR3_R_DERIVED_ODTN + + + + MEM_LPDDR3_R_ODT0_1X1 + off + + + MEM_LPDDR3_R_ODT0_2X2 + off,off + + + MEM_LPDDR3_R_ODT0_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_2X2 + off,off + + + MEM_LPDDR3_R_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_R_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_R_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_SEQ_ODT_TABLE_HI + 0 + + + MEM_LPDDR3_SEQ_ODT_TABLE_LO + 0 + + + MEM_LPDDR3_SPEEDBIN_ENUM + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TDH_DC_MV + 100 + + + MEM_LPDDR3_TDH_PS + 100 + + + MEM_LPDDR3_TDQSCKDL + 614 + + + MEM_LPDDR3_TDQSCKDM + 511 + + + MEM_LPDDR3_TDQSCKDS + 220 + + + MEM_LPDDR3_TDQSCK_DERV_PS + 2 + + + MEM_LPDDR3_TDQSCK_PS + 5500 + + + MEM_LPDDR3_TDQSQ_PS + 135 + + + MEM_LPDDR3_TDQSS_CYC + 1.25 + + + MEM_LPDDR3_TDSH_CYC + 0.2 + + + MEM_LPDDR3_TDSS_CYC + 0.2 + + + MEM_LPDDR3_TDS_AC_MV + 150 + + + MEM_LPDDR3_TDS_PS + 75 + + + MEM_LPDDR3_TFAW_CYC + 40 + + + MEM_LPDDR3_TFAW_NS + 50.0 + + + MEM_LPDDR3_TIH_DC_MV + 100 + + + MEM_LPDDR3_TIH_PS + 100 + + + MEM_LPDDR3_TINIT_CK + 499 + + + MEM_LPDDR3_TINIT_US + 500 + + + MEM_LPDDR3_TIS_AC_MV + 150 + + + MEM_LPDDR3_TIS_PS + 75 + + + MEM_LPDDR3_TMRR_CK_CYC + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + 10 + + + MEM_LPDDR3_TQH_CYC + 0.38 + + + MEM_LPDDR3_TQSH_CYC + 0.38 + + + MEM_LPDDR3_TRAS_CYC + 34 + + + MEM_LPDDR3_TRAS_NS + 42.5 + + + MEM_LPDDR3_TRCD_CYC + 17 + + + MEM_LPDDR3_TRCD_NS + 18.0 + + + MEM_LPDDR3_TREFI_CYC + 3120 + + + MEM_LPDDR3_TREFI_US + 3.9 + + + MEM_LPDDR3_TRFC_CYC + 168 + + + MEM_LPDDR3_TRFC_NS + 210.0 + + + MEM_LPDDR3_TRL_CYC + 10 + + + MEM_LPDDR3_TRP_CYC + 17 + + + MEM_LPDDR3_TRP_NS + 18.0 + + + MEM_LPDDR3_TRRD_CYC + 8 + + + MEM_LPDDR3_TRTP_CYC + 6 + + + MEM_LPDDR3_TWLH_PS + 175.0 + + + MEM_LPDDR3_TWLS_PS + 175.0 + + + MEM_LPDDR3_TWL_CYC + 6 + + + MEM_LPDDR3_TWR_CYC + 12 + + + MEM_LPDDR3_TWR_NS + 15.0 + + + MEM_LPDDR3_TWTR_CYC + 6 + + + MEM_LPDDR3_USE_DEFAULT_ODT + true + + + MEM_LPDDR3_WLSELECT + Set A + + + MEM_LPDDR3_W_DERIVED_ODT0 + + + + MEM_LPDDR3_W_DERIVED_ODT1 + + + + MEM_LPDDR3_W_DERIVED_ODT2 + + + + MEM_LPDDR3_W_DERIVED_ODT3 + + + + MEM_LPDDR3_W_DERIVED_ODTN + + + + MEM_LPDDR3_W_ODT0_1X1 + on + + + MEM_LPDDR3_W_ODT0_2X2 + on,on + + + MEM_LPDDR3_W_ODT0_4X4 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_2X2 + off,off + + + MEM_LPDDR3_W_ODT1_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_1X1 + Rank 0 + + + MEM_LPDDR3_W_ODTN_2X2 + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODTN_4X4 + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_NUM_OF_DATA_ENDPOINTS + 1 + + + MEM_NUM_OF_LOGICAL_RANKS + 1 + + + MEM_NUM_OF_PHYSICAL_RANKS + 1 + + + MEM_QDR2_ADDR_WIDTH + 19 + + + MEM_QDR2_BL + 4 + + + MEM_QDR2_BWS_EN + true + + + MEM_QDR2_BWS_N_PER_DEVICE + 4 + + + MEM_QDR2_BWS_N_WIDTH + 4 + + + MEM_QDR2_CQ_WIDTH + 1 + + + MEM_QDR2_DATA_PER_DEVICE + 36 + + + MEM_QDR2_DATA_WIDTH + 36 + + + MEM_QDR2_DEVICE_WIDTH + 1 + + + MEM_QDR2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR2_INTERNAL_JITTER_NS + 0.08 + + + MEM_QDR2_K_WIDTH + 1 + + + MEM_QDR2_SPEEDBIN_ENUM + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TCCQO_NS + 0.45 + + + MEM_QDR2_TCQDOH_NS + -0.09 + + + MEM_QDR2_TCQD_NS + 0.09 + + + MEM_QDR2_TCQH_NS + 0.71 + + + MEM_QDR2_THA_NS + 0.18 + + + MEM_QDR2_THD_NS + 0.18 + + + MEM_QDR2_TRL_CYC + 2.5 + + + MEM_QDR2_TSA_NS + 0.23 + + + MEM_QDR2_TSD_NS + 0.23 + + + MEM_QDR2_TWL_CYC + 1 + + + MEM_QDR2_WIDTH_EXPANDED + false + + + MEM_QDR4_AC_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_ADDR_INV_ENA + false + + + MEM_QDR4_ADDR_WIDTH + 21 + + + MEM_QDR4_AVL_CHNLS + 8 + + + MEM_QDR4_BL + 2 + + + MEM_QDR4_CK_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_CR0 + 0 + + + MEM_QDR4_CR1 + 0 + + + MEM_QDR4_CR2 + 0 + + + MEM_QDR4_DATA_INV_ENA + true + + + MEM_QDR4_DATA_ODT_MODE_ENUM + QDR4_ODT_25_PCT + + + MEM_QDR4_DEVICE_DEPTH + 1 + + + MEM_QDR4_DEVICE_WIDTH + 1 + + + MEM_QDR4_DINV_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DINV_WIDTH + 4 + + + MEM_QDR4_DK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_DK_WIDTH + 4 + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + 36 + + + MEM_QDR4_DQ_PER_PORT_WIDTH + 36 + + + MEM_QDR4_DQ_PER_RD_GROUP + 18 + + + MEM_QDR4_DQ_PER_WR_GROUP + 18 + + + MEM_QDR4_DQ_WIDTH + 72 + + + MEM_QDR4_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_QDR4_MEM_TYPE_ENUM + MEM_XP + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_QK_PER_PORT_WIDTH + 2 + + + MEM_QDR4_QK_WIDTH + 4 + + + MEM_QDR4_SKIP_ODT_SWEEPING + true + + + MEM_QDR4_SPEEDBIN_ENUM + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TASH_PS + 170 + + + MEM_QDR4_TCKDK_MAX_PS + 150 + + + MEM_QDR4_TCKDK_MIN_PS + -150 + + + MEM_QDR4_TCKQK_MAX_PS + 225 + + + MEM_QDR4_TCSH_PS + 170 + + + MEM_QDR4_TISH_PS + 150 + + + MEM_QDR4_TQH_CYC + 0.4 + + + MEM_QDR4_TQKQ_MAX_PS + 75 + + + MEM_QDR4_TRL_CYC + 8 + + + MEM_QDR4_TWL_CYC + 5 + + + MEM_QDR4_USE_ADDR_PARITY + false + + + MEM_QDR4_WIDTH_EXPANDED + false + + + MEM_READ_LATENCY + 23.0 + + + MEM_RLD2_ADDR_WIDTH + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + 3 + + + MEM_RLD2_BL + 4 + + + MEM_RLD2_CONFIG_ENUM + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_CS_WIDTH + 1 + + + MEM_RLD2_DEVICE_DEPTH + 1 + + + MEM_RLD2_DEVICE_WIDTH + 1 + + + MEM_RLD2_DK_WIDTH + 1 + + + MEM_RLD2_DM_EN + true + + + MEM_RLD2_DM_WIDTH + 1 + + + MEM_RLD2_DQ_PER_DEVICE + 9 + + + MEM_RLD2_DQ_PER_RD_GROUP + 9 + + + MEM_RLD2_DQ_PER_WR_GROUP + 9 + + + MEM_RLD2_DQ_WIDTH + 9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD2_MR + 0 + + + MEM_RLD2_ODT_MODE_ENUM + RLD2_ODT_ON + + + MEM_RLD2_QK_WIDTH + 1 + + + MEM_RLD2_REFRESH_INTERVAL_US + 0.24 + + + MEM_RLD2_SPEEDBIN_ENUM + RLD2_SPEEDBIN_18 + + + MEM_RLD2_TAH_NS + 0.3 + + + MEM_RLD2_TAS_NS + 0.3 + + + MEM_RLD2_TCKDK_MAX_NS + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + -0.3 + + + MEM_RLD2_TCKH_CYC + 0.45 + + + MEM_RLD2_TCKQK_MAX_NS + 0.2 + + + MEM_RLD2_TDH_NS + 0.17 + + + MEM_RLD2_TDS_NS + 0.17 + + + MEM_RLD2_TQKH_HCYC + 0.9 + + + MEM_RLD2_TQKQ_MAX_NS + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + -0.12 + + + MEM_RLD2_TRC + 8 + + + MEM_RLD2_TRL + 8 + + + MEM_RLD2_TWL + 9 + + + MEM_RLD2_WIDTH_EXPANDED + false + + + MEM_RLD3_ADDR_WIDTH + 20 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + RLD3_AREF_BAC + + + MEM_RLD3_BANK_ADDR_WIDTH + 4 + + + MEM_RLD3_BL + 2 + + + MEM_RLD3_CS_WIDTH + 1 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + RLD3_DL_RL16_WL17 + + + MEM_RLD3_DEPTH_EXPANDED + false + + + MEM_RLD3_DEVICE_DEPTH + 1 + + + MEM_RLD3_DEVICE_WIDTH + 1 + + + MEM_RLD3_DK_WIDTH + 2 + + + MEM_RLD3_DM_EN + true + + + MEM_RLD3_DM_WIDTH + 2 + + + MEM_RLD3_DQ_PER_DEVICE + 36 + + + MEM_RLD3_DQ_PER_RD_GROUP + 9 + + + MEM_RLD3_DQ_PER_WR_GROUP + 18 + + + MEM_RLD3_DQ_WIDTH + 36 + + + MEM_RLD3_FORMAT_ENUM + MEM_FORMAT_DISCRETE + + + MEM_RLD3_MR0 + 0 + + + MEM_RLD3_MR1 + 0 + + + MEM_RLD3_MR2 + 0 + + + MEM_RLD3_ODT_MODE_ENUM + RLD3_ODT_40 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_QK_WIDTH + 4 + + + MEM_RLD3_SPEEDBIN_ENUM + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TCKDK_MAX_CYC + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + 135 + + + MEM_RLD3_TDH_DC_MV + 100 + + + MEM_RLD3_TDH_PS + 5 + + + MEM_RLD3_TDS_AC_MV + 150 + + + MEM_RLD3_TDS_PS + -30 + + + MEM_RLD3_TIH_DC_MV + 100 + + + MEM_RLD3_TIH_PS + 65 + + + MEM_RLD3_TIS_AC_MV + 150 + + + MEM_RLD3_TIS_PS + 85 + + + MEM_RLD3_TQH_CYC + 0.38 + + + MEM_RLD3_TQKQ_MAX_PS + 75 + + + MEM_RLD3_T_RC_MODE_ENUM + RLD3_TRC_9 + + + MEM_RLD3_WIDTH_EXPANDED + false + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + RLD3_WRITE_1BANK + + + MEM_TTL_DATA_WIDTH + 72 + + + MEM_TTL_NUM_OF_READ_GROUPS + 9 + + + MEM_TTL_NUM_OF_WRITE_GROUPS + 9 + + + MEM_WRITE_LATENCY + 18 + + + NUM_IPS + 1 + + + NUM_IPS_SAVED + 0 + + + PHY_AC_CALIBRATED_OCT + true + + + PHY_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CALIBRATED_OCT + true + + + PHY_CK_CALIBRATED_OCT + true + + + PHY_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_CLAMSHELL_EN + false + + + PHY_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DATA_CALIBRATED_OCT + true + + + PHY_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DATA_OUT_SLEW_RATE_ENUM + + + + PHY_DDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_AC_IO_STD_ENUM + unset + + + PHY_DDR3_AC_MODE_ENUM + unset + + + PHY_DDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_CAL_ADDR0 + 0 + + + PHY_DDR3_CAL_ADDR1 + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + false + + + PHY_DDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_CK_IO_STD_ENUM + unset + + + PHY_DDR3_CK_MODE_ENUM + unset + + + PHY_DDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR3_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_DEFAULT_IO + true + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR3_IO_VOLTAGE + 1.5 + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_DDR3_MIMIC_HPS_EMIF + false + + + PHY_DDR3_PING_PONG_EN + false + + + PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_RATE_ENUM + RATE_QUARTER + + + PHY_DDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR3_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_STARTING_VREFIN + 70.0 + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_PING_PONG_EN + false + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_DDR4_AC_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_AC_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_ALLOW_72_DQ_WIDTH + false + + + PHY_DDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_CK_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_OFF + + + PHY_DDR4_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_CK_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_CLAMSHELL_EN + false + + + PHY_DDR4_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDR4_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM + DEEMPHASIS_MODE_HIGH + + + PHY_DDR4_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM + SLEW_RATE_FM_FAST + + + PHY_DDR4_DEFAULT_IO + false + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDR4_IO_VOLTAGE + 1.2 + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDR4_MIMIC_HPS_EMIF + false + + + PHY_DDR4_PING_PONG_EN + false + + + PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_RATE_ENUM + RATE_QUARTER + + + PHY_DDR4_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDR4_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_STARTING_VREFIN + 68.0 + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_AC_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_CLAMSHELL_EN + false + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + IN_OCT_60_CAL + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + OUT_OCT_40_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_USER_PING_PONG_EN + false + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + IO_STD_TRUE_DIFF_SIGNALING + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + IO_STD_CMOS_12 + + + PHY_DDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_2CH_EN + false + + + PHY_DDRT_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_AC_IO_STD_ENUM + unset + + + PHY_DDRT_AC_MODE_ENUM + unset + + + PHY_DDRT_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_CK_IO_STD_ENUM + unset + + + PHY_DDRT_CK_MODE_ENUM + unset + + + PHY_DDRT_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_DDRT_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_DEFAULT_IO + true + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + true + + + PHY_DDRT_EXPORT_CLK_STP_IF + false + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_DDRT_I2C_USE_SMC + false + + + PHY_DDRT_IC_EN + true + + + PHY_DDRT_IO_VOLTAGE + 1.2 + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_DDRT_MIMIC_HPS_EMIF + false + + + PHY_DDRT_PING_PONG_EN + false + + + PHY_DDRT_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_RATE_ENUM + RATE_QUARTER + + + PHY_DDRT_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + 10.0 + + + PHY_DDRT_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_IO_STD_ENUM + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_USER_PING_PONG_EN + false + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + unset + + + PHY_DDRT_USER_STARTING_VREFIN + 70.0 + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + false + + + PHY_DLL_CORE_UPDN_EN + false + + + PHY_FPGA_SPEEDGRADE_GUI + E2V (ES3) - change device under 'View'->'Device Family' + + + PHY_HMC_CLK_RATIO + 2 + + + PHY_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_AC_MODE_ENUM + unset + + + PHY_LPDDR3_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_CK_MODE_ENUM + unset + + + PHY_LPDDR3_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_CONFIG_ENUM + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_LPDDR3_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_DEFAULT_IO + true + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_LPDDR3_IO_VOLTAGE + 1.2 + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + 800.0 + + + PHY_LPDDR3_MIMIC_HPS_EMIF + false + + + PHY_LPDDR3_PING_PONG_EN + false + + + PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_RATE_ENUM + RATE_QUARTER + + + PHY_LPDDR3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + 10.0 + + + PHY_LPDDR3_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_STARTING_VREFIN + 70.0 + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_PING_PONG_EN + false + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_LPDDR3_USER_STARTING_VREFIN + 70.0 + + + PHY_MEM_CLK_FREQ_MHZ + 1200.0 + + + PHY_MIMIC_HPS_EMIF + false + + + PHY_PING_PONG_EN + false + + + PHY_QDR2_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_AC_IO_STD_ENUM + unset + + + PHY_QDR2_AC_MODE_ENUM + unset + + + PHY_QDR2_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_CK_IO_STD_ENUM + unset + + + PHY_QDR2_CK_MODE_ENUM + unset + + + PHY_QDR2_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR2_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_DEFAULT_IO + true + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR2_IO_VOLTAGE + 1.5 + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + 633.333 + + + PHY_QDR2_MIMIC_HPS_EMIF + false + + + PHY_QDR2_PING_PONG_EN + false + + + PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_RATE_ENUM + RATE_HALF + + + PHY_QDR2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR2_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_STARTING_VREFIN + 70.0 + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_PING_PONG_EN + false + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR2_USER_STARTING_VREFIN + 70.0 + + + PHY_QDR4_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_AC_IO_STD_ENUM + unset + + + PHY_QDR4_AC_MODE_ENUM + unset + + + PHY_QDR4_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_CK_IO_STD_ENUM + unset + + + PHY_QDR4_CK_MODE_ENUM + unset + + + PHY_QDR4_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_QDR4_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_DEFAULT_IO + true + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_QDR4_IO_VOLTAGE + 1.2 + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_QDR4_MIMIC_HPS_EMIF + false + + + PHY_QDR4_PING_PONG_EN + false + + + PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_RATE_ENUM + RATE_QUARTER + + + PHY_QDR4_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + 10.0 + + + PHY_QDR4_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_STARTING_VREFIN + 70.0 + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_AC_IO_STD_ENUM + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + true + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_PING_PONG_EN + false + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + unset + + + PHY_QDR4_USER_STARTING_VREFIN + 70.0 + + + PHY_RATE_ENUM + RATE_QUARTER + + + PHY_REF_CLK_FREQ_MHZ + 33.333 + + + PHY_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_AC_IO_STD_ENUM + unset + + + PHY_RLD2_AC_MODE_ENUM + unset + + + PHY_RLD2_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_CK_IO_STD_ENUM + unset + + + PHY_RLD2_CK_MODE_ENUM + unset + + + PHY_RLD2_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_CONFIG_ENUM + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD2_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_DEFAULT_IO + true + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD2_IO_VOLTAGE + 1.8 + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + 533.333 + + + PHY_RLD2_MIMIC_HPS_EMIF + false + + + PHY_RLD2_PING_PONG_EN + false + + + PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_RATE_ENUM + RATE_HALF + + + PHY_RLD2_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD2_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_STARTING_VREFIN + 70.0 + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_PING_PONG_EN + false + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD2_USER_STARTING_VREFIN + 70.0 + + + PHY_RLD3_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_AC_IO_STD_ENUM + unset + + + PHY_RLD3_AC_MODE_ENUM + unset + + + PHY_RLD3_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_CK_IO_STD_ENUM + unset + + + PHY_RLD3_CK_MODE_ENUM + unset + + + PHY_RLD3_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_CONFIG_ENUM + CONFIG_PHY_ONLY + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + false + + + PHY_RLD3_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_DEFAULT_IO + true + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + false + + + PHY_RLD3_IO_VOLTAGE + 1.2 + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + 1066.667 + + + PHY_RLD3_MIMIC_HPS_EMIF + false + + + PHY_RLD3_PING_PONG_EN + false + + + PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_RATE_ENUM + RATE_QUARTER + + + PHY_RLD3_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + 10.0 + + + PHY_RLD3_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_STARTING_VREFIN + 70.0 + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_AC_IO_STD_ENUM + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + true + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + unset + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_PING_PONG_EN + false + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + unset + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + -1.0 + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + unset + + + PHY_RLD3_USER_STARTING_VREFIN + 70.0 + + + PHY_RZQ + 240 + + + PHY_TARGET_IS_ES + false + + + PHY_TARGET_IS_ES2 + false + + + PHY_TARGET_IS_ES3 + true + + + PHY_TARGET_IS_PRODUCTION + false + + + PHY_TARGET_SPEEDGRADE + E2V + + + PHY_USER_PERIODIC_OCT_RECAL_ENUM + PERIODIC_OCT_RECAL_AUTO + + + PLL_ADD_EXTRA_CLKS + false + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 + 1200.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + 50.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + 0.0 + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + ps + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + ps + + + PLL_NUM_OF_EXTRA_CLKS + 0 + + + PLL_USER_NUM_OF_EXTRA_CLKS + 0 + + + PLL_VCO_CLK_FREQ_MHZ + 1200.0 + + + PORT_CTRL_AMM_ADDRESS_WIDTH + 27 + + + PORT_CTRL_AMM_BCOUNT_WIDTH + 7 + + + PORT_CTRL_AMM_BYTEEN_WIDTH + 64 + + + PORT_CTRL_AMM_RDATA_WIDTH + 512 + + + PORT_CTRL_AMM_WDATA_WIDTH + 512 + + + PORT_CTRL_AST_CMD_DATA_WIDTH + 61 + + + PORT_CTRL_AST_RD_DATA_WIDTH + 576 + + + PORT_CTRL_AST_WR_DATA_WIDTH + 648 + + + PORT_CTRL_ECC_CMD_INFO_WIDTH + 3 + + + PORT_CTRL_ECC_RDATA_ID_WIDTH + 13 + + + PORT_CTRL_ECC_READ_INFO_WIDTH + 3 + + + PORT_CTRL_ECC_STS_CORR_DROPPED_ADDR_WIDTH + 35 + + + PORT_CTRL_ECC_STS_CORR_DROPPED_COUNT_WIDTH + 4 + + + PORT_CTRL_ECC_STS_CORR_DROPPED_WIDTH + 1 + + + PORT_CTRL_ECC_STS_DBE_COUNT_WIDTH + 4 + + + PORT_CTRL_ECC_STS_DBE_ERROR_WIDTH + 1 + + + PORT_CTRL_ECC_STS_ERR_ADDR_WIDTH + 35 + + + PORT_CTRL_ECC_STS_INTR_WIDTH + 1 + + + PORT_CTRL_ECC_STS_SBE_COUNT_WIDTH + 4 + + + PORT_CTRL_ECC_STS_SBE_ERROR_WIDTH + 1 + + + PORT_CTRL_ECC_WB_POINTER_WIDTH + 12 + + + PORT_CTRL_ECC_WRITE_INFO_WIDTH + 15 + + + PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH + 10 + + + PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH + 2 + + + PORT_CTRL_MMR_MASTER_RDATA_WIDTH + 32 + + + PORT_CTRL_MMR_MASTER_WDATA_WIDTH + 32 + + + PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH + 10 + + + PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH + 2 + + + PORT_CTRL_MMR_SLAVE_RDATA_WIDTH + 32 + + + PORT_CTRL_MMR_SLAVE_WDATA_WIDTH + 32 + + + PREV_PROTOCOL_ENUM + PROTOCOL_DDR4 + + + PROTOCOL_ENUM + PROTOCOL_DDR4 + + + REGISTER_CORE_CMD_PIPELINE_WDATA + 0 + + + REGISTER_RDATA_PATH_NUM + 2 + + + REGISTER_ST_CMD_RDY_LAT_PATH + 0 + + + REGISTER_ST_RDATA_RDY_LAT_PATH + 0 + + + REGISTER_ST_WDATA_RDY_LAT_PATH + 0 + + + REGISTER_UFI_RDATA_PATH_NUM + 0 + + + REGISTER_WDATA_PATH_NUM + 2 + + + SHORT_QSYS_INTERFACE_NAMES + true + + + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_DEVICE_DIE_REVISIONS + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + + + SYS_INFO_DEVICE_FAMILY + Agilex 7 + + + SYS_INFO_DEVICE_POWER_MODEL + STANDARD_POWER + + + SYS_INFO_DEVICE_SPEEDGRADE + 2 + + + SYS_INFO_DEVICE_TEMPERATURE_GRADE + EXTENDED + + + SYS_INFO_UNIQUE_ID + ed_synth_emif_fm_0_emif_fm_0 + + + TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + TRAIT_SUPPORTS_VID + 1 + + + USER_CLK_RATIO + 4 + + + USE_AVL_BYTEEN + 1 + + + + altera_emif_ecc_fm + 19.1 + core + altera_emif_ecc_core + altera_emif_ecc_core + 0 + + ed_synth_emif_fm_0.emif_fm_0.ecc_core.core + + + + + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.qip b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.qip new file mode 100644 index 0000000000..b6c8810f3a --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.qip @@ -0,0 +1,949 @@ +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TOOL_VERSION "24.1" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_emif_fm" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name PRE_COMPILED_MODULE "ON" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name OCS_IP_FILE "/home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0.ip" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name OCS_IP_TYPE "altera_emif_fm" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name OCS_IP_VERSION "2.7.4" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name OCS_IP_HASH "z5lxzjq" +set_global_assignment -library "ed_synth_emif_fm_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "ed_synth_emif_fm_0.sopcinfo"] +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name SLD_INFO "QSYS_NAME ed_synth_emif_fm_0 HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "ed_synth_emif_fm_0" -name MISC_FILE [file join $::quartus(qip_path) "ed_synth_emif_fm_0.cmp"] +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 7" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TARGETED_PART_TRAIT "part.DEVICE_TEMPERATURE_GRADE::EXTENDED" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TARGETED_PART_TRAIT "part.DEVICE_POWER_MODEL::STANDARD_POWER" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TARGETED_PART_TRAIT "part.SUPPORTS_VID::1" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96A_REVB2" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 7}" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "ed_synth_emif_fm_0" -name MISC_FILE [file join $::quartus(qip_path) "../ed_synth_emif_fm_0.ip"] + +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_NAME "ZWRfc3ludGhfZW1pZl9mbV8wX2FsdGVyYV9lbWlmX2FyY2hfZm1fMTkxX2ZhYXB6eHk=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_DISPLAY_NAME "RU1JRiBBcmNoaXRlY3R1cmUgQ29tcG9uZW50" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_VERSION "MTkuMQ==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZSBBcmNoaXRlY3R1cmUgQ29tcG9uZW50" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJzL0ludGVybmFsIENvbXBvbmVudHM=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9zdXBwb3J0L2xpdGVyYXR1cmUvbGl0LWV4dGVybmFsLW1lbW9yeS1pbnRlcmZhY2UuaHRtbA==" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_NAME "YWx0ZXJhX2VtaWZfZWNjX2NvcmU=" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_DISPLAY_NAME "RU1JRiBFcnJvciBDb3JyZWN0aW9uIENvZGUgKEVDQykgQ29tcG9uZW50" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_VERSION "MTkuMQ==" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZSBFcnJvciBDb3JyZWN0aW9uIENvZGUgKEVDQykgQ29tcG9uZW50" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJzL0ludGVybmFsIENvbXBvbmVudHM=" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9zdXBwb3J0L2xpdGVyYXR1cmUvbGl0LWV4dGVybmFsLW1lbW9yeS1pbnRlcmZhY2UuaHRtbA==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_NAME "ZWRfc3ludGhfZW1pZl9mbV8wX2FsdGVyYV9lbWlmX2VjY18xOTFfejVseHpqcQ==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_DISPLAY_NAME "RU1JRiBFcnJvciBDb3JyZWN0aW9uIENvZGUgKEVDQykgQ29tcG9uZW50" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_VERSION "MTkuMQ==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZSBFcnJvciBDb3JyZWN0aW9uIENvZGUgKEVDQykgQ29tcG9uZW50" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJzL0ludGVybmFsIENvbXBvbmVudHM=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9zdXBwb3J0L2xpdGVyYXR1cmUvbGl0LWV4dGVybmFsLW1lbW9yeS1pbnRlcmZhY2UuaHRtbA==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_NAME "ZWRfc3ludGhfZW1pZl9mbV8wX2FsdGVyYV9lbWlmX2ZtXzI3NF8yYmJpYXlx" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_DISPLAY_NAME "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgKEVNSUYpIElQ" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_VERSION "Mi43LjQ=" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_DESCRIPTION "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgSW50ZWwgRlBHQSBJUA==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJz" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9zdXBwb3J0L2xpdGVyYXR1cmUvbGl0LWV4dGVybmFsLW1lbW9yeS1pbnRlcmZhY2UuaHRtbA==" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL3Byb2R1Y3RzLw==" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_COMPONENT_NAME "ZWRfc3ludGhfZW1pZl9mbV8w" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "ed_synth_emif_fm_0" -library "ed_synth_emif_fm_0" -name IP_COMPONENT_VERSION "MS4w" + +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to "pll_ref_clk" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "DIFFERENTIAL" -to "pll_ref_clk" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V" -to "oct_rzqin" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V SSTL" -to "mem_ck[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_ck[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_ck[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_ck[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V SSTL" -to "mem_ck_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_ck_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_ck_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_ck_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_a[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_a[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_a[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_a[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_act_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_act_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_act_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_act_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_ba[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_ba[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_ba[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_ba[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_ba[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_ba[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_ba[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_ba[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_bg[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_bg[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_bg[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_bg[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_bg[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_bg[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_bg[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_bg[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_cke[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_cke[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_cke[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_cke[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_cs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_cs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_cs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_cs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_odt[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_odt[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_odt[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_odt[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V" -to "mem_reset_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_reset_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "SSTL-12" -to "mem_par[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_par[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_par[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "OFF" -to "mem_par[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V" -to "mem_alert_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dqs[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "Differential 1.2-V POD" -to "mem_dqs_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dqs_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dqs_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dqs_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dqs_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[9]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[10]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[11]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[12]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[13]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[14]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[15]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[16]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[17]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[18]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[19]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[20]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[21]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[22]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[23]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[24]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[25]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[26]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[27]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[28]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[29]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[30]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[31]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[32]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[33]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[34]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[35]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[36]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[37]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[38]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[39]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[40]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[41]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[42]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[43]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[44]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[45]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[46]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[47]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[48]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[49]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[50]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[51]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[52]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[53]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[54]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[55]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[56]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[57]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[58]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[59]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[60]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[61]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[62]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[63]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[64]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[65]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[66]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[67]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[68]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[69]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[70]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dq[71]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[0]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[1]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[2]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[3]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[4]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[5]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[6]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[7]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IO_STANDARD "1.2-V POD" -to "mem_dbi_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_dbi_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name INPUT_TERMINATION "PARALLEL 60 OHM WITH CALIBRATION" -to "mem_dbi_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SLEW_RATE "2" -to "mem_dbi_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PROGRAMMABLE_DEEMPHASIS "HIGH_LP" -to "mem_dbi_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name PACKAGE_SKEW_COMPENSATION ON -to "mem_dbi_n[8]" +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name VREF_MODE "DDR4_CAL_RANGE2" -to "mem_dbi_n[8]" +set_instance_assignment -entity "fmiohmc_fifo" -library "altera_emif_ecc_fm_191" -name MESSAGE_DISABLE 14320 +set_instance_assignment -entity "fmiohmc_ecc" -library "altera_emif_ecc_fm_191" -name MESSAGE_DISABLE 10036 + +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_top.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_bufs.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufis.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_ufi_wrapper.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_i.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_se_o.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_i.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_df_o.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_udir_cp_i.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_df.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_bdir_se.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_buf_unused.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_cal_counter.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_fast_sim.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_pll_extra_clks.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_oct.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_core_clks_rsts.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hps_clks_rsts.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_local_reset.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles_wrap.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_tiles.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_io_lane_remap.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_avl_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_sideband_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_mmr_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_amm_data_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_phylite_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_hmc_ast_data_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_afi_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_seq_if.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_emif_arch_fm_regs.sv"] +set_global_assignment -library "altera_emif_arch_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/altera_std_synchronizer_nocut.v"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.dat"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_spice_files.zip"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_ip_parameters.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_utils.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_parameters.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_pin_map.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_io_timing.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_report_timing_core.tcl"] +set_instance_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy.sdc"] -no_sdc_promotion -no_auto_inst_discovery +set_global_assignment -library "altera_emif_arch_fm_191" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.hex"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_synth.txt"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_seq_params_sim.txt"] +set_global_assignment -library "altera_emif_arch_fm_191" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_arch_fm_191/synth/ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy_readme.txt"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/altera_emif_ecc_core.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/altera_emif_preload_ecc_encoder.sv"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_amm2ast.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_cb.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_112.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_altecc_decoder.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_decoder_64_decode.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_112.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_encoder_64_altecc_encoder.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_interface_fifo.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_mmr.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_pcm_112.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_sv_112.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_ecc_wrapper.v"] +set_global_assignment -library "altera_emif_ecc_fm_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_fm_191/synth/fmiohmc_fifo.v"] +set_global_assignment -library "altera_emif_ecc_191" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_ecc_191/synth/ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq.v"] +set_global_assignment -library "altera_emif_fm_274" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_fm_274/synth/ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq.v"] +set_global_assignment -library "ed_synth_emif_fm_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/ed_synth_emif_fm_0.v"] + + +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_TOOL_NAME "altera_emif_fm" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_TOOL_VERSION "2.7.4" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" -library "altera_emif_fm_274" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_TOOL_NAME "altera_emif_ecc" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" -library "altera_emif_ecc_191" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_TOOL_NAME "altera_emif_ecc_fm" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "altera_emif_ecc_core" -library "altera_emif_ecc_fm_191" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_TOOL_NAME "altera_emif_arch_fm" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" -library "altera_emif_arch_fm_191" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.sopcinfo b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.sopcinfo new file mode 100644 index 0000000000..e01f3e7b97 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.sopcinfo @@ -0,0 +1,75083 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + pll_ref_clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + pll_ref_clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + pll_ref_clk + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + emif_calbus_clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + emif_calbus_clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + emif_calbus_clk + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + EXTENDED + false + true + false + true + PART_TRAIT + DEVICE_TEMPERATURE_GRADE + + + java.lang.String + STANDARD_POWER + false + true + false + true + PART_TRAIT + DEVICE_POWER_MODEL + + + [Ljava.lang.String; + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + false + true + false + true + DEVICE_DIE_REVISIONS + + + java.lang.String + FAMILY_AGILEX + true + true + false + true + + + java.lang.String + 1 + false + true + false + true + PART_TRAIT + SUPPORTS_VID + + + java.lang.String + IO96A_REVB2 + false + true + false + true + PART_TRAIT + DEVICE_IOBANK_REVISION + + + java.lang.String + PROTOCOL_DDR4 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + cal_debug_clk_clock_sink + + + java.lang.String + ed_synth_emif_fm_0_emif_fm_0 + false + true + false + true + UNIQUE_ID + + + java.lang.String + PROTOCOL_DDR4 + true + true + false + true + + + java.lang.String + E2V (ES3) - change device under 'View'->'Device Family' + true + true + true + true + + + java.lang.String + E2V + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + RATE_QUARTER + true + true + false + true + + + double + 1200.0 + true + true + false + true + + + double + 33.333 + true + true + false + true + + + double + 10.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 240 + true + true + true + true + + + boolean + false + true + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + true + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + true + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + true + true + false + true + + + java.lang.String + IO_STD_POD_12 + true + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + true + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + true + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + true + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + true + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_HIGH + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 1200.0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 1200.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 1200.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 1200.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 1200.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 1200.0 + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 33.333 + false + true + true + true + + + double + 10.0 + false + true + true + true + + + java.lang.String + RATE_QUARTER + false + true + true + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + double + 33.333 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + true + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + true + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + true + true + + + java.lang.String + unset + false + true + true + true + + + java.lang.String + unset + false + true + true + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + true + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + true + true + + + java.lang.String + unset + false + true + true + true + + + java.lang.String + unset + false + true + true + true + + + java.lang.String + IO_STD_POD_12 + false + true + true + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + true + true + + + java.lang.String + unset + false + true + true + true + + + java.lang.String + unset + false + true + true + true + + + java.lang.String + IN_OCT_60_CAL + false + true + true + true + + + boolean + true + false + true + true + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + IO_STD_TRUE_DIFF_SIGNALING + false + true + true + true + + + java.lang.String + IO_STD_CMOS_12 + false + true + true + true + + + java.lang.String + IO_STD_SSTL_12 + true + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + true + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + true + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + true + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + true + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + true + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + true + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + true + true + false + true + + + java.lang.String + IO_STD_POD_12 + true + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + true + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + true + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_HIGH + true + true + false + true + + + java.lang.String + IN_OCT_60_CAL + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 68.0 + true + true + true + true + + + java.lang.String + IO_STD_TRUE_DIFF_SIGNALING + true + true + false + true + + + java.lang.String + IO_STD_CMOS_12 + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 633.333 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_HALF + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 533.333 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_HALF + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.8 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + CONFIG_PHY_ONLY + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 800.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + boolean + true + true + true + false + true + + + double + 70.0 + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + unset + true + true + false + true + + + java.lang.String + MEM_FORMAT_RDIMM + true + true + false + true + + + double + 23.0 + true + true + false + true + + + int + 18 + true + true + false + true + + + int + 8 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 72 + true + true + false + true + + + int + 9 + true + true + false + true + + + int + 9 + true + true + false + true + + + java.lang.String + MEM_FORMAT_UDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 15 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + 0000000000000000 + false + true + false + true + + + java.lang.String + 000000000000000000 + false + true + false + true + + + java.lang.String + DDR3_ALERT_N_PLACEMENT_AC_LANES + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 72 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + DDR3_BL_BL8 + false + true + false + true + + + java.lang.String + DDR3_BT_SEQUENTIAL + false + true + false + true + + + java.lang.String + DDR3_ASR_MANUAL + false + true + false + true + + + java.lang.String + DDR3_SRT_NORMAL + false + true + false + true + + + java.lang.String + DDR3_PD_OFF + false + true + false + true + + + java.lang.String + DDR3_DRV_STR_RZQ_7 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR3_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR3_RTT_WR_RZQ_4 + false + true + false + true + + + int + 10 + false + true + false + true + + + java.lang.String + DDR3_ATCL_DISABLED + false + true + false + true + + + int + 14 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + false + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + false + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + false + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + false + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + false + true + + + [Ljava.lang.String; + off,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + [Ljava.lang.String; + ,, + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + DDR3_SPEEDBIN_2133 + false + true + false + true + + + int + 60 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 95 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 53 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 55 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 180 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 125.0 + false + true + false + true + + + double + 125.0 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 33.0 + false + true + false + true + + + double + 13.09 + false + true + false + true + + + double + 13.09 + false + true + false + true + + + double + 7.8 + false + true + false + true + + + double + 160.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 8 + false + true + false + true + + + double + 25.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 499 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 900 + true + true + false + true + + + int + 1200 + true + true + false + true + + + int + 36 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 14 + true + true + false + true + + + int + 171 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 27 + true + true + false + true + + + int + 8320 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + MEM_FORMAT_RDIMM + false + true + true + true + + + int + 72 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 2 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + java.lang.String + DDR4_BL_BL8 + false + true + false + true + + + java.lang.String + DDR4_BT_SEQUENTIAL + false + true + false + true + + + int + 21 + false + true + true + true + + + java.lang.String + DDR4_RTT_NOM_RZQ_4 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_ATCL_DISABLED + false + true + true + true + + + java.lang.String + DDR4_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDR4_ASR_MANUAL_NORMAL + false + true + false + true + + + java.lang.String + DDR4_RTT_WR_ODT_DISABLED + false + true + false + true + + + int + 16 + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_GEARDOWN_HR + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_FINE_REFRESH_FIXED_1X + false + true + true + true + + + java.lang.String + DDR4_MPR_READ_FORMAT_SERIAL + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + DDR4_AC_PARITY_LATENCY_DISABLE + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_RTT_PARK_ODT_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + double + 56.0 + false + true + false + true + + + java.lang.String + DDR4_VREFDQ_TRAINING_RANGE_1 + false + true + false + true + + + java.lang.String + DDR4_RCD_CA_IBT_100 + false + true + true + true + + + java.lang.String + DDR4_RCD_CS_IBT_100 + false + true + true + true + + + java.lang.String + DDR4_RCD_CKE_IBT_100 + false + true + true + true + + + java.lang.String + DDR4_RCD_ODT_IBT_100 + false + true + true + true + + + java.lang.String + DDR4_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_WR_RZQ_3 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_DRV_STR_RZQ_7 + false + true + false + true + + + int + 101 + false + true + true + true + + + int + 5 + false + true + true + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 37 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 20 + false + true + false + true + + + int + 39 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 240 + false + true + false + true + + + int + 9 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 17 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 68.0 + true + true + false + true + + + double + 70.0 + true + true + false + true + + + double + 70.0 + true + true + true + true + + + java.lang.String + DDR4_VREFDQ_TRAINING_RANGE_0 + true + true + false + true + + + java.lang.String + Range 1 - 60% to 92.5% + true + true + true + true + + + java.lang.String + DDR4_DRV_STR_RZQ_7 + true + true + false + true + + + java.lang.String + DDR4_RTT_WR_ODT_DISABLED + true + true + false + true + + + java.lang.String + DDR4_RTT_NOM_ODT_DISABLED + true + true + false + true + + + java.lang.String + DDR4_RTT_PARK_RZQ_4 + true + true + false + true + + + java.lang.String + RZQ/7 (34 Ohm) + true + true + true + true + + + java.lang.String + Dynamic ODT off + true + true + true + true + + + java.lang.String + ODT Disabled + true + true + true + true + + + java.lang.String + RZQ/4 (60 Ohm) + true + true + true + true + + + java.lang.String + DDR4_DB_RTT_NOM_ODT_DISABLED + true + true + false + true + + + java.lang.String + DDR4_DB_RTT_WR_RZQ_3 + true + true + false + true + + + java.lang.String + DDR4_DB_RTT_PARK_ODT_DISABLED + true + true + false + true + + + java.lang.String + DDR4_DB_DRV_STR_RZQ_7 + true + true + false + true + + + java.lang.String + RTT_NOM disabled + true + true + false + true + + + java.lang.String + RZQ/3 (80 Ohm) + true + true + false + true + + + java.lang.String + RTT_PARK disabled + true + true + false + true + + + java.lang.String + RZQ/7 (34 Ohm) + true + true + false + true + + + int + 9 + true + true + false + true + + + int + 72 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 17 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 2164 + true + true + false + true + + + int + 65537 + true + true + false + true + + + int + 131112 + true + true + false + true + + + int + 197632 + true + true + false + true + + + int + 264192 + true + true + false + true + + + int + 332896 + true + true + false + true + + + int + 395279 + true + true + false + true + + + java.lang.String + 00000020000000003900000D40030B0F556000 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 13 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + true + false + true + true + true + + + [Ljava.lang.String; + Rank 0 + false + false + true + true + + + [Ljava.lang.String; + off + false + true + true + true + + + [Ljava.lang.String; + Rank 0 + false + false + true + true + + + [Ljava.lang.String; + on + false + true + true + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + false + true + true + + + [Ljava.lang.String; + off,off + false + true + true + true + + + [Ljava.lang.String; + off,off + false + true + true + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + false + true + true + + + [Ljava.lang.String; + on,off + false + true + true + true + + + [Ljava.lang.String; + off,on + false + true + true + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + true + true + + + [Ljava.lang.String; + off,off,on,on + false + true + true + true + + + [Ljava.lang.String; + on,on,off,off + false + true + true + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + true + true + + + [Ljava.lang.String; + off,off,on,on + false + true + true + true + + + [Ljava.lang.String; + on,on,off,off + false + true + true + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + true + true + + + [Ljava.lang.String; + off,off,on,off + false + true + true + true + + + [Ljava.lang.String; + off,off,off,on + false + true + true + true + + + [Ljava.lang.String; + on,off,off,off + false + true + true + true + + + [Ljava.lang.String; + off,on,off,off + false + true + true + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + false + true + true + + + [Ljava.lang.String; + on,off,on,off + false + true + true + true + + + [Ljava.lang.String; + off,on,off,on + false + true + true + true + + + [Ljava.lang.String; + on,off,on,off + false + true + true + true + + + [Ljava.lang.String; + off,on,off,on + false + true + true + true + + + [Ljava.lang.String; + Rank 0,-,-,- + true + true + true + true + + + [Ljava.lang.String; + (Drive) RZQ/7 (34 Ohm),-,-,- + true + true + true + true + + + [Ljava.lang.String; + -,-,-,- + true + true + true + true + + + [Ljava.lang.String; + -,-,-,- + true + true + true + true + + + [Ljava.lang.String; + -,-,-,- + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + [Ljava.lang.String; + Rank 0,-,-,- + true + true + true + true + + + [Ljava.lang.String; + (Park) RZQ/4 (60 Ohm),-,-,- + true + true + true + true + + + [Ljava.lang.String; + -,-,-,- + true + true + true + true + + + [Ljava.lang.String; + -,-,-,- + true + true + true + true + + + [Ljava.lang.String; + -,-,-,- + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + DDR4_SPEEDBIN_2666 + false + true + true + true + + + int + 62 + false + true + true + true + + + int + 100 + false + true + true + true + + + int + 87 + false + true + true + true + + + int + 75 + false + true + true + true + + + double + 0.2 + false + true + true + true + + + int + 130 + false + true + true + true + + + double + 0.14 + false + true + true + true + + + double + 0.74 + false + true + true + true + + + double + 0.72 + false + true + true + true + + + int + 175 + false + true + true + true + + + double + 0.27 + false + true + true + true + + + double + 0.4 + false + true + true + true + + + double + 0.18 + false + true + true + true + + + double + 0.18 + false + true + true + true + + + double + 0.13 + false + true + true + true + + + double + 0.13 + false + true + true + true + + + int + 500 + false + true + true + true + + + int + 8 + false + true + true + true + + + double + 32.0 + false + true + true + true + + + double + 14.16 + false + true + true + true + + + double + 14.16 + false + true + true + true + + + double + 7.8 + false + true + true + true + + + double + 350.0 + false + true + true + true + + + double + 15.0 + false + true + true + true + + + int + 9 + false + true + true + true + + + int + 3 + false + true + true + true + + + double + 21.0 + false + true + true + true + + + int + 6 + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 6 + false + true + true + true + + + int + 4 + false + true + true + true + + + double + 90.0 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 0.1 + false + true + false + true + + + int + 66 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 600000 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 450 + true + true + false + true + + + int + 900 + true + true + false + true + + + int + 1200 + true + true + false + true + + + int + 39 + true + true + false + true + + + int + 17 + true + true + false + true + + + int + 17 + true + true + false + true + + + int + 420 + true + true + false + true + + + int + 18 + true + true + false + true + + + int + 9 + true + true + false + true + + + int + 26 + true + true + false + true + + + int + 9360 + true + true + false + true + + + int + 6 + true + true + false + true + + + int + 108 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 19 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 4 + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 36 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + QDR2_SPEEDBIN_633 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 0.23 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.23 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.09 + false + true + false + true + + + double + -0.09 + false + true + false + true + + + double + 0.08 + false + true + false + true + + + double + 0.71 + false + true + false + true + + + double + 0.45 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 21 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_OUTPUT_DRIVE_25_PCT + false + true + false + true + + + java.lang.String + QDR4_OUTPUT_DRIVE_25_PCT + false + true + false + true + + + java.lang.String + MEM_XP + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 18 + true + true + false + true + + + int + 18 + true + true + false + true + + + int + 72 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 36 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + QDR4_SPEEDBIN_2133 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + -150 + false + true + false + true + + + int + 225 + false + true + false + true + + + int + 170 + false + true + false + true + + + int + 170 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 4 + false + true + false + true + + + java.lang.String + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + false + true + false + true + + + java.lang.String + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + false + true + false + true + + + java.lang.String + RLD2_ODT_ON + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 9 + true + true + false + true + + + int + 9 + true + true + false + true + + + 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+ + int + 109 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 5.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.5 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + false + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 8.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.15 + true + true + false + true + + + double + 0.15 + true + true + false + true + + + double + 0.06 + true + true + false + true + + + double + 0.12 + true + true + false + true + + + double + 0.13 + true + true + false + true + + + double + 0.02 + true + true + false + true + + + double + 0.18 + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + -0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 5.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.5 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 7.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 3.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + -0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 7.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 3.5 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 8.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 4.0 + true + true + false + true + + + double + 2.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 10 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + false + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 9 + true + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 9 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 11 + true + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + java.lang.String + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 128 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + POSTED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + COARSE + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + true + true + false + true + + + int + 512 + true + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + FAST_SIM_OVERRIDE_DEFAULT + false + true + false + true + + + java.lang.String + avl + false + true + false + true + + + java.lang.String + avl_release + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SOFT_NIOS_MODE_DISABLED + false + true + false + true + + + int + 100 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 57600 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + java.lang.String + auto + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + true + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_JTAG + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 5 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + SHORT + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + true + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_JTAG + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + true + true + + + boolean + true + false + false + true + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + false + true + true + + + java.lang.String + SHORT + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_JTAG + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + true + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + true + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + true + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + local_reset_req + Input + 1 + local_reset_req + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + local_reset_done + Output + 1 + local_reset_done + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + false + + pll_ref_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + pll_locked + Output + 1 + pll_locked + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + oct_rzqin + Input + 1 + oct_rzqin + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + mem_ck + Output + 1 + mem_ck + + + mem_ck_n + Output + 1 + mem_ck_n + + + mem_a + Output + 17 + mem_a + + + mem_act_n + Output + 1 + mem_act_n + + + mem_ba + Output + 2 + mem_ba + + + mem_bg + Output + 2 + mem_bg + + + mem_cke + Output + 1 + mem_cke + + + mem_cs_n + Output + 1 + mem_cs_n + + + mem_odt + Output + 1 + mem_odt + + + mem_reset_n + Output + 1 + mem_reset_n + + + mem_par + Output + 1 + mem_par + + + mem_alert_n + Input + 1 + mem_alert_n + + + mem_dqs + Bidir + 9 + mem_dqs + + + mem_dqs_n + Bidir + 9 + mem_dqs_n + + + mem_dq + Bidir + 72 + mem_dq + + + mem_dbi_n + Bidir + 9 + mem_dbi_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + local_cal_success + Output + 1 + local_cal_success + + + local_cal_fail + Output + 1 + local_cal_fail + + + + + + java.lang.String + emif_calbus_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + calbus_read + Input + 1 + calbus_read + + + calbus_write + Input + 1 + calbus_write + + + calbus_address + Input + 20 + calbus_address + + + calbus_wdata + Input + 32 + calbus_wdata + + + calbus_rdata + Output + 32 + calbus_rdata + + + calbus_seq_param_tbl + Output + 4096 + calbus_seq_param_tbl + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + false + + calbus_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + true + + emif_usr_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + emif_usr_clk + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + ctrl_ecc_user_interrupt_0 + Output + 1 + ctrl_ecc_user_interrupt + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + true + true + + + java.math.BigInteger + 8589934592 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + emif_usr_clk + false + true + true + true + + + java.lang.String + emif_usr_reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 64 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.math.BigInteger + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 35 + false + true + true + true + + + java.lang.Integer + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + 8589934592 + false + + amm_ready_0 + Output + 1 + waitrequest_n + + + amm_read_0 + Input + 1 + read + + + amm_write_0 + Input + 1 + write + + + amm_address_0 + Input + 27 + address + + + amm_readdata_0 + Output + 512 + readdata + + + amm_writedata_0 + Input + 512 + writedata + + + amm_burstcount_0 + Input + 7 + burstcount + + + amm_byteenable_0 + Input + 64 + byteenable + + + amm_readdatavalid_0 + Output + 1 + readdatavalid + + + + + + + java.lang.String + Agilex 7 + false + true + false + true + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + + + java.lang.String + 2 + false + true + false + true + + + java.lang.String + EXTENDED + false + true + false + true + + + java.lang.String + STANDARD_POWER + false + true + false + true + + + [Ljava.lang.String; + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + false + true + false + true + + + java.lang.String + FAMILY_AGILEX + false + true + false + true + + + java.lang.String + 1 + false + true + false + true + + + java.lang.String + IO96A_REVB2 + false + true + false + true + + + java.lang.String + PROTOCOL_DDR4 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 50000000 + false + true + false + true + + + java.lang.String + ed_synth_emif_fm_0_emif_fm_0 + false + true + false + true + + + java.lang.String + PROTOCOL_DDR4 + false + true + false + true + + + java.lang.String + E2V (ES3) - change device under 'View'->'Device Family' + false + true + false + true + + + java.lang.String + E2V + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 33.333 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 240 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + IO_STD_POD_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_HIGH + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 33.333 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 33.333 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + IO_STD_POD_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + IN_OCT_60_CAL + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + IO_STD_TRUE_DIFF_SIGNALING + false + true + false + true + + + java.lang.String + IO_STD_CMOS_12 + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + IO_STD_POD_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_HIGH + false + true + false + true + + + java.lang.String + IN_OCT_60_CAL + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 68.0 + false + true + false + true + + + java.lang.String + IO_STD_TRUE_DIFF_SIGNALING + false + true + false + true + + + java.lang.String + IO_STD_CMOS_12 + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 633.333 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_HALF + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 533.333 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_HALF + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.8 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_ONLY + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 800.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + MEM_FORMAT_RDIMM + false + true + false + true + + + double + 23.0 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 9 + false + true + false + true + + + java.lang.String + MEM_FORMAT_UDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 15 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + 0000000000000000 + false + true + false + true + + + java.lang.String + 000000000000000000 + false + true + false + true + + + java.lang.String + DDR3_ALERT_N_PLACEMENT_AC_LANES + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDR3_BL_BL8 + false + true + false + true + + + java.lang.String + DDR3_BT_SEQUENTIAL + false + true + false + true + + + java.lang.String + DDR3_ASR_MANUAL + false + true + false + true + + + java.lang.String + DDR3_SRT_NORMAL + false + true + false + true + + + java.lang.String + DDR3_PD_OFF + false + true + false + true + + + java.lang.String + DDR3_DRV_STR_RZQ_7 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR3_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR3_RTT_WR_RZQ_4 + false + true + false + true + + + int + 10 + false + true + false + true + + + java.lang.String + DDR3_ATCL_DISABLED + false + true + false + true + + + int + 14 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDR3_SPEEDBIN_2133 + false + true + false + true + + + int + 60 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 95 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 53 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 55 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 180 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 125.0 + false + true + false + true + + + double + 125.0 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 33.0 + false + true + false + true + + + double + 13.09 + false + true + false + true + + + double + 13.09 + false + true + false + true + + + double + 7.8 + false + true + false + true + + + double + 160.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 8 + false + true + false + true + + + double + 25.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 499 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 14 + false + true + false + true + + + int + 14 + false + true + false + true + + + int + 171 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 27 + false + true + false + true + + + int + 8320 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + MEM_FORMAT_RDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_BL_BL8 + false + true + false + true + + + java.lang.String + DDR4_BT_SEQUENTIAL + false + true + false + true + + + int + 21 + false + true + false + true + + + java.lang.String + DDR4_RTT_NOM_RZQ_4 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_ATCL_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDR4_ASR_MANUAL_NORMAL + false + true + false + true + + + java.lang.String + DDR4_RTT_WR_ODT_DISABLED + false + true + false + true + + + int + 16 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_GEARDOWN_HR + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_FINE_REFRESH_FIXED_1X + false + true + false + true + + + java.lang.String + DDR4_MPR_READ_FORMAT_SERIAL + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + DDR4_AC_PARITY_LATENCY_DISABLE + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_RTT_PARK_ODT_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 56.0 + false + true + false + true + + + java.lang.String + DDR4_VREFDQ_TRAINING_RANGE_1 + false + true + false + true + + + java.lang.String + DDR4_RCD_CA_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_RCD_CS_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_RCD_CKE_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_RCD_ODT_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_WR_RZQ_3 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_DRV_STR_RZQ_7 + false + true + false + true + + + int + 101 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 37 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 20 + false + true + false + true + + + int + 39 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 240 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + double + 68.0 + false + true + false + true + + + double + 70.0 + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + DDR4_VREFDQ_TRAINING_RANGE_0 + false + true + false + true + + + java.lang.String + Range 1 - 60% to 92.5% + false + true + false + true + + + java.lang.String + DDR4_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDR4_RTT_WR_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_RTT_PARK_RZQ_4 + false + true + false + true + + + java.lang.String + RZQ/7 (34 Ohm) + false + true + false + true + + + java.lang.String + Dynamic ODT off + false + true + false + true + + + java.lang.String + ODT Disabled + false + true + false + true + + + java.lang.String + RZQ/4 (60 Ohm) + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_WR_RZQ_3 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + RTT_NOM disabled + false + true + false + true + + + java.lang.String + RZQ/3 (80 Ohm) + false + true + false + true + + + java.lang.String + RTT_PARK disabled + false + true + false + true + + + java.lang.String + RZQ/7 (34 Ohm) + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2164 + false + true + false + true + + + int + 65537 + false + true + false + true + + + int + 131112 + false + true + false + true + + + int + 197632 + false + true + false + true + + + int + 264192 + false + true + false + true + + + int + 332896 + false + true + false + true + + + int + 395279 + false + true + false + true + + + java.lang.String + 00000020000000003900000D40030B0F556000 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 13 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,-,-,- + false + true + false + true + + + [Ljava.lang.String; + (Drive) RZQ/7 (34 Ohm),-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + Rank 0,-,-,- + false + true + false + true + + + [Ljava.lang.String; + (Park) RZQ/4 (60 Ohm),-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDR4_SPEEDBIN_2666 + false + true + false + true + + + int + 62 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 87 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + int + 130 + false + true + false + true + + + double + 0.14 + false + true + false + true + + + double + 0.74 + false + true + false + true + + + double + 0.72 + false + true + false + true + + + int + 175 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 8 + false + true + false + true + + + double + 32.0 + false + true + false + true + + + double + 14.16 + false + true + false + true + + + double + 14.16 + false + true + false + true + + + double + 7.8 + false + true + false + true + + + double + 350.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 3 + false + true + false + true + + + double + 21.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 90.0 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 0.1 + false + true + false + true + + + int + 66 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 600000 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + int + 39 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 420 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 26 + false + true + false + true + + + int + 9360 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 108 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 19 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 4 + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + QDR2_SPEEDBIN_633 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 0.23 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.23 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.09 + false + true + false + true + + + double + -0.09 + false + true + false + true + + + double + 0.08 + false + true + false + true + + + double + 0.71 + false + true + false + true + + + double + 0.45 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 21 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_OUTPUT_DRIVE_25_PCT + false + true + false + true + + + java.lang.String + QDR4_OUTPUT_DRIVE_25_PCT + false + true + false + true + + + java.lang.String + MEM_XP + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + QDR4_SPEEDBIN_2133 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + -150 + false + true + false + true + + + int + 225 + false + true + false + true + + + int + 170 + false + true + false + true + + + int + 170 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 4 + false + true + false + true + + + java.lang.String + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + false + true + false + true + + + java.lang.String + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + false + true + false + true + + + java.lang.String + RLD2_ODT_ON + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + RLD2_SPEEDBIN_18 + false + true + false + true + + + double + 0.24 + false + true + false + true + + + double + 0.45 + false + true + false + true + + + double + 0.9 + false + true + false + true + + + double + 0.3 + false + true + false + true + + + double + 0.3 + false + true + false + true + + + double + 0.17 + false + true + false + true + + + double + 0.17 + false + true + false + true + + + double + 0.12 + false + true + false + true + + + double + -0.12 + false + true + false + true + + + double + 0.3 + false + true + false + true + + + double + -0.3 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 20 + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 2 + false + true + false + true + + + java.lang.String + RLD3_DL_RL16_WL17 + false + true + false + true + + + java.lang.String + RLD3_TRC_9 + false + true + false + true + + + java.lang.String + RLD3_OUTPUT_DRIVE_40 + false + true + false + true + + + java.lang.String + RLD3_ODT_40 + false + true + false + true + + + java.lang.String + RLD3_AREF_BAC + false + true + false + true + + + java.lang.String + RLD3_WRITE_1BANK + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + RLD3_SPEEDBIN_093E + false + true + false + true + + + int + -30 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + -0.27 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 85 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 65 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 32 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 15 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 8 + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + LPDDR3_BL_BL8 + false + true + false + true + + + java.lang.String + LPDDR3_DL_RL12_WL6 + false + true + false + true + + + java.lang.String + LPDDR3_DRV_STR_40D_40U + false + true + false + true + + + java.lang.String + LPDDR3_DQODT_DISABLE + false + true + false + true + + + java.lang.String + LPDDR3_PDODT_DISABLED + false + true + false + true + + + java.lang.String + Set A + false + true + false + true + + + java.lang.String + LPDDR3_NWR_NWR12 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,on + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,on,on,on + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + LPDDR3_SPEEDBIN_1600 + false + true + false + true + + + int + 75 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 135 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 614 + false + true + false + true + + + double + 1.25 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + double + 175.0 + false + true + false + true + + + double + 175.0 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 10 + false + true + false + true + + + double + 42.5 + false + true + false + true + + + double + 18.0 + false + true + false + true + + + double + 18.0 + false + true + false + true + + + double + 3.9 + false + true + false + true + + + double + 210.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 499 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 220 + false + true + false + true + + + int + 511 + false + true + false + true + + + int + 5500 + false + true + false + true + + + int + 34 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 168 + false + true + false + true + + + int + 12 + false + true + false + true + + + int + 40 + false + true + false + true + + + int + 3120 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 6 + false + true + false + true + + + java.lang.String + MEM_FORMAT_LRDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_ALERT_N_PLACEMENT_AUTO + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_PWR_MODE_12W + false + true + false + true + + + java.lang.String + DDRT_BL_BL8 + false + true + false + true + + + java.lang.String + DDRT_BT_SEQUENTIAL + false + true + false + true + + + int + 15 + false + true + false + true + + + java.lang.String + DDRT_RTT_NOM_RZQ_4 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_ATCL_DISABLED + false + true + false + true + + + java.lang.String + DDRT_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDRT_ASR_MANUAL_NORMAL + false + true + false + true + + + java.lang.String + DDRT_RTT_WR_ODT_DISABLED + false + true + false + true + + + int + 18 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_GEARDOWN_HR + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_FINE_REFRESH_FIXED_1X + false + true + false + true + + + java.lang.String + DDRT_MPR_READ_FORMAT_SERIAL + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + DDRT_AC_PARITY_LATENCY_DISABLE + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_RTT_PARK_ODT_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 56.0 + false + true + false + true + + + java.lang.String + DDRT_VREFDQ_TRAINING_RANGE_1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 6 + false + true + false + true + + + java.lang.String + DDRT_RCD_CA_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_RCD_CS_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_RCD_CKE_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_RCD_ODT_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDRT_DB_RTT_WR_RZQ_4 + false + true + false + true + + + java.lang.String + DDRT_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDRT_DB_DRV_STR_RZQ_7 + false + true + false + true + + + int + 85 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 25 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 20 + false + true + false + true + + + int + 39 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 240 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + double + 56.0 + false + true + false + true + + + java.lang.String + DDRT_VREFDQ_TRAINING_RANGE_1 + false + true + false + true + + + java.lang.String + Range 2 - 45% to 77.5% + false + true + false + true + + + int + 2 + false + true + false + true + + + int + -1 + false + true + false + true + + + int + -1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDRT_SPEEDBIN_2400 + false + true + false + true + + + int + 60 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 95 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + int + 136 + false + true + false + true + + + double + 0.16 + false + true + false + true + + + double + 0.76 + false + true + false + true + + + double + 0.72 + false + true + false + true + + + int + 165 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 8 + false + true + false + true + + + double + 32.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + double + 7.8 + false + true + false + true + + + double + 260.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 3 + false + true + false + true + + + double + 21.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 90.0 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 0.1 + false + true + false + true + + + int + 66 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 499 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 14 + false + true + false + true + + + int + 14 + false + true + false + true + + + int + 171 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 27 + false + true + false + true + + + int + 8320 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 109 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.15 + false + true + false + true + + + double + 0.15 + false + true + false + true + + + double + 0.06 + false + true + false + true + + + double + 0.12 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + -0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 7.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 3.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + -0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 7.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 3.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 2 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 9 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 11 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + java.lang.String + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 128 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + POSTED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + COARSE + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 512 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + FAST_SIM_OVERRIDE_DEFAULT + false + true + false + true + + + java.lang.String + avl + false + true + false + true + + + java.lang.String + avl_release + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SOFT_NIOS_MODE_DISABLED + false + true + false + true + + + int + 100 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 57600 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + auto + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_JTAG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_JTAG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_JTAG + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + 14nm5 + true + true + true + true + + + boolean + false + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 9 + true + true + true + true + + + int + 20 + true + true + true + true + + + boolean + false + true + true + true + true + + + boolean + true + true + true + true + true + + + java.lang.String + DQS_BUS_MODE_X8_X9 + true + true + true + true + + + java.lang.String + use_0_1_2_3_lane + true + true + true + true + + + int + 1 + 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true + true + + + int + 275876963 + true + true + true + true + + + int + 103911395 + true + true + true + true + + + int + 275876963 + true + true + true + true + + + int + 103911395 + true + true + true + true + + + int + 275876963 + true + true + true + true + + + int + 103911395 + true + true + true + true + + + int + 275876963 + true + true + true + true + + + int + 103911395 + true + true + true + true + + + int + 1073741823 + true + true + true + true + + + int + 1073741823 + true + true + true + true + + + int + 1073741823 + true + true + true + true + + + int + 1073741823 + true + true + true + true + + + int + 1073741823 + true + true + true + true + + + int + 1073741823 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + 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+ int + 3 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 403177984 + true + true + true + true + + + int + 168067584 + true + true + true + true + + + int + 35717208 + true + true + true + true + + + int + 140518930 + true + true + true + true + + + int + 886403 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 10 + true + true + true + true + + + java.lang.String + preamble_one_cycle + true + true + true + true + + + java.lang.String + dbi_wr_dis + true + true + true + true + + + java.lang.String + dbi_rd_ena + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + packed + true + true + true + true + + + int + 3 + true + true + true + true + + + java.lang.String + dqs_diff_in_1_a + true + true + true + true + + + java.lang.String + dqs_constant_b + true + true + true + true + + + int + 52 + true + true + true + true + + + java.lang.String + dll_ctl_dynamic + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + boolean + false + true + true + true + true + + + boolean + false + true + true + true + true + + + boolean + false + true + true + true + true + + + java.lang.String + on + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + java.lang.String + local_p_clk + true + true + true + true + + + boolean + false + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + java.lang.String + pin_ufi_use_in_direct_out_direct + true + true + true + true + + + int + 350 + true + true + true + true + + + int + 350 + true + true + true + true + + + int + 350 + true + true + true + true + + + int + 350 + true + true + true + true + + + int + 350 + true + true + true + true + + + int + 350 + true + true + true + true + + + java.lang.String + pingpong_off + true + true + true + true + + + java.lang.String + cs_width_0 + true + true + true + true + + + java.lang.String + col_width_10 + true + true + true + true + + + java.lang.String + row_width_16 + true + true + true + true + + + java.lang.String + bank_width_2 + true + true + true + true + + + java.lang.String + bank_group_width_2 + true + true + true + true + + + java.lang.String + addr_order_cs_row_ba_col + true + true + true + true + + + java.lang.String + arbiter_type_2t + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + java.lang.String + ctrl_disable + true + true + true + true + + + java.lang.String + dbc0_disable + true + true + true + true + + + java.lang.String + dbc1_disable + true + true + true + true + + + java.lang.String + dbc2_disable + true + true + true + true + + + java.lang.String + dbc3_disable + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + -1 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 33825 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 7 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + int + 8 + true + true + true + true + + + int + 52 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 26 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 15 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 21 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 12 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 28 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 20 + true + true + true + true + + + int + 8 + true + true + true + true + + + int + 4681 + true + true + true + true + + + int + 211 + true + true + true + true + + + int + 16 + true + true + true + true + + + int + 16 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 5 + true + true + true + true + + + int + 768 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 12 + true + true + true + true + + + int + 9 + true + true + true + true + + + int + 9 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 5 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 14 + true + true + true + true + + + int + 5 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 197632 + true + true + true + true + + + int + 264192 + true + true + true + true + + + int + 5216 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 513 + true + true + true + true + + + int + 385 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 28 + true + true + true + true + + + int + 20 + true + true + true + true + + + int + 19 + true + true + true + true + + + int + 17 + true + true + true + true + + + int + 15 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 257 + true + true + true + true + + + int + 127 + true + true + true + true + + + int + 273 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 1 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 1 + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 2 + true + true + true + true + + + java.lang.String + pingpong_off + true + true + true + true + + + java.lang.String + cs_width_0 + true + true + true + true + + + java.lang.String + col_width_10 + true + true + true + true + + + java.lang.String + row_width_16 + true + true + true + true + + + java.lang.String + bank_width_2 + true + true + true + true + + + java.lang.String + bank_group_width_2 + true + true + true + true + + + java.lang.String + addr_order_cs_row_ba_col + true + true + true + true + + + java.lang.String + arbiter_type_2t + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + java.lang.String + ctrl_disable + true + true + true + true + + + java.lang.String + dbc0_disable + true + true + true + true + + + java.lang.String + dbc1_disable + true + true + true + true + + + java.lang.String + dbc2_disable + true + true + true + true + + + java.lang.String + dbc3_disable + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + -1 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 33825 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 7 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + int + 8 + true + true + true + true + + + int + 52 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 26 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 15 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 21 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 12 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 28 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 20 + true + true + true + true + + + int + 8 + true + true + true + true + + + int + 4681 + true + true + true + true + + + int + 211 + true + true + true + true + + + int + 16 + true + true + true + true + + + int + 16 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 5 + true + true + true + true + + + int + 768 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 12 + true + true + true + true + + + int + 9 + true + true + true + true + + + int + 9 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 5 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 14 + true + true + true + true + + + int + 5 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 197632 + true + true + true + true + + + int + 264192 + true + true + true + true + + + int + 5216 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 513 + true + true + true + true + + + int + 385 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 28 + true + true + true + true + + + int + 20 + true + true + true + true + + + int + 19 + true + true + true + true + + + int + 17 + true + true + true + true + + + int + 15 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 257 + true + true + true + true + + + int + 127 + true + true + true + true + + + int + 273 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 1 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + disable + true + true + true + true + + + int + 1 + true + true + true + true + + + java.lang.String + enable + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 12 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 16 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 57345 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 58369 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 0 + true + true + true + true + + + int + 6 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + 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true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 61 + true + true + true + true + + + int + 648 + true + true + true + true + + + int + 576 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 16 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 15 + true + true + true + true + + + int + 13 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 12 + true + true + true + true + + + int + 10 + true + true + true + true + + + int + 32 + true + true + true + true + + + int + 32 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 4096 + true + true + true + true + + + int + 4096 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 9 + true + true + true + true + + + int + 8 + true + true + true + true + + + int + 8 + true + true + true + true + + + int + 4 + true + true + true + true + + + int + 3 + true + true + true + true + + + int + 4 + true + true + true + true + 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18 + true + true + true + true + + + int + 256 + true + true + true + true + + + int + 256 + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + pll_fbclk_mux_1_glb + true + true + true + true + + + java.lang.String + pll_fbclk_mux_2_m_cnt + true + true + true + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + true + true + + + java.lang.String + pll_cp_setting12 + true + true + true + true + + + java.lang.String + pll_bw_res_setting4 + true + true + true + true + + + java.lang.String + high + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + 3336 ps + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + int + 50 + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + 1668 ps + true + true + true + true + + + java.lang.String + 600.0 MHz + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + int + 50 + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true 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true + + + java.lang.String + true + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 2 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + 3336 ps + true + true + true + true + + + java.lang.String + 300.0 MHz + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + int + 50 + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + int + 256 + true + true + true + true + + + int + 256 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + 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true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + java.lang.String + 0.0 MHz + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + int + 50 + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + int + 256 + true + true + true + true + + + int + 256 + true + true + true + true + + + int + 1 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + true + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + java.lang.String + 0.0 MHz + true + true + true + true + + + java.lang.String + 0 ps + true + true + true + true + + + int + 50 + true + true + true + true + + + java.lang.String + false + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + local_reset_req + Input + 1 + local_reset_req + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + local_reset_done + Output + 1 + local_reset_done + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + false + + pll_ref_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + pll_locked + Output + 1 + pll_locked + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + oct_rzqin + Input + 1 + oct_rzqin + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + mem_ck + Output + 1 + mem_ck + + + mem_ck_n + Output + 1 + mem_ck_n + + + mem_a + Output + 17 + mem_a + + + mem_act_n + Output + 1 + mem_act_n + + + mem_ba + Output + 2 + mem_ba + + + mem_bg + Output + 2 + mem_bg + + + mem_cke + Output + 1 + mem_cke + + + mem_cs_n + Output + 1 + mem_cs_n + + + mem_odt + Output + 1 + mem_odt + + + mem_reset_n + Output + 1 + mem_reset_n + + + mem_par + Output + 1 + mem_par + + + mem_alert_n + Input + 1 + mem_alert_n + + + mem_dqs + Bidir + 9 + mem_dqs + + + mem_dqs_n + Bidir + 9 + mem_dqs_n + + + mem_dq + Bidir + 72 + mem_dq + + + mem_dbi_n + Bidir + 9 + mem_dbi_n + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + local_cal_success + Output + 1 + local_cal_success + + + local_cal_fail + Output + 1 + local_cal_fail + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + true + + emif_usr_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + emif_usr_clk + Output + 1 + clk + + + false + emif_fm_0_ecc_core + emif_usr_clk_in + emif_fm_0_ecc_core.emif_usr_clk_in + + + + + + java.lang.String + emif_usr_clk + false + true + false + true + + + java.lang.String + emif_usr_reset_n + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + 0 + false + + ast_cmd_valid_0 + Input + 1 + valid + + + ast_cmd_ready_0 + Output + 1 + ready + + + ast_cmd_data_0 + Input + 61 + data + + + + + + java.lang.String + emif_usr_clk + false + true + false + true + + + java.lang.String + emif_usr_reset_n + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 648 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + 0 + false + + ast_wr_valid_0 + Input + 1 + valid + + + ast_wr_ready_0 + Output + 1 + ready + + + ast_wr_data_0 + Input + 648 + data + + + + + + java.lang.String + emif_usr_clk + false + true + false + true + + + java.lang.String + emif_usr_reset_n + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 576 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + 0 + true + + ast_rd_valid_0 + Output + 1 + valid + + + ast_rd_ready_0 + Input + 1 + ready + + + ast_rd_data_0 + Output + 576 + data + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + ctrl_ecc_write_info_0 + Input + 15 + ctrl_ecc_write_info + + + ctrl_ecc_rdata_id_0 + Output + 13 + ctrl_ecc_rdata_id + + + ctrl_ecc_read_info_0 + Output + 3 + ctrl_ecc_read_info + + + ctrl_ecc_cmd_info_0 + Output + 3 + ctrl_ecc_cmd_info + + + ctrl_ecc_idle_0 + Output + 1 + ctrl_ecc_idle + + + ctrl_ecc_wr_pointer_info_0 + Output + 12 + ctrl_ecc_wr_pointer_info + + + + + + java.lang.String + emif_calbus_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + calbus_read + Input + 1 + calbus_read + + + calbus_write + Input + 1 + calbus_write + + + calbus_address + Input + 20 + calbus_address + + + calbus_wdata + Input + 32 + calbus_wdata + + + calbus_rdata + Output + 32 + calbus_rdata + + + calbus_seq_param_tbl + Output + 4096 + calbus_seq_param_tbl + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + false + + calbus_clk + Input + 1 + clk + + + + + + + java.lang.String + Agilex 7 + false + true + false + true + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + + + java.lang.String + 2 + false + true + false + true + + + java.lang.String + EXTENDED + false + true + false + true + + + java.lang.String + STANDARD_POWER + false + true + false + true + + + [Ljava.lang.String; + HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB + false + true + false + true + + + java.lang.String + FAMILY_AGILEX + false + true + false + true + + + java.lang.String + 1 + false + true + false + true + + + java.lang.String + IO96A_REVB2 + false + true + false + true + + + java.lang.String + PROTOCOL_DDR4 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 50000000 + false + true + false + true + + + java.lang.String + ed_synth_emif_fm_0_emif_fm_0 + false + true + false + true + + + java.lang.String + PROTOCOL_DDR4 + false + true + false + true + + + java.lang.String + E2V (ES3) - change device under 'View'->'Device Family' + false + true + false + true + + + java.lang.String + E2V + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 33.333 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 240 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + IO_STD_POD_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_HIGH + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + ps + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 50.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 33.333 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 33.333 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + IO_STD_POD_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + IN_OCT_60_CAL + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + IO_STD_TRUE_DIFF_SIGNALING + false + true + false + true + + + java.lang.String + IO_STD_CMOS_12 + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + IO_STD_SSTL_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_OFF + false + true + false + true + + + java.lang.String + IO_STD_POD_12 + false + true + false + true + + + java.lang.String + OUT_OCT_40_CAL + false + true + false + true + + + java.lang.String + SLEW_RATE_FM_FAST + false + true + false + true + + + java.lang.String + DEEMPHASIS_MODE_HIGH + false + true + false + true + + + java.lang.String + IN_OCT_60_CAL + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 68.0 + false + true + false + true + + + java.lang.String + IO_STD_TRUE_DIFF_SIGNALING + false + true + false + true + + + java.lang.String + IO_STD_CMOS_12 + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 633.333 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_HALF + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 533.333 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_HALF + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.8 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_ONLY + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1066.667 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_HARD_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 800.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + CONFIG_PHY_AND_SOFT_CTRL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1200.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + -1.0 + false + true + false + true + + + double + 10.0 + false + true + false + true + + + java.lang.String + RATE_QUARTER + false + true + false + true + + + java.lang.String + CORE_CLKS_SHARING_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 1.2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + PERIODIC_OCT_RECAL_AUTO + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + double + -1.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + unset + false + true + false + true + + + java.lang.String + MEM_FORMAT_RDIMM + false + true + false + true + + + double + 23.0 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 9 + false + true + false + true + + + java.lang.String + MEM_FORMAT_UDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 15 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + 0000000000000000 + false + true + false + true + + + java.lang.String + 000000000000000000 + false + true + false + true + + + java.lang.String + DDR3_ALERT_N_PLACEMENT_AC_LANES + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDR3_BL_BL8 + false + true + false + true + + + java.lang.String + DDR3_BT_SEQUENTIAL + false + true + false + true + + + java.lang.String + DDR3_ASR_MANUAL + false + true + false + true + + + java.lang.String + DDR3_SRT_NORMAL + false + true + false + true + + + java.lang.String + DDR3_PD_OFF + false + true + false + true + + + java.lang.String + DDR3_DRV_STR_RZQ_7 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR3_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR3_RTT_WR_RZQ_4 + false + true + false + true + + + int + 10 + false + true + false + true + + + java.lang.String + DDR3_ATCL_DISABLED + false + true + false + true + + + int + 14 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDR3_SPEEDBIN_2133 + false + true + false + true + + + int + 60 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 95 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 53 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 55 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 180 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 125.0 + false + true + false + true + + + double + 125.0 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 33.0 + false + true + false + true + + + double + 13.09 + false + true + false + true + + + double + 13.09 + false + true + false + true + + + double + 7.8 + false + true + false + true + + + double + 160.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 8 + false + true + false + true + + + double + 25.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 499 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 14 + false + true + false + true + + + int + 14 + false + true + false + true + + + int + 171 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 27 + false + true + false + true + + + int + 8320 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + MEM_FORMAT_RDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_ALERT_N_PLACEMENT_FM_LANE3 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_BL_BL8 + false + true + false + true + + + java.lang.String + DDR4_BT_SEQUENTIAL + false + true + false + true + + + int + 21 + false + true + false + true + + + java.lang.String + DDR4_RTT_NOM_RZQ_4 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_ATCL_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDR4_ASR_MANUAL_NORMAL + false + true + false + true + + + java.lang.String + DDR4_RTT_WR_ODT_DISABLED + false + true + false + true + + + int + 16 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_GEARDOWN_HR + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_FINE_REFRESH_FIXED_1X + false + true + false + true + + + java.lang.String + DDR4_MPR_READ_FORMAT_SERIAL + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + DDR4_AC_PARITY_LATENCY_DISABLE + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDR4_RTT_PARK_ODT_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 56.0 + false + true + false + true + + + java.lang.String + DDR4_VREFDQ_TRAINING_RANGE_1 + false + true + false + true + + + java.lang.String + DDR4_RCD_CA_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_RCD_CS_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_RCD_CKE_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_RCD_ODT_IBT_100 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_WR_RZQ_3 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_DRV_STR_RZQ_7 + false + true + false + true + + + int + 101 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 37 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 20 + false + true + false + true + + + int + 39 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 240 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + double + 68.0 + false + true + false + true + + + double + 70.0 + false + true + false + true + + + double + 70.0 + false + true + false + true + + + java.lang.String + DDR4_VREFDQ_TRAINING_RANGE_0 + false + true + false + true + + + java.lang.String + Range 1 - 60% to 92.5% + false + true + false + true + + + java.lang.String + DDR4_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDR4_RTT_WR_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_RTT_PARK_RZQ_4 + false + true + false + true + + + java.lang.String + RZQ/7 (34 Ohm) + false + true + false + true + + + java.lang.String + Dynamic ODT off + false + true + false + true + + + java.lang.String + ODT Disabled + false + true + false + true + + + java.lang.String + RZQ/4 (60 Ohm) + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_WR_RZQ_3 + false + true + false + true + + + java.lang.String + DDR4_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDR4_DB_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + RTT_NOM disabled + false + true + false + true + + + java.lang.String + RZQ/3 (80 Ohm) + false + true + false + true + + + java.lang.String + RTT_PARK disabled + false + true + false + true + + + java.lang.String + RZQ/7 (34 Ohm) + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 2164 + false + true + false + true + + + int + 65537 + false + true + false + true + + + int + 131112 + false + true + false + true + + + int + 197632 + false + true + false + true + + + int + 264192 + false + true + false + true + + + int + 332896 + false + true + false + true + + + int + 395279 + false + true + false + true + + + java.lang.String + 00000020000000003900000D40030B0F556000 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 13 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + on,off,on,off + false + true + false + true + + + [Ljava.lang.String; + off,on,off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,-,-,- + false + true + false + true + + + [Ljava.lang.String; + (Drive) RZQ/7 (34 Ohm),-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + Rank 0,-,-,- + false + true + false + true + + + [Ljava.lang.String; + (Park) RZQ/4 (60 Ohm),-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + -,-,-,- + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + [Ljava.lang.String; + + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + DDR4_SPEEDBIN_2666 + false + true + false + true + + + int + 62 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 87 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + int + 130 + false + true + false + true + + + double + 0.14 + false + true + false + true + + + double + 0.74 + false + true + false + true + + + double + 0.72 + false + true + false + true + + + int + 175 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + double + 0.13 + false + true + false + true + + + int + 500 + false + true + false + true + + + int + 8 + false + true + false + true + + + double + 32.0 + false + true + false + true + + + double + 14.16 + false + true + false + true + + + double + 14.16 + false + true + false + true + + + double + 7.8 + false + true + false + true + + + double + 350.0 + false + true + false + true + + + double + 15.0 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 3 + false + true + false + true + + + double + 21.0 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 90.0 + false + true + false + true + + + int + 16 + false + true + false + true + + + int + 4 + false + true + false + true + + + double + 0.1 + false + true + false + true + + + int + 66 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 600000 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 450 + false + true + false + true + + + int + 900 + false + true + false + true + + + int + 1200 + false + true + false + true + + + int + 39 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 420 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 26 + false + true + false + true + + + int + 9360 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 108 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 19 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 4 + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + QDR2_SPEEDBIN_633 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 0.23 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.23 + false + true + false + true + + + double + 0.18 + false + true + false + true + + + double + 0.09 + false + true + false + true + + + double + -0.09 + false + true + false + true + + + double + 0.08 + false + true + false + true + + + double + 0.71 + false + true + false + true + + + double + 0.45 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 21 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_ODT_25_PCT + false + true + false + true + + + java.lang.String + QDR4_OUTPUT_DRIVE_25_PCT + false + true + false + true + + + java.lang.String + QDR4_OUTPUT_DRIVE_25_PCT + false + true + false + true + + + java.lang.String + MEM_XP + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + QDR4_SPEEDBIN_2133 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.4 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + -150 + false + true + false + true + + + int + 225 + false + true + false + true + + + int + 170 + false + true + false + true + + + int + 170 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 21 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 4 + false + true + false + true + + + java.lang.String + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + false + true + false + true + + + java.lang.String + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + false + true + false + true + + + java.lang.String + RLD2_ODT_ON + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + RLD2_SPEEDBIN_18 + false + true + false + true + + + double + 0.24 + false + true + false + true + + + double + 0.45 + false + true + false + true + + + double + 0.9 + false + true + false + true + + + double + 0.3 + false + true + false + true + + + double + 0.3 + false + true + false + true + + + double + 0.17 + false + true + false + true + + + double + 0.17 + false + true + false + true + + + double + 0.12 + false + true + false + true + + + double + -0.12 + false + true + false + true + + + double + 0.3 + false + true + false + true + + + double + -0.3 + false + true + false + true + + + double + 0.2 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 20 + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 2 + false + true + false + true + + + java.lang.String + RLD3_DL_RL16_WL17 + false + true + false + true + + + java.lang.String + RLD3_TRC_9 + false + true + false + true + + + java.lang.String + RLD3_OUTPUT_DRIVE_40 + false + true + false + true + + + java.lang.String + RLD3_ODT_40 + false + true + false + true + + + java.lang.String + RLD3_AREF_BAC + false + true + false + true + + + java.lang.String + RLD3_WRITE_1BANK + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 36 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + RLD3_SPEEDBIN_093E + false + true + false + true + + + int + -30 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + double + 0.27 + false + true + false + true + + + double + -0.27 + false + true + false + true + + + int + 135 + false + true + false + true + + + int + 85 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 65 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 32 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 15 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 8 + false + true + false + true + + + java.lang.String + MEM_FORMAT_DISCRETE + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + LPDDR3_BL_BL8 + false + true + false + true + + + java.lang.String + LPDDR3_DL_RL12_WL6 + false + true + false + true + + + java.lang.String + LPDDR3_DRV_STR_40D_40U + false + true + false + true + + + java.lang.String + LPDDR3_DQODT_DISABLE + false + true + false + true + + + java.lang.String + LPDDR3_PDODT_DISABLED + false + true + false + true + + + java.lang.String + Set A + false + true + false + true + + + java.lang.String + LPDDR3_NWR_NWR12 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,on + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off 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[Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + [Ljava.lang.String; + , + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + LPDDR3_SPEEDBIN_1600 + false + true + false + true + + + int + 75 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 75 + false + true + false + true + + + int + 150 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 100 + false + true + false + true + + + int + 135 + false + true + false + true + + + double + 0.38 + false + true + false + true + + + int + 614 + false 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false + true + false + true + + + int + 220 + false + true + false + true + + + int + 511 + false + true + false + true + + + int + 5500 + false + true + false + true + + + int + 34 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 17 + false + true + false + true + + + int + 168 + false + true + false + true + + + int + 12 + false + true + false + true + + + int + 40 + false + true + false + true + + + int + 3120 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 6 + false + true + false + true + + + java.lang.String + MEM_FORMAT_LRDIMM + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 18 + false + true + false + true + + + int + 10 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 2 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_ALERT_N_PLACEMENT_AUTO + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_PWR_MODE_12W + false + true + false + true + + + java.lang.String + DDRT_BL_BL8 + false + true + false + true + + + java.lang.String + DDRT_BT_SEQUENTIAL + false + true + false + true + + + int + 15 + false + true + false + true + + + java.lang.String + DDRT_RTT_NOM_RZQ_4 + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + DDRT_ATCL_DISABLED + false + true + false + true + + + java.lang.String + DDRT_DRV_STR_RZQ_7 + false + true + false + true + + + java.lang.String + DDRT_ASR_MANUAL_NORMAL + false + true + false + true + + + java.lang.String + DDRT_RTT_WR_ODT_DISABLED + false + true + false + true + + + int + 18 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_GEARDOWN_HR + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_FINE_REFRESH_FIXED_1X + false + true + false + true + + + java.lang.String + DDRT_MPR_READ_FORMAT_SERIAL + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 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false + true + false + true + + + java.lang.String + DDRT_RCD_CA_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_RCD_CS_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_RCD_CKE_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_RCD_ODT_IBT_100 + false + true + false + true + + + java.lang.String + DDRT_DB_RTT_NOM_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDRT_DB_RTT_WR_RZQ_4 + false + true + false + true + + + java.lang.String + DDRT_DB_RTT_PARK_ODT_DISABLED + false + true + false + true + + + java.lang.String + DDRT_DB_DRV_STR_RZQ_7 + false + true + false + true + + + int + 85 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 29 + false + true + false + true + + + int + 25 + false + true + false + true + + + int + 21 + false + true + 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int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + double + 56.0 + false + true + false + true + + + java.lang.String + DDRT_VREFDQ_TRAINING_RANGE_1 + false + true + false + true + + + java.lang.String + Range 2 - 45% to 77.5% + false + true + false + true + + + int + 2 + false + true + false + true + + + int + -1 + false + true + false + true + + + int + -1 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 72 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true 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+ 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + off + false + true + false + true + + + [Ljava.lang.String; + Rank 0 + false + true + false + true + + + [Ljava.lang.String; + on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1 + false + true + false + true + + + [Ljava.lang.String; + on,off + false + true + false + true + + + [Ljava.lang.String; + off,on + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + off,off,off,off + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + Rank 0,Rank 1,Rank 2,Rank 3 + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + off,off,on,on + false + true + false + true + + + [Ljava.lang.String; + on,on,off,off + false + true + false + true + + + [Ljava.lang.String; + , + false + true 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false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + -0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 5.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 7.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 3.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + -0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 7.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 3.5 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + boolean + false + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.05 + false + true + false + true + + + double + 0.02 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + double + 0.6 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 8.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 4.0 + false + true + false + true + + + double + 2.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 2 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 9 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + int + 4 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 9 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 11 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + java.lang.String + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + CTRL_AVL_PROTOCOL_MM + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 10 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 128 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + POSTED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + COARSE + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 3 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 512 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + FAST_SIM_OVERRIDE_DEFAULT + false + true + false + true + + + java.lang.String + avl + false + true + false + true + + + java.lang.String + avl_release + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SOFT_NIOS_MODE_DISABLED + false + true + false + true + + + int + 100 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 57600 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + auto + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_JTAG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 5 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_JTAG + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_EXPORT + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + false + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + EFFMON_MODE_DISABLED + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + EMIF_PRI_PRELOAD.txt + false + true + false + true + + + java.lang.String + EMIF_SEC_PRELOAD.txt + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + TG_CFG_AMM_EXPORT_MODE_JTAG + false + true + false + true + + + java.lang.String + SHORT + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + java.lang.String + CALIP_0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + EXPORTED + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + AVAIL_EX_DESIGNS_GEN_DESIGN + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + HDL_FORMAT_VERILOG + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + TARGET_DEV_KIT_NONE + false + true + false + true + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + emif_usr_reset_n_in + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + true + + emif_usr_reset_n + Output + 1 + reset_n + + + + + + java.lang.String + + false + true + true + true + + + long + 300000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + emif_usr_clk + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + false + + emif_usr_reset_n_in + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + false + + emif_usr_clk_in + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + ctrl_ecc_write_info_0 + Output + 15 + ctrl_ecc_write_info + + + ctrl_ecc_rdata_id_0 + Input + 13 + ctrl_ecc_rdata_id + + + ctrl_ecc_read_info_0 + Input + 3 + ctrl_ecc_read_info + + + ctrl_ecc_cmd_info_0 + Input + 3 + ctrl_ecc_cmd_info + + + ctrl_ecc_idle_0 + Input + 1 + ctrl_ecc_idle + + + ctrl_ecc_wr_pointer_info_0 + Input + 12 + ctrl_ecc_wr_pointer_info + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + ctrl_ecc_user_interrupt_0 + Output + 1 + ctrl_ecc_user_interrupt + + + + + + java.lang.String + emif_usr_clk_in + false + true + false + true + + + java.lang.String + emif_usr_reset_n_in + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + 0 + true + + ast_cmd_valid_0 + Output + 1 + valid + + + ast_cmd_ready_0 + Input + 1 + ready + + + ast_cmd_data_0 + Output + 61 + data + + + + + + java.lang.String + emif_usr_clk_in + false + true + false + true + + + java.lang.String + emif_usr_reset_n_in + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 648 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + 0 + true + + ast_wr_valid_0 + Output + 1 + valid + + + ast_wr_ready_0 + Input + 1 + ready + + + ast_wr_data_0 + Output + 648 + data + + + + + + java.lang.String + emif_usr_clk_in + false + true + false + true + + + java.lang.String + emif_usr_reset_n_in + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 576 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + 0 + false + + ast_rd_valid_0 + Input + 1 + valid + + + ast_rd_ready_0 + Output + 1 + ready + + + ast_rd_data_0 + Input + 576 + data + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + true + true + + + java.math.BigInteger + 8589934592 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + emif_usr_clk + false + true + true + true + + + java.lang.String + emif_usr_reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + 0 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 64 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.math.BigInteger + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + [Ljava.lang.Integer; + + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 0 + false + true + true + true + + + java.lang.Integer + 35 + false + true + true + true + + + java.lang.Integer + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + 8589934592 + false + + amm_ready_0 + Output + 1 + waitrequest_n + + + amm_read_0 + Input + 1 + read + + + amm_write_0 + Input + 1 + write + + + amm_address_0 + Input + 27 + address + + + amm_readdata_0 + Output + 512 + readdata + + + amm_writedata_0 + Input + 512 + writedata + + + amm_burstcount_0 + Input + 7 + burstcount + + + amm_byteenable_0 + Input + 64 + byteenable + + + amm_readdatavalid_0 + Output + 1 + readdatavalid + + + + + + java.lang.Long + -1 + true + true + false + true + CLOCK_RATE + + + java.lang.Integer + -1 + true + true + false + true + CLOCK_DOMAIN + + + java.lang.Integer + -1 + true + true + false + true + RESET_DOMAIN + + + java.lang.String + + true + true + false + true + CLOCK_RESET_INFO + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + emif_fm_0_arch + emif_usr_clk + emif_fm_0_ecc_core + emif_usr_clk_in + + + + java.lang.Integer + -1 + true + true + false + true + RESET_DOMAIN + + + java.lang.Integer + -1 + true + true + false + true + CLOCK_DOMAIN + + + java.lang.String + + true + true + false + true + CLOCK_RESET_INFO + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + emif_fm_0_arch + emif_usr_reset_n + emif_fm_0_ecc_core + emif_usr_reset_n_in + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + emif_fm_0_ecc_core + ctrl_ecc_0 + emif_fm_0_arch + ctrl_ecc_0 + + + + java.lang.String + PIPELINE_STAGE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + HANDSHAKE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + DEFAULT + false + true + true + true + + + java.lang.String + GENERIC_CONVERTER + false + true + true + true + + + java.lang.String + GENERIC_CONVERTER + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + STANDARD + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + REGISTER_BASED + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + emif_fm_0_ecc_core + ctrl_ast_cmd_0 + emif_fm_0_arch + ctrl_ast_cmd_0 + + + + java.lang.String + PIPELINE_STAGE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + HANDSHAKE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + DEFAULT + false + true + true + true + + + java.lang.String + GENERIC_CONVERTER + false + true + true + true + + + java.lang.String + GENERIC_CONVERTER + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + STANDARD + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + REGISTER_BASED + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + emif_fm_0_ecc_core + ctrl_ast_wr_0 + emif_fm_0_arch + ctrl_ast_wr_0 + + + + java.lang.String + PIPELINE_STAGE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + HANDSHAKE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + DEFAULT + false + true + true + true + + + java.lang.String + GENERIC_CONVERTER + false + true + true + true + + + java.lang.String + GENERIC_CONVERTER + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + STANDARD + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + REGISTER_BASED + false + true + true + true + + + java.lang.String + FALSE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + emif_fm_0_arch + ctrl_ast_rd_0 + emif_fm_0_ecc_core + ctrl_ast_rd_0 + + + 1 + altera_emif_fm + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Memory Interfaces (EMIF) IP + 2.7.4 + + + 18 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 24.1 + + + 5 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 24.1 + + + 3 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 24.1 + + + 3 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 24.1 + + + 2 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Agent + 24.1 + + + 1 + altera_emif_arch_fm + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + EMIF Architecture Component + 19.1 + + + 3 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 24.1 + + + 3 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 24.1 + + + 1 + altera_emif_ecc + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + EMIF Error Correction Code (ECC) Component + 19.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 24.1 + + + 1 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 24.1 + + + 1 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 24.1 + + + 1 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Conduit Connection + 24.1 + + + 3 + avalon_streaming + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Streaming Connection + 24.1 + + 24.1 115 + + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.xml b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.xml new file mode 100644 index 0000000000..b6e7dbc5e7 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0.xml @@ -0,0 +1,12829 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: ed_synth_emif_fm_0" + "Generating: ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" + "Generating: ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" + "Generating: ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" + "Generating: altera_emif_ecc_core" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: altera_emif_ecc_core" + + + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_bb.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_bb.v new file mode 100644 index 0000000000..71cb2c90af --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_bb.v @@ -0,0 +1,46 @@ +module ed_synth_emif_fm_0 ( + input wire local_reset_req, // local_reset_req.local_reset_req, Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. + output wire local_reset_done, // local_reset_status.local_reset_done, Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. + input wire pll_ref_clk, // pll_ref_clk.clk, PLL reference clock input + output wire pll_locked, // pll_locked.pll_locked, PLL lock signal to indicate whether the PLL has locked + input wire oct_rzqin, // oct.oct_rzqin, Calibrated On-Chip Termination (OCT) RZQ input pin + output wire [0:0] mem_ck, // mem.mem_ck, CK clock + output wire [0:0] mem_ck_n, // .mem_ck_n, CK clock (negative leg) + output wire [16:0] mem_a, // .mem_a, Address + output wire [0:0] mem_act_n, // .mem_act_n, Activation command + output wire [1:0] mem_ba, // .mem_ba, Bank address + output wire [1:0] mem_bg, // .mem_bg, Bank group + output wire [0:0] mem_cke, // .mem_cke, Clock enable + output wire [0:0] mem_cs_n, // .mem_cs_n, Chip select + output wire [0:0] mem_odt, // .mem_odt, On-die termination + output wire [0:0] mem_reset_n, // .mem_reset_n, Asynchronous reset + output wire [0:0] mem_par, // .mem_par, Command and address parity + input wire [0:0] mem_alert_n, // .mem_alert_n, Alert flag + inout wire [8:0] mem_dqs, // .mem_dqs, Data strobe + inout wire [8:0] mem_dqs_n, // .mem_dqs_n, Data strobe (negative leg) + inout wire [71:0] mem_dq, // .mem_dq, Read/write data + inout wire [8:0] mem_dbi_n, // .mem_dbi_n, Acts as either the data bus inversion pin, or the data mask pin, depending on configuration. + output wire local_cal_success, // status.local_cal_success, When high, indicates that PHY calibration was successful + output wire local_cal_fail, // .local_cal_fail, When high, indicates that PHY calibration failed + input wire calbus_read, // emif_calbus.calbus_read, EMIF Calibration component bus for read + input wire calbus_write, // .calbus_write, EMIF Calibration component bus for write + input wire [19:0] calbus_address, // .calbus_address, EMIF Calibration component bus for address + input wire [31:0] calbus_wdata, // .calbus_wdata, EMIF Calibration component bus for write data + output wire [31:0] calbus_rdata, // .calbus_rdata, EMIF Calibration component bus for read data + output wire [4095:0] calbus_seq_param_tbl, // .calbus_seq_param_tbl, EMIF Calibration component bus for parameter table data + input wire calbus_clk, // emif_calbus_clk.clk, EMIF Calibration component bus for the clock + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n, Reset for the user clock domain. Asynchronous assertion and synchronous deassertion + output wire emif_usr_clk, // emif_usr_clk.clk, User clock domain + output wire ctrl_ecc_user_interrupt_0, // ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt, Controller ECC user interrupt signal to determine whether there is a bit error + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n, Wait-request is asserted when controller is busy + input wire amm_read_0, // .read, Read request signal + input wire amm_write_0, // .write, Write request signal + input wire [26:0] amm_address_0, // .address, Address for the read/write request + output wire [511:0] amm_readdata_0, // .readdata, Read data + input wire [511:0] amm_writedata_0, // .writedata, Write data + input wire [6:0] amm_burstcount_0, // .burstcount, Number of transfers in each read/write burst + input wire [63:0] amm_byteenable_0, // .byteenable, Byte-enable for write data + output wire amm_readdatavalid_0 // .readdatavalid, Indicates whether read data is valid + ); +endmodule + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_generation.rpt b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_generation.rpt new file mode 100644 index 0000000000..c27e0ae281 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_generation.rpt @@ -0,0 +1,33 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: ed_synth_emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. +Info: ed_synth_emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: PHY and controller running at 2x the frequency of user logic for improved efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 1A: Component and DIMM (with A17)". +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 4 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 33.333 MHz and user clock rate, in MHz: 1599.98, 1466.65, 1333.32, 1199.99, 1066.66, 933.32, 799.99, 666.66 +Info: ed_synth_emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: ed_synth_emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. +Info: ed_synth_emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: PHY and controller running at 2x the frequency of user logic for improved efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 1A: Component and DIMM (with A17)". +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 4 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 33.333 MHz and user clock rate, in MHz: 1599.98, 1466.65, 1333.32, 1199.99, 1066.66, 933.32, 799.99, 666.66 +Info: ed_synth_emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. +Info: ed_synth_emif_fm_0: "Transforming system: ed_synth_emif_fm_0" +Info: ed_synth_emif_fm_0: "Naming system components in system: ed_synth_emif_fm_0" +Info: ed_synth_emif_fm_0: "Processing generation queue" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" +Info: ed_synth_emif_fm_0: "Generating: altera_emif_ecc_core" +Info: ed_synth_emif_fm_0: Done "ed_synth_emif_fm_0" with 5 modules, 71 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_generation_previous.rpt b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_generation_previous.rpt new file mode 100644 index 0000000000..c27e0ae281 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_generation_previous.rpt @@ -0,0 +1,33 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: ed_synth_emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. +Info: ed_synth_emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: PHY and controller running at 2x the frequency of user logic for improved efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 1A: Component and DIMM (with A17)". +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 4 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 33.333 MHz and user clock rate, in MHz: 1599.98, 1466.65, 1333.32, 1199.99, 1066.66, 933.32, 799.99, 666.66 +Info: ed_synth_emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/ed_synth_emif_fm_0 --family="Agilex 7" --part=AGFB014R24B2E2V +Info: ed_synth_emif_fm_0.emif_fm_0: SPD Bytes must be set for RDIMM/LRDIMM and are unique to each memory module. Please check with the SPD provider to ensure correct SPD data. +Info: ed_synth_emif_fm_0.emif_fm_0: When ECC is enabled, a partial write using the DM pins triggers a read-modify-write operation. Frequent partial writes can lead to poor efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: EMIF IP requires EMIF Calibration IP to source its calbus clock and calbus conduit. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: PHY and controller running at 2x the frequency of user logic for improved efficiency. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Placement of address/command pins must follow "DDR4 Scheme 1A: Component and DIMM (with A17)". +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Interface estimated to require 2 I/O Bank(s) and 4 I/O PLL(s). This is only an estimation. Final usage depends on user pin location assignments and/or fitter behavior. +Info: ed_synth_emif_fm_0.emif_fm_0.arch: Valid memory frequencies for the current PLL reference clock of 33.333 MHz and user clock rate, in MHz: 1599.98, 1466.65, 1333.32, 1199.99, 1066.66, 933.32, 799.99, 666.66 +Info: ed_synth_emif_fm_0.emif_fm_0.arch: For additional documentation about the interface, consult the *_readme.txt file after generation. +Info: ed_synth_emif_fm_0: "Transforming system: ed_synth_emif_fm_0" +Info: ed_synth_emif_fm_0: "Naming system components in system: ed_synth_emif_fm_0" +Info: ed_synth_emif_fm_0: "Processing generation queue" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0_altera_emif_arch_fm_191_faapzxy" +Info: ed_synth_emif_fm_0: "Generating: ed_synth_emif_fm_0_altera_emif_ecc_191_z5lxzjq" +Info: ed_synth_emif_fm_0: "Generating: altera_emif_ecc_core" +Info: ed_synth_emif_fm_0: Done "ed_synth_emif_fm_0" with 5 modules, 71 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_inst.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_inst.v new file mode 100644 index 0000000000..cd9869d5d6 --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_inst.v @@ -0,0 +1,45 @@ + ed_synth_emif_fm_0 u0 ( + .local_reset_req (_connected_to_local_reset_req_), // input, width = 1, local_reset_req.local_reset_req + .local_reset_done (_connected_to_local_reset_done_), // output, width = 1, local_reset_status.local_reset_done + .pll_ref_clk (_connected_to_pll_ref_clk_), // input, width = 1, pll_ref_clk.clk + .pll_locked (_connected_to_pll_locked_), // output, width = 1, pll_locked.pll_locked + .oct_rzqin (_connected_to_oct_rzqin_), // input, width = 1, oct.oct_rzqin + .mem_ck (_connected_to_mem_ck_), // output, width = 1, mem.mem_ck + .mem_ck_n (_connected_to_mem_ck_n_), // output, width = 1, .mem_ck_n + .mem_a (_connected_to_mem_a_), // output, width = 17, .mem_a + .mem_act_n (_connected_to_mem_act_n_), // output, width = 1, .mem_act_n + .mem_ba (_connected_to_mem_ba_), // output, width = 2, .mem_ba + .mem_bg (_connected_to_mem_bg_), // output, width = 2, .mem_bg + .mem_cke (_connected_to_mem_cke_), // output, width = 1, .mem_cke + .mem_cs_n (_connected_to_mem_cs_n_), // output, width = 1, .mem_cs_n + .mem_odt (_connected_to_mem_odt_), // output, width = 1, .mem_odt + .mem_reset_n (_connected_to_mem_reset_n_), // output, width = 1, .mem_reset_n + .mem_par (_connected_to_mem_par_), // output, width = 1, .mem_par + .mem_alert_n (_connected_to_mem_alert_n_), // input, width = 1, .mem_alert_n + .mem_dqs (_connected_to_mem_dqs_), // inout, width = 9, .mem_dqs + .mem_dqs_n (_connected_to_mem_dqs_n_), // inout, width = 9, .mem_dqs_n + .mem_dq (_connected_to_mem_dq_), // inout, width = 72, .mem_dq + .mem_dbi_n (_connected_to_mem_dbi_n_), // inout, width = 9, .mem_dbi_n + .local_cal_success (_connected_to_local_cal_success_), // output, width = 1, status.local_cal_success + .local_cal_fail (_connected_to_local_cal_fail_), // output, width = 1, .local_cal_fail + .calbus_read (_connected_to_calbus_read_), // input, width = 1, emif_calbus.calbus_read + .calbus_write (_connected_to_calbus_write_), // input, width = 1, .calbus_write + .calbus_address (_connected_to_calbus_address_), // input, width = 20, .calbus_address + .calbus_wdata (_connected_to_calbus_wdata_), // input, width = 32, .calbus_wdata + .calbus_rdata (_connected_to_calbus_rdata_), // output, width = 32, .calbus_rdata + .calbus_seq_param_tbl (_connected_to_calbus_seq_param_tbl_), // output, width = 4096, .calbus_seq_param_tbl + .calbus_clk (_connected_to_calbus_clk_), // input, width = 1, emif_calbus_clk.clk + .emif_usr_reset_n (_connected_to_emif_usr_reset_n_), // output, width = 1, emif_usr_reset_n.reset_n + .emif_usr_clk (_connected_to_emif_usr_clk_), // output, width = 1, emif_usr_clk.clk + .ctrl_ecc_user_interrupt_0 (_connected_to_ctrl_ecc_user_interrupt_0_), // output, width = 1, ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt + .amm_ready_0 (_connected_to_amm_ready_0_), // output, width = 1, ctrl_amm_0.waitrequest_n + .amm_read_0 (_connected_to_amm_read_0_), // input, width = 1, .read + .amm_write_0 (_connected_to_amm_write_0_), // input, width = 1, .write + .amm_address_0 (_connected_to_amm_address_0_), // input, width = 27, .address + .amm_readdata_0 (_connected_to_amm_readdata_0_), // output, width = 512, .readdata + .amm_writedata_0 (_connected_to_amm_writedata_0_), // input, width = 512, .writedata + .amm_burstcount_0 (_connected_to_amm_burstcount_0_), // input, width = 7, .burstcount + .amm_byteenable_0 (_connected_to_amm_byteenable_0_), // input, width = 64, .byteenable + .amm_readdatavalid_0 (_connected_to_amm_readdatavalid_0_) // output, width = 1, .readdatavalid + ); + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_inst.vhd b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_inst.vhd new file mode 100644 index 0000000000..568b6e6dee --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/ed_synth_emif_fm_0_inst.vhd @@ -0,0 +1,93 @@ + component ed_synth_emif_fm_0 is + port ( + local_reset_req : in std_logic := 'X'; -- local_reset_req + local_reset_done : out std_logic; -- local_reset_done + pll_ref_clk : in std_logic := 'X'; -- clk + pll_locked : out std_logic; -- pll_locked + oct_rzqin : in std_logic := 'X'; -- oct_rzqin + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_a : out std_logic_vector(16 downto 0); -- mem_a + mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n + mem_ba : out std_logic_vector(1 downto 0); -- mem_ba + mem_bg : out std_logic_vector(1 downto 0); -- mem_bg + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n + mem_par : out std_logic_vector(0 downto 0); -- mem_par + mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n + mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n + mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq + mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + calbus_read : in std_logic := 'X'; -- calbus_read + calbus_write : in std_logic := 'X'; -- calbus_write + calbus_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- calbus_address + calbus_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_wdata + calbus_rdata : out std_logic_vector(31 downto 0); -- calbus_rdata + calbus_seq_param_tbl : out std_logic_vector(4095 downto 0); -- calbus_seq_param_tbl + calbus_clk : in std_logic := 'X'; -- clk + emif_usr_reset_n : out std_logic; -- reset_n + emif_usr_clk : out std_logic; -- clk + ctrl_ecc_user_interrupt_0 : out std_logic; -- ctrl_ecc_user_interrupt + amm_ready_0 : out std_logic; -- waitrequest_n + amm_read_0 : in std_logic := 'X'; -- read + amm_write_0 : in std_logic := 'X'; -- write + amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address + amm_readdata_0 : out std_logic_vector(511 downto 0); -- readdata + amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata + amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount + amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable + amm_readdatavalid_0 : out std_logic -- readdatavalid + ); + end component ed_synth_emif_fm_0; + + u0 : component ed_synth_emif_fm_0 + port map ( + local_reset_req => CONNECTED_TO_local_reset_req, -- local_reset_req.local_reset_req + local_reset_done => CONNECTED_TO_local_reset_done, -- local_reset_status.local_reset_done + pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk + pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked + oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin + mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck + mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n + mem_a => CONNECTED_TO_mem_a, -- .mem_a + mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n + mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba + mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg + mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke + mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n + mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt + mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n + mem_par => CONNECTED_TO_mem_par, -- .mem_par + mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n + mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs + mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n + mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq + mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n + local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success + local_cal_fail => CONNECTED_TO_local_cal_fail, -- .local_cal_fail + calbus_read => CONNECTED_TO_calbus_read, -- emif_calbus.calbus_read + calbus_write => CONNECTED_TO_calbus_write, -- .calbus_write + calbus_address => CONNECTED_TO_calbus_address, -- .calbus_address + calbus_wdata => CONNECTED_TO_calbus_wdata, -- .calbus_wdata + calbus_rdata => CONNECTED_TO_calbus_rdata, -- .calbus_rdata + calbus_seq_param_tbl => CONNECTED_TO_calbus_seq_param_tbl, -- .calbus_seq_param_tbl + calbus_clk => CONNECTED_TO_calbus_clk, -- emif_calbus_clk.clk + emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n + emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk + ctrl_ecc_user_interrupt_0 => CONNECTED_TO_ctrl_ecc_user_interrupt_0, -- ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt + amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n + amm_read_0 => CONNECTED_TO_amm_read_0, -- .read + amm_write_0 => CONNECTED_TO_amm_write_0, -- .write + amm_address_0 => CONNECTED_TO_amm_address_0, -- .address + amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata + amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata + amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount + amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable + amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0 -- .readdatavalid + ); + diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0/synth/ed_synth_emif_fm_0.v b/corev_apu/altera/ip/ed_synth_emif_fm_0/synth/ed_synth_emif_fm_0.v new file mode 100644 index 0000000000..305cedf14f --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0/synth/ed_synth_emif_fm_0.v @@ -0,0 +1,96 @@ +// ed_synth_emif_fm_0.v + +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module ed_synth_emif_fm_0 ( + input wire local_reset_req, // local_reset_req.local_reset_req, Signal from user logic to request the memory interface to be reset and recalibrated. Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles. + output wire local_reset_done, // local_reset_status.local_reset_done, Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. When local_reset_done is low, the memory interface is in reset. + input wire pll_ref_clk, // pll_ref_clk.clk, PLL reference clock input + output wire pll_locked, // pll_locked.pll_locked, PLL lock signal to indicate whether the PLL has locked + input wire oct_rzqin, // oct.oct_rzqin, Calibrated On-Chip Termination (OCT) RZQ input pin + output wire [0:0] mem_ck, // mem.mem_ck, CK clock + output wire [0:0] mem_ck_n, // .mem_ck_n, CK clock (negative leg) + output wire [16:0] mem_a, // .mem_a, Address + output wire [0:0] mem_act_n, // .mem_act_n, Activation command + output wire [1:0] mem_ba, // .mem_ba, Bank address + output wire [1:0] mem_bg, // .mem_bg, Bank group + output wire [0:0] mem_cke, // .mem_cke, Clock enable + output wire [0:0] mem_cs_n, // .mem_cs_n, Chip select + output wire [0:0] mem_odt, // .mem_odt, On-die termination + output wire [0:0] mem_reset_n, // .mem_reset_n, Asynchronous reset + output wire [0:0] mem_par, // .mem_par, Command and address parity + input wire [0:0] mem_alert_n, // .mem_alert_n, Alert flag + inout wire [8:0] mem_dqs, // .mem_dqs, Data strobe + inout wire [8:0] mem_dqs_n, // .mem_dqs_n, Data strobe (negative leg) + inout wire [71:0] mem_dq, // .mem_dq, Read/write data + inout wire [8:0] mem_dbi_n, // .mem_dbi_n, Acts as either the data bus inversion pin, or the data mask pin, depending on configuration. + output wire local_cal_success, // status.local_cal_success, When high, indicates that PHY calibration was successful + output wire local_cal_fail, // .local_cal_fail, When high, indicates that PHY calibration failed + input wire calbus_read, // emif_calbus.calbus_read, EMIF Calibration component bus for read + input wire calbus_write, // .calbus_write, EMIF Calibration component bus for write + input wire [19:0] calbus_address, // .calbus_address, EMIF Calibration component bus for address + input wire [31:0] calbus_wdata, // .calbus_wdata, EMIF Calibration component bus for write data + output wire [31:0] calbus_rdata, // .calbus_rdata, EMIF Calibration component bus for read data + output wire [4095:0] calbus_seq_param_tbl, // .calbus_seq_param_tbl, EMIF Calibration component bus for parameter table data + input wire calbus_clk, // emif_calbus_clk.clk, EMIF Calibration component bus for the clock + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n, Reset for the user clock domain. Asynchronous assertion and synchronous deassertion + output wire emif_usr_clk, // emif_usr_clk.clk, User clock domain + output wire ctrl_ecc_user_interrupt_0, // ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt, Controller ECC user interrupt signal to determine whether there is a bit error + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n, Wait-request is asserted when controller is busy + input wire amm_read_0, // .read, Read request signal + input wire amm_write_0, // .write, Write request signal + input wire [26:0] amm_address_0, // .address, Address for the read/write request + output wire [511:0] amm_readdata_0, // .readdata, Read data + input wire [511:0] amm_writedata_0, // .writedata, Write data + input wire [6:0] amm_burstcount_0, // .burstcount, Number of transfers in each read/write burst + input wire [63:0] amm_byteenable_0, // .byteenable, Byte-enable for write data + output wire amm_readdatavalid_0 // .readdatavalid, Indicates whether read data is valid + ); + + ed_synth_emif_fm_0_altera_emif_fm_274_2bbiayq emif_fm_0 ( + .local_reset_req (local_reset_req), // input, width = 1, local_reset_req.local_reset_req + .local_reset_done (local_reset_done), // output, width = 1, local_reset_status.local_reset_done + .pll_ref_clk (pll_ref_clk), // input, width = 1, pll_ref_clk.clk + .pll_locked (pll_locked), // output, width = 1, pll_locked.pll_locked + .oct_rzqin (oct_rzqin), // input, width = 1, oct.oct_rzqin + .mem_ck (mem_ck), // output, width = 1, mem.mem_ck + .mem_ck_n (mem_ck_n), // output, width = 1, .mem_ck_n + .mem_a (mem_a), // output, width = 17, .mem_a + .mem_act_n (mem_act_n), // output, width = 1, .mem_act_n + .mem_ba (mem_ba), // output, width = 2, .mem_ba + .mem_bg (mem_bg), // output, width = 2, .mem_bg + .mem_cke (mem_cke), // output, width = 1, .mem_cke + .mem_cs_n (mem_cs_n), // output, width = 1, .mem_cs_n + .mem_odt (mem_odt), // output, width = 1, .mem_odt + .mem_reset_n (mem_reset_n), // output, width = 1, .mem_reset_n + .mem_par (mem_par), // output, width = 1, .mem_par + .mem_alert_n (mem_alert_n), // input, width = 1, .mem_alert_n + .mem_dqs (mem_dqs), // inout, width = 9, .mem_dqs + .mem_dqs_n (mem_dqs_n), // inout, width = 9, .mem_dqs_n + .mem_dq (mem_dq), // inout, width = 72, .mem_dq + .mem_dbi_n (mem_dbi_n), // inout, width = 9, .mem_dbi_n + .local_cal_success (local_cal_success), // output, width = 1, status.local_cal_success + .local_cal_fail (local_cal_fail), // output, width = 1, .local_cal_fail + .calbus_read (calbus_read), // input, width = 1, emif_calbus.calbus_read + .calbus_write (calbus_write), // input, width = 1, .calbus_write + .calbus_address (calbus_address), // input, width = 20, .calbus_address + .calbus_wdata (calbus_wdata), // input, width = 32, .calbus_wdata + .calbus_rdata (calbus_rdata), // output, width = 32, .calbus_rdata + .calbus_seq_param_tbl (calbus_seq_param_tbl), // output, width = 4096, .calbus_seq_param_tbl + .calbus_clk (calbus_clk), // input, width = 1, emif_calbus_clk.clk + .emif_usr_reset_n (emif_usr_reset_n), // output, width = 1, emif_usr_reset_n.reset_n + .emif_usr_clk (emif_usr_clk), // output, width = 1, emif_usr_clk.clk + .ctrl_ecc_user_interrupt_0 (ctrl_ecc_user_interrupt_0), // output, width = 1, ctrl_ecc_user_interrupt_0.ctrl_ecc_user_interrupt + .amm_ready_0 (amm_ready_0), // output, width = 1, ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // input, width = 1, .read + .amm_write_0 (amm_write_0), // input, width = 1, .write + .amm_address_0 (amm_address_0), // input, width = 27, .address + .amm_readdata_0 (amm_readdata_0), // output, width = 512, .readdata + .amm_writedata_0 (amm_writedata_0), // input, width = 512, .writedata + .amm_burstcount_0 (amm_burstcount_0), // input, width = 7, .burstcount + .amm_byteenable_0 (amm_byteenable_0), // input, width = 64, .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0) // output, width = 1, .readdatavalid + ); + +endmodule diff --git a/corev_apu/altera/ip/emif_cal.ip b/corev_apu/altera/ip/emif_cal.ip new file mode 100644 index 0000000000..df313aa1ea --- /dev/null +++ b/corev_apu/altera/ip/emif_cal.ip @@ -0,0 +1,624 @@ + + + + Intel Corporation + emif_cal + emif_cal_0 + 2.7.4 + + + emif_calbus_0 + + + + + + + + calbus_read + + + calbus_read_0 + + + + + calbus_write + + + calbus_write_0 + + + + + calbus_address + + + calbus_address_0 + + + + + calbus_wdata + + + calbus_wdata_0 + + + + + calbus_rdata + + + calbus_rdata_0 + + + + + calbus_seq_param_tbl + + + calbus_seq_param_tbl_0 + + + + + + + + + associatedClock + associatedClock + emif_calbus_clk + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + emif_calbus_clk + + + + + + + + clk + + + calbus_clk + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_emif_cal + + QUARTUS_SYNTH + + + + + + + calbus_read_0 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + calbus_write_0 + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + calbus_address_0 + + out + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + calbus_wdata_0 + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + calbus_rdata_0 + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + calbus_seq_param_tbl_0 + + in + + + 0 + 4095 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + calbus_clk + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + emif_cal + altera_emif_cal + 2.7.4 + + + + + AXM_ID_NUM + AXI ID + 0 + + + NUM_CALBUS_INTERFACE + Number of Calibration Interfaces + 1 + + + DIAG_SIM_CAL_MODE_ENUM + Calibration mode for simulation + SIM_CAL_MODE_SKIP + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_SIM_VERBOSE + Show verbose simulation debug messages + false + + + ENABLE_DDRT + Enable DDRT functionality + false + + + DIAG_SYNTH_FOR_SIM + Synthesize for simulation + false + + + DIAG_EXTRA_CONFIGS + Extra configuration + + + + DIAG_EXPORT_VJI + Export Virtual JTAG Interface (VJI) + false + + + SHORT_QSYS_INTERFACE_NAMES + Use short Qsys interface names + true + + + DIAG_ENABLE_JTAG_UART + Enable JTAG UART + false + + + PHY_DDRT_EXPORT_CLK_STP_IF + Export clock stopper interface + false + + + AUTO_DEVICE_FAMILY + Auto DEVICE_FAMILY + Agilex 7 + + + AUTO_DEVICE + Auto DEVICE + AGFB014R24B2E2V + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 2 + + + AUTO_BOARD + Auto BOARD + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + + + + + + + board + Board + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + + + device + Device + AGFB014R24B2E2V + + + deviceFamily + Device family + Agilex 7 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Agilex 7"; + type = "String"; + } + } + element emif_cal_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>emif_calbus_0</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>calbus_read_0</name> + <role>calbus_read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_write_0</name> + <role>calbus_write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_address_0</name> + <role>calbus_address</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_wdata_0</name> + <role>calbus_wdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_rdata_0</name> + <role>calbus_rdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>calbus_seq_param_tbl_0</name> + <role>calbus_seq_param_tbl</role> + <direction>Input</direction> + <width>4096</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>emif_calbus_clk</value> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_calbus_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>calbus_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>emif_calbus_clk</key> + <value> + <connectionPointName>emif_calbus_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + <cpuInfoDefinition> + <version>1</version> + <cpuGroups/> + <exportedModules/> + <systemInformation> + <name>emif_cal_0</name> + <deviceFamily>Agilex 7</deviceFamily> + <generateLegacySim>false</generateLegacySim> + </systemInformation> +</cpuInfoDefinition> + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressAndMemoryMap + addressAndMemoryMap + 1.0 + + + + + + false + false + + \ No newline at end of file diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_274/synth/emif_cal_altera_emif_cal_274_kaypsya.v b/corev_apu/altera/ip/emif_cal/altera_emif_cal_274/synth/emif_cal_altera_emif_cal_274_kaypsya.v new file mode 100644 index 0000000000..64ff3a445a --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_274/synth/emif_cal_altera_emif_cal_274_kaypsya.v @@ -0,0 +1,166 @@ +// emif_cal_altera_emif_cal_274_kaypsya.v + +// This file was auto-generated from altera_emif_cal_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module emif_cal_altera_emif_cal_274_kaypsya ( + output wire calbus_read_0, // emif_calbus_0.calbus_read, EMIF Calibration component bus for read + output wire calbus_write_0, // .calbus_write, EMIF Calibration component bus for write + output wire [19:0] calbus_address_0, // .calbus_address, EMIF Calibration component bus for address + output wire [31:0] calbus_wdata_0, // .calbus_wdata, EMIF Calibration component bus for write data + input wire [31:0] calbus_rdata_0, // .calbus_rdata, EMIF Calibration component bus for read data + input wire [4095:0] calbus_seq_param_tbl_0, // .calbus_seq_param_tbl, EMIF Calibration component bus for parameter table data + output wire calbus_clk // emif_calbus_clk.clk, EMIF Calibration component bus for the clock + ); + + emif_cal_altera_emif_cal_iossm_274_yagv7fq #( + .NUM_CALBUS_USED (1), + .IOSSM_USE_MODEL (1), + .USE_SYNTH_FOR_SIM (0), + .USE_SOFT_NIOS (0), + .IOSSM_SIM_NIOS_PERIOD_PS (800), + .SEQ_GPT_GLOBAL_PAR_VER (2), + .SEQ_GPT_NIOS_C_VER (1), + .SEQ_GPT_COLUMN_ID (1), + .SEQ_GPT_NUM_IOPACKS (16), + .SEQ_GPT_NIOS_CLK_FREQ_KHZ (250000), + .SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ (1250000), + .SEQ_GPT_PARAM_TABLE_SIZE (612), + .SEQ_GPT_GLOBAL_SKIP_STEPS (8), + .SIM_SEQ_GPT_GLOBAL_SKIP_STEPS (1631), + .SEQ_GPT_GLOBAL_CAL_CONFIG (0), + .SEQ_GPT_SLAVE_CLK_DIVIDER (28), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (27), + .PORT_CAL_DEBUG_RDATA_WIDTH (32), + .PORT_CAL_DEBUG_WDATA_WIDTH (32), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (4), + .PORT_CALBUS_ADDRESS_WIDTH (20), + .PORT_CALBUS_WDATA_WIDTH (32), + .PORT_CALBUS_RDATA_WIDTH (32), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (4096), + .PORT_VJI_IR_IN_WIDTH (2), + .PORT_VJI_IR_OUT_WIDTH (2) + ) emif_cal ( + .calbus_read_0 (calbus_read_0), // output, width = 1, emif_calbus_0.calbus_read + .calbus_write_0 (calbus_write_0), // output, width = 1, .calbus_write + .calbus_address_0 (calbus_address_0), // output, width = 20, .calbus_address + .calbus_wdata_0 (calbus_wdata_0), // output, width = 32, .calbus_wdata + .calbus_rdata_0 (calbus_rdata_0), // input, width = 32, .calbus_rdata + .calbus_seq_param_tbl_0 (calbus_seq_param_tbl_0), // input, width = 4096, .calbus_seq_param_tbl + .calbus_clk (calbus_clk), // output, width = 1, emif_calbus_clk.clk + .cal_debug_waitrequest (), // (terminated), + .cal_debug_read (1'b0), // (terminated), + .cal_debug_write (1'b0), // (terminated), + .cal_debug_addr (27'b000000000000000000000000000), // (terminated), + .cal_debug_read_data (), // (terminated), + .cal_debug_write_data (32'b00000000000000000000000000000000), // (terminated), + .cal_debug_byteenable (4'b0000), // (terminated), + .cal_debug_read_data_valid (), // (terminated), + .cal_debug_clk (1'b0), // (terminated), + .cal_debug_reset_n (1'b1), // (terminated), + .calbus_read_1 (), // (terminated), + .calbus_write_1 (), // (terminated), + .calbus_address_1 (), // (terminated), + .calbus_wdata_1 (), // (terminated), + .calbus_rdata_1 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_1 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// (terminated), + .calbus_read_2 (), // (terminated), + .calbus_write_2 (), // (terminated), + .calbus_address_2 (), // (terminated), + .calbus_wdata_2 (), // (terminated), + .calbus_rdata_2 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_2 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// (terminated), + .calbus_read_3 (), // (terminated), + .calbus_write_3 (), // (terminated), + .calbus_address_3 (), // (terminated), + .calbus_wdata_3 (), // (terminated), + .calbus_rdata_3 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_3 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// (terminated), + .calbus_read_4 (), // (terminated), + .calbus_write_4 (), // (terminated), + .calbus_address_4 (), // (terminated), + .calbus_wdata_4 (), // (terminated), + .calbus_rdata_4 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_4 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// (terminated), + .calbus_read_5 (), // (terminated), + .calbus_write_5 (), // (terminated), + .calbus_address_5 (), // (terminated), + .calbus_wdata_5 (), // (terminated), + .calbus_rdata_5 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_5 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// (terminated), + .calbus_read_6 (), // (terminated), + .calbus_write_6 (), // (terminated), + .calbus_address_6 (), // (terminated), + .calbus_wdata_6 (), // (terminated), + .calbus_rdata_6 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_6 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// (terminated), + .calbus_read_7 (), // (terminated), + .calbus_write_7 (), // (terminated), + .calbus_address_7 (), // (terminated), + .calbus_wdata_7 (), // (terminated), + .calbus_rdata_7 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_7 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// (terminated), + .calbus_read_8 (), // (terminated), + .calbus_write_8 (), // (terminated), + .calbus_address_8 (), // (terminated), + .calbus_wdata_8 (), // (terminated), + .calbus_rdata_8 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_8 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_9 (), // (terminated), + .calbus_write_9 (), // (terminated), + .calbus_address_9 (), // (terminated), + .calbus_wdata_9 (), // (terminated), + .calbus_rdata_9 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_9 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_10 (), // (terminated), + .calbus_write_10 (), // (terminated), + .calbus_address_10 (), // (terminated), + .calbus_wdata_10 (), // (terminated), + .calbus_rdata_10 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_10 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_11 (), // (terminated), + .calbus_write_11 (), // (terminated), + .calbus_address_11 (), // (terminated), + .calbus_wdata_11 (), // (terminated), + .calbus_rdata_11 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_11 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_12 (), // (terminated), + .calbus_write_12 (), // (terminated), + .calbus_address_12 (), // (terminated), + .calbus_wdata_12 (), // (terminated), + .calbus_rdata_12 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_12 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_13 (), // (terminated), + .calbus_write_13 (), // (terminated), + .calbus_address_13 (), // (terminated), + .calbus_wdata_13 (), // (terminated), + .calbus_rdata_13 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_13 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_14 (), // (terminated), + .calbus_write_14 (), // (terminated), + .calbus_address_14 (), // (terminated), + .calbus_wdata_14 (), // (terminated), + .calbus_rdata_14 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_14 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .calbus_read_15 (), // (terminated), + .calbus_write_15 (), // (terminated), + .calbus_address_15 (), // (terminated), + .calbus_wdata_15 (), // (terminated), + .calbus_rdata_15 (32'b00000000000000000000000000000000), // (terminated), + .calbus_seq_param_tbl_15 (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated), + .vji_ir_in (2'b00), // (terminated), + .vji_ir_out (), // (terminated), + .vji_jtag_state_rti (1'b0), // (terminated), + .vji_tck (1'b0), // (terminated), + .vji_tdi (1'b0), // (terminated), + .vji_tdo (), // (terminated), + .vji_virtual_state_cdr (1'b0), // (terminated), + .vji_virtual_state_sdr (1'b0), // (terminated), + .vji_virtual_state_udr (1'b0), // (terminated), + .vji_virtual_state_uir (1'b0) // (terminated), + ); + +endmodule diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/altera_emif_cal_iossm.sv b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/altera_emif_cal_iossm.sv new file mode 100644 index 0000000000..77526c72c0 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/altera_emif_cal_iossm.sv @@ -0,0 +1,494 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +module altera_emif_cal_iossm #( + // IOSSM parameters + parameter IOSSM_CODE_HEX_FILENAME = "", + parameter IOSSM_USE_MODEL = 1, + + parameter IOSSM_SIM_GPT_HEX_FILENAME = "", + parameter IOSSM_SYNTH_GPT_HEX_FILENAME = "", + parameter IOSSM_SIM_NIOS_PERIOD_PS = 0, + + // Debug Parameters + parameter USE_SYNTH_FOR_SIM = 0, + parameter DIAG_EXPORT_VJI = 0, + + // Port widths for core debug access + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + + // Port widths for core debug access + parameter PORT_CALBUS_ADDRESS_WIDTH = 1, + parameter PORT_CALBUS_WDATA_WIDTH = 1, + parameter PORT_CALBUS_RDATA_WIDTH = 1, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 1, + + + // Global param table data + parameter SEQ_GPT_GLOBAL_PAR_VER = 0, + parameter SEQ_GPT_NIOS_C_VER = 0, + parameter SEQ_GPT_COLUMN_ID = 0, + parameter SEQ_GPT_NUM_IOPACKS = 0, + parameter SEQ_GPT_NIOS_CLK_FREQ_KHZ = 0, + parameter SEQ_GPT_PARAM_TABLE_SIZE = 0, + parameter SEQ_GPT_GLOBAL_SKIP_STEPS = 0, + parameter SEQ_GPT_GLOBAL_CAL_CONFIG = 0, + parameter SEQ_GPT_SLAVE_CLK_DIVIDER = 0, + + parameter SEQ_USE_SIM_PARAMS = "", + parameter SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ = 0, + parameter SIM_SEQ_GPT_GLOBAL_SKIP_STEPS = 0, + + // Hard-Nios debug ports + parameter PORT_VJI_IR_IN_WIDTH = 1, + parameter PORT_VJI_IR_OUT_WIDTH = 1, + + // Enable/disable Abstract PHY + parameter NUM_CALBUS_USED = 1, + parameter USE_SOFT_NIOS = 0 +) ( + + // EMIF calibration bus interfaces + output logic calbus_clk, + + output logic calbus_read_0, + output logic calbus_write_0, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_0, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_0, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_0, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_0, + + output logic calbus_read_1, + output logic calbus_write_1, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_1, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_1, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_1, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_1, + + output logic calbus_read_2, + output logic calbus_write_2, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_2, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_2, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_2, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_2, + + output logic calbus_read_3, + output logic calbus_write_3, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_3, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_3, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_3, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_3, + + output logic calbus_read_4, + output logic calbus_write_4, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_4, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_4, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_4, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_4, + + output logic calbus_read_5, + output logic calbus_write_5, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_5, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_5, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_5, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_5, + + output logic calbus_read_6, + output logic calbus_write_6, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_6, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_6, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_6, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_6, + + output logic calbus_read_7, + output logic calbus_write_7, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_7, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_7, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_7, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_7, + + output logic calbus_read_8, + output logic calbus_write_8, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_8, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_8, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_8, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_8, + + output logic calbus_read_9, + output logic calbus_write_9, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_9, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_9, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_9, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_9, + + output logic calbus_read_10, + output logic calbus_write_10, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_10, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_10, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_10, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_10, + + output logic calbus_read_11, + output logic calbus_write_11, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_11, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_11, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_11, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_11, + + output logic calbus_read_12, + output logic calbus_write_12, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_12, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_12, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_12, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_12, + + output logic calbus_read_13, + output logic calbus_write_13, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_13, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_13, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_13, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_13, + + output logic calbus_read_14, + output logic calbus_write_14, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_14, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_14, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_14, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_14, + + output logic calbus_read_15, + output logic calbus_write_15, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_15, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_15, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_15, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_15, + + // Input clock/reset intended for core logic connected to the Avalon slave port of the sequencer CPU. + // The "out" clock/reset is intended for daisy-chaining logic from multiple interfaces. + // Ports for "cal_debug" interface + input logic cal_debug_clk, + input logic cal_debug_reset_n, + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + // Hard-Nios debug port + input logic [1:0] vji_ir_in, + output logic [1:0] vji_ir_out, + input logic vji_jtag_state_rti, + input logic vji_tck, + input logic vji_tdi, + output logic vji_tdo, + input logic vji_virtual_state_cdr, + input logic vji_virtual_state_sdr, + input logic vji_virtual_state_udr, + input logic vji_virtual_state_uir +); + timeunit 1ns; + timeprecision 1ps; + + // Derive localparam values + + // Typically we synthesize full-calibration behavior for hardware, + // except when USE_SYNTH_FOR_SIM is set, which allows flows such + // as post-fit simulation to adopt RTL simulation behavior. + localparam REMAP_IOSSM_GPT_HEX_FILENAME = (SEQ_USE_SIM_PARAMS == "on") ? IOSSM_SIM_GPT_HEX_FILENAME : ( + (USE_SYNTH_FOR_SIM) ? IOSSM_SIM_GPT_HEX_FILENAME : IOSSM_SYNTH_GPT_HEX_FILENAME ); + localparam REMAP_SEQ_GPT_NIOS_CLK_FREQ_KHZ = (SEQ_USE_SIM_PARAMS == "on") ? SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ : ( + (USE_SYNTH_FOR_SIM) ? SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ : SEQ_GPT_NIOS_CLK_FREQ_KHZ ); + localparam REMAP_SEQ_GPT_GLOBAL_SKIP_STEPS = (SEQ_USE_SIM_PARAMS == "on") ? SIM_SEQ_GPT_GLOBAL_SKIP_STEPS : ( + (USE_SYNTH_FOR_SIM) ? SIM_SEQ_GPT_GLOBAL_SKIP_STEPS : SEQ_GPT_GLOBAL_SKIP_STEPS ); + + wire w_vji_cdr_to_the_hard_nios; + wire [ 1: 0] w_vji_ir_in_to_the_hard_nios; + wire w_vji_rti_to_the_hard_nios; + wire w_vji_sdr_to_the_hard_nios; + wire w_vji_tck_to_the_hard_nios; + wire w_vji_tdi_to_the_hard_nios; + wire w_vji_udr_to_the_hard_nios; + wire w_vji_uir_to_the_hard_nios; + + wire [ 1: 0] w_sld_vji_ir_out_from_the_hard_nios; + wire w_sld_vji_tdo_from_the_hard_nios; + wire [ 1: 0] w_vji_ir_out_from_the_hard_nios; + wire w_vji_tdo_from_the_hard_nios; + + wire [15:0][PORT_CALBUS_WDATA_WIDTH-1:0] calbus_rdata_i; + wire [15:0][PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_i; + + logic [7:0] soft_nios_read_data; + logic soft_nios_rdata_valid_n; + logic soft_nios_waitrequest_n; + + logic soft_nios_read; + logic soft_nios_write; + logic soft_nios_byteenable; + logic [7:0] soft_nios_write_data; + logic [6:0] soft_nios_address; + + + generate if (USE_SOFT_NIOS != 0) begin + altera_emif_f2c_gearbox #( + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH) + ) f2c_gearbox_inst ( + .clk (cal_debug_clk), + .reset_n (cal_debug_reset_n), + + .cal_debug_addr (cal_debug_addr), + .cal_debug_byteenable (cal_debug_byteenable), + .cal_debug_read (cal_debug_read), + .cal_debug_write (cal_debug_write), + .cal_debug_write_data (cal_debug_write_data), + + .cal_debug_read_data (cal_debug_read_data), + .cal_debug_read_data_valid(cal_debug_read_data_valid), + .cal_debug_waitrequest (cal_debug_waitrequest), + + .soft_nios_read_data (soft_nios_read_data), + .soft_nios_rdata_valid_n (soft_nios_rdata_valid_n), + .soft_nios_waitrequest_n (soft_nios_waitrequest_n), + + .soft_nios_read (soft_nios_read), + .soft_nios_write (soft_nios_write), + .soft_nios_byteenable (soft_nios_byteenable), + .soft_nios_write_data (soft_nios_write_data), + .soft_nios_address (soft_nios_address) + ); + end else begin + assign soft_nios_address = 7'd0; + assign soft_nios_byteenable = 1'b0; + assign soft_nios_write_data = 8'd0; + assign soft_nios_read = 1'b0; + assign soft_nios_write = 1'b0; + assign cal_debug_read_data = '0; + assign cal_debug_read_data_valid = '0; + assign cal_debug_waitrequest = '0; + end + endgenerate + + assign calbus_rdata_i[0] = (NUM_CALBUS_USED > 0) ? calbus_rdata_0 : 'd0; + assign calbus_seq_param_tbl_i[0] = (NUM_CALBUS_USED > 0) ? calbus_seq_param_tbl_0 : 'd0; + assign calbus_rdata_i[1] = (NUM_CALBUS_USED > 1) ? calbus_rdata_1 : 'd0; + assign calbus_seq_param_tbl_i[1] = (NUM_CALBUS_USED > 1) ? calbus_seq_param_tbl_1 : 'd0; + assign calbus_rdata_i[2] = (NUM_CALBUS_USED > 2) ? calbus_rdata_2 : 'd0; + assign calbus_seq_param_tbl_i[2] = (NUM_CALBUS_USED > 2) ? calbus_seq_param_tbl_2 : 'd0; + assign calbus_rdata_i[3] = (NUM_CALBUS_USED > 3) ? calbus_rdata_3 : 'd0; + assign calbus_seq_param_tbl_i[3] = (NUM_CALBUS_USED > 3) ? calbus_seq_param_tbl_3 : 'd0; + assign calbus_rdata_i[4] = (NUM_CALBUS_USED > 4) ? calbus_rdata_4 : 'd0; + assign calbus_seq_param_tbl_i[4] = (NUM_CALBUS_USED > 4) ? calbus_seq_param_tbl_4 : 'd0; + assign calbus_rdata_i[5] = (NUM_CALBUS_USED > 5) ? calbus_rdata_5 : 'd0; + assign calbus_seq_param_tbl_i[5] = (NUM_CALBUS_USED > 5) ? calbus_seq_param_tbl_5 : 'd0; + assign calbus_rdata_i[6] = (NUM_CALBUS_USED > 6) ? calbus_rdata_6 : 'd0; + assign calbus_seq_param_tbl_i[6] = (NUM_CALBUS_USED > 6) ? calbus_seq_param_tbl_6 : 'd0; + assign calbus_rdata_i[7] = (NUM_CALBUS_USED > 7) ? calbus_rdata_7 : 'd0; + assign calbus_seq_param_tbl_i[7] = (NUM_CALBUS_USED > 7) ? calbus_seq_param_tbl_7 : 'd0; + assign calbus_rdata_i[8] = (NUM_CALBUS_USED > 8) ? calbus_rdata_8 : 'd0; + assign calbus_seq_param_tbl_i[8] = (NUM_CALBUS_USED > 8) ? calbus_seq_param_tbl_8 : 'd0; + assign calbus_rdata_i[9] = (NUM_CALBUS_USED > 9) ? calbus_rdata_9 : 'd0; + assign calbus_seq_param_tbl_i[9] = (NUM_CALBUS_USED > 9) ? calbus_seq_param_tbl_9 : 'd0; + assign calbus_rdata_i[10] = (NUM_CALBUS_USED > 10) ? calbus_rdata_10 : 'd0; + assign calbus_seq_param_tbl_i[10] = (NUM_CALBUS_USED > 10) ? calbus_seq_param_tbl_10 : 'd0; + assign calbus_rdata_i[11] = (NUM_CALBUS_USED > 11) ? calbus_rdata_11 : 'd0; + assign calbus_seq_param_tbl_i[11] = (NUM_CALBUS_USED > 11) ? calbus_seq_param_tbl_11 : 'd0; + assign calbus_rdata_i[12] = (NUM_CALBUS_USED > 12) ? calbus_rdata_12 : 'd0; + assign calbus_seq_param_tbl_i[12] = (NUM_CALBUS_USED > 12) ? calbus_seq_param_tbl_12 : 'd0; + assign calbus_rdata_i[13] = (NUM_CALBUS_USED > 13) ? calbus_rdata_13 : 'd0; + assign calbus_seq_param_tbl_i[13] = (NUM_CALBUS_USED > 13) ? calbus_seq_param_tbl_13 : 'd0; + assign calbus_rdata_i[14] = (NUM_CALBUS_USED > 14) ? calbus_rdata_14 : 'd0; + assign calbus_seq_param_tbl_i[14] = (NUM_CALBUS_USED > 14) ? calbus_seq_param_tbl_14 : 'd0; + assign calbus_rdata_i[15] = (NUM_CALBUS_USED > 15) ? calbus_rdata_15 : 'd0; + assign calbus_seq_param_tbl_i[15] = (NUM_CALBUS_USED > 15) ? calbus_seq_param_tbl_15 : 'd0; + + tennm_iossm # ( + .gpt_ver (SEQ_GPT_GLOBAL_PAR_VER), + .nios_ver (SEQ_GPT_NIOS_C_VER), + .col_id (SEQ_GPT_COLUMN_ID), + .num_iopacks (SEQ_GPT_NUM_IOPACKS), + .pt_size (SEQ_GPT_PARAM_TABLE_SIZE), + .cal_config (SEQ_GPT_GLOBAL_CAL_CONFIG), + .slave_clk_divider (SEQ_GPT_SLAVE_CLK_DIVIDER), + .nios_clk_freq (REMAP_SEQ_GPT_NIOS_CLK_FREQ_KHZ), + .skip_steps (REMAP_SEQ_GPT_GLOBAL_SKIP_STEPS), + .parameter_table_hex_file (REMAP_IOSSM_GPT_HEX_FILENAME), + + .abstract_phy ("false"), + .iossm_sim_clk_period_ps (IOSSM_SIM_NIOS_PERIOD_PS), + .nios_calibration_code_hex_file(IOSSM_CODE_HEX_FILENAME), + .iossm_use_model (IOSSM_USE_MODEL) + ) io_ssm ( + .soft_nios_irq (4'b0), + .soft_nios_address (soft_nios_address), + .soft_nios_byteenable (soft_nios_byteenable), + .soft_nios_clk (cal_debug_clk), + .soft_nios_read (soft_nios_read), + .soft_nios_write (soft_nios_write), + .soft_nios_write_data (soft_nios_write_data), + .soft_nios_read_data (soft_nios_read_data), + .soft_nios_rdata_valid (soft_nios_rdata_valid_n), + .soft_nios_waitrequest (soft_nios_waitrequest_n), + + // IO Subsystem Calibration Bus + .calbus_clock (calbus_clk), + + .calbus_read_0 (calbus_read_0), + .calbus_write_0 (calbus_write_0), + .calbus_address_0 (calbus_address_0), + .calbus_wdata_0 (calbus_wdata_0), + .calbus_rdata_0 (calbus_rdata_i[0]), + .calbus_param_tbl_0 (calbus_seq_param_tbl_i[0]), + + .calbus_read_1 (calbus_read_1), + .calbus_write_1 (calbus_write_1), + .calbus_address_1 (calbus_address_1), + .calbus_wdata_1 (calbus_wdata_1), + .calbus_rdata_1 (calbus_rdata_i[1]), + .calbus_param_tbl_1 (calbus_seq_param_tbl_i[1]), + + .calbus_read_2 (calbus_read_2), + .calbus_write_2 (calbus_write_2), + .calbus_address_2 (calbus_address_2), + .calbus_wdata_2 (calbus_wdata_2), + .calbus_rdata_2 (calbus_rdata_i[2]), + .calbus_param_tbl_2 (calbus_seq_param_tbl_i[2]), + + .calbus_read_3 (calbus_read_3), + .calbus_write_3 (calbus_write_3), + .calbus_address_3 (calbus_address_3), + .calbus_wdata_3 (calbus_wdata_3), + .calbus_rdata_3 (calbus_rdata_i[3]), + .calbus_param_tbl_3 (calbus_seq_param_tbl_i[3]), + + .calbus_read_4 (calbus_read_4), + .calbus_write_4 (calbus_write_4), + .calbus_address_4 (calbus_address_4), + .calbus_wdata_4 (calbus_wdata_4), + .calbus_rdata_4 (calbus_rdata_i[4]), + .calbus_param_tbl_4 (calbus_seq_param_tbl_i[4]), + + .calbus_read_5 (calbus_read_5), + .calbus_write_5 (calbus_write_5), + .calbus_address_5 (calbus_address_5), + .calbus_wdata_5 (calbus_wdata_5), + .calbus_rdata_5 (calbus_rdata_i[5]), + .calbus_param_tbl_5 (calbus_seq_param_tbl_i[5]), + + .calbus_read_6 (calbus_read_6), + .calbus_write_6 (calbus_write_6), + .calbus_address_6 (calbus_address_6), + .calbus_wdata_6 (calbus_wdata_6), + .calbus_rdata_6 (calbus_rdata_i[6]), + .calbus_param_tbl_6 (calbus_seq_param_tbl_i[6]), + + .calbus_read_7 (calbus_read_7), + .calbus_write_7 (calbus_write_7), + .calbus_address_7 (calbus_address_7), + .calbus_wdata_7 (calbus_wdata_7), + .calbus_rdata_7 (calbus_rdata_i[7]), + .calbus_param_tbl_7 (calbus_seq_param_tbl_i[7]), + + .calbus_read_8 (calbus_read_8), + .calbus_write_8 (calbus_write_8), + .calbus_address_8 (calbus_address_8), + .calbus_wdata_8 (calbus_wdata_8), + .calbus_rdata_8 (calbus_rdata_i[8]), + .calbus_param_tbl_8 (calbus_seq_param_tbl_i[8]), + + .calbus_read_9 (calbus_read_9), + .calbus_write_9 (calbus_write_9), + .calbus_address_9 (calbus_address_9), + .calbus_wdata_9 (calbus_wdata_9), + .calbus_rdata_9 (calbus_rdata_i[9]), + .calbus_param_tbl_9 (calbus_seq_param_tbl_i[9]), + + .calbus_read_10 (calbus_read_10), + .calbus_write_10 (calbus_write_10), + .calbus_address_10 (calbus_address_10), + .calbus_wdata_10 (calbus_wdata_10), + .calbus_rdata_10 (calbus_rdata_i[10]), + .calbus_param_tbl_10 (calbus_seq_param_tbl_i[10]), + + .calbus_read_11 (calbus_read_11), + .calbus_write_11 (calbus_write_11), + .calbus_address_11 (calbus_address_11), + .calbus_wdata_11 (calbus_wdata_11), + .calbus_rdata_11 (calbus_rdata_i[11]), + .calbus_param_tbl_11 (calbus_seq_param_tbl_i[11]), + + .calbus_read_12 (calbus_read_12), + .calbus_write_12 (calbus_write_12), + .calbus_address_12 (calbus_address_12), + .calbus_wdata_12 (calbus_wdata_12), + .calbus_rdata_12 (calbus_rdata_i[12]), + .calbus_param_tbl_12 (calbus_seq_param_tbl_i[12]), + + .calbus_read_13 (calbus_read_13), + .calbus_write_13 (calbus_write_13), + .calbus_address_13 (calbus_address_13), + .calbus_wdata_13 (calbus_wdata_13), + .calbus_rdata_13 (calbus_rdata_i[13]), + .calbus_param_tbl_13 (calbus_seq_param_tbl_i[13]), + + .calbus_read_14 (calbus_read_14), + .calbus_write_14 (calbus_write_14), + .calbus_address_14 (calbus_address_14), + .calbus_wdata_14 (calbus_wdata_14), + .calbus_rdata_14 (calbus_rdata_i[14]), + .calbus_param_tbl_14 (calbus_seq_param_tbl_i[14]), + + .calbus_read_15 (calbus_read_15), + .calbus_write_15 (calbus_write_15), + .calbus_address_15 (calbus_address_15), + .calbus_wdata_15 (calbus_wdata_15), + .calbus_rdata_15 (calbus_rdata_i[15]), + .calbus_param_tbl_15 (calbus_seq_param_tbl_i[15]), + + // IO Subsystem Calibration Bus + .vji_cdr_to_the_hard_nios (w_vji_cdr_to_the_hard_nios), + .vji_ir_in_to_the_hard_nios (w_vji_ir_in_to_the_hard_nios), + .vji_rti_to_the_hard_nios (w_vji_rti_to_the_hard_nios), + .vji_sdr_to_the_hard_nios (w_vji_sdr_to_the_hard_nios), + .vji_tck_to_the_hard_nios (w_vji_tck_to_the_hard_nios), + .vji_tdi_to_the_hard_nios (w_vji_tdi_to_the_hard_nios), + .vji_udr_to_the_hard_nios (w_vji_udr_to_the_hard_nios), + .vji_uir_to_the_hard_nios (w_vji_uir_to_the_hard_nios), + .vji_ir_out_from_the_hard_nios (w_vji_ir_out_from_the_hard_nios), + .vji_tdo_from_the_hard_nios (w_vji_tdo_from_the_hard_nios) + ); + + assign w_vji_cdr_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_cdr : 1'b0; + assign w_vji_ir_in_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_ir_in : 2'b00; + assign w_vji_rti_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_jtag_state_rti : 1'b0; + assign w_vji_sdr_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_sdr : 1'b0; + assign w_vji_tck_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_tck : 1'b0; + assign w_vji_tdi_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_tdi : 1'b0; + assign w_vji_udr_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_udr : 1'b0; + assign w_vji_uir_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_uir : 1'b0; + assign vji_ir_out = DIAG_EXPORT_VJI ? w_vji_ir_out_from_the_hard_nios : 2'b0; + assign vji_tdo = DIAG_EXPORT_VJI ? w_vji_tdo_from_the_hard_nios : 1'b0; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0ECj3HSUaZMQdsHOEoejOcwJ2RhJ9P4QDVEXGenDAmBQiJAPz6SAV4DqS0an68FB0ZOw3u6Fz9ZnsNCxHESqqKIhmHXeOOJqT0TMS7OxARNfiGSYsGZkXP2aOsQbPMyMl9Na0FpG3tX2nCq+YzVLsQyswtPgjPY/GO4ZMgPdYdp5JKSfreaxYuiLxTeDp4puFh9fP23Bzc62FleY5N14rrOPKFwR+NKcP0ZnDKesfQUGVQgHNDWd+yn8MPE4yKAFnC5UhP6/1eV6IVnPI3KCE7+1uvsrcyVo72I9ZjECteGSwb7zUBuIknMGGJLamSDccEEzp3d9zoNmEWwYEsAQ6sfJVbzrvs9dqrDzmsgVd7rsFQsAaIXZPlOjRlQJBcoDI69G4leYK9upuWONmbxZPwESZDMmSech7WRSR+Pfg8IhH2pcuaqwx+Flyt8/fEZd1nHHn/r7IbrV7vPwpWv6bwfQE4+LOlUxGkicqW/zIbwPWua1Y1pF8kRl1B24DA9A2PuASSdsPDi8qf8524t2r4XrzPEfPSuA4z8fLDKNUZ6WPPatW6xFtOpQrgjniprbGZ5Cdzlihkh1KGZUQFWqGWG9vSMwb1XceNsZWsR1lhRieIwEpGXGARM7U6MnIf+7MlzH137TXgbWLPIOwNuFNQ1W5TQen1Ntb084V6b8dzDtE07gYYf8X3PH/73It0UuW5x0UXD6aSiIv+qp+H4rdL0sTo4SHIb8muoxzrwI7lCZtReafd6NvK5+I9wtZd+IdKqB6WabzhHQoHFJnu4BF4Z7" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/altera_emif_f2c_gearbox.sv b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/altera_emif_f2c_gearbox.sv new file mode 100644 index 0000000000..bb556d9e91 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/altera_emif_f2c_gearbox.sv @@ -0,0 +1,152 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +/////////////////////////////////////////////////////////////////////////////// +// This module implements the gearbox logic to compress the number of wire +// connections to the IOSSM debug port. +// +/////////////////////////////////////////////////////////////////////////////// + +module altera_emif_f2c_gearbox #( + // Port widths for core debug access + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1 +) ( + input logic clk, + input logic reset_n, + + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + input logic [7:0] soft_nios_read_data, + input logic soft_nios_rdata_valid_n, + input logic soft_nios_waitrequest_n, + + output logic soft_nios_read, + output logic soft_nios_write, + output logic soft_nios_byteenable, + output logic [7:0] soft_nios_write_data, + output logic [6:0] soft_nios_address +); + timeunit 1ps; + timeprecision 1ps; + + typedef enum logic [2:0] { + F2C_IDLE = 3'b000, + F2C_WAIT = 3'b001, + F2C_CMD = 3'b010, + F2C_RDATA= 3'b100 + } f2c_state_t; + + localparam F2C_RDATA_SHIFT_CNT = PORT_CAL_DEBUG_RDATA_WIDTH / 8; + localparam F2C_CMD_SHIFT_CNT = PORT_CAL_DEBUG_BYTEEN_WIDTH; + + logic f2c_cmd_valid; + logic f2c_cmd_rnw; + logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] f2c_cmd_addr; + logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] f2c_byteenable; + logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] f2c_write_data; + logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] f2c_read_data; + + logic [3:0] f2c_cmd_shift; + logic [3:0] f2c_data_shift; + + logic f2c_cmd_done; + logic f2c_rdata_done; + logic f2c_cmd_carry_out; + logic f2c_data_carry_out; + + f2c_state_t f2c_state /* synthesis ignore_power_up */; + + always_ff @(posedge clk, negedge reset_n) begin + if (!reset_n) + f2c_state <= F2C_IDLE; + else begin + case (f2c_state) + F2C_IDLE: + if (cal_debug_read | cal_debug_write) + f2c_state <= F2C_WAIT; + F2C_WAIT: + if (~soft_nios_waitrequest_n) + f2c_state <= F2C_CMD; + F2C_CMD: + if (f2c_cmd_done) + f2c_state <= f2c_cmd_rnw ? F2C_RDATA : F2C_IDLE; + F2C_RDATA: + if (f2c_rdata_done) + f2c_state <= F2C_IDLE; + default: + f2c_state <= F2C_IDLE; + endcase + end + end + + always_ff @(posedge clk, negedge reset_n) begin + if (!reset_n) begin + f2c_cmd_rnw <= 1'b0; + f2c_cmd_addr <= 'b0; + f2c_byteenable <= 'b0; + f2c_write_data <= 'b0; + f2c_cmd_shift <= 'b0; + f2c_data_shift <= 'b0; + end else if (f2c_state == F2C_IDLE) begin + f2c_cmd_rnw <= cal_debug_read; + f2c_cmd_addr <= cal_debug_addr; + f2c_byteenable <= cal_debug_byteenable; + f2c_write_data <= cal_debug_write_data; + f2c_cmd_shift <= 'b0; + f2c_data_shift <= 'b0; + end else if (f2c_state == F2C_CMD) begin + {f2c_cmd_carry_out, f2c_cmd_shift} <= f2c_cmd_shift + 1; + f2c_cmd_addr <= {7'b0,f2c_cmd_addr [PORT_CAL_DEBUG_ADDRESS_WIDTH - 1 : 7]}; + f2c_byteenable <= {1'b0,f2c_byteenable [PORT_CAL_DEBUG_BYTEEN_WIDTH - 1 : 1]}; + f2c_write_data <= {8'b0,f2c_write_data [PORT_CAL_DEBUG_WDATA_WIDTH - 1 : 8]}; + end else if (f2c_state == F2C_RDATA && ~soft_nios_rdata_valid_n) begin + {f2c_data_carry_out, f2c_data_shift} <= f2c_data_shift + 1; + f2c_read_data <= {soft_nios_read_data, f2c_read_data[PORT_CAL_DEBUG_RDATA_WIDTH - 1 : 8]}; + end + end + + always_ff @(posedge clk, negedge reset_n) begin + if (!reset_n) + cal_debug_read_data_valid <= 1'b0; + else + cal_debug_read_data_valid <= f2c_rdata_done; + end + + assign f2c_cmd_valid = f2c_state == F2C_CMD; + assign f2c_cmd_done = f2c_cmd_shift == (F2C_CMD_SHIFT_CNT - 1); + assign f2c_rdata_done = f2c_data_shift == (F2C_RDATA_SHIFT_CNT - 1); + + assign soft_nios_read = f2c_cmd_valid & f2c_cmd_rnw; + assign soft_nios_write = f2c_cmd_valid & ~f2c_cmd_rnw; + assign soft_nios_byteenable = f2c_byteenable [0]; + assign soft_nios_write_data = f2c_write_data [7:0]; + assign soft_nios_address = f2c_cmd_addr [6:0]; + + assign cal_debug_waitrequest = f2c_state != F2C_IDLE; + assign cal_debug_read_data = f2c_read_data; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0EBIioGIcwebGLngzwkT26A7K1SYyh9Dtiac9CerfvFZcK7Sg5dxGmob6a6YHlOjHgxgTAJfWGmg9lJmaH2CWRDnu0TGIto6A0JDLdyo1DDH4xDr12EuwtDrBAjsPgqUebpmVU1ybjm4TYcJj/AMqFqoU5LxerYQ2a99pjJ/ssQDQLWyooHVX74eCxsTnmMuPm/aoYF2IrWT+TN8zan+zKrydptRlQ7eRZZkOvOIadDHLBkEYfQFijyq0W8punO2tFyECjnB3RTgfEeHEXC3apKnn7ek5S5rKJ6RT9hyYVDxJC85a/LaLIrobdZQHtV+QGL0ZS28XJ4yVZ9OLSc5QHLUG1djNtoEbZ7GFeGXurxO4efq+Dg5T9s/FTdouXm/oo5a2hGYAJQE0W3a73xlwhdsszCM3Ml+7+xjCpdcUl2bLcfM+tvIvIeTH+cijMGf6OZL47JY2IogcSd8deavB6h+4WNun4kDom0YSBWepSH/kEWP7/Gz7uI9hxyO3N8gh/PIyO8tvg1ALVEgiTwIeergUGRwuDC9o9m4otU97aiHGDeyBMwTGZ2Jm2DOTBTLvTf5jFnsznVrPoqJWTFqWtvTr3+e3eW+Y+V6CyFzP1Zwj/QIuH5wXJ6RVZSmfuZKgyUwMkjYrlQzjtTYmDjthbxv+sJ+LFLW18jyTpt96JNjn9JKmIlFFt/sTVgRsLqU5sOAHSQuZiHxIkAjRccPG8dHmpXKS9G3jDSAa9fju7CtRnXvXJrjUWjEfqG6FF1Rz5c5PrQyCiLTiTyMkodlMzKQ" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq.sv b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq.sv new file mode 100644 index 0000000000..bd59e2da4f --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq.sv @@ -0,0 +1,300 @@ +module emif_cal_altera_emif_cal_iossm_274_yagv7fq #( + parameter NUM_CALBUS_USED = 0, + parameter IOSSM_USE_MODEL = 0, + parameter USE_SYNTH_FOR_SIM = 0, + parameter USE_SOFT_NIOS = 0, + parameter IOSSM_SIM_NIOS_PERIOD_PS = 0, + parameter SEQ_GPT_GLOBAL_PAR_VER = 0, + parameter SEQ_GPT_NIOS_C_VER = 0, + parameter SEQ_GPT_COLUMN_ID = 0, + parameter SEQ_GPT_NUM_IOPACKS = 0, + parameter SEQ_GPT_NIOS_CLK_FREQ_KHZ = 0, + parameter SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ = 0, + parameter SEQ_GPT_PARAM_TABLE_SIZE = 0, + parameter SEQ_GPT_GLOBAL_SKIP_STEPS = 0, + parameter SIM_SEQ_GPT_GLOBAL_SKIP_STEPS = 0, + parameter SEQ_GPT_GLOBAL_CAL_CONFIG = 0, + parameter SEQ_GPT_SLAVE_CLK_DIVIDER = 0, + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 0, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 0, + parameter PORT_CALBUS_ADDRESS_WIDTH = 0, + parameter PORT_CALBUS_WDATA_WIDTH = 0, + parameter PORT_CALBUS_RDATA_WIDTH = 0, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 0, + parameter PORT_VJI_IR_IN_WIDTH = 0, + parameter PORT_VJI_IR_OUT_WIDTH = 0 +) ( + output logic cal_debug_waitrequest, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [26:0] cal_debug_addr, + output logic [31:0] cal_debug_read_data, + input logic [31:0] cal_debug_write_data, + input logic [3:0] cal_debug_byteenable, + output logic cal_debug_read_data_valid, + input logic cal_debug_clk, + input logic cal_debug_reset_n, + output logic calbus_read_0, + output logic calbus_write_0, + output logic [19:0] calbus_address_0, + output logic [31:0] calbus_wdata_0, + input logic [31:0] calbus_rdata_0, + input logic [4095:0] calbus_seq_param_tbl_0, + output logic calbus_read_1, + output logic calbus_write_1, + output logic [19:0] calbus_address_1, + output logic [31:0] calbus_wdata_1, + input logic [31:0] calbus_rdata_1, + input logic [4095:0] calbus_seq_param_tbl_1, + output logic calbus_read_2, + output logic calbus_write_2, + output logic [19:0] calbus_address_2, + output logic [31:0] calbus_wdata_2, + input logic [31:0] calbus_rdata_2, + input logic [4095:0] calbus_seq_param_tbl_2, + output logic calbus_read_3, + output logic calbus_write_3, + output logic [19:0] calbus_address_3, + output logic [31:0] calbus_wdata_3, + input logic [31:0] calbus_rdata_3, + input logic [4095:0] calbus_seq_param_tbl_3, + output logic calbus_read_4, + output logic calbus_write_4, + output logic [19:0] calbus_address_4, + output logic [31:0] calbus_wdata_4, + input logic [31:0] calbus_rdata_4, + input logic [4095:0] calbus_seq_param_tbl_4, + output logic calbus_read_5, + output logic calbus_write_5, + output logic [19:0] calbus_address_5, + output logic [31:0] calbus_wdata_5, + input logic [31:0] calbus_rdata_5, + input logic [4095:0] calbus_seq_param_tbl_5, + output logic calbus_read_6, + output logic calbus_write_6, + output logic [19:0] calbus_address_6, + output logic [31:0] calbus_wdata_6, + input logic [31:0] calbus_rdata_6, + input logic [4095:0] calbus_seq_param_tbl_6, + output logic calbus_read_7, + output logic calbus_write_7, + output logic [19:0] calbus_address_7, + output logic [31:0] calbus_wdata_7, + input logic [31:0] calbus_rdata_7, + input logic [4095:0] calbus_seq_param_tbl_7, + output logic calbus_read_8, + output logic calbus_write_8, + output logic [19:0] calbus_address_8, + output logic [31:0] calbus_wdata_8, + input logic [31:0] calbus_rdata_8, + input logic [4095:0] calbus_seq_param_tbl_8, + output logic calbus_read_9, + output logic calbus_write_9, + output logic [19:0] calbus_address_9, + output logic [31:0] calbus_wdata_9, + input logic [31:0] calbus_rdata_9, + input logic [4095:0] calbus_seq_param_tbl_9, + output logic calbus_read_10, + output logic calbus_write_10, + output logic [19:0] calbus_address_10, + output logic [31:0] calbus_wdata_10, + input logic [31:0] calbus_rdata_10, + input logic [4095:0] calbus_seq_param_tbl_10, + output logic calbus_read_11, + output logic calbus_write_11, + output logic [19:0] calbus_address_11, + output logic [31:0] calbus_wdata_11, + input logic [31:0] calbus_rdata_11, + input logic [4095:0] calbus_seq_param_tbl_11, + output logic calbus_read_12, + output logic calbus_write_12, + output logic [19:0] calbus_address_12, + output logic [31:0] calbus_wdata_12, + input logic [31:0] calbus_rdata_12, + input logic [4095:0] calbus_seq_param_tbl_12, + output logic calbus_read_13, + output logic calbus_write_13, + output logic [19:0] calbus_address_13, + output logic [31:0] calbus_wdata_13, + input logic [31:0] calbus_rdata_13, + input logic [4095:0] calbus_seq_param_tbl_13, + output logic calbus_read_14, + output logic calbus_write_14, + output logic [19:0] calbus_address_14, + output logic [31:0] calbus_wdata_14, + input logic [31:0] calbus_rdata_14, + input logic [4095:0] calbus_seq_param_tbl_14, + output logic calbus_read_15, + output logic calbus_write_15, + output logic [19:0] calbus_address_15, + output logic [31:0] calbus_wdata_15, + input logic [31:0] calbus_rdata_15, + input logic [4095:0] calbus_seq_param_tbl_15, + output logic calbus_clk, + input logic [1:0] vji_ir_in, + output logic [1:0] vji_ir_out, + input logic vji_jtag_state_rti, + input logic vji_tck, + input logic vji_tdi, + output logic vji_tdo, + input logic vji_virtual_state_cdr, + input logic vji_virtual_state_sdr, + input logic vji_virtual_state_udr, + input logic vji_virtual_state_uir +); + timeunit 1ns; + timeprecision 1ps; + + emif_cal_altera_emif_cal_iossm_274_yagv7fq_arch # ( + .NUM_CALBUS_USED (NUM_CALBUS_USED), + .IOSSM_USE_MODEL (IOSSM_USE_MODEL), + .USE_SYNTH_FOR_SIM (USE_SYNTH_FOR_SIM), + .USE_SOFT_NIOS (USE_SOFT_NIOS), + .IOSSM_SIM_NIOS_PERIOD_PS (IOSSM_SIM_NIOS_PERIOD_PS), + .SEQ_GPT_GLOBAL_PAR_VER (SEQ_GPT_GLOBAL_PAR_VER), + .SEQ_GPT_NIOS_C_VER (SEQ_GPT_NIOS_C_VER), + .SEQ_GPT_COLUMN_ID (SEQ_GPT_COLUMN_ID), + .SEQ_GPT_NUM_IOPACKS (SEQ_GPT_NUM_IOPACKS), + .SEQ_GPT_NIOS_CLK_FREQ_KHZ (SEQ_GPT_NIOS_CLK_FREQ_KHZ), + .SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ (SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ), + .SEQ_GPT_PARAM_TABLE_SIZE (SEQ_GPT_PARAM_TABLE_SIZE), + .SEQ_GPT_GLOBAL_SKIP_STEPS (SEQ_GPT_GLOBAL_SKIP_STEPS), + .SIM_SEQ_GPT_GLOBAL_SKIP_STEPS (SIM_SEQ_GPT_GLOBAL_SKIP_STEPS), + .SEQ_GPT_GLOBAL_CAL_CONFIG (SEQ_GPT_GLOBAL_CAL_CONFIG), + .SEQ_GPT_SLAVE_CLK_DIVIDER (SEQ_GPT_SLAVE_CLK_DIVIDER), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CALBUS_ADDRESS_WIDTH (PORT_CALBUS_ADDRESS_WIDTH), + .PORT_CALBUS_WDATA_WIDTH (PORT_CALBUS_WDATA_WIDTH), + .PORT_CALBUS_RDATA_WIDTH (PORT_CALBUS_RDATA_WIDTH), + .PORT_CALBUS_SEQ_PARAM_TBL_WIDTH (PORT_CALBUS_SEQ_PARAM_TBL_WIDTH), + .PORT_VJI_IR_IN_WIDTH (PORT_VJI_IR_IN_WIDTH), + .PORT_VJI_IR_OUT_WIDTH (PORT_VJI_IR_OUT_WIDTH), + .SEQ_USE_SIM_PARAMS ("off"), + .IOSSM_CODE_HEX_FILENAME ("emif_cal_altera_emif_cal_iossm_274_yagv7fq_code.hex"), + .IOSSM_SIM_GPT_HEX_FILENAME ("emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.hex"), + .IOSSM_SYNTH_GPT_HEX_FILENAME ("emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.hex") + ) arch_inst ( + .cal_debug_waitrequest (cal_debug_waitrequest), + .cal_debug_read (cal_debug_read), + .cal_debug_write (cal_debug_write), + .cal_debug_addr (cal_debug_addr), + .cal_debug_read_data (cal_debug_read_data), + .cal_debug_write_data (cal_debug_write_data), + .cal_debug_byteenable (cal_debug_byteenable), + .cal_debug_read_data_valid (cal_debug_read_data_valid), + .cal_debug_clk (cal_debug_clk), + .cal_debug_reset_n (cal_debug_reset_n), + .calbus_read_0 (calbus_read_0), + .calbus_write_0 (calbus_write_0), + .calbus_address_0 (calbus_address_0), + .calbus_wdata_0 (calbus_wdata_0), + .calbus_rdata_0 (calbus_rdata_0), + .calbus_seq_param_tbl_0 (calbus_seq_param_tbl_0), + .calbus_read_1 (calbus_read_1), + .calbus_write_1 (calbus_write_1), + .calbus_address_1 (calbus_address_1), + .calbus_wdata_1 (calbus_wdata_1), + .calbus_rdata_1 (calbus_rdata_1), + .calbus_seq_param_tbl_1 (calbus_seq_param_tbl_1), + .calbus_read_2 (calbus_read_2), + .calbus_write_2 (calbus_write_2), + .calbus_address_2 (calbus_address_2), + .calbus_wdata_2 (calbus_wdata_2), + .calbus_rdata_2 (calbus_rdata_2), + .calbus_seq_param_tbl_2 (calbus_seq_param_tbl_2), + .calbus_read_3 (calbus_read_3), + .calbus_write_3 (calbus_write_3), + .calbus_address_3 (calbus_address_3), + .calbus_wdata_3 (calbus_wdata_3), + .calbus_rdata_3 (calbus_rdata_3), + .calbus_seq_param_tbl_3 (calbus_seq_param_tbl_3), + .calbus_read_4 (calbus_read_4), + .calbus_write_4 (calbus_write_4), + .calbus_address_4 (calbus_address_4), + .calbus_wdata_4 (calbus_wdata_4), + .calbus_rdata_4 (calbus_rdata_4), + .calbus_seq_param_tbl_4 (calbus_seq_param_tbl_4), + .calbus_read_5 (calbus_read_5), + .calbus_write_5 (calbus_write_5), + .calbus_address_5 (calbus_address_5), + .calbus_wdata_5 (calbus_wdata_5), + .calbus_rdata_5 (calbus_rdata_5), + .calbus_seq_param_tbl_5 (calbus_seq_param_tbl_5), + .calbus_read_6 (calbus_read_6), + .calbus_write_6 (calbus_write_6), + .calbus_address_6 (calbus_address_6), + .calbus_wdata_6 (calbus_wdata_6), + .calbus_rdata_6 (calbus_rdata_6), + .calbus_seq_param_tbl_6 (calbus_seq_param_tbl_6), + .calbus_read_7 (calbus_read_7), + .calbus_write_7 (calbus_write_7), + .calbus_address_7 (calbus_address_7), + .calbus_wdata_7 (calbus_wdata_7), + .calbus_rdata_7 (calbus_rdata_7), + .calbus_seq_param_tbl_7 (calbus_seq_param_tbl_7), + .calbus_read_8 (calbus_read_8), + .calbus_write_8 (calbus_write_8), + .calbus_address_8 (calbus_address_8), + .calbus_wdata_8 (calbus_wdata_8), + .calbus_rdata_8 (calbus_rdata_8), + .calbus_seq_param_tbl_8 (calbus_seq_param_tbl_8), + .calbus_read_9 (calbus_read_9), + .calbus_write_9 (calbus_write_9), + .calbus_address_9 (calbus_address_9), + .calbus_wdata_9 (calbus_wdata_9), + .calbus_rdata_9 (calbus_rdata_9), + .calbus_seq_param_tbl_9 (calbus_seq_param_tbl_9), + .calbus_read_10 (calbus_read_10), + .calbus_write_10 (calbus_write_10), + .calbus_address_10 (calbus_address_10), + .calbus_wdata_10 (calbus_wdata_10), + .calbus_rdata_10 (calbus_rdata_10), + .calbus_seq_param_tbl_10 (calbus_seq_param_tbl_10), + .calbus_read_11 (calbus_read_11), + .calbus_write_11 (calbus_write_11), + .calbus_address_11 (calbus_address_11), + .calbus_wdata_11 (calbus_wdata_11), + .calbus_rdata_11 (calbus_rdata_11), + .calbus_seq_param_tbl_11 (calbus_seq_param_tbl_11), + .calbus_read_12 (calbus_read_12), + .calbus_write_12 (calbus_write_12), + .calbus_address_12 (calbus_address_12), + .calbus_wdata_12 (calbus_wdata_12), + .calbus_rdata_12 (calbus_rdata_12), + .calbus_seq_param_tbl_12 (calbus_seq_param_tbl_12), + .calbus_read_13 (calbus_read_13), + .calbus_write_13 (calbus_write_13), + .calbus_address_13 (calbus_address_13), + .calbus_wdata_13 (calbus_wdata_13), + .calbus_rdata_13 (calbus_rdata_13), + .calbus_seq_param_tbl_13 (calbus_seq_param_tbl_13), + .calbus_read_14 (calbus_read_14), + .calbus_write_14 (calbus_write_14), + .calbus_address_14 (calbus_address_14), + .calbus_wdata_14 (calbus_wdata_14), + .calbus_rdata_14 (calbus_rdata_14), + .calbus_seq_param_tbl_14 (calbus_seq_param_tbl_14), + .calbus_read_15 (calbus_read_15), + .calbus_write_15 (calbus_write_15), + .calbus_address_15 (calbus_address_15), + .calbus_wdata_15 (calbus_wdata_15), + .calbus_rdata_15 (calbus_rdata_15), + .calbus_seq_param_tbl_15 (calbus_seq_param_tbl_15), + .calbus_clk (calbus_clk), + .vji_ir_in (vji_ir_in), + .vji_ir_out (vji_ir_out), + .vji_jtag_state_rti (vji_jtag_state_rti), + .vji_tck (vji_tck), + .vji_tdi (vji_tdi), + .vji_tdo (vji_tdo), + .vji_virtual_state_cdr (vji_virtual_state_cdr), + .vji_virtual_state_sdr (vji_virtual_state_sdr), + .vji_virtual_state_udr (vji_virtual_state_udr), + .vji_virtual_state_uir (vji_virtual_state_uir) + ); +endmodule diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_arch.sv b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_arch.sv new file mode 100644 index 0000000000..829b09eb35 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_arch.sv @@ -0,0 +1,494 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +module emif_cal_altera_emif_cal_iossm_274_yagv7fq_arch #( + // IOSSM parameters + parameter IOSSM_CODE_HEX_FILENAME = "", + parameter IOSSM_USE_MODEL = 1, + + parameter IOSSM_SIM_GPT_HEX_FILENAME = "", + parameter IOSSM_SYNTH_GPT_HEX_FILENAME = "", + parameter IOSSM_SIM_NIOS_PERIOD_PS = 0, + + // Debug Parameters + parameter USE_SYNTH_FOR_SIM = 0, + parameter DIAG_EXPORT_VJI = 0, + + // Port widths for core debug access + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + + // Port widths for core debug access + parameter PORT_CALBUS_ADDRESS_WIDTH = 1, + parameter PORT_CALBUS_WDATA_WIDTH = 1, + parameter PORT_CALBUS_RDATA_WIDTH = 1, + parameter PORT_CALBUS_SEQ_PARAM_TBL_WIDTH = 1, + + + // Global param table data + parameter SEQ_GPT_GLOBAL_PAR_VER = 0, + parameter SEQ_GPT_NIOS_C_VER = 0, + parameter SEQ_GPT_COLUMN_ID = 0, + parameter SEQ_GPT_NUM_IOPACKS = 0, + parameter SEQ_GPT_NIOS_CLK_FREQ_KHZ = 0, + parameter SEQ_GPT_PARAM_TABLE_SIZE = 0, + parameter SEQ_GPT_GLOBAL_SKIP_STEPS = 0, + parameter SEQ_GPT_GLOBAL_CAL_CONFIG = 0, + parameter SEQ_GPT_SLAVE_CLK_DIVIDER = 0, + + parameter SEQ_USE_SIM_PARAMS = "", + parameter SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ = 0, + parameter SIM_SEQ_GPT_GLOBAL_SKIP_STEPS = 0, + + // Hard-Nios debug ports + parameter PORT_VJI_IR_IN_WIDTH = 1, + parameter PORT_VJI_IR_OUT_WIDTH = 1, + + // Enable/disable Abstract PHY + parameter NUM_CALBUS_USED = 1, + parameter USE_SOFT_NIOS = 0 +) ( + + // EMIF calibration bus interfaces + output logic calbus_clk, + + output logic calbus_read_0, + output logic calbus_write_0, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_0, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_0, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_0, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_0, + + output logic calbus_read_1, + output logic calbus_write_1, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_1, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_1, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_1, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_1, + + output logic calbus_read_2, + output logic calbus_write_2, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_2, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_2, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_2, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_2, + + output logic calbus_read_3, + output logic calbus_write_3, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_3, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_3, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_3, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_3, + + output logic calbus_read_4, + output logic calbus_write_4, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_4, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_4, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_4, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_4, + + output logic calbus_read_5, + output logic calbus_write_5, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_5, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_5, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_5, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_5, + + output logic calbus_read_6, + output logic calbus_write_6, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_6, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_6, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_6, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_6, + + output logic calbus_read_7, + output logic calbus_write_7, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_7, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_7, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_7, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_7, + + output logic calbus_read_8, + output logic calbus_write_8, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_8, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_8, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_8, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_8, + + output logic calbus_read_9, + output logic calbus_write_9, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_9, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_9, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_9, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_9, + + output logic calbus_read_10, + output logic calbus_write_10, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_10, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_10, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_10, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_10, + + output logic calbus_read_11, + output logic calbus_write_11, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_11, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_11, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_11, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_11, + + output logic calbus_read_12, + output logic calbus_write_12, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_12, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_12, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_12, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_12, + + output logic calbus_read_13, + output logic calbus_write_13, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_13, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_13, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_13, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_13, + + output logic calbus_read_14, + output logic calbus_write_14, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_14, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_14, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_14, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_14, + + output logic calbus_read_15, + output logic calbus_write_15, + output logic [PORT_CALBUS_ADDRESS_WIDTH-1:0] calbus_address_15, + input logic [PORT_CALBUS_RDATA_WIDTH-1:0] calbus_rdata_15, + output logic [PORT_CALBUS_WDATA_WIDTH-1:0] calbus_wdata_15, + input logic [PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_15, + + // Input clock/reset intended for core logic connected to the Avalon slave port of the sequencer CPU. + // The "out" clock/reset is intended for daisy-chaining logic from multiple interfaces. + // Ports for "cal_debug" interface + input logic cal_debug_clk, + input logic cal_debug_reset_n, + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + // Hard-Nios debug port + input logic [1:0] vji_ir_in, + output logic [1:0] vji_ir_out, + input logic vji_jtag_state_rti, + input logic vji_tck, + input logic vji_tdi, + output logic vji_tdo, + input logic vji_virtual_state_cdr, + input logic vji_virtual_state_sdr, + input logic vji_virtual_state_udr, + input logic vji_virtual_state_uir +); + timeunit 1ns; + timeprecision 1ps; + + // Derive localparam values + + // Typically we synthesize full-calibration behavior for hardware, + // except when USE_SYNTH_FOR_SIM is set, which allows flows such + // as post-fit simulation to adopt RTL simulation behavior. + localparam REMAP_IOSSM_GPT_HEX_FILENAME = (SEQ_USE_SIM_PARAMS == "on") ? IOSSM_SIM_GPT_HEX_FILENAME : ( + (USE_SYNTH_FOR_SIM) ? IOSSM_SIM_GPT_HEX_FILENAME : IOSSM_SYNTH_GPT_HEX_FILENAME ); + localparam REMAP_SEQ_GPT_NIOS_CLK_FREQ_KHZ = (SEQ_USE_SIM_PARAMS == "on") ? SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ : ( + (USE_SYNTH_FOR_SIM) ? SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ : SEQ_GPT_NIOS_CLK_FREQ_KHZ ); + localparam REMAP_SEQ_GPT_GLOBAL_SKIP_STEPS = (SEQ_USE_SIM_PARAMS == "on") ? SIM_SEQ_GPT_GLOBAL_SKIP_STEPS : ( + (USE_SYNTH_FOR_SIM) ? SIM_SEQ_GPT_GLOBAL_SKIP_STEPS : SEQ_GPT_GLOBAL_SKIP_STEPS ); + + wire w_vji_cdr_to_the_hard_nios; + wire [ 1: 0] w_vji_ir_in_to_the_hard_nios; + wire w_vji_rti_to_the_hard_nios; + wire w_vji_sdr_to_the_hard_nios; + wire w_vji_tck_to_the_hard_nios; + wire w_vji_tdi_to_the_hard_nios; + wire w_vji_udr_to_the_hard_nios; + wire w_vji_uir_to_the_hard_nios; + + wire [ 1: 0] w_sld_vji_ir_out_from_the_hard_nios; + wire w_sld_vji_tdo_from_the_hard_nios; + wire [ 1: 0] w_vji_ir_out_from_the_hard_nios; + wire w_vji_tdo_from_the_hard_nios; + + wire [15:0][PORT_CALBUS_WDATA_WIDTH-1:0] calbus_rdata_i; + wire [15:0][PORT_CALBUS_SEQ_PARAM_TBL_WIDTH-1:0] calbus_seq_param_tbl_i; + + logic [7:0] soft_nios_read_data; + logic soft_nios_rdata_valid_n; + logic soft_nios_waitrequest_n; + + logic soft_nios_read; + logic soft_nios_write; + logic soft_nios_byteenable; + logic [7:0] soft_nios_write_data; + logic [6:0] soft_nios_address; + + + generate if (USE_SOFT_NIOS != 0) begin + altera_emif_f2c_gearbox #( + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH) + ) f2c_gearbox_inst ( + .clk (cal_debug_clk), + .reset_n (cal_debug_reset_n), + + .cal_debug_addr (cal_debug_addr), + .cal_debug_byteenable (cal_debug_byteenable), + .cal_debug_read (cal_debug_read), + .cal_debug_write (cal_debug_write), + .cal_debug_write_data (cal_debug_write_data), + + .cal_debug_read_data (cal_debug_read_data), + .cal_debug_read_data_valid(cal_debug_read_data_valid), + .cal_debug_waitrequest (cal_debug_waitrequest), + + .soft_nios_read_data (soft_nios_read_data), + .soft_nios_rdata_valid_n (soft_nios_rdata_valid_n), + .soft_nios_waitrequest_n (soft_nios_waitrequest_n), + + .soft_nios_read (soft_nios_read), + .soft_nios_write (soft_nios_write), + .soft_nios_byteenable (soft_nios_byteenable), + .soft_nios_write_data (soft_nios_write_data), + .soft_nios_address (soft_nios_address) + ); + end else begin + assign soft_nios_address = 7'd0; + assign soft_nios_byteenable = 1'b0; + assign soft_nios_write_data = 8'd0; + assign soft_nios_read = 1'b0; + assign soft_nios_write = 1'b0; + assign cal_debug_read_data = '0; + assign cal_debug_read_data_valid = '0; + assign cal_debug_waitrequest = '0; + end + endgenerate + + assign calbus_rdata_i[0] = (NUM_CALBUS_USED > 0) ? calbus_rdata_0 : 'd0; + assign calbus_seq_param_tbl_i[0] = (NUM_CALBUS_USED > 0) ? calbus_seq_param_tbl_0 : 'd0; + assign calbus_rdata_i[1] = (NUM_CALBUS_USED > 1) ? calbus_rdata_1 : 'd0; + assign calbus_seq_param_tbl_i[1] = (NUM_CALBUS_USED > 1) ? calbus_seq_param_tbl_1 : 'd0; + assign calbus_rdata_i[2] = (NUM_CALBUS_USED > 2) ? calbus_rdata_2 : 'd0; + assign calbus_seq_param_tbl_i[2] = (NUM_CALBUS_USED > 2) ? calbus_seq_param_tbl_2 : 'd0; + assign calbus_rdata_i[3] = (NUM_CALBUS_USED > 3) ? calbus_rdata_3 : 'd0; + assign calbus_seq_param_tbl_i[3] = (NUM_CALBUS_USED > 3) ? calbus_seq_param_tbl_3 : 'd0; + assign calbus_rdata_i[4] = (NUM_CALBUS_USED > 4) ? calbus_rdata_4 : 'd0; + assign calbus_seq_param_tbl_i[4] = (NUM_CALBUS_USED > 4) ? calbus_seq_param_tbl_4 : 'd0; + assign calbus_rdata_i[5] = (NUM_CALBUS_USED > 5) ? calbus_rdata_5 : 'd0; + assign calbus_seq_param_tbl_i[5] = (NUM_CALBUS_USED > 5) ? calbus_seq_param_tbl_5 : 'd0; + assign calbus_rdata_i[6] = (NUM_CALBUS_USED > 6) ? calbus_rdata_6 : 'd0; + assign calbus_seq_param_tbl_i[6] = (NUM_CALBUS_USED > 6) ? calbus_seq_param_tbl_6 : 'd0; + assign calbus_rdata_i[7] = (NUM_CALBUS_USED > 7) ? calbus_rdata_7 : 'd0; + assign calbus_seq_param_tbl_i[7] = (NUM_CALBUS_USED > 7) ? calbus_seq_param_tbl_7 : 'd0; + assign calbus_rdata_i[8] = (NUM_CALBUS_USED > 8) ? calbus_rdata_8 : 'd0; + assign calbus_seq_param_tbl_i[8] = (NUM_CALBUS_USED > 8) ? calbus_seq_param_tbl_8 : 'd0; + assign calbus_rdata_i[9] = (NUM_CALBUS_USED > 9) ? calbus_rdata_9 : 'd0; + assign calbus_seq_param_tbl_i[9] = (NUM_CALBUS_USED > 9) ? calbus_seq_param_tbl_9 : 'd0; + assign calbus_rdata_i[10] = (NUM_CALBUS_USED > 10) ? calbus_rdata_10 : 'd0; + assign calbus_seq_param_tbl_i[10] = (NUM_CALBUS_USED > 10) ? calbus_seq_param_tbl_10 : 'd0; + assign calbus_rdata_i[11] = (NUM_CALBUS_USED > 11) ? calbus_rdata_11 : 'd0; + assign calbus_seq_param_tbl_i[11] = (NUM_CALBUS_USED > 11) ? calbus_seq_param_tbl_11 : 'd0; + assign calbus_rdata_i[12] = (NUM_CALBUS_USED > 12) ? calbus_rdata_12 : 'd0; + assign calbus_seq_param_tbl_i[12] = (NUM_CALBUS_USED > 12) ? calbus_seq_param_tbl_12 : 'd0; + assign calbus_rdata_i[13] = (NUM_CALBUS_USED > 13) ? calbus_rdata_13 : 'd0; + assign calbus_seq_param_tbl_i[13] = (NUM_CALBUS_USED > 13) ? calbus_seq_param_tbl_13 : 'd0; + assign calbus_rdata_i[14] = (NUM_CALBUS_USED > 14) ? calbus_rdata_14 : 'd0; + assign calbus_seq_param_tbl_i[14] = (NUM_CALBUS_USED > 14) ? calbus_seq_param_tbl_14 : 'd0; + assign calbus_rdata_i[15] = (NUM_CALBUS_USED > 15) ? calbus_rdata_15 : 'd0; + assign calbus_seq_param_tbl_i[15] = (NUM_CALBUS_USED > 15) ? calbus_seq_param_tbl_15 : 'd0; + + tennm_iossm # ( + .gpt_ver (SEQ_GPT_GLOBAL_PAR_VER), + .nios_ver (SEQ_GPT_NIOS_C_VER), + .col_id (SEQ_GPT_COLUMN_ID), + .num_iopacks (SEQ_GPT_NUM_IOPACKS), + .pt_size (SEQ_GPT_PARAM_TABLE_SIZE), + .cal_config (SEQ_GPT_GLOBAL_CAL_CONFIG), + .slave_clk_divider (SEQ_GPT_SLAVE_CLK_DIVIDER), + .nios_clk_freq (REMAP_SEQ_GPT_NIOS_CLK_FREQ_KHZ), + .skip_steps (REMAP_SEQ_GPT_GLOBAL_SKIP_STEPS), + .parameter_table_hex_file (REMAP_IOSSM_GPT_HEX_FILENAME), + + .abstract_phy ("false"), + .iossm_sim_clk_period_ps (IOSSM_SIM_NIOS_PERIOD_PS), + .nios_calibration_code_hex_file(IOSSM_CODE_HEX_FILENAME), + .iossm_use_model (IOSSM_USE_MODEL) + ) io_ssm ( + .soft_nios_irq (4'b0), + .soft_nios_address (soft_nios_address), + .soft_nios_byteenable (soft_nios_byteenable), + .soft_nios_clk (cal_debug_clk), + .soft_nios_read (soft_nios_read), + .soft_nios_write (soft_nios_write), + .soft_nios_write_data (soft_nios_write_data), + .soft_nios_read_data (soft_nios_read_data), + .soft_nios_rdata_valid (soft_nios_rdata_valid_n), + .soft_nios_waitrequest (soft_nios_waitrequest_n), + + // IO Subsystem Calibration Bus + .calbus_clock (calbus_clk), + + .calbus_read_0 (calbus_read_0), + .calbus_write_0 (calbus_write_0), + .calbus_address_0 (calbus_address_0), + .calbus_wdata_0 (calbus_wdata_0), + .calbus_rdata_0 (calbus_rdata_i[0]), + .calbus_param_tbl_0 (calbus_seq_param_tbl_i[0]), + + .calbus_read_1 (calbus_read_1), + .calbus_write_1 (calbus_write_1), + .calbus_address_1 (calbus_address_1), + .calbus_wdata_1 (calbus_wdata_1), + .calbus_rdata_1 (calbus_rdata_i[1]), + .calbus_param_tbl_1 (calbus_seq_param_tbl_i[1]), + + .calbus_read_2 (calbus_read_2), + .calbus_write_2 (calbus_write_2), + .calbus_address_2 (calbus_address_2), + .calbus_wdata_2 (calbus_wdata_2), + .calbus_rdata_2 (calbus_rdata_i[2]), + .calbus_param_tbl_2 (calbus_seq_param_tbl_i[2]), + + .calbus_read_3 (calbus_read_3), + .calbus_write_3 (calbus_write_3), + .calbus_address_3 (calbus_address_3), + .calbus_wdata_3 (calbus_wdata_3), + .calbus_rdata_3 (calbus_rdata_i[3]), + .calbus_param_tbl_3 (calbus_seq_param_tbl_i[3]), + + .calbus_read_4 (calbus_read_4), + .calbus_write_4 (calbus_write_4), + .calbus_address_4 (calbus_address_4), + .calbus_wdata_4 (calbus_wdata_4), + .calbus_rdata_4 (calbus_rdata_i[4]), + .calbus_param_tbl_4 (calbus_seq_param_tbl_i[4]), + + .calbus_read_5 (calbus_read_5), + .calbus_write_5 (calbus_write_5), + .calbus_address_5 (calbus_address_5), + .calbus_wdata_5 (calbus_wdata_5), + .calbus_rdata_5 (calbus_rdata_i[5]), + .calbus_param_tbl_5 (calbus_seq_param_tbl_i[5]), + + .calbus_read_6 (calbus_read_6), + .calbus_write_6 (calbus_write_6), + .calbus_address_6 (calbus_address_6), + .calbus_wdata_6 (calbus_wdata_6), + .calbus_rdata_6 (calbus_rdata_i[6]), + .calbus_param_tbl_6 (calbus_seq_param_tbl_i[6]), + + .calbus_read_7 (calbus_read_7), + .calbus_write_7 (calbus_write_7), + .calbus_address_7 (calbus_address_7), + .calbus_wdata_7 (calbus_wdata_7), + .calbus_rdata_7 (calbus_rdata_i[7]), + .calbus_param_tbl_7 (calbus_seq_param_tbl_i[7]), + + .calbus_read_8 (calbus_read_8), + .calbus_write_8 (calbus_write_8), + .calbus_address_8 (calbus_address_8), + .calbus_wdata_8 (calbus_wdata_8), + .calbus_rdata_8 (calbus_rdata_i[8]), + .calbus_param_tbl_8 (calbus_seq_param_tbl_i[8]), + + .calbus_read_9 (calbus_read_9), + .calbus_write_9 (calbus_write_9), + .calbus_address_9 (calbus_address_9), + .calbus_wdata_9 (calbus_wdata_9), + .calbus_rdata_9 (calbus_rdata_i[9]), + .calbus_param_tbl_9 (calbus_seq_param_tbl_i[9]), + + .calbus_read_10 (calbus_read_10), + .calbus_write_10 (calbus_write_10), + .calbus_address_10 (calbus_address_10), + .calbus_wdata_10 (calbus_wdata_10), + .calbus_rdata_10 (calbus_rdata_i[10]), + .calbus_param_tbl_10 (calbus_seq_param_tbl_i[10]), + + .calbus_read_11 (calbus_read_11), + .calbus_write_11 (calbus_write_11), + .calbus_address_11 (calbus_address_11), + .calbus_wdata_11 (calbus_wdata_11), + .calbus_rdata_11 (calbus_rdata_i[11]), + .calbus_param_tbl_11 (calbus_seq_param_tbl_i[11]), + + .calbus_read_12 (calbus_read_12), + .calbus_write_12 (calbus_write_12), + .calbus_address_12 (calbus_address_12), + .calbus_wdata_12 (calbus_wdata_12), + .calbus_rdata_12 (calbus_rdata_i[12]), + .calbus_param_tbl_12 (calbus_seq_param_tbl_i[12]), + + .calbus_read_13 (calbus_read_13), + .calbus_write_13 (calbus_write_13), + .calbus_address_13 (calbus_address_13), + .calbus_wdata_13 (calbus_wdata_13), + .calbus_rdata_13 (calbus_rdata_i[13]), + .calbus_param_tbl_13 (calbus_seq_param_tbl_i[13]), + + .calbus_read_14 (calbus_read_14), + .calbus_write_14 (calbus_write_14), + .calbus_address_14 (calbus_address_14), + .calbus_wdata_14 (calbus_wdata_14), + .calbus_rdata_14 (calbus_rdata_i[14]), + .calbus_param_tbl_14 (calbus_seq_param_tbl_i[14]), + + .calbus_read_15 (calbus_read_15), + .calbus_write_15 (calbus_write_15), + .calbus_address_15 (calbus_address_15), + .calbus_wdata_15 (calbus_wdata_15), + .calbus_rdata_15 (calbus_rdata_i[15]), + .calbus_param_tbl_15 (calbus_seq_param_tbl_i[15]), + + // IO Subsystem Calibration Bus + .vji_cdr_to_the_hard_nios (w_vji_cdr_to_the_hard_nios), + .vji_ir_in_to_the_hard_nios (w_vji_ir_in_to_the_hard_nios), + .vji_rti_to_the_hard_nios (w_vji_rti_to_the_hard_nios), + .vji_sdr_to_the_hard_nios (w_vji_sdr_to_the_hard_nios), + .vji_tck_to_the_hard_nios (w_vji_tck_to_the_hard_nios), + .vji_tdi_to_the_hard_nios (w_vji_tdi_to_the_hard_nios), + .vji_udr_to_the_hard_nios (w_vji_udr_to_the_hard_nios), + .vji_uir_to_the_hard_nios (w_vji_uir_to_the_hard_nios), + .vji_ir_out_from_the_hard_nios (w_vji_ir_out_from_the_hard_nios), + .vji_tdo_from_the_hard_nios (w_vji_tdo_from_the_hard_nios) + ); + + assign w_vji_cdr_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_cdr : 1'b0; + assign w_vji_ir_in_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_ir_in : 2'b00; + assign w_vji_rti_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_jtag_state_rti : 1'b0; + assign w_vji_sdr_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_sdr : 1'b0; + assign w_vji_tck_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_tck : 1'b0; + assign w_vji_tdi_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_tdi : 1'b0; + assign w_vji_udr_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_udr : 1'b0; + assign w_vji_uir_to_the_hard_nios = DIAG_EXPORT_VJI ? vji_virtual_state_uir : 1'b0; + assign vji_ir_out = DIAG_EXPORT_VJI ? w_vji_ir_out_from_the_hard_nios : 2'b0; + assign vji_tdo = DIAG_EXPORT_VJI ? w_vji_tdo_from_the_hard_nios : 1'b0; + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "sfv4CgBD2gRw66FfSic/D/DxyUF4ju6abSGjNZTz+XJ5wNcp1RmzgamT61rscvjMkkNKCYCGE4Hkry++3eL2fSJkmOtrYLQextJ2AFr2kX/6sa63SwNG1Dg8CndZgqHpcPsbI8J/52/6EA/5eQJiUNmwpEDzzugi2WpUBRBy4gGrSJ7A8zUzUrkHlWNSHE1mVOTkuXrL/BUqA6hBwwkS7qZD/J3TRyAu6L9p+9tB0ECj3HSUaZMQdsHOEoejOcwJ2RhJ9P4QDVEXGenDAmBQiJAPz6SAV4DqS0an68FB0ZOw3u6Fz9ZnsNCxHESqqKIhmHXeOOJqT0TMS7OxARNfiGSYsGZkXP2aOsQbPMyMl9Na0FpG3tX2nCq+YzVLsQyswtPgjPY/GO4ZMgPdYdp5JKSfreaxYuiLxTeDp4puFh9fP23Bzc62FleY5N14rrOPKFwR+NKcP0ZnDKesfQUGVQgHNDWd+yn8MPE4yKAFnC5UhP6/1eV6IVnPI3KCE7+1uvsrcyVo72I9ZjECteGSwb7zUBuIknMGGJLamSDccEEzp3d9zoNmEWwYEsAQ6sfJVbzrvs9dqrDzmsgVd7rsFQsAaIXZPlOjRlQJBcoDI69G4leYK9upuWONmbxZPwESZDMmSech7WRSR+Pfg8IhH2pcuaqwx+Flyt8/fEZd1nHHn/r7IbrV7vPwpWv6bwfQE4+LOlUxGkicqW/zIbwPWua1Y1pF8kRl1B24DA9A2PuASSdsPDi8qf8524t2r4XrzPEfPSuA4z8fLDKNUZ6WPPatW6xFtOpQrgjniprbGZ5Cdzlihkh1KGZUQFWqGWG9vSMwb1XceNsZWsR1lhRieIwEpGXGARM7U6MnIf+7MlzH137TXgbWLPIOwNuFNQ1W5TQen1Ntb084V6b8dzDtE07gYYf8X3PH/73It0UuW5x0UXD6aSiIv+qp+H4rdL0sTo4SHIb8muoxzrwI7lCZtReafd6NvK5+I9wtZd+IdKqB6WabzhHQoHFJnu4BF4Z7" +`endif diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_code.hex b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_code.hex new file mode 100644 index 0000000000..ea4df0b630 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_code.hex @@ -0,0 +1,30722 @@ +:020000020000FC +:0400000000000834C0 +:04000100002008547F +:040002003400006066 +:0400030000000000F9 +:0400040000000000F8 +:0400050000000000F7 +:0400060000000000F6 +:0400070000000000F5 +:04000800980200203A +:04000900FC00108C5B +:04000A00001000AA38 +:04000B000000F014ED +:04000C000000E834D4 +:04000D00003CEF5470 +:04000E000400F76093 +:04000F000001D834E0 +:04001000D000DED46A +:040011000002D034E5 +:0400120000B8D694C8 +:0400130000001014C5 +:0400140000011814BB +:040015000001203492 +:04001600C40220A060 +:04001700B80000A08D +:040018005000002074 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+:0477FC000000000089 +:0477FD000000000088 +:0477FE000000000087 +:0477FF000000000086 +:00000001FF diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.hex b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.hex new file mode 100644 index 0000000000..b789cb0aef --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.hex @@ -0,0 +1,26 @@ +:047400000000000286 +:047401000000000186 +:047402000000000185 +:047403000000001075 +:04740400001312D08F +:04740500000002641D +:047406000000041F5F +:047407000000000081 +:047408000000001C64 +:04740900000000641B +:04740A00000000007E +:04740B00000000007D +:04740C00000000007C +:04740D00000000007B +:04740E00000000007A +:04740F000000000079 +:047410000000000078 +:047411000000000077 +:047412000000000076 +:047413000000000075 +:047414000000000074 +:047415000000000073 +:047416000000000072 +:047417000000000071 +:047418000000000070 +:00000001FF diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.txt b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.txt new file mode 100644 index 0000000000..f46e9ba0b2 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.txt @@ -0,0 +1,30 @@ +// This file is dynamically generated and is for information purposes only. +// It is not used during compilation or simulation. + +SEQ_GPT + 0x7400 SEQ_GPT_GLOBAL_PAR_VER : 2 0x00000002 + 0x7404 SEQ_GPT_NIOS_C_VER : 1 0x00000001 + 0x7408 SEQ_GPT_COLUMN_ID : 1 0x00000001 + 0x740C SEQ_GPT_NUM_IOPACKS : 16 0x00000010 + 0x7410 SEQ_GPT_NIOS_CLK_FREQ_KHZ : 1250000 0x001312D0 + 0x7414 SEQ_GPT_PARAM_TABLE_SIZE : 612 0x00000264 + 0x7418 SEQ_GPT_GLOBAL_SKIP_STEPS : 1055 0x0000041F + 0x741C SEQ_GPT_GLOBAL_CAL_CONFIG : 0 0x00000000 + 0x7420 SEQ_GPT_SLAVE_CLK_DIVIDER : 28 0x0000001C + 0x7424 SEQ_GPT_INTERFACE_PAR_PTRS + 0x7424 static_array_elem [0] : 100 0x00000064 + 0x7428 static_array_elem [1] : 0 0x00000000 + 0x742C static_array_elem [2] : 0 0x00000000 + 0x7430 static_array_elem [3] : 0 0x00000000 + 0x7434 static_array_elem [4] : 0 0x00000000 + 0x7438 static_array_elem [5] : 0 0x00000000 + 0x743C static_array_elem [6] : 0 0x00000000 + 0x7440 static_array_elem [7] : 0 0x00000000 + 0x7444 static_array_elem [8] : 0 0x00000000 + 0x7448 static_array_elem [9] : 0 0x00000000 + 0x744C static_array_elem [10] : 0 0x00000000 + 0x7450 static_array_elem [11] : 0 0x00000000 + 0x7454 static_array_elem [12] : 0 0x00000000 + 0x7458 static_array_elem [13] : 0 0x00000000 + 0x745C static_array_elem [14] : 0 0x00000000 + 0x7460 static_array_elem [15] : 0 0x00000000 diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.hex b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.hex new file mode 100644 index 0000000000..4a1e8c9ace --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.hex @@ -0,0 +1,26 @@ +:047400000000000286 +:047401000000000186 +:047402000000000185 +:047403000000001075 +:047404000003D09021 +:04740500000002641D +:04740600000000087A +:047407000000000081 +:047408000000001C64 +:04740900000000641B +:04740A00000000007E +:04740B00000000007D +:04740C00000000007C +:04740D00000000007B +:04740E00000000007A +:04740F000000000079 +:047410000000000078 +:047411000000000077 +:047412000000000076 +:047413000000000075 +:047414000000000074 +:047415000000000073 +:047416000000000072 +:047417000000000071 +:047418000000000070 +:00000001FF diff --git a/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.txt b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.txt new file mode 100644 index 0000000000..17d360f826 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.txt @@ -0,0 +1,30 @@ +// This file is dynamically generated and is for information purposes only. +// It is not used during compilation or simulation. + +SEQ_GPT + 0x7400 SEQ_GPT_GLOBAL_PAR_VER : 2 0x00000002 + 0x7404 SEQ_GPT_NIOS_C_VER : 1 0x00000001 + 0x7408 SEQ_GPT_COLUMN_ID : 1 0x00000001 + 0x740C SEQ_GPT_NUM_IOPACKS : 16 0x00000010 + 0x7410 SEQ_GPT_NIOS_CLK_FREQ_KHZ : 250000 0x0003D090 + 0x7414 SEQ_GPT_PARAM_TABLE_SIZE : 612 0x00000264 + 0x7418 SEQ_GPT_GLOBAL_SKIP_STEPS : 8 0x00000008 + 0x741C SEQ_GPT_GLOBAL_CAL_CONFIG : 0 0x00000000 + 0x7420 SEQ_GPT_SLAVE_CLK_DIVIDER : 28 0x0000001C + 0x7424 SEQ_GPT_INTERFACE_PAR_PTRS + 0x7424 static_array_elem [0] : 100 0x00000064 + 0x7428 static_array_elem [1] : 0 0x00000000 + 0x742C static_array_elem [2] : 0 0x00000000 + 0x7430 static_array_elem [3] : 0 0x00000000 + 0x7434 static_array_elem [4] : 0 0x00000000 + 0x7438 static_array_elem [5] : 0 0x00000000 + 0x743C static_array_elem [6] : 0 0x00000000 + 0x7440 static_array_elem [7] : 0 0x00000000 + 0x7444 static_array_elem [8] : 0 0x00000000 + 0x7448 static_array_elem [9] : 0 0x00000000 + 0x744C static_array_elem [10] : 0 0x00000000 + 0x7450 static_array_elem [11] : 0 0x00000000 + 0x7454 static_array_elem [12] : 0 0x00000000 + 0x7458 static_array_elem [13] : 0 0x00000000 + 0x745C static_array_elem [14] : 0 0x00000000 + 0x7460 static_array_elem [15] : 0 0x00000000 diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.bsf b/corev_apu/altera/ip/emif_cal/emif_cal.bsf new file mode 100644 index 0000000000..16d3a79b1f --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.bsf @@ -0,0 +1,100 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the Intel FPGA Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 504 240) + (text "emif_cal" (rect 227 0 261 12)(font "SansSerif" (font_size 11))) + (text "inst" (rect 8 224 20 236)(font "Arial" )) + (port + (pt 0 176) + (input) + (text "calbus_rdata_0[31..0]" (rect 0 0 84 12)(font "SansSerif" (font_size 8))) + (text "calbus_rdata_0[31..0]" (rect 4 165 130 176)(font "SansSerif" (font_size 8))) + (line (pt 0 176)(pt 187 176)(line_width 3)) + ) + (port + (pt 0 201) + (input) + (text "calbus_seq_param_tbl_0[4095..0]" (rect 0 0 136 12)(font "SansSerif" (font_size 8))) + (text "calbus_seq_param_tbl_0[4095..0]" (rect 4 190 190 201)(font "SansSerif" (font_size 8))) + (line (pt 0 201)(pt 187 201)(line_width 3)) + ) + (port + (pt 0 76) + (output) + (text "calbus_read_0" (rect 0 0 59 12)(font "SansSerif" (font_size 8))) + (text "calbus_read_0" (rect 4 65 82 76)(font "SansSerif" (font_size 8))) + ) + (port + (pt 0 101) + (output) + (text "calbus_write_0" (rect 0 0 59 12)(font "SansSerif" (font_size 8))) + (text "calbus_write_0" (rect 4 90 88 101)(font "SansSerif" (font_size 8))) + ) + (port + (pt 0 126) + (output) + (text "calbus_address_0[19..0]" (rect 0 0 96 12)(font "SansSerif" (font_size 8))) + (text "calbus_address_0[19..0]" (rect 4 115 142 126)(font "SansSerif" (font_size 8))) + ) + (port + (pt 0 151) + (output) + (text "calbus_wdata_0[31..0]" (rect 0 0 87 12)(font "SansSerif" (font_size 8))) + (text "calbus_wdata_0[31..0]" (rect 4 140 130 151)(font "SansSerif" (font_size 8))) + ) + (port + (pt 504 76) + (output) + (text "calbus_clk" (rect 0 0 41 12)(font "SansSerif" (font_size 8))) + (text "calbus_clk" (rect 456 65 516 76)(font "SansSerif" (font_size 8))) + (line (pt 504 76)(pt 187 76)(line_width 1)) + ) + (drawing + (text "emif_calbus_0" (rect 102 46 282 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "calbus_read" (rect 192 71 450 152)(font "SansSerif" (color 0 0 0))) + (text "calbus_write" (rect 192 96 456 202)(font "SansSerif" (color 0 0 0))) + (text "calbus_address" (rect 192 121 468 252)(font "SansSerif" (color 0 0 0))) + (text "calbus_wdata" (rect 192 146 456 302)(font "SansSerif" (color 0 0 0))) + (text "calbus_rdata" (rect 192 171 456 352)(font "SansSerif" (color 0 0 0))) + (text "calbus_seq_param_tbl" (rect 192 196 504 402)(font "SansSerif" (color 0 0 0))) + (text "emif_calbus_clk" (rect 324 46 738 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 308 71 634 152)(font "SansSerif" (color 0 0 0))) + (text " emif_cal " (rect 470 226 1000 462)(font "SansSerif" )) + (line (pt 187 34)(pt 323 34)(line_width 1)) + (line (pt 323 34)(pt 323 226)(line_width 1)) + (line (pt 187 226)(pt 323 226)(line_width 1)) + (line (pt 187 34)(pt 187 226)(line_width 1)) + (line (pt 504 101)(pt 187 101)(line_width 1)) + (line (pt 504 126)(pt 187 126)(line_width 3)) + (line (pt 504 151)(pt 187 151)(line_width 3)) + (line (pt 188 55)(pt 188 205)(line_width 1)) + (line (pt 189 55)(pt 189 205)(line_width 1)) + (line (pt 504 76)(pt 323 76)(line_width 1)) + (line (pt 322 55)(pt 322 80)(line_width 1)) + (line (pt 321 55)(pt 321 80)(line_width 1)) + (line (pt 0 0)(pt 504 0)(line_width 1)) + (line (pt 504 0)(pt 504 243)(line_width 1)) + (line (pt 0 243)(pt 504 243)(line_width 1)) + (line (pt 0 0)(pt 0 243)(line_width 1)) + ) +) diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.cmp b/corev_apu/altera/ip/emif_cal/emif_cal.cmp new file mode 100644 index 0000000000..2c8a59c08d --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.cmp @@ -0,0 +1,12 @@ + component emif_cal is + port ( + calbus_read_0 : out std_logic; -- calbus_read + calbus_write_0 : out std_logic; -- calbus_write + calbus_address_0 : out std_logic_vector(19 downto 0); -- calbus_address + calbus_wdata_0 : out std_logic_vector(31 downto 0); -- calbus_wdata + calbus_rdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_rdata + calbus_seq_param_tbl_0 : in std_logic_vector(4095 downto 0) := (others => 'X'); -- calbus_seq_param_tbl + calbus_clk : out std_logic -- clk + ); + end component emif_cal; + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.html b/corev_apu/altera/ip/emif_cal/emif_cal.html new file mode 100644 index 0000000000..2cee8b6f8b --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.html @@ -0,0 +1,208 @@ + + + + + datasheet for emif_cal + + + + + + + + +
emif_cal +
+
+
+ + + + + +
2024.07.03.12:58:24Datasheet
+
+
Overview
+
+
+ + + + +
+
+
+
+
+
+
+
Memory Map
+ + + + +
+ +
+
+

emif_cal_0

altera_emif_cal v2.7.4 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NUM_CALBUS_INTERFACE1
DIAG_SIM_CAL_MODE_ENUMSIM_CAL_MODE_SKIP
DIAG_EXPORT_SEQ_AVALON_SLAVECAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_SIM_VERBOSEfalse
DIAG_EXTRA_CONFIGS
DIAG_ENABLE_JTAG_UARTfalse
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

emif_cal_0_emif_cal

altera_emif_cal_iossm v2.7.4 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NUM_CALBUS_INTERFACE1
DIAG_SIM_CAL_MODE_ENUMSIM_CAL_MODE_SKIP
DIAG_EXPORT_SEQ_AVALON_SLAVECAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_SIM_VERBOSEfalse
DIAG_EXTRA_CONFIGS
DIAG_ENABLE_JTAG_UARTfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.01 seconds
+ + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.qgsynthc b/corev_apu/altera/ip/emif_cal/emif_cal.qgsynthc new file mode 100644 index 0000000000..310c87ce9e --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.qgsynthc @@ -0,0 +1,241 @@ + + + emif_cal + + + + emif_cal + 1.0 + emif_cal + emif_cal + 0 + + + + + emif_cal_0 + + + + AXM_ID_NUM + 0 + + + DIAG_ENABLE_JTAG_UART + false + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_EXPORT_VJI + false + + + DIAG_EXTRA_CONFIGS + + + + DIAG_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_SIM_VERBOSE + false + + + DIAG_SYNTH_FOR_SIM + false + + + ENABLE_DDRT + false + + + NUM_CALBUS_INTERFACE + 1 + + + PHY_DDRT_EXPORT_CLK_STP_IF + false + + + SHORT_QSYS_INTERFACE_NAMES + true + + + + altera_emif_cal + 2.7.4 + emif_cal_0 + emif_cal_altera_emif_cal_274_kaypsya + 0 + + emif_cal.emif_cal_0 + + + + emif_cal + + + + DIAG_ENABLE_JTAG_UART + false + + + DIAG_EXPORT_SEQ_AVALON_SLAVE + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_EXPORT_VJI + false + + + DIAG_EXTRA_CONFIGS + + + + DIAG_SIM_CAL_MODE_ENUM + SIM_CAL_MODE_SKIP + + + DIAG_SIM_VERBOSE + false + + + DIAG_SYNTH_FOR_SIM + false + + + ENABLE_DDRT + false + + + IOSSM_SIM_NIOS_PERIOD_PS + 800 + + + IOSSM_USE_MODEL + 1 + + + NUM_CALBUS_INTERFACE + 1 + + + NUM_CALBUS_USED + 1 + + + PORT_CALBUS_ADDRESS_WIDTH + 20 + + + PORT_CALBUS_RDATA_WIDTH + 32 + + + PORT_CALBUS_SEQ_PARAM_TBL_WIDTH + 4096 + + + PORT_CALBUS_WDATA_WIDTH + 32 + + + PORT_CAL_DEBUG_ADDRESS_WIDTH + 27 + + + PORT_CAL_DEBUG_BYTEEN_WIDTH + 4 + + + PORT_CAL_DEBUG_RDATA_WIDTH + 32 + + + PORT_CAL_DEBUG_WDATA_WIDTH + 32 + + + PORT_VJI_IR_IN_WIDTH + 2 + + + PORT_VJI_IR_OUT_WIDTH + 2 + + + SEQ_GPT_COLUMN_ID + 1 + + + SEQ_GPT_GLOBAL_CAL_CONFIG + 0 + + + SEQ_GPT_GLOBAL_PAR_VER + 2 + + + SEQ_GPT_GLOBAL_SKIP_STEPS + 8 + + + SEQ_GPT_NIOS_CLK_FREQ_KHZ + 250000 + + + SEQ_GPT_NIOS_C_VER + 1 + + + SEQ_GPT_NUM_IOPACKS + 16 + + + SEQ_GPT_PARAM_TABLE_SIZE + 612 + + + SEQ_GPT_SLAVE_CLK_DIVIDER + 28 + + + SHORT_QSYS_INTERFACE_NAMES + true + + + SIM_SEQ_GPT_GLOBAL_SKIP_STEPS + 1631 + + + SIM_SEQ_GPT_NIOS_CLK_FREQ_KHZ + 1250000 + + + USE_SOFT_NIOS + 0 + + + USE_SYNTH_FOR_SIM + 0 + + + + altera_emif_cal_iossm + 2.7.4 + emif_cal + emif_cal_altera_emif_cal_iossm_274_yagv7fq + 0 + + emif_cal.emif_cal_0.emif_cal + + + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.qip b/corev_apu/altera/ip/emif_cal/emif_cal.qip new file mode 100644 index 0000000000..85eda7fe45 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.qip @@ -0,0 +1,65 @@ +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_TOOL_VERSION "24.1" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_emif_cal" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name PRE_COMPILED_MODULE "ON" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name OCS_IP_FILE "/home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal.ip" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name OCS_IP_TYPE "altera_emif_cal" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name OCS_IP_VERSION "2.7.4" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name OCS_IP_HASH "yagv7fq" +set_global_assignment -library "emif_cal" -name SOPCINFO_FILE [file join $::quartus(qip_path) "emif_cal.sopcinfo"] +set_global_assignment -entity "emif_cal" -library "emif_cal" -name SLD_INFO "QSYS_NAME emif_cal HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "emif_cal" -name MISC_FILE [file join $::quartus(qip_path) "emif_cal.cmp"] +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_TARGETED_DEVICE_FAMILY "Agilex 7" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 7}" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "emif_cal" -name MISC_FILE [file join $::quartus(qip_path) "../emif_cal.ip"] + +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_NAME "ZW1pZl9jYWxfYWx0ZXJhX2VtaWZfY2FsX2lvc3NtXzI3NF95YWd2N2Zx" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_DISPLAY_NAME "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgSW50ZWwgQ2FsaWJyYXRpb24gSVA=" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_VERSION "Mi43LjQ=" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_DESCRIPTION "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgSW50ZWwgQ2FsaWJyYXRpb24gSVA=" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJz" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9zdXBwb3J0L2xpdGVyYXR1cmUvbGl0LWV4dGVybmFsLW1lbW9yeS1pbnRlcmZhY2UuaHRtbA==" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_NAME "ZW1pZl9jYWxfYWx0ZXJhX2VtaWZfY2FsXzI3NF9rYXlwc3lh" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_DISPLAY_NAME "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgSW50ZWwgQ2FsaWJyYXRpb24gSVA=" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_VERSION "Mi43LjQ=" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_DESCRIPTION "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgSW50ZWwgQ2FsaWJyYXRpb24gSVA=" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_GROUP "TWVtb3J5IEludGVyZmFjZXMgYW5kIENvbnRyb2xsZXJz" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9zdXBwb3J0L2xpdGVyYXR1cmUvbGl0LWV4dGVybmFsLW1lbW9yeS1pbnRlcmZhY2UuaHRtbA==" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_COMPONENT_NAME "ZW1pZl9jYWw=" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "emif_cal" -library "emif_cal" -name IP_COMPONENT_VERSION "MS4w" + + +set_global_assignment -library "altera_emif_cal_iossm_274" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/altera_emif_cal_iossm.sv"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/altera_emif_f2c_gearbox.sv"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_code.hex"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.hex"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_sim_global_param_tbl.txt"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.hex"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_synth_global_param_tbl.txt"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq_arch.sv"] +set_global_assignment -library "altera_emif_cal_iossm_274" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_emif_cal_iossm_274/synth/emif_cal_altera_emif_cal_iossm_274_yagv7fq.sv"] +set_global_assignment -library "altera_emif_cal_274" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_emif_cal_274/synth/emif_cal_altera_emif_cal_274_kaypsya.v"] +set_global_assignment -library "emif_cal" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/emif_cal.v"] + + +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_TOOL_NAME "altera_emif_cal" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_TOOL_VERSION "2.7.4" +set_global_assignment -entity "emif_cal_altera_emif_cal_274_kaypsya" -library "altera_emif_cal_274" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_TOOL_NAME "altera_emif_cal_iossm" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_TOOL_VERSION "2.7.4" +set_global_assignment -entity "emif_cal_altera_emif_cal_iossm_274_yagv7fq" -library "altera_emif_cal_iossm_274" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.sopcinfo b/corev_apu/altera/ip/emif_cal/emif_cal.sopcinfo new file mode 100644 index 0000000000..57e85f3fac --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.sopcinfo @@ -0,0 +1,896 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + int + 0 + false + true + false + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + true + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + java.lang.String + emif_calbus_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + calbus_read_0 + Output + 1 + calbus_read + + + calbus_write_0 + Output + 1 + calbus_write + + + calbus_address_0 + Output + 20 + calbus_address + + + calbus_wdata_0 + Output + 32 + calbus_wdata + + + calbus_rdata_0 + Input + 32 + calbus_rdata + + + calbus_seq_param_tbl_0 + Input + 4096 + calbus_seq_param_tbl + + + + + + java.lang.String + + false + true + true + true + + + long + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + calbus_clk + Output + 1 + clk + + + + + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + SIM_CAL_MODE_SKIP + false + true + true + true + + + java.lang.String + CAL_DEBUG_EXPORT_MODE_DISABLED + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 800 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 16 + true + true + false + true + + + int + 250000 + true + true + false + true + + + int + 1250000 + true + true + false + true + + + int + 612 + true + true + false + true + + + int + 8 + true + true + false + true + + + int + 1631 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 28 + true + true + false + true + + + int + 27 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 20 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 32 + true + true + false + true + + + int + 4096 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + emif_calbus_clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + calbus_read_0 + Output + 1 + calbus_read + + + calbus_write_0 + Output + 1 + calbus_write + + + calbus_address_0 + Output + 20 + calbus_address + + + calbus_wdata_0 + Output + 32 + calbus_wdata + + + calbus_rdata_0 + Input + 32 + calbus_rdata + + + calbus_seq_param_tbl_0 + Input + 4096 + calbus_seq_param_tbl + + + + + + java.lang.String + + false + true + true + true + + + long + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + calbus_clk + Output + 1 + clk + + + + + 1 + altera_emif_cal + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Memory Interfaces Intel Calibration IP + 2.7.4 + + + 2 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 24.1 + + + 2 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 24.1 + + + 1 + altera_emif_cal_iossm + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Memory Interfaces Intel Calibration IP + 2.7.4 + + 24.1 115 + + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal.xml b/corev_apu/altera/ip/emif_cal/emif_cal.xml new file mode 100644 index 0000000000..5c8c3732c5 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal.xml @@ -0,0 +1,273 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: emif_cal" + "Generating: emif_cal_altera_emif_cal_274_kaypsya" + "Generating: emif_cal_altera_emif_cal_iossm_274_yagv7fq" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: emif_cal_altera_emif_cal_274_kaypsya" + "Generating: emif_cal_altera_emif_cal_iossm_274_yagv7fq" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: emif_cal_altera_emif_cal_iossm_274_yagv7fq" + + + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal_bb.v b/corev_apu/altera/ip/emif_cal/emif_cal_bb.v new file mode 100644 index 0000000000..cbed7f8c9f --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal_bb.v @@ -0,0 +1,11 @@ +module emif_cal ( + output wire calbus_read_0, // emif_calbus_0.calbus_read, EMIF Calibration component bus for read + output wire calbus_write_0, // .calbus_write, EMIF Calibration component bus for write + output wire [19:0] calbus_address_0, // .calbus_address, EMIF Calibration component bus for address + output wire [31:0] calbus_wdata_0, // .calbus_wdata, EMIF Calibration component bus for write data + input wire [31:0] calbus_rdata_0, // .calbus_rdata, EMIF Calibration component bus for read data + input wire [4095:0] calbus_seq_param_tbl_0, // .calbus_seq_param_tbl, EMIF Calibration component bus for parameter table data + output wire calbus_clk // emif_calbus_clk.clk, EMIF Calibration component bus for the clock + ); +endmodule + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal_generation.rpt b/corev_apu/altera/ip/emif_cal/emif_cal_generation.rpt new file mode 100644 index 0000000000..aafa62bbf0 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal_generation.rpt @@ -0,0 +1,15 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal --family="Agilex 7" --part=AGFB014R24B2E2V +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal --family="Agilex 7" --part=AGFB014R24B2E2V +Info: emif_cal: "Transforming system: emif_cal" +Info: emif_cal: "Naming system components in system: emif_cal" +Info: emif_cal: "Processing generation queue" +Info: emif_cal: "Generating: emif_cal" +Info: emif_cal: "Generating: emif_cal_altera_emif_cal_274_kaypsya" +Info: emif_cal: "Generating: emif_cal_altera_emif_cal_iossm_274_yagv7fq" +Info: emif_cal: Done "emif_cal" with 3 modules, 11 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/emif_cal/emif_cal_generation_previous.rpt b/corev_apu/altera/ip/emif_cal/emif_cal_generation_previous.rpt new file mode 100644 index 0000000000..aafa62bbf0 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal_generation_previous.rpt @@ -0,0 +1,15 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal --family="Agilex 7" --part=AGFB014R24B2E2V +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/intel/emif_cal --family="Agilex 7" --part=AGFB014R24B2E2V +Info: emif_cal: "Transforming system: emif_cal" +Info: emif_cal: "Naming system components in system: emif_cal" +Info: emif_cal: "Processing generation queue" +Info: emif_cal: "Generating: emif_cal" +Info: emif_cal: "Generating: emif_cal_altera_emif_cal_274_kaypsya" +Info: emif_cal: "Generating: emif_cal_altera_emif_cal_iossm_274_yagv7fq" +Info: emif_cal: Done "emif_cal" with 3 modules, 11 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/emif_cal/emif_cal_inst.v b/corev_apu/altera/ip/emif_cal/emif_cal_inst.v new file mode 100644 index 0000000000..61cc976f06 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal_inst.v @@ -0,0 +1,10 @@ + emif_cal u0 ( + .calbus_read_0 (_connected_to_calbus_read_0_), // output, width = 1, emif_calbus_0.calbus_read + .calbus_write_0 (_connected_to_calbus_write_0_), // output, width = 1, .calbus_write + .calbus_address_0 (_connected_to_calbus_address_0_), // output, width = 20, .calbus_address + .calbus_wdata_0 (_connected_to_calbus_wdata_0_), // output, width = 32, .calbus_wdata + .calbus_rdata_0 (_connected_to_calbus_rdata_0_), // input, width = 32, .calbus_rdata + .calbus_seq_param_tbl_0 (_connected_to_calbus_seq_param_tbl_0_), // input, width = 4096, .calbus_seq_param_tbl + .calbus_clk (_connected_to_calbus_clk_) // output, width = 1, emif_calbus_clk.clk + ); + diff --git a/corev_apu/altera/ip/emif_cal/emif_cal_inst.vhd b/corev_apu/altera/ip/emif_cal/emif_cal_inst.vhd new file mode 100644 index 0000000000..12cdf23c33 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/emif_cal_inst.vhd @@ -0,0 +1,23 @@ + component emif_cal is + port ( + calbus_read_0 : out std_logic; -- calbus_read + calbus_write_0 : out std_logic; -- calbus_write + calbus_address_0 : out std_logic_vector(19 downto 0); -- calbus_address + calbus_wdata_0 : out std_logic_vector(31 downto 0); -- calbus_wdata + calbus_rdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_rdata + calbus_seq_param_tbl_0 : in std_logic_vector(4095 downto 0) := (others => 'X'); -- calbus_seq_param_tbl + calbus_clk : out std_logic -- clk + ); + end component emif_cal; + + u0 : component emif_cal + port map ( + calbus_read_0 => CONNECTED_TO_calbus_read_0, -- emif_calbus_0.calbus_read + calbus_write_0 => CONNECTED_TO_calbus_write_0, -- .calbus_write + calbus_address_0 => CONNECTED_TO_calbus_address_0, -- .calbus_address + calbus_wdata_0 => CONNECTED_TO_calbus_wdata_0, -- .calbus_wdata + calbus_rdata_0 => CONNECTED_TO_calbus_rdata_0, -- .calbus_rdata + calbus_seq_param_tbl_0 => CONNECTED_TO_calbus_seq_param_tbl_0, -- .calbus_seq_param_tbl + calbus_clk => CONNECTED_TO_calbus_clk -- emif_calbus_clk.clk + ); + diff --git a/corev_apu/altera/ip/emif_cal/synth/emif_cal.v b/corev_apu/altera/ip/emif_cal/synth/emif_cal.v new file mode 100644 index 0000000000..a3ff61f0fe --- /dev/null +++ b/corev_apu/altera/ip/emif_cal/synth/emif_cal.v @@ -0,0 +1,26 @@ +// emif_cal.v + +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module emif_cal ( + output wire calbus_read_0, // emif_calbus_0.calbus_read, EMIF Calibration component bus for read + output wire calbus_write_0, // .calbus_write, EMIF Calibration component bus for write + output wire [19:0] calbus_address_0, // .calbus_address, EMIF Calibration component bus for address + output wire [31:0] calbus_wdata_0, // .calbus_wdata, EMIF Calibration component bus for write data + input wire [31:0] calbus_rdata_0, // .calbus_rdata, EMIF Calibration component bus for read data + input wire [4095:0] calbus_seq_param_tbl_0, // .calbus_seq_param_tbl, EMIF Calibration component bus for parameter table data + output wire calbus_clk // emif_calbus_clk.clk, EMIF Calibration component bus for the clock + ); + + emif_cal_altera_emif_cal_274_kaypsya emif_cal_0 ( + .calbus_read_0 (calbus_read_0), // output, width = 1, emif_calbus_0.calbus_read + .calbus_write_0 (calbus_write_0), // output, width = 1, .calbus_write + .calbus_address_0 (calbus_address_0), // output, width = 20, .calbus_address + .calbus_wdata_0 (calbus_wdata_0), // output, width = 32, .calbus_wdata + .calbus_rdata_0 (calbus_rdata_0), // input, width = 32, .calbus_rdata + .calbus_seq_param_tbl_0 (calbus_seq_param_tbl_0), // input, width = 4096, .calbus_seq_param_tbl + .calbus_clk (calbus_clk) // output, width = 1, emif_calbus_clk.clk + ); + +endmodule diff --git a/corev_apu/altera/ip/iddr_intel.ip b/corev_apu/altera/ip/iddr_intel.ip new file mode 100644 index 0000000000..d136afa04d --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel.ip @@ -0,0 +1,439 @@ + + + + Intel Corporation + iddr_intel + gpio_0 + 22.1.0 + + + ck + + + + + + + + export + + + ck + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + dout + + + + + + + + export + + + dout + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + pad_in + + + + + + + + export + + + pad_in + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_gpio + + QUARTUS_SYNTH + + + + + + ck + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + dout + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + pad_in + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + iddr_intel + altera_gpio + 22.1.0 + + + + + device_family + device_family + Agilex 7 + + + PIN_TYPE_GUI + Data Direction + Input + + + SIZE + Data width + 1 + + + gui_enable_migratable_port_names + Use legacy top-level port names + false + + + gui_diff_buff + Use differential buffer + false + + + gui_pseudo_diff + Use pseudo-differential buffer + false + + + gui_bus_hold + Use bus-hold circuitry + false + + + gui_open_drain + Use open-drain output + false + + + gui_use_oe + Enable output enable port + false + + + gui_enable_termination_ports + Enable seriestermination/paralleltermination ports + false + + + gui_io_reg_mode + Register mode + DDIO + + + gui_sreset_mode + Enable synchronous clear / preset port + None + + + gui_areset_mode + Enable asynchronous clear / preset port + None + + + gui_enable_cke + Enable clock enable port + false + + + gui_hr_logic + Half Rate Logic + false + + + gui_ddio_with_delay + Input DDIO With Delay + false + + + gui_separate_io_clks + Separate input/output Clocks + false + + + SYS_INFO_DEVICE + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_FAMILY + SYS_INFO_FAMILY + Agilex 7 + + + SYS_INFO_TRAIT_IOBANK_REVISION + SYS_INFO_TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + EXT_DRIVER_PARAM + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + GENERATE_SDC_FILE + false + + + IP_MIGRATE_PORT_MAP_FILE + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 2 + + + AUTO_BOARD + Auto BOARD + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + + + + + + + board + Board + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + + + device + Device + AGFB014R24B2E2V + + + deviceFamily + Device family + Agilex 7 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element gpio_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/corev_apu/altera/ip/iddr_intel/altera_gpio_2210/synth/iddr_intel_altera_gpio_2210_id4velq.v b/corev_apu/altera/ip/iddr_intel/altera_gpio_2210/synth/iddr_intel_altera_gpio_2210_id4velq.v new file mode 100644 index 0000000000..4f155eb422 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/altera_gpio_2210/synth/iddr_intel_altera_gpio_2210_id4velq.v @@ -0,0 +1,58 @@ +// iddr_intel_altera_gpio_2210_id4velq.v + +// This file was auto-generated from altera_gpio_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module iddr_intel_altera_gpio_2210_id4velq ( + input wire ck, // ck.export, In input and output paths, this clock feeds a packed register or DDIO. In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter. + output wire [1:0] dout, // dout.export, Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode: Bypass or simple register - DATA_SIZE = SIZE DDIO - DATA_SIZE = 2 x SIZE + input wire [0:0] pad_in // pad_in.export, Input signal from the pad. + ); + + altera_gpio #( + .SIZE (1), + .PIN_TYPE ("input"), + .REGISTER_MODE ("ddr"), + .HALF_RATE ("false"), + .DDIO_WITH_DELAY ("false"), + .SEPARATE_I_O_CLOCKS ("false"), + .BUFFER_TYPE ("single-ended"), + .PSEUDO_DIFF ("false"), + .ARESET_MODE ("none"), + .SRESET_MODE ("none"), + .OPEN_DRAIN ("false"), + .BUS_HOLD ("false"), + .ENABLE_OE ("false"), + .ENABLE_CKE ("false"), + .ENABLE_TERM ("false") + ) core ( + .ck (ck), // input, width = 1, ck.export + .dout (dout), // output, width = 2, dout.export + .pad_in (pad_in), // input, width = 1, pad_in.export + .cke (1'b1), // (terminated), + .ck_fr_in (1'b0), // (terminated), + .ck_fr_out (1'b0), // (terminated), + .ck_in (1'b0), // (terminated), + .ck_out (1'b0), // (terminated), + .ck_fr (1'b0), // (terminated), + .ck_hr_in (1'b0), // (terminated), + .ck_hr_out (1'b0), // (terminated), + .ck_hr (1'b0), // (terminated), + .din (2'b00), // (terminated), + .oe (1'b0), // (terminated), + .pad_io (), // (terminated), + .pad_io_b (), // (terminated), + .pad_in_b (1'b0), // (terminated), + .pad_out (), // (terminated), + .pad_out_b (), // (terminated), + .terminationcontrol (1'b0), // (terminated), + .aclr (1'b0), // (terminated), + .aset (1'b0), // (terminated), + .sclr (1'b0), // (terminated), + .sset (1'b0) // (terminated), + ); + +endmodule diff --git a/corev_apu/altera/ip/iddr_intel/altera_gpio_core10_2210/synth/altera_gpio.sv b/corev_apu/altera/ip/iddr_intel/altera_gpio_core10_2210/synth/altera_gpio.sv new file mode 100644 index 0000000000..b3417ee0d5 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/altera_gpio_core10_2210/synth/altera_gpio.sv @@ -0,0 +1,705 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +(* altera_attribute = "-name UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL OFF" *) +module altera_gpio_one_bit( + ck, + ck_in, + ck_out, + ck_fr, + ck_fr_in, + ck_fr_out, + ck_hr, + ck_hr_in, + ck_hr_out, + oe, + din, + dout, + pad, + pad_b, + terminationcontrol, + aclr, + aset, + sclr, + sset, + cke +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter PSEUDO_DIFF = "false"; + parameter REGISTER_MODE = "none"; + parameter HALF_RATE = "false"; + parameter SEPARATE_I_O_CLOCKS = "false"; + parameter ARESET_MODE = "none"; + parameter SRESET_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter OPEN_DRAIN = "false"; + parameter ENABLE_CKE = "false"; + parameter ENABLE_OE = "false"; + parameter ENABLE_TERM = "false"; + + localparam OE_SIZE = (HALF_RATE == "true") ? 2 : 1; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? + (HALF_RATE == "true") ? + 4 : 2 + : 1; + + input ck; + input ck_in; + input ck_out; + input ck_fr; + input ck_fr_in; + input ck_fr_out; + input ck_hr; + input ck_hr_in; + input ck_hr_out; + input [OE_SIZE - 1:0] oe; + input [DATA_SIZE - 1:0] din; + output [DATA_SIZE - 1:0] dout; + inout pad; + inout pad_b; + input terminationcontrol; + input aclr; + input aset; + input sclr; + input sset; + input cke; + + wire hr_out_clk; + wire fr_out_clk; + wire hr_in_clk; + wire fr_in_clk; + + wire din_ddr; + wire buf_in; + + wire areset; + wire sreset; + + generate + if(ARESET_MODE == "preset") begin + assign areset = ~aset; + end + else begin + assign areset = ~aclr; + end + endgenerate + + generate + if(SRESET_MODE == "preset") begin + assign sreset = sset; + end + else begin + assign sreset = sclr; + end + endgenerate + + generate + if(SEPARATE_I_O_CLOCKS == "true") + begin + if(HALF_RATE == "true") begin + assign hr_out_clk = ck_hr_out; + assign fr_out_clk = ck_fr_out; + assign hr_in_clk = ck_hr_in; + assign fr_in_clk = ck_fr_in; + end + else begin + assign fr_out_clk = ck_out; + assign fr_in_clk = ck_in; + end + end + else begin + if(HALF_RATE == "true") begin + assign hr_out_clk = ck_hr; + assign fr_out_clk = ck_fr; + assign hr_in_clk = ck_hr; + assign fr_in_clk = ck_fr; + end + else begin + assign fr_out_clk = ck; + assign fr_in_clk = ck; + end + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin: out_path + wire [1:0] din_fr; + + if (HALF_RATE == "true") + begin: out_path_hr + tennm_ddio_out + #( + .half_rate_mode("true"), + .async_mode(ARESET_MODE) + ) iodout_hr_ddio_0 ( + .areset(areset), + .datainhi(din[2]), + .datainlo(din[0]), + .dataout(din_fr[0]), + .clk (hr_out_clk) + ); + + tennm_ddio_out + #( + .half_rate_mode("true"), + .async_mode(ARESET_MODE) + ) iodout_hr_ddio_1 ( + .areset(areset), + .datainhi(din[3]), + .datainlo(din[1]), + .dataout(din_fr[1]), + .clk (hr_out_clk) + ); + end + else + begin: out_path_hr_byp + assign din_fr[DATA_SIZE - 1:0] = din; + end + + if (REGISTER_MODE == "ddr") + begin: out_path_fr + tennm_ddio_out + #( + .half_rate_mode("false"), + .async_mode(ARESET_MODE), + .sync_mode(SRESET_MODE) + ) fr_out_data_ddio ( + .ena(cke), + .areset(areset), + .sreset(sreset), + .datainhi(din_fr[1]), + .datainlo(din_fr[0]), + .dataout(din_ddr), + .clk (fr_out_clk) + ); + end + else if (REGISTER_MODE == "sdr") + begin: out_path_reg + reg reg_data_out; + always @(posedge fr_out_clk) + reg_data_out <= din_fr[0]; + + assign din_ddr = reg_data_out; + end + else + begin: out_path_byp + assign din_ddr = din_fr[0]; + end + end + endgenerate + + generate + wire oe_fr; + wire oe_ddr; + + if (PIN_TYPE == "bidir" || ENABLE_OE == "true") + begin: oe_path + if (HALF_RATE == "true") + begin: oe_path_hr + tennm_ddio_out + #( + .half_rate_mode("true") + ) oe_in_hr_ddio ( + .datainhi(oe[1]), + .datainlo(oe[0]), + .dataout(oe_fr), + .clk (hr_out_clk) + ); + end + else + begin: oe_path_hr_byp + assign oe_fr = oe[0]; + end + + if (REGISTER_MODE == "sdr" || REGISTER_MODE == "ddr") + begin: oe_path_fr + reg oe_reg; + always @(posedge fr_out_clk) oe_reg <= oe_fr; + assign oe_ddr = oe_reg; + end + else + begin: oe_path_byp + assign oe_ddr = oe_fr; + end + end + else if (PIN_TYPE == "output") + begin + assign oe_ddr = 1'b1; + end + else + begin + assign oe_ddr = 1'b0; + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin : input_path + wire [1:0] buf_in_fr; + + if (REGISTER_MODE == "ddr") + begin: in_path_fr + tennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode(SRESET_MODE) + ) buffer_data_in_fr_ddio ( + .ena(cke), + .areset(areset), + .sreset(sreset), + .datain(buf_in), + .clk (fr_in_clk), + .regouthi(buf_in_fr[1]), + .regoutlo(buf_in_fr[0]) + ); + end + else if (REGISTER_MODE == "sdr") + begin: in_path_reg + reg ro; + always @(posedge fr_in_clk) begin + ro <= buf_in; + end + assign buf_in_fr[0] = ro; + end + else + begin: in_byp + assign buf_in_fr[0] = buf_in; + end + + if (HALF_RATE == "true") + begin: in_path_hr + tennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode("none") + ) buffer_data_in_hr_ddio_0 ( + .areset(areset), + .datain(buf_in_fr[0]), + .clk (hr_in_clk), + .regouthi(dout[2]), + .regoutlo(dout[0]) + ); + + tennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode("none") + ) buffer_data_in_hr_ddio_1 ( + .areset(areset), + .datain(buf_in_fr[1]), + .clk (hr_in_clk), + .regouthi(dout[3]), + .regoutlo(dout[1]) + ); + end + else + begin: in_path_hr_byp + assign dout[DATA_SIZE - 1:0] = buf_in_fr[DATA_SIZE - 1:0]; + end + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin : output_buffer + if(BUFFER_TYPE == "differential") begin + wire obuf_din; + wire obuf_din_b; + wire obuf_oe; + wire obuf_oe_b; + + if(PSEUDO_DIFF == "true") begin + if (PIN_TYPE == "output" && ENABLE_OE == "false") + begin : oe_path + tennm_pseudo_diff_out pseudo_diff_out( + .i(din_ddr), + .o(obuf_din), + .obar(obuf_din_b) + ); + + if (ENABLE_TERM == "true") begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .term_in(terminationcontrol), + .i(obuf_din), + .o(pad) + ); + + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .term_in(terminationcontrol), + .i(obuf_din_b), + .o(pad_b) + ); + end + else begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(obuf_din), + .o(pad) + ); + + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .i(obuf_din_b), + .o(pad_b) + ); + end + end + else begin + tennm_pseudo_diff_out pseudo_diff_out( + .i(din_ddr), + .o(obuf_din), + .obar(obuf_din_b), + .oein(oe_ddr), + .oeout(obuf_oe), + .oebout(obuf_oe_b) + ); + if (ENABLE_TERM == "true") begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .term_in(terminationcontrol), + .i(obuf_din), + .oe(obuf_oe), + .o(pad) + ); + + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .term_in(terminationcontrol), + .i(obuf_din_b), + .oe(obuf_oe_b), + .o(pad_b) + ); + end + else begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(obuf_din), + .oe(obuf_oe), + .o(pad) + ); + + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .i(obuf_din_b), + .oe(obuf_oe_b), + .o(pad_b) + ); + end + end + end + else begin + if (ENABLE_TERM == "true") begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .term_in(terminationcontrol), + .i(din_ddr), + .o(pad), + .obar(pad_b) + ); + end + else begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(din_ddr), + .o(pad), + .obar(pad_b) + ); + end + + end + end + else begin + if (PIN_TYPE == "bidir" || ENABLE_OE == "true") begin + if (ENABLE_TERM == "true") begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .term_in(terminationcontrol), + .i(din_ddr), + .oe(oe_ddr), + .o(pad) + ); + end + else begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .i(din_ddr), + .oe(oe_ddr), + .o(pad) + ); + end + end + else begin + if (ENABLE_TERM == "true") begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .term_in(terminationcontrol), + .i(din_ddr), + .o(pad) + ); + end + else begin + tennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .i(din_ddr), + .o(pad) + ); + end + end + end + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin : input_buffer + if(BUFFER_TYPE == "differential") begin + if (ENABLE_TERM == "true") begin + tennm_io_ibuf + #( + .differential_mode("true"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .term_in(terminationcontrol), + .o(buf_in) + ); + end + else begin + tennm_io_ibuf + #( + .differential_mode("true"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .o(buf_in) + ); + end + end + else begin + if (ENABLE_TERM == "true") begin + tennm_io_ibuf + #( + .differential_mode("false"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .term_in(terminationcontrol), + .o(buf_in) + ); + end + else begin + tennm_io_ibuf + #( + .differential_mode("false"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .o(buf_in) + ); + end + end + end + endgenerate + +endmodule + +(* altera_attribute = "-name UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL OFF" *) +module altera_gpio( + ck, + ck_in, + ck_out, + ck_fr, + ck_fr_in, + ck_fr_out, + ck_hr, + ck_hr_in, + ck_hr_out, + oe, + din, + dout, + pad_io, + pad_io_b, + pad_in, + pad_in_b, + pad_out, + pad_out_b, + terminationcontrol, + aclr, + aset, + sclr, + sset, + cke +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter PSEUDO_DIFF = "false"; + parameter REGISTER_MODE = "none"; + parameter HALF_RATE = "false"; + parameter SEPARATE_I_O_CLOCKS = "false"; + parameter SIZE = 4; + parameter ARESET_MODE = "none"; + parameter SRESET_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter OPEN_DRAIN = "false"; + parameter ENABLE_CKE = "false"; + parameter ENABLE_OE = "false"; + parameter ENABLE_TERM = "false"; + parameter DDIO_WITH_DELAY = "false"; + + localparam OE_SIZE = (HALF_RATE == "true") ? 2 : 1; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? + (HALF_RATE == "true") ? + 4 : 2 + : 1; + + input ck; + input ck_in; + input ck_out; + input ck_fr; + input ck_fr_in; + input ck_fr_out; + input ck_hr; + input ck_hr_in; + input ck_hr_out; + input [SIZE * OE_SIZE - 1:0] oe; + input [SIZE * DATA_SIZE - 1:0] din; + output [SIZE * DATA_SIZE - 1:0] dout; + input terminationcontrol; + inout [SIZE - 1:0] pad_io; + inout [SIZE - 1:0] pad_io_b; + input [SIZE - 1:0] pad_in; + input [SIZE - 1:0] pad_in_b; + output [SIZE - 1:0] pad_out; + output [SIZE - 1:0] pad_out_b; + input aclr; + input aset; + input sclr; + input sset; + input cke; + + wire [SIZE * OE_SIZE - 1:0] oe_reordered; + wire [SIZE * DATA_SIZE - 1:0] din_reordered; + wire [SIZE * DATA_SIZE - 1:0] dout_reordered; + wire [SIZE - 1:0] pad_io; + wire [SIZE - 1:0] pad_io_b; + + generate + if (PIN_TYPE == "input") + begin + assign pad_io = pad_in; + assign pad_io_b = pad_in_b; + end + else if (PIN_TYPE == "output") + begin + assign pad_out = pad_io; + assign pad_out_b = pad_io_b; + end + endgenerate + + genvar j, k; + generate + for(j = 0; j < SIZE ; j = j + 1) begin : j_loop + for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop + assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE]; + assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k]; + end + for(k = 0; k < OE_SIZE; k = k + 1) begin : k_oe_loop + assign oe_reordered[j * OE_SIZE + k] = oe[j + k * SIZE]; + end + end + endgenerate + + genvar i; + generate + for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop + altera_gpio_one_bit #( + .PIN_TYPE(PIN_TYPE), + .BUFFER_TYPE(BUFFER_TYPE), + .PSEUDO_DIFF(PSEUDO_DIFF), + .REGISTER_MODE(REGISTER_MODE), + .HALF_RATE(HALF_RATE), + .SEPARATE_I_O_CLOCKS(SEPARATE_I_O_CLOCKS), + .ARESET_MODE(ARESET_MODE), + .SRESET_MODE(SRESET_MODE), + .BUS_HOLD(BUS_HOLD), + .OPEN_DRAIN(OPEN_DRAIN), + .ENABLE_CKE(ENABLE_CKE), + .ENABLE_OE(ENABLE_OE), + .ENABLE_TERM(ENABLE_TERM) + ) altera_gpio_bit_i ( + .ck(ck), + .ck_in(ck_in), + .ck_out(ck_out), + .ck_fr(ck_fr), + .ck_fr_in(ck_fr_in), + .ck_fr_out(ck_fr_out), + .ck_hr(ck_hr), + .ck_hr_in(ck_hr_in), + .ck_hr_out(ck_hr_out), + .oe(oe_reordered[(i + 1) * OE_SIZE - 1 : i * OE_SIZE]), + .din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .pad(pad_io[i]), + .pad_b(pad_io_b[i]), + .terminationcontrol(terminationcontrol), + .aclr(aclr), + .aset(aset), + .sclr(sclr), + .sset(sset), + .cke(cke) + ); + end + endgenerate + +endmodule +`ifdef QUESTA_INTEL_OEM +`pragma questa_oem_00 "Xw7zHY4BqltP71AyShWqYISoLhZT3SxrpyEl7BQuEYmT9aXwFInZOB1+8NAM9Abxac/nqs+RlyE9whduUc9F1yz69gW4lO+wlI8NI9FlvhMmczOfpPoswd02wxY1mC0KUEBF6UVmqVmGgPRlVgar5aXf/783J2fwrQfqbxgQXykWiGLaQMHxcul/bgoN4hFEn1TMYUy/tTE8m8koc22984w19xYrqWuXU/0ySEZYOIJoZBnitKgbUBY3rDzQ99Qg6tQmDbxcCCc6z9INYtbZjIF888CRyYARe9DOQqPTCv6nAt5dj9MQAds4YCMxEsm/ilQC6lg9f2Hk9/Lnn4DeJsk/LyWFN4dH5y3vUGWAYvFdPxB3itFnRFHPeuSxjpmbRXFgSdt5Us1xo5IrPuTTs0p8YAvpbK7GNhnxmBBQ9XNe2afXMLKKrTIYBi7oQIyumhDsvAGNG15ikezHkiJxkQjs4gKtz8RaPx8/4Gg8kkzzKu0wvztFnLqWYq7A1HIP6SRHKHG/174lC6asBipM4vS/iIpoEVsMUoBakLAuhoYLGJdWzqqLyOFIIaiRYuRMgS8aNVlHPBLmKaw+2xiWb0T7NkSgk/c2m/pWV2IZxY9VZMOQM3mzJNtKEzfK+k++EYqyPByvqplT1MqLNRuUhN/vr2A1kGjk9O96NP9YMJROxPvNo+pyzL23l9MIAanx058zhdxd/405zzFUan7ijQ/E4D7UbPwP8kLAlnC0PiRsdyXNUR4nzDJ0iv6esmOYjFDnaplTxRHNkyHS1nAdPgGm7moCYQa50uWfqzpwq5dwC2OMZ6Oiuj/fSU5rQt87X5EyLOHBDPsqG35YFBjKIVoJQfiM9c61EQ2uSrjrBssFfB17FNs1EnHQmaDyJNrBDx8VioA83cj24TL+zDzdYdZEdmIvsNahsOSSrIZsdxqLKLgUPw4JzJ1Mb8i39r/a/0OfC5QryVXDrsbU1XROXFX9IQ7ugnw6fhgFFgvW3AZDOFa2GDcTvxHHE3rvj8wf" +`endif \ No newline at end of file diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.bsf b/corev_apu/altera/ip/iddr_intel/iddr_intel.bsf new file mode 100644 index 0000000000..3be587e261 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.bsf @@ -0,0 +1,71 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the Intel FPGA Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 184 168) + (text "iddr_intel" (rect 63 0 97 12)(font "SansSerif" (font_size 11))) + (text "inst" (rect 8 152 20 164)(font "Arial" )) + (port + (pt 0 76) + (input) + (text "ck" (rect 0 0 9 12)(font "SansSerif" (font_size 8))) + (text "ck" (rect 4 65 16 76)(font "SansSerif" (font_size 8))) + (line (pt 0 76)(pt 51 76)(line_width 1)) + ) + (port + (pt 0 126) + (input) + (text "pad_in" (rect 0 0 25 12)(font "SansSerif" (font_size 8))) + (text "pad_in" (rect 4 115 40 126)(font "SansSerif" (font_size 8))) + (line (pt 0 126)(pt 51 126)(line_width 1)) + ) + (port + (pt 184 76) + (output) + (text "dout[1..0]" (rect 0 0 35 12)(font "SansSerif" (font_size 8))) + (text "dout[1..0]" (rect 142 65 202 76)(font "SansSerif" (font_size 8))) + (line (pt 184 76)(pt 136 76)(line_width 3)) + ) + (drawing + (text "ck" (rect 39 46 90 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "export" (rect 56 71 148 152)(font "SansSerif" (color 0 0 0))) + (text "dout" (rect 137 46 298 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "export" (rect 106 71 248 152)(font "SansSerif" (color 0 0 0))) + (text "pad_in" (rect 13 96 62 205)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "export" (rect 56 121 148 252)(font "SansSerif" (color 0 0 0))) + (text " iddr_intel " (rect 145 151 362 312)(font "SansSerif" )) + (line (pt 51 34)(pt 136 34)(line_width 1)) + (line (pt 136 34)(pt 136 151)(line_width 1)) + (line (pt 51 151)(pt 136 151)(line_width 1)) + (line (pt 51 34)(pt 51 151)(line_width 1)) + (line (pt 52 55)(pt 52 80)(line_width 1)) + (line (pt 53 55)(pt 53 80)(line_width 1)) + (line (pt 135 55)(pt 135 80)(line_width 1)) + (line (pt 134 55)(pt 134 80)(line_width 1)) + (line (pt 52 105)(pt 52 130)(line_width 1)) + (line (pt 53 105)(pt 53 130)(line_width 1)) + (line (pt 0 0)(pt 184 0)(line_width 1)) + (line (pt 184 0)(pt 184 168)(line_width 1)) + (line (pt 0 168)(pt 184 168)(line_width 1)) + (line (pt 0 0)(pt 0 168)(line_width 1)) + ) +) diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.cmp b/corev_apu/altera/ip/iddr_intel/iddr_intel.cmp new file mode 100644 index 0000000000..f8e8685071 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.cmp @@ -0,0 +1,8 @@ + component iddr_intel is + port ( + ck : in std_logic := 'X'; -- export + dout : out std_logic_vector(1 downto 0); -- export + pad_in : in std_logic_vector(0 downto 0) := (others => 'X') -- export + ); + end component iddr_intel; + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.html b/corev_apu/altera/ip/iddr_intel/iddr_intel.html new file mode 100644 index 0000000000..919bdac627 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.html @@ -0,0 +1,193 @@ + + + + + datasheet for iddr_intel + + + + + + + + +
iddr_intel +
+
+
+ + + + + +
2024.06.20.13:40:16Datasheet
+
+
Overview
+
+
+ + + + +
+
+
+
+
+
+
+
Memory Map
+ + + + +
+ +
+
+

gpio_0

altera_gpio v22.1.0 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PIN_TYPE_GUIInput
SIZE1
gui_enable_migratable_port_namesfalse
gui_diff_bufffalse
gui_pseudo_diff_off_shadowfalse
gui_bus_holdfalse
gui_open_drain_shadowfalse
gui_use_oe_off_shadowfalse
gui_enable_termination_portsfalse
gui_io_reg_modeDDIO
gui_sreset_modeNone
gui_areset_modeNone
gui_enable_ckefalse
gui_hr_logicfalse
gui_separate_io_clks_off_shadowfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.01 seconds
+ + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.qgsynthc b/corev_apu/altera/ip/iddr_intel/iddr_intel.qgsynthc new file mode 100644 index 0000000000..d173a89901 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.qgsynthc @@ -0,0 +1,446 @@ + + + iddr_intel + + + + iddr_intel + 1.0 + iddr_intel + iddr_intel + 0 + + + + + gpio_0 + + + + ARESET_MODE + none + + + BUFFER_TYPE + single-ended + + + BUS_HOLD + false + + + DDIO_WITH_DELAY + false + + + ENABLE_CKE + false + + + ENABLE_OE + false + + + ENABLE_TERM + false + + + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + false + + + HALF_RATE + false + + + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + OPEN_DRAIN + false + + + PIN_TYPE + input + + + PIN_TYPE_GUI + Input + + + PSEUDO_DIFF + false + + + REGISTER_MODE + ddr + + + SEPARATE_I_O_CLOCKS + false + + + SIZE + 1 + + + SRESET_MODE + none + + + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_FAMILY + Agilex 7 + + + SYS_INFO_TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + device_family + Agilex 7 + + + gui_areset_mode + None + + + gui_areset_mode_off_shadow + None + + + gui_bus_hold + false + + + gui_bus_hold_shadow + false + + + gui_ddio_with_delay + false + + + gui_ddio_with_delay_off_shadow + false + + + gui_diff_buff + false + + + gui_enable_cke + false + + + gui_enable_cke_off_shadow + false + + + gui_enable_migratable_port_names + false + + + gui_enable_termination_ports + false + + + gui_enable_termination_ports_shadow + false + + + gui_hr_logic + false + + + gui_hr_logic_off_shadow + false + + + gui_io_reg_mode + DDIO + + + gui_open_drain + false + + + gui_open_drain_shadow + false + + + gui_pseudo_diff + false + + + gui_pseudo_diff_off_shadow + false + + + gui_pseudo_diff_on_shadow + true + + + gui_separate_io_clks + false + + + gui_separate_io_clks_off_shadow + false + + + gui_sreset_mode + None + + + gui_sreset_mode_off_shadow + None + + + gui_use_oe + false + + + gui_use_oe_off_shadow + false + + + gui_use_oe_on_shadow + true + + + + altera_gpio + 22.1.0 + gpio_0 + iddr_intel_altera_gpio_2210_id4velq + 0 + + iddr_intel.gpio_0 + + + + core + + + + ARESET_MODE + none + + + BUFFER_TYPE + single-ended + + + BUS_HOLD + false + + + DDIO_WITH_DELAY + false + + + ENABLE_CKE + false + + + ENABLE_OE + false + + + ENABLE_TERM + false + + + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + false + + + HALF_RATE + false + + + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + OPEN_DRAIN + false + + + PIN_TYPE + input + + + PIN_TYPE_GUI + Input + + + PSEUDO_DIFF + false + + + REGISTER_MODE + ddr + + + SEPARATE_I_O_CLOCKS + false + + + SIZE + 1 + + + SRESET_MODE + none + + + SYS_INFO_DEVICE + AGFB014R24B2E2V + + + SYS_INFO_FAMILY + Agilex 7 + + + SYS_INFO_TRAIT_IOBANK_REVISION + IO96A_REVB2 + + + gui_areset_mode + None + + + gui_areset_mode_off_shadow + None + + + gui_bus_hold + false + + + gui_bus_hold_shadow + false + + + gui_ddio_with_delay + false + + + gui_ddio_with_delay_off_shadow + false + + + gui_diff_buff + false + + + gui_enable_cke + false + + + gui_enable_cke_off_shadow + false + + + gui_enable_migratable_port_names + false + + + gui_enable_termination_ports + false + + + gui_enable_termination_ports_shadow + false + + + gui_hr_logic + false + + + gui_hr_logic_off_shadow + false + + + gui_io_reg_mode + DDIO + + + gui_open_drain + false + + + gui_open_drain_shadow + false + + + gui_pseudo_diff + false + + + gui_pseudo_diff_off_shadow + false + + + gui_pseudo_diff_on_shadow + true + + + gui_separate_io_clks + false + + + gui_separate_io_clks_off_shadow + false + + + gui_sreset_mode + None + + + gui_sreset_mode_off_shadow + None + + + gui_use_oe + false + + + gui_use_oe_off_shadow + false + + + gui_use_oe_on_shadow + true + + + + altera_gpio_core10 + 22.1.0 + core + altera_gpio + altera_gpio + 0 + + iddr_intel.gpio_0.core + + + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.qip b/corev_apu/altera/ip/iddr_intel/iddr_intel.qip new file mode 100644 index 0000000000..ec88912dec --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.qip @@ -0,0 +1,64 @@ +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TOOL_VERSION "24.1" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_gpio" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name PRE_COMPILED_MODULE "ON" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name OCS_IP_FILE "/home/angela/Documents/github/cva6/corev_apu/fpga/iddr_intel.ip" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name OCS_IP_TYPE "altera_gpio" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name OCS_IP_VERSION "22.1.0" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name OCS_IP_HASH "id4velq" +set_global_assignment -library "iddr_intel" -name SOPCINFO_FILE [file join $::quartus(qip_path) "iddr_intel.sopcinfo"] +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name SLD_INFO "QSYS_NAME iddr_intel HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "iddr_intel" -name MISC_FILE [file join $::quartus(qip_path) "iddr_intel.cmp"] +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TARGETED_DEVICE_FAMILY "Agilex 7" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96A_REVB2" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 7}" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "iddr_intel" -name MISC_FILE [file join $::quartus(qip_path) "../iddr_intel.ip"] + +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW8=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBDb3JlIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_VERSION "MjIuMS4w" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRlBHQSBHUElPIENvcmU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_COMPONENT_GROUP "SS9P" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_NAME "aWRkcl9pbnRlbF9hbHRlcmFfZ3Bpb18yMjEwX2lkNHZlbHE=" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBJbnRlbCBGUEdBIElQ" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_VERSION "MjIuMS4w" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DESCRIPTION "VGhlIEdQSU8gSW50ZWwgRlBHQSBJUCBwcm92aWRlcyBmZWF0dXJlcyB0byBzdXBwb3J0IHRoZSBkZXZpY2UgSS9PIGJsb2Nrcy4gWW91IGNhbiB1c2UgR1BJT3MgaW4gZ2VuZXJhbCBhcHBsaWNhdGlvbnMgdGhhdCBhcmUgbm90IHNwZWNpZmljIHRvIHRyYW5zY2VpdmVycywgbWVtb3J5IGludGVyZmFjZXMsIG9yIExWRFMuIFlvdSBjYW4gdXNlIHRoZSBJbnRlbCBRdWFydHVzIFByaW1lIHBhcmFtZXRlciBlZGl0b3IgdG8gY29uZmlndXJlIHRoZSBHUElPIEludGVsIEZQR0EgSVAu" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0kvTw==" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzNi8yMy0yLTIxLTAtMC91c2VyLWd1aWRlLWFuZC1kZXZpY2VzLmh0bWw=" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4Mzc4MC8yMy0zL2dlbmVyYWwtcHVycG9zZS1pLW8tb3ZlcnZpZXcuaHRtbA==" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzc3MjEzOC8yMy00L2dlbmVyYWwtcHVycG9zZS1pLW8tb3ZlcnZpZXcuaHRtbA==" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzUxOC8yMy0yL2ktby1vdmVydmlldy5odG1s" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzQ3OS8=" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_COMPONENT_NAME "aWRkcl9pbnRlbA==" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "iddr_intel" -library "iddr_intel" -name IP_COMPONENT_VERSION "MS4w" + +set_instance_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name MESSAGE_DISABLE 10034 +set_instance_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name MESSAGE_DISABLE 10230 +set_instance_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name MESSAGE_DISABLE 10036 + +set_global_assignment -library "altera_gpio_core10_2210" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_gpio_core10_2210/synth/altera_gpio.sv"] +set_global_assignment -library "altera_gpio_2210" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_gpio_2210/synth/iddr_intel_altera_gpio_2210_id4velq.v"] +set_global_assignment -library "iddr_intel" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/iddr_intel.v"] + + +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_TOOL_NAME "altera_gpio" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_TOOL_VERSION "22.1.0" +set_global_assignment -entity "iddr_intel_altera_gpio_2210_id4velq" -library "altera_gpio_2210" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_TOOL_NAME "altera_gpio_core10" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_TOOL_VERSION "22.1.0" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core10_2210" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.sopcinfo b/corev_apu/altera/ip/iddr_intel/iddr_intel.sopcinfo new file mode 100644 index 0000000000..e47da252b6 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.sopcinfo @@ -0,0 +1,716 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + Input + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + false + true + true + + + boolean + true + true + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + false + true + true + + + boolean + true + true + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + false + false + true + + + java.lang.String + DDIO + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + java.lang.String + None + true + false + false + true + + + java.lang.String + None + false + true + true + true + + + java.lang.String + None + true + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + false + false + true + + + boolean + false + false + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + false + false + false + true + + + boolean + false + true + false + true + true + + + java.lang.String + input + true + true + false + true + + + java.lang.String + ddr + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + single-ended + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + none + true + true + false + true + + + java.lang.String + none + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + IO96A_REVB2 + false + true + false + true + PART_TRAIT + DEVICE_IOBANK_REVISION + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + altddio_bidir_port_map.csv + false + true + false + true + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Intel Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA + false + true + false + true + BOARD + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + ck + Input + 1 + export + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + dout + Output + 2 + export + + + + + + ui.blockdiagram.direction + input + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + pad_in + Input + 1 + export + + + + + 1 + altera_gpio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + GPIO Intel FPGA IP + 22.1.0 + + + 3 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 24.1 + + 24.1 115 + + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel.xml b/corev_apu/altera/ip/iddr_intel/iddr_intel.xml new file mode 100644 index 0000000000..d2654080ff --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel.xml @@ -0,0 +1,248 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: iddr_intel" + "Generating: iddr_intel_altera_gpio_2210_id4velq" + "Generating: altera_gpio" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: iddr_intel_altera_gpio_2210_id4velq" + "Generating: altera_gpio" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: altera_gpio" + + + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel_bb.v b/corev_apu/altera/ip/iddr_intel/iddr_intel_bb.v new file mode 100644 index 0000000000..c34e40f115 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel_bb.v @@ -0,0 +1,7 @@ +module iddr_intel ( + input wire ck, // ck.export, In input and output paths, this clock feeds a packed register or DDIO. In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter. + output wire [1:0] dout, // dout.export, Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode: Bypass or simple register - DATA_SIZE = SIZE DDIO - DATA_SIZE = 2 x SIZE + input wire [0:0] pad_in // pad_in.export, Input signal from the pad. + ); +endmodule + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel_generation.rpt b/corev_apu/altera/ip/iddr_intel/iddr_intel_generation.rpt new file mode 100644 index 0000000000..aebc247393 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel_generation.rpt @@ -0,0 +1,17 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/iddr_intel.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/iddr_intel --family="Agilex 7" --part=AGFB014R24B2E2V +Info: iddr_intel.gpio_0: Intel GPIO supports a maximum interface frequency of 300 MHZ. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6/corev_apu/fpga/iddr_intel.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6/corev_apu/fpga/iddr_intel --family="Agilex 7" --part=AGFB014R24B2E2V +Info: iddr_intel.gpio_0: Intel GPIO supports a maximum interface frequency of 300 MHZ. +Info: iddr_intel: "Transforming system: iddr_intel" +Info: iddr_intel: "Naming system components in system: iddr_intel" +Info: iddr_intel: "Processing generation queue" +Info: iddr_intel: "Generating: iddr_intel" +Info: iddr_intel: "Generating: iddr_intel_altera_gpio_2210_id4velq" +Info: iddr_intel: "Generating: altera_gpio" +Info: iddr_intel: Done "iddr_intel" with 3 modules, 3 files +Info: Finished: Create HDL design files for synthesis diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel_inst.v b/corev_apu/altera/ip/iddr_intel/iddr_intel_inst.v new file mode 100644 index 0000000000..63f364d9d7 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel_inst.v @@ -0,0 +1,6 @@ + iddr_intel u0 ( + .ck (_connected_to_ck_), // input, width = 1, ck.export + .dout (_connected_to_dout_), // output, width = 2, dout.export + .pad_in (_connected_to_pad_in_) // input, width = 1, pad_in.export + ); + diff --git a/corev_apu/altera/ip/iddr_intel/iddr_intel_inst.vhd b/corev_apu/altera/ip/iddr_intel/iddr_intel_inst.vhd new file mode 100644 index 0000000000..d512f5a914 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/iddr_intel_inst.vhd @@ -0,0 +1,15 @@ + component iddr_intel is + port ( + ck : in std_logic := 'X'; -- export + dout : out std_logic_vector(1 downto 0); -- export + pad_in : in std_logic_vector(0 downto 0) := (others => 'X') -- export + ); + end component iddr_intel; + + u0 : component iddr_intel + port map ( + ck => CONNECTED_TO_ck, -- ck.export + dout => CONNECTED_TO_dout, -- dout.export + pad_in => CONNECTED_TO_pad_in -- pad_in.export + ); + diff --git a/corev_apu/altera/ip/iddr_intel/synth/iddr_intel.v b/corev_apu/altera/ip/iddr_intel/synth/iddr_intel.v new file mode 100644 index 0000000000..15d42d25bf --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel/synth/iddr_intel.v @@ -0,0 +1,18 @@ +// iddr_intel.v + +// Generated using ACDS version 24.1 115 + +`timescale 1 ps / 1 ps +module iddr_intel ( + input wire ck, // ck.export, In input and output paths, this clock feeds a packed register or DDIO. In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter. + output wire [1:0] dout, // dout.export, Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode: Bypass or simple register - DATA_SIZE = SIZE DDIO - DATA_SIZE = 2 x SIZE + input wire [0:0] pad_in // pad_in.export, Input signal from the pad. + ); + + iddr_intel_altera_gpio_2210_id4velq gpio_0 ( + .ck (ck), // input, width = 1, ck.export + .dout (dout), // output, width = 2, dout.export + .pad_in (pad_in) // input, width = 1, pad_in.export + ); + +endmodule diff --git a/corev_apu/altera/ip/io_pll.ip b/corev_apu/altera/ip/io_pll.ip new file mode 100644 index 0000000000..58d2c90ee7 --- /dev/null +++ b/corev_apu/altera/ip/io_pll.ip @@ -0,0 +1,2038 @@ + + + + Intel Corporation + io_pll + iopll_0 + 19.3.1 + + + refclk + + + + + + + + clk + + + refclk + + + + + + + + + clockRate + Clock rate + 100000000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + input + + + + + + + locked + + + + + + + + export + + + locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + reset + + + + + + + + reset + + + rst + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + ui.blockdiagram.direction + input + + + + + + + outclk0 + + + + + + + + clk + + + outclk_0 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 200000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk1 + + + + + + + + clk + + + outclk_1 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk2 + + + + + + + + clk + + + outclk_2 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 200000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk3 + + + + + + + + clk + + + outclk_3 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk4 + + + + + + + + clk + + + outclk_4 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 100000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_iopll + + QUARTUS_SYNTH + + + + + + refclk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_0 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_1 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_2 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_3 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_4 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + io_pll + altera_iopll + 19.3.1 + + + + + gui_debug_mode + + false + + + gui_skip_sdc_generation + + false + + + gui_include_iossm + + false + + + gui_cal_code_hex_file + + iossm.hex + + + gui_parameter_table_hex_file + + seq_params_sim.hex + + + gui_pll_tclk_mux_en + + false + + + gui_pll_tclk_sel + + pll_tclk_m_src + + + gui_pll_vco_freq_band_0 + + pll_freq_clk0_band18 + + + gui_pll_vco_freq_band_1 + + pll_freq_clk1_band18 + + + gui_pll_freqcal_en + + true + + + gui_pll_freqcal_req_flag + + true + + + gui_cal_converge + + false + + + gui_cal_error + + cal_clean + + + gui_pll_cal_done + + false + + + gui_pll_type + + S10_Simple + + + gui_pll_m_cnt_in_src + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src0 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src1 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src2 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src3 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src4 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src5 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src6 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src7 + + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src8 + + c_m_cnt_in_src_ph_mux_clk + + + system_info_device_family + Device Family + Agilex 7 + + + system_info_device_component + Component + AGFB014R24B2E2V + + + system_info_device_speed_grade + Speed Grade + 2 + + + system_info_device_iobank_rev + IO Bank Revision + + + + system_part_trait_speed_grade + Speed Grade Trait + 2 + + + system_part_trait_iobank_rev + IO Bank Revision Trait + IO96A_REVB2 + + + gui_usr_device_speed_grade + Speed Grade + 1 + + + gui_en_reconf + Enable dynamic reconfiguration of PLL + false + + + gui_en_iossm_reconf + Enable dynamic reconfiguration of PLL using Calibration IP + false + + + gui_user_base_address + User base address of PLL for dynamic reconfiguration (0..255) + 0 + + + gui_en_dps_ports + Enable access to dynamic phase shift ports + false + + + gui_pll_mode + PLL Mode + Integer-N PLL + + + gui_location_type + IOPLL Type + I/O Bank + + + gui_use_logical + Use logical PLL + false + + + gui_reference_clock_frequency + Reference Clock Frequency + 100.0 + + + gui_reference_clock_frequency_ps + Reference Clock Frequency + 10000.0 + + + gui_use_coreclk + Refclk source is global clock + true + + + gui_refclk_might_change + My reference clock frequency might change + false + + + gui_fractional_cout + Fractional carry out + 32 + + + gui_prot_mode + prot_mode + UNUSED + + + gui_dsm_out_sel + DSM Order + 1st_order + + + gui_use_locked + Enable locked output port + true + + + gui_en_adv_params + Enable physical output clock parameters + false + + + gui_pll_bandwidth_preset + PLL Bandwidth Preset + Medium + + + gui_lock_setting + Lock Threshold Setting + Low Lock Time + + + gui_pll_auto_reset + PLL Auto Reset + false + + + gui_en_lvds_ports + Access to PLL LVDS_CLK/LOADEN output port + Disabled + + + gui_en_periphery_ports + Enable access to I/O Bank clock ports + false + + + gui_operation_mode + Compensation Mode + direct + + + gui_feedback_clock + Feedback Clock + Global Clock + + + gui_clock_to_compensate + Compensated Outclk + 0 + + + gui_use_NDFB_modes + Use Nondedicated Feedback Path + false + + + gui_refclk_switch + Create a second input clock signal 'refclk1' + false + + + gui_refclk1_frequency + Second Reference Clock Frequency + 100.0 + + + gui_en_phout_ports + Enable access to PLL DPA output port + false + + + gui_phout_division + PLL DPA output division + 1 + + + gui_en_extclkout_ports + Enable access to PLL external clock output port + false + + + gui_number_of_clocks + Number Of Clocks + 5 + + + gui_multiply_factor + Multiply Factor (M-Counter) + 25 + + + gui_divide_factor_n + Divide Factor (N-Counter) + 6 + + + gui_frac_multiply_factor + Fractional Multiply Factor (K) + 1 + + + gui_fix_vco_frequency + Specify VCO frequency + false + + + gui_fixed_vco_frequency + Desired VCO Frequency + 600.0 + + + gui_fixed_vco_frequency_ps + Desired VCO Frequency + 1667.0 + + + gui_vco_frequency + Actual VCO Frequency + 1250.0 + + + gui_enable_output_counter_cascading + Enable output counter cascading + false + + + gui_mif_gen_options + MIF Generation Options + Generate New MIF File + + + gui_new_mif_file_path + Path to New MIF file + ~/pll.mif + + + gui_existing_mif_file_path + Path to Existing MIF file + ~/pll.mif + + + gui_mif_config_name + Name of Current Configuration + unnamed + + + gui_active_clk + Create an 'active_clk' signal to indicate the input clock in use + false + + + gui_clk_bad + Create a 'clkbad' signal for each of the input clocks + false + + + gui_switchover_mode + Switchover Mode + Automatic Switchover + + + gui_switchover_delay + Switchover Delay + 0 + + + gui_enable_cascade_out + Create a 'cascade_out' signal to connect to a downstream PLL + false + + + gui_cascade_outclk_index + cascade_out source + 0 + + + gui_enable_cascade_in + Create an 'adjpllin' (cascade in) signal to connect to an upstream PLL through IO Column Cascading + false + + + gui_enable_permit_cal + Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal input signal) + false + + + gui_enable_upstream_out_clk + Connect outclk to a downstream PLL through Core Clock Network Cascading + false + + + gui_pll_cascading_mode + Connection Signal Type to Upstream PLL + adjpllin + + + gui_enable_mif_dps + Enable Dynamic Phase Shift for MIF streaming + false + + + gui_dps_cntr + DPS Counter Selection + C0 + + + gui_dps_num + Number of Dynamic Phase Shifts + 1 + + + gui_dps_dir + Dynamic Phase Shift Direction + Positive + + + gui_extclkout_0_source + extclk_out[0] source + C0 + + + gui_extclkout_1_source + extclk_out[1] source + C0 + + + gui_extclkout_source + extclk_out source + C0 + + + gui_clock_name_global + Give clocks global names + false + + + gui_clock_name_string0 + Clock Name + outclk0 + + + gui_clock_name_string1 + Clock Name + outclk1 + + + gui_clock_name_string2 + Clock Name + outclk2 + + + gui_clock_name_string3 + Clock Name + outclk3 + + + gui_clock_name_string4 + Clock Name + outclk4 + + + gui_clock_name_string5 + Clock Name + outclk5 + + + gui_clock_name_string6 + Clock Name + outclk6 + + + gui_clock_name_string7 + Clock Name + outclk7 + + + gui_clock_name_string8 + Clock Name + outclk8 + + + gui_clock_name_string9 + Clock Name + outclk9 + + + gui_clock_name_string10 + Clock Name + outclk10 + + + gui_clock_name_string11 + Clock Name + outclk11 + + + gui_clock_name_string12 + Clock Name + outclk12 + + + gui_clock_name_string13 + Clock Name + outclk13 + + + gui_clock_name_string14 + Clock Name + outclk14 + + + gui_clock_name_string15 + Clock Name + outclk15 + + + gui_clock_name_string16 + Clock Name + outclk16 + + + gui_clock_name_string17 + Clock Name + outclk17 + + + gui_divide_factor_c0 + Divide Factor (C-Counter) + 1 + + + gui_divide_factor_c1 + Divide Factor (C-Counter) + 25 + + + gui_divide_factor_c2 + Divide Factor (C-Counter) + 25 + + + gui_divide_factor_c3 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c4 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c5 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c6 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c7 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c8 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c9 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c10 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c11 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c12 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c13 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c14 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c15 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c16 + Divide Factor (C-Counter) + 6 + + + gui_divide_factor_c17 + Divide Factor (C-Counter) + 6 + + + gui_cascade_counter0 + Make this a cascade counter + false + + + gui_cascade_counter1 + Make this a cascade counter + false + + + gui_cascade_counter2 + Make this a cascade counter + false + + + gui_cascade_counter3 + Make this a cascade counter + false + + + gui_cascade_counter4 + Make this a cascade counter + false + + + gui_cascade_counter5 + Make this a cascade counter + false + + + gui_cascade_counter6 + Make this a cascade counter + false + + + gui_cascade_counter7 + Make this a cascade counter + false + + + gui_cascade_counter8 + Make this a cascade counter + false + + + gui_cascade_counter9 + Make this a cascade counter + false + + + gui_cascade_counter10 + Make this a cascade counter + false + + + gui_cascade_counter11 + Make this a cascade counter + false + + + gui_cascade_counter12 + Make this a cascade counter + false + + + gui_cascade_counter13 + Make this a cascade counter + false + + + gui_cascade_counter14 + Make this a cascade counter + false + + + gui_cascade_counter15 + Make this a cascade counter + false + + + gui_cascade_counter16 + Make this a cascade counter + false + + + gui_cascade_counter17 + Make this a cascade counter + false + + + gui_output_clock_frequency0 + Desired Frequency + 200.0 + + + gui_output_clock_frequency1 + Desired Frequency + 125.0 + + + gui_output_clock_frequency2 + Desired Frequency + 200.0 + + + gui_output_clock_frequency3 + Desired Frequency + 125.0 + + + gui_output_clock_frequency4 + Desired Frequency + 100.0 + + + gui_output_clock_frequency5 + Desired Frequency + 100.0 + + + gui_output_clock_frequency6 + Desired Frequency + 100.0 + + + gui_output_clock_frequency7 + Desired Frequency + 100.0 + + + gui_output_clock_frequency8 + Desired Frequency + 100.0 + + + gui_output_clock_frequency9 + Desired Frequency + 100.0 + + + gui_output_clock_frequency10 + Desired Frequency + 100.0 + + + gui_output_clock_frequency11 + Desired Frequency + 100.0 + + + gui_output_clock_frequency12 + Desired Frequency + 100.0 + + + gui_output_clock_frequency13 + Desired Frequency + 100.0 + + + gui_output_clock_frequency14 + Desired Frequency + 100.0 + + + gui_output_clock_frequency15 + Desired Frequency + 100.0 + + + gui_output_clock_frequency16 + Desired Frequency + 100.0 + + + gui_output_clock_frequency17 + Desired Frequency + 100.0 + + + gui_output_clock_frequency_ps0 + Desired Frequency + 5000.0 + + + gui_output_clock_frequency_ps1 + Desired Frequency + 8000.0 + + + gui_output_clock_frequency_ps2 + Desired Frequency + 5000.0 + + + gui_output_clock_frequency_ps3 + Desired Frequency + 8000.0 + + + gui_output_clock_frequency_ps4 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps5 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps6 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps7 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps8 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps9 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps10 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps11 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps12 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps13 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps14 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps15 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps16 + Desired Frequency + 10000.0 + + + gui_output_clock_frequency_ps17 + Desired Frequency + 10000.0 + + + gui_ps_units0 + Phase Shift Units + ps + + + gui_ps_units1 + Phase Shift Units + ps + + + gui_ps_units2 + Phase Shift Units + ps + + + gui_ps_units3 + Phase Shift Units + degrees + + + gui_ps_units4 + Phase Shift Units + ps + + + gui_ps_units5 + Phase Shift Units + ps + + + gui_ps_units6 + Phase Shift Units + ps + + + gui_ps_units7 + Phase Shift Units + ps + + + gui_ps_units8 + Phase Shift Units + ps + + + gui_ps_units9 + Phase Shift Units + ps + + + gui_ps_units10 + Phase Shift Units + ps + + + gui_ps_units11 + Phase Shift Units + ps + + + gui_ps_units12 + Phase Shift Units + ps + + + gui_ps_units13 + Phase Shift Units + ps + + + gui_ps_units14 + Phase Shift Units + ps + + + gui_ps_units15 + Phase Shift Units + ps + + + gui_ps_units16 + Phase Shift Units + ps + + + gui_ps_units17 + Phase Shift Units + ps + + + gui_phase_shift0 + Desired Phase Shift + 0.0 + + + gui_phase_shift1 + Desired Phase Shift + 0.0 + + + gui_phase_shift2 + Desired Phase Shift + 0.0 + + + gui_phase_shift3 + Desired Phase Shift + 0.0 + + + gui_phase_shift4 + Desired Phase Shift + 0.0 + + + gui_phase_shift5 + Desired Phase Shift + 0.0 + + + gui_phase_shift6 + Desired Phase Shift + 0.0 + + + gui_phase_shift7 + Desired Phase Shift + 0.0 + + + gui_phase_shift8 + Desired Phase Shift + 0.0 + + + gui_phase_shift9 + Desired Phase Shift + 0.0 + + + gui_phase_shift10 + Desired Phase Shift + 0.0 + + + gui_phase_shift11 + Desired Phase Shift + 0.0 + + + gui_phase_shift12 + Desired Phase Shift + 0.0 + + + gui_phase_shift13 + Desired Phase Shift + 0.0 + + + gui_phase_shift14 + Desired Phase Shift + 0.0 + + + gui_phase_shift15 + Desired Phase Shift + 0.0 + + + gui_phase_shift16 + Desired Phase Shift + 0.0 + + + gui_phase_shift17 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg0 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg1 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg2 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg3 + Desired Phase Shift + 90.0 + + + gui_phase_shift_deg4 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg5 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg6 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg7 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg8 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg9 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg10 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg11 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg12 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg13 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg14 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg15 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg16 + Desired Phase Shift + 0.0 + + + gui_phase_shift_deg17 + Desired Phase Shift + 0.0 + + + gui_duty_cycle0 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle1 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle2 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle3 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle4 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle5 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle6 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle7 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle8 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle9 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle10 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle11 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle12 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle13 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle14 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle15 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle16 + Desired Duty Cycle + 50.0 + + + gui_duty_cycle17 + Desired Duty Cycle + 50.0 + + + gui_simulation_type + Force full PLL simulation model + false + + + hp_qsys_scripting_mode + hp_qsys_scripting_mode + false + + + + + + + embeddedsw.dts.compatible + altr,pll + + + embeddedsw.dts.group + clock + + + embeddedsw.dts.vendor + altr + + + + + + + board + Board + default + + + device + Device + AGFB014R24B2E2V + + + deviceFamily + Device family + Agilex 7 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element iopll_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>outclk0</key> + <value> + <connectionPointName>outclk0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>200000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk1</key> + <value> + <connectionPointName>outclk1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk2</key> + <value> + <connectionPointName>outclk2</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>200000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk3</key> + <value> + <connectionPointName>outclk3</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk4</key> + <value> + <connectionPointName>outclk4</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>100000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + dflBitArray + dflBitArray + + + + cpuInfo + cpuInfo + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/sim/io_pll_altera_iopll_1931_oypl3jq.vo b/corev_apu/altera/ip/io_pll/altera_iopll_1931/sim/io_pll_altera_iopll_1931_oypl3jq.vo new file mode 100644 index 0000000000..d4b24db1e2 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/sim/io_pll_altera_iopll_1931_oypl3jq.vo @@ -0,0 +1,450 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// This is a testing TERP file. +// Wrappers for other families can be found in altera_pll.v (pre Arria 10) and twentynm_iopll.v + +`timescale 1ps/1ps +module io_pll_altera_iopll_1931_oypl3jq +( + // interface refclk + input wire refclk, + // interface locked + output wire locked, + // interface reset + input wire rst, + // interface outclk0 + output wire outclk_0, + // interface outclk1 + output wire outclk_1, + // interface outclk2 + output wire outclk_2, + // interface outclk3 + output wire outclk_3, + // interface outclk4 + output wire outclk_4 +); + +wire [1:0] extclk_out_wire; +wire refclk1; +assign refclk1 = 1'b0; +wire fbclk; +assign fbclk = 1'b0; +wire fboutclk; +wire zdbfbclk; +wire [1:0] loaden; +wire phase_done; +wire [29:0] reconfig_to_pll; +assign reconfig_to_pll = 30'b0; +wire scanclk; +assign scanclk = 1'b0; +wire [7:0] phout; +wire [2:0] num_phase_shifts; +assign num_phase_shifts = 3'b0; +wire permit_cal; +assign permit_cal = 1'b1; +wire fblvds_out; +assign fblvds_out = 1'b1; +wire [4:0] cntsel; +assign cntsel = 5'b0; +wire [1:0] clkbad; +wire [1:0] lvds_clk; +wire [8:0] outclk; +wire [2:0] unused_wires_high; + +wire [0:0] unused_wires_low; +assign unused_wires_low = outclk[0:0]; +assign unused_wires_high = outclk[8:6]; +assign outclk_0 = outclk[1]; +assign outclk_1 = outclk[2]; +assign outclk_2 = outclk[3]; +assign outclk_3 = outclk[4]; +assign outclk_4 = outclk[5]; +wire phase_en; +assign phase_en = 1'b0; +wire extswitch; +assign extswitch = 1'b0; +wire cascade_out; +wire dll_output; +assign dll_output = 1'b1; +wire activeclk; +wire adjpllin; +assign adjpllin = 1'b0; +wire updn; +assign updn = 1'b0; +wire [10:0] reconfig_from_pll; + +wire feedback_clk; +wire fb_clkin; +wire fb_out_clk; +wire fboutclk_wire; +wire locked_wire; +wire [10:0] reconfig_from_pll_wire; +wire gnd /* synthesis keep*/; + +// For use in dps pulse gen module. +wire final_updn; +wire final_phase_en; +wire [3:0] final_cntsel; +wire [2:0] final_num_ps; +assign reconfig_from_pll[10:0] = reconfig_from_pll_wire; + +wire adjpllin_wire = 1'b0; +wire dedicated_refclk_wire = 1'b0; + +//Calibration wires +wire cal_ok_wire; + +// Reset logic: + +//Synchronise the reset signal using Flip-Flop to avoid race condition HSD : https://hsdes.intel.com/appstore/article/#/14021123640 +// Uncomment the lines from 160 to 176 and comment lines 189 190 to workaround the race condition for FM87 +// +// +//reg cal_ok_wire_synced; +// +//always @ (posedge refclk or posedge rst) begin +// +// if (rst) begin +// cal_ok_wire_synced <= 1'b0; +// end else begin +// cal_ok_wire_synced <= cal_ok_wire; +// end +// +//end +// +//wire rst_n_wire = ~((rst & cal_ok_wire_synced) | (~permit_cal)); +//wire dprio_rst_n_wire = ~((~reconfig_to_pll[1] & cal_ok_wire_synced) | (~permit_cal)); + +// There are a few scenarios: +// - Upstream PLL : +// - reset is anded with cal_ok_wire so that a reset signal from the +// user can't interrupt calibration. +// - permit_cal tied off to 1 -> rst_n_wire = ~(rst & cal_ok_wire) +// - Downstream PLL: +// - connect upstream locked to downstream permit_cal +// - until upstream PLL is locked, keep reset high so that the PLL +// can't be calibrated. + +// To get the FM hot potato passing temporarily skip cal_ok and permit_cal + +// +//wire rst_n_wire = ~((rst & cal_ok_wire) | (~permit_cal)); +//Removing cal_ok_wire support since its causing race condition in Hardware, +//Cal_ok_wire should not have a self loop happening and also got confirmation +//from PFE that this gating logic is handled within the Hardware HSD: 14021123640 + +wire rst_n_wire = ~(rst | (~permit_cal)); +wire dprio_rst_n_wire = ~((~reconfig_to_pll[1] & cal_ok_wire) | (~permit_cal)); + + +//------------- Counter enable localparams ------------------------------- +localparam counter0_enable = "false"; +localparam counter1_enable = "true"; +localparam counter2_enable = "true"; +localparam counter3_enable = "true"; +localparam counter4_enable = "true"; +localparam counter5_enable = "true"; +localparam counter6_enable = "false"; +localparam counter7_enable = "false"; +localparam counter8_enable = "false"; +//------------- Counter enable localparams ------------------------------- + + +// ========================================================================================== +// Instantiate tennm_iopll! +// ========================================================================================== +tennm_iopll #( + .auto_clk_sw_en("false"), + .bw_mode("mid_bw"), + .c0_bypass_en("true"), + .c0_even_duty_en("false"), + .c0_high(256), + .c0_low(256), + .c0_out_en(counter0_enable), + .c0_ph_mux_prst(0), + .c0_prst(1), + .c1_bypass_en("false"), + .c1_even_duty_en("true"), + .c1_high(3), + .c1_low(2), + .c1_out_en(counter1_enable), + .c1_ph_mux_prst(0), + .c1_prst(1), + .c2_bypass_en("false"), + .c2_even_duty_en("false"), + .c2_high(4), + .c2_low(4), + .c2_out_en(counter2_enable), + .c2_ph_mux_prst(0), + .c2_prst(1), + .c3_bypass_en("false"), + .c3_even_duty_en("true"), + .c3_high(3), + .c3_low(2), + .c3_out_en(counter3_enable), + .c3_ph_mux_prst(0), + .c3_prst(1), + .c4_bypass_en("false"), + .c4_even_duty_en("false"), + .c4_high(4), + .c4_low(4), + .c4_out_en(counter4_enable), + .c4_ph_mux_prst(0), + .c4_prst(3), + .c5_bypass_en("false"), + .c5_even_duty_en("false"), + .c5_high(5), + .c5_low(5), + .c5_out_en(counter5_enable), + .c5_ph_mux_prst(0), + .c5_prst(1), + .c6_bypass_en("true"), + .c6_even_duty_en("false"), + .c6_high(256), + .c6_low(256), + .c6_out_en(counter6_enable), + .c6_ph_mux_prst(0), + .c6_prst(1), + .c7_bypass_en("true"), + .c7_even_duty_en("false"), + .c7_high(256), + .c7_low(256), + .c7_out_en(counter7_enable), + .c7_ph_mux_prst(0), + .c7_prst(1), + .c8_bypass_en("true"), + .c8_even_duty_en("false"), + .c8_high(256), + .c8_low(256), + .c8_out_en(counter8_enable), + .c8_ph_mux_prst(0), + .c8_prst(1), + .clkin_0_src("coreclkin"), + .clkin_1_src("ioclkin_0"), + .clock_name_0(""), + .clock_name_1("outclk0"), + .clock_name_2("outclk1"), + .clock_name_3("outclk2"), + .clock_name_4("outclk3"), + .clock_name_5("outclk4"), + .clock_name_6(""), + .clock_name_7(""), + .clock_name_8(""), + .clock_name_global_0("false"), + .clock_name_global_1("false"), + .clock_name_global_2("false"), + .clock_name_global_3("false"), + .clock_name_global_4("false"), + .clock_name_global_5("false"), + .clock_name_global_6("false"), + .clock_name_global_7("false"), + .clock_name_global_8("false"), + .clock_to_compensate(1), + .duty_cycle_0(50), + .duty_cycle_1(50), + .duty_cycle_2(50), + .duty_cycle_3(50), + .duty_cycle_4(50), + .duty_cycle_5(50), + .duty_cycle_6(50), + .duty_cycle_7(50), + .duty_cycle_8(50), + .extclk_0_cnt_src("pll_extclk_cnt_src_vss"), + .extclk_0_enable("true"), + .extclk_1_cnt_src("pll_extclk_cnt_src_vss"), + .extclk_1_enable("true"), + .feedback("direct"), + .iopll_type("TOP_BOTTOM"), + .m_counter_bypass_en("false"), + .m_counter_even_duty_en("false"), + .m_counter_high(5), + .m_counter_low(5), + .m_counter_scratch(1), + .manu_clk_sw_en("false"), + .merging_permitted("false"), + .n_counter_bypass_en("true"), + .n_counter_high(256), + .n_counter_low(256), + .n_counter_odd_div_duty_en("false"), + .outclk0("0 ps"), + .outclk1("200.0 MHz"), + .outclk2("125.0 MHz"), + .outclk3("200.0 MHz"), + .outclk4("125.0 MHz"), + .outclk5("100.0 MHz"), + .outclk6("0 ps"), + .outclk7("0 ps"), + .outclk8("0 ps"), + .pfd("100.0 MHz"), + .phase_shift_0("0 ps"), + .phase_shift_1("0 ps"), + .phase_shift_2("0 ps"), + .phase_shift_3("0 ps"), + .phase_shift_4("2000 ps"), + .phase_shift_5("0 ps"), + .phase_shift_6("0 ps"), + .phase_shift_7("0 ps"), + .phase_shift_8("0 ps"), + .prot_mode("BASIC"), + .refclk_src_mux("clk_0"), + .refclk_time("100.0 MHz"), + .self_reset_en("false"), + .simple_pll("false"), + .uc_channel_base_addr(16'h0), + .vco("1000.0 MHz") +) tennm_pll ( + .clken(2'b00), + .cnt_sel(4'b0), + .num_phase_shifts(3'b0), + .phase_en(1'b0), + .up_dn(1'b0), + .dprio_clk(1'b0), + .core_refclk(refclk), + .csr_clk(1'b1), + .csr_en(1'b1), + .csr_in(1'b1), + .dprio_rst_n(rst_n_wire), + .dprio_address(9'b0), + .read(1'b0), + .write(1'b0), + .writedata(8'b0), + .pll_select_top_avl(1'b1), // Hardcoded to use the top PLL for now. + .dps_rst_n(rst_n_wire), + .extswitch(extswitch), + .fbclk_in(1'b0), + .fblvds_in(1'b0), + .mdio_dis(1'b0), + .pfden(1'b1), + .pipeline_global_en_n(1'b0), + .pll_cascade_in(adjpllin_wire), + .pma_csr_test_dis(1'b1), + .refclk({2'b0,refclk1, dedicated_refclk_wire}), + .rst_n(rst_n_wire), + .scan_mode_n(1'b1), + .scan_shift_n(1'b1), + .uc_cal_addr(20'b0), + .uc_cal_clk(1'b0), + .uc_cal_read(1'b0), + .uc_cal_write(1'b0), + .uc_cal_writedata(8'b0), + .user_mode(1'b1), + .zdb_in(1'b0), + .block_select(), + .clk0_bad(clkbad[0]), + .clk1_bad(clkbad[1]), + .clksel(activeclk), + .csr_out(), + .dll_output(dll_output), + .extclk_dft(), + .extclk_output({extclk_out_wire[1], fboutclk_wire}), + .fbclk_out(feedback_clk), + .fblvds_out(fblvds_out), + .lf_reset(), + .loaden(loaden), + .lock(locked_wire), + .lvds_clk(lvds_clk), + .outclk(outclk), + .phase_done(phase_done), + .pll_cascade_out(cascade_out), + .pll_pd(), + .readdata(reconfig_from_pll_wire[7:0]), + .vcop_en(), + .vcoph(phout), + .cal_ok(cal_ok_wire) +); + +assign reconfig_from_pll_wire[8] = locked_wire; +assign reconfig_from_pll_wire[9] = phase_done; +assign reconfig_from_pll_wire[10] = cal_ok_wire; +assign extclk_out_wire[0] = fboutclk_wire; + +assign fboutclk = fboutclk_wire; +assign locked = locked_wire; + +// ================================================================================== +// Create clock buffers for fbclk, fboutclk and zdbfbclk if necessary. +// ================================================================================== +assign zdbfbclk = 0; + +endmodule + + +// ================================================================================= +// The final_phase_en signal should be a signal pulse (there was a silicon bug +// involving this problem on Arria 10. DPS pulse gen generates a singe final_phase_en +// pulse when the user_phase_en goes high. +// It also delays the other signal by one clock cycle +// ================================================================================= + +module dps_pulse_gen_io_pll_altera_iopll_1931_oypl3jq ( + input wire clk, // the DPS clock + input wire rst, // active high reset + input wire user_phase_en, // the user's phase_en signal + input wire user_updn, + input wire [2:0] user_num_ps, + input wire [3:0] user_cntsel, + output reg phase_en, // the phase_en signal for the IOPLL atom + output reg updn, + output reg [2:0] num_ps, + output reg [3:0] cntsel + ); + + //------------------------------------------------------------------------- + // States + localparam IDLE = 0, // Idle state: user_phase_en = 0, phase_en = 0 + PULSE = 1, // Activate state: phase_en = 1 + WAIT = 2; // Wait for user_phase_en to go low + + //------------------------------------------------------------------------- + // FSM current and next states + reg [1:0] state, next; + + // State update + always @(posedge clk) begin + + updn <= user_updn; + cntsel <= user_cntsel; + num_ps <= user_num_ps; + + if (rst) state <= IDLE; + else state <= next; + end + + //------------------------------------------------------------------------- + // Next-state and output logic + always @(*) begin + next = IDLE; // Default next state + phase_en = 1'b0; // Default output + + case (state) + IDLE : begin + if (user_phase_en) next = PULSE; + else next = IDLE; + end + + PULSE : begin + phase_en = 1'b1; + next = WAIT; + end + + WAIT : begin + if (~user_phase_en) next = IDLE; + else next = WAIT; + end + endcase + end + + endmodule + + diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/agilex_iobank_pll.ipxact b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/agilex_iobank_pll.ipxact new file mode 100644 index 0000000000..f42f006eed --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/agilex_iobank_pll.ipxact @@ -0,0 +1,3214 @@ + + + + Vendor + Library + fmiopllwrap_top + 1 + + + fmiopllwrap_top_csr + DPRIOCSR + fmiopllwrap_top + + fmiopllwrap_top_csr + xdprio_dps_iopll.xdprio + 0 + 624 + 624 + register + + fmiopllwrap_top_csr + 0 + 624 + + cr_n_hi + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_hi[8:0] + 0 + 9 + false + write-only + + + reserved0 + + 9 + 3 + false + write-only + + + cr_isel + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_isel[2:0] + 12 + 3 + false + write-only + + + cr_n_lo_8 + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_lo[8] + 15 + 1 + false + write-only + + + cr_n_lo + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_lo[7:0] + 16 + 8 + false + write-only + + + cr_m_directfb + xiopll_custom.xiopll_core.xfb.cr_m_directfb + 24 + 1 + false + write-only + + + cr_tclk + xiopll_custom.xiopll_core.xtestmux.cr_tclk[1:0] + 25 + 2 + false + write-only + + + crdly_m + xiopll_custom.xiopll_core.xmcnt_iopll.xpm_fine_dly.crdly[4:0] + 27 + 5 + false + write-only + + + crhi_m + xiopll_custom.xiopll_core.xmcnt_iopll.crhi[8:0] + 32 + 9 + false + write-only + + + crsel_m + xiopll_custom.xiopll_core.xmcnt_iopll.crsel[1:0] + 41 + 2 + false + write-only + + + crprst_m + xiopll_custom.xiopll_core.xmcnt_iopll.crprst[10:0] + 43 + 11 + false + write-only + + + reserved1 + + 54 + 1 + false + write-only + + + crlo_m_8 + xiopll_custom.xiopll_core.xmcnt_iopll.crlo[8] + 55 + 1 + false + write-only + + + crlo_m + xiopll_custom.xiopll_core.xmcnt_iopll.crlo[7:0] + 56 + 8 + false + write-only + + + cr_atpg_up_ndwn + xiopll_custom.xiopll_core.xvco_iopll.cr_atpg_up_ndwn[7:0] + 64 + 8 + false + write-only + + + cr_extclk0_sel + xiopll_custom.xextclk0.crsel[3:0] + 72 + 4 + false + write-only + + + cr_vcocalsel_clk1_2 + xiopll_custom.cr_vcocalsel_clk1[5:3] + 76 + 3 + false + write-only + + + cr_testdnen + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_testdnen + 79 + 1 + false + write-only + + + cr_testupen + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_testupen + 80 + 1 + false + write-only + + + cr_rplctrl + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_rplctrl[1:0] + 81 + 2 + false + write-only + + + cr_bwctrl + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_bwctrl[3:0] + 83 + 4 + false + write-only + + + cr_rcpmode + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_rcpmode + 87 + 1 + false + write-only + + + cr_vcop + xiopll_custom.xiopll_core.xvco_iopll.cr_vcop[7:0] + 88 + 8 + false + write-only + + + cr_lockf + xiopll_custom.xiopll_core.xlockf.cr_lockf[11:0] + 96 + 12 + false + write-only + + + cr_lock_test + xiopll_custom.xiopll_core.xlockf.cr_lock_test + 108 + 1 + false + write-only + + + cr_icp_high + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_icp_high[2:0] + 109 + 3 + false + write-only + + + cr_unlockf + xiopll_custom.xiopll_core.xlockf.cr_unlockf[2:0] + 112 + 3 + false + write-only + + + cr_atb + xiopll_custom.xiopll_core.xatb_iopll.cr_atb[4:0] + 115 + 5 + false + write-only + + + cr_pllen + xfpll_ctrl.cr_pllen|xiopll_custom.xpllcoutbuf0.cr_pllen|xiopll_custom.xpllcoutbuf1.cr_pllen|xiopll_custom.xpllcoutbuf2.cr_pllen|xiopll_custom.xpllcoutbuf3.cr_pllen|xiopll_custom.xpllcoutbuf4.cr_pllen|xiopll_custom.xpllcoutbuf5.cr_pllen|xiopll_custom.xpllcoutbuf6.cr_pllen|xiopll_custom.xpllcoutbuf7.cr_pllen|xiopll_custom.xpllcoutbuf8.cr_pllen + 120 + 1 + false + write-only + + + cr_ctrl_override + xfpll_ctrl.cr_ctrl_override + 121 + 1 + false + write-only + + + cr_testen + xfpll_ctrl.cr_testen + 122 + 1 + false + write-only + + + cr_inv + xfpll_ctrl.cr_inv + 123 + 1 + false + write-only + + + cr_vccd_pd + xfpll_ctrl.cr_vccd_pd + 124 + 1 + false + write-only + + + cr_self_rst + xfpll_ctrl.cr_self_rst[1:0] + 125 + 2 + false + write-only + + + defer_cal_user_mode + xiopll_custom.defer_cal_user_mode + 127 + 1 + false + write-only + + + cr_refclk_dly + xiopll_custom.xiopll_core.xref.cr_refclk_dly[2:0] + 128 + 3 + false + write-only + + + cr_fbclk_sel + xiopll_custom.xiopll_core.xfb.cr_fbclk_sel[1:0] + 131 + 2 + false + write-only + + + cr_fbclk_dly + xiopll_custom.xiopll_core.xfb.cr_fbclk_dly[2:0] + 133 + 3 + false + write-only + + + cr_clksel + xiopll_custom.xclkin_sw.xclkin_mux.xmux1.crsel[2:0],xiopll_custom.xclkin_sw.xclkin_mux.xmux0.crsel[2:0] + 136 + 6 + false + write-only + + + cr_clkin_sw_clkloss_fltr + xiopll_custom.xclkin_sw.xpm_pll_so.cr_clkloss_fltr[1:0] + 142 + 2 + false + write-only + + + cr_so + xiopll_custom.xclkin_sw.xpm_pll_so.cr_so[7:0] + 144 + 8 + false + write-only + + + cr_dll_sel + xiopll_custom.xdllout.crsel[3:0] + 152 + 4 + false + write-only + + + cr_n_dly + xiopll_custom.xiopll_core.xfine_dly_n.crdly[4:0] + 156 + 5 + false + write-only + + + reserved2 + + 161 + 1 + false + write-only + + + cr_extclk0_enable + xiopll_custom.xextclk0.crenable + 162 + 1 + false + write-only + + + cr_extclk0_inv + xiopll_custom.xextclk0.crinv + 163 + 1 + false + write-only + + + cr_extclk1_sel + xiopll_custom.xextclk1.crsel[3:0] + 164 + 4 + false + write-only + + + cr_extclk1_enable + xiopll_custom.xextclk1.crenable + 168 + 1 + false + write-only + + + cr_extclk1_inv + xiopll_custom.xextclk1.crinv + 169 + 1 + false + write-only + + + cr_extclk_dllout_en + xiopll_custom.xcoutbuf3.inb,xiopll_custom.xcoutbuf2.inb,xiopll_custom.xcoutbuf1.inb,xiopll_custom.xcoutbuf0.inb + 170 + 4 + false + write-only + + + cr_fblvdsout + xiopll_custom.x221.cr_fblvdsout + 174 + 1 + false + write-only + + + cr_pllcout8 + xiopll_custom.xpllcoutbuf8.cr_pllcout + 175 + 1 + false + write-only + + + cr_pllcout + xiopll_custom.xpllcoutbuf7.cr_pllcout,xiopll_custom.xpllcoutbuf6.cr_pllcout,xiopll_custom.xpllcoutbuf5.cr_pllcout,xiopll_custom.xpllcoutbuf4.cr_pllcout,xiopll_custom.xpllcoutbuf3.cr_pllcout,xiopll_custom.xpllcoutbuf2.cr_pllcout,xiopll_custom.xpllcoutbuf1.cr_pllcout,xiopll_custom.xpllcoutbuf0.cr_pllcout + 176 + 8 + false + write-only + + + cr_lvds0_dly + xiopll_custom.xfine_dly_0.crdly[4:0] + 184 + 5 + false + write-only + + + cr_lvds0_enable + xiopll_custom.xfine_dly_0.crenable + 189 + 1 + false + write-only + + + cr_lvds1_enable + xiopll_custom.xfine_dly_2.crenable + 190 + 1 + false + write-only + + + cr_cal_converge + xiopll_custom.cr_cal_converge + 191 + 1 + false + write-only + + + cr_loaden0_dly + xiopll_custom.xfine_dly_1.crdly[4:0] + 192 + 5 + false + write-only + + + cr_loaden0_enable + xiopll_custom.xfine_dly_1.crenable + 197 + 1 + false + write-only + + + cr_loaden1_enable + xiopll_custom.xfine_dly_3.crenable + 198 + 1 + false + write-only + + + cr_cal_error + xiopll_custom.cr_cal_error + 199 + 1 + false + write-only + + + cr_lvds1_dly + xiopll_custom.xfine_dly_2.crdly[4:0] + 200 + 5 + false + write-only + + + cr_vcocalsel_clk1_1 + xiopll_custom.cr_vcocalsel_clk1[2:0] + 205 + 3 + false + write-only + + + cr_loaden1_dly + xiopll_custom.xfine_dly_3.crdly[4:0] + 208 + 5 + false + write-only + + + cr_cal_done + xiopll_custom.cr_cal_done + 213 + 1 + false + write-only + + + cr_ref_clkloss_fltr + xiopll_custom.xiopll_core.xtestmux.cr_ref_clkloss_fltr[1:0] + 214 + 2 + false + write-only + + + crhi_c0 + xiopll_custom.xccnt_iopll0.crhi[8:0] + 216 + 9 + false + write-only + + + crsel_c0 + xiopll_custom.xccnt_iopll0.crsel[1:0] + 225 + 2 + false + write-only + + + crprst_c0 + xiopll_custom.xccnt_iopll0.crprst[10:0] + 227 + 11 + false + write-only + + + reserved3 + + 238 + 1 + false + write-only + + + crlo_c0_8 + xiopll_custom.xccnt_iopll0.crlo[8] + 239 + 1 + false + write-only + + + crlo_c0 + xiopll_custom.xccnt_iopll0.crlo[7:0] + 240 + 8 + false + write-only + + + crhi_c1 + xiopll_custom.xccnt_iopll1.crhi[8:0] + 248 + 9 + false + write-only + + + crsel_c1 + xiopll_custom.xccnt_iopll1.crsel[1:0] + 257 + 2 + false + write-only + + + crprst_c1 + xiopll_custom.xccnt_iopll1.crprst[10:0] + 259 + 11 + false + write-only + + + reserved4 + + 270 + 1 + false + write-only + + + crlo_c1_8 + xiopll_custom.xccnt_iopll1.crlo[8] + 271 + 1 + false + write-only + + + crlo_c1 + xiopll_custom.xccnt_iopll1.crlo[7:0] + 272 + 8 + false + write-only + + + crhi_c2 + xiopll_custom.xccnt_iopll2.crhi[8:0] + 280 + 9 + false + write-only + + + crsel_c2 + xiopll_custom.xccnt_iopll2.crsel[1:0] + 289 + 2 + false + write-only + + + crprst_c2 + xiopll_custom.xccnt_iopll2.crprst[10:0] + 291 + 11 + false + write-only + + + reserved5 + + 302 + 1 + false + write-only + + + crlo_c2_8 + xiopll_custom.xccnt_iopll2.crlo[8] + 303 + 1 + false + write-only + + + crlo_c2 + xiopll_custom.xccnt_iopll2.crlo[7:0] + 304 + 8 + false + write-only + + + crhi_c3 + xiopll_custom.xccnt_iopll3.crhi[8:0] + 312 + 9 + false + write-only + + + crsel_c3 + xiopll_custom.xccnt_iopll3.crsel[1:0] + 321 + 2 + false + write-only + + + crprst_c3 + xiopll_custom.xccnt_iopll3.crprst[10:0] + 323 + 11 + false + write-only + + + reserved6 + + 334 + 1 + false + write-only + + + crlo_c3_8 + xiopll_custom.xccnt_iopll3.crlo[8] + 335 + 1 + false + write-only + + + crlo_c3 + xiopll_custom.xccnt_iopll3.crlo[7:0] + 336 + 8 + false + write-only + + + crhi_c4 + xiopll_custom.xccnt_iopll4.crhi[8:0] + 344 + 9 + false + write-only + + + crsel_c4 + xiopll_custom.xccnt_iopll4.crsel[1:0] + 353 + 2 + false + write-only + + + crprst_c4 + xiopll_custom.xccnt_iopll4.crprst[10:0] + 355 + 11 + false + write-only + + + reserved7 + + 366 + 1 + false + write-only + + + crlo_c4_8 + xiopll_custom.xccnt_iopll4.crlo[8] + 367 + 1 + false + write-only + + + crlo_c4 + xiopll_custom.xccnt_iopll4.crlo[7:0] + 368 + 8 + false + write-only + + + crhi_c5 + xiopll_custom.xccnt_iopll5.crhi[8:0] + 376 + 9 + false + write-only + + + crsel_c5 + xiopll_custom.xccnt_iopll5.crsel[1:0] + 385 + 2 + false + write-only + + + crprst_c5 + xiopll_custom.xccnt_iopll5.crprst[10:0] + 387 + 11 + false + write-only + + + reserved8 + + 398 + 1 + false + write-only + + + crlo_c5_8 + xiopll_custom.xccnt_iopll5.crlo[8] + 399 + 1 + false + write-only + + + crlo_c5 + xiopll_custom.xccnt_iopll5.crlo[7:0] + 400 + 8 + false + write-only + + + crhi_c6 + xiopll_custom.xccnt_iopll6.crhi[8:0] + 408 + 9 + false + write-only + + + crsel_c6 + xiopll_custom.xccnt_iopll6.crsel[1:0] + 417 + 2 + false + write-only + + + crprst_c6 + xiopll_custom.xccnt_iopll6.crprst[10:0] + 419 + 11 + false + write-only + + + reserved9 + + 430 + 1 + false + write-only + + + crlo_c6_8 + xiopll_custom.xccnt_iopll6.crlo[8] + 431 + 1 + false + write-only + + + crlo_c6 + xiopll_custom.xccnt_iopll6.crlo[7:0] + 432 + 8 + false + write-only + + + crhi_c7 + xiopll_custom.xccnt_iopll7.crhi[8:0] + 440 + 9 + false + write-only + + + crsel_c7 + xiopll_custom.xccnt_iopll7.crsel[1:0] + 449 + 2 + false + write-only + + + crprst_c7 + xiopll_custom.xccnt_iopll7.crprst[10:0] + 451 + 11 + false + write-only + + + reserved10 + + 462 + 1 + false + write-only + + + crlo_c7_8 + xiopll_custom.xccnt_iopll7.crlo[8] + 463 + 1 + false + write-only + + + crlo_c7 + xiopll_custom.xccnt_iopll7.crlo[7:0] + 464 + 8 + false + write-only + + + crhi_c8 + xiopll_custom.xccnt_iopll8.crhi[8:0] + 472 + 9 + false + write-only + + + crsel_c8 + xiopll_custom.xccnt_iopll8.crsel[1:0] + 481 + 2 + false + write-only + + + crprst_c8 + xiopll_custom.xccnt_iopll8.crprst[10:0] + 483 + 11 + false + write-only + + + reserved11 + + 494 + 1 + false + write-only + + + crlo_c8_8 + xiopll_custom.xccnt_iopll8.crlo[8] + 495 + 1 + false + write-only + + + crlo_c8 + xiopll_custom.xccnt_iopll8.crlo[7:0] + 496 + 8 + false + write-only + + + crdly_c0 + xiopll_custom.xccnt_iopll0.xpm_fine_dly.crdly[4:0] + 504 + 5 + false + write-only + + + cr_clkloss_det_en + xiopll_custom.xiopll_core.xtestmux.cr_clkloss_det_en + 509 + 1 + false + write-only + + + crdly_c1 + xiopll_custom.xccnt_iopll1.xpm_fine_dly.crdly[4:0] + 510 + 5 + false + write-only + + + cr_pllreset + xiopll_custom.cr_pllreset + 515 + 1 + false + write-only + + + crdly_c2 + xiopll_custom.xccnt_iopll2.xpm_fine_dly.crdly[4:0] + 516 + 5 + false + write-only + + + cr_clkloss_det_fb_ovrd + xiopll_custom.xiopll_core.xtestmux.cr_clkloss_det_fb_ovrd + 521 + 1 + false + write-only + + + crdly_c3 + xiopll_custom.xccnt_iopll3.xpm_fine_dly.crdly[4:0] + 522 + 5 + false + write-only + + + cr_cal_en_vreg0 + xiopll_custom.xvreg_0p9v0.cal_en + 527 + 1 + false + write-only + + + crdly_c4 + xiopll_custom.xccnt_iopll4.xpm_fine_dly.crdly[4:0] + 528 + 5 + false + write-only + + + cr_refclk_equal + xiopll_custom.cr_refclk_equal + 533 + 1 + false + write-only + + + crdly_c5 + xiopll_custom.xccnt_iopll5.xpm_fine_dly.crdly[4:0] + 534 + 5 + false + write-only + + + user_handle_cal_fail + xiopll_custom.user_handle_cal_fail + 539 + 1 + false + write-only + + + crdly_c6 + xiopll_custom.xccnt_iopll6.xpm_fine_dly.crdly[4:0] + 540 + 5 + false + write-only + + + cr_cal_en_vreg1 + xiopll_custom.xvreg_0p9v1.cal_en + 545 + 1 + false + write-only + + + crdly_c7 + xiopll_custom.xccnt_iopll7.xpm_fine_dly.crdly[4:0] + 546 + 5 + false + write-only + + + cr_ppmclk + xiopll_custom.xpllcoutbuf0.cr_ppmclk|xiopll_custom.xpllcoutbuf1.cr_ppmclk|xiopll_custom.xpllcoutbuf2.cr_ppmclk|xiopll_custom.xpllcoutbuf3.cr_ppmclk|xiopll_custom.xpllcoutbuf4.cr_ppmclk|xiopll_custom.xpllcoutbuf5.cr_ppmclk|xiopll_custom.xpllcoutbuf6.cr_ppmclk|xiopll_custom.xpllcoutbuf7.cr_ppmclk|xiopll_custom.xpllcoutbuf8.cr_ppmclk + 551 + 1 + false + write-only + + + crdly_c8 + xiopll_custom.xccnt_iopll8.xpm_fine_dly.crdly[4:0] + 552 + 5 + false + write-only + + + cr_plniotri + xfpll_ctrl.cr_plniotri + 557 + 1 + false + write-only + + + cr_fb_clkloss_fltr + xiopll_custom.xiopll_core.xtestmux.cr_fb_clkloss_fltr[1:0] + 558 + 2 + false + write-only + + + + cr_vreg0calsel + xiopll_custom.xvreg_0p9v0.calsel[4:0] + 560 + 5 + false + write-only + + + + cr_lckdet_sel + xiopll_custom.xiopll_core.xlockdet.cr_lckdet_sel[2:0] + 565 + 3 + false + write-only + + + + cr_vreg1calsel + xiopll_custom.xvreg_0p9v1.calsel[4:0] + 568 + 5 + false + write-only + + + + cr_lckdet_hys_sel + xiopll_custom.xiopll_core.xlockdet.cr_lckdet_hys_sel[2:0] + 573 + 3 + false + write-only + + + + cr_vreg0_override + xiopll_custom.xvreg_0p9v0.ovrride + 576 + 1 + false + write-only + + + + cr_vreg1_override + xiopll_custom.xvreg_0p9v1.ovrride + 577 + 1 + false + write-only + + + + cr_vcocalsel_clk0 + xiopll_custom.cr_vcocalsel_clk0[5:0] + 578 + 6 + false + write-only + + + + cr_freqcal_en + xiopll_custom.cr_freqcal_en + 584 + 1 + false + write-only + + + + cr_freqcal_biasctl + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_freqcal_biasctl[2:0] + 585 + 3 + false + write-only + + + + cr_clk_sel_override + xiopll_custom.xclkin_sw.xpm_pll_so.cr_clk_sel_override + 588 + 1 + false + write-only + + + cr_clk_sel_override_value + xiopll_custom.xclkin_sw.xpm_pll_so.cr_clk_sel_override_value + 589 + 1 + false + write-only + + + cr_freqcal_req_flag + xiopll_custom.cr_freqcal_req_flag + 590 + 1 + false + write-only + + + cr_vcocal_rstb + xiopll_custom.xiopll_core.xvco_cal.resetb + 591 + 1 + false + write-only + + + cr_dprio_interface_sel + xdprio_dps_iopll.dprio_out_reg[599:592] + 592 + 8 + false + write-only + + + dprio_base_addr + xdprio_dps_iopll.dprio_base_addr[8:0] + 600 + 9 + false + write-only + + + coreAvlBaseAddress + 0 + + + + + r_calibration_en + xdprio_dps_iopll.r_calibration_en + 609 + 1 + false + write-only + + + extra_csr + xdprio_dps_iopll.extra_csr[11:10] + 610 + 2 + false + write-only + + + dprio_cvp_inter_sel_csr_ctrl + xdprio_dps_iopll.dprio_cvp_inter_sel_csr_ctrl + 612 + 1 + false + write-only + + + dprio_force_inter_sel_csr_ctrl + xdprio_dps_iopll.dprio_force_inter_sel_csr_ctrl + 613 + 1 + false + write-only + + + dprio_broadcast_en_csr_ctrl + xdprio_dps_iopll.dprio_broadcast_en_csr_ctrl + 614 + 1 + false + write-only + + + dprio_power_iso_en_csr_ctrl + xdprio_dps_iopll.dprio_power_iso_en_csr_ctrl + 615 + 1 + false + write-only + + + uc_channel_base_addr + xdprio_dps_iopll.uc_channel_base_addr[7:0] + 616 + 8 + false + write-only + + + + 1 + + + fmiopllwrap_top_avl + DPRIOAVL + fmiopllwrap_top + + fmiopllwrap_top_avl + 0 + 600 + 8 + register + + iopll_reg_0 + 0x0 + 8 + + cr_n_hi + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_hi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_1 + 0x1 + 8 + + cr_n_hi + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_hi[8] + 0 + 1 + false + read-write + + + reserved0 + + 1 + 3 + false + read-write + + + cr_isel + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_isel[2:0] + 4 + 3 + false + read-write + + + cr_n_lo_8 + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_lo[8] + 7 + 1 + false + read-write + + + + iopll_reg_2 + 0x2 + 8 + + cr_n_lo + xiopll_custom.xiopll_core.xncnt_iopll.cr_n_lo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_3 + 0x3 + 8 + + cr_m_directfb + xiopll_custom.xiopll_core.xfb.cr_m_directfb + 0 + 1 + false + read-write + + + cr_tclk + xiopll_custom.xiopll_core.xtestmux.cr_tclk[1:0] + 1 + 2 + false + read-write + + + crdly_m + xiopll_custom.xiopll_core.xmcnt_iopll.xpm_fine_dly.crdly[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_4 + 0x4 + 8 + + crhi_m + xiopll_custom.xiopll_core.xmcnt_iopll.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_5 + 0x5 + 8 + + crhi_m + xiopll_custom.xiopll_core.xmcnt_iopll.crhi[8] + 0 + 1 + false + read-write + + + crsel_m + xiopll_custom.xiopll_core.xmcnt_iopll.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_m + xiopll_custom.xiopll_core.xmcnt_iopll.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_6 + 0x6 + 8 + + crprst_m + xiopll_custom.xiopll_core.xmcnt_iopll.crprst[10:5] + 0 + 6 + false + read-write + + + reserved1 + + 6 + 1 + false + read-write + + + crlo_m_8 + xiopll_custom.xiopll_core.xmcnt_iopll.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_7 + 0x7 + 8 + + crlo_m + xiopll_custom.xiopll_core.xmcnt_iopll.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_8 + 0x8 + 8 + + cr_atpg_up_ndwn + xiopll_custom.xiopll_core.xvco_iopll.cr_atpg_up_ndwn[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_9 + 0x9 + 8 + + cr_extclk0_sel + xiopll_custom.xextclk0.crsel[3:0] + 0 + 4 + false + read-write + + + cr_vcocalsel_clk1_2 + xiopll_custom.cr_vcocalsel_clk1[5:3] + 4 + 3 + false + read-write + + + cr_testdnen + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_testdnen + 7 + 1 + false + read-write + + + + iopll_reg_10 + 0xa + 8 + + cr_testupen + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_testupen + 0 + 1 + false + read-write + + + cr_rplctrl + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_rplctrl[1:0] + 1 + 2 + false + read-write + + + cr_bwctrl + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_bwctrl[3:0] + 3 + 4 + false + read-write + + + cr_rcpmode + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_rcpmode + 7 + 1 + false + read-write + + + + iopll_reg_11 + 0xb + 8 + + cr_vcop + xiopll_custom.xiopll_core.xvco_iopll.cr_vcop[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_12 + 0xc + 8 + + cr_lockf + xiopll_custom.xiopll_core.xlockf.cr_lockf[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_13 + 0xd + 8 + + cr_lockf + xiopll_custom.xiopll_core.xlockf.cr_lockf[11:8] + 0 + 4 + false + read-write + + + cr_lock_test + xiopll_custom.xiopll_core.xlockf.cr_lock_test + 4 + 1 + false + read-write + + + cr_icp_high + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_icp_high[2:0] + 5 + 3 + false + read-write + + + + + iopll_reg_14 + 0xe + 8 + + cr_unlockf + xiopll_custom.xiopll_core.xlockf.cr_unlockf[2:0] + 0 + 3 + false + read-write + + + cr_atb + xiopll_custom.xiopll_core.xatb_iopll.cr_atb[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_15 + 0xf + 8 + + cr_pllen + xfpll_ctrl.cr_pllen|xiopll_custom.xpllcoutbuf0.cr_pllen|xiopll_custom.xpllcoutbuf1.cr_pllen|xiopll_custom.xpllcoutbuf2.cr_pllen|xiopll_custom.xpllcoutbuf3.cr_pllen|xiopll_custom.xpllcoutbuf4.cr_pllen|xiopll_custom.xpllcoutbuf5.cr_pllen|xiopll_custom.xpllcoutbuf6.cr_pllen|xiopll_custom.xpllcoutbuf7.cr_pllen|xiopll_custom.xpllcoutbuf8.cr_pllen + 0 + 1 + false + read-write + + + cr_ctrl_override + xfpll_ctrl.cr_ctrl_override + 1 + 1 + false + read-write + + + cr_testen + xfpll_ctrl.cr_testen + 2 + 1 + false + read-write + + + cr_inv + xfpll_ctrl.cr_inv + 3 + 1 + false + read-write + + + cr_vccd_pd + xfpll_ctrl.cr_vccd_pd + 4 + 1 + false + read-write + + + cr_self_rst + xfpll_ctrl.cr_self_rst[1:0] + 5 + 2 + false + read-write + + + defer_cal_user_mode + xiopll_custom.defer_cal_user_mode + 7 + 1 + false + read-write + + + + iopll_reg_16 + 0x10 + 8 + + cr_refclk_dly + xiopll_custom.xiopll_core.xref.cr_refclk_dly[2:0] + 0 + 3 + false + read-write + + + cr_fbclk_sel + xiopll_custom.xiopll_core.xfb.cr_fbclk_sel[1:0] + 3 + 2 + false + read-write + + + cr_fbclk_dly + xiopll_custom.xiopll_core.xfb.cr_fbclk_dly[2:0] + 5 + 3 + false + read-write + + + + iopll_reg_17 + 0x11 + 8 + + cr_clksel + xiopll_custom.xclkin_sw.xclkin_mux.xmux1.crsel[2:0],xiopll_custom.xclkin_sw.xclkin_mux.xmux0.crsel[2:0] + 0 + 6 + false + read-write + + + cr_clkin_sw_clkloss_fltr + xiopll_custom.xclkin_sw.xpm_pll_so.cr_clkloss_fltr[1:0] + 6 + 2 + false + read-write + + + + iopll_reg_18 + 0x12 + 8 + + cr_so + xiopll_custom.xclkin_sw.xpm_pll_so.cr_so[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_19 + 0x13 + 8 + + cr_dll_sel + xiopll_custom.xdllout.crsel[3:0] + 0 + 4 + false + read-write + + + cr_n_dly + xiopll_custom.xiopll_core.xfine_dly_n.crdly[3:0] + 4 + 4 + false + read-write + + + + iopll_reg_20 + 0x14 + 8 + + cr_n_dly + xiopll_custom.xiopll_core.xfine_dly_n.crdly[4] + 0 + 1 + false + read-write + + + reserved2 + + 1 + 1 + false + read-write + + + cr_extclk0_enable + xiopll_custom.xextclk0.crenable + 2 + 1 + false + read-write + + + cr_extclk0_inv + xiopll_custom.xextclk0.crinv + 3 + 1 + false + read-write + + + cr_extclk1_sel + xiopll_custom.xextclk1.crsel[3:0] + 4 + 4 + false + read-write + + + + iopll_reg_21 + 0x15 + 8 + + cr_extclk1_enable + xiopll_custom.xextclk1.crenable + 0 + 1 + false + read-write + + + cr_extclk1_inv + xiopll_custom.xextclk1.crinv + 1 + 1 + false + read-write + + + cr_extclk_dllout_en + xiopll_custom.xcoutbuf3.inb,xiopll_custom.xcoutbuf2.inb,xiopll_custom.xcoutbuf1.inb,xiopll_custom.xcoutbuf0.inb + 2 + 4 + false + read-write + + + cr_fblvdsout + xiopll_custom.x221.cr_fblvdsout + 6 + 1 + false + read-write + + + cr_pllcout8 + xiopll_custom.xpllcoutbuf8.cr_pllcout + 7 + 1 + false + read-write + + + + iopll_reg_22 + 0x16 + 8 + + cr_pllcout + xiopll_custom.xpllcoutbuf7.cr_pllcout,xiopll_custom.xpllcoutbuf6.cr_pllcout,xiopll_custom.xpllcoutbuf5.cr_pllcout,xiopll_custom.xpllcoutbuf4.cr_pllcout,xiopll_custom.xpllcoutbuf3.cr_pllcout,xiopll_custom.xpllcoutbuf2.cr_pllcout,xiopll_custom.xpllcoutbuf1.cr_pllcout,xiopll_custom.xpllcoutbuf0.cr_pllcout + 0 + 8 + false + read-write + + + + iopll_reg_23 + 0x17 + 8 + + cr_lvds0_dly + xiopll_custom.xfine_dly_0.crdly[4:0] + 0 + 5 + false + read-write + + + cr_lvds0_enable + xiopll_custom.xfine_dly_0.crenable + 5 + 1 + false + read-write + + + cr_lvds1_enable + xiopll_custom.xfine_dly_2.crenable + 6 + 1 + false + read-write + + + cr_cal_converge + xiopll_custom.cr_cal_converge + 7 + 1 + false + read-write + + + + iopll_reg_24 + 0x18 + 8 + + cr_loaden0_dly + xiopll_custom.xfine_dly_1.crdly[4:0] + 0 + 5 + false + read-write + + + cr_loaden0_enable + xiopll_custom.xfine_dly_1.crenable + 5 + 1 + false + read-write + + + cr_loaden1_enable + xiopll_custom.xfine_dly_3.crenable + 6 + 1 + false + read-write + + + cr_cal_error + xiopll_custom.cr_cal_error + 7 + 1 + false + read-write + + + + iopll_reg_25 + 0x19 + 8 + + cr_lvds1_dly + xiopll_custom.xfine_dly_2.crdly[4:0] + 0 + 5 + false + read-write + + + cr_vcocalsel_clk1_1 + xiopll_custom.cr_vcocalsel_clk1[2:0] + 5 + 3 + false + read-write + + + + iopll_reg_26 + 0x1a + 8 + + cr_loaden1_dly + xiopll_custom.xfine_dly_3.crdly[4:0] + 0 + 5 + false + read-write + + + cr_cal_done + xiopll_custom.cr_cal_done + 5 + 1 + false + read-write + + + cr_ref_clkloss_fltr + xiopll_custom.xiopll_core.xtestmux.cr_ref_clkloss_fltr[1:0] + 6 + 2 + false + read-write + + + + iopll_reg_27 + 0x1b + 8 + + crhi_c0 + xiopll_custom.xccnt_iopll0.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_28 + 0x1c + 8 + + crhi_c0 + xiopll_custom.xccnt_iopll0.crhi[8] + 0 + 1 + false + read-write + + + crsel_c0 + xiopll_custom.xccnt_iopll0.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c0 + xiopll_custom.xccnt_iopll0.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_29 + 0x1d + 8 + + crprst_c0 + xiopll_custom.xccnt_iopll0.crprst[10:5] + 0 + 6 + false + read-write + + + reserved3 + + 6 + 1 + false + read-write + + + crlo_c0_8 + xiopll_custom.xccnt_iopll0.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_30 + 0x1e + 8 + + crlo_c0 + xiopll_custom.xccnt_iopll0.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_31 + 0x1f + 8 + + crhi_c1 + xiopll_custom.xccnt_iopll1.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_32 + 0x20 + 8 + + crhi_c1 + xiopll_custom.xccnt_iopll1.crhi[8] + 0 + 1 + false + read-write + + + crsel_c1 + xiopll_custom.xccnt_iopll1.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c1 + xiopll_custom.xccnt_iopll1.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_33 + 0x21 + 8 + + crprst_c1 + xiopll_custom.xccnt_iopll1.crprst[10:5] + 0 + 6 + false + read-write + + + reserved4 + + 6 + 1 + false + read-write + + + crlo_c1_8 + xiopll_custom.xccnt_iopll1.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_34 + 0x22 + 8 + + crlo_c1 + xiopll_custom.xccnt_iopll1.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_35 + 0x23 + 8 + + crhi_c2 + xiopll_custom.xccnt_iopll2.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_36 + 0x24 + 8 + + crhi_c2 + xiopll_custom.xccnt_iopll2.crhi[8] + 0 + 1 + false + read-write + + + crsel_c2 + xiopll_custom.xccnt_iopll2.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c2 + xiopll_custom.xccnt_iopll2.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_37 + 0x25 + 8 + + crprst_c2 + xiopll_custom.xccnt_iopll2.crprst[10:5] + 0 + 6 + false + read-write + + + reserved5 + + 6 + 1 + false + read-write + + + crlo_c2_8 + xiopll_custom.xccnt_iopll2.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_38 + 0x26 + 8 + + crlo_c2 + xiopll_custom.xccnt_iopll2.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_39 + 0x27 + 8 + + crhi_c3 + xiopll_custom.xccnt_iopll3.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_40 + 0x28 + 8 + + crhi_c3 + xiopll_custom.xccnt_iopll3.crhi[8] + 0 + 1 + false + read-write + + + crsel_c3 + xiopll_custom.xccnt_iopll3.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c3 + xiopll_custom.xccnt_iopll3.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_41 + 0x29 + 8 + + crprst_c3 + xiopll_custom.xccnt_iopll3.crprst[10:5] + 0 + 6 + false + read-write + + + reserved6 + + 6 + 1 + false + read-write + + + crlo_c3_8 + xiopll_custom.xccnt_iopll3.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_42 + 0x2a + 8 + + crlo_c3 + xiopll_custom.xccnt_iopll3.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_43 + 0x2b + 8 + + crhi_c4 + xiopll_custom.xccnt_iopll4.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_44 + 0x2c + 8 + + crhi_c4 + xiopll_custom.xccnt_iopll4.crhi[8] + 0 + 1 + false + read-write + + + crsel_c4 + xiopll_custom.xccnt_iopll4.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c4 + xiopll_custom.xccnt_iopll4.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_45 + 0x2d + 8 + + crprst_c4 + xiopll_custom.xccnt_iopll4.crprst[10:5] + 0 + 6 + false + read-write + + + reserved7 + + 6 + 1 + false + read-write + + + crlo_c4_8 + xiopll_custom.xccnt_iopll4.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_46 + 0x2e + 8 + + crlo_c4 + xiopll_custom.xccnt_iopll4.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_47 + 0x2f + 8 + + crhi_c5 + xiopll_custom.xccnt_iopll5.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_48 + 0x30 + 8 + + crhi_c5 + xiopll_custom.xccnt_iopll5.crhi[8] + 0 + 1 + false + read-write + + + crsel_c5 + xiopll_custom.xccnt_iopll5.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c5 + xiopll_custom.xccnt_iopll5.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_49 + 0x31 + 8 + + crprst_c5 + xiopll_custom.xccnt_iopll5.crprst[10:5] + 0 + 6 + false + read-write + + + reserved8 + + 6 + 1 + false + read-write + + + crlo_c5_8 + xiopll_custom.xccnt_iopll5.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_50 + 0x32 + 8 + + crlo_c5 + xiopll_custom.xccnt_iopll5.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_51 + 0x33 + 8 + + crhi_c6 + xiopll_custom.xccnt_iopll6.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_52 + 0x34 + 8 + + crhi_c6 + xiopll_custom.xccnt_iopll6.crhi[8] + 0 + 1 + false + read-write + + + crsel_c6 + xiopll_custom.xccnt_iopll6.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c6 + xiopll_custom.xccnt_iopll6.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_53 + 0x35 + 8 + + crprst_c6 + xiopll_custom.xccnt_iopll6.crprst[10:5] + 0 + 6 + false + read-write + + + reserved9 + + 6 + 1 + false + read-write + + + crlo_c6_8 + xiopll_custom.xccnt_iopll6.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_54 + 0x36 + 8 + + crlo_c6 + xiopll_custom.xccnt_iopll6.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_55 + 0x37 + 8 + + crhi_c7 + xiopll_custom.xccnt_iopll7.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_56 + 0x38 + 8 + + crhi_c7 + xiopll_custom.xccnt_iopll7.crhi[8] + 0 + 1 + false + read-write + + + crsel_c7 + xiopll_custom.xccnt_iopll7.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c7 + xiopll_custom.xccnt_iopll7.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_57 + 0x39 + 8 + + crprst_c7 + xiopll_custom.xccnt_iopll7.crprst[10:5] + 0 + 6 + false + read-write + + + reserved10 + + 6 + 1 + false + read-write + + + crlo_c7_8 + xiopll_custom.xccnt_iopll7.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_58 + 0x3a + 8 + + crlo_c7 + xiopll_custom.xccnt_iopll7.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_59 + 0x3b + 8 + + crhi_c8 + xiopll_custom.xccnt_iopll8.crhi[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_60 + 0x3c + 8 + + crhi_c8 + xiopll_custom.xccnt_iopll8.crhi[8] + 0 + 1 + false + read-write + + + crsel_c8 + xiopll_custom.xccnt_iopll8.crsel[1:0] + 1 + 2 + false + read-write + + + crprst_c8 + xiopll_custom.xccnt_iopll8.crprst[4:0] + 3 + 5 + false + read-write + + + + iopll_reg_61 + 0x3d + 8 + + crprst_c8 + xiopll_custom.xccnt_iopll8.crprst[10:5] + 0 + 6 + false + read-write + + + reserved11 + + 6 + 1 + false + read-write + + + crlo_c8_8 + xiopll_custom.xccnt_iopll8.crlo[8] + 7 + 1 + false + read-write + + + + iopll_reg_62 + 0x3e + 8 + + crlo_c8 + xiopll_custom.xccnt_iopll8.crlo[7:0] + 0 + 8 + false + read-write + + + + iopll_reg_63 + 0x3f + 8 + + crdly_c0 + xiopll_custom.xccnt_iopll0.xpm_fine_dly.crdly[4:0] + 0 + 5 + false + read-write + + + cr_clkloss_det_en + xiopll_custom.xiopll_core.xtestmux.cr_clkloss_det_en + 5 + 1 + false + read-write + + + crdly_c1 + xiopll_custom.xccnt_iopll1.xpm_fine_dly.crdly[1:0] + 6 + 2 + false + read-write + + + + iopll_reg_64 + 0x40 + 8 + + crdly_c1 + xiopll_custom.xccnt_iopll1.xpm_fine_dly.crdly[4:2] + 0 + 3 + false + read-write + + + cr_pllreset + xiopll_custom.cr_pllreset + 3 + 1 + false + read-write + + + crdly_c2 + xiopll_custom.xccnt_iopll2.xpm_fine_dly.crdly[3:0] + 4 + 4 + false + read-write + + + + iopll_reg_65 + 0x41 + 8 + + crdly_c2 + xiopll_custom.xccnt_iopll2.xpm_fine_dly.crdly[4] + 0 + 1 + false + read-write + + + cr_clkloss_det_fb_ovrd + xiopll_custom.xiopll_core.xtestmux.cr_clkloss_det_fb_ovrd + 1 + 1 + false + read-write + + + crdly_c3 + xiopll_custom.xccnt_iopll3.xpm_fine_dly.crdly[4:0] + 2 + 5 + false + read-write + + + cr_cal_en_vreg0 + xiopll_custom.xvreg_0p9v0.cal_en + 7 + 1 + false + read-write + + + + iopll_reg_66 + 0x42 + 8 + + crdly_c4 + xiopll_custom.xccnt_iopll4.xpm_fine_dly.crdly[4:0] + 0 + 5 + false + read-write + + + cr_refclk_equal + xiopll_custom.cr_refclk_equal + 5 + 1 + false + read-write + + + crdly_c5 + xiopll_custom.xccnt_iopll5.xpm_fine_dly.crdly[1:0] + 6 + 2 + false + read-write + + + + iopll_reg_67 + 0x43 + 8 + + crdly_c5 + xiopll_custom.xccnt_iopll5.xpm_fine_dly.crdly[4:2] + 0 + 3 + false + read-write + + + user_handle_cal_fail + xiopll_custom.user_handle_cal_fail + 3 + 1 + false + read-write + + + crdly_c6 + xiopll_custom.xccnt_iopll6.xpm_fine_dly.crdly[3:0] + 4 + 4 + false + read-write + + + + iopll_reg_68 + 0x44 + 8 + + crdly_c6 + xiopll_custom.xccnt_iopll6.xpm_fine_dly.crdly[4] + 0 + 1 + false + read-write + + + cr_cal_en_vreg1 + xiopll_custom.xvreg_0p9v1.cal_en + 1 + 1 + false + read-write + + + crdly_c7 + xiopll_custom.xccnt_iopll7.xpm_fine_dly.crdly[4:0] + 2 + 5 + false + read-write + + + cr_ppmclk + xiopll_custom.xpllcoutbuf0.cr_ppmclk|xiopll_custom.xpllcoutbuf1.cr_ppmclk|xiopll_custom.xpllcoutbuf2.cr_ppmclk|xiopll_custom.xpllcoutbuf3.cr_ppmclk|xiopll_custom.xpllcoutbuf4.cr_ppmclk|xiopll_custom.xpllcoutbuf5.cr_ppmclk|xiopll_custom.xpllcoutbuf6.cr_ppmclk|xiopll_custom.xpllcoutbuf7.cr_ppmclk|xiopll_custom.xpllcoutbuf8.cr_ppmclk + 7 + 1 + false + read-write + + + + iopll_reg_69 + 0x45 + 8 + + crdly_c8 + xiopll_custom.xccnt_iopll8.xpm_fine_dly.crdly[4:0] + 0 + 5 + false + read-write + + + cr_plniotri + xfpll_ctrl.cr_plniotri + 5 + 1 + false + read-write + + + cr_fb_clkloss_fltr + xiopll_custom.xiopll_core.xtestmux.cr_fb_clkloss_fltr[1:0] + 6 + 2 + false + read-write + + + + + + iopll_reg_70 + 0x46 + 8 + + cr_vreg0calsel + xiopll_custom.xvreg_0p9v0.calsel[4:0] + 0 + 5 + false + read-write + + + cr_lckdet_sel + xiopll_custom.xiopll_core.xlockdet.cr_lckdet_sel[2:0] + 5 + 3 + false + read-write + + + + + iopll_reg_71 + 0x47 + 8 + + cr_vreg1calsel + xiopll_custom.xvreg_0p9v1.calsel[4:0] + 0 + 5 + false + read-write + + + cr_lckdet_hys_sel + xiopll_custom.xiopll_core.xlockdet.cr_lckdet_hys_sel[2:0] + 5 + 3 + false + read-write + + + + + iopll_reg_72 + 0x48 + 8 + + cr_vreg0_override + xiopll_custom.xvreg_0p9v0.ovrride + 0 + 1 + false + read-write + + + cr_vreg1_override + xiopll_custom.xvreg_0p9v1.ovrride + 1 + 1 + false + read-write + + + cr_vcocalsel_clk0 + xiopll_custom.cr_vcocalsel_clk0[5:0] + 2 + 6 + false + read-write + + + + iopll_reg_73 + 0x49 + 8 + + cr_freqcal_en + xiopll_custom.cr_freqcal_en + 0 + 1 + false + read-write + + + cr_freqcal_biasctl + xiopll_custom.xiopll_core.xchgpmplf_iopll.cr_freqcal_biasctl[2:0] + 1 + 3 + false + read-write + + + cr_clk_sel_override + xiopll_custom.xclkin_sw.xpm_pll_so.cr_clk_sel_override + 4 + 1 + false + read-write + + + cr_clk_sel_override_value + xiopll_custom.xclkin_sw.xpm_pll_so.cr_clk_sel_override_value + 5 + 1 + false + read-write + + + cr_freqcal_req_flag + xiopll_custom.cr_freqcal_req_flag + 6 + 1 + false + read-write + + + cr_vcocal_rstb + xiopll_custom.xiopll_core.xvco_cal.resetb + 7 + 1 + false + read-write + + + + + iopll_reg_74 + 0x4a + 8 + + cr_dprio_interface_sel + xdprio_dps_iopll.dprio_out_reg[599:592] + 0 + 8 + false + read-write + + + + iopll_status_0 + 0x4b + 8 + + counter_full + xdprio_dps_iopll.counter_full + 0 + 8 + false + read-only + + + + + iopll_status_1 + 0x4c + 8 + + refclk_cnt + xdprio_dps_iopll.refclk_counter[7:0] + 0 + 8 + false + read-only + + + + + + iopll_status_2 + 0x4d + 8 + + fbclk_cnt + xdprio_dps_iopll.fbclk_counter[7:0] + 0 + 8 + false + read-only + + + + + + + 8 + + + diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.sdc b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.sdc new file mode 100644 index 0000000000..725ce41370 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.sdc @@ -0,0 +1,179 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the timing constraints for the Altera PLL. +# * The helper routines are defined in io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl +# +# NOTE +# ---- +# Debug switch. Change to 1 to get more run-time debug information +set debug 0 + +set script_dir [file dirname [info script]] + +source "$script_dir/io_pll_altera_iopll_1931_oypl3jq_parameters.tcl" +source "$script_dir/io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl" + +#################### +# # +# GENERAL SETTINGS # +# # +#################### + +# This is a global setting and will apply to the whole design. +# This setting is required for the memory interface to be +# properly constrained. +derive_clock_uncertainty + + +# All timing requirements will be represented in nanoseconds with up to 3 decimal places of precision +set_time_format -unit ns -decimal_places 3 + +# Determine if entity names are on +set entity_names_on [ ai_are_entity_names_on ] + +if {[catch {load_package atoms + load_package sdc_ext + load_package design + catch {read_atom_netlist} read_atom_netlist_out + set read_atom_netlist_error [regexp "ERROR" $read_atom_netlist_out] + } err_loading_packages]} { + post_message -type error "Failed to load packages required by IOPLL SDC: $err_loading_packages" +} + +# This is the main call to the netlist traversal routines +# that will automatically find all pins and registers required +# to apply timing constraints. +# During the fitter, the routines will be called only once +# and cached data will be used in all subsequent calls. + + + +if {[info exists ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_ai_pll_db]} { + # Clean-up stale content + unset ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_ai_pll_db +} +if {[catch {ai_initialize_pll_db ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_ai_pll_db} err_initializing_db]} { + post_message -type warning "Failed to find atom information in IOPLL SDC: $err_initializing_db" +} + +# If multiple instances of this core are present in the +# design they will all be constrained through the +# following loop +set instances [ array names ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_ai_pll_db ] +foreach { inst } $instances { + if { [ info exists pins ] } { + # Clean-up stale content + unset pins + } + + # -------------------------------- # + # - - # + # --- Determine PLL Parameters --- # + # - - # + # -------------------------------- # + + set pll_atoms [get_atom_nodes -matching ${inst}* -type IOPLL] + set num_pll_inst [get_collection_size $pll_atoms] + + if {$num_pll_inst > 1} { + # Error condition + post_message -type error "SDC: More than one PLL atom found with instance name $inst" + } else { + # Use IP generated parameters + if { $debug } { + post_message -type info "SDC: using IP generated parameter values" + } + } + + # These dictionaries hold all the clock information. + lassign $::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_ai_pll_db($inst) base_clock_data_dict gen_clock_data_dict + + # ------------------------ # + # - - # + # ---REFERENCE CLOCK(s)--- # + # - - # + # ------------------------ # + dict for {clock_key info} $base_clock_data_dict { + dict with info { + if {$is_fpga_pin && !$exists} { + create_clock -period $period \ + -waveform [ list 0 $half_period] \ + -name $name $port_node_name + } + } + } + # ------------------------- # + # - - # + # --- OUTPUT PLL CLOCKS --- # + # - - # + # ------------------------- # + dict for {clock_key info} $gen_clock_data_dict { + dict with info { + if {[is_post_syn_sta]} { + if {$is_valid && !$exists} { + create_non_virtual_generated_clock_with_master_or_source \ + $master \ + $src \ + $name \ + $multiply_by \ + $divide_by \ + $phase \ + $duty_cycle \ + $pin_node_name + + if {[string match lvds* $clock_key] && [string match *loaden* $pattern] && [dict exists $gen_clock_data_dict $clock_key "through_pin" ] } { + set_max_delay_in_fit_or_false_path_in_sta_through_no_warn $through_pin $max_delay + } + } elseif {[is_m_n_cntr $pattern]} { + create_virtual_generated_clock_with_master_or_source \ + $master \ + $src \ + $name \ + $multiply_by \ + $divide_by \ + $phase \ + $duty_cycle + } + } else { + if {$is_valid && !$exists} { + create_generated_clock -add \ + -source $src \ + -name $name \ + -multiply_by $multiply_by \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cycle \ + $pin_node_name + + if {[string match lvds* $clock_key] && [string match *loaden* $pattern] && [dict exists $gen_clock_data_dict $clock_key "through_pin" ] } { + set_max_delay_in_fit_or_false_path_in_sta_through_no_warn $through_pin $max_delay + } + } + } + } + } + + foreach_in_collection node [get_nodes -no_duplicates -nowarn "${inst}|tennm_pll|dprio_rst_n"] { + set_false_path -through [get_node_info -name $node] + } +} diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.v b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.v new file mode 100644 index 0000000000..d4b24db1e2 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.v @@ -0,0 +1,450 @@ +// (C) 2001-2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// This is a testing TERP file. +// Wrappers for other families can be found in altera_pll.v (pre Arria 10) and twentynm_iopll.v + +`timescale 1ps/1ps +module io_pll_altera_iopll_1931_oypl3jq +( + // interface refclk + input wire refclk, + // interface locked + output wire locked, + // interface reset + input wire rst, + // interface outclk0 + output wire outclk_0, + // interface outclk1 + output wire outclk_1, + // interface outclk2 + output wire outclk_2, + // interface outclk3 + output wire outclk_3, + // interface outclk4 + output wire outclk_4 +); + +wire [1:0] extclk_out_wire; +wire refclk1; +assign refclk1 = 1'b0; +wire fbclk; +assign fbclk = 1'b0; +wire fboutclk; +wire zdbfbclk; +wire [1:0] loaden; +wire phase_done; +wire [29:0] reconfig_to_pll; +assign reconfig_to_pll = 30'b0; +wire scanclk; +assign scanclk = 1'b0; +wire [7:0] phout; +wire [2:0] num_phase_shifts; +assign num_phase_shifts = 3'b0; +wire permit_cal; +assign permit_cal = 1'b1; +wire fblvds_out; +assign fblvds_out = 1'b1; +wire [4:0] cntsel; +assign cntsel = 5'b0; +wire [1:0] clkbad; +wire [1:0] lvds_clk; +wire [8:0] outclk; +wire [2:0] unused_wires_high; + +wire [0:0] unused_wires_low; +assign unused_wires_low = outclk[0:0]; +assign unused_wires_high = outclk[8:6]; +assign outclk_0 = outclk[1]; +assign outclk_1 = outclk[2]; +assign outclk_2 = outclk[3]; +assign outclk_3 = outclk[4]; +assign outclk_4 = outclk[5]; +wire phase_en; +assign phase_en = 1'b0; +wire extswitch; +assign extswitch = 1'b0; +wire cascade_out; +wire dll_output; +assign dll_output = 1'b1; +wire activeclk; +wire adjpllin; +assign adjpllin = 1'b0; +wire updn; +assign updn = 1'b0; +wire [10:0] reconfig_from_pll; + +wire feedback_clk; +wire fb_clkin; +wire fb_out_clk; +wire fboutclk_wire; +wire locked_wire; +wire [10:0] reconfig_from_pll_wire; +wire gnd /* synthesis keep*/; + +// For use in dps pulse gen module. +wire final_updn; +wire final_phase_en; +wire [3:0] final_cntsel; +wire [2:0] final_num_ps; +assign reconfig_from_pll[10:0] = reconfig_from_pll_wire; + +wire adjpllin_wire = 1'b0; +wire dedicated_refclk_wire = 1'b0; + +//Calibration wires +wire cal_ok_wire; + +// Reset logic: + +//Synchronise the reset signal using Flip-Flop to avoid race condition HSD : https://hsdes.intel.com/appstore/article/#/14021123640 +// Uncomment the lines from 160 to 176 and comment lines 189 190 to workaround the race condition for FM87 +// +// +//reg cal_ok_wire_synced; +// +//always @ (posedge refclk or posedge rst) begin +// +// if (rst) begin +// cal_ok_wire_synced <= 1'b0; +// end else begin +// cal_ok_wire_synced <= cal_ok_wire; +// end +// +//end +// +//wire rst_n_wire = ~((rst & cal_ok_wire_synced) | (~permit_cal)); +//wire dprio_rst_n_wire = ~((~reconfig_to_pll[1] & cal_ok_wire_synced) | (~permit_cal)); + +// There are a few scenarios: +// - Upstream PLL : +// - reset is anded with cal_ok_wire so that a reset signal from the +// user can't interrupt calibration. +// - permit_cal tied off to 1 -> rst_n_wire = ~(rst & cal_ok_wire) +// - Downstream PLL: +// - connect upstream locked to downstream permit_cal +// - until upstream PLL is locked, keep reset high so that the PLL +// can't be calibrated. + +// To get the FM hot potato passing temporarily skip cal_ok and permit_cal + +// +//wire rst_n_wire = ~((rst & cal_ok_wire) | (~permit_cal)); +//Removing cal_ok_wire support since its causing race condition in Hardware, +//Cal_ok_wire should not have a self loop happening and also got confirmation +//from PFE that this gating logic is handled within the Hardware HSD: 14021123640 + +wire rst_n_wire = ~(rst | (~permit_cal)); +wire dprio_rst_n_wire = ~((~reconfig_to_pll[1] & cal_ok_wire) | (~permit_cal)); + + +//------------- Counter enable localparams ------------------------------- +localparam counter0_enable = "false"; +localparam counter1_enable = "true"; +localparam counter2_enable = "true"; +localparam counter3_enable = "true"; +localparam counter4_enable = "true"; +localparam counter5_enable = "true"; +localparam counter6_enable = "false"; +localparam counter7_enable = "false"; +localparam counter8_enable = "false"; +//------------- Counter enable localparams ------------------------------- + + +// ========================================================================================== +// Instantiate tennm_iopll! +// ========================================================================================== +tennm_iopll #( + .auto_clk_sw_en("false"), + .bw_mode("mid_bw"), + .c0_bypass_en("true"), + .c0_even_duty_en("false"), + .c0_high(256), + .c0_low(256), + .c0_out_en(counter0_enable), + .c0_ph_mux_prst(0), + .c0_prst(1), + .c1_bypass_en("false"), + .c1_even_duty_en("true"), + .c1_high(3), + .c1_low(2), + .c1_out_en(counter1_enable), + .c1_ph_mux_prst(0), + .c1_prst(1), + .c2_bypass_en("false"), + .c2_even_duty_en("false"), + .c2_high(4), + .c2_low(4), + .c2_out_en(counter2_enable), + .c2_ph_mux_prst(0), + .c2_prst(1), + .c3_bypass_en("false"), + .c3_even_duty_en("true"), + .c3_high(3), + .c3_low(2), + .c3_out_en(counter3_enable), + .c3_ph_mux_prst(0), + .c3_prst(1), + .c4_bypass_en("false"), + .c4_even_duty_en("false"), + .c4_high(4), + .c4_low(4), + .c4_out_en(counter4_enable), + .c4_ph_mux_prst(0), + .c4_prst(3), + .c5_bypass_en("false"), + .c5_even_duty_en("false"), + .c5_high(5), + .c5_low(5), + .c5_out_en(counter5_enable), + .c5_ph_mux_prst(0), + .c5_prst(1), + .c6_bypass_en("true"), + .c6_even_duty_en("false"), + .c6_high(256), + .c6_low(256), + .c6_out_en(counter6_enable), + .c6_ph_mux_prst(0), + .c6_prst(1), + .c7_bypass_en("true"), + .c7_even_duty_en("false"), + .c7_high(256), + .c7_low(256), + .c7_out_en(counter7_enable), + .c7_ph_mux_prst(0), + .c7_prst(1), + .c8_bypass_en("true"), + .c8_even_duty_en("false"), + .c8_high(256), + .c8_low(256), + .c8_out_en(counter8_enable), + .c8_ph_mux_prst(0), + .c8_prst(1), + .clkin_0_src("coreclkin"), + .clkin_1_src("ioclkin_0"), + .clock_name_0(""), + .clock_name_1("outclk0"), + .clock_name_2("outclk1"), + .clock_name_3("outclk2"), + .clock_name_4("outclk3"), + .clock_name_5("outclk4"), + .clock_name_6(""), + .clock_name_7(""), + .clock_name_8(""), + .clock_name_global_0("false"), + .clock_name_global_1("false"), + .clock_name_global_2("false"), + .clock_name_global_3("false"), + .clock_name_global_4("false"), + .clock_name_global_5("false"), + .clock_name_global_6("false"), + .clock_name_global_7("false"), + .clock_name_global_8("false"), + .clock_to_compensate(1), + .duty_cycle_0(50), + .duty_cycle_1(50), + .duty_cycle_2(50), + .duty_cycle_3(50), + .duty_cycle_4(50), + .duty_cycle_5(50), + .duty_cycle_6(50), + .duty_cycle_7(50), + .duty_cycle_8(50), + .extclk_0_cnt_src("pll_extclk_cnt_src_vss"), + .extclk_0_enable("true"), + .extclk_1_cnt_src("pll_extclk_cnt_src_vss"), + .extclk_1_enable("true"), + .feedback("direct"), + .iopll_type("TOP_BOTTOM"), + .m_counter_bypass_en("false"), + .m_counter_even_duty_en("false"), + .m_counter_high(5), + .m_counter_low(5), + .m_counter_scratch(1), + .manu_clk_sw_en("false"), + .merging_permitted("false"), + .n_counter_bypass_en("true"), + .n_counter_high(256), + .n_counter_low(256), + .n_counter_odd_div_duty_en("false"), + .outclk0("0 ps"), + .outclk1("200.0 MHz"), + .outclk2("125.0 MHz"), + .outclk3("200.0 MHz"), + .outclk4("125.0 MHz"), + .outclk5("100.0 MHz"), + .outclk6("0 ps"), + .outclk7("0 ps"), + .outclk8("0 ps"), + .pfd("100.0 MHz"), + .phase_shift_0("0 ps"), + .phase_shift_1("0 ps"), + .phase_shift_2("0 ps"), + .phase_shift_3("0 ps"), + .phase_shift_4("2000 ps"), + .phase_shift_5("0 ps"), + .phase_shift_6("0 ps"), + .phase_shift_7("0 ps"), + .phase_shift_8("0 ps"), + .prot_mode("BASIC"), + .refclk_src_mux("clk_0"), + .refclk_time("100.0 MHz"), + .self_reset_en("false"), + .simple_pll("false"), + .uc_channel_base_addr(16'h0), + .vco("1000.0 MHz") +) tennm_pll ( + .clken(2'b00), + .cnt_sel(4'b0), + .num_phase_shifts(3'b0), + .phase_en(1'b0), + .up_dn(1'b0), + .dprio_clk(1'b0), + .core_refclk(refclk), + .csr_clk(1'b1), + .csr_en(1'b1), + .csr_in(1'b1), + .dprio_rst_n(rst_n_wire), + .dprio_address(9'b0), + .read(1'b0), + .write(1'b0), + .writedata(8'b0), + .pll_select_top_avl(1'b1), // Hardcoded to use the top PLL for now. + .dps_rst_n(rst_n_wire), + .extswitch(extswitch), + .fbclk_in(1'b0), + .fblvds_in(1'b0), + .mdio_dis(1'b0), + .pfden(1'b1), + .pipeline_global_en_n(1'b0), + .pll_cascade_in(adjpllin_wire), + .pma_csr_test_dis(1'b1), + .refclk({2'b0,refclk1, dedicated_refclk_wire}), + .rst_n(rst_n_wire), + .scan_mode_n(1'b1), + .scan_shift_n(1'b1), + .uc_cal_addr(20'b0), + .uc_cal_clk(1'b0), + .uc_cal_read(1'b0), + .uc_cal_write(1'b0), + .uc_cal_writedata(8'b0), + .user_mode(1'b1), + .zdb_in(1'b0), + .block_select(), + .clk0_bad(clkbad[0]), + .clk1_bad(clkbad[1]), + .clksel(activeclk), + .csr_out(), + .dll_output(dll_output), + .extclk_dft(), + .extclk_output({extclk_out_wire[1], fboutclk_wire}), + .fbclk_out(feedback_clk), + .fblvds_out(fblvds_out), + .lf_reset(), + .loaden(loaden), + .lock(locked_wire), + .lvds_clk(lvds_clk), + .outclk(outclk), + .phase_done(phase_done), + .pll_cascade_out(cascade_out), + .pll_pd(), + .readdata(reconfig_from_pll_wire[7:0]), + .vcop_en(), + .vcoph(phout), + .cal_ok(cal_ok_wire) +); + +assign reconfig_from_pll_wire[8] = locked_wire; +assign reconfig_from_pll_wire[9] = phase_done; +assign reconfig_from_pll_wire[10] = cal_ok_wire; +assign extclk_out_wire[0] = fboutclk_wire; + +assign fboutclk = fboutclk_wire; +assign locked = locked_wire; + +// ================================================================================== +// Create clock buffers for fbclk, fboutclk and zdbfbclk if necessary. +// ================================================================================== +assign zdbfbclk = 0; + +endmodule + + +// ================================================================================= +// The final_phase_en signal should be a signal pulse (there was a silicon bug +// involving this problem on Arria 10. DPS pulse gen generates a singe final_phase_en +// pulse when the user_phase_en goes high. +// It also delays the other signal by one clock cycle +// ================================================================================= + +module dps_pulse_gen_io_pll_altera_iopll_1931_oypl3jq ( + input wire clk, // the DPS clock + input wire rst, // active high reset + input wire user_phase_en, // the user's phase_en signal + input wire user_updn, + input wire [2:0] user_num_ps, + input wire [3:0] user_cntsel, + output reg phase_en, // the phase_en signal for the IOPLL atom + output reg updn, + output reg [2:0] num_ps, + output reg [3:0] cntsel + ); + + //------------------------------------------------------------------------- + // States + localparam IDLE = 0, // Idle state: user_phase_en = 0, phase_en = 0 + PULSE = 1, // Activate state: phase_en = 1 + WAIT = 2; // Wait for user_phase_en to go low + + //------------------------------------------------------------------------- + // FSM current and next states + reg [1:0] state, next; + + // State update + always @(posedge clk) begin + + updn <= user_updn; + cntsel <= user_cntsel; + num_ps <= user_num_ps; + + if (rst) state <= IDLE; + else state <= next; + end + + //------------------------------------------------------------------------- + // Next-state and output logic + always @(*) begin + next = IDLE; // Default next state + phase_en = 1'b0; // Default output + + case (state) + IDLE : begin + if (user_phase_en) next = PULSE; + else next = IDLE; + end + + PULSE : begin + phase_en = 1'b1; + next = WAIT; + end + + WAIT : begin + if (~user_phase_en) next = IDLE; + else next = WAIT; + end + endcase + end + + endmodule + + diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_all_ip_params.tcl b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_all_ip_params.tcl new file mode 100644 index 0000000000..ce5b131105 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_all_ip_params.tcl @@ -0,0 +1,827 @@ +# PLL parameters + +#USER W A R N I N G ! +#USER The PLL parameters are statically defined in this +#USER file at generation time! + +set ::pll_corename io_pll_altera_iopll_1931_oypl3jq + +set ::pll_all_ip_params [dict create] + +dict set ::pll_all_ip_params gui_device_family "Agilex 7" +dict set ::pll_all_ip_params gui_device_component "AGFB014R24B2E2V" +dict set ::pll_all_ip_params gui_device_speed_grade "2" +dict set ::pll_all_ip_params gui_device_iobank_rev "IO96A_REVB2" +dict set ::pll_all_ip_params gui_debug_mode "false" +dict set ::pll_all_ip_params gui_skip_sdc_generation "false" +dict set ::pll_all_ip_params gui_include_iossm "false" +dict set ::pll_all_ip_params gui_cal_code_hex_file "iossm.hex" +dict set ::pll_all_ip_params gui_parameter_table_hex_file "seq_params_sim.hex" +dict set ::pll_all_ip_params gui_pll_tclk_mux_en "false" +dict set ::pll_all_ip_params gui_pll_tclk_sel "pll_tclk_m_src" +dict set ::pll_all_ip_params gui_pll_vco_freq_band_0 "pll_freq_clk0_band18" +dict set ::pll_all_ip_params gui_pll_vco_freq_band_1 "pll_freq_clk1_band18" +dict set ::pll_all_ip_params gui_pll_freqcal_en "true" +dict set ::pll_all_ip_params gui_pll_freqcal_req_flag "true" +dict set ::pll_all_ip_params gui_cal_converge "false" +dict set ::pll_all_ip_params gui_cal_error "cal_clean" +dict set ::pll_all_ip_params gui_pll_cal_done "false" +dict set ::pll_all_ip_params gui_pll_type "S10_Simple" +dict set ::pll_all_ip_params gui_pll_m_cnt_in_src "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src0 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src1 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src2 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src3 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src4 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src5 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src6 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src7 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params gui_c_cnt_in_src8 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params system_info_device_family "Agilex 7" +dict set ::pll_all_ip_params system_info_device_component "AGFB014R24B2E2V" +dict set ::pll_all_ip_params system_info_device_speed_grade "2" +dict set ::pll_all_ip_params system_part_trait_speed_grade "2" +dict set ::pll_all_ip_params system_part_trait_iobank_rev "IO96A_REVB2" +dict set ::pll_all_ip_params gui_usr_device_speed_grade "1" +dict set ::pll_all_ip_params gui_en_reconf "false" +dict set ::pll_all_ip_params gui_en_iossm_reconf "false" +dict set ::pll_all_ip_params gui_user_base_address "0" +dict set ::pll_all_ip_params gui_en_dps_ports "false" +dict set ::pll_all_ip_params gui_pll_mode "Integer-N PLL" +dict set ::pll_all_ip_params gui_location_type "I/O Bank" +dict set ::pll_all_ip_params gui_use_logical "false" +dict set ::pll_all_ip_params gui_reference_clock_frequency "100.0" +dict set ::pll_all_ip_params gui_reference_clock_frequency_ps "10000.0" +dict set ::pll_all_ip_params gui_use_coreclk "true" +dict set ::pll_all_ip_params gui_refclk_might_change "false" +dict set ::pll_all_ip_params gui_fractional_cout "32" +dict set ::pll_all_ip_params gui_prot_mode "UNUSED" +dict set ::pll_all_ip_params gui_dsm_out_sel "1st_order" +dict set ::pll_all_ip_params gui_use_locked "true" +dict set ::pll_all_ip_params gui_en_adv_params "false" +dict set ::pll_all_ip_params gui_pll_bandwidth_preset "Medium" +dict set ::pll_all_ip_params gui_lock_setting "Low Lock Time" +dict set ::pll_all_ip_params gui_pll_auto_reset "false" +dict set ::pll_all_ip_params gui_en_lvds_ports "Disabled" +dict set ::pll_all_ip_params gui_en_periphery_ports "false" +dict set ::pll_all_ip_params gui_operation_mode "direct" +dict set ::pll_all_ip_params gui_feedback_clock "Global Clock" +dict set ::pll_all_ip_params gui_clock_to_compensate "0" +dict set ::pll_all_ip_params gui_use_NDFB_modes "false" +dict set ::pll_all_ip_params gui_refclk_switch "false" +dict set ::pll_all_ip_params gui_refclk1_frequency "100.0" +dict set ::pll_all_ip_params gui_en_phout_ports "false" +dict set ::pll_all_ip_params gui_phout_division "1" +dict set ::pll_all_ip_params gui_en_extclkout_ports "false" +dict set ::pll_all_ip_params gui_number_of_clocks "5" +dict set ::pll_all_ip_params gui_multiply_factor "25" +dict set ::pll_all_ip_params gui_divide_factor_n "6" +dict set ::pll_all_ip_params gui_frac_multiply_factor "1" +dict set ::pll_all_ip_params gui_fix_vco_frequency "false" +dict set ::pll_all_ip_params gui_fixed_vco_frequency "600.0" +dict set ::pll_all_ip_params gui_fixed_vco_frequency_ps "1667.0" +dict set ::pll_all_ip_params gui_vco_frequency "1250.0" +dict set ::pll_all_ip_params gui_enable_output_counter_cascading "false" +dict set ::pll_all_ip_params gui_mif_gen_options "Generate New MIF File" +dict set ::pll_all_ip_params gui_new_mif_file_path "~/pll.mif" +dict set ::pll_all_ip_params gui_existing_mif_file_path "~/pll.mif" +dict set ::pll_all_ip_params gui_mif_config_name "unnamed" +dict set ::pll_all_ip_params gui_active_clk "false" +dict set ::pll_all_ip_params gui_clk_bad "false" +dict set ::pll_all_ip_params gui_switchover_mode "Automatic Switchover" +dict set ::pll_all_ip_params gui_switchover_delay "0" +dict set ::pll_all_ip_params gui_enable_cascade_out "false" +dict set ::pll_all_ip_params gui_cascade_outclk_index "0" +dict set ::pll_all_ip_params gui_enable_cascade_in "false" +dict set ::pll_all_ip_params gui_enable_permit_cal "false" +dict set ::pll_all_ip_params gui_enable_upstream_out_clk "false" +dict set ::pll_all_ip_params gui_pll_cascading_mode "adjpllin" +dict set ::pll_all_ip_params gui_enable_mif_dps "false" +dict set ::pll_all_ip_params gui_dps_cntr "C0" +dict set ::pll_all_ip_params gui_dps_num "1" +dict set ::pll_all_ip_params gui_dps_dir "Positive" +dict set ::pll_all_ip_params gui_extclkout_0_source "C0" +dict set ::pll_all_ip_params gui_extclkout_1_source "C0" +dict set ::pll_all_ip_params gui_extclkout_source "C0" +dict set ::pll_all_ip_params gui_clock_name_global "false" +dict set ::pll_all_ip_params gui_clock_name_string0 "outclk0" +dict set ::pll_all_ip_params gui_clock_name_string1 "outclk1" +dict set ::pll_all_ip_params gui_clock_name_string2 "outclk2" +dict set ::pll_all_ip_params gui_clock_name_string3 "outclk3" +dict set ::pll_all_ip_params gui_clock_name_string4 "outclk4" +dict set ::pll_all_ip_params gui_clock_name_string5 "outclk5" +dict set ::pll_all_ip_params gui_clock_name_string6 "outclk6" +dict set ::pll_all_ip_params gui_clock_name_string7 "outclk7" +dict set ::pll_all_ip_params gui_clock_name_string8 "outclk8" +dict set ::pll_all_ip_params gui_clock_name_string9 "outclk9" +dict set ::pll_all_ip_params gui_clock_name_string10 "outclk10" +dict set ::pll_all_ip_params gui_clock_name_string11 "outclk11" +dict set ::pll_all_ip_params gui_clock_name_string12 "outclk12" +dict set ::pll_all_ip_params gui_clock_name_string13 "outclk13" +dict set ::pll_all_ip_params gui_clock_name_string14 "outclk14" +dict set ::pll_all_ip_params gui_clock_name_string15 "outclk15" +dict set ::pll_all_ip_params gui_clock_name_string16 "outclk16" +dict set ::pll_all_ip_params gui_clock_name_string17 "outclk17" +dict set ::pll_all_ip_params gui_divide_factor_c0 "1" +dict set ::pll_all_ip_params gui_divide_factor_c1 "25" +dict set ::pll_all_ip_params gui_divide_factor_c2 "25" +dict set ::pll_all_ip_params gui_divide_factor_c3 "6" +dict set ::pll_all_ip_params gui_divide_factor_c4 "6" +dict set ::pll_all_ip_params gui_divide_factor_c5 "6" +dict set ::pll_all_ip_params gui_divide_factor_c6 "6" +dict set ::pll_all_ip_params gui_divide_factor_c7 "6" +dict set ::pll_all_ip_params gui_divide_factor_c8 "6" +dict set ::pll_all_ip_params gui_divide_factor_c9 "6" +dict set ::pll_all_ip_params gui_divide_factor_c10 "6" +dict set ::pll_all_ip_params gui_divide_factor_c11 "6" +dict set ::pll_all_ip_params gui_divide_factor_c12 "6" +dict set ::pll_all_ip_params gui_divide_factor_c13 "6" +dict set ::pll_all_ip_params gui_divide_factor_c14 "6" +dict set ::pll_all_ip_params gui_divide_factor_c15 "6" +dict set ::pll_all_ip_params gui_divide_factor_c16 "6" +dict set ::pll_all_ip_params gui_divide_factor_c17 "6" +dict set ::pll_all_ip_params gui_cascade_counter0 "false" +dict set ::pll_all_ip_params gui_cascade_counter1 "false" +dict set ::pll_all_ip_params gui_cascade_counter2 "false" +dict set ::pll_all_ip_params gui_cascade_counter3 "false" +dict set ::pll_all_ip_params gui_cascade_counter4 "false" +dict set ::pll_all_ip_params gui_cascade_counter5 "false" +dict set ::pll_all_ip_params gui_cascade_counter6 "false" +dict set ::pll_all_ip_params gui_cascade_counter7 "false" +dict set ::pll_all_ip_params gui_cascade_counter8 "false" +dict set ::pll_all_ip_params gui_cascade_counter9 "false" +dict set ::pll_all_ip_params gui_cascade_counter10 "false" +dict set ::pll_all_ip_params gui_cascade_counter11 "false" +dict set ::pll_all_ip_params gui_cascade_counter12 "false" +dict set ::pll_all_ip_params gui_cascade_counter13 "false" +dict set ::pll_all_ip_params gui_cascade_counter14 "false" +dict set ::pll_all_ip_params gui_cascade_counter15 "false" +dict set ::pll_all_ip_params gui_cascade_counter16 "false" +dict set ::pll_all_ip_params gui_cascade_counter17 "false" +dict set ::pll_all_ip_params gui_output_clock_frequency0 "200.0" +dict set ::pll_all_ip_params gui_output_clock_frequency1 "125.0" +dict set ::pll_all_ip_params gui_output_clock_frequency2 "200.0" +dict set ::pll_all_ip_params gui_output_clock_frequency3 "125.0" +dict set ::pll_all_ip_params gui_output_clock_frequency4 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency5 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency6 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency7 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency8 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency9 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency10 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency11 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency12 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency13 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency14 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency15 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency16 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency17 "100.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps0 "5000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps1 "8000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps2 "5000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps3 "8000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps4 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps5 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps6 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps7 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps8 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps9 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps10 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps11 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps12 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps13 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps14 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps15 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps16 "10000.0" +dict set ::pll_all_ip_params gui_output_clock_frequency_ps17 "10000.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency0 "200.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency1 "125.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency2 "200.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency3 "125.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency4 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency5 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency6 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency7 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency8 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency9 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency10 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency11 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency12 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency13 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency14 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency15 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency16 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency17 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range0 "198.333333 198.412698 198.571429 200.0 201.428571 201.587302" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range1 "114.285714 116.666667 120.0 125.0 127.272727 133.333333" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range2 "125.0 142.857143 166.666667 200.0 250.0 333.333333" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range3 "90.909091 100.0 111.111111 125.0 142.857143 166.666667" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range4 "76.923077 83.333333 90.909091 100.0 111.111111 125.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range5 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range6 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range7 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range8 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range9 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range10 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range11 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range12 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range13 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range14 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range15 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range16 "100.0" +dict set ::pll_all_ip_params gui_actual_output_clock_frequency_range17 "100.0" +dict set ::pll_all_ip_params gui_ps_units0 "ps" +dict set ::pll_all_ip_params gui_ps_units1 "ps" +dict set ::pll_all_ip_params gui_ps_units2 "ps" +dict set ::pll_all_ip_params gui_ps_units3 "degrees" +dict set ::pll_all_ip_params gui_ps_units4 "ps" +dict set ::pll_all_ip_params gui_ps_units5 "ps" +dict set ::pll_all_ip_params gui_ps_units6 "ps" +dict set ::pll_all_ip_params gui_ps_units7 "ps" +dict set ::pll_all_ip_params gui_ps_units8 "ps" +dict set ::pll_all_ip_params gui_ps_units9 "ps" +dict set ::pll_all_ip_params gui_ps_units10 "ps" +dict set ::pll_all_ip_params gui_ps_units11 "ps" +dict set ::pll_all_ip_params gui_ps_units12 "ps" +dict set ::pll_all_ip_params gui_ps_units13 "ps" +dict set ::pll_all_ip_params gui_ps_units14 "ps" +dict set ::pll_all_ip_params gui_ps_units15 "ps" +dict set ::pll_all_ip_params gui_ps_units16 "ps" +dict set ::pll_all_ip_params gui_ps_units17 "ps" +dict set ::pll_all_ip_params gui_phase_shift0 "0.0" +dict set ::pll_all_ip_params gui_phase_shift1 "0.0" +dict set ::pll_all_ip_params gui_phase_shift2 "0.0" +dict set ::pll_all_ip_params gui_phase_shift3 "0.0" +dict set ::pll_all_ip_params gui_phase_shift4 "0.0" +dict set ::pll_all_ip_params gui_phase_shift5 "0.0" +dict set ::pll_all_ip_params gui_phase_shift6 "0.0" +dict set ::pll_all_ip_params gui_phase_shift7 "0.0" +dict set ::pll_all_ip_params gui_phase_shift8 "0.0" +dict set ::pll_all_ip_params gui_phase_shift9 "0.0" +dict set ::pll_all_ip_params gui_phase_shift10 "0.0" +dict set ::pll_all_ip_params gui_phase_shift11 "0.0" +dict set ::pll_all_ip_params gui_phase_shift12 "0.0" +dict set ::pll_all_ip_params gui_phase_shift13 "0.0" +dict set ::pll_all_ip_params gui_phase_shift14 "0.0" +dict set ::pll_all_ip_params gui_phase_shift15 "0.0" +dict set ::pll_all_ip_params gui_phase_shift16 "0.0" +dict set ::pll_all_ip_params gui_phase_shift17 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg0 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg1 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg2 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg3 "90.0" +dict set ::pll_all_ip_params gui_phase_shift_deg4 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg5 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg6 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg7 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg8 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg9 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg10 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg11 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg12 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg13 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg14 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg15 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg16 "0.0" +dict set ::pll_all_ip_params gui_phase_shift_deg17 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift0 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift1 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift2 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift3 "2000.0" +dict set ::pll_all_ip_params gui_actual_phase_shift4 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift5 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift6 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift7 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift8 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift9 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift10 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift11 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift12 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift13 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift14 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift15 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift16 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift17 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range0 "0.0 125.0 250.0 375.0 500.0 625.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range1 "0.0 125.0 250.0 375.0 500.0 625.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range2 "0.0 125.0 250.0 375.0 500.0 625.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range3 "1625.0 1750.0 1875.0 2000.0 2125.0 2250.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range4 "0.0 125.0 250.0 375.0 500.0 625.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range5 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range6 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range7 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range8 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range9 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range10 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range11 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range12 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range13 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range14 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range15 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range16 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_range17 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg0 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg1 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg2 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg3 "90.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg4 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg5 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg6 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg7 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg8 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg9 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg10 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg11 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg12 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg13 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg14 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg15 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg16 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg17 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range0 "0.0 9.0 18.0 27.0 36.0 45.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range1 "0.0 5.6 11.2 16.9 22.5 28.1" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range2 "0.0 9.0 18.0 27.0 36.0 45.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range3 "73.1 78.8 84.4 90.0 95.6 101.2" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range4 "0.0 4.5 9.0 13.5 18.0 22.5" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range5 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range6 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range7 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range8 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range9 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range10 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range11 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range12 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range13 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range14 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range15 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range16 "0.0" +dict set ::pll_all_ip_params gui_actual_phase_shift_deg_range17 "0.0" +dict set ::pll_all_ip_params gui_duty_cycle0 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle1 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle2 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle3 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle4 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle5 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle6 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle7 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle8 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle9 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle10 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle11 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle12 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle13 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle14 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle15 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle16 "50.0" +dict set ::pll_all_ip_params gui_duty_cycle17 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle0 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle1 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle2 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle3 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle4 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle5 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle6 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle7 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle8 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle9 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle10 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle11 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle12 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle13 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle14 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle15 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle16 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle17 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range0 "20.0 30.0 40.0 50.0 60.0 70.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range1 "31.25 37.5 43.75 50.0 56.25 62.5" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range2 "20.0 30.0 40.0 50.0 60.0 70.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range3 "31.25 37.5 43.75 50.0 56.25 62.5" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range4 "35.0 40.0 45.0 50.0 55.0 60.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range5 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range6 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range7 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range8 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range9 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range10 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range11 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range12 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range13 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range14 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range15 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range16 "50.0" +dict set ::pll_all_ip_params gui_actual_duty_cycle_range17 "50.0" +dict set ::pll_all_ip_params gui_simulation_type "false" +dict set ::pll_all_ip_params parameterTable_names "{M-Counter Divide Setting} {N-Counter Divide Setting} {VCO Frequency} {C-Counter-0 Divide Setting} {C-Counter-1 Divide Setting} {C-Counter-2 Divide Setting} {C-Counter-3 Divide Setting} {C-Counter-4 Divide Setting} {C-Counter-5 Divide Setting} {C-Counter-6 Divide Setting} {C-Counter-7 Divide Setting} {C-Counter-8 Divide Setting} {PLL Auto Reset} {M-Counter Hi Divide} {M-Counter Lo Divide} {M-Counter Even Duty Enable} {M-Counter Bypass Enable} {N-Counter Hi Divide} {N-Counter Lo Divide} {N-Counter Even Duty Enable} {N-Counter Bypass Enable} {C-Counter-0 Hi Divide} {C-Counter-1 Hi Divide} {C-Counter-2 Hi Divide} {C-Counter-3 Hi Divide} {C-Counter-4 Hi Divide} {C-Counter-5 Hi Divide} {C-Counter-6 Hi Divide} {C-Counter-7 Hi Divide} {C-Counter-8 Hi Divide} {C-Counter-0 Lo Divide} {C-Counter-1 Lo Divide} {C-Counter-2 Lo Divide} {C-Counter-3 Lo Divide} {C-Counter-4 Lo Divide} {C-Counter-5 Lo Divide} {C-Counter-6 Lo Divide} {C-Counter-7 Lo Divide} {C-Counter-8 Lo Divide} {C-Counter-0 Even Duty Enable} {C-Counter-1 Even Duty Enable} {C-Counter-2 Even Duty Enable} {C-Counter-3 Even Duty Enable} {C-Counter-4 Even Duty Enable} {C-Counter-5 Even Duty Enable} {C-Counter-6 Even Duty Enable} {C-Counter-7 Even Duty Enable} {C-Counter-8 Even Duty Enable} {C-Counter-0 Bypass Enable} {C-Counter-1 Bypass Enable} {C-Counter-2 Bypass Enable} {C-Counter-3 Bypass Enable} {C-Counter-4 Bypass Enable} {C-Counter-5 Bypass Enable} {C-Counter-6 Bypass Enable} {C-Counter-7 Bypass Enable} {C-Counter-8 Bypass Enable} {C-Counter-0 Preset} {C-Counter-1 Preset} {C-Counter-2 Preset} {C-Counter-3 Preset} {C-Counter-4 Preset} {C-Counter-5 Preset} {C-Counter-6 Preset} {C-Counter-7 Preset} {C-Counter-8 Preset} {C-Counter-0 Phase Mux Preset} {C-Counter-1 Phase Mux Preset} {C-Counter-2 Phase Mux Preset} {C-Counter-3 Phase Mux Preset} {C-Counter-4 Phase Mux Preset} {C-Counter-5 Phase Mux Preset} {C-Counter-6 Phase Mux Preset} {C-Counter-7 Phase Mux Preset} {C-Counter-8 Phase Mux Preset} {Charge Pump Current} {Bandwidth Control}" +dict set ::pll_all_ip_params parameterTable_values "10 1 {1000.0 MHz} 1 5 8 5 8 10 1 1 1 false 5 5 false false 256 256 false true 256 3 4 3 4 5 256 256 256 256 2 4 2 4 5 256 256 256 false true false true false false false false false true false false false false false true true true 1 1 1 1 3 1 1 1 1 0 0 0 0 0 0 0 0 0 pll_cp_setting5 pll_bw_res_setting3" +dict set ::pll_all_ip_params mifTable_names "{The MIF file specified does not yet exist}" +dict set ::pll_all_ip_params pll_m_cnt_basic "1" +dict set ::pll_all_ip_params pll_m_cnt "1" +dict set ::pll_all_ip_params prot_mode "BASIC" +dict set ::pll_all_ip_params protocol_mode "PROTOCOL_MODE_BASIC" +dict set ::pll_all_ip_params m_cnt_hi_div "5" +dict set ::pll_all_ip_params eff_m_cnt "1" +dict set ::pll_all_ip_params multiply_factor "10" +dict set ::pll_all_ip_params use_core_refclk "true" +dict set ::pll_all_ip_params m_cnt_lo_div "5" +dict set ::pll_all_ip_params n_cnt_hi_div "256" +dict set ::pll_all_ip_params n_cnt_lo_div "256" +dict set ::pll_all_ip_params m_cnt_bypass_en "false" +dict set ::pll_all_ip_params n_cnt_bypass_en "true" +dict set ::pll_all_ip_params m_cnt_odd_div_duty_en "false" +dict set ::pll_all_ip_params n_cnt_odd_div_duty_en "false" +dict set ::pll_all_ip_params pll_vco_div "1" +dict set ::pll_all_ip_params pll_cp_current "pll_cp_setting5" +dict set ::pll_all_ip_params pll_bwctrl "pll_bw_res_setting3" +dict set ::pll_all_ip_params pll_ripplecap_ctrl "pll_ripplecap_setting1" +dict set ::pll_all_ip_params pll_fractional_division "1" +dict set ::pll_all_ip_params fractional_vco_multiplier "false" +dict set ::pll_all_ip_params reference_clock_frequency "100.0 MHz" +dict set ::pll_all_ip_params pll_fractional_cout "1" +dict set ::pll_all_ip_params pll_dsm_out_sel "1st_order" +dict set ::pll_all_ip_params operation_mode "direct" +dict set ::pll_all_ip_params number_of_clocks "5" +dict set ::pll_all_ip_params number_of_outclks "5" +dict set ::pll_all_ip_params pll_vcoph_div "1" +dict set ::pll_all_ip_params pll_type "TOP_BOTTOM" +dict set ::pll_all_ip_params pll_subtype "General" +dict set ::pll_all_ip_params pll_output_clk_frequency "1000.0 MHz" +dict set ::pll_all_ip_params pll_pfd_frequency "100.0 MHz" +dict set ::pll_all_ip_params mimic_fbclk_type "gclk" +dict set ::pll_all_ip_params pll_bw_sel "mid_bw" +dict set ::pll_all_ip_params pll_slf_rst "false" +dict set ::pll_all_ip_params pll_fbclk_mux_1 "pll_fbclk_mux_1_glb" +dict set ::pll_all_ip_params pll_fbclk_mux_2 "pll_fbclk_mux_2_m_cnt" +dict set ::pll_all_ip_params pll_m_cnt_in_src "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params pll_clkin_0_src "coreclkin" +dict set ::pll_all_ip_params refclk1_frequency "0 MHz" +dict set ::pll_all_ip_params pll_clk_loss_sw_en "false" +dict set ::pll_all_ip_params pll_manu_clk_sw_en "false" +dict set ::pll_all_ip_params pll_auto_clk_sw_en "false" +dict set ::pll_all_ip_params pll_clkin_1_src "ioclkin_0" +dict set ::pll_all_ip_params pll_clk_sw_dly "0" +dict set ::pll_all_ip_params pll_extclk_0_cnt_src "pll_extclk_cnt_src_vss" +dict set ::pll_all_ip_params pll_extclk_1_cnt_src "pll_extclk_cnt_src_vss" +dict set ::pll_all_ip_params pll_lock_fltr_cfg "100" +dict set ::pll_all_ip_params pll_unlock_fltr_cfg "2" +dict set ::pll_all_ip_params lock_mode "low_lock_time" +dict set ::pll_all_ip_params clock_to_compensate "1" +dict set ::pll_all_ip_params clock_name_global "false" +dict set ::pll_all_ip_params pll_freqcal_en "true" +dict set ::pll_all_ip_params pll_defer_cal_user_mode "true" +dict set ::pll_all_ip_params dprio_interface_sel "3" +dict set ::pll_all_ip_params merging_permitted "false" +dict set ::pll_all_ip_params bandwidth_mode "BANDWIDTH_MODE_AUTO" +dict set ::pll_all_ip_params compensation_clk_source "COMPENSATION_CLK_SOURCE_UNUSED" +dict set ::pll_all_ip_params compensation_mode "COMPENSATION_MODE_DIRECT" +dict set ::pll_all_ip_params cascade_mode "CASCADE_MODE_STANDALONE" +dict set ::pll_all_ip_params fb_clk_delay "0" +dict set ::pll_all_ip_params fb_clk_fractional_div_den "1" +dict set ::pll_all_ip_params fb_clk_fractional_div_num "1" +dict set ::pll_all_ip_params fb_clk_fractional_div_value "1" +dict set ::pll_all_ip_params fb_clk_m_div "0" +dict set ::pll_all_ip_params out_clk_cascading_source "OUT_CLK_CASCADING_SOURCE_UNUSED" +dict set ::pll_all_ip_params out_clk_external_0_source "OUT_CLK_EXTERNAL_0_SOURCE_UNUSED" +dict set ::pll_all_ip_params out_clk_external_1_source "OUT_CLK_EXTERNAL_1_SOURCE_UNUSED" +dict set ::pll_all_ip_params out_clk_periph_0_delay "0" +dict set ::pll_all_ip_params out_clk_periph_0_en "true" +dict set ::pll_all_ip_params out_clk_periph_1_delay "0" +dict set ::pll_all_ip_params out_clk_periph_1_en "true" +dict set ::pll_all_ip_params ref_clk_delay "0" +dict set ::pll_all_ip_params ref_clk_n_div "1" +dict set ::pll_all_ip_params set_dutycycle "SET_DUTYCYCLE_FRACTION" +dict set ::pll_all_ip_params set_fractional "SET_FRACTIONAL_FRACTION" +dict set ::pll_all_ip_params set_freq "SET_FREQ_DIVISION" +dict set ::pll_all_ip_params set_phase "SET_PHASE_NUM_SHIFTS" +dict set ::pll_all_ip_params pfd_clk_freq "100000000" +dict set ::pll_all_ip_params vco_clk_freq "1000000000" +dict set ::pll_all_ip_params c_cnt_hi_div0 "256" +dict set ::pll_all_ip_params c_cnt_hi_div1 "3" +dict set ::pll_all_ip_params c_cnt_hi_div2 "4" +dict set ::pll_all_ip_params c_cnt_hi_div3 "3" +dict set ::pll_all_ip_params c_cnt_hi_div4 "4" +dict set ::pll_all_ip_params c_cnt_hi_div5 "5" +dict set ::pll_all_ip_params c_cnt_hi_div6 "256" +dict set ::pll_all_ip_params c_cnt_hi_div7 "256" +dict set ::pll_all_ip_params c_cnt_hi_div8 "256" +dict set ::pll_all_ip_params c_cnt_hi_div9 "256" +dict set ::pll_all_ip_params c_cnt_hi_div10 "1" +dict set ::pll_all_ip_params c_cnt_hi_div11 "1" +dict set ::pll_all_ip_params c_cnt_hi_div12 "1" +dict set ::pll_all_ip_params c_cnt_hi_div13 "1" +dict set ::pll_all_ip_params c_cnt_hi_div14 "1" +dict set ::pll_all_ip_params c_cnt_hi_div15 "1" +dict set ::pll_all_ip_params c_cnt_hi_div16 "1" +dict set ::pll_all_ip_params c_cnt_hi_div17 "1" +dict set ::pll_all_ip_params c_cnt_lo_div0 "256" +dict set ::pll_all_ip_params c_cnt_lo_div1 "2" +dict set ::pll_all_ip_params c_cnt_lo_div2 "4" +dict set ::pll_all_ip_params c_cnt_lo_div3 "2" +dict set ::pll_all_ip_params c_cnt_lo_div4 "4" +dict set ::pll_all_ip_params c_cnt_lo_div5 "5" +dict set ::pll_all_ip_params c_cnt_lo_div6 "256" +dict set ::pll_all_ip_params c_cnt_lo_div7 "256" +dict set ::pll_all_ip_params c_cnt_lo_div8 "256" +dict set ::pll_all_ip_params c_cnt_lo_div9 "256" +dict set ::pll_all_ip_params c_cnt_lo_div10 "1" +dict set ::pll_all_ip_params c_cnt_lo_div11 "1" +dict set ::pll_all_ip_params c_cnt_lo_div12 "1" +dict set ::pll_all_ip_params c_cnt_lo_div13 "1" +dict set ::pll_all_ip_params c_cnt_lo_div14 "1" +dict set ::pll_all_ip_params c_cnt_lo_div15 "1" +dict set ::pll_all_ip_params c_cnt_lo_div16 "1" +dict set ::pll_all_ip_params c_cnt_lo_div17 "1" +dict set ::pll_all_ip_params c_cnt_prst0 "1" +dict set ::pll_all_ip_params c_cnt_prst1 "1" +dict set ::pll_all_ip_params c_cnt_prst2 "1" +dict set ::pll_all_ip_params c_cnt_prst3 "1" +dict set ::pll_all_ip_params c_cnt_prst4 "3" +dict set ::pll_all_ip_params c_cnt_prst5 "1" +dict set ::pll_all_ip_params c_cnt_prst6 "1" +dict set ::pll_all_ip_params c_cnt_prst7 "1" +dict set ::pll_all_ip_params c_cnt_prst8 "1" +dict set ::pll_all_ip_params c_cnt_prst9 "1" +dict set ::pll_all_ip_params c_cnt_prst10 "1" +dict set ::pll_all_ip_params c_cnt_prst11 "1" +dict set ::pll_all_ip_params c_cnt_prst12 "1" +dict set ::pll_all_ip_params c_cnt_prst13 "1" +dict set ::pll_all_ip_params c_cnt_prst14 "1" +dict set ::pll_all_ip_params c_cnt_prst15 "1" +dict set ::pll_all_ip_params c_cnt_prst16 "1" +dict set ::pll_all_ip_params c_cnt_prst17 "1" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst0 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst1 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst2 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst3 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst4 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst5 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst6 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst7 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst8 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst9 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst10 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst11 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst12 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst13 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst14 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst15 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst16 "0" +dict set ::pll_all_ip_params c_cnt_ph_mux_prst17 "0" +dict set ::pll_all_ip_params c_cnt_in_src0 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src1 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src2 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src3 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src4 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src5 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src6 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src7 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src8 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src9 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src10 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src11 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src12 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src13 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src14 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src15 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src16 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_in_src17 "c_m_cnt_in_src_ph_mux_clk" +dict set ::pll_all_ip_params c_cnt_bypass_en0 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en1 "false" +dict set ::pll_all_ip_params c_cnt_bypass_en2 "false" +dict set ::pll_all_ip_params c_cnt_bypass_en3 "false" +dict set ::pll_all_ip_params c_cnt_bypass_en4 "false" +dict set ::pll_all_ip_params c_cnt_bypass_en5 "false" +dict set ::pll_all_ip_params c_cnt_bypass_en6 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en7 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en8 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en9 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en10 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en11 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en12 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en13 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en14 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en15 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en16 "true" +dict set ::pll_all_ip_params c_cnt_bypass_en17 "true" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en0 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en1 "true" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en2 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en3 "true" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en4 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en5 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en6 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en7 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en8 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en9 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en10 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en11 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en12 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en13 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en14 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en15 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en16 "false" +dict set ::pll_all_ip_params c_cnt_odd_div_duty_en17 "false" +dict set ::pll_all_ip_params output_clock_frequency0 "0 ps" +dict set ::pll_all_ip_params output_clock_frequency1 "200.0 MHz" +dict set ::pll_all_ip_params output_clock_frequency2 "125.0 MHz" +dict set ::pll_all_ip_params output_clock_frequency3 "200.0 MHz" +dict set ::pll_all_ip_params output_clock_frequency4 "125.0 MHz" +dict set ::pll_all_ip_params output_clock_frequency5 "100.0 MHz" +dict set ::pll_all_ip_params output_clock_frequency6 "0 ps" +dict set ::pll_all_ip_params output_clock_frequency7 "0 ps" +dict set ::pll_all_ip_params output_clock_frequency8 "0 ps" +dict set ::pll_all_ip_params output_clock_frequency9 "0 ps" +dict set ::pll_all_ip_params output_clock_frequency10 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency11 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency12 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency13 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency14 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency15 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency16 "0 MHz" +dict set ::pll_all_ip_params output_clock_frequency17 "0 MHz" +dict set ::pll_all_ip_params phase_shift0 "0 ps" +dict set ::pll_all_ip_params phase_shift1 "0 ps" +dict set ::pll_all_ip_params phase_shift2 "0 ps" +dict set ::pll_all_ip_params phase_shift3 "0 ps" +dict set ::pll_all_ip_params phase_shift4 "2000 ps" +dict set ::pll_all_ip_params phase_shift5 "0 ps" +dict set ::pll_all_ip_params phase_shift6 "0 ps" +dict set ::pll_all_ip_params phase_shift7 "0 ps" +dict set ::pll_all_ip_params phase_shift8 "0 ps" +dict set ::pll_all_ip_params phase_shift9 "0 ps" +dict set ::pll_all_ip_params phase_shift10 "0 ps" +dict set ::pll_all_ip_params phase_shift11 "0 ps" +dict set ::pll_all_ip_params phase_shift12 "0 ps" +dict set ::pll_all_ip_params phase_shift13 "0 ps" +dict set ::pll_all_ip_params phase_shift14 "0 ps" +dict set ::pll_all_ip_params phase_shift15 "0 ps" +dict set ::pll_all_ip_params phase_shift16 "0 ps" +dict set ::pll_all_ip_params phase_shift17 "0 ps" +dict set ::pll_all_ip_params duty_cycle0 "50" +dict set ::pll_all_ip_params duty_cycle1 "50" +dict set ::pll_all_ip_params duty_cycle2 "50" +dict set ::pll_all_ip_params duty_cycle3 "50" +dict set ::pll_all_ip_params duty_cycle4 "50" +dict set ::pll_all_ip_params duty_cycle5 "50" +dict set ::pll_all_ip_params duty_cycle6 "50" +dict set ::pll_all_ip_params duty_cycle7 "50" +dict set ::pll_all_ip_params duty_cycle8 "50" +dict set ::pll_all_ip_params duty_cycle9 "50" +dict set ::pll_all_ip_params duty_cycle10 "50" +dict set ::pll_all_ip_params duty_cycle11 "50" +dict set ::pll_all_ip_params duty_cycle12 "50" +dict set ::pll_all_ip_params duty_cycle13 "50" +dict set ::pll_all_ip_params duty_cycle14 "50" +dict set ::pll_all_ip_params duty_cycle15 "50" +dict set ::pll_all_ip_params duty_cycle16 "50" +dict set ::pll_all_ip_params duty_cycle17 "50" +dict set ::pll_all_ip_params clock_name_1 "outclk0" +dict set ::pll_all_ip_params clock_name_2 "outclk1" +dict set ::pll_all_ip_params clock_name_3 "outclk2" +dict set ::pll_all_ip_params clock_name_4 "outclk3" +dict set ::pll_all_ip_params clock_name_5 "outclk4" +dict set ::pll_all_ip_params clock_name_global_0 "false" +dict set ::pll_all_ip_params clock_name_global_1 "false" +dict set ::pll_all_ip_params clock_name_global_2 "false" +dict set ::pll_all_ip_params clock_name_global_3 "false" +dict set ::pll_all_ip_params clock_name_global_4 "false" +dict set ::pll_all_ip_params clock_name_global_5 "false" +dict set ::pll_all_ip_params clock_name_global_6 "false" +dict set ::pll_all_ip_params clock_name_global_7 "false" +dict set ::pll_all_ip_params clock_name_global_8 "false" +dict set ::pll_all_ip_params divide_factor0 "1" +dict set ::pll_all_ip_params divide_factor1 "1" +dict set ::pll_all_ip_params divide_factor2 "1" +dict set ::pll_all_ip_params divide_factor3 "1" +dict set ::pll_all_ip_params divide_factor4 "1" +dict set ::pll_all_ip_params divide_factor5 "1" +dict set ::pll_all_ip_params divide_factor6 "1" +dict set ::pll_all_ip_params divide_factor7 "1" +dict set ::pll_all_ip_params divide_factor8 "1" +dict set ::pll_all_ip_params out_clk_0_c_div "1" +dict set ::pll_all_ip_params out_clk_1_c_div "1" +dict set ::pll_all_ip_params out_clk_2_c_div "1" +dict set ::pll_all_ip_params out_clk_3_c_div "1" +dict set ::pll_all_ip_params out_clk_4_c_div "1" +dict set ::pll_all_ip_params out_clk_5_c_div "1" +dict set ::pll_all_ip_params out_clk_6_c_div "1" +dict set ::pll_all_ip_params out_clk_0_core_en "true" +dict set ::pll_all_ip_params out_clk_1_core_en "true" +dict set ::pll_all_ip_params out_clk_2_core_en "true" +dict set ::pll_all_ip_params out_clk_3_core_en "true" +dict set ::pll_all_ip_params out_clk_4_core_en "true" +dict set ::pll_all_ip_params out_clk_5_core_en "true" +dict set ::pll_all_ip_params out_clk_6_core_en "true" +dict set ::pll_all_ip_params out_clk_0_delay "0" +dict set ::pll_all_ip_params out_clk_1_delay "0" +dict set ::pll_all_ip_params out_clk_2_delay "0" +dict set ::pll_all_ip_params out_clk_3_delay "0" +dict set ::pll_all_ip_params out_clk_4_delay "0" +dict set ::pll_all_ip_params out_clk_5_delay "0" +dict set ::pll_all_ip_params out_clk_6_delay "0" +dict set ::pll_all_ip_params out_clk_0_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_1_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_2_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_3_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_4_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_5_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_6_dutycycle_den "2" +dict set ::pll_all_ip_params out_clk_0_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_1_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_2_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_3_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_4_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_5_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_6_dutycycle_num "1" +dict set ::pll_all_ip_params out_clk_0_phase_shifts "0" +dict set ::pll_all_ip_params out_clk_1_phase_shifts "0" +dict set ::pll_all_ip_params out_clk_2_phase_shifts "0" +dict set ::pll_all_ip_params out_clk_3_phase_shifts "0" +dict set ::pll_all_ip_params out_clk_4_phase_shifts "0" +dict set ::pll_all_ip_params out_clk_5_phase_shifts "0" +dict set ::pll_all_ip_params out_clk_6_phase_shifts "0" +dict set ::pll_all_ip_params ref_clk_0_freq "100000000" +dict set ::pll_all_ip_params ref_clk_1_freq "100000000" +dict set ::pll_all_ip_params out_clk_0_freq "1000000000" +dict set ::pll_all_ip_params out_clk_1_freq "1000000000" +dict set ::pll_all_ip_params out_clk_2_freq "1000000000" +dict set ::pll_all_ip_params out_clk_3_freq "1000000000" +dict set ::pll_all_ip_params out_clk_4_freq "1000000000" +dict set ::pll_all_ip_params out_clk_5_freq "1000000000" +dict set ::pll_all_ip_params out_clk_6_freq "1000000000" +dict set ::pll_all_ip_params out_clk_0_phase_ps "1000000000" +dict set ::pll_all_ip_params out_clk_1_phase_ps "1000000000" +dict set ::pll_all_ip_params out_clk_2_phase_ps "1000000000" +dict set ::pll_all_ip_params out_clk_3_phase_ps "1000000000" +dict set ::pll_all_ip_params out_clk_4_phase_ps "1000000000" +dict set ::pll_all_ip_params out_clk_5_phase_ps "1000000000" +dict set ::pll_all_ip_params out_clk_6_phase_ps "1000000000" +dict set ::pll_all_ip_params pll_tclk_mux_en "false" +dict set ::pll_all_ip_params pll_tclk_sel "pll_tclk_m_src" +dict set ::pll_all_ip_params pll_vco_freq_band_0 "pll_freq_clk0_band18" +dict set ::pll_all_ip_params pll_vco_freq_band_1 "pll_freq_clk1_band18" +dict set ::pll_all_ip_params pll_freqcal_req_flag "true" +dict set ::pll_all_ip_params cal_converge "false" +dict set ::pll_all_ip_params cal_error "cal_clean" +dict set ::pll_all_ip_params pll_cal_done "false" +dict set ::pll_all_ip_params include_iossm "false" +dict set ::pll_all_ip_params cal_code_hex_file "iossm.hex" +dict set ::pll_all_ip_params parameter_table_hex_file "seq_params_sim.hex" +dict set ::pll_all_ip_params iossm_nios_sim_clk_period_ps "1333" +dict set ::pll_all_ip_params hp_number_of_family_allowable_clocks "9" +dict set ::pll_all_ip_params hp_previous_num_clocks "1" +dict set ::pll_all_ip_params hp_actual_vco_frequency_fp "600.0" +dict set ::pll_all_ip_params hp_qsys_scripting_mode "false" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp0 "200.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp1 "125.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp2 "200.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp3 "125.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp4 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp5 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp6 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp7 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp8 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp9 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp10 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp11 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp12 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp13 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp14 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp15 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp16 "100.0" +dict set ::pll_all_ip_params hp_actual_output_clock_frequency_fp17 "100.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp0 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp1 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp2 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp3 "2000.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp4 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp5 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp6 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp7 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp8 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp9 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp10 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp11 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp12 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp13 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp14 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp15 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp16 "0.0" +dict set ::pll_all_ip_params hp_actual_phase_shift_fp17 "0.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp0 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp1 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp2 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp3 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp4 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp5 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp6 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp7 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp8 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp9 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp10 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp11 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp12 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp13 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp14 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp15 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp16 "50.0" +dict set ::pll_all_ip_params hp_actual_duty_cycle_fp17 "50.0" diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_parameters.tcl b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_parameters.tcl new file mode 100644 index 0000000000..4ad7f4eaab --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_parameters.tcl @@ -0,0 +1,121 @@ +# PLL Parameters + +#USER W A R N I N G ! +#USER The PLL parameters are statically defined in this +#USER file at generation time! +#USER To ensure timing constraints and timing reports are correct, when you make +#USER any changes to the PLL component using the Qsys, +#USER apply those changes to the PLL parameters in this file + +set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename io_pll_altera_iopll_1931_oypl3jq + +set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data [dict create] +set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data [dict create] +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk pattern __inst_name__|tennm_pll|core_refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk node_type pin +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk port_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk port_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk is_fpga_pin false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk is_main_refclk true +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk name "__inst_name___refclk" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk period 10.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data refclk half_period 5.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock pattern __inst_name__|tennm_pll~ncntr_reg +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock node_type register +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock name "__inst_name___n_cnt_clk" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock multiply_by 1 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock divide_by 1 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock phase 0.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data n_cnt_clock duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock pattern __inst_name__|tennm_pll~mcntr_reg +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock node_type register +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock name "__inst_name___m_cnt_clk" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock multiply_by 1 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock divide_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock phase 0.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data m_cnt_clock duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 pattern __inst_name__|tennm_pll|outclk\[1\] +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 node_type pin +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 name __inst_name___outclk0 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 multiply_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 divide_by 5 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 phase 0.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk1 counter_index 1 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 pattern __inst_name__|tennm_pll|outclk\[2\] +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 node_type pin +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 name __inst_name___outclk1 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 multiply_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 divide_by 8 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 phase 0.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk2 counter_index 2 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 pattern __inst_name__|tennm_pll|outclk\[3\] +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 node_type pin +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 name __inst_name___outclk2 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 multiply_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 divide_by 5 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 phase 0.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk3 counter_index 3 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 pattern __inst_name__|tennm_pll|outclk\[4\] +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 node_type pin +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 name __inst_name___outclk3 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 multiply_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 divide_by 8 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 phase 90.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk4 counter_index 4 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 pattern __inst_name__|tennm_pll|outclk\[5\] +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 node_type pin +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 pin_id "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 pin_node_name "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 is_valid false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 exists false +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 name __inst_name___outclk4 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 src refclk +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 master "" +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 multiply_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 divide_by 10 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 phase 0.000 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 duty_cycle 50 +dict set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data outclk5 counter_index 5 diff --git a/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl new file mode 100644 index 0000000000..b2fc9d5a97 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl @@ -0,0 +1,1096 @@ +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +##################################################################### +# +# THIS IS AN AUTO-GENERATED FILE! +# ------------------------------- +# If you modify this files, all your changes will be lost if you +# regenerate the core! +# +# FILE DESCRIPTION +# ---------------- +# This file contains the traversal routines that are used by +# io_pll_altera_iopll_1931_oypl3jq.sdc scripts. +# +# These routines are only meant to support the SDC. +# Trying to using them in a different context can have unexpected +# results. + +set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_debug 0 + +set script_dir [file dirname [info script]] + +source [file join $script_dir io_pll_altera_iopll_1931_oypl3jq_parameters.tcl] + +proc get_warnings_disabled {} { + set local_disable_warnings true + set inis [split [get_global_assignment -name INI_VARS] ";"] + foreach ini $inis { + set ini_lst [split $ini "="] + lassign $ini_lst ini_name ini_value + if {$ini_name == "disable_warnings" && $ini_value == "off"} { + set local_disable_warnings false + break + } + } + return $local_disable_warnings +} +set ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_disable_warnings [get_warnings_disabled] + +# ---------------------------------------------------------------- +# +proc ai_post_message {msg_type msg {msg_context sta_only}} { +# +# Description: Posts a message to Quartus, depending on +# msg_context (sta_only, all) +# +# +# +# ---------------------------------------------------------------- + + if {$msg_type == "debug"} { + if {$::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_debug} { + puts $msg + } + } else { + if {$msg_context == "all"} { + post_message -type $msg_type $msg + } elseif {$msg_context == "sta_only"} { + if {$::TimeQuestInfo(nameofexecutable) == "quartus_sta"} { + post_message -type $msg_type $msg + } + } + } +} + +# ---------------------------------------------------------------- +# +proc ai_are_entity_names_on { } { +# +# Description: Determines if the entity names option is on +# +# ---------------------------------------------------------------- + return [set_project_mode -is_show_entity] +} + +# ---------------------------------------------------------------- +# +proc ai_initialize_pll_db { pll_db_par } { +# +# Description: Gets the instances of this particular PLL IP and creates the pin +# cache +# +# ---------------------------------------------------------------- + upvar $pll_db_par local_pll_db + + global ::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename + + ai_post_message info "Initializing PLL database for CORE $::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename" + set instance_list [ai_get_core_instance_list $::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename] + + foreach instname $instance_list { + ai_post_message info "Finding port-to-pin mapping for CORE: $::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename INSTANCE: $instname" + + set clock_data_dicts [ai_get_pll_pins $instname] + lassign $clock_data_dicts base_clock_data_dict gen_clock_data_dict + print_clock_data $base_clock_data_dict + print_clock_data $gen_clock_data_dict + + set local_pll_db($instname) $clock_data_dicts + } +} + +# ---------------------------------------------------------------- +# +proc ai_get_core_instance_list {corename} { +# +# Description: Converts node names from one style to another style +# +# ---------------------------------------------------------------- + set full_instance_list [ai_get_core_full_instance_list $corename] + set instance_list [list] + + foreach inst $full_instance_list { + if {[lsearch $instance_list [escape_brackets $inst]] == -1} { + ai_post_message debug "Found instance: $inst" + lappend instance_list $inst + } + } + return $instance_list +} + +# ---------------------------------------------------------------- +# +proc ai_get_core_full_instance_list {corename} { +# +# Description: Finds the instances of the particular IP by searching through the cells +# +# ---------------------------------------------------------------- + + set instance_list [design::get_instances -entity $corename] + + if {[ llength $instance_list ] == 0} { + + if {!$::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_disable_warnings} { + ai_post_message warning "The auto-constraining script was not able to detect any instance for core < $corename >" all + ai_post_message warning "Verify the following:" + ai_post_message warning " The core < $corename > is instantiated within another component (wrapper)" all + ai_post_message warning " The core is not the top-level of the project" all + } + } + + return $instance_list +} +proc ai_get_registers {pattern} { + if {$::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_disable_warnings} { + return [get_registers -nowarn -no_duplicates $pattern] + } else { + return [get_registers -no_duplicates $pattern] + } +} +proc ai_get_pins {pattern} { + if {$::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_corename_disable_warnings} { + return [get_pins -nowarn -no_duplicates $pattern] + } else { + return [get_pins -no_duplicates $pattern] + } +} +proc ai_get_pin_node_name {pattern} { + set pin_collection [ai_get_pins $pattern] + set num_pins [get_collection_size $pin_collection] + if {$num_pins == 1} { + foreach_in_collection id $pin_collection { + set node_name [get_node_info -name $id] + return $node_name + } + } + return "" + +} + +# ---------------------------------------------------------------- +# +proc ai_get_collection_size_from_pattern {pattern} { +# +# Description: Takes a string regex and gets the pin collection. +# +# ---------------------------------------------------------------- + set pin_collection [get_pins -no_duplicates $pattern] + return [get_collection_size $pin_collection] +} + +# ---------------------------------------------------------------- +# +proc print_clock_data {d} { +# +# Description: Prints clock data dict +# +# ---------------------------------------------------------------- + dict for {clock_key info} $d { + ai_post_message debug "Clock: $clock_key" + dict for {key val} $info { + ai_post_message debug " $key: $val" + } + } +} + +# ---------------------------------------------------------------- +# +proc ai_subst_instname {clock_data_dict patt} { +# +# Description: Takes a string regex and gets the pin collection. +# +# ---------------------------------------------------------------- + dict for {clock_key info} $clock_data_dict { + dict with info { + regsub -all "__inst_name__" $name $patt new_name + regsub -all "__inst_name__" $pattern $patt new_pattern + + dict set clock_data_dict $clock_key name $new_name + dict set clock_data_dict $clock_key pattern $new_pattern + + if {[dict exists $clock_data_dict $clock_key "through_pin" ]} { + regsub -all "__inst_name__" $through_pin $patt new_through_pin + dict set clock_data_dict $clock_key through_pin $new_through_pin + } + } + } + return $clock_data_dict +} +# ---------------------------------------------------------------- +# +proc ai_update_genclk_div_mult {clock_data_dict pll_parameters_dict} { +# +# Description: Updates the dict with div/mult values collected from +# the PLL's atom parameters. +# +# ---------------------------------------------------------------- + set compensated_counter_div 0 + set clock_to_compensate [dict get $pll_parameters_dict clock_to_compensate] + # Loop over dict to find the compensated counter's div value first. + dict for {clock_key info} $clock_data_dict { + dict with info { + if {[info exists counter_index]} { + if {$counter_index == $clock_to_compensate} { + set compensated_counter_div [dict get $pll_parameters_dict c${counter_index}_total] + } + } + } + unset -nocomplain counter_index + } + dict for {clock_key info} $clock_data_dict { + dict with info { + ai_post_message debug "Getting div/mult factors for clock $clock_key" + + set ccnt -1 + if {[info exists counter_index]} { + set ccnt [dict get $pll_parameters_dict c${counter_index}_total] + set ccnt_dc [dict get $pll_parameters_dict duty_cycle${counter_index}] + } else { + set counter_index -1 + set ccnt_dc 50 + } + set mult_div [ai_get_mult_div_factors \ + $clock_key \ + $src \ + [dict get $pll_parameters_dict n_total] \ + [dict get $pll_parameters_dict m_total] \ + $ccnt \ + $counter_index \ + $compensated_counter_div \ + [dict get $pll_parameters_dict compensation_mode] \ + [dict get $pll_parameters_dict clock_to_compensate]] + + lassign $mult_div mult div + + ai_post_message debug "Setting mult_div factors for: $clock_key to $mult/$div" + + dict set clock_data_dict $clock_key multiply_by $mult + dict set clock_data_dict $clock_key divide_by $div + dict set clock_data_dict $clock_key duty_cycle $ccnt_dc + } + unset -nocomplain counter_index + } + return $clock_data_dict +} +# ---------------------------------------------------------------- +# +proc ai_set_genclk_pin_info {clock_data_dict} { +# +# Description: Updates the dict with pin info collected from making +# STA API calls. +# +# ---------------------------------------------------------------- + dict for {clock_key info} $clock_data_dict { + dict with info { + ai_post_message debug "Setting pin info for clock $clock_key" + if {$node_type == "register"} { + set pin_collection [ai_get_registers $pattern] + } elseif {$node_type == "pin"} { + set pin_collection [ai_get_pins $pattern] + } else { + ai_post_message "debug" "Incorrect type of node." + } + set num_pins [get_collection_size $pin_collection] + if {$num_pins == 1} { + # Always set valid to true if we found the pin node + ai_post_message debug "Setting clock as valid." + dict set clock_data_dict $clock_key is_valid true + + # This for loop should only loop once. + foreach_in_collection id $pin_collection { + set node_name [get_node_info -name $id] + dict set clock_data_dict $clock_key pin_id $id + dict set clock_data_dict $clock_key pin_node_name $node_name + } + # Check if clock_exists, if it does, then + # set key "exists" on the clock info dict. + dict set clock_data_dict $clock_key exists [ai_clock_exists $node_name] + + + } else { + dict set clock_data_dict $clock_key is_valid false + } + + } + } + return $clock_data_dict + + +} +# ---------------------------------------------------------------- +# +proc ai_set_baseclk_pin_info {clock_data_dict refclk_data_dict pll_name} { +# + # Description: Updates the dict with pin info collected from refclk data + # dict, which was obtained by traversing netlist. +# +# ---------------------------------------------------------------- + ai_post_message debug "In ai_set_baseclk_pin_info" + + dict for {clock_key info} $clock_data_dict { + dict with info { + ai_post_message debug "Setting pin info for clock $clock_key" + + set node_name "" + dict for {clock_id info} $refclk_data_dict { + dict with info { + # Figure out which refclk is the baseclk based on input muxes + set pll_atom [ai_get_pll_atom $pll_name] + set clkin_enum "ENUM_IOPLL_CLKIN_0_SRC" + if {!$is_main_refclk} { + set clkin_enum "ENUM_IOPLL_CLKIN_1_SRC" + } + set refclk_src [get_atom_node_info -key $clkin_enum -node $pll_atom] + + set refclk_port_name "$pattern" + if {[regexp {[0-9]+} $refclk_src refclk_index]} { + set refclk_port_name "$pattern\[$refclk_index\]" + } + if {[string equal -nocase $refclk_port_name $ref_pin_node_name]} { + dict set clock_data_dict $clock_key pin_id $ref_pin_id + dict set clock_data_dict $clock_key pin_node_name $ref_pin_node_name + dict set clock_data_dict $clock_key port_id $ref_port_id + dict set clock_data_dict $clock_key port_node_name $ref_port_node_name + dict set clock_data_dict $clock_key is_fpga_pin $ref_is_fpga_pin + set node_name $ref_port_node_name + break + } + } + } + # Check if clock_exists, if it does, then + # set key "exists" on the clock info dict. + dict set clock_data_dict $clock_key exists [ai_clock_exists $node_name] + + } + } + return $clock_data_dict + +} +proc ai_get_n_cnt_clock_node_name {gen_clock_data_dict} { + dict for {clock_key info} $gen_clock_data_dict { + dict with info { + ai_post_message debug "Clock: $clock_key, pin_node_name: $pin_node_name" + + if {$clock_key == "n_cnt_clock"} { + return $pin_node_name + } + } + } + return "" +} + +# ---------------------------------------------------------------- +# +proc ai_update_baseclk_data {base_clock_data_dict pll_parameters_dict} { +# + # Description: Updates the refclk information based on atom settings +# +# ---------------------------------------------------------------- + ai_post_message debug "In ai_update_baseclk_data_dict" + + dict for {base_clock_key info} $base_clock_data_dict { + dict with info { + if {$is_main_refclk} { + set ref_period [dict get $pll_parameters_dict refclk_period] + set ref_period [expr round($ref_period * 1000.0)/1000.0] + set ref_period [format %.3f $ref_period] + dict set base_clock_data_dict $base_clock_key period $ref_period + + set half_period [expr $ref_period /2] + set half_period [expr round($half_period * 1000.0)/1000.0] + set half_period [format %.3f $half_period] + dict set base_clock_data_dict $base_clock_key half_period $half_period + } + } + } + + return $base_clock_data_dict +} + +# ---------------------------------------------------------------- +# +proc ai_update_genclk_sources {base_clock_data_dict gen_clock_data_dict pll_parameters_dict} { +# +# Description: Updates the genclk data dict with src nodes from the appropriate +# refclks +# +# ---------------------------------------------------------------- + ai_post_message debug "In ai_update_genclk_sources" + + # Check if vcoph pin exists, if it does then set the clock source + # as vcoph otherwise set it to either refclk or n_cnt_clock + set vcoph_exists false + if {[dict exists $gen_clock_data_dict vcoph]} { + set vcoph_pin_name [ai_get_pin_node_name [dict get $gen_clock_data_dict vcoph pattern]] + if {$vcoph_pin_name != ""} { + ai_post_message debug "vcoph pin name: $vcoph_pin_name " + set vcoph_exists true + } + } + + dict for {clock_key info} $gen_clock_data_dict { + dict with info { + ai_post_message debug "Setting src pin info for clock $clock_key" + + set node_name "" + set main_refclk_key "" + dict for {base_clock_key base_clock_data_dict_info} $base_clock_data_dict { + dict with base_clock_data_dict_info { + if {$is_main_refclk} { + set main_refclk_key $base_clock_key + if {$is_fpga_pin} { + set node_name $port_node_name + } else { + set node_name $pin_node_name + } + break + } + } + } + if {$clock_key != "n_cnt_clock" && ![dict get $pll_parameters_dict n_bypass]} { + set src "n_cnt_clock" + } + + if {$src == "refclk" || $src == "cascade_in" || $src == "pll_cascade_in" || $src == "core_refclk"} { + set src_ $node_name + } elseif {$src == "n_cnt_clock"} { + if {[is_post_syn_sta]} { + set gen_clock_data_dict_for_post_syn $gen_clock_data_dict + dict for {clk_key gen_clock_data_dict_for_post_syn_info} $gen_clock_data_dict_for_post_syn { + if {$clk_key == "n_cnt_clock"} { + dict set gen_clock_data_dict $clock_key master [dict get $gen_clock_data_dict_for_post_syn_info name] + } + } + } else { + set src_ [ai_get_n_cnt_clock_node_name $gen_clock_data_dict] + } + } else { + set src_ "" + ai_post_message "warning" "Undefined clock source: $src" + dict set gen_clock_data_dict $clock_key is_valid false + } + + if {$clock_key != "n_cnt_clock" && $clock_key != "vcoph" && $vcoph_exists} { + set src_ $vcoph_pin_name + } + dict set gen_clock_data_dict $clock_key src $src_ + } + } + return $gen_clock_data_dict +} +proc ai_invalidate_clocks {clock_data_dict} { + # Set the is_valid flag on each clock to false + dict for {clock_key info} $clock_data_dict { + dict with info { + dict set clock_data_dict $clock_key is_valid false + } + } + return $clock_data_dict +} +proc ai_get_first_outclk_node {clock_data_dict} { + set outclk_pin_id "None" + dict for {clock_key info} $clock_data_dict { + dict with info { + if {$node_type == "pin" && $is_valid} { + set outclk_pin_id $pin_id + break + } + } + } + if {$outclk_pin_id == "None"} { + ai_post_message "warning" "Could not find any valid outclks" + } + return $outclk_pin_id +} +# ---------------------------------------------------------------- +# +proc ai_get_pll_pins { instname } { +# +# Description: Stores the pins of interest for the instance of the IP +# +# ---------------------------------------------------------------- + + set base_clock_data_dict $::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_base_clock_data + set gen_clock_data_dict $::GLOBAL_top_io_pll_altera_iopll_1931_oypl3jq_gen_clock_data + # First regsub the instance name for the pin names and patterns. + set base_clock_data_dict [ai_subst_instname $base_clock_data_dict $instname] + set gen_clock_data_dict [ai_subst_instname $gen_clock_data_dict $instname] + + + set pll_parameters_dict [ai_get_pll_atom_parameters $instname] + set gen_clock_data_dict [ai_set_genclk_pin_info $gen_clock_data_dict] + + ai_post_message debug "gen_clock_data_dict initial: " + print_clock_data $gen_clock_data_dict + + # Traverse the first generated clock back to find FPGA pins for refclks. + set outclk_node_id [ai_get_first_outclk_node $gen_clock_data_dict] + if {$outclk_node_id != "None"} { + set refclk_data_dict [ai_get_input_clk_info $outclk_node_id] + ai_post_message debug "refclk_data_dict: " + print_clock_data $refclk_data_dict + + set base_clock_data_dict [ai_set_baseclk_pin_info $base_clock_data_dict $refclk_data_dict $instname] + set gen_clock_data_dict [ai_update_genclk_sources $base_clock_data_dict $gen_clock_data_dict $pll_parameters_dict] + set gen_clock_data_dict [ai_update_genclk_div_mult $gen_clock_data_dict $pll_parameters_dict] + set base_clock_data_dict [ai_update_baseclk_data $base_clock_data_dict $pll_parameters_dict] + ai_post_message debug "base_clock_data_dict: " + print_clock_data $base_clock_data_dict + ai_post_message debug "gen_clock_data_dict final: " + print_clock_data $gen_clock_data_dict + } else { + # Make sure that we don't create any clock constraints + # if no output clock was found + set gen_clock_data_dict [ai_invalidate_clocks $gen_clock_data_dict] + } + + return [list $base_clock_data_dict $gen_clock_data_dict] + +} + +# ---------------------------------------------------------------- +# +proc ai_get_input_clk_info { outclk_pin_id } { +# +# Description: Searches back from the output of the PLL to find the reference clock pin. +# If the reference clock is fed by an input buffer, it finds that pin, otherwise +# in cascading modes it will return the immediate reference clock input of the PLL. +# +# ---------------------------------------------------------------- + if {[ai_is_node_type_pll_clk $outclk_pin_id]} { + #stores the refclk pin ids that were found by tracing the + #output clocks back up + array set refclk_array [list] + ai_traverse_fanin_up_to_depth $outclk_pin_id ai_is_node_type_pll_inclk clock refclk_array 20 + array set refclk_info_array [list] + foreach {net_id id} [array get refclk_array] { + set net_name [get_node_info -name $net_id] + set refclk_info_array($net_id) $net_name + + } + # Dict to hold the refclk info found by traversing the netlist back. + # refclk_data = { + # clock_id = { + # ref_pin_id: str, + # ref_pin_node_name: str, + # ref_port_id: str, + # ref_port_node_name: str, + # ref_is_fpga_pin: true/false, + # } + # } + set refclk_data [dict create] + + set clock_id 0 + + #only works if there is either 1 or 2 refclks + if {[array size refclk_array] == 1 || [array size refclk_array] == 2} { + #iterate over each refclk pin and trace back to find its input port + foreach refclk_pin_id [array names refclk_info_array] { + array set user_refclk_array [list] + array unset refclk_array + array unset user_refclk_array [list] + + ai_traverse_fanin_up_to_depth $refclk_pin_id ai_is_node_type_user_clock clock user_refclk_array 5 + ai_traverse_fanin_up_to_depth $refclk_pin_id ai_is_node_type_pin clock refclk_array 5 + + # If fed by any user specified clock (which could be specified at the pin level or at the + # buffer level), then use that pin as the source. + # Otherwise, trace back to the dedicated input pin (depth 5 so that we don't include global clocks) + if {[array size user_refclk_array] == 1 || [array size refclk_array] < 1} { + # Fed by a user specified clock, a global clock etc. + dict set refclk_data $clock_id ref_pin_id $refclk_pin_id + dict set refclk_data $clock_id ref_pin_node_name $refclk_info_array($refclk_pin_id) + dict set refclk_data $clock_id ref_port_id "" + dict set refclk_data $clock_id ref_port_node_name "" + dict set refclk_data $clock_id ref_is_fpga_pin false + } else { + # Fed by a dedicated input pin + set port_id_ [lindex [array names refclk_array] 0] + + dict set refclk_data $clock_id ref_pin_id $refclk_pin_id + dict set refclk_data $clock_id ref_pin_node_name $refclk_info_array($refclk_pin_id) + dict set refclk_data $clock_id ref_port_id $port_id_ + dict set refclk_data $clock_id ref_port_node_name [get_node_info -name $port_id_] + dict set refclk_data $clock_id ref_is_fpga_pin true + } + + incr clock_id + } + } else { + ai_post_message critical_warning "Could not find PLL ref clock that feeds [get_node_info -name $outclk_pin_id]" all + } + } else { + ai_post_message error "Internal error: ai_get_input_clk_info only works for PLL output clocks" all + } + return $refclk_data +} + +# ---------------------------------------------------------------- +# +proc ai_is_node_type_pin { node_id } { +# +# Description: Determines if a node is a top-level port of the FPGA +# +# ---------------------------------------------------------------- + + set node_type [get_node_info -type $node_id] + if {$node_type == "port"} { + set result 1 + } else { + set result 0 + } + return $result +} + +# ---------------------------------------------------------------- +# +proc ai_is_node_type_user_clock { node_id } { +# +# Description: Determines if a node is a user-defined clock +# +# ---------------------------------------------------------------- + set node_name [get_node_info -name $node_id] + + if {[ai_clock_exists $node_name]} { + return 1 + } else { + return 0 + } +} + +# ---------------------------------------------------------------- +# +proc ai_is_node_type_pll_clk { node_id } { +# +# Description: Determines if a node is an output of a PLL +# +# ---------------------------------------------------------------- + + set cell_id [get_node_info -cell $node_id] + + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "IOPLL"} { + set node_name [get_node_info -name $node_id] + ai_post_message debug "Node_name: $node_name" + if {[string match "*fourteennm_pll\|outclk\\\[*\\\]" $node_name]||[string match "*tennm_pll\|outclk\\\[*\\\]" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll~ncntr_reg" $node_name]||[string match "*tennm_pll~ncntr_reg" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll~c*cntr_reg" $node_name]||[string match "*tennm_pll~c*cntr_reg" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll~mcntr_reg" $node_name]||[string match "*tennm_pll~mcntr_reg" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll\|lvds_clk\\\[*\\\]" $node_name]||[string match "*tennm_pll\|lvds_clk\\\[*\\\]" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll\|loaden\\\[*\\\]" $node_name]||[string match "*tennm_pll\|loaden\\\[*\\\]" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll\|vcoph\\\[*\\\]" $node_name]||[string match "*tennm_pll\|vcoph\\\[*\\\]" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll\|pll_cascade_out" $node_name]||[string match "*tennm_pll\|pll_cascade_out" $node_name]} { + set result 1 + } elseif {[string match "*fourteennm_pll\|extclk_output\\\[*\\\]" $node_name]||[string match "*tennm_pll\|extclk_output\\\[*\\\]" $node_name]} { + set result 1 + } else { + set result 0 + } + } else { + set result 0 + } + } + return $result +} + +# ---------------------------------------------------------------- +# +proc ai_is_node_type_pll_inclk { node_id } { +# +# Description: Determines if a node is an input of a PLL +# +# ---------------------------------------------------------------- + + + set cell_id [get_node_info -cell $node_id] + + if {$cell_id == ""} { + set result 0 + } else { + set atom_type [get_cell_info -atom_type $cell_id] + if {$atom_type == "IOPLL"} { + set node_name [get_node_info -name $node_id] + set fanin_edges [get_node_info -clock_edges $node_id] + if {([string match "*|refclk\\\[*\\\]" $node_name]) && [llength $fanin_edges] > 0} { + set result 1 + } elseif {([string match "*|pll_cascade_in" $node_name]) && [llength $fanin_edges] > 0} { + set result 1 + } elseif {([string match "*|cascade_in" $node_name]) && [llength $fanin_edges] > 0} { + set result 1 + } elseif {([string match "*|core_refclk" $node_name]) && [llength $fanin_edges] > 0} { + set result 1 + } else { + set result 0 + } + } else { + set result 0 + } + } + return $result +} + +# ----------------------------------------------------------------- +# +proc ai_find_pll_inclk { match_command edge_type } { +# +# Desciption: Finds the pll inclk pin whose name matches the +# match_command. Returns the inclk pin name if such +# a pin is found, and returns "" if it is not found +# +# ----------------------------------------------------------------- + + set fanin_id "" + foreach_in_collection pin [get_pins $match_command] { + if {[llength [get_node_info -${edge_type}_edges $pin]] > 0} { + set fanin_id $pin + break + } + } + return $fanin_id +} + +# ---------------------------------------------------------------- +# +proc ai_traverse_fanin_up_to_depth { node_id match_command edge_type results_array_name depth} { +# +# Description: General traversal function up until a depth. Use a function pointer to decide +# ending conditions. +# +# ---------------------------------------------------------------- + + upvar 1 $results_array_name results + + if {$depth < 0} { + error "Internal error: Bad timing netlist search depth" + } + + ai_post_message debug "\[ai_traverse_fanin_up_to_depth\] called with node_id: $node_id cmd: \"$match_command\" type: $edge_type node: [get_node_info -name $node_id]" + if {[is_post_syn_sta] && $match_command == "ai_is_node_type_pll_inclk"} { + set atom_name [get_cell_info -name [get_node_info -cell $node_id]] + set fanin_id [ai_find_pll_inclk $atom_name|core*refclk* $edge_type] + if {$fanin_id == ""} { + set fanin_id [ai_find_pll_inclk $atom_name|pll*cascade*in* $edge_type] + } + if {$fanin_id == ""} { + set fanin_id [ai_find_pll_inclk $atom_name|ref*clk* $edge_type] + } + set results($fanin_id) 1 + ai_post_message debug "\[ai_traverse_fanin_up_to_depth\] post syn model returning fanin id: [get_node_info -name $fanin_id]" + return + } + + set fanin_edges [get_node_info -${edge_type}_edges $node_id] + set number_of_fanin_edges [llength $fanin_edges] + for {set i 0} {$i != $number_of_fanin_edges} {incr i} { + set fanin_edge [lindex $fanin_edges $i] + set fanin_id [get_edge_info -src $fanin_edge] + if {$match_command == "" || [eval $match_command $fanin_id] != 0} { + set results($fanin_id) 1 + } elseif {$depth == 0} { + } else { + ai_traverse_fanin_up_to_depth $fanin_id $match_command $edge_type results [expr {$depth - 1}] + } + } +} + +# ---------------------------------------------------------------- +# +proc ai_index_in_collection { col j } { +# +# Description: Returns a particular index in a collection. +# Analagous to lindex for lists. +# +# ---------------------------------------------------------------- + + set i 0 + foreach_in_collection path $col { + if {$i == $j} { + return $path + } + set i [expr $i + 1] + } + return "" +} + +# +# Description: Rounds a given floating point number +# to 3 decimal places +# +# ---------------------------------------------------------------- +proc ai_round_3dp { x } { + return [expr { round($x * 1000) / 1000.0 } ] +} + +# ---------------------------------------------------------------- +# Description: Checks whether a given clock already exists +# ---------------------------------------------------------------- +proc ai_clock_exists { clock_name } { + set clock_found false + set input_clocks_col [get_clocks -nowarn] + set num_input_clocks [get_collection_size $input_clocks_col] + + if {$num_input_clocks > 0} { + foreach_in_collection iclk $input_clocks_col { + if {![is_clock_defined $iclk]} { + continue + } + + set clk_targets_col [get_clock_info -target $iclk] + set num_clk_targets [get_collection_size $clk_targets_col] + if {$num_clk_targets > 0} { + foreach_in_collection itgt $clk_targets_col { + set node_name [get_node_info -name $itgt] + if {[string compare $node_name $clock_name] == 0} { + set clock_found true + break + } + } + } + if {$clock_found == true} { + break; + } + } + } + + return $clock_found +} + +proc ai_get_pll_atom {instname} { + foreach_in_collection node [get_atom_nodes -type IOPLL] { + set name [get_atom_node_info -key NAME -node $node] + set node_list($name) $node + + if {[string first $instname $name] > -1} { + return $node + } + } + set sdc_file_name [info script] + ai_post_message warning "Could not find IOPLL atom with the name <$instname> while processing <$sdc_file_name>. Please check the synthesis report to ensure that the IOPLL was not synthesized away." all +} +proc ai_get_mult_div_factors {clock_key src ncnt mcnt ccnt counter_index \ + compensated_counter_div compensation_mode \ + clock_to_compensate} { + if {$clock_key == "vcoph"} { + set clock_mult $mcnt + set clock_div 1 + } elseif {$clock_key == "n_cnt_clock"} { + set clock_mult 1 + set clock_div $ncnt + } elseif {$clock_key == "m_cnt_clock"} { + set clock_mult 1 + set clock_div [expr {$mcnt * $ncnt}] + } else { + + if {[string first "vcoph" $src] > -1} { + set clock_mult 1 + set clock_div $ccnt + } else { + # Handle NDFB mode. + # The equation for counter which is to be compensated: C_k = M / N + # The equation for all other counters: C_!k = (M * C_k) / (N * C_!k) + if {$compensation_mode == "NON_DEDICATED_SOURCE_SYNC" || $compensation_mode == "NON_DEDICATED_NORMAL"} { + if {$counter_index == $clock_to_compensate} { + set clock_mult $mcnt + # Instead of dividing by N, we just divide by 1 + # since a clock based on the N counter would be created + # if N > 1 and this clock would be derived based on that, + # so we already have a division happening. + set clock_div 1 + } else { + set clock_mult [expr $mcnt * $compensated_counter_div] + set clock_div $ccnt + } + } else { + ai_post_message debug "Normal C counter" + set clock_mult $mcnt + set clock_div $ccnt + } + } + } + return [list $clock_mult $clock_div] + +} +# ---------------------------------------------------------------- +# +proc ai_get_pll_atom_parameters {instname} { +# +# Description: Gets the PLL paramaters from the Quartus atom and not +# from the IP generated parameters. +# +# ---------------------------------------------------------------- + + set pll_atom [ai_get_pll_atom $instname] + + dict set pll_params compensation_mode [get_atom_node_info -key ENUM_IOPLL_FEEDBACK -node $pll_atom] + dict set pll_params clock_to_compensate [get_atom_node_info -key INT_IOPLL_CLOCK_TO_COMPENSATE -node $pll_atom] + + # Get refclk frequency (might have changed since IP generation) + set refclk_freq [get_atom_node_info -key TIME_IOPLL_REFCLK_TIME -node $pll_atom] + set refclk_int [string trim $refclk_freq "*MHZmhz"] + set refclk_period [expr 1000.0 / $refclk_int] + dict set pll_params refclk_period $refclk_period + + dict set pll_params m_hi_div [get_atom_node_info -key INT_IOPLL_M_COUNTER_HIGH -node $pll_atom] + dict set pll_params m_lo_div [get_atom_node_info -key INT_IOPLL_M_COUNTER_LOW -node $pll_atom] + dict set pll_params m_bypass [get_atom_node_info -key BOOL_IOPLL_M_COUNTER_BYPASS_EN -node $pll_atom] + if {[dict get $pll_params m_bypass]} { + set total 1 + } else { + set total [expr [dict get $pll_params m_hi_div] + [dict get $pll_params m_lo_div]] + } + dict set pll_params m_total $total + + dict set pll_params n_hi_div [get_atom_node_info -key INT_IOPLL_N_COUNTER_HIGH -node $pll_atom] + dict set pll_params n_lo_div [get_atom_node_info -key INT_IOPLL_N_COUNTER_LOW -node $pll_atom] + dict set pll_params n_bypass [get_atom_node_info -key BOOL_IOPLL_N_COUNTER_BYPASS_EN -node $pll_atom] + if {[dict get $pll_params n_bypass]} { + set total 1 + } else { + set total [expr [dict get $pll_params n_hi_div] + [dict get $pll_params n_lo_div]] + } + dict set pll_params n_total $total + + for { set i 0 } { $i < 9} { incr i } { + # Get the C counter parameter settings from the atom netlist + dict set pll_params c${i}_hi_div [get_atom_node_info -key INT_IOPLL_C${i}_HIGH -node $pll_atom] + dict set pll_params c${i}_lo_div [get_atom_node_info -key INT_IOPLL_C${i}_LOW -node $pll_atom] + dict set pll_params c${i}_bypass [get_atom_node_info -key BOOL_IOPLL_C${i}_BYPASS_EN -node $pll_atom] + dict set pll_params c${i}_odd_div_duty_en [get_atom_node_info -key BOOL_IOPLL_C${i}_EVEN_DUTY_EN -node $pll_atom] + + # Calculate the total counter value + if {[dict get $pll_params c${i}_bypass]} { + set total 1 + } else { + set total [expr [dict get $pll_params c${i}_hi_div] + [dict get $pll_params c${i}_lo_div]] + } + dict set pll_params c${i}_total $total + + # Calculate the duty cycle + if {[dict get $pll_params c${i}_bypass]} { + set total_duty 50 + } else { + if {[dict get $pll_params c${i}_odd_div_duty_en]} { + set duty_tweak 1 + } else { + set duty_tweak 0 + } + set total_duty [expr (([dict get $pll_params c${i}_hi_div] - (0.5*$duty_tweak))*100)/$total] + set total_duty [format %.3f $total_duty] + } + dict set pll_params duty_cycle${i} $total_duty + } + + return $pll_params +} + +#__ACDS_USER_COMMENT__Set max delay if in fit flow, otherwise set false path through "through_pin" +# originally in the LVDS SDC. This is called if we are exporting loaden to LVDS +proc set_max_delay_in_fit_or_false_path_in_sta_through_no_warn {through_pin delay} { + + set through_pin_collection [get_pins -compatibility_mode -nowarn $through_pin] + if {[get_collection_size $through_pin_collection] <= 0} { return } + + # if fit_flow == 1 + if {$::TimeQuestInfo(nameofexecutable) == "quartus_fit" } { + set_max_delay -through $through_pin_collection $delay + } else { + set_false_path -through $through_pin_collection + } +} + +# ---------------------------------------------------------------- +# +proc is_m_n_cntr {pattern} { +# +# Description: Determines if a pattern matches m/n_cntr +# +# ---------------------------------------------------------------- + + if {[string match "*fourteennm_pll~ncntr_reg" $pattern]||[string match "*tennm_pll~ncntr_reg" $pattern]|| + [string match "*fourteennm_pll~mcntr_reg" $pattern]||[string match "*tennm_pll~mcntr_reg" $pattern]|| + [string match "*tennm_ph2_iopll~ncntr_reg" $pattern]||[string match "*tennm_ph2_iopll~mcntr_reg" $pattern]} { + return 1 + } else { + return 0 + } +} + +# ---------------------------------------------------------------- +# +proc create_non_virtual_generated_clock_with_master_or_source \ +{master source name multiply_by divide_by phase duty_cycle pin_node_name} { +# +# Description: Creates a non-virtual generated clock using +# the -source or the -master argument +# +# ---------------------------------------------------------------- + if {$master != ""} { + create_generated_clock -add \ + -master $master \ + -name $name \ + -multiply_by $multiply_by \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cycle \ + $pin_node_name + } else { + create_generated_clock -add \ + -source $source \ + -name $name \ + -multiply_by $multiply_by \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cycle \ + $pin_node_name + } +} + +# ---------------------------------------------------------------- +# +proc create_virtual_generated_clock_with_master_or_source \ +{master source name multiply_by divide_by phase duty_cycle} { +# +# Description: Creates a virtual generated clock using +# the -source or the -master argument +# +# ---------------------------------------------------------------- + if {$master != ""} { + create_generated_clock -add \ + -master $master \ + -name $name \ + -multiply_by $multiply_by \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cycle + } else { + create_generated_clock -add \ + -source $source \ + -name $name \ + -multiply_by $multiply_by \ + -divide_by $divide_by \ + -phase $phase \ + -duty_cycle $duty_cycle + } +} diff --git a/corev_apu/altera/ip/io_pll/greybox/io_pll.v b/corev_apu/altera/ip/io_pll/greybox/io_pll.v new file mode 100644 index 0000000000..518a727f90 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/greybox/io_pll.v @@ -0,0 +1,323 @@ +// Copyright (C) 2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the Intel FPGA Software License Subscription Agreements +// on the Quartus Prime software download page. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 24.1.0 Build 115 03/21/2024 SC Pro Edition" + +// DATE "10/15/2024 10:52:25" + +// +// Device: Altera AGFB014R24B2E2V Package FBGA2486 +// + +// +// This greybox netlist file is for third party Synthesis Tools +// for timing and resource estimation only. +// + + +module io_pll ( + locked, + outclk_0, + outclk_1, + outclk_2, + outclk_3, + outclk_4, + refclk, + rst)/* synthesis synthesis_greybox=0 */; +output locked; +output outclk_0; +output outclk_1; +output outclk_2; +output outclk_3; +output outclk_4; +input refclk; +input rst; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +// unknown value (1'bx) is not needed for this tool. Default to 1'b0 +assign unknown = 1'b0; + +wire \iopll_0.tennm_pll_O_BLOCK_SELECT ; +wire \iopll_0.locked ; +wire \iopll_0.outclk_0 ; +wire \iopll_0.outclk_1 ; +wire \iopll_0.outclk_2 ; +wire \iopll_0.outclk_3 ; +wire \iopll_0.outclk_4 ; + +wire [8:0] \iopll_0.tennm_pll_OUTCLK_bus ; + +assign \iopll_0.outclk_0 = \iopll_0.tennm_pll_OUTCLK_bus [1]; +assign \iopll_0.outclk_1 = \iopll_0.tennm_pll_OUTCLK_bus [2]; +assign \iopll_0.outclk_2 = \iopll_0.tennm_pll_OUTCLK_bus [3]; +assign \iopll_0.outclk_3 = \iopll_0.tennm_pll_OUTCLK_bus [4]; +assign \iopll_0.outclk_4 = \iopll_0.tennm_pll_OUTCLK_bus [5]; + +tennm_iopll \iopll_0.tennm_pll ( + .core_refclk(refclk), + .csr_clk(vcc), + .csr_en(vcc), + .csr_in(vcc), + .dprio_clk(gnd), + .dprio_rst_n(~rst), + .dps_rst_n(~rst), + .extswitch(gnd), + .fbclk_in(gnd), + .fblvds_in(gnd), + .mdio_dis(gnd), + .pfden(vcc), + .phase_en(gnd), + .pipeline_global_en_n(gnd), + .pll_cascade_in(gnd), + .pll_select_top_avl(vcc), + .pma_csr_test_dis(vcc), + .read(gnd), + .rst_n(~rst), + .scan_mode_n(vcc), + .scan_shift_n(vcc), + .uc_cal_clk(gnd), + .uc_cal_read(gnd), + .uc_cal_write(gnd), + .up_dn(gnd), + .user_mode(vcc), + .write(gnd), + .zdb_in(gnd), + .clken({gnd,gnd}), + .cnt_sel({gnd,gnd,gnd,gnd}), + .dprio_address({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .num_phase_shifts({gnd,gnd,gnd}), + .refclk({gnd,gnd,gnd,gnd}), + .uc_cal_addr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .uc_cal_writedata({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .writedata({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .block_select(\iopll_0.tennm_pll_O_BLOCK_SELECT ), + .cal_ok(), + .clk0_bad(), + .clk1_bad(), + .clksel(), + .core_avl_busy(), + .core_cal_done(), + .csr_out(), + .dll_output(), + .fbclk_out(), + .fblvds_out(), + .iopll_out_sig1(), + .iopll_out_sig2(), + .lf_reset(), + .lock(\iopll_0.locked ), + .phase_done(), + .pll_cascade_out(), + .pll_pd(), + .vcop_en(), + .extclk_dft(), + .extclk_output(), + .loaden(), + .lvds_clk(), + .outclk(\iopll_0.tennm_pll_OUTCLK_bus ), + .readdata(), + .uc_cal_readdata(), + .vcoph()); +defparam \iopll_0.tennm_pll .auto_clk_sw_en = "false"; +defparam \iopll_0.tennm_pll .bw_mode = "mid_bw"; +defparam \iopll_0.tennm_pll .c0_bypass_en = "true"; +defparam \iopll_0.tennm_pll .c0_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c0_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c0_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c0_high = 256; +defparam \iopll_0.tennm_pll .c0_low = 256; +defparam \iopll_0.tennm_pll .c0_out_en = "false"; +defparam \iopll_0.tennm_pll .c0_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c0_prst = 1; +defparam \iopll_0.tennm_pll .c1_bypass_en = "false"; +defparam \iopll_0.tennm_pll .c1_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c1_even_duty_en = "true"; +defparam \iopll_0.tennm_pll .c1_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c1_high = 3; +defparam \iopll_0.tennm_pll .c1_low = 2; +defparam \iopll_0.tennm_pll .c1_out_en = "true"; +defparam \iopll_0.tennm_pll .c1_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c1_prst = 1; +defparam \iopll_0.tennm_pll .c2_bypass_en = "false"; +defparam \iopll_0.tennm_pll .c2_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c2_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c2_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c2_high = 4; +defparam \iopll_0.tennm_pll .c2_low = 4; +defparam \iopll_0.tennm_pll .c2_out_en = "true"; +defparam \iopll_0.tennm_pll .c2_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c2_prst = 1; +defparam \iopll_0.tennm_pll .c3_bypass_en = "false"; +defparam \iopll_0.tennm_pll .c3_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c3_even_duty_en = "true"; +defparam \iopll_0.tennm_pll .c3_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c3_high = 3; +defparam \iopll_0.tennm_pll .c3_low = 2; +defparam \iopll_0.tennm_pll .c3_out_en = "true"; +defparam \iopll_0.tennm_pll .c3_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c3_prst = 1; +defparam \iopll_0.tennm_pll .c4_bypass_en = "false"; +defparam \iopll_0.tennm_pll .c4_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c4_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c4_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c4_high = 4; +defparam \iopll_0.tennm_pll .c4_low = 4; +defparam \iopll_0.tennm_pll .c4_out_en = "true"; +defparam \iopll_0.tennm_pll .c4_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c4_prst = 3; +defparam \iopll_0.tennm_pll .c5_bypass_en = "false"; +defparam \iopll_0.tennm_pll .c5_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c5_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c5_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c5_high = 5; +defparam \iopll_0.tennm_pll .c5_low = 5; +defparam \iopll_0.tennm_pll .c5_out_en = "true"; +defparam \iopll_0.tennm_pll .c5_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c5_prst = 1; +defparam \iopll_0.tennm_pll .c6_bypass_en = "true"; +defparam \iopll_0.tennm_pll .c6_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c6_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c6_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c6_high = 256; +defparam \iopll_0.tennm_pll .c6_low = 256; +defparam \iopll_0.tennm_pll .c6_out_en = "false"; +defparam \iopll_0.tennm_pll .c6_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c6_prst = 1; +defparam \iopll_0.tennm_pll .c7_bypass_en = "true"; +defparam \iopll_0.tennm_pll .c7_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c7_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c7_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c7_high = 256; +defparam \iopll_0.tennm_pll .c7_low = 256; +defparam \iopll_0.tennm_pll .c7_out_en = "false"; +defparam \iopll_0.tennm_pll .c7_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c7_prst = 1; +defparam \iopll_0.tennm_pll .c8_bypass_en = "true"; +defparam \iopll_0.tennm_pll .c8_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c8_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .c8_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .c8_high = 256; +defparam \iopll_0.tennm_pll .c8_low = 256; +defparam \iopll_0.tennm_pll .c8_out_en = "false"; +defparam \iopll_0.tennm_pll .c8_ph_mux_prst = 0; +defparam \iopll_0.tennm_pll .c8_prst = 1; +defparam \iopll_0.tennm_pll .clkin_0_src = "coreclkin"; +defparam \iopll_0.tennm_pll .clkin_1_src = "ioclkin_0"; +defparam \iopll_0.tennm_pll .clock_name_1 = "outclk0"; +defparam \iopll_0.tennm_pll .clock_name_2 = "outclk1"; +defparam \iopll_0.tennm_pll .clock_name_3 = "outclk2"; +defparam \iopll_0.tennm_pll .clock_name_4 = "outclk3"; +defparam \iopll_0.tennm_pll .clock_name_5 = "outclk4"; +defparam \iopll_0.tennm_pll .clock_name_global_0 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_1 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_2 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_3 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_4 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_5 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_6 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_7 = "false"; +defparam \iopll_0.tennm_pll .clock_name_global_8 = "false"; +defparam \iopll_0.tennm_pll .clock_to_compensate = 1; +defparam \iopll_0.tennm_pll .cmp_buf_dly = "0 ps"; +defparam \iopll_0.tennm_pll .device_variant = "device1"; +defparam \iopll_0.tennm_pll .duty_cycle_0 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_1 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_2 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_3 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_4 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_5 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_6 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_7 = 50; +defparam \iopll_0.tennm_pll .duty_cycle_8 = 50; +defparam \iopll_0.tennm_pll .extclk_0_cnt_src = "pll_extclk_cnt_src_vss"; +defparam \iopll_0.tennm_pll .extclk_0_enable = "true"; +defparam \iopll_0.tennm_pll .extclk_1_cnt_src = "pll_extclk_cnt_src_vss"; +defparam \iopll_0.tennm_pll .extclk_1_enable = "true"; +defparam \iopll_0.tennm_pll .feedback = "direct"; +defparam \iopll_0.tennm_pll .iopll_type = "top_bottom"; +defparam \iopll_0.tennm_pll .loaden_0_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .loaden_0_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .loaden_1_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .loaden_1_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .lock_mode = "mid_lock_time"; +defparam \iopll_0.tennm_pll .lvdsclk_0_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .lvdsclk_0_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .lvdsclk_1_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .lvdsclk_1_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .m_counter_bypass_en = "false"; +defparam \iopll_0.tennm_pll .m_counter_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .m_counter_even_duty_en = "false"; +defparam \iopll_0.tennm_pll .m_counter_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .m_counter_high = 5; +defparam \iopll_0.tennm_pll .m_counter_low = 5; +defparam \iopll_0.tennm_pll .m_counter_scratch = 1; +defparam \iopll_0.tennm_pll .manu_clk_sw_en = "false"; +defparam \iopll_0.tennm_pll .merging_permitted = "false"; +defparam \iopll_0.tennm_pll .n_counter_bypass_en = "true"; +defparam \iopll_0.tennm_pll .n_counter_coarse_dly = "0 ps"; +defparam \iopll_0.tennm_pll .n_counter_fine_dly = "0 ps"; +defparam \iopll_0.tennm_pll .n_counter_high = 256; +defparam \iopll_0.tennm_pll .n_counter_low = 256; +defparam \iopll_0.tennm_pll .n_counter_odd_div_duty_en = "false"; +defparam \iopll_0.tennm_pll .outclk0 = "0 ps"; +defparam \iopll_0.tennm_pll .outclk1 = "200.0 mhz"; +defparam \iopll_0.tennm_pll .outclk2 = "125.0 mhz"; +defparam \iopll_0.tennm_pll .outclk3 = "200.0 mhz"; +defparam \iopll_0.tennm_pll .outclk4 = "125.0 mhz"; +defparam \iopll_0.tennm_pll .outclk5 = "100.0 mhz"; +defparam \iopll_0.tennm_pll .outclk6 = "0 ps"; +defparam \iopll_0.tennm_pll .outclk7 = "0 ps"; +defparam \iopll_0.tennm_pll .outclk8 = "0 ps"; +defparam \iopll_0.tennm_pll .pfd = "100.0 mhz"; +defparam \iopll_0.tennm_pll .phase_shift_0 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_1 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_2 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_3 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_4 = "2000 ps"; +defparam \iopll_0.tennm_pll .phase_shift_5 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_6 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_7 = "0 ps"; +defparam \iopll_0.tennm_pll .phase_shift_8 = "0 ps"; +defparam \iopll_0.tennm_pll .prot_mode = "basic"; +defparam \iopll_0.tennm_pll .ref_buf_dly = "0 ps"; +defparam \iopll_0.tennm_pll .refclk_src_mux = "clk_0"; +defparam \iopll_0.tennm_pll .refclk_time = "100.0 mhz"; +defparam \iopll_0.tennm_pll .self_reset_en = "false"; +defparam \iopll_0.tennm_pll .silicon_rev = "reva"; +defparam \iopll_0.tennm_pll .simple_pll = "false"; +defparam \iopll_0.tennm_pll .speed_grade = "dash1"; +defparam \iopll_0.tennm_pll .uc_channel_base_addr = 0; +defparam \iopll_0.tennm_pll .vco = "1000.0 mhz"; +defparam \iopll_0.tennm_pll .zdb_in_clk_src = "clk0"; + +assign locked = \iopll_0.locked ; + +assign outclk_0 = \iopll_0.outclk_0 ; + +assign outclk_1 = \iopll_0.outclk_1 ; + +assign outclk_2 = \iopll_0.outclk_2 ; + +assign outclk_3 = \iopll_0.outclk_3 ; + +assign outclk_4 = \iopll_0.outclk_4 ; + +endmodule diff --git a/corev_apu/altera/ip/io_pll/io_pll.bsf b/corev_apu/altera/ip/io_pll/io_pll.bsf new file mode 100644 index 0000000000..00d509e179 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.bsf @@ -0,0 +1,126 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the Intel FPGA Software License Subscription Agreements +on the Quartus Prime software download page. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 368) + (text "io_pll" (rect 69 0 87 12)(font "SansSerif" (font_size 11))) + (text "inst" (rect 8 352 20 364)(font "Arial" )) + (port + (pt 0 76) + (input) + (text "refclk" (rect 0 0 22 12)(font "SansSerif" (font_size 8))) + (text "refclk" (rect 4 65 40 76)(font "SansSerif" (font_size 8))) + (line (pt 0 76)(pt 51 76)(line_width 1)) + ) + (port + (pt 0 126) + (input) + (text "rst" (rect 0 0 10 12)(font "SansSerif" (font_size 8))) + (text "rst" (rect 4 115 22 126)(font "SansSerif" (font_size 8))) + (line (pt 0 126)(pt 51 126)(line_width 1)) + ) + (port + (pt 168 76) + (output) + (text "locked" (rect 0 0 24 12)(font "SansSerif" (font_size 8))) + (text "locked" (rect 137 65 173 76)(font "SansSerif" (font_size 8))) + (line (pt 168 76)(pt 119 76)(line_width 1)) + ) + (port + (pt 168 126) + (output) + (text "outclk_0" (rect 0 0 33 12)(font "SansSerif" (font_size 8))) + (text "outclk_0" (rect 127 115 175 126)(font "SansSerif" (font_size 8))) + (line (pt 168 126)(pt 119 126)(line_width 1)) + ) + (port + (pt 168 176) + (output) + (text "outclk_1" (rect 0 0 31 12)(font "SansSerif" (font_size 8))) + (text "outclk_1" (rect 129 165 177 176)(font "SansSerif" (font_size 8))) + (line (pt 168 176)(pt 119 176)(line_width 1)) + ) + (port + (pt 168 226) + (output) + (text "outclk_2" (rect 0 0 33 12)(font "SansSerif" (font_size 8))) + (text "outclk_2" (rect 127 215 175 226)(font "SansSerif" (font_size 8))) + (line (pt 168 226)(pt 119 226)(line_width 1)) + ) + (port + (pt 168 276) + (output) + (text "outclk_3" (rect 0 0 33 12)(font "SansSerif" (font_size 8))) + (text "outclk_3" (rect 127 265 175 276)(font "SansSerif" (font_size 8))) + (line (pt 168 276)(pt 119 276)(line_width 1)) + ) + (port + (pt 168 326) + (output) + (text "outclk_4" (rect 0 0 34 12)(font "SansSerif" (font_size 8))) + (text "outclk_4" (rect 127 315 175 326)(font "SansSerif" (font_size 8))) + (line (pt 168 326)(pt 119 326)(line_width 1)) + ) + (drawing + (text "refclk" (rect 19 46 74 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 56 71 130 152)(font "SansSerif" (color 0 0 0))) + (text "locked" (rect 120 46 276 105)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "export" (rect 89 71 214 152)(font "SansSerif" (color 0 0 0))) + (text "reset" (rect 22 96 74 205)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "reset" (rect 56 121 142 252)(font "SansSerif" (color 0 0 0))) + (text "outclk0" (rect 120 96 282 205)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 104 121 226 252)(font "SansSerif" (color 0 0 0))) + (text "outclk1" (rect 120 146 282 305)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 104 171 226 352)(font "SansSerif" (color 0 0 0))) + (text "outclk2" (rect 120 196 282 405)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 104 221 226 452)(font "SansSerif" (color 0 0 0))) + (text "outclk3" (rect 120 246 282 505)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 104 271 226 552)(font "SansSerif" (color 0 0 0))) + (text "outclk4" (rect 120 296 282 605)(font "SansSerif" (color 128 0 0)(font_size 9))) + (text "clk" (rect 104 321 226 652)(font "SansSerif" (color 0 0 0))) + (text " io_pll " (rect 145 351 338 712)(font "SansSerif" )) + (line (pt 51 34)(pt 119 34)(line_width 1)) + (line (pt 119 34)(pt 119 351)(line_width 1)) + (line (pt 51 351)(pt 119 351)(line_width 1)) + (line (pt 51 34)(pt 51 351)(line_width 1)) + (line (pt 52 55)(pt 52 80)(line_width 1)) + (line (pt 53 55)(pt 53 80)(line_width 1)) + (line (pt 118 55)(pt 118 80)(line_width 1)) + (line (pt 117 55)(pt 117 80)(line_width 1)) + (line (pt 52 105)(pt 52 130)(line_width 1)) + (line (pt 53 105)(pt 53 130)(line_width 1)) + (line (pt 118 105)(pt 118 130)(line_width 1)) + (line (pt 117 105)(pt 117 130)(line_width 1)) + (line (pt 118 155)(pt 118 180)(line_width 1)) + (line (pt 117 155)(pt 117 180)(line_width 1)) + (line (pt 118 205)(pt 118 230)(line_width 1)) + (line (pt 117 205)(pt 117 230)(line_width 1)) + (line (pt 118 255)(pt 118 280)(line_width 1)) + (line (pt 117 255)(pt 117 280)(line_width 1)) + (line (pt 118 305)(pt 118 330)(line_width 1)) + (line (pt 117 305)(pt 117 330)(line_width 1)) + (line (pt 0 0)(pt 168 0)(line_width 1)) + (line (pt 168 0)(pt 168 368)(line_width 1)) + (line (pt 0 368)(pt 168 368)(line_width 1)) + (line (pt 0 0)(pt 0 368)(line_width 1)) + ) +) diff --git a/corev_apu/altera/ip/io_pll/io_pll.cmp b/corev_apu/altera/ip/io_pll/io_pll.cmp new file mode 100644 index 0000000000..dd0657c37f --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.cmp @@ -0,0 +1,13 @@ + component io_pll is + port ( + refclk : in std_logic := 'X'; -- clk + locked : out std_logic; -- export + rst : in std_logic := 'X'; -- reset + outclk_0 : out std_logic; -- clk + outclk_1 : out std_logic; -- clk + outclk_2 : out std_logic; -- clk + outclk_3 : out std_logic; -- clk + outclk_4 : out std_logic -- clk + ); + end component io_pll; + diff --git a/corev_apu/altera/ip/io_pll/io_pll.csv b/corev_apu/altera/ip/io_pll/io_pll.csv new file mode 100644 index 0000000000..47e343fe9f --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.csv @@ -0,0 +1,18 @@ +# system info io_pll on 2024.10.15.08:52:05 +system_info: +name,value +DEVICE,AGFB014R24B2E2V +DEVICE_FAMILY,Agilex 7 +GENERATION_ID,0 +# +# +# Files generated for io_pll on 2024.10.15.08:52:05 +files: +filepath,kind,attributes,module,is_top +sim/io_pll.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,io_pll,true +altera_iopll_1931/sim/io_pll_altera_iopll_1931_oypl3jq.vo,VERILOG,,io_pll_altera_iopll_1931_oypl3jq,false +# +# Map from instance-path to kind of module +instances: +instancePath,module +io_pll.iopll_0,io_pll_altera_iopll_1931_oypl3jq diff --git a/corev_apu/altera/ip/io_pll/io_pll.html b/corev_apu/altera/ip/io_pll/io_pll.html new file mode 100644 index 0000000000..c818f12aa6 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.html @@ -0,0 +1,1397 @@ + + + + + datasheet for io_pll + + + + + + + + +
io_pll +
+
+
+ + + + + +
2024.10.15.08:52:06Datasheet
+
+
Overview
+
+
+ + + + +
+
+
+
+
+
+
+
Memory Map
+ + + + +
+ +
+
+

iopll_0

altera_iopll v19.3.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
gui_device_familyAgilex 7
gui_device_componentAGFB014R24B2E2V
gui_device_speed_grade2
gui_en_reconffalse
gui_en_dps_portsfalse
gui_location_typeI/O Bank
gui_reference_clock_frequency100.0
gui_use_coreclktrue
gui_use_lockedtrue
gui_en_adv_paramsfalse
gui_pll_bandwidth_presetMedium
gui_lock_settingLow Lock Time
gui_pll_auto_resetfalse
gui_en_lvds_portsDisabled
gui_operation_modedirect
gui_refclk_switchfalse
gui_refclk1_frequency100.0
gui_en_phout_portsfalse
gui_en_extclkout_portsfalse
gui_number_of_clocks5
gui_fix_vco_frequencyfalse
gui_enable_output_counter_cascadingfalse
gui_mif_gen_optionsGenerate New MIF File
gui_new_mif_file_path~/pll.mif
gui_mif_config_nameunnamed
gui_active_clkfalse
gui_clk_badfalse
gui_switchover_modeAutomatic Switchover
gui_switchover_delay0
gui_enable_cascade_outfalse
gui_cascade_outclk_index0
gui_enable_cascade_infalse
gui_enable_permit_calfalse
gui_extclkout_0_sourceC0
gui_extclkout_1_sourceC0
gui_clock_name_globalfalse
gui_clock_name_string0outclk0
gui_clock_name_string1outclk1
gui_clock_name_string2outclk2
gui_clock_name_string3outclk3
gui_clock_name_string4outclk4
gui_clock_name_string5outclk5
gui_clock_name_string6outclk6
gui_clock_name_string7outclk7
gui_clock_name_string8outclk8
gui_clock_name_string9outclk9
gui_clock_name_string10outclk10
gui_clock_name_string11outclk11
gui_clock_name_string12outclk12
gui_clock_name_string13outclk13
gui_clock_name_string14outclk14
gui_clock_name_string15outclk15
gui_clock_name_string16outclk16
gui_clock_name_string17outclk17
gui_divide_factor_c56
gui_divide_factor_c66
gui_divide_factor_c76
gui_divide_factor_c86
gui_divide_factor_c96
gui_divide_factor_c106
gui_divide_factor_c116
gui_divide_factor_c126
gui_divide_factor_c136
gui_divide_factor_c146
gui_divide_factor_c156
gui_divide_factor_c166
gui_divide_factor_c176
gui_cascade_counter5false
gui_cascade_counter6false
gui_cascade_counter7false
gui_cascade_counter8false
gui_cascade_counter9false
gui_cascade_counter10false
gui_cascade_counter11false
gui_cascade_counter12false
gui_cascade_counter13false
gui_cascade_counter14false
gui_cascade_counter15false
gui_cascade_counter16false
gui_cascade_counter17false
gui_output_clock_frequency0200.0
gui_output_clock_frequency1125.0
gui_output_clock_frequency2200.0
gui_output_clock_frequency3125.0
gui_output_clock_frequency4100.0
gui_output_clock_frequency5100.0
gui_output_clock_frequency6100.0
gui_output_clock_frequency7100.0
gui_output_clock_frequency8100.0
gui_output_clock_frequency9100.0
gui_output_clock_frequency10100.0
gui_output_clock_frequency11100.0
gui_output_clock_frequency12100.0
gui_output_clock_frequency13100.0
gui_output_clock_frequency14100.0
gui_output_clock_frequency15100.0
gui_output_clock_frequency16100.0
gui_output_clock_frequency17100.0
gui_output_clock_frequency_ps510000.0
gui_output_clock_frequency_ps610000.0
gui_output_clock_frequency_ps710000.0
gui_output_clock_frequency_ps810000.0
gui_output_clock_frequency_ps910000.0
gui_output_clock_frequency_ps1010000.0
gui_output_clock_frequency_ps1110000.0
gui_output_clock_frequency_ps1210000.0
gui_output_clock_frequency_ps1310000.0
gui_output_clock_frequency_ps1410000.0
gui_output_clock_frequency_ps1510000.0
gui_output_clock_frequency_ps1610000.0
gui_output_clock_frequency_ps1710000.0
gui_actual_output_clock_frequency0200.0
gui_actual_output_clock_frequency1125.0
gui_actual_output_clock_frequency2200.0
gui_actual_output_clock_frequency3125.0
gui_actual_output_clock_frequency4100.0
gui_actual_output_clock_frequency5100.0
gui_actual_output_clock_frequency6100.0
gui_actual_output_clock_frequency7100.0
gui_actual_output_clock_frequency8100.0
gui_actual_output_clock_frequency9100.0
gui_actual_output_clock_frequency10100.0
gui_actual_output_clock_frequency11100.0
gui_actual_output_clock_frequency12100.0
gui_actual_output_clock_frequency13100.0
gui_actual_output_clock_frequency14100.0
gui_actual_output_clock_frequency15100.0
gui_actual_output_clock_frequency16100.0
gui_actual_output_clock_frequency17100.0
gui_actual_output_clock_frequency_range0198.333333,198.412698,198.571429,200.0,201.428571,201.587302
gui_actual_output_clock_frequency_range1114.285714,116.666667,120.0,125.0,127.272727,133.333333
gui_actual_output_clock_frequency_range2125.0,142.857143,166.666667,200.0,250.0,333.333333
gui_actual_output_clock_frequency_range390.909091,100.0,111.111111,125.0,142.857143,166.666667
gui_actual_output_clock_frequency_range476.923077,83.333333,90.909091,100.0,111.111111,125.0
gui_actual_output_clock_frequency_range5100.0
gui_actual_output_clock_frequency_range6100.0
gui_actual_output_clock_frequency_range7100.0
gui_actual_output_clock_frequency_range8100.0
gui_actual_output_clock_frequency_range9100.0
gui_actual_output_clock_frequency_range10100.0
gui_actual_output_clock_frequency_range11100.0
gui_actual_output_clock_frequency_range12100.0
gui_actual_output_clock_frequency_range13100.0
gui_actual_output_clock_frequency_range14100.0
gui_actual_output_clock_frequency_range15100.0
gui_actual_output_clock_frequency_range16100.0
gui_actual_output_clock_frequency_range17100.0
gui_ps_units0ps
gui_ps_units1ps
gui_ps_units2ps
gui_ps_units3degrees
gui_ps_units4ps
gui_ps_units5ps
gui_ps_units6ps
gui_ps_units7ps
gui_ps_units8ps
gui_ps_units9ps
gui_ps_units10ps
gui_ps_units11ps
gui_ps_units12ps
gui_ps_units13ps
gui_ps_units14ps
gui_ps_units15ps
gui_ps_units16ps
gui_ps_units17ps
gui_phase_shift00.0
gui_phase_shift10.0
gui_phase_shift20.0
gui_phase_shift40.0
gui_phase_shift50.0
gui_phase_shift60.0
gui_phase_shift70.0
gui_phase_shift80.0
gui_phase_shift90.0
gui_phase_shift100.0
gui_phase_shift110.0
gui_phase_shift120.0
gui_phase_shift130.0
gui_phase_shift140.0
gui_phase_shift150.0
gui_phase_shift160.0
gui_phase_shift170.0
gui_phase_shift_deg390.0
gui_phase_shift_deg50.0
gui_phase_shift_deg60.0
gui_phase_shift_deg70.0
gui_phase_shift_deg80.0
gui_phase_shift_deg90.0
gui_phase_shift_deg100.0
gui_phase_shift_deg110.0
gui_phase_shift_deg120.0
gui_phase_shift_deg130.0
gui_phase_shift_deg140.0
gui_phase_shift_deg150.0
gui_phase_shift_deg160.0
gui_phase_shift_deg170.0
gui_actual_phase_shift00.0
gui_actual_phase_shift10.0
gui_actual_phase_shift20.0
gui_actual_phase_shift40.0
gui_actual_phase_shift50.0
gui_actual_phase_shift60.0
gui_actual_phase_shift70.0
gui_actual_phase_shift80.0
gui_actual_phase_shift90.0
gui_actual_phase_shift100.0
gui_actual_phase_shift110.0
gui_actual_phase_shift120.0
gui_actual_phase_shift130.0
gui_actual_phase_shift140.0
gui_actual_phase_shift150.0
gui_actual_phase_shift160.0
gui_actual_phase_shift170.0
gui_actual_phase_shift_range00.0,125.0,250.0,375.0,500.0,625.0
gui_actual_phase_shift_range10.0,125.0,250.0,375.0,500.0,625.0
gui_actual_phase_shift_range20.0,125.0,250.0,375.0,500.0,625.0
gui_actual_phase_shift_range40.0,125.0,250.0,375.0,500.0,625.0
gui_actual_phase_shift_range50.0
gui_actual_phase_shift_range60.0
gui_actual_phase_shift_range70.0
gui_actual_phase_shift_range80.0
gui_actual_phase_shift_range90.0
gui_actual_phase_shift_range100.0
gui_actual_phase_shift_range110.0
gui_actual_phase_shift_range120.0
gui_actual_phase_shift_range130.0
gui_actual_phase_shift_range140.0
gui_actual_phase_shift_range150.0
gui_actual_phase_shift_range160.0
gui_actual_phase_shift_range170.0
gui_actual_phase_shift_deg390.0
gui_actual_phase_shift_deg50.0
gui_actual_phase_shift_deg60.0
gui_actual_phase_shift_deg70.0
gui_actual_phase_shift_deg80.0
gui_actual_phase_shift_deg90.0
gui_actual_phase_shift_deg100.0
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gui_actual_phase_shift_deg120.0
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gui_actual_phase_shift_deg150.0
gui_actual_phase_shift_deg160.0
gui_actual_phase_shift_deg170.0
gui_actual_phase_shift_deg_range373.1,78.8,84.4,90.0,95.6,101.2
gui_actual_phase_shift_deg_range50.0
gui_actual_phase_shift_deg_range60.0
gui_actual_phase_shift_deg_range70.0
gui_actual_phase_shift_deg_range80.0
gui_actual_phase_shift_deg_range90.0
gui_actual_phase_shift_deg_range100.0
gui_actual_phase_shift_deg_range110.0
gui_actual_phase_shift_deg_range120.0
gui_actual_phase_shift_deg_range130.0
gui_actual_phase_shift_deg_range140.0
gui_actual_phase_shift_deg_range150.0
gui_actual_phase_shift_deg_range160.0
gui_actual_phase_shift_deg_range170.0
gui_duty_cycle050.0
gui_duty_cycle150.0
gui_duty_cycle250.0
gui_duty_cycle350.0
gui_duty_cycle450.0
gui_duty_cycle550.0
gui_duty_cycle650.0
gui_duty_cycle750.0
gui_duty_cycle850.0
gui_duty_cycle950.0
gui_duty_cycle1050.0
gui_duty_cycle1150.0
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gui_duty_cycle1450.0
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gui_actual_duty_cycle250.0
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gui_actual_duty_cycle1750.0
gui_actual_duty_cycle_range020.0,30.0,40.0,50.0,60.0,70.0
gui_actual_duty_cycle_range131.25,37.5,43.75,50.0,56.25,62.5
gui_actual_duty_cycle_range220.0,30.0,40.0,50.0,60.0,70.0
gui_actual_duty_cycle_range331.25,37.5,43.75,50.0,56.25,62.5
gui_actual_duty_cycle_range435.0,40.0,45.0,50.0,55.0,60.0
gui_actual_duty_cycle_range550.0
gui_actual_duty_cycle_range650.0
gui_actual_duty_cycle_range750.0
gui_actual_duty_cycle_range850.0
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gui_actual_duty_cycle_range1350.0
gui_actual_duty_cycle_range1450.0
gui_actual_duty_cycle_range1550.0
gui_actual_duty_cycle_range1650.0
gui_actual_duty_cycle_range1750.0
parameterTable_namesM-Counter Divide Setting,N-Counter Divide Setting,VCO Frequency,C-Counter-0 Divide Setting,C-Counter-1 Divide Setting,C-Counter-2 Divide Setting,C-Counter-3 Divide Setting,C-Counter-4 Divide Setting,C-Counter-5 Divide Setting,C-Counter-6 Divide Setting,C-Counter-7 Divide Setting,C-Counter-8 Divide Setting,PLL Auto Reset,M-Counter Hi Divide,M-Counter Lo Divide,M-Counter Even Duty Enable,M-Counter Bypass Enable,N-Counter Hi Divide,N-Counter Lo Divide,N-Counter Even Duty Enable,N-Counter Bypass Enable,C-Counter-0 Hi Divide,C-Counter-1 Hi Divide,C-Counter-2 Hi Divide,C-Counter-3 Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control
parameterTable_values10,1,1000.0 MHz,1,5,8,5,8,10,1,1,1,false,5,5,false,false,256,256,false,true,256,3,4,3,4,5,256,256,256,256,2,4,2,4,5,256,256,256,false,true,false,true,false,false,false,false,false,true,false,false,false,false,false,true,true,true,1,1,1,1,3,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting5,pll_bw_res_setting3
mifTable_namesThe MIF file specified does not yet exist
mifTable_values
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.01 seconds
+ + diff --git a/corev_apu/altera/ip/io_pll/io_pll.ipxact b/corev_apu/altera/ip/io_pll/io_pll.ipxact new file mode 100644 index 0000000000..2de31fd02d --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.ipxact @@ -0,0 +1,664 @@ + + + Intel Corporation + io_pll + io_pll + 1.0 + + + refclk + + + + + + + + clk + + + refclk + + + + + + + + + clockRate + Clock rate + 100000000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + input + + + + + + + locked + + + + + + + + export + + + locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + reset + + + + + + + + reset + + + rst + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + ui.blockdiagram.direction + input + + + + + + + outclk0 + + + + + + + + clk + + + outclk_0 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 200000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk1 + + + + + + + + clk + + + outclk_1 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk2 + + + + + + + + clk + + + outclk_2 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 200000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk3 + + + + + + + + clk + + + outclk_3 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk4 + + + + + + + + clk + + + outclk_4 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 100000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + io_pll + + QUARTUS_SYNTH + + + + + + refclk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_0 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_1 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_2 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_3 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_4 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + QUARTUS_SYNTH + + altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.v + verilogSource + false + + io_pll + + + + altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_all_ip_params.tcl + + false + + io_pll + + + + altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_parameters.tcl + + false + + io_pll + + + + altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.sdc + + false + + io_pll + + + + altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl + + false + + io_pll + + + + altera_iopll_1931/synth/agilex_iobank_pll.ipxact + unknown + false + + io_pll + + + + synth/io_pll.v + verilogSource + false + + io_pll + + + + + + + Intel Corporation + io_pll + io_pll + 1.0 + + + + + AUTO_GENERATION_ID + Auto GENERATION_ID + 0 + + + AUTO_UNIQUE_ID + Auto UNIQUE_ID + + + + AUTO_DEVICE_FAMILY + Auto DEVICE_FAMILY + Agilex 7 + + + AUTO_DEVICE + Auto DEVICE + AGFB014R24B2E2V + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 2 + + + AUTO_BOARD + Auto BOARD + default + + + AUTO_REFCLK_CLOCK_RATE + Auto CLOCK_RATE + -1 + + + AUTO_REFCLK_CLOCK_DOMAIN + Auto CLOCK_DOMAIN + -1 + + + AUTO_REFCLK_RESET_DOMAIN + Auto RESET_DOMAIN + -1 + + + + + diff --git a/corev_apu/altera/ip/io_pll/io_pll.ppf b/corev_apu/altera/ip/io_pll/io_pll.ppf new file mode 100644 index 0000000000..9c16a3a4d6 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.ppf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + diff --git a/corev_apu/altera/ip/io_pll/io_pll.qgsimc b/corev_apu/altera/ip/io_pll/io_pll.qgsimc new file mode 100644 index 0000000000..814ea488ce --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.qgsimc @@ -0,0 +1,3328 @@ + + + io_pll + + + + io_pll + 1.0 + io_pll + io_pll + 0 + + + + + iopll_0 + + + + bandwidth_mode + BANDWIDTH_MODE_AUTO + + + c_cnt_bypass_en0 + true + + + c_cnt_bypass_en1 + false + + + c_cnt_bypass_en10 + true + + + c_cnt_bypass_en11 + true + + + c_cnt_bypass_en12 + true + + + c_cnt_bypass_en13 + true + + + c_cnt_bypass_en14 + true + + + c_cnt_bypass_en15 + true + + + c_cnt_bypass_en16 + true + + + c_cnt_bypass_en17 + true + + + c_cnt_bypass_en2 + false + + + c_cnt_bypass_en3 + false + + + c_cnt_bypass_en4 + false + + + c_cnt_bypass_en5 + false + + + c_cnt_bypass_en6 + true + + + c_cnt_bypass_en7 + true + + + c_cnt_bypass_en8 + true + + + c_cnt_bypass_en9 + true + + + c_cnt_hi_div0 + 256 + + + c_cnt_hi_div1 + 3 + + + c_cnt_hi_div10 + 1 + + + c_cnt_hi_div11 + 1 + + + c_cnt_hi_div12 + 1 + + + c_cnt_hi_div13 + 1 + + + c_cnt_hi_div14 + 1 + + + c_cnt_hi_div15 + 1 + + + c_cnt_hi_div16 + 1 + + + c_cnt_hi_div17 + 1 + + + c_cnt_hi_div2 + 4 + + + c_cnt_hi_div3 + 3 + + + c_cnt_hi_div4 + 4 + + + c_cnt_hi_div5 + 5 + + + c_cnt_hi_div6 + 256 + + + c_cnt_hi_div7 + 256 + + + c_cnt_hi_div8 + 256 + + + c_cnt_hi_div9 + 256 + + + c_cnt_in_src0 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src1 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src10 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src11 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src12 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src13 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src14 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src15 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src16 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src17 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src2 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src3 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src4 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src5 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src6 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src7 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src8 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src9 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_lo_div0 + 256 + + + c_cnt_lo_div1 + 2 + + + c_cnt_lo_div10 + 1 + + + c_cnt_lo_div11 + 1 + + + c_cnt_lo_div12 + 1 + + + c_cnt_lo_div13 + 1 + + + c_cnt_lo_div14 + 1 + + + c_cnt_lo_div15 + 1 + + + c_cnt_lo_div16 + 1 + + + c_cnt_lo_div17 + 1 + + + c_cnt_lo_div2 + 4 + + + c_cnt_lo_div3 + 2 + + + c_cnt_lo_div4 + 4 + + + c_cnt_lo_div5 + 5 + + + c_cnt_lo_div6 + 256 + + + c_cnt_lo_div7 + 256 + + + c_cnt_lo_div8 + 256 + + + c_cnt_lo_div9 + 256 + + + c_cnt_odd_div_duty_en0 + false + + + c_cnt_odd_div_duty_en1 + true + + + c_cnt_odd_div_duty_en10 + false + + + c_cnt_odd_div_duty_en11 + false + + + c_cnt_odd_div_duty_en12 + false + + + c_cnt_odd_div_duty_en13 + false + + + c_cnt_odd_div_duty_en14 + false + + + c_cnt_odd_div_duty_en15 + false + + + c_cnt_odd_div_duty_en16 + false + + + c_cnt_odd_div_duty_en17 + false + + + c_cnt_odd_div_duty_en2 + false + + + c_cnt_odd_div_duty_en3 + true + + + c_cnt_odd_div_duty_en4 + false + + + c_cnt_odd_div_duty_en5 + false + + + c_cnt_odd_div_duty_en6 + false + + + c_cnt_odd_div_duty_en7 + false + + + c_cnt_odd_div_duty_en8 + false + + + c_cnt_odd_div_duty_en9 + false + + + c_cnt_ph_mux_prst0 + 0 + + + c_cnt_ph_mux_prst1 + 0 + + + c_cnt_ph_mux_prst10 + 0 + + + c_cnt_ph_mux_prst11 + 0 + + + c_cnt_ph_mux_prst12 + 0 + + + c_cnt_ph_mux_prst13 + 0 + + + c_cnt_ph_mux_prst14 + 0 + + + c_cnt_ph_mux_prst15 + 0 + + + c_cnt_ph_mux_prst16 + 0 + + + c_cnt_ph_mux_prst17 + 0 + + + c_cnt_ph_mux_prst2 + 0 + + + c_cnt_ph_mux_prst3 + 0 + + + c_cnt_ph_mux_prst4 + 0 + + + c_cnt_ph_mux_prst5 + 0 + + + c_cnt_ph_mux_prst6 + 0 + + + c_cnt_ph_mux_prst7 + 0 + + + c_cnt_ph_mux_prst8 + 0 + + + c_cnt_ph_mux_prst9 + 0 + + + c_cnt_prst0 + 1 + + + c_cnt_prst1 + 1 + + + c_cnt_prst10 + 1 + + + c_cnt_prst11 + 1 + + + c_cnt_prst12 + 1 + + + c_cnt_prst13 + 1 + + + c_cnt_prst14 + 1 + + + c_cnt_prst15 + 1 + + + c_cnt_prst16 + 1 + + + c_cnt_prst17 + 1 + + + c_cnt_prst2 + 1 + + + c_cnt_prst3 + 1 + + + c_cnt_prst4 + 3 + + + c_cnt_prst5 + 1 + + + c_cnt_prst6 + 1 + + + c_cnt_prst7 + 1 + + + c_cnt_prst8 + 1 + + + c_cnt_prst9 + 1 + + + cal_code_hex_file + iossm.hex + + + cal_converge + false + + + cal_error + cal_clean + + + cascade_mode + CASCADE_MODE_STANDALONE + + + clock_name_0 + + + + clock_name_1 + outclk0 + + + clock_name_2 + outclk1 + + + clock_name_3 + outclk2 + + + clock_name_4 + outclk3 + + + clock_name_5 + outclk4 + + + clock_name_6 + + + + clock_name_7 + + + + clock_name_8 + + + + clock_name_global + false + + + clock_name_global_0 + false + + + clock_name_global_1 + false + + + clock_name_global_2 + false + + + clock_name_global_3 + false + + + clock_name_global_4 + false + + + clock_name_global_5 + false + + + clock_name_global_6 + false + + + clock_name_global_7 + false + + + clock_name_global_8 + false + + + clock_to_compensate + 1 + + + compensation_clk_source + COMPENSATION_CLK_SOURCE_UNUSED + + + compensation_mode + COMPENSATION_MODE_DIRECT + + + divide_factor0 + 1 + + + divide_factor1 + 1 + + + divide_factor2 + 1 + + + divide_factor3 + 1 + + + divide_factor4 + 1 + + + divide_factor5 + 1 + + + divide_factor6 + 1 + + + divide_factor7 + 1 + + + divide_factor8 + 1 + + + dprio_interface_sel + 3 + + + duty_cycle0 + 50 + + + duty_cycle1 + 50 + + + duty_cycle10 + 50 + + + duty_cycle11 + 50 + + + duty_cycle12 + 50 + + + duty_cycle13 + 50 + + + duty_cycle14 + 50 + + + duty_cycle15 + 50 + + + duty_cycle16 + 50 + + + duty_cycle17 + 50 + + + duty_cycle2 + 50 + + + duty_cycle3 + 50 + + + duty_cycle4 + 50 + + + duty_cycle5 + 50 + + + duty_cycle6 + 50 + + + duty_cycle7 + 50 + + + duty_cycle8 + 50 + + + duty_cycle9 + 50 + + + eff_m_cnt + 1 + + + fb_clk_delay + 0 + + + fb_clk_fractional_div_den + 1 + + + fb_clk_fractional_div_num + 1 + + + fb_clk_fractional_div_value + 1 + + + fb_clk_m_div + 0 + + + fractional_vco_multiplier + false + + + gui_active_clk + false + + + gui_actual_duty_cycle0 + 50.0 + + + gui_actual_duty_cycle1 + 50.0 + + + gui_actual_duty_cycle10 + 50.0 + + + gui_actual_duty_cycle11 + 50.0 + + + gui_actual_duty_cycle12 + 50.0 + + + gui_actual_duty_cycle13 + 50.0 + + + gui_actual_duty_cycle14 + 50.0 + + + gui_actual_duty_cycle15 + 50.0 + + + gui_actual_duty_cycle16 + 50.0 + + + gui_actual_duty_cycle17 + 50.0 + + + gui_actual_duty_cycle2 + 50.0 + + + gui_actual_duty_cycle3 + 50.0 + + + gui_actual_duty_cycle4 + 50.0 + + + gui_actual_duty_cycle5 + 50.0 + + + gui_actual_duty_cycle6 + 50.0 + + + gui_actual_duty_cycle7 + 50.0 + + + gui_actual_duty_cycle8 + 50.0 + + + gui_actual_duty_cycle9 + 50.0 + + + gui_actual_duty_cycle_range0 + 20.0,30.0,40.0,50.0,60.0,70.0 + + + gui_actual_duty_cycle_range1 + 31.25,37.5,43.75,50.0,56.25,62.5 + + + gui_actual_duty_cycle_range10 + 50.0 + + + gui_actual_duty_cycle_range11 + 50.0 + + + gui_actual_duty_cycle_range12 + 50.0 + + + gui_actual_duty_cycle_range13 + 50.0 + + + gui_actual_duty_cycle_range14 + 50.0 + + + gui_actual_duty_cycle_range15 + 50.0 + + + gui_actual_duty_cycle_range16 + 50.0 + + + gui_actual_duty_cycle_range17 + 50.0 + + + gui_actual_duty_cycle_range2 + 20.0,30.0,40.0,50.0,60.0,70.0 + + + gui_actual_duty_cycle_range3 + 31.25,37.5,43.75,50.0,56.25,62.5 + + + gui_actual_duty_cycle_range4 + 35.0,40.0,45.0,50.0,55.0,60.0 + + + gui_actual_duty_cycle_range5 + 50.0 + + + gui_actual_duty_cycle_range6 + 50.0 + + + gui_actual_duty_cycle_range7 + 50.0 + + + gui_actual_duty_cycle_range8 + 50.0 + + + gui_actual_duty_cycle_range9 + 50.0 + + + gui_actual_output_clock_frequency0 + 200.0 + + + gui_actual_output_clock_frequency1 + 125.0 + + + gui_actual_output_clock_frequency10 + 100.0 + + + gui_actual_output_clock_frequency11 + 100.0 + + + gui_actual_output_clock_frequency12 + 100.0 + + + gui_actual_output_clock_frequency13 + 100.0 + + + gui_actual_output_clock_frequency14 + 100.0 + + + gui_actual_output_clock_frequency15 + 100.0 + + + gui_actual_output_clock_frequency16 + 100.0 + + + gui_actual_output_clock_frequency17 + 100.0 + + + gui_actual_output_clock_frequency2 + 200.0 + + + gui_actual_output_clock_frequency3 + 125.0 + + + gui_actual_output_clock_frequency4 + 100.0 + + + gui_actual_output_clock_frequency5 + 100.0 + + + gui_actual_output_clock_frequency6 + 100.0 + + + gui_actual_output_clock_frequency7 + 100.0 + + + gui_actual_output_clock_frequency8 + 100.0 + + + gui_actual_output_clock_frequency9 + 100.0 + + + gui_actual_output_clock_frequency_range0 + 198.333333,198.412698,198.571429,200.0,201.428571,201.587302 + + + gui_actual_output_clock_frequency_range1 + 114.285714,116.666667,120.0,125.0,127.272727,133.333333 + + + gui_actual_output_clock_frequency_range10 + 100.0 + + + gui_actual_output_clock_frequency_range11 + 100.0 + + + gui_actual_output_clock_frequency_range12 + 100.0 + + + gui_actual_output_clock_frequency_range13 + 100.0 + + + gui_actual_output_clock_frequency_range14 + 100.0 + + + gui_actual_output_clock_frequency_range15 + 100.0 + + + gui_actual_output_clock_frequency_range16 + 100.0 + + + gui_actual_output_clock_frequency_range17 + 100.0 + + + gui_actual_output_clock_frequency_range2 + 125.0,142.857143,166.666667,200.0,250.0,333.333333 + + + gui_actual_output_clock_frequency_range3 + 90.909091,100.0,111.111111,125.0,142.857143,166.666667 + + + gui_actual_output_clock_frequency_range4 + 76.923077,83.333333,90.909091,100.0,111.111111,125.0 + + + gui_actual_output_clock_frequency_range5 + 100.0 + + + gui_actual_output_clock_frequency_range6 + 100.0 + + + gui_actual_output_clock_frequency_range7 + 100.0 + + + gui_actual_output_clock_frequency_range8 + 100.0 + + + gui_actual_output_clock_frequency_range9 + 100.0 + + + gui_actual_phase_shift0 + 0.0 + + + gui_actual_phase_shift1 + 0.0 + + + gui_actual_phase_shift10 + 0.0 + + + gui_actual_phase_shift11 + 0.0 + + + gui_actual_phase_shift12 + 0.0 + + + gui_actual_phase_shift13 + 0.0 + + + gui_actual_phase_shift14 + 0.0 + + + gui_actual_phase_shift15 + 0.0 + + + gui_actual_phase_shift16 + 0.0 + + + gui_actual_phase_shift17 + 0.0 + + + gui_actual_phase_shift2 + 0.0 + + + gui_actual_phase_shift3 + 2000.0 + + + gui_actual_phase_shift4 + 0.0 + + + gui_actual_phase_shift5 + 0.0 + + + gui_actual_phase_shift6 + 0.0 + + + gui_actual_phase_shift7 + 0.0 + + + gui_actual_phase_shift8 + 0.0 + + + gui_actual_phase_shift9 + 0.0 + + + gui_actual_phase_shift_deg0 + 0.0 + + + gui_actual_phase_shift_deg1 + 0.0 + + + gui_actual_phase_shift_deg10 + 0.0 + + + gui_actual_phase_shift_deg11 + 0.0 + + + gui_actual_phase_shift_deg12 + 0.0 + + + gui_actual_phase_shift_deg13 + 0.0 + + + gui_actual_phase_shift_deg14 + 0.0 + + + gui_actual_phase_shift_deg15 + 0.0 + + + gui_actual_phase_shift_deg16 + 0.0 + + + gui_actual_phase_shift_deg17 + 0.0 + + + gui_actual_phase_shift_deg2 + 0.0 + + + gui_actual_phase_shift_deg3 + 90.0 + + + gui_actual_phase_shift_deg4 + 0.0 + + + gui_actual_phase_shift_deg5 + 0.0 + + + gui_actual_phase_shift_deg6 + 0.0 + + + gui_actual_phase_shift_deg7 + 0.0 + + + gui_actual_phase_shift_deg8 + 0.0 + + + gui_actual_phase_shift_deg9 + 0.0 + + + gui_actual_phase_shift_deg_range0 + 0.0,9.0,18.0,27.0,36.0,45.0 + + + gui_actual_phase_shift_deg_range1 + 0.0,5.6,11.2,16.9,22.5,28.1 + + + gui_actual_phase_shift_deg_range10 + 0.0 + + + gui_actual_phase_shift_deg_range11 + 0.0 + + + gui_actual_phase_shift_deg_range12 + 0.0 + + + gui_actual_phase_shift_deg_range13 + 0.0 + + + gui_actual_phase_shift_deg_range14 + 0.0 + + + gui_actual_phase_shift_deg_range15 + 0.0 + + + gui_actual_phase_shift_deg_range16 + 0.0 + + + gui_actual_phase_shift_deg_range17 + 0.0 + + + gui_actual_phase_shift_deg_range2 + 0.0,9.0,18.0,27.0,36.0,45.0 + + + gui_actual_phase_shift_deg_range3 + 73.1,78.8,84.4,90.0,95.6,101.2 + + + gui_actual_phase_shift_deg_range4 + 0.0,4.5,9.0,13.5,18.0,22.5 + + + gui_actual_phase_shift_deg_range5 + 0.0 + + + gui_actual_phase_shift_deg_range6 + 0.0 + + + gui_actual_phase_shift_deg_range7 + 0.0 + + + gui_actual_phase_shift_deg_range8 + 0.0 + + + gui_actual_phase_shift_deg_range9 + 0.0 + + + gui_actual_phase_shift_range0 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range1 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range10 + 0.0 + + + gui_actual_phase_shift_range11 + 0.0 + + + gui_actual_phase_shift_range12 + 0.0 + + + gui_actual_phase_shift_range13 + 0.0 + + + gui_actual_phase_shift_range14 + 0.0 + + + gui_actual_phase_shift_range15 + 0.0 + + + gui_actual_phase_shift_range16 + 0.0 + + + gui_actual_phase_shift_range17 + 0.0 + + + gui_actual_phase_shift_range2 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range3 + 1625.0,1750.0,1875.0,2000.0,2125.0,2250.0 + + + gui_actual_phase_shift_range4 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range5 + 0.0 + + + gui_actual_phase_shift_range6 + 0.0 + + + gui_actual_phase_shift_range7 + 0.0 + + + gui_actual_phase_shift_range8 + 0.0 + + + gui_actual_phase_shift_range9 + 0.0 + + + gui_c_cnt_in_src0 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src1 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src2 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src3 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src4 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src5 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src6 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src7 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src8 + c_m_cnt_in_src_ph_mux_clk + + + gui_cal_code_hex_file + iossm.hex + + + gui_cal_converge + false + + + gui_cal_error + cal_clean + + + gui_cascade_counter0 + false + + + gui_cascade_counter1 + false + + + gui_cascade_counter10 + false + + + gui_cascade_counter11 + false + + + gui_cascade_counter12 + false + + + gui_cascade_counter13 + false + + + gui_cascade_counter14 + false + + + gui_cascade_counter15 + false + + + gui_cascade_counter16 + false + + + gui_cascade_counter17 + false + + + gui_cascade_counter2 + false + + + gui_cascade_counter3 + false + + + gui_cascade_counter4 + false + + + gui_cascade_counter5 + false + + + gui_cascade_counter6 + false + + + gui_cascade_counter7 + false + + + gui_cascade_counter8 + false + + + gui_cascade_counter9 + false + + + gui_cascade_outclk_index + 0 + + + gui_clk_bad + false + + + gui_clock_name_global + false + + + gui_clock_name_string0 + outclk0 + + + gui_clock_name_string1 + outclk1 + + + gui_clock_name_string10 + outclk10 + + + gui_clock_name_string11 + outclk11 + + + gui_clock_name_string12 + outclk12 + + + gui_clock_name_string13 + outclk13 + + + gui_clock_name_string14 + outclk14 + + + gui_clock_name_string15 + outclk15 + + + gui_clock_name_string16 + outclk16 + + + gui_clock_name_string17 + outclk17 + + + gui_clock_name_string2 + outclk2 + + + gui_clock_name_string3 + outclk3 + + + gui_clock_name_string4 + outclk4 + + + gui_clock_name_string5 + outclk5 + + + gui_clock_name_string6 + outclk6 + + + gui_clock_name_string7 + outclk7 + + + gui_clock_name_string8 + outclk8 + + + gui_clock_name_string9 + outclk9 + + + gui_clock_to_compensate + 0 + + + gui_debug_mode + false + + + gui_device_component + AGFB014R24B2E2V + + + gui_device_family + Agilex 7 + + + gui_device_iobank_rev + IO96A_REVB2 + + + gui_device_speed_grade + 2 + + + gui_divide_factor_c0 + 1 + + + gui_divide_factor_c1 + 25 + + + gui_divide_factor_c10 + 6 + + + gui_divide_factor_c11 + 6 + + + gui_divide_factor_c12 + 6 + + + gui_divide_factor_c13 + 6 + + + gui_divide_factor_c14 + 6 + + + gui_divide_factor_c15 + 6 + + + gui_divide_factor_c16 + 6 + + + gui_divide_factor_c17 + 6 + + + gui_divide_factor_c2 + 25 + + + gui_divide_factor_c3 + 6 + + + gui_divide_factor_c4 + 6 + + + gui_divide_factor_c5 + 6 + + + gui_divide_factor_c6 + 6 + + + gui_divide_factor_c7 + 6 + + + gui_divide_factor_c8 + 6 + + + gui_divide_factor_c9 + 6 + + + gui_divide_factor_n + 6 + + + gui_dps_cntr + C0 + + + gui_dps_dir + Positive + + + gui_dps_num + 1 + + + gui_dsm_out_sel + 1st_order + + + gui_duty_cycle0 + 50.0 + + + gui_duty_cycle1 + 50.0 + + + gui_duty_cycle10 + 50.0 + + + gui_duty_cycle11 + 50.0 + + + gui_duty_cycle12 + 50.0 + + + gui_duty_cycle13 + 50.0 + + + gui_duty_cycle14 + 50.0 + + + gui_duty_cycle15 + 50.0 + + + gui_duty_cycle16 + 50.0 + + + gui_duty_cycle17 + 50.0 + + + gui_duty_cycle2 + 50.0 + + + gui_duty_cycle3 + 50.0 + + + gui_duty_cycle4 + 50.0 + + + gui_duty_cycle5 + 50.0 + + + gui_duty_cycle6 + 50.0 + + + gui_duty_cycle7 + 50.0 + + + gui_duty_cycle8 + 50.0 + + + gui_duty_cycle9 + 50.0 + + + gui_en_adv_params + false + + + gui_en_dps_ports + false + + + gui_en_extclkout_ports + false + + + gui_en_iossm_reconf + false + + + gui_en_lvds_ports + Disabled + + + gui_en_periphery_ports + false + + + gui_en_phout_ports + false + + + gui_en_reconf + false + + + gui_enable_cascade_in + false + + + gui_enable_cascade_out + false + + + gui_enable_mif_dps + false + + + gui_enable_output_counter_cascading + false + + + gui_enable_permit_cal + false + + + gui_enable_upstream_out_clk + false + + + gui_existing_mif_file_path + ~/pll.mif + + + gui_extclkout_0_source + C0 + + + gui_extclkout_1_source + C0 + + + gui_extclkout_source + C0 + + + gui_feedback_clock + Global Clock + + + gui_fix_vco_frequency + false + + + gui_fixed_vco_frequency + 600.0 + + + gui_fixed_vco_frequency_ps + 1667.0 + + + gui_frac_multiply_factor + 1 + + + gui_fractional_cout + 32 + + + gui_include_iossm + false + + + gui_location_type + I/O Bank + + + gui_lock_setting + Low Lock Time + + + gui_mif_config_name + unnamed + + + gui_mif_gen_options + Generate New MIF File + + + gui_multiply_factor + 25 + + + gui_new_mif_file_path + ~/pll.mif + + + gui_number_of_clocks + 5 + + + gui_operation_mode + direct + + + gui_output_clock_frequency0 + 200.0 + + + gui_output_clock_frequency1 + 125.0 + + + gui_output_clock_frequency10 + 100.0 + + + gui_output_clock_frequency11 + 100.0 + + + gui_output_clock_frequency12 + 100.0 + + + gui_output_clock_frequency13 + 100.0 + + + gui_output_clock_frequency14 + 100.0 + + + gui_output_clock_frequency15 + 100.0 + + + gui_output_clock_frequency16 + 100.0 + + + gui_output_clock_frequency17 + 100.0 + + + gui_output_clock_frequency2 + 200.0 + + + gui_output_clock_frequency3 + 125.0 + + + gui_output_clock_frequency4 + 100.0 + + + gui_output_clock_frequency5 + 100.0 + + + gui_output_clock_frequency6 + 100.0 + + + gui_output_clock_frequency7 + 100.0 + + + gui_output_clock_frequency8 + 100.0 + + + gui_output_clock_frequency9 + 100.0 + + + gui_output_clock_frequency_ps0 + 5000.0 + + + gui_output_clock_frequency_ps1 + 8000.0 + + + gui_output_clock_frequency_ps10 + 10000.0 + + + gui_output_clock_frequency_ps11 + 10000.0 + + + gui_output_clock_frequency_ps12 + 10000.0 + + + gui_output_clock_frequency_ps13 + 10000.0 + + + gui_output_clock_frequency_ps14 + 10000.0 + + + gui_output_clock_frequency_ps15 + 10000.0 + + + gui_output_clock_frequency_ps16 + 10000.0 + + + gui_output_clock_frequency_ps17 + 10000.0 + + + gui_output_clock_frequency_ps2 + 5000.0 + + + gui_output_clock_frequency_ps3 + 8000.0 + + + gui_output_clock_frequency_ps4 + 10000.0 + + + gui_output_clock_frequency_ps5 + 10000.0 + + + gui_output_clock_frequency_ps6 + 10000.0 + + + gui_output_clock_frequency_ps7 + 10000.0 + + + gui_output_clock_frequency_ps8 + 10000.0 + + + gui_output_clock_frequency_ps9 + 10000.0 + + + gui_parameter_table_hex_file + seq_params_sim.hex + + + gui_phase_shift0 + 0.0 + + + gui_phase_shift1 + 0.0 + + + gui_phase_shift10 + 0.0 + + + gui_phase_shift11 + 0.0 + + + gui_phase_shift12 + 0.0 + + + gui_phase_shift13 + 0.0 + + + gui_phase_shift14 + 0.0 + + + gui_phase_shift15 + 0.0 + + + gui_phase_shift16 + 0.0 + + + gui_phase_shift17 + 0.0 + + + gui_phase_shift2 + 0.0 + + + gui_phase_shift3 + 0.0 + + + gui_phase_shift4 + 0.0 + + + gui_phase_shift5 + 0.0 + + + gui_phase_shift6 + 0.0 + + + gui_phase_shift7 + 0.0 + + + gui_phase_shift8 + 0.0 + + + gui_phase_shift9 + 0.0 + + + gui_phase_shift_deg0 + 0.0 + + + gui_phase_shift_deg1 + 0.0 + + + gui_phase_shift_deg10 + 0.0 + + + gui_phase_shift_deg11 + 0.0 + + + gui_phase_shift_deg12 + 0.0 + + + gui_phase_shift_deg13 + 0.0 + + + gui_phase_shift_deg14 + 0.0 + + + gui_phase_shift_deg15 + 0.0 + + + gui_phase_shift_deg16 + 0.0 + + + gui_phase_shift_deg17 + 0.0 + + + gui_phase_shift_deg2 + 0.0 + + + gui_phase_shift_deg3 + 90.0 + + + gui_phase_shift_deg4 + 0.0 + + + gui_phase_shift_deg5 + 0.0 + + + gui_phase_shift_deg6 + 0.0 + + + gui_phase_shift_deg7 + 0.0 + + + gui_phase_shift_deg8 + 0.0 + + + gui_phase_shift_deg9 + 0.0 + + + gui_phout_division + 1 + + + gui_pll_auto_reset + false + + + gui_pll_bandwidth_preset + Medium + + + gui_pll_cal_done + false + + + gui_pll_cascading_mode + adjpllin + + + gui_pll_freqcal_en + true + + + gui_pll_freqcal_req_flag + true + + + gui_pll_m_cnt_in_src + c_m_cnt_in_src_ph_mux_clk + + + gui_pll_mode + Integer-N PLL + + + gui_pll_tclk_mux_en + false + + + gui_pll_tclk_sel + pll_tclk_m_src + + + gui_pll_type + S10_Simple + + + gui_pll_vco_freq_band_0 + pll_freq_clk0_band18 + + + gui_pll_vco_freq_band_1 + pll_freq_clk1_band18 + + + gui_prot_mode + UNUSED + + + gui_ps_units0 + ps + + + gui_ps_units1 + ps + + + gui_ps_units10 + ps + + + gui_ps_units11 + ps + + + gui_ps_units12 + ps + + + gui_ps_units13 + ps + + + gui_ps_units14 + ps + + + gui_ps_units15 + ps + + + gui_ps_units16 + ps + + + gui_ps_units17 + ps + + + gui_ps_units2 + ps + + + gui_ps_units3 + degrees + + + gui_ps_units4 + ps + + + gui_ps_units5 + ps + + + gui_ps_units6 + ps + + + gui_ps_units7 + ps + + + gui_ps_units8 + ps + + + gui_ps_units9 + ps + + + gui_refclk1_frequency + 100.0 + + + gui_refclk_might_change + false + + + gui_refclk_switch + false + + + gui_reference_clock_frequency + 100.0 + + + gui_reference_clock_frequency_ps + 10000.0 + + + gui_simulation_type + false + + + gui_skip_sdc_generation + false + + + gui_switchover_delay + 0 + + + gui_switchover_mode + Automatic Switchover + + + gui_use_NDFB_modes + false + + + gui_use_coreclk + true + + + gui_use_locked + true + + + gui_use_logical + false + + + gui_user_base_address + 0 + + + gui_usr_device_speed_grade + 1 + + + gui_vco_frequency + 1250.0 + + + hp_actual_duty_cycle_fp0 + 50.0 + + + hp_actual_duty_cycle_fp1 + 50.0 + + + hp_actual_duty_cycle_fp10 + 50.0 + + + hp_actual_duty_cycle_fp11 + 50.0 + + + hp_actual_duty_cycle_fp12 + 50.0 + + + hp_actual_duty_cycle_fp13 + 50.0 + + + hp_actual_duty_cycle_fp14 + 50.0 + + + hp_actual_duty_cycle_fp15 + 50.0 + + + hp_actual_duty_cycle_fp16 + 50.0 + + + hp_actual_duty_cycle_fp17 + 50.0 + + + hp_actual_duty_cycle_fp2 + 50.0 + + + hp_actual_duty_cycle_fp3 + 50.0 + + + hp_actual_duty_cycle_fp4 + 50.0 + + + hp_actual_duty_cycle_fp5 + 50.0 + + + hp_actual_duty_cycle_fp6 + 50.0 + + + hp_actual_duty_cycle_fp7 + 50.0 + + + hp_actual_duty_cycle_fp8 + 50.0 + + + hp_actual_duty_cycle_fp9 + 50.0 + + + hp_actual_output_clock_frequency_fp0 + 200.0 + + + hp_actual_output_clock_frequency_fp1 + 125.0 + + + hp_actual_output_clock_frequency_fp10 + 100.0 + + + hp_actual_output_clock_frequency_fp11 + 100.0 + + + hp_actual_output_clock_frequency_fp12 + 100.0 + + + hp_actual_output_clock_frequency_fp13 + 100.0 + + + hp_actual_output_clock_frequency_fp14 + 100.0 + + + hp_actual_output_clock_frequency_fp15 + 100.0 + + + hp_actual_output_clock_frequency_fp16 + 100.0 + + + hp_actual_output_clock_frequency_fp17 + 100.0 + + + hp_actual_output_clock_frequency_fp2 + 200.0 + + + hp_actual_output_clock_frequency_fp3 + 125.0 + + + hp_actual_output_clock_frequency_fp4 + 100.0 + + + hp_actual_output_clock_frequency_fp5 + 100.0 + + + hp_actual_output_clock_frequency_fp6 + 100.0 + + + hp_actual_output_clock_frequency_fp7 + 100.0 + + + hp_actual_output_clock_frequency_fp8 + 100.0 + + + hp_actual_output_clock_frequency_fp9 + 100.0 + + + hp_actual_phase_shift_fp0 + 0.0 + + + hp_actual_phase_shift_fp1 + 0.0 + + + hp_actual_phase_shift_fp10 + 0.0 + + + hp_actual_phase_shift_fp11 + 0.0 + + + hp_actual_phase_shift_fp12 + 0.0 + + + hp_actual_phase_shift_fp13 + 0.0 + + + hp_actual_phase_shift_fp14 + 0.0 + + + hp_actual_phase_shift_fp15 + 0.0 + + + hp_actual_phase_shift_fp16 + 0.0 + + + hp_actual_phase_shift_fp17 + 0.0 + + + hp_actual_phase_shift_fp2 + 0.0 + + + hp_actual_phase_shift_fp3 + 2000.0 + + + hp_actual_phase_shift_fp4 + 0.0 + + + hp_actual_phase_shift_fp5 + 0.0 + + + hp_actual_phase_shift_fp6 + 0.0 + + + hp_actual_phase_shift_fp7 + 0.0 + + + hp_actual_phase_shift_fp8 + 0.0 + + + hp_actual_phase_shift_fp9 + 0.0 + + + hp_actual_vco_frequency_fp + 600.0 + + + hp_number_of_family_allowable_clocks + 9 + + + hp_parameter_update_message + + + + hp_previous_num_clocks + 1 + + + hp_qsys_scripting_mode + false + + + include_iossm + false + + + iossm_nios_sim_clk_period_ps + 1333 + + + lock_mode + low_lock_time + + + m_cnt_bypass_en + false + + + m_cnt_hi_div + 5 + + + m_cnt_lo_div + 5 + + + m_cnt_odd_div_duty_en + false + + + merging_permitted + false + + + mifTable_names + The MIF file specified does not yet exist + + + mifTable_values + + + + mimic_fbclk_type + gclk + + + multiply_factor + 10 + + + n_cnt_bypass_en + true + + + n_cnt_hi_div + 256 + + + n_cnt_lo_div + 256 + + + n_cnt_odd_div_duty_en + false + + + number_of_clocks + 5 + + + number_of_outclks + 5 + + + operation_mode + direct + + + out_clk_0_c_div + 1 + + + out_clk_0_core_en + true + + + out_clk_0_delay + 0 + + + out_clk_0_dutycycle_den + 2 + + + out_clk_0_dutycycle_num + 1 + + + out_clk_0_freq + 1000000000 + + + out_clk_0_phase_ps + 1000000000 + + + out_clk_0_phase_shifts + 0 + + + out_clk_1_c_div + 1 + + + out_clk_1_core_en + true + + + out_clk_1_delay + 0 + + + out_clk_1_dutycycle_den + 2 + + + out_clk_1_dutycycle_num + 1 + + + out_clk_1_freq + 1000000000 + + + out_clk_1_phase_ps + 1000000000 + + + out_clk_1_phase_shifts + 0 + + + out_clk_2_c_div + 1 + + + out_clk_2_core_en + true + + + out_clk_2_delay + 0 + + + out_clk_2_dutycycle_den + 2 + + + out_clk_2_dutycycle_num + 1 + + + out_clk_2_freq + 1000000000 + + + out_clk_2_phase_ps + 1000000000 + + + out_clk_2_phase_shifts + 0 + + + out_clk_3_c_div + 1 + + + out_clk_3_core_en + true + + + out_clk_3_delay + 0 + + + out_clk_3_dutycycle_den + 2 + + + out_clk_3_dutycycle_num + 1 + + + out_clk_3_freq + 1000000000 + + + out_clk_3_phase_ps + 1000000000 + + + out_clk_3_phase_shifts + 0 + + + out_clk_4_c_div + 1 + + + out_clk_4_core_en + true + + + out_clk_4_delay + 0 + + + out_clk_4_dutycycle_den + 2 + + + out_clk_4_dutycycle_num + 1 + + + out_clk_4_freq + 1000000000 + + + out_clk_4_phase_ps + 1000000000 + + + out_clk_4_phase_shifts + 0 + + + out_clk_5_c_div + 1 + + + out_clk_5_core_en + true + + + out_clk_5_delay + 0 + + + out_clk_5_dutycycle_den + 2 + + + out_clk_5_dutycycle_num + 1 + + + out_clk_5_freq + 1000000000 + + + out_clk_5_phase_ps + 1000000000 + + + out_clk_5_phase_shifts + 0 + + + out_clk_6_c_div + 1 + + + out_clk_6_core_en + true + + + out_clk_6_delay + 0 + + + out_clk_6_dutycycle_den + 2 + + + out_clk_6_dutycycle_num + 1 + + + out_clk_6_freq + 1000000000 + + + out_clk_6_phase_ps + 1000000000 + + + out_clk_6_phase_shifts + 0 + + + out_clk_cascading_source + OUT_CLK_CASCADING_SOURCE_UNUSED + + + out_clk_external_0_source + OUT_CLK_EXTERNAL_0_SOURCE_UNUSED + + + out_clk_external_1_source + OUT_CLK_EXTERNAL_1_SOURCE_UNUSED + + + out_clk_periph_0_delay + 0 + + + out_clk_periph_0_en + true + + + out_clk_periph_1_delay + 0 + + + out_clk_periph_1_en + true + + + output_clock_frequency0 + 0 ps + + + output_clock_frequency1 + 200.0 MHz + + + output_clock_frequency10 + 0 MHz + + + output_clock_frequency11 + 0 MHz + + + output_clock_frequency12 + 0 MHz + + + output_clock_frequency13 + 0 MHz + + + output_clock_frequency14 + 0 MHz + + + output_clock_frequency15 + 0 MHz + + + output_clock_frequency16 + 0 MHz + + + output_clock_frequency17 + 0 MHz + + + output_clock_frequency2 + 125.0 MHz + + + output_clock_frequency3 + 200.0 MHz + + + output_clock_frequency4 + 125.0 MHz + + + output_clock_frequency5 + 100.0 MHz + + + output_clock_frequency6 + 0 ps + + + output_clock_frequency7 + 0 ps + + + output_clock_frequency8 + 0 ps + + + output_clock_frequency9 + 0 ps + + + parameterTable_names + M-Counter Divide Setting,N-Counter Divide Setting,VCO Frequency,C-Counter-0 Divide Setting,C-Counter-1 Divide Setting,C-Counter-2 Divide Setting,C-Counter-3 Divide Setting,C-Counter-4 Divide Setting,C-Counter-5 Divide Setting,C-Counter-6 Divide Setting,C-Counter-7 Divide Setting,C-Counter-8 Divide Setting,PLL Auto Reset,M-Counter Hi Divide,M-Counter Lo Divide,M-Counter Even Duty Enable,M-Counter Bypass Enable,N-Counter Hi Divide,N-Counter Lo Divide,N-Counter Even Duty Enable,N-Counter Bypass Enable,C-Counter-0 Hi Divide,C-Counter-1 Hi Divide,C-Counter-2 Hi Divide,C-Counter-3 Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control + + + parameterTable_values + 10,1,1000.0 MHz,1,5,8,5,8,10,1,1,1,false,5,5,false,false,256,256,false,true,256,3,4,3,4,5,256,256,256,256,2,4,2,4,5,256,256,256,false,true,false,true,false,false,false,false,false,true,false,false,false,false,false,true,true,true,1,1,1,1,3,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting5,pll_bw_res_setting3 + + + parameter_table_hex_file + seq_params_sim.hex + + + pfd_clk_freq + 100000000 + + + phase_shift0 + 0 ps + + + phase_shift1 + 0 ps + + + phase_shift10 + 0 ps + + + phase_shift11 + 0 ps + + + phase_shift12 + 0 ps + + + phase_shift13 + 0 ps + + + phase_shift14 + 0 ps + + + phase_shift15 + 0 ps + + + phase_shift16 + 0 ps + + + phase_shift17 + 0 ps + + + phase_shift2 + 0 ps + + + phase_shift3 + 0 ps + + + phase_shift4 + 2000 ps + + + phase_shift5 + 0 ps + + + phase_shift6 + 0 ps + + + phase_shift7 + 0 ps + + + phase_shift8 + 0 ps + + + phase_shift9 + 0 ps + + + pll_auto_clk_sw_en + false + + + pll_bw_sel + mid_bw + + + pll_bwctrl + pll_bw_res_setting3 + + + pll_cal_done + false + + + pll_clk_loss_sw_en + false + + + pll_clk_sw_dly + 0 + + + pll_clkin_0_src + coreclkin + + + pll_clkin_1_src + ioclkin_0 + + + pll_cp_current + pll_cp_setting5 + + + pll_defer_cal_user_mode + true + + + pll_dsm_out_sel + 1st_order + + + pll_extclk_0_cnt_src + pll_extclk_cnt_src_vss + + + pll_extclk_1_cnt_src + pll_extclk_cnt_src_vss + + + pll_fbclk_mux_1 + pll_fbclk_mux_1_glb + + + pll_fbclk_mux_2 + pll_fbclk_mux_2_m_cnt + + + pll_fractional_cout + 1 + + + pll_fractional_division + 1 + + + pll_freqcal_en + true + + + pll_freqcal_req_flag + true + + + pll_lock_fltr_cfg + 100 + + + pll_m_cnt + 1 + + + pll_m_cnt_basic + 1 + + + pll_m_cnt_in_src + c_m_cnt_in_src_ph_mux_clk + + + pll_manu_clk_sw_en + false + + + pll_output_clk_frequency + 1000.0 MHz + + + pll_pfd_frequency + 100.0 MHz + + + pll_ripplecap_ctrl + pll_ripplecap_setting1 + + + pll_slf_rst + false + + + pll_subtype + General + + + pll_tclk_mux_en + false + + + pll_tclk_sel + pll_tclk_m_src + + + pll_type + TOP_BOTTOM + + + pll_unlock_fltr_cfg + 2 + + + pll_vco_div + 1 + + + pll_vco_freq_band_0 + pll_freq_clk0_band18 + + + pll_vco_freq_band_1 + pll_freq_clk1_band18 + + + pll_vcoph_div + 1 + + + prot_mode + BASIC + + + protocol_mode + PROTOCOL_MODE_BASIC + + + ref_clk_0_freq + 100000000 + + + ref_clk_1_freq + 100000000 + + + ref_clk_delay + 0 + + + ref_clk_n_div + 1 + + + refclk1_frequency + 0 MHz + + + reference_clock_frequency + 100.0 MHz + + + set_dutycycle + SET_DUTYCYCLE_FRACTION + + + set_fractional + SET_FRACTIONAL_FRACTION + + + set_freq + SET_FREQ_DIVISION + + + set_phase + SET_PHASE_NUM_SHIFTS + + + system_info_device_component + AGFB014R24B2E2V + + + system_info_device_family + Agilex 7 + + + system_info_device_iobank_rev + + + + system_info_device_speed_grade + 2 + + + system_part_trait_iobank_rev + IO96A_REVB2 + + + system_part_trait_speed_grade + 2 + + + use_core_refclk + true + + + vco_clk_freq + 1000000000 + + + + altera_iopll + 19.3.1 + iopll_0 + io_pll_altera_iopll_1931_oypl3jq + 0 + + io_pll.iopll_0 + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/io_pll/io_pll.qgsynthc b/corev_apu/altera/ip/io_pll/io_pll.qgsynthc new file mode 100644 index 0000000000..814ea488ce --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.qgsynthc @@ -0,0 +1,3328 @@ + + + io_pll + + + + io_pll + 1.0 + io_pll + io_pll + 0 + + + + + iopll_0 + + + + bandwidth_mode + BANDWIDTH_MODE_AUTO + + + c_cnt_bypass_en0 + true + + + c_cnt_bypass_en1 + false + + + c_cnt_bypass_en10 + true + + + c_cnt_bypass_en11 + true + + + c_cnt_bypass_en12 + true + + + c_cnt_bypass_en13 + true + + + c_cnt_bypass_en14 + true + + + c_cnt_bypass_en15 + true + + + c_cnt_bypass_en16 + true + + + c_cnt_bypass_en17 + true + + + c_cnt_bypass_en2 + false + + + c_cnt_bypass_en3 + false + + + c_cnt_bypass_en4 + false + + + c_cnt_bypass_en5 + false + + + c_cnt_bypass_en6 + true + + + c_cnt_bypass_en7 + true + + + c_cnt_bypass_en8 + true + + + c_cnt_bypass_en9 + true + + + c_cnt_hi_div0 + 256 + + + c_cnt_hi_div1 + 3 + + + c_cnt_hi_div10 + 1 + + + c_cnt_hi_div11 + 1 + + + c_cnt_hi_div12 + 1 + + + c_cnt_hi_div13 + 1 + + + c_cnt_hi_div14 + 1 + + + c_cnt_hi_div15 + 1 + + + c_cnt_hi_div16 + 1 + + + c_cnt_hi_div17 + 1 + + + c_cnt_hi_div2 + 4 + + + c_cnt_hi_div3 + 3 + + + c_cnt_hi_div4 + 4 + + + c_cnt_hi_div5 + 5 + + + c_cnt_hi_div6 + 256 + + + c_cnt_hi_div7 + 256 + + + c_cnt_hi_div8 + 256 + + + c_cnt_hi_div9 + 256 + + + c_cnt_in_src0 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src1 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src10 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src11 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src12 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src13 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src14 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src15 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src16 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src17 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src2 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src3 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src4 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src5 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src6 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src7 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src8 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_in_src9 + c_m_cnt_in_src_ph_mux_clk + + + c_cnt_lo_div0 + 256 + + + c_cnt_lo_div1 + 2 + + + c_cnt_lo_div10 + 1 + + + c_cnt_lo_div11 + 1 + + + c_cnt_lo_div12 + 1 + + + c_cnt_lo_div13 + 1 + + + c_cnt_lo_div14 + 1 + + + c_cnt_lo_div15 + 1 + + + c_cnt_lo_div16 + 1 + + + c_cnt_lo_div17 + 1 + + + c_cnt_lo_div2 + 4 + + + c_cnt_lo_div3 + 2 + + + c_cnt_lo_div4 + 4 + + + c_cnt_lo_div5 + 5 + + + c_cnt_lo_div6 + 256 + + + c_cnt_lo_div7 + 256 + + + c_cnt_lo_div8 + 256 + + + c_cnt_lo_div9 + 256 + + + c_cnt_odd_div_duty_en0 + false + + + c_cnt_odd_div_duty_en1 + true + + + c_cnt_odd_div_duty_en10 + false + + + c_cnt_odd_div_duty_en11 + false + + + c_cnt_odd_div_duty_en12 + false + + + c_cnt_odd_div_duty_en13 + false + + + c_cnt_odd_div_duty_en14 + false + + + c_cnt_odd_div_duty_en15 + false + + + c_cnt_odd_div_duty_en16 + false + + + c_cnt_odd_div_duty_en17 + false + + + c_cnt_odd_div_duty_en2 + false + + + c_cnt_odd_div_duty_en3 + true + + + c_cnt_odd_div_duty_en4 + false + + + c_cnt_odd_div_duty_en5 + false + + + c_cnt_odd_div_duty_en6 + false + + + c_cnt_odd_div_duty_en7 + false + + + c_cnt_odd_div_duty_en8 + false + + + c_cnt_odd_div_duty_en9 + false + + + c_cnt_ph_mux_prst0 + 0 + + + c_cnt_ph_mux_prst1 + 0 + + + c_cnt_ph_mux_prst10 + 0 + + + c_cnt_ph_mux_prst11 + 0 + + + c_cnt_ph_mux_prst12 + 0 + + + c_cnt_ph_mux_prst13 + 0 + + + c_cnt_ph_mux_prst14 + 0 + + + c_cnt_ph_mux_prst15 + 0 + + + c_cnt_ph_mux_prst16 + 0 + + + c_cnt_ph_mux_prst17 + 0 + + + c_cnt_ph_mux_prst2 + 0 + + + c_cnt_ph_mux_prst3 + 0 + + + c_cnt_ph_mux_prst4 + 0 + + + c_cnt_ph_mux_prst5 + 0 + + + c_cnt_ph_mux_prst6 + 0 + + + c_cnt_ph_mux_prst7 + 0 + + + c_cnt_ph_mux_prst8 + 0 + + + c_cnt_ph_mux_prst9 + 0 + + + c_cnt_prst0 + 1 + + + c_cnt_prst1 + 1 + + + c_cnt_prst10 + 1 + + + c_cnt_prst11 + 1 + + + c_cnt_prst12 + 1 + + + c_cnt_prst13 + 1 + + + c_cnt_prst14 + 1 + + + c_cnt_prst15 + 1 + + + c_cnt_prst16 + 1 + + + c_cnt_prst17 + 1 + + + c_cnt_prst2 + 1 + + + c_cnt_prst3 + 1 + + + c_cnt_prst4 + 3 + + + c_cnt_prst5 + 1 + + + c_cnt_prst6 + 1 + + + c_cnt_prst7 + 1 + + + c_cnt_prst8 + 1 + + + c_cnt_prst9 + 1 + + + cal_code_hex_file + iossm.hex + + + cal_converge + false + + + cal_error + cal_clean + + + cascade_mode + CASCADE_MODE_STANDALONE + + + clock_name_0 + + + + clock_name_1 + outclk0 + + + clock_name_2 + outclk1 + + + clock_name_3 + outclk2 + + + clock_name_4 + outclk3 + + + clock_name_5 + outclk4 + + + clock_name_6 + + + + clock_name_7 + + + + clock_name_8 + + + + clock_name_global + false + + + clock_name_global_0 + false + + + clock_name_global_1 + false + + + clock_name_global_2 + false + + + clock_name_global_3 + false + + + clock_name_global_4 + false + + + clock_name_global_5 + false + + + clock_name_global_6 + false + + + clock_name_global_7 + false + + + clock_name_global_8 + false + + + clock_to_compensate + 1 + + + compensation_clk_source + COMPENSATION_CLK_SOURCE_UNUSED + + + compensation_mode + COMPENSATION_MODE_DIRECT + + + divide_factor0 + 1 + + + divide_factor1 + 1 + + + divide_factor2 + 1 + + + divide_factor3 + 1 + + + divide_factor4 + 1 + + + divide_factor5 + 1 + + + divide_factor6 + 1 + + + divide_factor7 + 1 + + + divide_factor8 + 1 + + + dprio_interface_sel + 3 + + + duty_cycle0 + 50 + + + duty_cycle1 + 50 + + + duty_cycle10 + 50 + + + duty_cycle11 + 50 + + + duty_cycle12 + 50 + + + duty_cycle13 + 50 + + + duty_cycle14 + 50 + + + duty_cycle15 + 50 + + + duty_cycle16 + 50 + + + duty_cycle17 + 50 + + + duty_cycle2 + 50 + + + duty_cycle3 + 50 + + + duty_cycle4 + 50 + + + duty_cycle5 + 50 + + + duty_cycle6 + 50 + + + duty_cycle7 + 50 + + + duty_cycle8 + 50 + + + duty_cycle9 + 50 + + + eff_m_cnt + 1 + + + fb_clk_delay + 0 + + + fb_clk_fractional_div_den + 1 + + + fb_clk_fractional_div_num + 1 + + + fb_clk_fractional_div_value + 1 + + + fb_clk_m_div + 0 + + + fractional_vco_multiplier + false + + + gui_active_clk + false + + + gui_actual_duty_cycle0 + 50.0 + + + gui_actual_duty_cycle1 + 50.0 + + + gui_actual_duty_cycle10 + 50.0 + + + gui_actual_duty_cycle11 + 50.0 + + + gui_actual_duty_cycle12 + 50.0 + + + gui_actual_duty_cycle13 + 50.0 + + + gui_actual_duty_cycle14 + 50.0 + + + gui_actual_duty_cycle15 + 50.0 + + + gui_actual_duty_cycle16 + 50.0 + + + gui_actual_duty_cycle17 + 50.0 + + + gui_actual_duty_cycle2 + 50.0 + + + gui_actual_duty_cycle3 + 50.0 + + + gui_actual_duty_cycle4 + 50.0 + + + gui_actual_duty_cycle5 + 50.0 + + + gui_actual_duty_cycle6 + 50.0 + + + gui_actual_duty_cycle7 + 50.0 + + + gui_actual_duty_cycle8 + 50.0 + + + gui_actual_duty_cycle9 + 50.0 + + + gui_actual_duty_cycle_range0 + 20.0,30.0,40.0,50.0,60.0,70.0 + + + gui_actual_duty_cycle_range1 + 31.25,37.5,43.75,50.0,56.25,62.5 + + + gui_actual_duty_cycle_range10 + 50.0 + + + gui_actual_duty_cycle_range11 + 50.0 + + + gui_actual_duty_cycle_range12 + 50.0 + + + gui_actual_duty_cycle_range13 + 50.0 + + + gui_actual_duty_cycle_range14 + 50.0 + + + gui_actual_duty_cycle_range15 + 50.0 + + + gui_actual_duty_cycle_range16 + 50.0 + + + gui_actual_duty_cycle_range17 + 50.0 + + + gui_actual_duty_cycle_range2 + 20.0,30.0,40.0,50.0,60.0,70.0 + + + gui_actual_duty_cycle_range3 + 31.25,37.5,43.75,50.0,56.25,62.5 + + + gui_actual_duty_cycle_range4 + 35.0,40.0,45.0,50.0,55.0,60.0 + + + gui_actual_duty_cycle_range5 + 50.0 + + + gui_actual_duty_cycle_range6 + 50.0 + + + gui_actual_duty_cycle_range7 + 50.0 + + + gui_actual_duty_cycle_range8 + 50.0 + + + gui_actual_duty_cycle_range9 + 50.0 + + + gui_actual_output_clock_frequency0 + 200.0 + + + gui_actual_output_clock_frequency1 + 125.0 + + + gui_actual_output_clock_frequency10 + 100.0 + + + gui_actual_output_clock_frequency11 + 100.0 + + + gui_actual_output_clock_frequency12 + 100.0 + + + gui_actual_output_clock_frequency13 + 100.0 + + + gui_actual_output_clock_frequency14 + 100.0 + + + gui_actual_output_clock_frequency15 + 100.0 + + + gui_actual_output_clock_frequency16 + 100.0 + + + gui_actual_output_clock_frequency17 + 100.0 + + + gui_actual_output_clock_frequency2 + 200.0 + + + gui_actual_output_clock_frequency3 + 125.0 + + + gui_actual_output_clock_frequency4 + 100.0 + + + gui_actual_output_clock_frequency5 + 100.0 + + + gui_actual_output_clock_frequency6 + 100.0 + + + gui_actual_output_clock_frequency7 + 100.0 + + + gui_actual_output_clock_frequency8 + 100.0 + + + gui_actual_output_clock_frequency9 + 100.0 + + + gui_actual_output_clock_frequency_range0 + 198.333333,198.412698,198.571429,200.0,201.428571,201.587302 + + + gui_actual_output_clock_frequency_range1 + 114.285714,116.666667,120.0,125.0,127.272727,133.333333 + + + gui_actual_output_clock_frequency_range10 + 100.0 + + + gui_actual_output_clock_frequency_range11 + 100.0 + + + gui_actual_output_clock_frequency_range12 + 100.0 + + + gui_actual_output_clock_frequency_range13 + 100.0 + + + gui_actual_output_clock_frequency_range14 + 100.0 + + + gui_actual_output_clock_frequency_range15 + 100.0 + + + gui_actual_output_clock_frequency_range16 + 100.0 + + + gui_actual_output_clock_frequency_range17 + 100.0 + + + gui_actual_output_clock_frequency_range2 + 125.0,142.857143,166.666667,200.0,250.0,333.333333 + + + gui_actual_output_clock_frequency_range3 + 90.909091,100.0,111.111111,125.0,142.857143,166.666667 + + + gui_actual_output_clock_frequency_range4 + 76.923077,83.333333,90.909091,100.0,111.111111,125.0 + + + gui_actual_output_clock_frequency_range5 + 100.0 + + + gui_actual_output_clock_frequency_range6 + 100.0 + + + gui_actual_output_clock_frequency_range7 + 100.0 + + + gui_actual_output_clock_frequency_range8 + 100.0 + + + gui_actual_output_clock_frequency_range9 + 100.0 + + + gui_actual_phase_shift0 + 0.0 + + + gui_actual_phase_shift1 + 0.0 + + + gui_actual_phase_shift10 + 0.0 + + + gui_actual_phase_shift11 + 0.0 + + + gui_actual_phase_shift12 + 0.0 + + + gui_actual_phase_shift13 + 0.0 + + + gui_actual_phase_shift14 + 0.0 + + + gui_actual_phase_shift15 + 0.0 + + + gui_actual_phase_shift16 + 0.0 + + + gui_actual_phase_shift17 + 0.0 + + + gui_actual_phase_shift2 + 0.0 + + + gui_actual_phase_shift3 + 2000.0 + + + gui_actual_phase_shift4 + 0.0 + + + gui_actual_phase_shift5 + 0.0 + + + gui_actual_phase_shift6 + 0.0 + + + gui_actual_phase_shift7 + 0.0 + + + gui_actual_phase_shift8 + 0.0 + + + gui_actual_phase_shift9 + 0.0 + + + gui_actual_phase_shift_deg0 + 0.0 + + + gui_actual_phase_shift_deg1 + 0.0 + + + gui_actual_phase_shift_deg10 + 0.0 + + + gui_actual_phase_shift_deg11 + 0.0 + + + gui_actual_phase_shift_deg12 + 0.0 + + + gui_actual_phase_shift_deg13 + 0.0 + + + gui_actual_phase_shift_deg14 + 0.0 + + + gui_actual_phase_shift_deg15 + 0.0 + + + gui_actual_phase_shift_deg16 + 0.0 + + + gui_actual_phase_shift_deg17 + 0.0 + + + gui_actual_phase_shift_deg2 + 0.0 + + + gui_actual_phase_shift_deg3 + 90.0 + + + gui_actual_phase_shift_deg4 + 0.0 + + + gui_actual_phase_shift_deg5 + 0.0 + + + gui_actual_phase_shift_deg6 + 0.0 + + + gui_actual_phase_shift_deg7 + 0.0 + + + gui_actual_phase_shift_deg8 + 0.0 + + + gui_actual_phase_shift_deg9 + 0.0 + + + gui_actual_phase_shift_deg_range0 + 0.0,9.0,18.0,27.0,36.0,45.0 + + + gui_actual_phase_shift_deg_range1 + 0.0,5.6,11.2,16.9,22.5,28.1 + + + gui_actual_phase_shift_deg_range10 + 0.0 + + + gui_actual_phase_shift_deg_range11 + 0.0 + + + gui_actual_phase_shift_deg_range12 + 0.0 + + + gui_actual_phase_shift_deg_range13 + 0.0 + + + gui_actual_phase_shift_deg_range14 + 0.0 + + + gui_actual_phase_shift_deg_range15 + 0.0 + + + gui_actual_phase_shift_deg_range16 + 0.0 + + + gui_actual_phase_shift_deg_range17 + 0.0 + + + gui_actual_phase_shift_deg_range2 + 0.0,9.0,18.0,27.0,36.0,45.0 + + + gui_actual_phase_shift_deg_range3 + 73.1,78.8,84.4,90.0,95.6,101.2 + + + gui_actual_phase_shift_deg_range4 + 0.0,4.5,9.0,13.5,18.0,22.5 + + + gui_actual_phase_shift_deg_range5 + 0.0 + + + gui_actual_phase_shift_deg_range6 + 0.0 + + + gui_actual_phase_shift_deg_range7 + 0.0 + + + gui_actual_phase_shift_deg_range8 + 0.0 + + + gui_actual_phase_shift_deg_range9 + 0.0 + + + gui_actual_phase_shift_range0 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range1 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range10 + 0.0 + + + gui_actual_phase_shift_range11 + 0.0 + + + gui_actual_phase_shift_range12 + 0.0 + + + gui_actual_phase_shift_range13 + 0.0 + + + gui_actual_phase_shift_range14 + 0.0 + + + gui_actual_phase_shift_range15 + 0.0 + + + gui_actual_phase_shift_range16 + 0.0 + + + gui_actual_phase_shift_range17 + 0.0 + + + gui_actual_phase_shift_range2 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range3 + 1625.0,1750.0,1875.0,2000.0,2125.0,2250.0 + + + gui_actual_phase_shift_range4 + 0.0,125.0,250.0,375.0,500.0,625.0 + + + gui_actual_phase_shift_range5 + 0.0 + + + gui_actual_phase_shift_range6 + 0.0 + + + gui_actual_phase_shift_range7 + 0.0 + + + gui_actual_phase_shift_range8 + 0.0 + + + gui_actual_phase_shift_range9 + 0.0 + + + gui_c_cnt_in_src0 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src1 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src2 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src3 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src4 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src5 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src6 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src7 + c_m_cnt_in_src_ph_mux_clk + + + gui_c_cnt_in_src8 + c_m_cnt_in_src_ph_mux_clk + + + gui_cal_code_hex_file + iossm.hex + + + gui_cal_converge + false + + + gui_cal_error + cal_clean + + + gui_cascade_counter0 + false + + + gui_cascade_counter1 + false + + + gui_cascade_counter10 + false + + + gui_cascade_counter11 + false + + + gui_cascade_counter12 + false + + + gui_cascade_counter13 + false + + + gui_cascade_counter14 + false + + + gui_cascade_counter15 + false + + + gui_cascade_counter16 + false + + + gui_cascade_counter17 + false + + + gui_cascade_counter2 + false + + + gui_cascade_counter3 + false + + + gui_cascade_counter4 + false + + + gui_cascade_counter5 + false + + + gui_cascade_counter6 + false + + + gui_cascade_counter7 + false + + + gui_cascade_counter8 + false + + + gui_cascade_counter9 + false + + + gui_cascade_outclk_index + 0 + + + gui_clk_bad + false + + + gui_clock_name_global + false + + + gui_clock_name_string0 + outclk0 + + + gui_clock_name_string1 + outclk1 + + + gui_clock_name_string10 + outclk10 + + + gui_clock_name_string11 + outclk11 + + + gui_clock_name_string12 + outclk12 + + + gui_clock_name_string13 + outclk13 + + + gui_clock_name_string14 + outclk14 + + + gui_clock_name_string15 + outclk15 + + + gui_clock_name_string16 + outclk16 + + + gui_clock_name_string17 + outclk17 + + + gui_clock_name_string2 + outclk2 + + + gui_clock_name_string3 + outclk3 + + + gui_clock_name_string4 + outclk4 + + + gui_clock_name_string5 + outclk5 + + + gui_clock_name_string6 + outclk6 + + + gui_clock_name_string7 + outclk7 + + + gui_clock_name_string8 + outclk8 + + + gui_clock_name_string9 + outclk9 + + + gui_clock_to_compensate + 0 + + + gui_debug_mode + false + + + gui_device_component + AGFB014R24B2E2V + + + gui_device_family + Agilex 7 + + + gui_device_iobank_rev + IO96A_REVB2 + + + gui_device_speed_grade + 2 + + + gui_divide_factor_c0 + 1 + + + gui_divide_factor_c1 + 25 + + + gui_divide_factor_c10 + 6 + + + gui_divide_factor_c11 + 6 + + + gui_divide_factor_c12 + 6 + + + gui_divide_factor_c13 + 6 + + + gui_divide_factor_c14 + 6 + + + gui_divide_factor_c15 + 6 + + + gui_divide_factor_c16 + 6 + + + gui_divide_factor_c17 + 6 + + + gui_divide_factor_c2 + 25 + + + gui_divide_factor_c3 + 6 + + + gui_divide_factor_c4 + 6 + + + gui_divide_factor_c5 + 6 + + + gui_divide_factor_c6 + 6 + + + gui_divide_factor_c7 + 6 + + + gui_divide_factor_c8 + 6 + + + gui_divide_factor_c9 + 6 + + + gui_divide_factor_n + 6 + + + gui_dps_cntr + C0 + + + gui_dps_dir + Positive + + + gui_dps_num + 1 + + + gui_dsm_out_sel + 1st_order + + + gui_duty_cycle0 + 50.0 + + + gui_duty_cycle1 + 50.0 + + + gui_duty_cycle10 + 50.0 + + + gui_duty_cycle11 + 50.0 + + + gui_duty_cycle12 + 50.0 + + + gui_duty_cycle13 + 50.0 + + + gui_duty_cycle14 + 50.0 + + + gui_duty_cycle15 + 50.0 + + + gui_duty_cycle16 + 50.0 + + + gui_duty_cycle17 + 50.0 + + + gui_duty_cycle2 + 50.0 + + + gui_duty_cycle3 + 50.0 + + + gui_duty_cycle4 + 50.0 + + + gui_duty_cycle5 + 50.0 + + + gui_duty_cycle6 + 50.0 + + + gui_duty_cycle7 + 50.0 + + + gui_duty_cycle8 + 50.0 + + + gui_duty_cycle9 + 50.0 + + + gui_en_adv_params + false + + + gui_en_dps_ports + false + + + gui_en_extclkout_ports + false + + + gui_en_iossm_reconf + false + + + gui_en_lvds_ports + Disabled + + + gui_en_periphery_ports + false + + + gui_en_phout_ports + false + + + gui_en_reconf + false + + + gui_enable_cascade_in + false + + + gui_enable_cascade_out + false + + + gui_enable_mif_dps + false + + + gui_enable_output_counter_cascading + false + + + gui_enable_permit_cal + false + + + gui_enable_upstream_out_clk + false + + + gui_existing_mif_file_path + ~/pll.mif + + + gui_extclkout_0_source + C0 + + + gui_extclkout_1_source + C0 + + + gui_extclkout_source + C0 + + + gui_feedback_clock + Global Clock + + + gui_fix_vco_frequency + false + + + gui_fixed_vco_frequency + 600.0 + + + gui_fixed_vco_frequency_ps + 1667.0 + + + gui_frac_multiply_factor + 1 + + + gui_fractional_cout + 32 + + + gui_include_iossm + false + + + gui_location_type + I/O Bank + + + gui_lock_setting + Low Lock Time + + + gui_mif_config_name + unnamed + + + gui_mif_gen_options + Generate New MIF File + + + gui_multiply_factor + 25 + + + gui_new_mif_file_path + ~/pll.mif + + + gui_number_of_clocks + 5 + + + gui_operation_mode + direct + + + gui_output_clock_frequency0 + 200.0 + + + gui_output_clock_frequency1 + 125.0 + + + gui_output_clock_frequency10 + 100.0 + + + gui_output_clock_frequency11 + 100.0 + + + gui_output_clock_frequency12 + 100.0 + + + gui_output_clock_frequency13 + 100.0 + + + gui_output_clock_frequency14 + 100.0 + + + gui_output_clock_frequency15 + 100.0 + + + gui_output_clock_frequency16 + 100.0 + + + gui_output_clock_frequency17 + 100.0 + + + gui_output_clock_frequency2 + 200.0 + + + gui_output_clock_frequency3 + 125.0 + + + gui_output_clock_frequency4 + 100.0 + + + gui_output_clock_frequency5 + 100.0 + + + gui_output_clock_frequency6 + 100.0 + + + gui_output_clock_frequency7 + 100.0 + + + gui_output_clock_frequency8 + 100.0 + + + gui_output_clock_frequency9 + 100.0 + + + gui_output_clock_frequency_ps0 + 5000.0 + + + gui_output_clock_frequency_ps1 + 8000.0 + + + gui_output_clock_frequency_ps10 + 10000.0 + + + gui_output_clock_frequency_ps11 + 10000.0 + + + gui_output_clock_frequency_ps12 + 10000.0 + + + gui_output_clock_frequency_ps13 + 10000.0 + + + gui_output_clock_frequency_ps14 + 10000.0 + + + gui_output_clock_frequency_ps15 + 10000.0 + + + gui_output_clock_frequency_ps16 + 10000.0 + + + gui_output_clock_frequency_ps17 + 10000.0 + + + gui_output_clock_frequency_ps2 + 5000.0 + + + gui_output_clock_frequency_ps3 + 8000.0 + + + gui_output_clock_frequency_ps4 + 10000.0 + + + gui_output_clock_frequency_ps5 + 10000.0 + + + gui_output_clock_frequency_ps6 + 10000.0 + + + gui_output_clock_frequency_ps7 + 10000.0 + + + gui_output_clock_frequency_ps8 + 10000.0 + + + gui_output_clock_frequency_ps9 + 10000.0 + + + gui_parameter_table_hex_file + seq_params_sim.hex + + + gui_phase_shift0 + 0.0 + + + gui_phase_shift1 + 0.0 + + + gui_phase_shift10 + 0.0 + + + gui_phase_shift11 + 0.0 + + + gui_phase_shift12 + 0.0 + + + gui_phase_shift13 + 0.0 + + + gui_phase_shift14 + 0.0 + + + gui_phase_shift15 + 0.0 + + + gui_phase_shift16 + 0.0 + + + gui_phase_shift17 + 0.0 + + + gui_phase_shift2 + 0.0 + + + gui_phase_shift3 + 0.0 + + + gui_phase_shift4 + 0.0 + + + gui_phase_shift5 + 0.0 + + + gui_phase_shift6 + 0.0 + + + gui_phase_shift7 + 0.0 + + + gui_phase_shift8 + 0.0 + + + gui_phase_shift9 + 0.0 + + + gui_phase_shift_deg0 + 0.0 + + + gui_phase_shift_deg1 + 0.0 + + + gui_phase_shift_deg10 + 0.0 + + + gui_phase_shift_deg11 + 0.0 + + + gui_phase_shift_deg12 + 0.0 + + + gui_phase_shift_deg13 + 0.0 + + + gui_phase_shift_deg14 + 0.0 + + + gui_phase_shift_deg15 + 0.0 + + + gui_phase_shift_deg16 + 0.0 + + + gui_phase_shift_deg17 + 0.0 + + + gui_phase_shift_deg2 + 0.0 + + + gui_phase_shift_deg3 + 90.0 + + + gui_phase_shift_deg4 + 0.0 + + + gui_phase_shift_deg5 + 0.0 + + + gui_phase_shift_deg6 + 0.0 + + + gui_phase_shift_deg7 + 0.0 + + + gui_phase_shift_deg8 + 0.0 + + + gui_phase_shift_deg9 + 0.0 + + + gui_phout_division + 1 + + + gui_pll_auto_reset + false + + + gui_pll_bandwidth_preset + Medium + + + gui_pll_cal_done + false + + + gui_pll_cascading_mode + adjpllin + + + gui_pll_freqcal_en + true + + + gui_pll_freqcal_req_flag + true + + + gui_pll_m_cnt_in_src + c_m_cnt_in_src_ph_mux_clk + + + gui_pll_mode + Integer-N PLL + + + gui_pll_tclk_mux_en + false + + + gui_pll_tclk_sel + pll_tclk_m_src + + + gui_pll_type + S10_Simple + + + gui_pll_vco_freq_band_0 + pll_freq_clk0_band18 + + + gui_pll_vco_freq_band_1 + pll_freq_clk1_band18 + + + gui_prot_mode + UNUSED + + + gui_ps_units0 + ps + + + gui_ps_units1 + ps + + + gui_ps_units10 + ps + + + gui_ps_units11 + ps + + + gui_ps_units12 + ps + + + gui_ps_units13 + ps + + + gui_ps_units14 + ps + + + gui_ps_units15 + ps + + + gui_ps_units16 + ps + + + gui_ps_units17 + ps + + + gui_ps_units2 + ps + + + gui_ps_units3 + degrees + + + gui_ps_units4 + ps + + + gui_ps_units5 + ps + + + gui_ps_units6 + ps + + + gui_ps_units7 + ps + + + gui_ps_units8 + ps + + + gui_ps_units9 + ps + + + gui_refclk1_frequency + 100.0 + + + gui_refclk_might_change + false + + + gui_refclk_switch + false + + + gui_reference_clock_frequency + 100.0 + + + gui_reference_clock_frequency_ps + 10000.0 + + + gui_simulation_type + false + + + gui_skip_sdc_generation + false + + + gui_switchover_delay + 0 + + + gui_switchover_mode + Automatic Switchover + + + gui_use_NDFB_modes + false + + + gui_use_coreclk + true + + + gui_use_locked + true + + + gui_use_logical + false + + + gui_user_base_address + 0 + + + gui_usr_device_speed_grade + 1 + + + gui_vco_frequency + 1250.0 + + + hp_actual_duty_cycle_fp0 + 50.0 + + + hp_actual_duty_cycle_fp1 + 50.0 + + + hp_actual_duty_cycle_fp10 + 50.0 + + + hp_actual_duty_cycle_fp11 + 50.0 + + + hp_actual_duty_cycle_fp12 + 50.0 + + + hp_actual_duty_cycle_fp13 + 50.0 + + + hp_actual_duty_cycle_fp14 + 50.0 + + + hp_actual_duty_cycle_fp15 + 50.0 + + + hp_actual_duty_cycle_fp16 + 50.0 + + + hp_actual_duty_cycle_fp17 + 50.0 + + + hp_actual_duty_cycle_fp2 + 50.0 + + + hp_actual_duty_cycle_fp3 + 50.0 + + + hp_actual_duty_cycle_fp4 + 50.0 + + + hp_actual_duty_cycle_fp5 + 50.0 + + + hp_actual_duty_cycle_fp6 + 50.0 + + + hp_actual_duty_cycle_fp7 + 50.0 + + + hp_actual_duty_cycle_fp8 + 50.0 + + + hp_actual_duty_cycle_fp9 + 50.0 + + + hp_actual_output_clock_frequency_fp0 + 200.0 + + + hp_actual_output_clock_frequency_fp1 + 125.0 + + + hp_actual_output_clock_frequency_fp10 + 100.0 + + + hp_actual_output_clock_frequency_fp11 + 100.0 + + + hp_actual_output_clock_frequency_fp12 + 100.0 + + + hp_actual_output_clock_frequency_fp13 + 100.0 + + + hp_actual_output_clock_frequency_fp14 + 100.0 + + + hp_actual_output_clock_frequency_fp15 + 100.0 + + + hp_actual_output_clock_frequency_fp16 + 100.0 + + + hp_actual_output_clock_frequency_fp17 + 100.0 + + + hp_actual_output_clock_frequency_fp2 + 200.0 + + + hp_actual_output_clock_frequency_fp3 + 125.0 + + + hp_actual_output_clock_frequency_fp4 + 100.0 + + + hp_actual_output_clock_frequency_fp5 + 100.0 + + + hp_actual_output_clock_frequency_fp6 + 100.0 + + + hp_actual_output_clock_frequency_fp7 + 100.0 + + + hp_actual_output_clock_frequency_fp8 + 100.0 + + + hp_actual_output_clock_frequency_fp9 + 100.0 + + + hp_actual_phase_shift_fp0 + 0.0 + + + hp_actual_phase_shift_fp1 + 0.0 + + + hp_actual_phase_shift_fp10 + 0.0 + + + hp_actual_phase_shift_fp11 + 0.0 + + + hp_actual_phase_shift_fp12 + 0.0 + + + hp_actual_phase_shift_fp13 + 0.0 + + + hp_actual_phase_shift_fp14 + 0.0 + + + hp_actual_phase_shift_fp15 + 0.0 + + + hp_actual_phase_shift_fp16 + 0.0 + + + hp_actual_phase_shift_fp17 + 0.0 + + + hp_actual_phase_shift_fp2 + 0.0 + + + hp_actual_phase_shift_fp3 + 2000.0 + + + hp_actual_phase_shift_fp4 + 0.0 + + + hp_actual_phase_shift_fp5 + 0.0 + + + hp_actual_phase_shift_fp6 + 0.0 + + + hp_actual_phase_shift_fp7 + 0.0 + + + hp_actual_phase_shift_fp8 + 0.0 + + + hp_actual_phase_shift_fp9 + 0.0 + + + hp_actual_vco_frequency_fp + 600.0 + + + hp_number_of_family_allowable_clocks + 9 + + + hp_parameter_update_message + + + + hp_previous_num_clocks + 1 + + + hp_qsys_scripting_mode + false + + + include_iossm + false + + + iossm_nios_sim_clk_period_ps + 1333 + + + lock_mode + low_lock_time + + + m_cnt_bypass_en + false + + + m_cnt_hi_div + 5 + + + m_cnt_lo_div + 5 + + + m_cnt_odd_div_duty_en + false + + + merging_permitted + false + + + mifTable_names + The MIF file specified does not yet exist + + + mifTable_values + + + + mimic_fbclk_type + gclk + + + multiply_factor + 10 + + + n_cnt_bypass_en + true + + + n_cnt_hi_div + 256 + + + n_cnt_lo_div + 256 + + + n_cnt_odd_div_duty_en + false + + + number_of_clocks + 5 + + + number_of_outclks + 5 + + + operation_mode + direct + + + out_clk_0_c_div + 1 + + + out_clk_0_core_en + true + + + out_clk_0_delay + 0 + + + out_clk_0_dutycycle_den + 2 + + + out_clk_0_dutycycle_num + 1 + + + out_clk_0_freq + 1000000000 + + + out_clk_0_phase_ps + 1000000000 + + + out_clk_0_phase_shifts + 0 + + + out_clk_1_c_div + 1 + + + out_clk_1_core_en + true + + + out_clk_1_delay + 0 + + + out_clk_1_dutycycle_den + 2 + + + out_clk_1_dutycycle_num + 1 + + + out_clk_1_freq + 1000000000 + + + out_clk_1_phase_ps + 1000000000 + + + out_clk_1_phase_shifts + 0 + + + out_clk_2_c_div + 1 + + + out_clk_2_core_en + true + + + out_clk_2_delay + 0 + + + out_clk_2_dutycycle_den + 2 + + + out_clk_2_dutycycle_num + 1 + + + out_clk_2_freq + 1000000000 + + + out_clk_2_phase_ps + 1000000000 + + + out_clk_2_phase_shifts + 0 + + + out_clk_3_c_div + 1 + + + out_clk_3_core_en + true + + + out_clk_3_delay + 0 + + + out_clk_3_dutycycle_den + 2 + + + out_clk_3_dutycycle_num + 1 + + + out_clk_3_freq + 1000000000 + + + out_clk_3_phase_ps + 1000000000 + + + out_clk_3_phase_shifts + 0 + + + out_clk_4_c_div + 1 + + + out_clk_4_core_en + true + + + out_clk_4_delay + 0 + + + out_clk_4_dutycycle_den + 2 + + + out_clk_4_dutycycle_num + 1 + + + out_clk_4_freq + 1000000000 + + + out_clk_4_phase_ps + 1000000000 + + + out_clk_4_phase_shifts + 0 + + + out_clk_5_c_div + 1 + + + out_clk_5_core_en + true + + + out_clk_5_delay + 0 + + + out_clk_5_dutycycle_den + 2 + + + out_clk_5_dutycycle_num + 1 + + + out_clk_5_freq + 1000000000 + + + out_clk_5_phase_ps + 1000000000 + + + out_clk_5_phase_shifts + 0 + + + out_clk_6_c_div + 1 + + + out_clk_6_core_en + true + + + out_clk_6_delay + 0 + + + out_clk_6_dutycycle_den + 2 + + + out_clk_6_dutycycle_num + 1 + + + out_clk_6_freq + 1000000000 + + + out_clk_6_phase_ps + 1000000000 + + + out_clk_6_phase_shifts + 0 + + + out_clk_cascading_source + OUT_CLK_CASCADING_SOURCE_UNUSED + + + out_clk_external_0_source + OUT_CLK_EXTERNAL_0_SOURCE_UNUSED + + + out_clk_external_1_source + OUT_CLK_EXTERNAL_1_SOURCE_UNUSED + + + out_clk_periph_0_delay + 0 + + + out_clk_periph_0_en + true + + + out_clk_periph_1_delay + 0 + + + out_clk_periph_1_en + true + + + output_clock_frequency0 + 0 ps + + + output_clock_frequency1 + 200.0 MHz + + + output_clock_frequency10 + 0 MHz + + + output_clock_frequency11 + 0 MHz + + + output_clock_frequency12 + 0 MHz + + + output_clock_frequency13 + 0 MHz + + + output_clock_frequency14 + 0 MHz + + + output_clock_frequency15 + 0 MHz + + + output_clock_frequency16 + 0 MHz + + + output_clock_frequency17 + 0 MHz + + + output_clock_frequency2 + 125.0 MHz + + + output_clock_frequency3 + 200.0 MHz + + + output_clock_frequency4 + 125.0 MHz + + + output_clock_frequency5 + 100.0 MHz + + + output_clock_frequency6 + 0 ps + + + output_clock_frequency7 + 0 ps + + + output_clock_frequency8 + 0 ps + + + output_clock_frequency9 + 0 ps + + + parameterTable_names + M-Counter Divide Setting,N-Counter Divide Setting,VCO Frequency,C-Counter-0 Divide Setting,C-Counter-1 Divide Setting,C-Counter-2 Divide Setting,C-Counter-3 Divide Setting,C-Counter-4 Divide Setting,C-Counter-5 Divide Setting,C-Counter-6 Divide Setting,C-Counter-7 Divide Setting,C-Counter-8 Divide Setting,PLL Auto Reset,M-Counter Hi Divide,M-Counter Lo Divide,M-Counter Even Duty Enable,M-Counter Bypass Enable,N-Counter Hi Divide,N-Counter Lo Divide,N-Counter Even Duty Enable,N-Counter Bypass Enable,C-Counter-0 Hi Divide,C-Counter-1 Hi Divide,C-Counter-2 Hi Divide,C-Counter-3 Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control + + + parameterTable_values + 10,1,1000.0 MHz,1,5,8,5,8,10,1,1,1,false,5,5,false,false,256,256,false,true,256,3,4,3,4,5,256,256,256,256,2,4,2,4,5,256,256,256,false,true,false,true,false,false,false,false,false,true,false,false,false,false,false,true,true,true,1,1,1,1,3,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting5,pll_bw_res_setting3 + + + parameter_table_hex_file + seq_params_sim.hex + + + pfd_clk_freq + 100000000 + + + phase_shift0 + 0 ps + + + phase_shift1 + 0 ps + + + phase_shift10 + 0 ps + + + phase_shift11 + 0 ps + + + phase_shift12 + 0 ps + + + phase_shift13 + 0 ps + + + phase_shift14 + 0 ps + + + phase_shift15 + 0 ps + + + phase_shift16 + 0 ps + + + phase_shift17 + 0 ps + + + phase_shift2 + 0 ps + + + phase_shift3 + 0 ps + + + phase_shift4 + 2000 ps + + + phase_shift5 + 0 ps + + + phase_shift6 + 0 ps + + + phase_shift7 + 0 ps + + + phase_shift8 + 0 ps + + + phase_shift9 + 0 ps + + + pll_auto_clk_sw_en + false + + + pll_bw_sel + mid_bw + + + pll_bwctrl + pll_bw_res_setting3 + + + pll_cal_done + false + + + pll_clk_loss_sw_en + false + + + pll_clk_sw_dly + 0 + + + pll_clkin_0_src + coreclkin + + + pll_clkin_1_src + ioclkin_0 + + + pll_cp_current + pll_cp_setting5 + + + pll_defer_cal_user_mode + true + + + pll_dsm_out_sel + 1st_order + + + pll_extclk_0_cnt_src + pll_extclk_cnt_src_vss + + + pll_extclk_1_cnt_src + pll_extclk_cnt_src_vss + + + pll_fbclk_mux_1 + pll_fbclk_mux_1_glb + + + pll_fbclk_mux_2 + pll_fbclk_mux_2_m_cnt + + + pll_fractional_cout + 1 + + + pll_fractional_division + 1 + + + pll_freqcal_en + true + + + pll_freqcal_req_flag + true + + + pll_lock_fltr_cfg + 100 + + + pll_m_cnt + 1 + + + pll_m_cnt_basic + 1 + + + pll_m_cnt_in_src + c_m_cnt_in_src_ph_mux_clk + + + pll_manu_clk_sw_en + false + + + pll_output_clk_frequency + 1000.0 MHz + + + pll_pfd_frequency + 100.0 MHz + + + pll_ripplecap_ctrl + pll_ripplecap_setting1 + + + pll_slf_rst + false + + + pll_subtype + General + + + pll_tclk_mux_en + false + + + pll_tclk_sel + pll_tclk_m_src + + + pll_type + TOP_BOTTOM + + + pll_unlock_fltr_cfg + 2 + + + pll_vco_div + 1 + + + pll_vco_freq_band_0 + pll_freq_clk0_band18 + + + pll_vco_freq_band_1 + pll_freq_clk1_band18 + + + pll_vcoph_div + 1 + + + prot_mode + BASIC + + + protocol_mode + PROTOCOL_MODE_BASIC + + + ref_clk_0_freq + 100000000 + + + ref_clk_1_freq + 100000000 + + + ref_clk_delay + 0 + + + ref_clk_n_div + 1 + + + refclk1_frequency + 0 MHz + + + reference_clock_frequency + 100.0 MHz + + + set_dutycycle + SET_DUTYCYCLE_FRACTION + + + set_fractional + SET_FRACTIONAL_FRACTION + + + set_freq + SET_FREQ_DIVISION + + + set_phase + SET_PHASE_NUM_SHIFTS + + + system_info_device_component + AGFB014R24B2E2V + + + system_info_device_family + Agilex 7 + + + system_info_device_iobank_rev + + + + system_info_device_speed_grade + 2 + + + system_part_trait_iobank_rev + IO96A_REVB2 + + + system_part_trait_speed_grade + 2 + + + use_core_refclk + true + + + vco_clk_freq + 1000000000 + + + + altera_iopll + 19.3.1 + iopll_0 + io_pll_altera_iopll_1931_oypl3jq + 0 + + io_pll.iopll_0 + + + + + \ No newline at end of file diff --git a/corev_apu/altera/ip/io_pll/io_pll.qip b/corev_apu/altera/ip/io_pll/io_pll.qip new file mode 100644 index 0000000000..20c0132911 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.qip @@ -0,0 +1,56 @@ +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TOOL_VERSION "24.1" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_iopll" +set_global_assignment -entity "io_pll" -library "io_pll" -name PRE_COMPILED_MODULE "ON" +set_global_assignment -entity "io_pll" -library "io_pll" -name OCS_IP_FILE "/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll.ip" +set_global_assignment -entity "io_pll" -library "io_pll" -name OCS_IP_TYPE "altera_iopll" +set_global_assignment -entity "io_pll" -library "io_pll" -name OCS_IP_VERSION "19.3.1" +set_global_assignment -entity "io_pll" -library "io_pll" -name OCS_IP_HASH "oypl3jq" +set_global_assignment -library "io_pll" -name SOPCINFO_FILE [file join $::quartus(qip_path) "io_pll.sopcinfo"] +set_global_assignment -entity "io_pll" -library "io_pll" -name SLD_INFO "QSYS_NAME io_pll HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "io_pll" -name MISC_FILE [file join $::quartus(qip_path) "io_pll.cmp"] +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TARGETED_DEVICE_FAMILY "Agilex 7" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TARGETED_PART_TRAIT "DEVICE_SPEEDGRADE::2" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96A_REVB2" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 7}" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "io_pll" -name MISC_FILE [file join $::quartus(qip_path) "../io_pll.ip"] + +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_NAME "aW9fcGxsX2FsdGVyYV9pb3BsbF8xOTMxX295cGwzanE=" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DISPLAY_NAME "SU9QTEwgSW50ZWwgRlBHQSBJUA==" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_VERSION "MTkuMy4x" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRlBHQSBQaGFzZS1Mb2NrZWQgTG9vcCAoSU9QTEwgSW50ZWwgRlBHQSBJUCkgY29yZSBhbGxvd3MgeW91IHRvIGNvbmZpZ3VyZSB0aGUgc2V0dGluZ3Mgb2YgdGhlICBJL08gUExMLg==" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0Nsb2NrczsgUExMcyBhbmQgUmVzZXRzL1BMTA==" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzI4NS8=" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzI4NS8=" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzE5NS8yMC0zL2NvcmUtOTU3NTEuaHRtbA==" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4Mzc2MS8=" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzc2OTAwMS8=" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzE2Ni8=" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_COMPONENT_NAME "aW9fcGxs" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "io_pll" -library "io_pll" -name IP_COMPONENT_VERSION "MS4w" + + +set_global_assignment -library "altera_iopll_1931" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.v"] +set_instance_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_all_ip_params.tcl"] +set_instance_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_parameters.tcl"] +set_instance_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq.sdc"] -no_sdc_promotion -no_auto_inst_discovery -read_during_post_syn_and_post_fit_timing_analysis +set_instance_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name TCL_ENTITY_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/io_pll_altera_iopll_1931_oypl3jq_pin_map.tcl"] +set_global_assignment -library "altera_iopll_1931" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/agilex_iobank_pll.ipxact"] +set_global_assignment -library "io_pll" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/io_pll.v"] + + +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_TOOL_NAME "altera_iopll" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_TOOL_VERSION "19.3.1" +set_global_assignment -entity "io_pll_altera_iopll_1931_oypl3jq" -library "altera_iopll_1931" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/corev_apu/altera/ip/io_pll/io_pll.sopcinfo b/corev_apu/altera/ip/io_pll/io_pll.sopcinfo new file mode 100644 index 0000000000..469849caae --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.sopcinfo @@ -0,0 +1,7332 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + default + false + true + false + true + BOARD + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + refclk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + refclk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + refclk + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + embeddedsw.dts.compatible + altr,pll + + + embeddedsw.dts.group + clock + + + embeddedsw.dts.vendor + altr + + + java.lang.String + Agilex 7 + true + false + true + true + + + java.lang.String + AGFB014R24B2E2V + true + false + true + true + + + int + 2 + true + true + true + true + + + java.lang.String + IO96A_REVB2 + true + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + iossm.hex + false + true + false + true + + + java.lang.String + seq_params_sim.hex + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + pll_tclk_m_src + false + true + false + true + + + java.lang.String + pll_freq_clk0_band18 + false + true + false + true + + + java.lang.String + pll_freq_clk1_band18 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + cal_clean + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + S10_Simple + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + false + true + false + true + + + java.lang.String + Agilex 7 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + AGFB014R24B2E2V + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + + false + true + false + true + + + java.lang.String + 2 + false + true + false + true + PART_TRAIT + DEVICE_SPEEDGRADE + + + java.lang.String + IO96A_REVB2 + false + true + false + true + PART_TRAIT + DEVICE_IOBANK_REVISION + + + java.lang.String + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + true + true + + + java.lang.String + Integer-N PLL + false + true + false + true + + + java.lang.String + I/O Bank + false + true + true + true + + + boolean + false + false + true + false + true + + + double + 100.0 + false + true + true + true + + + double + 10000.0 + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 32 + false + true + false + true + + + java.lang.String + UNUSED + false + true + false + true + + + java.lang.String + 1st_order + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + Medium + false + true + true + true + + + java.lang.String + Low Lock Time + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + Disabled + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + direct + false + true + true + true + + + java.lang.String + Global Clock + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 100.0 + false + false + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 5 + false + true + true + true + + + int + 25 + false + true + false + true + + + int + 6 + false + true + false + true + + + long + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 600.0 + false + false + false + true + + + double + 1667.0 + false + true + false + true + + + java.lang.String + 1250.0 + false + true + false + true + + + boolean + false + false + false + true + true + + + java.lang.String + Generate New MIF File + false + false + true + true + + + java.lang.String + ~/pll.mif + false + false + true + true + + + java.lang.String + ~/pll.mif + false + false + false + true + + + java.lang.String + unnamed + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + Automatic Switchover + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + 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Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control + true + true + true + true + + + [Ljava.lang.String; + 10,1,1000.0 MHz,1,5,8,5,8,10,1,1,1,false,5,5,false,false,256,256,false,true,256,3,4,3,4,5,256,256,256,256,2,4,2,4,5,256,256,256,false,true,false,true,false,false,false,false,false,true,false,false,false,false,false,true,true,true,1,1,1,1,3,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting5,pll_bw_res_setting3 + true + true + true + true + + + [Ljava.lang.String; + The MIF file specified does not yet exist + true + true + true + true + + + [Ljava.lang.String; + + true + true + true + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + BASIC + true + true + false + true + + + java.lang.String + PROTOCOL_MODE_BASIC + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 10 + true + true + false + true + + + boolean + true + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + pll_cp_setting5 + true + true + false + true + + + java.lang.String + pll_bw_res_setting3 + true + true + false + true + + + java.lang.String + pll_ripplecap_setting1 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + 100.0 MHz + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + 1st_order + true + true + false + true + + + java.lang.String + direct + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + TOP_BOTTOM + true + true + false + true + + + java.lang.String + General + true + true + false + true + + + java.lang.String + 1000.0 MHz + true + true + false + true + + + java.lang.String + 100.0 MHz + true + true + false + true + + + java.lang.String + gclk + true + true + false + true + + + java.lang.String + mid_bw + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + pll_fbclk_mux_1_glb + true + true + false + true + + + java.lang.String + pll_fbclk_mux_2_m_cnt + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + coreclkin + true + true + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + java.lang.String + ioclkin_0 + true + false + false + true + + + int + 0 + true + false + false + true + + + java.lang.String + pll_extclk_cnt_src_vss + true + true + false + true + + + java.lang.String + pll_extclk_cnt_src_vss + true + true + false + true + + + int + 100 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + low_lock_time + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + false + false + true + + + int + 3 + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + BANDWIDTH_MODE_AUTO + true + true + false + true + + + java.lang.String + COMPENSATION_CLK_SOURCE_UNUSED + true + true + false + true + + + java.lang.String + COMPENSATION_MODE_DIRECT + true + true + false + true + + + java.lang.String + CASCADE_MODE_STANDALONE + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + OUT_CLK_CASCADING_SOURCE_UNUSED + true + true + false + true + + + java.lang.String + OUT_CLK_EXTERNAL_0_SOURCE_UNUSED + true + true + false + true + + + java.lang.String + OUT_CLK_EXTERNAL_1_SOURCE_UNUSED + true + true + false + true + + + long + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + long + 0 + true + true + false + true + + + boolean + true + true + true + false + true + + + long + 0 + true + true + false + true + + + int + 1 + true + true + false + true + + + java.lang.String + SET_DUTYCYCLE_FRACTION + true + true + false + true + + + java.lang.String + SET_FRACTIONAL_FRACTION + true + true + false + true + + + java.lang.String + SET_FREQ_DIVISION + true + true + false + true + + + java.lang.String + SET_PHASE_NUM_SHIFTS + true + true + false + true + + + java.math.BigInteger + 100000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 256 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 4 + true + true + false + true + + + int + 5 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + true + false + true + + + int + 256 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 3 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 1 + true + false + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + int + 0 + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + true + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + java.lang.String + c_m_cnt_in_src_ph_mux_clk + true + false + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 200.0 MHz + true + true + false + true + + + java.lang.String + 125.0 MHz + true + true + false + true + + + java.lang.String + 200.0 MHz + true + true + false + true + + + java.lang.String + 125.0 MHz + true + true + false + true + + + java.lang.String + 100.0 MHz + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 MHz + true + false + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 2000 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + true + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + java.lang.String + 0 ps + true + false + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + true + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + int + 50 + true + false + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + outclk0 + true + true + false + true + + + java.lang.String + outclk1 + true + true + false + true + + + java.lang.String + outclk2 + true + true + false + true + + + java.lang.String + outclk3 + true + true + false + true + + + java.lang.String + outclk4 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + true + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 2 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 1 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + long + 0 + true + true + false + true + + + java.math.BigInteger + 100000000 + true + true + false + true + + + java.math.BigInteger + 100000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + java.math.BigInteger + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + long + 1000000000 + true + true + false + true + + + boolean + false + true + false + false + true + + + java.lang.String + pll_tclk_m_src + true + false + false + true + + + java.lang.String + pll_freq_clk0_band18 + true + false + false + true + + + java.lang.String + pll_freq_clk1_band18 + true + false + false + true + + + boolean + true + true + false + false + true + + + boolean + false + true + false + false + true + + + java.lang.String + cal_clean + true + false + false + true + + + boolean + false + true + false + false + true + + + boolean + false + true + false + false + true + + + java.lang.String + iossm.hex + true + false + false + true + + + java.lang.String + seq_params_sim.hex + true + false + false + true + + + int + 1333 + true + false + false + true + + + int + 9 + true + true + false + true + + + int + 1 + true + true + false + true + + + double + 600.0 + true + true + false + true + + + java.lang.String + + true + true + false + true + + + boolean + false + false + true + false + true + + + double + 200.0 + true + true + false + true + + + double + 125.0 + true + true + false + true + + + double + 200.0 + true + true + false + true + + + double + 125.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 100.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 2000.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 0.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + double + 50.0 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + ui.blockdiagram.direction + input + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + 0 + false + + refclk + Input + 1 + clk + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + 0 + false + + locked + Output + 1 + export + + + + + + ui.blockdiagram.direction + input + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + 0 + false + + rst + Input + 1 + reset + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + long + 200000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + outclk_0 + Output + 1 + clk + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + long + 125000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + outclk_1 + Output + 1 + clk + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + long + 200000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + outclk_2 + Output + 1 + clk + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + long + 125000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + outclk_3 + Output + 1 + clk + + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + long + 100000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + 0 + true + + outclk_4 + Output + 1 + clk + + + + + 1 + altera_iopll + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + IOPLL Intel FPGA IP + 19.3.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 24.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 24.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 24.1 + + + 5 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 24.1 + + 24.1 115 + + diff --git a/corev_apu/altera/ip/io_pll/io_pll.spd b/corev_apu/altera/ip/io_pll/io_pll.spd new file mode 100644 index 0000000000..0673e0309e --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.spd @@ -0,0 +1,15 @@ + + + + + + + + diff --git a/corev_apu/altera/ip/io_pll/io_pll.xml b/corev_apu/altera/ip/io_pll/io_pll.xml new file mode 100644 index 0000000000..45cf6fcab2 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll.xml @@ -0,0 +1,1079 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: io_pll" + "Generating: io_pll_altera_iopll_1931_oypl3jq" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: io_pll_altera_iopll_1931_oypl3jq" + + + diff --git a/corev_apu/altera/ip/io_pll/io_pll_bb.v b/corev_apu/altera/ip/io_pll/io_pll_bb.v new file mode 100644 index 0000000000..f741fe5214 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll_bb.v @@ -0,0 +1,12 @@ +module io_pll ( + input wire refclk, // refclk.clk + output wire locked, // locked.export + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire outclk_3, // outclk3.clk + output wire outclk_4 // outclk4.clk + ); +endmodule + diff --git a/corev_apu/altera/ip/io_pll/io_pll_generation.rpt b/corev_apu/altera/ip/io_pll/io_pll_generation.rpt new file mode 100644 index 0000000000..797016fe1e --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll_generation.rpt @@ -0,0 +1,65 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create simulation model +Info: qsys-generate /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll --family="Agilex 7" --part=AGFB014R24B2E2V +Info: io_pll.iopll_0: Able to implement PLL with user settings +Info: io_pll: "Transforming system: io_pll" +Info: io_pll: "Naming system components in system: io_pll" +Info: io_pll: "Processing generation queue" +Info: io_pll: "Generating: io_pll" +Info: io_pll: "Generating: io_pll_altera_iopll_1931_oypl3jq" +Info: io_pll: Done "io_pll" with 2 modules, 2 files +Info: Generating the following file(s) for VCSMX simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: common/vcsmx_files.tcl +Info: Generating the following file(s) for XCELIUM simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: common/xcelium_files.tcl +Info: Generating the following file(s) for VCS simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: common/vcs_files.tcl +Info: Generating the following file(s) for MODELSIM simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: common/modelsim_files.tcl +Info: Generating the following file(s) for RIVIERA simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: common/riviera_files.tcl +Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/. +Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. +Info: Finished: Create simulation model +Info: Starting: Create simulation script +Info: sim-script-gen --system-file=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll.ip --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ --use-relative-paths=true --modelsim-flow=traditional +Info: Generating the following file(s) for VCSMX simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: synopsys/vcsmx/synopsys_sim.setup +Info: synopsys/vcsmx/vcsmx_setup.sh +Info: Generating the following file(s) for XCELIUM simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: xcelium/cds.lib +Info: xcelium/hdl.var +Info: xcelium/xcelium_setup.sh +Info: 2 .cds.lib files in xcelium/cds_libs/ directory +Info: Generating the following file(s) for VCS simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: synopsys/vcs/vcs_setup.sh +Info: Generating the following file(s) for MODELSIM simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: mentor/msim_setup.tcl +Info: Generating the following file(s) for RIVIERA simulator in /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/ directory: +Info: aldec/rivierapro_setup.tcl +Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll/sim/. +Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. +Info: Finished: Create simulation script +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll --family="Agilex 7" --part=AGFB014R24B2E2V +Info: io_pll.iopll_0: Able to implement PLL with user settings +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll.ip --synthesis=VERILOG --greybox --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll --family="Agilex 7" --part=AGFB014R24B2E2V +Info: io_pll.iopll_0: Able to implement PLL with user settings +Info: io_pll: "Transforming system: io_pll" +Info: io_pll: "Naming system components in system: io_pll" +Info: io_pll: "Processing generation queue" +Info: io_pll: "Generating: io_pll" +Info: io_pll: "Generating: io_pll_altera_iopll_1931_oypl3jq" +Info: io_pll: Done "io_pll" with 2 modules, 7 files +Info: Generating third-party timing and resource estimation model ... +Info: Done generating third-party timing and resource estimation model. +Info: Finished: Create HDL design files for synthesis +Info: Starting: IP-XACT +Info: qsys-generate /home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll.ip --synthesis=VERILOG --ipxact --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/intel/ip/io_pll --family="Agilex 7" --part=AGFB014R24B2E2V +Info: Finished: IP-XACT +Info: Starting: Generate IP Core Documentation +Info: No documentation filesets were found for components in io_pll. No files generated. +Info: Finished: Generate IP Core Documentation diff --git a/corev_apu/altera/ip/io_pll/io_pll_generation_previous.rpt b/corev_apu/altera/ip/io_pll/io_pll_generation_previous.rpt new file mode 100644 index 0000000000..323b796b3e --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll_generation_previous.rpt @@ -0,0 +1,21 @@ +Info: Generated by version: 24.1 build 115 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/angela/Documents/github/cva6_intel/cva6/corev_apu/fpga/intel/io_pll.ip --block-symbol-file --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/fpga/intel/io_pll --family="Agilex 7" --part=AGFB014R24B2E2V +Warning: io_pll.iopll_0: Able to implement PLL - Actual outclk frequency 2 differs from requested setting +Warning: io_pll.iopll_0: Able to implement PLL - Actual outclk frequency 4 differs from requested setting +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/angela/Documents/github/cva6_intel/cva6/corev_apu/fpga/intel/io_pll.ip --synthesis=VERILOG --output-directory=/home/angela/Documents/github/cva6_intel/cva6/corev_apu/fpga/intel/io_pll --family="Agilex 7" --part=AGFB014R24B2E2V +Warning: io_pll.iopll_0: Able to implement PLL - Actual outclk frequency 2 differs from requested setting +Warning: io_pll.iopll_0: Able to implement PLL - Actual outclk frequency 4 differs from requested setting +Info: io_pll: "Transforming system: io_pll" +Info: io_pll: "Naming system components in system: io_pll" +Info: io_pll: "Processing generation queue" +Info: io_pll: "Generating: io_pll" +Info: io_pll: "Generating: io_pll_altera_iopll_1931_2chfxvi" +Info: io_pll: Done "io_pll" with 2 modules, 7 files +Info: Finished: Create HDL design files for synthesis +Info: Starting: Generate IP Core Documentation +Info: No documentation filesets were found for components in io_pll. No files generated. +Info: Finished: Generate IP Core Documentation diff --git a/corev_apu/altera/ip/io_pll/io_pll_inst.v b/corev_apu/altera/ip/io_pll/io_pll_inst.v new file mode 100644 index 0000000000..daf2e21bc2 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll_inst.v @@ -0,0 +1,11 @@ + io_pll u0 ( + .refclk (_connected_to_refclk_), // input, width = 1, refclk.clk + .locked (_connected_to_locked_), // output, width = 1, locked.export + .rst (_connected_to_rst_), // input, width = 1, reset.reset + .outclk_0 (_connected_to_outclk_0_), // output, width = 1, outclk0.clk + .outclk_1 (_connected_to_outclk_1_), // output, width = 1, outclk1.clk + .outclk_2 (_connected_to_outclk_2_), // output, width = 1, outclk2.clk + .outclk_3 (_connected_to_outclk_3_), // output, width = 1, outclk3.clk + .outclk_4 (_connected_to_outclk_4_) // output, width = 1, outclk4.clk + ); + diff --git a/corev_apu/altera/ip/io_pll/io_pll_inst.vhd b/corev_apu/altera/ip/io_pll/io_pll_inst.vhd new file mode 100644 index 0000000000..e1f724eaa1 --- /dev/null +++ b/corev_apu/altera/ip/io_pll/io_pll_inst.vhd @@ -0,0 +1,25 @@ + component io_pll is + port ( + refclk : in std_logic := 'X'; -- clk + locked : out std_logic; -- export + rst : in std_logic := 'X'; -- reset + outclk_0 : out std_logic; -- clk + outclk_1 : out std_logic; -- clk + outclk_2 : out std_logic; -- clk + outclk_3 : out std_logic; -- clk + outclk_4 : out std_logic -- clk + ); + end component io_pll; + + u0 : component io_pll + port map ( + refclk => CONNECTED_TO_refclk, -- refclk.clk + locked => CONNECTED_TO_locked, -- locked.export + rst => CONNECTED_TO_rst, -- reset.reset + outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk + outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk + outclk_2 => CONNECTED_TO_outclk_2, -- outclk2.clk + outclk_3 => CONNECTED_TO_outclk_3, -- outclk3.clk + outclk_4 => CONNECTED_TO_outclk_4 -- outclk4.clk + ); + diff --git a/corev_apu/altera/ip/io_pll/sim/aldec/rivierapro_setup.tcl b/corev_apu/altera/ip/io_pll/sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000000..25420cee5f --- /dev/null +++ b/corev_apu/altera/ip/io_pll/sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,380 @@ + +# (C) 2001-2024 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Intel +# Program License Subscription Agreement, Intel MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Intel and sold by Intel +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 24.1 115 linux 2024.10.15.08:52:05 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# io_pll +# +# Intel recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Intel simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR
+
+ + + + +
+
+
+
All Components +
   + emif_fm_0 + altera_emif_fm 2.7.4 +
   + emif_fm_0_ecc_core + altera_emif_ecc 19.1 +
+