From 834402a5bf295906809542cb66547d1eafc87141 Mon Sep 17 00:00:00 2001 From: ajalali Date: Fri, 6 Dec 2024 16:06:17 +0100 Subject: [PATCH 1/2] [CVXIF] Various fixes for bugs report with CVXIF's UVM agent --- core/cvxif_compressed_if_driver.sv | 16 +++++++++------- core/cvxif_issue_register_commit_if_driver.sv | 2 +- core/id_stage.sv | 13 ++++++++----- core/issue_read_operands.sv | 12 ++++++------ 4 files changed, 24 insertions(+), 19 deletions(-) diff --git a/core/cvxif_compressed_if_driver.sv b/core/cvxif_compressed_if_driver.sv index e874b9b190..26fdeab85b 100644 --- a/core/cvxif_compressed_if_driver.sv +++ b/core/cvxif_compressed_if_driver.sv @@ -21,13 +21,14 @@ module cvxif_compressed_if_driver #( input logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_i, input logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_i, + input logic [CVA6Cfg.NrIssuePorts-1:0] instruction_valid_i, input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_i, output logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_o, output logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_o, output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_o, input logic stall_i, - output logic stall_o, + output logic [CVA6Cfg.NrIssuePorts-1:0] stall_o, // CVXIF Compressed interface input logic compressed_ready_i, input x_compressed_resp_t compressed_resp_i, @@ -43,9 +44,10 @@ module cvxif_compressed_if_driver #( compressed_valid_o = 1'b0; compressed_req_o.instr = '0; compressed_req_o.hartid = hart_id_i; - stall_o = stall_i; + stall_o[0] = stall_i; + stall_o[1] = 1'b0; if (is_illegal_i[0]) begin - compressed_valid_o = is_illegal_i[0]; + compressed_valid_o = is_illegal_i[0] && instruction_valid_i[0]; compressed_req_o.instr = instruction_i[0][15:0]; is_illegal_o[0] = ~compressed_resp_i.accept; instruction_o[0] = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i[0]; @@ -53,20 +55,20 @@ module cvxif_compressed_if_driver #( if (~stall_i) begin // Propagate stall from macro decoder or wait for compressed ready if compressed transaction is happening. // Stall if both instruction are illegal + stall_o[0] = (compressed_valid_o && ~compressed_ready_i); if (CVA6Cfg.SuperscalarEn) begin - stall_o = is_illegal_i[1]; - end else begin - stall_o = (compressed_valid_o && ~compressed_ready_i); + stall_o[1] = is_illegal_i[1]; end end end if (CVA6Cfg.SuperscalarEn) begin if (~is_illegal_i[0] && is_illegal_i[1]) begin // 2nd instruction is illegal - compressed_valid_o = is_illegal_i[1]; + compressed_valid_o = is_illegal_i[1] && instruction_valid_i[1]; compressed_req_o.instr = instruction_i[1][15:0]; is_illegal_o[1] = ~compressed_resp_i.accept; instruction_o[1] = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i[1]; is_compressed_o[1] = compressed_resp_i.accept ? 1'b0 : is_compressed_i[1]; + stall_o[1] = (compressed_valid_o && ~compressed_ready_i); end end end diff --git a/core/cvxif_issue_register_commit_if_driver.sv b/core/cvxif_issue_register_commit_if_driver.sv index 2b6ab540d0..16ebaa5bc7 100644 --- a/core/cvxif_issue_register_commit_if_driver.sv +++ b/core/cvxif_issue_register_commit_if_driver.sv @@ -60,7 +60,7 @@ module cvxif_issue_register_commit_if_driver #( // Always do commit transaction with issue // If instruction goes to execute then it is not speculative - assign commit_valid_o = issue_valid_o; + assign commit_valid_o = issue_valid_o && issue_ready_i; assign commit_o.hartid = issue_req_o.hartid; assign commit_o.id = issue_req_o.id; assign commit_o.commit_kill = 1'b0; diff --git a/core/id_stage.sv b/core/id_stage.sv index 43583bde01..6bed74bd4e 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -111,11 +111,12 @@ module id_stage #( logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cvxif; logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr_i; - logic stall_instr_fetch; + logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch; logic stall_macro_deco; logic is_last_macro_instr_o; logic is_double_rd_macro_instr_o; + if (CVA6Cfg.RVC) begin // --------------------------------------------------------- // 1. Check if they are compressed and expand in case they are @@ -166,6 +167,7 @@ module id_stage #( .is_compressed_i (is_compressed_cvxif), .is_illegal_i (is_illegal_cvxif), .instruction_i (instruction_cvxif), + .instruction_valid_i (fetch_entry_valid_i), .is_compressed_o (is_compressed_cmp), .is_illegal_o (is_illegal_cmp), .instruction_o (instruction), @@ -187,6 +189,7 @@ module id_stage #( .hart_id_i (hart_id_i), .is_compressed_i (is_compressed), .is_illegal_i (is_illegal), + .instruction_valid_i (fetch_entry_valid_i), .instruction_i (compressed_instr), .is_compressed_o (is_compressed_cmp), .is_illegal_o (is_illegal_cmp), @@ -290,7 +293,7 @@ module id_stage #( if (issue_n[1].valid) begin issue_n[0] = issue_n[1]; issue_n[1].valid = 1'b0; - end else if (fetch_entry_valid_i[0]) begin + end else if (fetch_entry_valid_i[0] && !stall_instr_fetch[0]) begin fetch_entry_ready_o[0] = 1'b1; issue_n[0] = '{1'b1, decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; end @@ -298,11 +301,11 @@ module id_stage #( if (!issue_n[1].valid) begin if (fetch_entry_ready_o[0]) begin - if (fetch_entry_valid_i[1]) begin + if (fetch_entry_valid_i[1] && !stall_instr_fetch[1]) begin fetch_entry_ready_o[1] = 1'b1; issue_n[1] = '{1'b1, decoded_instruction[1], orig_instr[1], is_control_flow_instr[1]}; end - end else if (fetch_entry_valid_i[0]) begin + end else if (fetch_entry_valid_i[0] && !stall_instr_fetch[0]) begin fetch_entry_ready_o[0] = 1'b1; issue_n[1] = '{1'b1, decoded_instruction[0], orig_instr[0], is_control_flow_instr[0]}; end @@ -325,7 +328,7 @@ module id_stage #( // or the issue stage is currently acknowledging an instruction, which means that we will have space // for a new instruction if ((!issue_q[0].valid || issue_instr_ack_i[0]) && fetch_entry_valid_i[0]) begin - if (stall_instr_fetch) begin + if (stall_instr_fetch[0]) begin fetch_entry_ready_o[0] = 1'b0; end else begin fetch_entry_ready_o[0] = 1'b1; diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index fa357f42fb..8ea332dc03 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -679,7 +679,7 @@ module issue_read_operands stall_rs3[0] = 1'b0; end end - stall_raw[0] = stall_rs1[0] || stall_rs2[0] || stall_rs3[0]; + stall_raw[0] = x_transaction_rejected ? 1'b0 : stall_rs1[0] || stall_rs2[0] || stall_rs3[0]; end if (CVA6Cfg.SuperscalarEn) begin @@ -932,16 +932,16 @@ module issue_read_operands end end - if (CVA6Cfg.SuperscalarEn) begin - if (!issue_ack[0]) begin - issue_ack[1] = 1'b0; - end - end issue_ack_o = issue_ack; // Do not acknoledge the issued instruction if transaction is not completed. if (issue_instr_i[0].fu == CVXIF && !(x_transaction_accepted_o || x_transaction_rejected)) begin issue_ack_o[0] = issue_instr_i[0].ex.valid && issue_instr_valid_i[0]; end + if (CVA6Cfg.SuperscalarEn) begin + if (!issue_ack_o[0]) begin + issue_ack_o[1] = 1'b0; + end + end end // ---------------------- From 6b01db0e09648f0bdb9a961f35d2eceba77f6af3 Mon Sep 17 00:00:00 2001 From: Guillaume Chauvon Date: Thu, 19 Dec 2024 14:01:21 +0100 Subject: [PATCH 2/2] Update options and simulators to support CVXIF's UVM agent --- .gitlab-ci.yml | 6 ------ verif/regress/cvxif_verif_regression.sh | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8f7e6d5824..c3f0a6a391 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -250,12 +250,6 @@ cvxif-regression: DASHBOARD_SORT_INDEX: 5 DASHBOARD_JOB_CATEGORY: "Basic" COLLECT_SIMU_LOGS: 1 - SPIKE_TANDEM: 1 - parallel: - matrix: - - DV_SIMULATORS: - - "veri-testharness,spike" - - "vcs-testharness" script: - bash verif/regress/cvxif_verif_regression.sh - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone diff --git a/verif/regress/cvxif_verif_regression.sh b/verif/regress/cvxif_verif_regression.sh index 4d7b9e6503..42709d37eb 100644 --- a/verif/regress/cvxif_verif_regression.sh +++ b/verif/regress/cvxif_verif_regression.sh @@ -40,10 +40,10 @@ export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBO cd verif/sim/ make -C ../.. clean make clean_all -python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=vcs-testharness,spike $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld make -C ../.. clean make clean_all -python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=vcs-uvm,spike --issrun_opts="+enabled_cvxif" --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld make -C ../.. clean make clean_all