From 48ac38fb35e90aa70d6af835fdf3e948f2ec08c8 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 03:43:57 -0800 Subject: [PATCH 01/14] Add exceptionsM to fcov --- config/rv32gc/coverage.svh | 7 ++++++- config/rv64gc/coverage.svh | 5 +++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 614cd5c3d..d3953b916 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN32 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 32'h0000 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -39,4 +43,5 @@ `include "RV32VM_PMP_coverage.svh" `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" \ No newline at end of file +`include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 07561b1de..3974d7f96 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN64 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 64'h00000000 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -39,6 +43,7 @@ `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 034624523397179fc4ce5c85daff0979cfb8e7ce Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 16:36:59 -0800 Subject: [PATCH 02/14] removed unused and redundant clint base variable --- config/rv32gc/coverage.svh | 1 - config/rv64gc/coverage.svh | 1 - 2 files changed, 2 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index d3953b916..b05362f8d 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -9,7 +9,6 @@ `define XLEN32 1 // Define relevant addresses -`define CLINT_BASE 64'h02000000 `define ACCESS_FAULT_ADDRESS 32'h0000 // Unprivileged extensions diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 3974d7f96..85abee104 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,7 +9,6 @@ `define XLEN64 1 // Define relevant addresses -`define CLINT_BASE 64'h02000000 `define ACCESS_FAULT_ADDRESS 64'h00000000 // Unprivileged extensions From c105c4c720e945570311ca2f804219346cdc5826 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 17:04:12 -0800 Subject: [PATCH 03/14] restored clint base for interrupt tests --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index b05362f8d..0403b7e4b 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -10,6 +10,7 @@ // Define relevant addresses `define ACCESS_FAULT_ADDRESS 32'h0000 +`define CLINT_BASE 64'h02000000 // Unprivileged extensions `include "RV32I_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 85abee104..e7c574020 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -10,6 +10,7 @@ // Define relevant addresses `define ACCESS_FAULT_ADDRESS 64'h00000000 +`define CLINT_BASE 64'h02000000 // Unprivileged extensions `include "RV64I_coverage.svh" From 7be6311f51807104317d81705603a4f21de2c826 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:11:50 -0800 Subject: [PATCH 04/14] Update cvw-arch-verif submodule --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 6d658b7b4..812f30af7 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769 +Subproject commit 812f30af765c0a692c506e42493f494278c00fe0 From 55fb7e07b3dca67557d6131c62eeae87cc8c5163 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:12:52 -0800 Subject: [PATCH 05/14] Add cvw-arch-verif to main Makefile --- Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 323b18b1d..52513a812 100644 --- a/Makefile +++ b/Makefile @@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory SIM = ${WALLY}/sim -.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean +.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean -all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks +all: riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif # benchmarks # riscof builds the riscv-arch-test and wally-riscv-arch-test suites riscof: @@ -36,6 +36,10 @@ embench: coverage: $(MAKE) -C tests/coverage +cvw-arch-verif: + $(MAKE) -C ${WALLY}/addins/cvw-arch-verif + clean: $(MAKE) clean -C sim $(MAKE) clean -C ${WALLY}/tests/fp + $(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif From 53fe1c2598ff186c3b413ea0e0343807f4ac9118 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 17 Nov 2024 00:00:40 -0800 Subject: [PATCH 06/14] Add dependabot file --- .github/dependabot.yml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 .github/dependabot.yml diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..a91ebaf1d --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,17 @@ +# To get started with Dependabot version updates, you'll need to specify which +# package ecosystems to update and where the package manifests are located. +# Please see the documentation for all configuration options: +# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file + +version: 2 +updates: + # Update git submodules to latest version + - package-ecosystem: "gitsubmodule" + directory: "/" + schedule: + interval: "weekly" + # Update actions in the GitHub Actions workflow files + - package-ecosystem: "github-actions" + directory: "/" + schedule: + interval: "weekly" From aa72ed1c19d49db60420322857884416ffc6073e Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 16:36:14 +0000 Subject: [PATCH 07/14] Bump addins/verilog-ethernet from `c180b22` to `6f5ea41` Bumps [addins/verilog-ethernet](https://github.com/rosethompson/verilog-ethernet) from `c180b22` to `6f5ea41`. - [Commits](https://github.com/rosethompson/verilog-ethernet/compare/c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d...6f5ea41584c49543e63415e37356ebb24b07d89d) --- updated-dependencies: - dependency-name: addins/verilog-ethernet dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/verilog-ethernet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index c180b22ed..6f5ea4158 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d +Subproject commit 6f5ea41584c49543e63415e37356ebb24b07d89d From 7d80a8992a535710eed2702106ce8359b5a45aa0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:55:46 -0800 Subject: [PATCH 08/14] Remove FreeRTOS --- .gitmodules | 3 --- addins/FreeRTOS-Kernel | 1 - 2 files changed, 4 deletions(-) delete mode 160000 addins/FreeRTOS-Kernel diff --git a/.gitmodules b/.gitmodules index 34a374174..5a1e8d4dc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,9 +8,6 @@ [submodule "addins/coremark"] path = addins/coremark url = https://github.com/eembc/coremark -[submodule "addins/FreeRTOS-Kernel"] - path = addins/FreeRTOS-Kernel - url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git [submodule "addins/vivado-boards"] path = addins/vivado-boards url = https://github.com/Digilent/vivado-boards/ diff --git a/addins/FreeRTOS-Kernel b/addins/FreeRTOS-Kernel deleted file mode 160000 index 17a46c252..000000000 --- a/addins/FreeRTOS-Kernel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31 From 015b3f0d680f94a93720abf2434962d6b87c49d7 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 16:59:13 +0000 Subject: [PATCH 09/14] Bump addins/vivado-boards from `e5f0728` to `8ed4f99` Bumps [addins/vivado-boards](https://github.com/Digilent/vivado-boards) from `e5f0728` to `8ed4f99`. - [Commits](https://github.com/Digilent/vivado-boards/compare/e5f0728cd284d10080ae8eb03fc86e7b5eafcb72...8ed4f9981da1d80badb0b1f65e250b2dbf7a564d) --- updated-dependencies: - dependency-name: addins/vivado-boards dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/vivado-boards | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/vivado-boards b/addins/vivado-boards index e5f0728cd..8ed4f9981 160000 --- a/addins/vivado-boards +++ b/addins/vivado-boards @@ -1 +1 @@ -Subproject commit e5f0728cd284d10080ae8eb03fc86e7b5eafcb72 +Subproject commit 8ed4f9981da1d80badb0b1f65e250b2dbf7a564d From 7358c1fe67208bbd3e2284b6ebcc01e1020afd34 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 25 Nov 2024 15:50:29 -0600 Subject: [PATCH 10/14] Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status. --- fpga/zsbl/spi.c | 2 +- fpga/zsbl/spi.h | 2 +- src/uncore/spi_fifo.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 04d609648..4e75086ad 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -31,7 +31,7 @@ uint8_t spi_txrx(uint8_t byte) { spi_sendbyte(byte); - waittx(); + waitrx(); return spi_readbyte(); } diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index f9e88fa6d..5a472142f 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -106,7 +106,7 @@ static inline void waittx() { } static inline void waitrx() { - while(read_reg(SPI_IP) & 2) {} + while(!(read_reg(SPI_IP) & 2)) {} } static inline uint8_t spi_readbyte() { diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv index 1e4910faf..514e9df7b 100644 --- a/src/uncore/spi_fifo.sv +++ b/src/uncore/spi_fifo.sv @@ -26,7 +26,7 @@ module spi_fifo #(parameter M=3, N=8)( // 2^M entries of N bits assign rdata = mem[raddr]; always_ff @(posedge PCLK) - if (winc & ~wfull) mem[waddr] <= wdata; + if (winc & wen & ~wfull) mem[waddr] <= wdata; // write and read are enabled always_ff @(posedge PCLK) From 58628ed37001437f36e238cfefc2913f901ef5f1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 15:43:11 -0800 Subject: [PATCH 11/14] Remove riscvISACOV submodule --- .gitmodules | 3 --- addins/riscvISACOV | 1 - 2 files changed, 4 deletions(-) delete mode 160000 addins/riscvISACOV diff --git a/.gitmodules b/.gitmodules index 5a1e8d4dc..672ec445f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -26,9 +26,6 @@ path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif ignore = dirty -[submodule "addins/riscvISACOV"] - path = addins/riscvISACOV - url = https://github.com/riscv-verification/riscvISACOV.git [submodule "addins/berkeley-softfloat-3"] path = addins/berkeley-softfloat-3 url = https://github.com/ucb-bar/berkeley-softfloat-3.git diff --git a/addins/riscvISACOV b/addins/riscvISACOV deleted file mode 160000 index ac9fa2d38..000000000 --- a/addins/riscvISACOV +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ac9fa2d386c0cb2f44e1e1e83a555d585034dfa3 From 6e1d2efc002457e6a361c2efc16f024cad92fd9b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 20:29:55 -0800 Subject: [PATCH 12/14] Update wally.do to use new isacov location --- sim/questa/wally.do | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 6f613c404..f42bf4930 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -110,9 +110,8 @@ if {[lcheck lst "--fcov"]} { set FCvlog "+define+INCLUDE_TRACE2COV \ +define+IDV_INCLUDE_TRACE2COV \ +define+COVER_BASE_RV32I \ - +incdir+$env(WALLY)/addins/riscvISACOV/source \ + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ " - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" } From 6b792f876038fabc159368555d1c28300a12e932 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 20:33:36 -0800 Subject: [PATCH 13/14] Update cvw-arch-verif to version with isacov --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 812f30af7..d6bae481c 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 812f30af765c0a692c506e42493f494278c00fe0 +Subproject commit d6bae481c784461a2d2be14325041ea284319098 From daddbed8e67e0eaafbf60ca142886fa190f7ad21 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 26 Nov 2024 08:15:36 -0800 Subject: [PATCH 14/14] Revert "Bump addins/verilog-ethernet from `c180b22` to `6f5ea41`" --- addins/verilog-ethernet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index 6f5ea4158..c180b22ed 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit 6f5ea41584c49543e63415e37356ebb24b07d89d +Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d