Welcome to CORE-V Wally Discussions

[MikeOpenHWGroup]

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[burkettttt]

looking over wally-tool-chain-install.sh and it is decidely Ubuntu in flavor. Is there a RHEL 8 modified version making use of dnf, *-devel, and RHEL 8 named versions of the libraries and tools needed? I realize some of these tools may need to be compiled from source on RHEL 8 if there's not an equivalent. Not looking to avoid the effort, just don't want to re-invent what may already be available.
Thanks for your time.

[stineje]

Hi, Thanks for the Email. Our version currently uses buildroot but I am sure it can be easily ported to other flavors. We had a desire to port a RTOS but have not done this one yet. All items should be contained in the repository and if you need any help, let us know. Take care. All my best, James

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On Aug 11, 2023, at 11:12 AM, burkettttt ***@***.***> wrote: CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe looking over wally-tool-chain-install.sh and it is decidely Ubuntu in flavor. Is there a RHEL 8 modified version making use of dnf, *-devel, and RHEL 8 named versions of the libraries and tools needed? I realize some of these tools may need to be compiled from source on RHEL 8 if there's not an equivalent. Not looking to avoid the effort, just don't want to re-invent what may already be available. Thanks for your time. — Reply to this email directly, view it on GitHub <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fopenhwgroup%2Fcvw%2Fdiscussions%2F253%23discussioncomment-6703384&data=05%7C01%7Cjames.stine%40okstate.edu%7C6ed2ae2e754747701d4d08db9a85d192%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638273671758701939%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=kxYnv3s9ntVceGeJs6Ww61BtB%2BVoS1kCdwcxU3gD3DE%3D&reserved=0>, or unsubscribe <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fnotifications%2Funsubscribe-auth%2FAFSIHPGCW35MTUKOUMOB6PDXUZKYHANCNFSM6AAAAAAXCVCCGI&data=05%7C01%7Cjames.stine%40okstate.edu%7C6ed2ae2e754747701d4d08db9a85d192%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638273671758701939%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=tjG7ZMFLQcBDvpZzW9%2FWFuvpZxnp2SMDiLXaNT3P2Z0%3D&reserved=0>. You are receiving this because you are subscribed to this thread.

[davidharrishmc]

I think James answered with respect to booting buildroot Linux on the processor. If the question is with respect to the development environment, we’ve had great difficulty getting Sail running reliably on RHEL and Sail is a required component of the riscof verification flow. The difficulties occurred even trying to build from source. Therefore we migrated to Ubuntu. If you are a RHEL and Sail whiz and can get them running reliably together, we’d be thrilled to add it. David

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On Aug 11, 2023, at 9:57 AM, James E. Stine ***@***.***> wrote: Hi, Thanks for the Email. Our version currently uses buildroot but I am sure it can be easily ported to other flavors. We had a desire to port a RTOS but have not done this one yet. All items should be contained in the repository and if you need any help, let us know. Take care. All my best, James > On Aug 11, 2023, at 11:12 AM, burkettttt ***@***.***> wrote: > > CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe > > looking over wally-tool-chain-install.sh and it is decidely Ubuntu in flavor. Is there a RHEL 8 modified version making use of dnf, *-devel, and RHEL 8 named versions of the libraries and tools needed? I realize some of these tools may need to be compiled from source on RHEL 8 if there's not an equivalent. Not looking to avoid the effort, just don't want to re-invent what may already be available. > Thanks for your time. > > — > Reply to this email directly, view it on GitHub <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fopenhwgroup%2Fcvw%2Fdiscussions%2F253%23discussioncomment-6703384&data=05%7C01%7Cjames.stine%40okstate.edu%7C6ed2ae2e754747701d4d08db9a85d192%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638273671758701939%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=kxYnv3s9ntVceGeJs6Ww61BtB%2BVoS1kCdwcxU3gD3DE%3D&reserved=0>, or unsubscribe <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fnotifications%2Funsubscribe-auth%2FAFSIHPGCW35MTUKOUMOB6PDXUZKYHANCNFSM6AAAAAAXCVCCGI&data=05%7C01%7Cjames.stine%40okstate.edu%7C6ed2ae2e754747701d4d08db9a85d192%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638273671758701939%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=tjG7ZMFLQcBDvpZzW9%2FWFuvpZxnp2SMDiLXaNT3P2Z0%3D&reserved=0>. > You are receiving this because you are subscribed to this thread. > — Reply to this email directly, view it on GitHub <#253 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA37PMN5YYTVS6N6XNFDXUZP7LANCNFSM6AAAAAAXCVCCGI>. You are receiving this because you are subscribed to this thread.

[burkettttt]

Thanks to both of you for the replies. David is closer to what I was looking for. I know RHEL, but Sail is something brand new to me. Systems Administrator in classroom support, not a wiz outside of that. Had a request to see about loading CVW on the RHEL systems. There are some restricted lab systems running UBUNTU, but not once I admin. I'll pass along your reply David and see what the Faculty and TAs want to do going forward.

[davidharrishmc]

Getting everything running for CORE-V Wally is not trivial and seems to break in different ways on each system we’ve tried to use it on. I would be happy to support installing on Ubuntu, especially so I can improve the installation documentation with any difficulties specific to your systems. Take a look at the Sail installation and consider attempting to install it on your RHEL system. It has given us and others a lot of grief on that platform. I’ve spoken with the developer, and there is no immediate plan for better support. David Harris

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On Aug 16, 2023, at 1:42 PM, burkettttt ***@***.***> wrote: Thanks to both of you for the replies. David is closer to what I was looking for. I know RHEL, but Sail is something brand new to me. Systems Administrator in classroom support, not a wiz outside of that. Had a request to see about loading CVW on the RHEL systems. There are some restricted lab systems running UBUNTU, but not once I admin. I'll pass along your reply David and see what the Faculty and TAs want to do going forward. — Reply to this email directly, view it on GitHub <#253 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA363XYU3OJJBF3C45YTXVUWD7ANCNFSM6AAAAAAXCVCCGI>. You are receiving this because you commented.

[burkettttt]

David: Appreciate the offer of help. I will certainly take you up on it. I need to step back from this project for a few weeks though because classes start on Monday and will be a bit chaotic. I'll get back to you when I start back on this.

[jiande-my]

Hi,

I am a final year Computer Engineering student with a keen interest in computer architecture. I came across a project titled 'CORE-V Wally Technology Readiness Level 5' in the LFX mentorship program and would like to contribute to it. My skills include C, Python, and SystemVerilog. Could you provide more details about this project, along with study materials, references, or any guides to help me get started?

Jian De

[davidharrishmc]

Jian, Nice to meet you. The project description has everything I know about the project right now. The Wally Git repository and RISC-V specifications might give you more of a sense of the project. David Harris

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On Jan 9, 2024, at 9:33 AM, Jian De ***@***.***> wrote: Hi, I am a final year Computer Engineering student with a keen interest in computer architecture. I came across a project titled 'CORE-V Wally Technology Readiness Level 5 <https://mentorship.lfx.linuxfoundation.org/project/cc564a0f-72d5-4588-ad83-0e5bb0257df2>' in the LFX mentorship program and would like to contribute to it. My skills include C, Python, and SystemVerilog. Could you provide more details about this project, along with study materials, references, or any guides to help me get started? Jian De — Reply to this email directly, view it on GitHub <#253 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA37NAW6UULIFRI45BETYNV5OZAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4DANRZG44DE>. You are receiving this because you commented.

[stineje]

Hi, Great to hear from you. Much of the description on the items will be included in our upcoming textbook. You are welcome to ask questions and we will do all we can to help. It should be at the https://github.com/openhwgroup/cvw webpage. There are constant updates so things are usually working but may break periodically. Let us know if we can help. Take care. J

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On Mar 18, 2024, at 10:58 AM, Zoro210 ***@***.***> wrote: Is there any specification or reference, I am trying to analyse the whole code, can anyone suggest. — Reply to this email directly, view it on GitHub <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fopenhwgroup%2Fcvw%2Fdiscussions%2F253%23discussioncomment-8830049&data=05%7C02%7Cjames.stine%40okstate.edu%7Cb43c8b06d81547c9ebcc08dc4764347a%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638463742917965666%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=8x2wAxQNhZR5U5JVnE5h3lqkZoNvNUpnBUUZLci%2BWUA%3D&reserved=0>, or unsubscribe <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fnotifications%2Funsubscribe-auth%2FAFSIHPBVMEDELRTJURVV5CLYY4FI5AVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4DQMZQGA2DS&data=05%7C02%7Cjames.stine%40okstate.edu%7Cb43c8b06d81547c9ebcc08dc4764347a%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638463742917976683%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=46iOowZ5YpqkL9Vhj%2FVLaMitNGm0ReAqJOCwlgyxvhY%3D&reserved=0>. You are receiving this because you commented.

[stineje]

Hi, Great to hear from you again. Our book is with the publisher and will hopefully be out soon. Is there something I can help you with in the mean time? Did you build the toolchain? Please let me know - happy to help! Take care. All my best, James

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On Mar 18, 2024, at 11:30 PM, Zoro210 ***@***.***> wrote: In the code, they have mentioned RISC-V System on Chip Design Chapter 7 like that. Can I get the documentation of that book or can I know where to find it? — Reply to this email directly, view it on GitHub <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fopenhwgroup%2Fcvw%2Fdiscussions%2F253%23discussioncomment-8835702&data=05%7C02%7Cjames.stine%40okstate.edu%7Cc2dd05743fe44fe0b3e808dc47cd5359%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638464194393207925%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=bzVyUtucdc%2FROKAOEiDOh4KGv1gvfn0of0opAi7%2BDlI%3D&reserved=0>, or unsubscribe <https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fnotifications%2Funsubscribe-auth%2FAFSIHPHHSBTYFPQYWQFAXSDYY65OXAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4DQMZVG4YDE&data=05%7C02%7Cjames.stine%40okstate.edu%7Cc2dd05743fe44fe0b3e808dc47cd5359%7C2a69c91de8494e34a230cdf8b27e1964%7C0%7C0%7C638464194393218536%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=gcJdp6f%2Biy4ecJPP1LJkVxbNa0TYLC0edaIOgQTkbhM%3D&reserved=0>. You are receiving this because you commented.

[davidharrishmc]

LSUHWSTRB is the HWSTRB signal from the LSU to the AHB port to control which bytes are written (for example, when doing a store halfword over a 64-bit interface). Wally is configurable to have a data cache or not (P.DCACHE_SUPPORTED). The logic to control HWSTRB is different in systems with and without a cache. Wally instantiates either ahbcacheinterface or ahbinterface, accordingly.

[davidharrishmc]

DCACHE_SUPPORTED is set in the config file. There’s a lot going on here that will be documented in the textbook. What is your application for Wally? If you’re an individual looking to experiment with open hardware, it would be easiest to wait until the book comes out next year. If you are part of an organization looking for a collaboration, let’s talk about how to support you before the book is available. Feel free to email me directly at my Harvey Mudd College address. David Harris

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On Apr 3, 2024, at 9:37 PM, Zoro210 ***@***.***> wrote: Thank you for your response. So, how will the core know if there is cache or not and how the HWSTRB will be selected based on with or without cache? I didn't find any logic regarding this. — Reply to this email directly, view it on GitHub <#253 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA34GKYCVDZVZEU2V2BLY3TKJLAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4TAMBUG43TG>. You are receiving this because you commented.

[shriyan111]

Heyy
Im just going through the core v wally here i have one doubt can you please clear this
what is the difference between P.FLEN and P.LLEN and P.XLEN is this size are same but name given F ,L,X is with respect to floating point and load and store instructions or is there any other difference here?

for example:
input logic [P.FLEN-1:0] ReadDataW,
output logic [P.LLEN-1:0] ReadDataW,

[davidharrishmc]

XLEN is the RISC-V standard: 32 for RV32 or 64 for RV64
FLEN is also the RISC-V standard: 32 for F, 64 for FD, or 128 for FDQ
LLEN = max(XLEN, FLEN) is the size of the largest word transferred through the load/store unit

[shriyan111]

Thank you for clearing my doubt.

[shriyan111]

Hello

I have some doubt in the IEU's datapath file in line no 130,

mux2 #(P.XLEN) divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);

here if I want to work on only MDU unit without FPU how can I control IntDivW ?

it is internal variable in IEU right? is there any way of making it everytime low with respect to my case.

in controller it is calculated like IntdivE = MDUE&funct3E[2].

after 2 stage same intdivE value is taken as IntdivW so everytime IntdivE is changing right? could you please clarify this for me.

[Prasadbindu]

Machine Mode Registers should not be read while the core is in Supervisor Mode or User Mode. However, based on the RTL, it appears that the Machine Mode Registers are being read in both User Mode and Supervisor Mode. I have been able to read Machine Mode registers such as MSTATUS, MEDELEG, MVENDORID, MISA, and MARCHID. Can you explain why this is happening?

[rosethompson]

@Prasadbindu This sounds like a bug. This should have caused IllegalCSRAccessM (see privileged/csr.sv) to rise and subsequently assert TrapM. I will investigate.

[rosethompson]

@Prasadbindu I am not able to reproduce the bug you are seeing. I used the following code to attempt to trigger the issue you described. However, CVW traps on the csr read of mstatus in the user_mode_entry section. The code first forces a switch to user mode then reads m mode registers.

switch_modes_read_csrs:

        # start by writing 0 to mstatus to set to previous mode to 00 (user)
        csrrw   t0, mstatus, zero
        la      t1, user_mode_entry
        csrrw   t0, mepc, t1
        mret

.align 2
user_mode_entry:
        nop
        nop
        nop
        # read mstatus
        csrr t2, mstatus
        csrr t3, medeleg

	ret

The following code in privileged/csr.sv checks csr premissions and appears to be correct. Can you provide the code your causes the failure?

  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) |
                                     (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE);

[Prasadbindu]

We are also getting the trap and the cause, but we are additionally receiving the CSR read value, whether it is an expected behavior?

We are not verifying the entire Walley core SOC design; we are only verifying the privileged module using a UVM testbench. In the testbench, I am able to read the CSR values(along with trap) from S mode. The sequence is as follows:

Set mstatus.MPP to 01
Set the mideleg register
Call the mret instruction to enter S mode
Read mvendorid
Read marchid

[davidharrishmc]

I believe it is expected and harmless that you are receiving the CSR read value at the same time as a trap. The trap will flush the pipeline, preventing the read value from being written to the register file. The flush logic is outside the privileged module, so your UVM testbench will have no way of knowing about the flush.

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On May 22, 2024, at 7:36 AM, Prasadbindu ***@***.***> wrote: We are also getting the trap and the cause, but we are additionally receiving the CSR read value, whether it is an expected behavior? We are not verifying the entire Walley core SOC design; we are only verifying the privileged module using a UVM testbench. In the testbench, I am able to read the CSR values(along with trap) from S mode. The sequence is as follows: Set mstatus.MPP to 01 Set the mideleg register Call the mret instruction to enter S mode Read mvendorid Read marchid — Reply to this email directly, view it on GitHub <#253 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA32QICHCWK6AI2MHWB3ZDQVEPAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4TKMJWGY2DQ>. You are receiving this because you commented.

[Prasadbindu]

Thank you for clarifying the doubt.

[Prasadbindu]

@ross144 @MikeOpenHWGroup I am planning to verify the entire Walley core SOC. I would greatly appreciate it if you could provide me with some insights and guidance on how to start the SOC verification process.

[rosethompson]

Hi Prasadbindu, we already have a fairly robust simulation infrastructure which we are continuing to improve. We have several scripts which help automate testing.
wsim: launches a single instance of a simulator, Questa, VCS, or Verilator with a variety of different command options. Questa is currently fully supported and VCS and Verilator are in progress.
wsim takes two required parameters . The is a configuration of Wally found in the cvw/config or cvw/config/deriv directories. This defines all the parameters for this version of Wally. specifies which tests to run. testsuites are defined in cvw/testbench/tests.vh. For example you can run

wsim rv64gc arch64i

to run the 64-bit applications config with the riscv-arch-test integer tests.

To simulate a single elf file run wsim rv64gc --elf

wsim takes many different options. For example --gui will launch in gui mode with a waveform. --lockstep will run with ImperasDV (can only be run with a single elf file). --coverage will collect code coverage (still working on functional coverage). wsim -h will list all options.

The cvw/README.md has several examples at the end.

To run all the standard regression tests we have another script regression-wally. This launches multiple parallel jobs equal to the number of CPU threads. This also takes options --coverage and --fpu to collect code coverage. Coverage is reported in cvw/sim/questa/cov/rv64gc_coverage_hierarchical.rpt

Both scripts are located in cvw/bin and are part of the path after sourcing cvw/setup.sh

Our recommended flow is to copy cvw/site-setup.sh to a global location on your system. By default we use RISCV=/opt/riscv
Then set any required licenses and paths in this file.

Each time you open a terminal then run

source ./setup.sh

to place required tools in the PATH variable.

[Prasadbindu]

Thank you for your valuable input

[Prasadbindu]

@ross144 @MikeOpenHWGroup As per your guidance I started with the SoC Verification. After Doing the setup we ran wsim rv32gc arch32i. I am getting the below error.
Error: Failed to open file "../../tests/riscof/work/rtscv-arch-test/rv321_m/1/src/add-01.S/ref/ref.elf.objdump.lab" for reading
Within riscof directory there is no work directory. Do we need to run any commands/scripts to create these directories. Kindly Guide us.

[shriyan111]

Hello,
Here im trying to verify both single precision and double precision , double precision is verified successfully but in single precision not a number (NaN) signal is high every time ,is there any way of controlling this?.

[davidharrishmc]

Did you nan box the single precision numbers?

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On Thu, May 30, 2024 at 11:11 AM shriyan111 ***@***.***> wrote: Hello, Here im trying to verify both single precision and double precision , double precision is verified successfully but in single precision not a number (NaN) signal is high every time ,is there any way of controlling this?. — Reply to this email directly, view it on GitHub <#253 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA35RN4YKPVIU3BGEHRTZE3UG7AVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4TMMBTGQ4TK> . You are receiving this because you commented.Message ID: ***@***.***>

[shriyan111]

Oh! i didn't now its working.
Thank you.

[davidharrishmc]

You can try running your tests on spike or sail before running them on the Wally verilog. That will help you avoid problems like this. David

…

On Thu, May 30, 2024 at 12:12 PM shriyan111 ***@***.***> wrote: Oh! i didn't now its working. Thank you. — Reply to this email directly, view it on GitHub <#253 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA33YGS3ONI5I4FGUUO3ZE33QDAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43SRDJONRXK43TNFXW4Q3PNVWWK3TUHM4TMMBUGEYTG> . You are receiving this because you commented.Message ID: ***@***.***>

[shriyan111]

Ok,sure i will.
Thank you

[Prasadbindu]

Hello,
Actually I am verifying cache sub block .while i am giving inputs through [255:0] fetch-buffer but it is updating the same data to four way cache .it not updating different data in four way cache. what may be the reason !

and i saw in cvw file 4096 instructions per way .each cache way requires 4096 instructions or more .

[rosethompson]

I am a bit confused by what you are saying. The cache issues bus requests and pickups up bus read data on the fetch buffer. It then writes that data into one of the ways. If the access is load or amo it also muxes the correct word out.

The way size is configured in bytes not instructions per way. The default is 4096 bytes per way.

[AishwaryaPrabhu1]

Hello,
The wallyriscvtopall block diagram has SDC block in it. But no code for it is explicitly present for SDC under uncore. Kindly throw some light on this.

[rosethompson]

The code for the SDC block is a git submodule in cvw/addins/ahbsdc. We are in the process of changing this code right now, but the current repo works are as follows.
The SDC block is only used in the FPGA and interfaces to axi. We use multiple Xilinx IP to convert from axi to ahb, clock conversion, bus widths, xbar, etc to communicate. The uncore still knows about the SDC and treats it like a standard AHB peripheral when used in the FPGA.

[davidharrishmc]

After you installed the tools, did you run make? Did it give you any errors or warnings? It should invoke riscof and create files under tests/riscof/work. If it didn’t, you’ll need to troubleshoot why.

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On Jul 22, 2024, at 3:40 AM, Prasadbindu ***@***.***> wrote: @ross144 <https://github.com/ross144> @MikeOpenHWGroup <https://github.com/MikeOpenHWGroup> As per your guidance I started with the SoC Verification. After Doing the setup we ran wsim rv32gc arch32i. I am getting the below error. There is no work directory created under riscof Error: Failed to open file "../../tests/riscof/work/rtscv-arch-test/rv321_m/1/src/add-01.S/ref/ref.elf.objdump.lab" for reading Whether we need run other commands along with this or some other changes needs to be done. Kindly Guide us. — Reply to this email directly, view it on GitHub <#253 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA32M7NLS5VTF24RTRVLZNTORFAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTAMJRGM2DSMQ>. You are receiving this because you commented.

[Prasadbindu]

when we are running make command it is throwing the following error...
make riscof
make[1]: Entering directory '/home/mavenadmin/wally_core/cvw'
make -C sim
make[2]: Entering directory '/home/mavenadmin/wally_core/cvw/sim'
make -C ../tests/riscof/
make[3]: Entering directory '/home/mavenadmin/wally_core/cvw/tests/riscof'
mkdir -p ./riscof_work
mkdir -p ./work
mkdir -p ./work/riscv-arch-test
mkdir -p ./work/wally-riscv-arch-test
sed 's,{0},/home/mavenadmin/wally_core/cvw/tests/riscof,g;s,{1},32gc,g' config.ini > config32.ini
sed 's,{0},/home/mavenadmin/wally_core/cvw/tests/riscof,g;s,{1},64gc,g' config.ini > config64.ini
sed 's,{0},/home/mavenadmin/wally_core/cvw/tests/riscof,g;s,{1},32e,g' config.ini > config32e.ini
riscof run --work-dir=./riscof_work --config=config32.ini --suite=../../addins/riscv-arch-test/riscv-test-suite/ --env=../../addins/riscv-arch-test/riscv-test-suite/env --no-browser
make[3]: riscof: Command not found
make[3]: *** [Makefile:28: arch32] Error 127
make[3]: Leaving directory '/home/mavenadmin/wally_core/cvw/tests/riscof'
make[2]: *** [Makefile:121: riscoftests] Error 2
make[2]: Leaving directory '/home/mavenadmin/wally_core/cvw/sim'
make[1]: *** [Makefile:16: riscof] Error 2
make[1]: Leaving directory '/home/mavenadmin/wally_core/cvw'
make: *** [Makefile:8: all] Error 2

[davidharrishmc]

It says riscof: Command not found. You must not have installed riscof. Did you go through all the steps in bin/wally-tool-chain-install.sh? Many RISC-V tools are fussy, and it’s safest on a new platform to enter the commands one by one and watch for errors and warnings. What platform are you running on? riscof depends on Sail, which is especially touchy to install, particularly on RedHat distros.

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On Jul 22, 2024, at 5:09 AM, Prasadbindu ***@***.***> wrote: when we are running make command it is throwing the following error... make riscof make[1]: Entering directory '/home/mavenadmin/wally_core/cvw' make -C sim make[2]: Entering directory '/home/mavenadmin/wally_core/cvw/sim' make -C ../tests/riscof/ make[3]: Entering directory '/home/mavenadmin/wally_core/cvw/tests/riscof' mkdir -p ./riscof_work mkdir -p ./work mkdir -p ./work/riscv-arch-test mkdir -p ./work/wally-riscv-arch-test sed 's,{0},/home/mavenadmin/wally_core/cvw/tests/riscof,g;s,{1},32gc,g' config.ini > config32.ini sed 's,{0},/home/mavenadmin/wally_core/cvw/tests/riscof,g;s,{1},64gc,g' config.ini > config64.ini sed 's,{0},/home/mavenadmin/wally_core/cvw/tests/riscof,g;s,{1},32e,g' config.ini > config32e.ini riscof run --work-dir=./riscof_work --config=config32.ini --suite=../../addins/riscv-arch-test/riscv-test-suite/ --env=../../addins/riscv-arch-test/riscv-test-suite/env --no-browser make[3]: riscof: Command not found make[3]: *** [Makefile:28: arch32] Error 127 make[3]: Leaving directory '/home/mavenadmin/wally_core/cvw/tests/riscof' make[2]: *** [Makefile:121: riscoftests] Error 2 make[2]: Leaving directory '/home/mavenadmin/wally_core/cvw/sim' make[1]: *** [Makefile:16: riscof] Error 2 make[1]: Leaving directory '/home/mavenadmin/wally_core/cvw' make: *** [Makefile:8: all] Error 2 — Reply to this email directly, view it on GitHub <#253 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA33PURPMDG4LBD3QZ73ZNTY6DAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTAMJRGQZDQNA>. You are receiving this because you commented.

[AishwaryaPrabhu1]

Thanks for your inputs. Earlier we have missed to run bin/wally-tool-chain-install.sh. Now we have executed each and every step in the script. Though initially we have faced some issues in some of the steps, we were able to fix and proceed further.

And now, we are able to use wsim and run simulations. But now we want to implement UVM based testbench for this SOC and explore how to add new testcases to verify the peripheral communication. It will be really helpful if there is any document or README file which explains how this testbench and various testcases are implemented and running. Please guide us in this regard.

[davidharrishmc]

Glad you were able to install the RISC-V tools. If there were any specific changes you had to make that you recorded, we’d appreciate hearing which OS/version you are running and exactly what you had to do. We are working on a more robust installation script that has been tested against more OS versions. Unfortunately there is not formal documentation of the testbench and there won’t be anything elaborate in the near future. The general principle is simple. The testbench reads an ELF that has been converted to hexadecimal (“elf.memfile”) format into memory. It generates a clock, applies reset, runs, and checks if the halting condition for that testbench is satisfied (such as a j self-loop at the end of riscv-arch-test), and reports the status. There are many additional features in this testbench. For example, there are links to RVVI to run tests in lockstep with ImperasDV or collect functional coverage. There is a module to decode instructions to display them in waveforms for easier debugging. There is a riscvassertions module that checks for illegal combinations of configuration parameters. At the end of a sim, some data is in the cache rather than main memory, and there is a module that flushes the cache to main memory to simplify checking signatures for riscv-arch-test. You won’t need any of these extra features in UVM. I would suggest that if the current testbench isn’t satisfactory for your needs, create a new one. Start with the basic features of putting a test in main memory, applying clock and reset, and checking for a termination condition appropriate to the specific program you are running. Then add your UVM features.

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On Jul 23, 2024, at 11:17 PM, AishwaryaPrabhu1 ***@***.***> wrote: Thanks for your inputs. Earlier we have missed to run bin/wally-tool-chain-install.sh. Now we have executed each and every step in the script. Though initially we have faced some issues in some of the steps, we were able to fix and proceed further. And now, we are able to use wsim and run simulations. But now we want to implement UVM based testbench for this SOC and explore how to add new testcases to verify the peripheral communication. It will be really helpful if there is any document or README file which explains how this testbench and various testcases are implemented and running. Please guide us in this regard. — Reply to this email directly, view it on GitHub <#253 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA33WGTR5HEEEDUAQGUTZN5BI3AVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTAMJTGM3TCMA>. You are receiving this because you commented.

[AishwaryaPrabhu1]

The OS version we used was Ubuntu 20.04.6 LTS. The existing script worked for us while doing this setup. We have not done any changes.

[jordancarlin]

I'm surprised the existing script worked. I've found that on Ubuntu 20.04 LTS gcc-10 is needed for Verilator to work correctly and a newer version of glibc is needed for QEMU. You didn't run into those issues?

[AishwaryaPrabhu1]

Sorry for the typo, the OS version we used was Ubuntu 22.04.3 LTS.

[jordancarlin]

That makes more sense. That is the distro that has had the most testing done.

[AishwaryaPrabhu1]

We could successfully run the test cases and verify all the instructions. Now we want to verify the SOC using peripherals, for example, we want to verify the communication between UART and SPI. Please guide us how to add our testcases by which we can verify these peripheral communication.

[AishwaryaPrabhu1]

Hello!!
We are getting the below error while doing the synthesis of wallypipelinedsoc rv32gc. Please guide us.

[davidharrishmc]

You’re trying to synthesize a RAM with 536870880 words. The RAM size is too big. ‘ram_ahb_0000000080000000_0000000007ffffff_0_883626' You’ll need a configuration with a smaller RAM. Here is a synthesis command using the derived syn_rv32e configuration, with less memory. make synth DESIGN=wallypipelinedcore TECH=sky130 CONFIG=syn_rv32e FREQ=330 There’s a lot about this in Chapter 6, which is in production now and will be out in the spring. Synthesis is very touchy. You’ll need to be a fairly sophisticated synthesis user to bring this all up without the documentation from the book. If this is a personal project, I’d suggest waiting for the book in Spring 2025. If it’s something larger where a collaboration would be sensible, please reach out to me by email to discuss sharing a draft earlier. David Harris

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On Nov 6, 2024, at 1:53 AM, AishwaryaPrabhu1 ***@***.***> wrote: Hello!! We are getting the below error while doing the synthesis. Please guide us. Screenshot.from.2024-11-06.12-11-14.png (view on web) <https://github.com/user-attachments/assets/08177405-5aae-48a4-bc8f-237406dc5374> — Reply to this email directly, view it on GitHub <#253 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AR4AA3YZDCN6UYWYQE5BB2DZ7HRLNAVCNFSM6AAAAAAXCVCCGKVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTCMJWGQ3TIOI>. You are receiving this because you commented.