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However, Sail does not yet seem to support it. Running riscof on c.mul fails, hanging with an infinite trap loop.
more ../tests/riscof/riscof_work/rv32i_m/C/src/cmul-01.S/ref/cmul-01.log
[78] [M]: 0x80000122 (0x6605) c.lui a2, 1
x12 <- 0x00001000
mem[X,0x80000124] -> 0x9E49
[79] [M]: 0x80000124 (0x9E49) c.illegal 40521
trapping from M to M to handle illegal-instruction
Adding Zcb to Wally will inolve chanigng spike_rv{32/64}gc_isa.yaml, and regression-wally to have Zcb.
ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
The text was updated successfully, but these errors were encountered:
gcc 13.2.0 now seems to support Zcb.
However, Sail does not yet seem to support it. Running riscof on c.mul fails, hanging with an infinite trap loop.
more ../tests/riscof/riscof_work/rv32i_m/C/src/cmul-01.S/ref/cmul-01.log
[78] [M]: 0x80000122 (0x6605) c.lui a2, 1
x12 <- 0x00001000
mem[X,0x80000124] -> 0x9E49
[79] [M]: 0x80000124 (0x9E49) c.illegal 40521
trapping from M to M to handle illegal-instruction
Here is a pending PR for Zcb into Sail.
riscv/sail-riscv#322
riscv-non-isa/riscv-arch-test#418
Adding Zcb to Wally will inolve chanigng spike_rv{32/64}gc_isa.yaml, and regression-wally to have Zcb.
ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
The text was updated successfully, but these errors were encountered: