Skip to content

@SkillSurf SkillSurf

Change the repository type filter

All

    Repositories list

    12 repositories

    • 8b-sar-adc-unic_cass

      Public
      100KSPS 8-bit Fully-differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) for Low-power Applications (UNIC-CASS program by IEEE CASS)
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Nov 24, 2024Nov 24, 2024

    • tt09-matmul-system

      Public
      Matmul + UART + AXI Stream
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Nov 7, 2024Nov 7, 2024

    • tinytapout-matmul-system

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Nov 7, 2024Nov 7, 2024

    • inv-sky130-unic-cass

      Public
      Verilog
      •
      Apache License 2.0
      •2•0•0•0•Updated Sep 22, 2024Sep 22, 2024

    • cmos_inverter_sky130

      Public
      CMOS Inverter Design, Analysis and Layout in SKY130
      MIT License
      •4•3•0•0•Updated Sep 21, 2024Sep 21, 2024

    • ML4_edgeAI

      Public
      C
      •2•0•0•0•Updated Sep 1, 2024Sep 1, 2024

    • systemverilog

      Public
      SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
      HCL
      •
      MIT License
      •15•33•0•0•Updated Jun 18, 2024Jun 18, 2024

    • introduction_qc

      Public
      Introduction to Quantum Computing Free One-Day Workshop
      Mathematica
      •
      MIT License
      •1•4•0•0•Updated Jun 9, 2024Jun 9, 2024

    • modern_cpp

      Public
      C++
      •
      MIT License
      •0•0•0•0•Updated Jun 9, 2024Jun 9, 2024

    • introduction_genAI

      Public
      Introduction to GenAI Free One-Day Workshop
      Jupyter Notebook
      •
      MIT License
      •3•19•0•0•Updated Jun 9, 2024Jun 9, 2024

    • .github

      Public
      0•0•0•0•Updated May 19, 2024May 19, 2024

    • a-risc

      Public
      A Custom RISC CPU in 99 Lines of SystemVerilog
      SystemVerilog
      •1•3•0•0•Updated Jan 19, 2023Jan 19, 2023