{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"corundum","owner":"corundum","isFork":false,"description":"Open source FPGA-based NIC and platform for in-network compute","allTopics":["linux","networking","nic","in-network-compute","fpga"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":6,"issueCount":96,"starsCount":1628,"forksCount":410,"license":"Other","participation":[11,12,7,0,3,0,2,1,16,25,12,14,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-05T08:24:12.659Z"}},{"type":"Public","name":"verilog-pcie","owner":"corundum","isFork":true,"description":"Verilog PCI express components","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":18,"forksCount":284,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:04:04.892Z"}},{"type":"Public","name":"verilog-axis","owner":"corundum","isFork":true,"description":"Verilog AXI stream components for FPGA implementation","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":221,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:04:00.012Z"}},{"type":"Public","name":"verilog-ethernet","owner":"corundum","isFork":true,"description":"Verilog Ethernet components for FPGA implementation","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":14,"forksCount":669,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:03:57.754Z"}},{"type":"Public","name":"cocotbext-axi","owner":"corundum","isFork":true,"description":"AXI interface modules for Cocotb","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":68,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:03:48.552Z"}},{"type":"Public","name":"cocotbext-pcie","owner":"corundum","isFork":true,"description":"PCI express simulation framework for Cocotb","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":43,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:03:41.792Z"}},{"type":"Public","name":"scapy","owner":"corundum","isFork":true,"description":"Scapy: the Python-based interactive packet manipulation program & library. Supports Python 2 & Python 3.","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":2003,"license":"GNU General Public License v2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:03:38.134Z"}},{"type":"Public","name":"verilog-axi","owner":"corundum","isFork":true,"description":"Verilog AXI components for FPGA implementation","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":2,"forksCount":434,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:03:31.321Z"}},{"type":"Public","name":"cocotbext-eth","owner":"corundum","isFork":true,"description":"Ethernet interface modules for Cocotb","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":16,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-26T02:03:26.840Z"}},{"type":"Public","name":"ethernet-switch","owner":"corundum","isFork":false,"description":"Ethernet switch implementation written in Verilog","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":38,"forksCount":8,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-13T01:49:40.773Z"}},{"type":"Public","name":"timespec","owner":"corundum","isFork":true,"description":"Functions for working with timespec structures","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":19,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-01-12T17:38:24.736Z"}},{"type":"Public","name":"dpdk","owner":"corundum","isFork":true,"description":"Data Plane Development Kit","allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1212,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-01-12T17:36:26.609Z"}},{"type":"Public","name":"dma-bench","owner":"corundum","isFork":true,"description":"","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":11,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-11-15T01:23:08.561Z"}}],"repositoryCount":13,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"corundum repositories"}