How to use the register RESET_SR correctly?

[gege0500]

The value read from the 32-bit register RESET_SR is always 0xFF, why? How can this register be read correctly?

[nitindeshpande]

Hello @gege0500

If you are seeing the lowest bit set, that means, it is a power-on-reset (POR). Other reset reason bits should be ignored in that case.

The procedure the properly read the RESET_SR is as follows:

To read the RESET_SR, the process needs to be followed as below.

• In the e51() function read the RESET_SR register and store it in a variable.
• Immediately write 0 into to arm it for the next cycle.
• After this, a reset event e.g soft_reset will cause its bit to go to ‘1’

Note also that there may be multiple bits set in that register depending on the root cause of the reset.
For example: When the MSS is rebooted by the debugger, it will cause the SCB_MSS_RESET and SCB_CPU_RESET bits to be asserted as well.

RESET_SR = 0x1c7 => All resets happened EXCEPT watchdog, fabric and debugger. CPU Soft Reset being the root cause.
RESET_SR = 0xcf => All resets happened EXCEPT watchdog and fabric. Debugger being the root cause.

Hope this helps.

[gege0500]

Thank you for your reply. What is the ranking of the importance of all reset reasons?