UART baud rate with an 75MHz AHB clock

[Bharris100]

Platform = mpfs250TL. I am running a HSS built from the 2022.8 release as my FSBL, and bare metal MSS. We are working on reducing dynamic operating power by reducing the CPU/AXI/AHB clock frequencies to 150MHz/150MHz/75MHz. In MSS configurator we are setting the dividers to boot in the HSS to 600MHz/300MHz/75MHz to keep the boot fast, then reducing the CPU/AXI clocks in the MSS SW to the slower frequencies. The issue I am seeing is that the MMUART baud rate gets cut in half, only post boot the hart0 is parked in WFI. The baud rate is correct completely through the HSS boot startup, and I get my correct first messages from hart1, then it appears that the baud rate is divided by 2 as if somewhere the MMUART gets reinitialized expecting the APB clock to be 150MHz instead of the actual 75MHz it is set to.

I have searched through the MSS and not found where this switch might be happening. I would appreciate help in finding any place I might look where the baud rate might be effected post boot.
Thanks in advance,

[Bharris100]

A critical point I let out is that it works fine in debug, which lead me to this:



Yes, the answer is that I had not Properly updated the "Includes" for Assembly and GNUC to point to the correct board.