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emulator.c
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emulator.c
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#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <stdlib.h>
#include <strings.h>
#include <arpa/inet.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <stdint.h>
#include "emulator.h"
#include "opcode.h"
#define AL "\033[100D\33[65C"
#define dtrace(...) do { if( debug ) fprintf(stderr, __VA_ARGS__); } while(0)
struct cpu_state cpu;
bool debug = false;
bool run;
bool do_step;
int32_t count = 0;
static int32_t timer_int = 0;
static int32_t fakeflash_state = 0;
static int32_t flash_auto_select = 0;
static bool flash_log = false;
static bool log_reg = false;
static int32_t pll_control = 0;
static int32_t blk_enables = 0;
static int32_t perf_sys_pll = 0;
static int32_t irq_mask = 0;
static int32_t irq_stat = 0;
static int32_t timer_ctl0 = 0;
static int32_t timer_ctl1 = 0;
static int32_t timer_ctl2 = 0;
static int32_t uart0_ctrl = 0;
static int32_t uart0_baud_rate = 0;
static int32_t uart0_mctl = 0;
static int32_t uart0_ir = (1 << 5) << 16;
static int32_t uart1_ctrl = 0;
static int32_t uart1_baud_rate = 0;
static int32_t uart1_mctl = 0;
static int32_t uart1_ir = (1 << 5) << 16;
static int32_t mpi_csbase_0 = 0;
static int32_t mpi_csctl_0 = 0;
static int32_t mpi_csbase_1 = 0;
static int32_t mpi_csctl_1 = 0;
static int32_t pci_timers = 0;
static int32_t sdram_cfg = 0;
static int32_t sdram_unk1 = 0;
static int32_t sdram_unk2 = 0;
static int32_t sdram_mbase = 0;
static int32_t sdram_unk3 = 0;
int8_t flash_read_byte(uint32_t vaddr)
{
int8_t rv = 0x0;
switch(vaddr)
{
case 0x9f000021:
rv = 'Q';
break;
case 0x9f000023:
rv = 'R';
break;
case 0x9f000025:
rv = 'Y';
break;
case 0x9f000081:
rv = 'P';
break;
case 0x9f000083:
rv = 'R';
break;
case 0x9f000085:
rv = 'I';
break;
default:
rv = 0x0;
break;
}
return rv;
}
bool disable_flash = false;
int16_t flash_read_short(uint32_t vaddr)
{
int16_t rv = 0x0;
if( flash_auto_select == 3 )
{
if( (vaddr & 0x3) == 0 )
return 0x2000; /* Manufacturer code, from ST M29W160EB datasheet */
else
exit(1);
}
if(disable_flash == true )
return 0;
vaddr &= 0x1fffff;
switch(vaddr)
{
case 0x20:
rv = 0x5100; /* Q */
break;
case 0x22:
rv = 0x5200; /* R */
break;
case 0x24:
rv = 0x5900; /* Y */
break;
case 0x26:
rv = 0x0200; /* AMD compatible, from ST M29W160EB datasheet */
break;
case 0x28:
rv = 0x0000; /* AMD compatible, from ST M29W160EB datasheet */
break;
case 0x2a:
rv = 0x4000; /* Address for Primary Algorithm extended Query, from ST M29W160EB datasheet */
break;
case 0x2e:
rv = 0x0000; /* Alternate Vendor Command Set, from ST M29W160EB datasheet */
break;
case 0x32:
rv = 0x0000; /* Address for Alternate Algorithm extended Query, from ST M29W160EB datasheet */
break;
case 0x4e:
rv = 0x1500; /* 2MB size, from ST M29W160EB datasheet */
break;
case 0x50:
rv = 0x0200; /* x8, x16, Async., from ST M29W160EB datasheet */
break;
case 0x54:
rv = 0x0000; /* Max num of mutli-byte program bytes, from ST M29W160EB datasheet */
break;
case 0x56:
rv = 0x0000; /* Max num of mutli-byte program bytes, from ST M29W160EB datasheet */
break;
case 0x58:
rv = 0x0400; /* 4 erase block regions, from ST M29W160EB datasheet */
break;
case 0x5a:
rv = 0x0000; /* 1 block region 1, from ST M29W160EB datasheet */
break;
case 0x5c:
rv = 0x0000; /* 1 block region 1, from ST M29W160EB datasheet */
break;
case 0x5e:
rv = 0x4000; /* 16 KB region 1 size, from ST M29W160EB datasheet */
break;
case 0x60:
rv = 0x0000; /* 16 KB region 1 size, from ST M29W160EB datasheet */
break;
case 0x62:
rv = 0x0100; /* 2 blocks region 2, from ST M29W160EB datasheet */
break;
case 0x64:
rv = 0x0000; /* 2 blocks region 2, from ST M29W160EB datasheet */
break;
case 0x66:
rv = 0x2000; /* 8 KB region 1 size, from ST M29W160EB datasheet */
break;
case 0x68:
rv = 0x0000; /* 8 KB region 1 size, from ST M29W160EB datasheet */
break;
case 0x6a:
rv = 0x0000; /* 1 block region 3, from ST M29W160EB datasheet */
break;
case 0x6c:
rv = 0x0000; /* 1 block region 3, from ST M29W160EB datasheet */
break;
case 0x6e:
rv = 0x8000; /* 32 KB region 3 size, from ST M29W160EB datasheet */
break;
case 0x70:
rv = 0x0000; /* 32 KB region 3 size, from ST M29W160EB datasheet */
break;
case 0x72:
rv = 0x1e00; /* 31 blocks region 4, from ST M29W160EB datasheet */
break;
case 0x74:
rv = 0x0000; /* 31 blocks region 4, from ST M29W160EB datasheet */
break;
case 0x76:
rv = 0x0000; /* 64 KB region 4 size, from ST M29W160EB datasheet */
break;
case 0x78:
rv = 0x0100; /* 64 KB region 4 size, from ST M29W160EB datasheet */
break;
case 0x80:
rv = 0x5000; /* P */
break;
case 0x82:
rv = 0x5200; /* R */
break;
case 0x84:
rv = 0x4900; /* I */
break;
case 0x86:
rv = 0x3100; /* Major version number, ASCII */
break;
case 0x88:
rv = 0x3000; /* Minor version number, ASCII */
break;
default:
rv = 0x0;
break;
}
return rv;
}
void flash_write(uint32_t vaddr, uint16_t val)
{
printf( "fakeflash write @ 0x%08x <= 0x%08x (pc:0x%08x)\n", vaddr, val, cpu.pc );
vaddr &= 0x1fffff;
if(vaddr == 0x0 && (val == 0xf0 || val == 0xf0f0))
{
fakeflash_state = 0;
flash_auto_select = 0;
}
if(vaddr == 0x0 && (val == 0xff || val == 0xffff))
{
fakeflash_state = 0;
flash_auto_select = 0;
}
if(vaddr == 0xaa && (val == 0x98 || val == 0x9898))
{
fakeflash_state = 1;
flash_log = 1;
}
if(vaddr == 0xaaa && (val == 0xaa || val == 0xaaaa ) && fakeflash_state == 0 && flash_auto_select == 0)
{
flash_auto_select = 1;
}
if(vaddr == 0x554 && (val == 0x55 || val == 0x5555 ) && fakeflash_state == 0 && flash_auto_select == 1)
{
flash_auto_select = 2;
}
if(vaddr == 0xaaa && (val == 0x90 || val == 0x9090 ) && fakeflash_state == 0 && flash_auto_select == 2)
{
flash_auto_select = 3;
fakeflash_state = 1;
}
printf("fakeflash write state: %d\n", fakeflash_state);
}
void reg_write_byte(uint32_t vaddr, uint8_t val)
{
/* printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val); */
if(vaddr == 0xfffe0008)
{
perf_sys_pll = (perf_sys_pll & 0xffffff00) | val;
printf("Set perf sys pll b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe000a)
{
printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe000b)
{
printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0015)
{
printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0016)
{
printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0017)
{
printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0301)
{
uart0_ctrl = (uart0_ctrl & 0xffff00ff) | val << 8;
printf("Set uart0 ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0302)
{
uart0_ctrl = (uart0_ctrl & 0xff00ffff) | val << 16;
printf("Set uart0 ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0303)
{
uart0_ctrl = (uart0_ctrl & 0x00ffffff) | val << 24;
printf("Set uart0 ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe030a)
{
uart0_mctl = (uart0_mctl & 0xff00ffff) | val << 16;
printf("Set uart0 mctl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0317)
{
// printf("Set uart0 txbuf '%c'\n", val);
printf("%c", val);
fflush(stdout);
uart0_ir |= (1 << 5) << 16;
}
else if(vaddr == 0xfffe0323)
{
uart1_ctrl = (uart1_ctrl & 0x00ffffff) | val << 24;
printf("Set uart0 ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0803)
{
printf("Set spi? ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe0881)
{
printf("Set spi? ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe3000)
{
printf("Set docsis? ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe3068)
{
printf("Set ??? b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe31e8)
{
printf("Set ??? b(0x%x) = 0x%02x\n", vaddr, val);
}
else if(vaddr == 0xfffe3601)
{
printf("Set docsis? ctrl b(0x%x) = 0x%02x\n", vaddr, val);
}
else
{
printf("Reg write b(0x%x) = 0x%02x\n", vaddr, val);
// exit(1);
}
}
void reg_write_short(uint32_t vaddr, uint16_t val)
{
/* printf("Reg write s(0x%x) = 0x%04x\n", vaddr, val); */
if(vaddr == 0xfffe0006)
{
blk_enables = (blk_enables & 0x0000ffff) | val << 16;
printf("Set blk enables s(0x%x) = 0x%04x\n", vaddr, val);
}
else if(vaddr == 0xfffe0310)
{
uart0_ir = (uart0_ir & 0xffff0000) | val;
/* printf("Set uart0 ir s(0x%x) = 0x%04x @ 0x%08x\n", vaddr, val, cpu.pc); */
}
else if(vaddr == 0xfffe0316)
{
// printf("Set uart0 txbuf '%c'\n", val);
printf("%c", val);
fflush(stdout);
uart0_ir |= (1 << 5) << 16;
}
else
{
/* printf("Reg write s(0x%x) = 0x%04x\n", vaddr, val); */
/* exit(1); */
}
}
void reg_write_word(uint32_t vaddr, uint32_t val)
{
/* printf("Reg write w(0x%x) = 0x%08x\n", vaddr, val); */
if(vaddr == 0xfffe0008)
{
printf("Set PLL_control w(0x%x) = 0x%08x\n", vaddr, val);
pll_control = val;
}
else if(vaddr == 0xfffe000c)
{
printf("Set irq mask w(0x%x) = 0x%08x\n", vaddr, val);
irq_mask = val;
}
else if(vaddr == 0xfffe0204)
{
printf("Set timer0 ctl w(0x%x) = 0x%08x\n", vaddr, val);
timer_ctl0 = val;
}
else if(vaddr == 0xfffe0208)
{
printf("Set timer1 ctl w(0x%x) = 0x%08x\n", vaddr, val);
timer_ctl1 = val;
}
else if(vaddr == 0xfffe020c)
{
printf("Set timer2 ctl w(0x%x) = 0x%08x\n", vaddr, val);
timer_ctl2 = val;
}
else if(vaddr == 0xfffe0304)
{
printf("Set uart0 baud w(0x%x) = 0x%08x\n", vaddr, val);
uart0_baud_rate = val;
}
else if(vaddr == 0xfffe2000)
{
printf("Set mpi csbase0 w(0x%x) = 0x%08x\n", vaddr, val);
mpi_csbase_0 = val;
}
else if(vaddr == 0xfffe2004)
{
printf("Set mpi csctl0 w(0x%x) = 0x%08x\n", vaddr, val);
mpi_csctl_0 = val;
}
else if(vaddr == 0xfffe2008)
{
printf("Set mpi csbase1 w(0x%x) = 0x%08x\n", vaddr, val);
mpi_csbase_1 = val;
}
else if(vaddr == 0xfffe200c)
{
printf("Set mpi csctl1 w(0x%x) = 0x%08x\n", vaddr, val);
mpi_csctl_1 = val;
}
else if(vaddr == 0xfffe2040)
{
printf("Set pci timers w(0x%x) = 0x%08x\n", vaddr, val);
pci_timers = val;
}
else if(vaddr == 0xfffe2300)
{
printf("Set sdram cfg w(0x%x) = 0x%08x\n", vaddr, val);
sdram_cfg = val;
}
else if(vaddr == 0xfffe2304)
{
printf("Set sdram unk1 w(0x%x) = 0x%08x\n", vaddr, val);
sdram_unk1 = val;
}
else if(vaddr == 0xfffe2308)
{
printf("Set sdram unk2 w(0x%x) = 0x%08x\n", vaddr, val);
sdram_unk2 = val;
}
else if(vaddr == 0xfffe230c)
{
printf("Set sdram mbase w(0x%x) = 0x%08x\n", vaddr, val);
sdram_mbase = val;
}
else
{
/* printf("Reg write w(0x%x) = 0x%08x\n", vaddr, val); */
/* exit(1); */
}
}
int32_t get_reg_val(uint32_t vaddr)
{
if( log_reg && vaddr != 0xfffe0203 && vaddr != 0xfffe0312 )
printf("Reg read w(0x%x) @ 0x%08x\n", vaddr, cpu.pc);
if(vaddr == 0xfffe0000)
return 0xa0003348;
else if(vaddr == 0xfffe0003)
return 0xa0;
else if(vaddr == 0xfffe0006)
return blk_enables >> 16;
else if(vaddr == 0xfffe0008)
return pll_control;
else if(vaddr == 0xfffe000c)
return irq_mask;
else if(vaddr == 0xfffe0010)
return irq_stat;
else if(vaddr == 0xfffe0310)
{
/* printf("Reg read uart0 ir mask w(0x%x) = 0x%08x @ 0x%08x\n", vaddr, uart0_ir, cpu.pc); */
return uart0_ir;
}
else if(vaddr == 0xfffe0312)
{
short ret = uart0_ir >> 16;
/* printf("Reg read uart0 ir stat w(0x%x) = 0x%08x @ 0x%08x\n", vaddr, uart0_ir, cpu.pc); */
/* uart0_ir &= 0xffff; */
return ret;
}
else if(vaddr == 0xFFFE2000)
return 0x1F00000B;
else if(vaddr == 0xFFFE2008)
return 0x1A000008;
else if(vaddr == 0xFFFE2010)
return 0x00000000;
else if(vaddr == 0xFFFE2018)
return 0x00000000;
else if(vaddr == 0xFFFE2020)
return 0x00000000;
else if(vaddr == 0xFFFE2028)
return 0x00000000;
else if(vaddr == 0xFFFE2004)
return 0x00000019;
else if(vaddr == 0xFFFE200C)
return 0x00000019;
else if(vaddr == 0xFFFE2014)
return 0x00000000;
else if(vaddr == 0xFFFE201C)
return 0x00000000;
else if(vaddr == 0xFFFE2024)
return 0x00000000;
else if(vaddr == 0xFFFE202C)
return 0x00000000;
else if(vaddr == 0xFFFE0203)
{
if(timer_int == 2) {
timer_int = 1;
return 0xff;
}
else if(timer_int == 1) {
timer_int = 0;
return 0xff;
}
else
return 0x0;
}
else if(vaddr == 0xFFFE2308)
{
return sdram_unk3;
}
else
{
/* printf("Reg read w(0x%x) @ 0x%08x\n", vaddr, cpu.pc); */
/* exit(1); */
}
return 0;
}
int32_t get_instruction(uint32_t address, int8_t *ram, int8_t *flash)
{
int32_t instruction = 0x0;
if(address >= RAM_START && address < RAM_END)
instruction = *(int32_t *)(ram+address-RAM_START);
else if(address >= FLASH_START && address < FLASH_END)
instruction = *(int32_t *)(flash+address-FLASH_START);
else
exit(1);
instruction = ntohl(instruction);
return instruction;
}
uint32_t decode_opcode(uint32_t instruction)
{
return instruction >> 26;
}
uint32_t decode_special_opcode(uint32_t instruction)
{
return (instruction & 0x3f);
}
uint32_t decode_special2_opcode(uint32_t instruction)
{
return (instruction & 0x3f);
}
uint32_t decode_special_branch_opcode(uint32_t instruction)
{
return (instruction & 0x1f0000) >>16;
}
int32_t get_jump_address(int32_t instruction, int32_t pc)
{
instruction = (pc & 0xf0000000) | ((instruction & 0x03ffffff) << 2);
return instruction;
}
int32_t get_rs(int32_t instruction)
{
return (instruction & 0x03e00000) >> 21;
}
int32_t get_rt(int32_t instruction)
{
return (instruction & 0x001f0000) >> 16;
}
int32_t get_rd(int32_t instruction)
{
return (instruction & 0x0000f800) >> 11;
}
int32_t get_sa(int32_t instruction)
{
return (instruction & 0x000007c0) >> 6;
}
int16_t get_immediate16(int32_t instruction)
{
return (instruction & 0x0000ffff);
}
int16_t get_offset(int32_t instruction)
{
return (instruction & 0x0000ffff);
}
int32_t get_base(int32_t instruction)
{
return get_rs(instruction);
}
int32_t flash_read(uint32_t vaddr, int8_t *flash, uint8_t width)
{
if( flash_log && fakeflash_state )
{
printf("flash read (%u)0x%08x (pc:0x%08x)\n", width, vaddr, cpu.pc);
}
switch( width )
{
case 1:
if(fakeflash_state)
{
return flash_read_byte(vaddr);
}
else
{
return *(int8_t *)(flash+vaddr-FLASH_START);
}
case 2:
if(fakeflash_state)
{
return flash_read_short(vaddr);
}
else
{
return *(int16_t *)(flash+vaddr-FLASH_START);
}
case 4:
if(fakeflash_state)
{
/* printf("read word in cfi state\n"); */
/* exit(1); */
return 0;
}
else
{
return *(int32_t *)(flash+vaddr-FLASH_START);
}
}
return 0;
}
int32_t load_word(uint32_t vaddr, int8_t *ram, int8_t *flash)
{
int32_t word = 0;
if(vaddr >= REG_START && vaddr <= REG_END)
return (int32_t)get_reg_val(vaddr);
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
word = flash_read( vaddr, flash, 4 );
else if(vaddr >= FAKEFLASH_START && vaddr < FAKEFLASH_END)
word = flash_read( vaddr, flash, 4 );
else if(vaddr >= RAM_START && vaddr < RAM_END)
word = *(int32_t *)(ram+vaddr-RAM_START);
word = ntohl(word);
return word;
}
void store_word(uint32_t vaddr, int32_t val, int8_t *ram, int8_t *flash)
{
if(vaddr >= REG_START && vaddr <= REG_END)
return reg_write_word(vaddr, val);
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
return flash_write(vaddr, val);
else if(vaddr >= RAM_START && vaddr < RAM_END)
{
*(int32_t *)(ram+vaddr-RAM_START) = htonl(val);
return;
}
printf("can't write 0x%08x to 0x%x\n", val, vaddr);
}
uint16_t load_short(uint32_t vaddr, int8_t *ram, int8_t *flash)
{
int16_t word = 0;
if(vaddr >= REG_START && vaddr <= REG_END)
return (int16_t)get_reg_val(vaddr);
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
word = (int16_t)flash_read( vaddr, flash, 2 );
else if(vaddr >= FAKEFLASH_START && vaddr < FAKEFLASH_END)
word = (int16_t)flash_read( vaddr, flash, 2 );
else if(vaddr >= RAM_START && vaddr < RAM_END)
word = *(int16_t *)(ram+vaddr-RAM_START);
word = ntohs(word);
return word;
}
void store_short(uint32_t vaddr, int16_t val, int8_t *ram, int8_t *flash)
{
if(vaddr >= REG_START && vaddr <= REG_END)
return reg_write_short(vaddr, val);
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
return flash_write(vaddr, val);
else if(vaddr >= FAKEFLASH_START && vaddr < FAKEFLASH_END)
return flash_write(vaddr, val);
else if(vaddr >= RAM_START && vaddr < RAM_END)
{
*(int16_t *)(ram+vaddr-RAM_START) = htons(val);
return;
}
printf("can't write 0x%04x to 0x%x\n", val, vaddr);
}
uint8_t load_byte(uint32_t vaddr, int8_t *ram, int8_t *flash)
{
int8_t byte = 0;
if(vaddr >= REG_START && vaddr <= REG_END)
return (int8_t)get_reg_val(vaddr);
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
byte = (int8_t)flash_read( vaddr, flash, 1 );
else if(vaddr >= FAKEFLASH_START && vaddr < FAKEFLASH_END)
byte = (int8_t)flash_read( vaddr, flash, 1 );
else if(vaddr >= RAM_START && vaddr < RAM_END)
byte = *(int8_t *)(ram+vaddr-RAM_START);
return byte;
}
void store_byte(uint32_t vaddr, int8_t val, int8_t *ram, int8_t *flash)
{
if(vaddr >= REG_START && vaddr <= REG_END)
return reg_write_byte(vaddr, val);
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
return flash_write(vaddr, val);
else if(vaddr >= FLASH_START && vaddr < FLASH_END)
return flash_write(vaddr, val);
else if(vaddr >= RAM_START && vaddr < RAM_END)
{
*(int8_t *)(ram+vaddr-RAM_START) = val;
return;
}
printf("can't write 0x%02x to 0x%x\n", val, vaddr);
}
char *r2rn(int32_t reg)
{
switch (reg)
{
case 0:
return "$0";
case 1:
return "$at";
case 2:
return "$v0";
case 3:
return "$v1";
case 4:
return "$a0";
case 5:
return "$a1";
case 6:
return "$a2";
case 7:
return "$a3";
case 8:
return "$t0";
case 9:
return "$t1";
case 10:
return "$t2";
case 11:
return "$t3";
case 12:
return "$t4";
case 13:
return "$t5";
case 14:
return "$t6";
case 15:
return "$t7";
case 16:
return "$s0";
case 17:
return "$s1";
case 18:
return "$s2";
case 19:
return "$s3";
case 20:
return "$s4";
case 21:
return "$s5";
case 22:
return "$s6";
case 23:
return "$s7";
case 24:
return "$t8";
case 25:
return "$t9";
case 26:
return "$k0";
case 27:
return "$k1";
case 28:
return "$gp";
case 29:
return "$sp";
case 30:
return "$s8";
case 31:
return "$ra";
}
return "";
}
#if 0
void dump_regs(struct cpu_state *cpu)
{
dtrace("$0: 0x%08x $at: 0x%08x $v0: 0x%08x $v1: 0x%08x $a0: 0x%08x $a1: 0x%08x $a2: 0x%08x $a3: 0x%08x\n", cpu->reg[0], cpu->reg[1], cpu->reg[2], cpu->reg[3], cpu->reg[4], cpu->reg[5], cpu->reg[6], cpu->reg[7]);
dtrace("$t0: 0x%08x $t1: 0x%08x $t2: 0x%08x $t3: 0x%08x $t4: 0x%08x $t5: 0x%08x $t6: 0x%08x $t7: 0x%08x\n", cpu->reg[8], cpu->reg[9], cpu->reg[10], cpu->reg[11], cpu->reg[12], cpu->reg[13], cpu->reg[14], cpu->reg[15]);
dtrace("$s0: 0x%08x $s1: 0x%08x $s2: 0x%08x $s3: 0x%08x $s4: 0x%08x $s5: 0x%08x $s6: 0x%08x $s7: 0x%08x\n", cpu->reg[16], cpu->reg[17], cpu->reg[18], cpu->reg[19], cpu->reg[20], cpu->reg[21], cpu->reg[22], cpu->reg[23]);
dtrace("$t8: 0x%08x $t9: 0x%08x $k0: 0x%08x $k1: 0x%08x $gp: 0x%08x $sp: 0x%08x $s8: 0x%08x $ra: 0x%08x\n", cpu->reg[24], cpu->reg[25], cpu->reg[26], cpu->reg[27], cpu->reg[28], cpu->reg[29], cpu->reg[30], cpu->reg[31]);
}
#endif
int32_t *get_address(uint32_t vaddr, int8_t *ram, int8_t *flash)
{
if(vaddr >= REG_START && vaddr <= REG_END)
return 0;
else
vaddr = vaddr & ~0x20000000;
if(vaddr >= FLASH_START && vaddr < FLASH_END)
return (int32_t *)(flash+(vaddr-FLASH_START));
else if(vaddr >= RAM_START && vaddr < RAM_END)
return (int32_t *)(ram+(vaddr-RAM_START));
return 0;
}
void process_callbacks(struct cpu_state *cpu)
{
struct callback *cb;
for(cb = cpu->callbacks; cb; cb = cb->next)
{
if(cb->address == cpu->pc)
cb->callback(cpu);
}
}
inline static void cli( struct cpu_state *cpu )
{
char buf[100] = { 0 };
if( debug )
{
instlog(cpu);
}
if( !run )
{
printf("MIPS> ");
fflush( stdout );
read( 0, buf, 100 );
if( strncmp( buf, "run", 3 ) == 0 )
{
run = true;
debug = false;
return;
}
else if( strncmp( buf, "drun", 4 ) == 0 )
{
run = true;
debug = true;
return;
}
else if( strncmp( buf, "step", 3 ) == 0 )
{
do_step = true;
debug = true;
return;
}
else if( strncmp( buf, "s\n", 2 ) == 0 )
{
do_step = true;
debug = true;
return;
}
else if( strncmp( buf, "next", 3 ) == 0 )
{
do_step = false;
run = true;
register_callback(cpu, cpu->pc+4, bp);
return;
}
else if( strncmp( buf, "bp", 2 ) == 0 )
{
int number = (int)strtol(buf + 3, NULL, 0);
do_step = true;
register_callback(cpu, number, bp);
cli(cpu);
return;
}
if( !do_step )
{
exit(1);
}
}
}
void instlog(struct cpu_state *cpu)
{
int32_t instruction;
int32_t opcode;
int32_t rs;
int32_t rt;
int32_t rd;
int32_t sa;
int32_t base;
uint32_t vaddr;
int32_t offset;
int16_t im16;
instruction = get_instruction(cpu->pc, cpu->ram, cpu->flash);
dtrace("0x%x: ", cpu->pc);
base = get_base(instruction);
im16 = get_immediate16(instruction);
offset = get_offset(instruction);
rd = get_rd(instruction);
rs = get_rs(instruction);
rt = get_rt(instruction);
sa = get_sa(instruction);
vaddr = cpu->reg[base]+offset;
opcode = decode_opcode(instruction);
if(opcode == 0)
{
opcode = decode_special_opcode(instruction);
switch(opcode)
{
case INS_SLL: /* 000000 */
if(sa == 0)
dtrace("\tnop\n");
else
dtrace("\tsll\t%s, %s, %d" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rt), sa, r2rn(rd), (uint32_t)cpu->reg[rt] << sa);
break;
case INS_MOVF: /* 000001 */
printf("\tmovf not implemented\n");
exit(1);
break;
case INS_SRL: /* 000010 */
dtrace("\tsrl\t%s, %s, %d" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rt), sa, r2rn(rd), (uint32_t)cpu->reg[rt] >> sa);
break;
case INS_SRA: /* 000011 */
dtrace("\tsllv\t%s, %s, %d" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rt), sa, r2rn(rd), cpu->reg[rt] >> sa);
break;
case INS_SLLV: /* 000100 */
dtrace("\tsllv\t%s, %s, %s" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rt), r2rn(rs), r2rn(rd), (uint32_t)cpu->reg[rt] << (cpu->reg[rs] & 0x1f));
break;
case INS_SRLV: /* 000110 */
dtrace("\tsrlv\t%s, %s, %s" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rt), r2rn(rs), r2rn(rd), (uint32_t)cpu->reg[rt] >> (cpu->reg[rs] & 0x1f));
break;
case INS_SRAV: /* 000111 */
dtrace("\tsrav\t%s, %s, %s" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rt), r2rn(rs), r2rn(rd), (int32_t)cpu->reg[rt] >> (cpu->reg[rs] & 0x1f));
break;
case INS_JR: /* 001000 */
dtrace("\tjr\t%s" AL "(0x%x)\n",
r2rn(rs), cpu->reg[rs] & ~0x20000000);
break;
case INS_JALR: /* 001001 */
dtrace("\tjalr\t%s, %s" AL "(0x%x)\n",
r2rn(rs), r2rn(rd), cpu->reg[rs] & ~0x20000000);
break;
case INS_MOVZ: /* 001010 */
if(cpu->reg[rt] == 0)
dtrace("\tmovz\t%s, %s, %s" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rs), r2rn(rt), r2rn(rd), cpu->reg[rs]);
else
dtrace("\tmovz\t%s, %s, %s" AL "(%s = 0x%x)\n",
r2rn(rd), r2rn(rs), r2rn(rt), r2rn(rd), cpu->reg[rd]);
break;
case INS_MOVN: /* 001011 */
if(cpu->reg[rt] != 0)
dtrace("\tmovn\t%s, %s, %s" AL "(%s = 0x%x)\n",