From ff4e9464d4d3918e52249724623ca2da5b8cb529 Mon Sep 17 00:00:00 2001 From: Valerii Koval Date: Wed, 17 Jun 2020 19:44:59 +0300 Subject: [PATCH 1/3] Fix broken package path when programming FPGA --- builder/main.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builder/main.py b/builder/main.py index ef2d7d1..cbb8907 100644 --- a/builder/main.py +++ b/builder/main.py @@ -198,7 +198,7 @@ def run_verilator(target, source, env): "-s", '"%s"' % os.path.join( - env.PioPlatform().get_package_dir("framework-wd-riscv-sdk"), + platform.get_package_dir("framework-wd-riscv-sdk") or "", "board", env.BoardConfig().get("build.variant", ""), ), From 87f298732301d2eabe11af8741eb0cadcd765240 Mon Sep 17 00:00:00 2001 From: Valerii Koval Date: Wed, 17 Jun 2020 19:47:53 +0300 Subject: [PATCH 2/3] Fix Nexys A7 board name --- boards/swervolf_nexys.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/swervolf_nexys.json b/boards/swervolf_nexys.json index f9b2c57..8af44a2 100644 --- a/boards/swervolf_nexys.json +++ b/boards/swervolf_nexys.json @@ -20,7 +20,7 @@ "openocd_config": "swervolf_nexys_debug.cfg" }, "frameworks": ["wd-riscv-sdk"], - "name": "digilentincNexys A7", + "name": "Digilent Nexys A7", "upload": { "maximum_ram_size": 1216512, "maximum_size": 16777216, From d4f2adec25bd87996254ae1f9c80630198263dbe Mon Sep 17 00:00:00 2001 From: Valerii Koval Date: Wed, 17 Jun 2020 19:48:52 +0300 Subject: [PATCH 3/3] Bump version to 0.1.1 --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index b589c38..10fe824 100644 --- a/platform.json +++ b/platform.json @@ -12,7 +12,7 @@ "type": "git", "url": "https://github.com/platformio/platform-chipsalliance.git" }, - "version": "0.1.0", + "version": "0.1.1", "packageRepositories": [ "https://dl.bintray.com/platformio/dl-packages/manifest.json", "http://dl.platformio.org/packages/manifest.json"