From 9dc5a41483e3507a2018444aecf26f6e1ea061e4 Mon Sep 17 00:00:00 2001 From: Luca Colagrande Date: Mon, 11 Dec 2023 14:43:47 +0100 Subject: [PATCH] src: Remove missing pin warnings --- src/axi_to_mem_interleaved.sv | 3 +++ src/axi_to_mem_split.sv | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/axi_to_mem_interleaved.sv b/src/axi_to_mem_interleaved.sv index 9a5f87805..06dc1c2a4 100644 --- a/src/axi_to_mem_interleaved.sv +++ b/src/axi_to_mem_interleaved.sv @@ -282,6 +282,8 @@ module axi_to_mem_interleaved_intf #( input logic clk_i, /// Asynchronous reset, active low input logic rst_ni, + /// Testmode enable + input logic test_i, /// Status output, busy flag of `axi_to_mem` output logic busy_o, /// AXI4+ATOP slave port @@ -337,6 +339,7 @@ module axi_to_mem_interleaved_intf #( ) i_axi_to_mem_interleaved ( .clk_i, .rst_ni, + .test_i, .busy_o, .axi_req_i ( mem_axi_req ), .axi_resp_o ( mem_axi_resp ), diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index 28ce40831..3e98bda2e 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -196,6 +196,8 @@ module axi_to_mem_split_intf #( input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, + /// Testmode enable + input logic test_i, /// See `axi_to_mem_split`, port `busy_o`. output logic busy_o, /// AXI4+ATOP slave interface port. @@ -244,6 +246,7 @@ module axi_to_mem_split_intf #( ) i_axi_to_mem_split ( .clk_i, .rst_ni, + .test_i, .busy_o, .axi_req_i (axi_req), .axi_resp_o (axi_resp),