From 10d087cc22ac20ceb07963b349ad5f44b7906dfa Mon Sep 17 00:00:00 2001 From: Moritz Scherer Date: Fri, 11 Oct 2024 13:52:39 +0200 Subject: [PATCH] Fix rebasing bugs --- bender.mk | 2 +- hw/chimera_clu_domain.sv | 22 +++++------ hw/chimera_pkg.sv | 7 +--- hw/chimera_top_wrapper.sv | 4 +- hw/convolve/chimera_cluster_ethcluster.sv | 16 ++++---- hw/convolve/chimera_cluster_kulcluster.sv | 16 ++++---- hw/convolve/chimera_cluster_tuddcim.sv | 48 +++++++++++------------ hw/convolve/chimera_cluster_tuedcim.sv | 16 ++++---- hw/convolve/chimera_cluster_tuemega.sv | 16 ++++---- 9 files changed, 71 insertions(+), 76 deletions(-) diff --git a/bender.mk b/bender.mk index c2b3fb1..cf835f3 100644 --- a/bender.mk +++ b/bender.mk @@ -9,4 +9,4 @@ COMMON_TARGS ?= COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl SIM_TARGS = -t test -t sim -EXT_TARGS = -t tuedcim -t tuemega -t kulcluster -t tuddcim -t ethcluster +EXT_TARGS = -t tuedcim -t tuemega -t kulcluster -t tuddcim diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index a3bf767..995eb24 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -26,7 +26,7 @@ module chimera_clu_domain ) ( input logic soc_clk_i, input logic [ ExtClusters-1:0] clu_clk_i, - input logic [ ExtClusters-1:0] rst_sync_ni, + input logic rst_ni, input logic [ ExtClusters-1:0] widemem_bypass_i, //----------------------------- // Interrupt ports @@ -75,7 +75,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), .msip_i (msip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), .hart_base_id_i (10'(`PREVNRCORES(TUEDCIMIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[TUEDCIMIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[TUEDCIMIDX]), @@ -107,7 +107,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), .msip_i (msip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), .hart_base_id_i (10'(`PREVNRCORES(TUEDCIMIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[TUEDCIMIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[TUEDCIMIDX]), @@ -140,7 +140,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), .msip_i (msip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), .hart_base_id_i (10'(`PREVNRCORES(TUEMEGAIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[TUEMEGAIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEMEGAIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[TUEMEGAIDX]), @@ -172,7 +172,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), .msip_i (msip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), .hart_base_id_i (10'(`PREVNRCORES(TUEMEGAIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[TUEMEGAIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEMEGAIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[TUEMEGAIDX]), @@ -207,7 +207,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), .msip_i (msip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), .hart_base_id_i (10'(`PREVNRCORES(TUDDCIMIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[TUDDCIMIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUDDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[TUDDCIMIDX]), @@ -239,7 +239,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), .msip_i (msip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), .hart_base_id_i (10'(`PREVNRCORES(TUDDCIMIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[TUDDCIMIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUDDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[TUDDCIMIDX]), @@ -274,7 +274,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), .msip_i (msip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), .hart_base_id_i (10'(`PREVNRCORES(KULCLUSTERIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[KULCLUSTERIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[KULCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[KULCLUSTERIDX]), @@ -306,7 +306,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), .msip_i (msip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), .hart_base_id_i (10'(`PREVNRCORES(KULCLUSTERIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[KULCLUSTERIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[KULCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[KULCLUSTERIDX]), @@ -341,7 +341,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), .msip_i (msip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), .hart_base_id_i (10'(`PREVNRCORES(ETHCLUSTERIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[ETHCLUSTERIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[ETHCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[ETHCLUSTERIDX]), @@ -373,7 +373,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), .msip_i (msip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), .hart_base_id_i (10'(`PREVNRCORES(ETHCLUSTERIDX) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[ETHCLUSTERIDX][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[ETHCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_req_i[ETHCLUSTERIDX]), diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index a6cea2e..cc35b77 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -110,15 +110,13 @@ ExtClusters 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 }; - localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; - // Parameters for Memory Island localparam int MemIslandIdx = ClusterIdx[ExtClusters-1] + 1; localparam doub_bt MemIslRegionStart = 64'h4800_0000; localparam doub_bt MemIslRegionEnd = 64'h4804_0000; localparam aw_bt MemIslAxiMstIdWidth = 1; - localparam byte_bt MemIslNarrowToWideFactor = 4; + localparam byte_bt MemIslNarrowToWideFactor = 16; localparam byte_bt MemIslNarrowPorts = 1; localparam byte_bt MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); localparam byte_bt MemIslNumWideBanks = 2; @@ -154,9 +152,6 @@ ExtClusters cfg.AddrWidth = 48; cfg.LlcOutRegionEnd = 'hFFFF_FFFF; - cfg.MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.MemIslNarrowToWideFactor = 16; - cfg.AxiExtNumWideMst = $countones(ChimeraClusterCfg.hasWideMasterPort); // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index d060e68..e55702c 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -336,7 +336,7 @@ module chimera_top_wrapper ) i_cluster_domain ( .soc_clk_i (soc_clk_i), .clu_clk_i (clu_clk_gated), - .rst_sync_ni (pmu_rst_clusters_ni), + .rst_ni (rst_ni), .widemem_bypass_i (wide_mem_bypass_mode), .debug_req_i (dbg_ext_req), .xeip_i (xeip_ext), @@ -344,7 +344,7 @@ module chimera_top_wrapper .msip_i (msip_ext), .narrow_in_req_i (axi_slv_req[ClusterIdx[0]+:ExtClusters]), .narrow_in_resp_o (axi_slv_rsp[ClusterIdx[0]+:ExtClusters]), - .narrow_out_req_o (axi_mst_req), + .narrow_out_req_o (axi_mst_req,) .narrow_out_resp_i(axi_mst_rsp), .wide_out_req_o (axi_wide_mst_req), .wide_out_resp_i (axi_wide_mst_rsp), diff --git a/hw/convolve/chimera_cluster_ethcluster.sv b/hw/convolve/chimera_cluster_ethcluster.sv index 50286e6..5149481 100644 --- a/hw/convolve/chimera_cluster_ethcluster.sv +++ b/hw/convolve/chimera_cluster_ethcluster.sv @@ -8,7 +8,7 @@ module chimera_cluster_ethcluster import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, + parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 2, parameter type narrow_in_req_t = logic, @@ -34,7 +34,7 @@ module chimera_cluster_ethcluster // Cluster base addressing //----------------------------- input logic [ 9:0] hart_base_id_i, - input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports @@ -55,16 +55,16 @@ module chimera_cluster_ethcluster localparam int WideDataWidth = $bits(wide_out_req_o.w.data); localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); - localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1; + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - typedef logic [Cfg.AddrWidth-1:0] axi_addr_t; - typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; - typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; - typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; @@ -117,7 +117,7 @@ module chimera_cluster_ethcluster axi_cluster_out_wide_req_t clu_axi_wide_mst_req; axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; - if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter narrow_adapter #( .narrow_in_req_t (axi_soc_out_narrow_req_t), diff --git a/hw/convolve/chimera_cluster_kulcluster.sv b/hw/convolve/chimera_cluster_kulcluster.sv index 206044a..758503b 100644 --- a/hw/convolve/chimera_cluster_kulcluster.sv +++ b/hw/convolve/chimera_cluster_kulcluster.sv @@ -8,7 +8,7 @@ module chimera_cluster_kulcluster import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, + parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 2, parameter type narrow_in_req_t = logic, @@ -34,7 +34,7 @@ module chimera_cluster_kulcluster // Cluster base addressing //----------------------------- input logic [ 9:0] hart_base_id_i, - input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports @@ -55,16 +55,16 @@ module chimera_cluster_kulcluster localparam int WideDataWidth = $bits(wide_out_req_o.w.data); localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); - localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1; + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - typedef logic [Cfg.AddrWidth-1:0] axi_addr_t; - typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; - typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; - typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; @@ -117,7 +117,7 @@ module chimera_cluster_kulcluster axi_cluster_out_wide_req_t clu_axi_wide_mst_req; axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; - if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter narrow_adapter #( .narrow_in_req_t (axi_soc_out_narrow_req_t), diff --git a/hw/convolve/chimera_cluster_tuddcim.sv b/hw/convolve/chimera_cluster_tuddcim.sv index d1b6ee3..b075566 100644 --- a/hw/convolve/chimera_cluster_tuddcim.sv +++ b/hw/convolve/chimera_cluster_tuddcim.sv @@ -8,7 +8,7 @@ module chimera_cluster_tuddcim import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, + parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 2, parameter type narrow_in_req_t = logic, @@ -19,35 +19,35 @@ module chimera_cluster_tuddcim parameter type wide_out_resp_t = logic ) ( - input logic soc_clk_i, - input logic clu_clk_i, - input logic rst_ni, - input logic widemem_bypass_i, + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, //----------------------------- // Interrupt ports //----------------------------- - input logic [ NrCores-1:0] debug_req_i, - input logic [ NrCores-1:0] meip_i, - input logic [ NrCores-1:0] mtip_i, - input logic [ NrCores-1:0] msip_i, + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, //----------------------------- // Cluster base addressing //----------------------------- - input logic [ 9:0] hart_base_id_i, - input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i, - input logic [ 31:0] boot_addr_i, + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports //----------------------------- - input narrow_in_req_t narrow_in_req_i, - output narrow_in_resp_t narrow_in_resp_o, - output narrow_out_req_t [ 1:0] narrow_out_req_o, - input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, //----------------------------- //Wide AXI ports //----------------------------- - output wide_out_req_t wide_out_req_o, - input wide_out_resp_t wide_out_resp_i + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i ); `include "axi/typedef.svh" @@ -55,16 +55,16 @@ module chimera_cluster_tuddcim localparam int WideDataWidth = $bits(wide_out_req_o.w.data); localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); - localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1; + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - typedef logic [Cfg.AddrWidth-1:0] axi_addr_t; - typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; - typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; - typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; @@ -117,7 +117,7 @@ module chimera_cluster_tuddcim axi_cluster_out_wide_req_t clu_axi_wide_mst_req; axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; - if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter narrow_adapter #( .narrow_in_req_t (axi_soc_out_narrow_req_t), diff --git a/hw/convolve/chimera_cluster_tuedcim.sv b/hw/convolve/chimera_cluster_tuedcim.sv index 826a8a8..52b1880 100644 --- a/hw/convolve/chimera_cluster_tuedcim.sv +++ b/hw/convolve/chimera_cluster_tuedcim.sv @@ -8,7 +8,7 @@ module chimera_cluster_tuedcim import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, + parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 2, parameter type narrow_in_req_t = logic, @@ -34,7 +34,7 @@ module chimera_cluster_tuedcim // Cluster base addressing //----------------------------- input logic [ 9:0] hart_base_id_i, - input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports @@ -55,16 +55,16 @@ module chimera_cluster_tuedcim localparam int WideDataWidth = $bits(wide_out_req_o.w.data); localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); - localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1; + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - typedef logic [Cfg.AddrWidth-1:0] axi_addr_t; - typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; - typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; - typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; @@ -117,7 +117,7 @@ module chimera_cluster_tuedcim axi_cluster_out_wide_req_t clu_axi_wide_mst_req; axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; - if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter narrow_adapter #( .narrow_in_req_t (axi_soc_out_narrow_req_t), diff --git a/hw/convolve/chimera_cluster_tuemega.sv b/hw/convolve/chimera_cluster_tuemega.sv index 102c5be..944a2b9 100644 --- a/hw/convolve/chimera_cluster_tuemega.sv +++ b/hw/convolve/chimera_cluster_tuemega.sv @@ -8,7 +8,7 @@ module chimera_cluster_tuemega import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, + parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 2, parameter type narrow_in_req_t = logic, @@ -34,7 +34,7 @@ module chimera_cluster_tuemega // Cluster base addressing //----------------------------- input logic [ 9:0] hart_base_id_i, - input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports @@ -55,16 +55,16 @@ module chimera_cluster_tuemega localparam int WideDataWidth = $bits(wide_out_req_o.w.data); localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); - localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1; + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - typedef logic [Cfg.AddrWidth-1:0] axi_addr_t; - typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; - typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; - typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; @@ -117,7 +117,7 @@ module chimera_cluster_tuemega axi_cluster_out_wide_req_t clu_axi_wide_mst_req; axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; - if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter narrow_adapter #( .narrow_in_req_t (axi_soc_out_narrow_req_t),