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HW: Add condition on AXI Isolation insertion
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@Lore0599
Lore0599 committed Sep 25, 2024
1 parent 1a46799 commit 14ab4ff
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Showing 2 changed files with 87 additions and 67 deletions.
151 changes: 84 additions & 67 deletions hw/chimera_clu_domain.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ module chimera_clu_domain
) (
input logic soc_clk_i,
input logic [ ExtClusters-1:0] clu_clk_i,
input logic [ ExtClusters-1:0] rst_ni,
input logic [ ExtClusters-1:0] rst_sync_ni,
input logic [ ExtClusters-1:0] widemem_bypass_i,
//-----------------------------
// Interrupt ports
Expand Down Expand Up @@ -76,83 +76,100 @@ module chimera_clu_domain

for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_clusters

// Add AXI isolation at the Narrow Input Interface
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (Cfg.AxiDataWidth),
.AxiIdWidth (AxiSlvIdWidth),
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (narrow_in_req_t),
.axi_resp_t (narrow_in_resp_t)
) i_iso_narrow_in_cluster (
.clk_i (soc_clk_i),
.rst_ni (rst_ni[extClusterIdx]),
.slv_req_i (narrow_in_req_i[extClusterIdx]),
.slv_resp_o(narrow_in_resp_o[extClusterIdx]),
.mst_req_o (narrow_in_isolated_req[extClusterIdx]),
.mst_resp_i(narrow_in_isolated_resp[extClusterIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o(isolated_narrow_in[extClusterIdx])
);

// Add AXI isolation at the Narrow Output Interface.
// Two ports for each cluster: one to convert stray wides, one for the original narrow
for (
genvar narrowOutIdx = 2 * extClusterIdx;
narrowOutIdx < 2 * extClusterIdx + 2;
narrowOutIdx++
) begin : gen_iso_narrow_out
if (Pasim == 1) begin : gen_cluster_iso
// Add AXI isolation at the Narrow Input Interface
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (Cfg.AxiDataWidth),
.AxiIdWidth (Cfg.AxiMstIdWidth),
.AxiIdWidth (AxiSlvIdWidth),
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (narrow_out_req_t),
.axi_resp_t (narrow_out_resp_t)
) i_iso_narrow_out_cluster (
.clk_i (soc_clk_i),
.rst_ni (rst_ni[extClusterIdx]),
.slv_req_i (narrow_out_isolated_req[narrowOutIdx]),
.slv_resp_o(narrow_out_isolated_resp[narrowOutIdx]),
.mst_req_o (narrow_out_req_o[narrowOutIdx]),
.mst_resp_i(narrow_out_resp_i[narrowOutIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o(isolated_narrow_out[narrowOutIdx])
.axi_req_t (narrow_in_req_t),
.axi_resp_t (narrow_in_resp_t)
) i_iso_narrow_in_cluster (
.clk_i (soc_clk_i),
.rst_sync_ni(rst_sync_ni[extClusterIdx]),
.slv_req_i (narrow_in_req_i[extClusterIdx]),
.slv_resp_o (narrow_in_resp_o[extClusterIdx]),
.mst_req_o (narrow_in_isolated_req[extClusterIdx]),
.mst_resp_i (narrow_in_isolated_resp[extClusterIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o (isolated_narrow_in[extClusterIdx])
);
end : gen_iso_narrow_out

// Add AXI isolation at the Wide Interface
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (AxiWideDataWidth),
.AxiIdWidth (Cfg.MemIslAxiMstIdWidth), // To Check
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (wide_out_req_t),
.axi_resp_t (wide_out_resp_t)
) i_iso_wide_cluster (
.clk_i (soc_clk_i),
.rst_ni (rst_ni[extClusterIdx]),
.slv_req_i (wide_out_isolated_req[extClusterIdx]),
.slv_resp_o(wide_out_isolated_resp[extClusterIdx]),
.mst_req_o (wide_out_req_o[extClusterIdx]),
.mst_resp_i(wide_out_resp_i[extClusterIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o(isolated_wide_out[extClusterIdx])
);

assign isolate_o[extClusterIdx] = isolated_narrow_in[extClusterIdx] &
// Add AXI isolation at the Narrow Output Interface.
// Two ports for each cluster: one to convert stray wides, one for the original narrow
for (
genvar narrowOutIdx = 2 * extClusterIdx;
narrowOutIdx < 2 * extClusterIdx + 2;
narrowOutIdx++
) begin : gen_iso_narrow_out
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (Cfg.AxiDataWidth),
.AxiIdWidth (Cfg.AxiMstIdWidth),
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (narrow_out_req_t),
.axi_resp_t (narrow_out_resp_t)
) i_iso_narrow_out_cluster (
.clk_i (soc_clk_i),
.rst_sync_ni(rst_sync_ni[extClusterIdx]),
.slv_req_i (narrow_out_isolated_req[narrowOutIdx]),
.slv_resp_o (narrow_out_isolated_resp[narrowOutIdx]),
.mst_req_o (narrow_out_req_o[narrowOutIdx]),
.mst_resp_i (narrow_out_resp_i[narrowOutIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o (isolated_narrow_out[narrowOutIdx])
);
end : gen_iso_narrow_out

// Add AXI isolation at the Wide Interface
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (AxiWideDataWidth),
.AxiIdWidth (Cfg.MemIslAxiMstIdWidth), // To Check
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (wide_out_req_t),
.axi_resp_t (wide_out_resp_t)
) i_iso_wide_cluster (
.clk_i (soc_clk_i),
.rst_sync_ni(rst_sync_ni[extClusterIdx]),
.slv_req_i (wide_out_isolated_req[extClusterIdx]),
.slv_resp_o (wide_out_isolated_resp[extClusterIdx]),
.mst_req_o (wide_out_req_o[extClusterIdx]),
.mst_resp_i (wide_out_resp_i[extClusterIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o (isolated_wide_out[extClusterIdx])
);

assign isolate_o[extClusterIdx] = isolated_narrow_in[extClusterIdx] &
isolated_narrow_out[2*extClusterIdx+:2] &
isolated_wide_out[extClusterIdx];

end else begin : gen_no_cluster_iso // bypass isolate if not required

assign narrow_in_isolated_req[extClusterIdx] = narrow_in_req_i[extClusterIdx];
assign narrow_in_resp_o[extClusterIdx] = narrow_in_isolated_resp[extClusterIdx];

assign narrow_out_req_o[2*extClusterIdx] = narrow_out_isolated_req[2*extClusterIdx];
assign narrow_out_isolated_resp[2*extClusterIdx] = narrow_out_resp_i[2*extClusterIdx];

assign narrow_out_req_o[2*extClusterIdx+1] = narrow_out_isolated_req[2*extClusterIdx+1];
assign narrow_out_isolated_resp[2*extClusterIdx+1] = narrow_out_resp_i[2*extClusterIdx+1];

assign narrow_in_isolated_req[extClusterIdx] = wide_out_isolated_req[extClusterIdx];
assign wide_out_isolated_resp[extClusterIdx] = wide_out_resp_i[extClusterIdx];

end : gen_no_cluster_iso

chimera_cluster #(
.Cfg (Cfg),
.NrCores (`NRCORES(extClusterIdx)),
Expand All @@ -165,7 +182,7 @@ module chimera_clu_domain
) i_chimera_cluster (
.soc_clk_i (soc_clk_i),
.clu_clk_i (clu_clk_i[extClusterIdx]),
.rst_ni (rst_ni[extClusterIdx]),
.rst_ni (rst_sync_ni[extClusterIdx]),
.widemem_bypass_i (widemem_bypass_i[extClusterIdx]),
.debug_req_i (debug_req_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]),
.meip_i (xeip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]),
Expand Down
3 changes: 3 additions & 0 deletions hw/chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,9 @@ package chimera_pkg;

localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;

// Power Aware Simulation Configuration Enable
localparam int unsigned Pasim = 0;

function automatic cheshire_cfg_t gen_chimera_cfg();
localparam int AddrWidth = DefaultCfg.AddrWidth;

Expand Down

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