diff --git a/target/sim/src/fixture_chimera_soc.sv b/target/sim/src/fixture_chimera_soc.sv
index 033335a..db4c9f9 100644
--- a/target/sim/src/fixture_chimera_soc.sv
+++ b/target/sim/src/fixture_chimera_soc.sv
@@ -28,36 +28,36 @@ module fixture_chimera_soc #(
   //  DUT  //
   ///////////
 
-  logic                 soc_clk;
-  logic                 clu_clk;
-  logic                 rst_n;
-  logic                 test_mode;
-  logic [          1:0] boot_mode;
-  logic                 rtc;
-
-  logic                 jtag_tck;
-  logic                 jtag_trst_n;
-  logic                 jtag_tms;
-  logic                 jtag_tdi;
-  logic                 jtag_tdo;
-
-  logic                 uart_tx;
-  logic                 uart_rx;
-
-  logic                 i2c_sda_o;
-  logic                 i2c_sda_i;
-  logic                 i2c_sda_en;
-  logic                 i2c_scl_o;
-  logic                 i2c_scl_i;
-  logic                 i2c_scl_en;
-
-  logic                 spih_sck_o;
-  logic                 spih_sck_en;
-  logic [SpihNumCs-1:0] spih_csb_o;
-  logic [SpihNumCs-1:0] spih_csb_en;
-  logic [          3:0] spih_sd_o;
-  logic [          3:0] spih_sd_i;
-  logic [          3:0] spih_sd_en;
+  logic                                   soc_clk;
+  logic                                   clu_clk;
+  logic                                   rst_n;
+  logic                                   test_mode;
+  logic [           1:0]                  boot_mode;
+  logic                                   rtc;
+
+  logic                                   jtag_tck;
+  logic                                   jtag_trst_n;
+  logic                                   jtag_tms;
+  logic                                   jtag_tdi;
+  logic                                   jtag_tdo;
+
+  logic                                   uart_tx;
+  logic                                   uart_rx;
+
+  logic                                   i2c_sda_o;
+  logic                                   i2c_sda_i;
+  logic                                   i2c_sda_en;
+  logic                                   i2c_scl_o;
+  logic                                   i2c_scl_i;
+  logic                                   i2c_scl_en;
+
+  logic                                   spih_sck_o;
+  logic                                   spih_sck_en;
+  logic [ SpihNumCs-1:0]                  spih_csb_o;
+  logic [ SpihNumCs-1:0]                  spih_csb_en;
+  logic [           3:0]                  spih_sd_o;
+  logic [           3:0]                  spih_sd_i;
+  logic [           3:0]                  spih_sd_en;
 
   logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no;
   logic [HypNumPhys-1:0]                  hyper_ck_i;
@@ -67,17 +67,17 @@ module fixture_chimera_soc #(
   logic [HypNumPhys-1:0]                  hyper_rwds_o;
   logic [HypNumPhys-1:0]                  hyper_rwds_i;
   logic [HypNumPhys-1:0]                  hyper_rwds_oe_o;
-  logic [HypNumPhys-1:0][7:0]             hyper_dq_i;
-  logic [HypNumPhys-1:0][7:0]             hyper_dq_o;
+  logic [HypNumPhys-1:0][            7:0] hyper_dq_i;
+  logic [HypNumPhys-1:0][            7:0] hyper_dq_o;
   logic [HypNumPhys-1:0]                  hyper_dq_oe_o;
   logic [HypNumPhys-1:0]                  hyper_reset_no;
 
-  wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn;
-  wire [HypNumPhys-1:0]                  pad_hyper_ck;
-  wire [HypNumPhys-1:0]                  pad_hyper_ckn;
-  wire [HypNumPhys-1:0]                  pad_hyper_rwds;
-  wire [HypNumPhys-1:0]                  pad_hyper_resetn;
-  wire [HypNumPhys-1:0][7:0]             pad_hyper_dq;
+  wire  [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn;
+  wire  [HypNumPhys-1:0]                  pad_hyper_ck;
+  wire  [HypNumPhys-1:0]                  pad_hyper_ckn;
+  wire  [HypNumPhys-1:0]                  pad_hyper_rwds;
+  wire  [HypNumPhys-1:0]                  pad_hyper_resetn;
+  wire  [HypNumPhys-1:0][            7:0] pad_hyper_dq;
 
   chimera_top_wrapper #(
     .SelectedCfg(SelectedCfg)
@@ -152,16 +152,16 @@ module fixture_chimera_soc #(
   ///////////
 
   vip_chimera_soc #(
-    .DutCfg           (DutCfg),
+    .DutCfg                (DutCfg),
     // Determine whether we preload the hyperram model or not User preload. If 0, the memory model
     // is not preloaded at time 0.
-    .HypUserPreload ( `HYP_USER_PRELOAD ),
+    .HypUserPreload        (`HYP_USER_PRELOAD),
     // Mem files for hyperram model. The argument is considered only if HypUserPreload==1 in the
     // memory model.
-    .Hyp0UserPreloadMemFile ( `HYP0_PRELOAD_MEM_FILE ),
-    .Hyp1UserPreloadMemFile ( `HYP1_PRELOAD_MEM_FILE ),
-    .axi_ext_mst_req_t(axi_mst_req_t),
-    .axi_ext_mst_rsp_t(axi_mst_rsp_t)
+    .Hyp0UserPreloadMemFile(`HYP0_PRELOAD_MEM_FILE),
+    .Hyp1UserPreloadMemFile(`HYP1_PRELOAD_MEM_FILE),
+    .axi_ext_mst_req_t     (axi_mst_req_t),
+    .axi_ext_mst_rsp_t     (axi_mst_rsp_t)
   ) vip (
     .*
   );
diff --git a/target/sim/src/tb_chimera_pkg.sv b/target/sim/src/tb_chimera_pkg.sv
index 2c5a09f..85d3141 100644
--- a/target/sim/src/tb_chimera_pkg.sv
+++ b/target/sim/src/tb_chimera_pkg.sv
@@ -43,7 +43,7 @@ package tb_chimera_pkg;
   };
 
   // HyperBus
-  localparam int HypNumPhys  = 2;
+  localparam int HypNumPhys = 2;
   localparam int HypNumChips = 2;
 
   //TODO(smazzola): define correct parameters after HyperBus integration
diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv
index 000c747..9b191bb 100644
--- a/target/sim/src/vip_chimera_soc.sv
+++ b/target/sim/src/vip_chimera_soc.sv
@@ -13,70 +13,70 @@ module vip_chimera_soc
   import cheshire_pkg::*;
 #(
   // DUT (must be set)
-  parameter cheshire_cfg_t DutCfg            = '0,
-  parameter int unsigned HypNumPhys     = 2,
-  parameter int unsigned HypNumChips    = 2,
+  parameter cheshire_cfg_t DutCfg      = '0,
+  parameter int unsigned   HypNumPhys  = 2,
+  parameter int unsigned   HypNumChips = 2,
 
-  parameter type         axi_ext_mst_req_t = logic,
-  parameter type         axi_ext_mst_rsp_t = logic,
+  parameter type         axi_ext_mst_req_t      = logic,
+  parameter type         axi_ext_mst_rsp_t      = logic,
   // Timing
-  parameter time         ClkPeriodClu      = 2ns,
-  parameter time         ClkPeriodSys      = 5ns,
-  parameter time         ClkPeriodJtag     = 20ns,
-  parameter time         ClkPeriodRtc      = 30518ns,
-  parameter int unsigned RstCycles         = 5,
-  parameter real         TAppl             = 0.1,
-  parameter real         TTest             = 0.9,
+  parameter time         ClkPeriodClu           = 2ns,
+  parameter time         ClkPeriodSys           = 5ns,
+  parameter time         ClkPeriodJtag          = 20ns,
+  parameter time         ClkPeriodRtc           = 30518ns,
+  parameter int unsigned RstCycles              = 5,
+  parameter real         TAppl                  = 0.1,
+  parameter real         TTest                  = 0.9,
   // UART
-  parameter int unsigned UartBaudRate      = 115200,
-  parameter int unsigned UartParityEna     = 0,
-  parameter int unsigned UartBurstBytes    = 256,
-  parameter int unsigned UartWaitCycles    = 60,
+  parameter int unsigned UartBaudRate           = 115200,
+  parameter int unsigned UartParityEna          = 0,
+  parameter int unsigned UartBurstBytes         = 256,
+  parameter int unsigned UartWaitCycles         = 60,
   // Serial Link
-  parameter int unsigned SlinkMaxWaitAx    = 100,
-  parameter int unsigned SlinkMaxWaitR     = 5,
-  parameter int unsigned SlinkMaxWaitResp  = 20,
-  parameter int unsigned SlinkBurstBytes   = 1024,
-  parameter int unsigned SlinkMaxTxns      = 32,
-  parameter int unsigned SlinkMaxTxnsPerId = 16,
-  parameter bit          SlinkAxiDebug     = 0,
+  parameter int unsigned SlinkMaxWaitAx         = 100,
+  parameter int unsigned SlinkMaxWaitR          = 5,
+  parameter int unsigned SlinkMaxWaitResp       = 20,
+  parameter int unsigned SlinkBurstBytes        = 1024,
+  parameter int unsigned SlinkMaxTxns           = 32,
+  parameter int unsigned SlinkMaxTxnsPerId      = 16,
+  parameter bit          SlinkAxiDebug          = 0,
   // HyperRAM (hardcoded to HypNumPhys = 2)
-  parameter int unsigned HypUserPreload = 0,
+  parameter int unsigned HypUserPreload         = 0,
   parameter string       Hyp0UserPreloadMemFile = "",
   parameter string       Hyp1UserPreloadMemFile = "",
   // Derived Parameters;  *do not override*
-  parameter int unsigned AxiStrbWidth      = DutCfg.AxiDataWidth / 8,
-  parameter int unsigned AxiStrbBits       = $clog2(DutCfg.AxiDataWidth / 8)
+  parameter int unsigned AxiStrbWidth           = DutCfg.AxiDataWidth / 8,
+  parameter int unsigned AxiStrbBits            = $clog2(DutCfg.AxiDataWidth / 8)
 ) (
-  output logic                 soc_clk,
-  output logic                 clu_clk,
-  output logic                 rst_n,
-  output logic                 test_mode,
-  output logic [          1:0] boot_mode,
-  output logic                 rtc,
+  output logic                                   soc_clk,
+  output logic                                   clu_clk,
+  output logic                                   rst_n,
+  output logic                                   test_mode,
+  output logic [           1:0]                  boot_mode,
+  output logic                                   rtc,
   // JTAG interface
-  output logic                 jtag_tck,
-  output logic                 jtag_trst_n,
-  output logic                 jtag_tms,
-  output logic                 jtag_tdi,
-  input  logic                 jtag_tdo,
+  output logic                                   jtag_tck,
+  output logic                                   jtag_trst_n,
+  output logic                                   jtag_tms,
+  output logic                                   jtag_tdi,
+  input  logic                                   jtag_tdo,
   // UART interface
-  input  logic                 uart_tx,
-  output logic                 uart_rx,
+  input  logic                                   uart_tx,
+  output logic                                   uart_rx,
   // I2C interface
-  inout  wire                  i2c_sda,
-  inout  wire                  i2c_scl,
+  inout  wire                                    i2c_sda,
+  inout  wire                                    i2c_scl,
   // SPI host interface
-  inout  wire                  spih_sck,
-  inout  wire  [SpihNumCs-1:0] spih_csb,
-  inout  wire  [          3:0] spih_sd,
+  inout  wire                                    spih_sck,
+  inout  wire  [ SpihNumCs-1:0]                  spih_csb,
+  inout  wire  [           3:0]                  spih_sd,
   // Hyperbus interface
-  wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
-  wire [HypNumPhys-1:0]                  pad_hyper_ck,
-  wire [HypNumPhys-1:0]                  pad_hyper_ckn,
-  wire [HypNumPhys-1:0]                  pad_hyper_rwds,
-  wire [HypNumPhys-1:0]                  pad_hyper_resetn,
-  wire [HypNumPhys-1:0][7:0]             pad_hyper_dq
+         wire  [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
+         wire  [HypNumPhys-1:0]                  pad_hyper_ck,
+         wire  [HypNumPhys-1:0]                  pad_hyper_ckn,
+         wire  [HypNumPhys-1:0]                  pad_hyper_rwds,
+         wire  [HypNumPhys-1:0]                  pad_hyper_resetn,
+         wire  [HypNumPhys-1:0][            7:0] pad_hyper_dq
 );
 
   `include "cheshire/typedef.svh"
@@ -571,43 +571,46 @@ module vip_chimera_soc
   // Hyperbus //
   //////////////
 
-  localparam string HypUserPreloadMemFiles [HypNumPhys] = '{Hyp0UserPreloadMemFile, Hyp1UserPreloadMemFile};
+  localparam string HypUserPreloadMemFiles[HypNumPhys] = '{
+      Hyp0UserPreloadMemFile,
+      Hyp1UserPreloadMemFile
+  };
 
-  for (genvar i=0; i<HypNumPhys; i++) begin : hyperrams
-    for (genvar j=0; j<HypNumChips; j++) begin : chips
+  for (genvar i = 0; i < HypNumPhys; i++) begin : hyperrams
+    for (genvar j = 0; j < HypNumChips; j++) begin : chips
       s27ks0641 #(
-        .UserPreload   ( HypUserPreload ),
-        .mem_file_name ( HypUserPreloadMemFiles[i] ),
-        .TimingModel ( "S27KS0641DPBHI020" )
+        .UserPreload  (HypUserPreload),
+        .mem_file_name(HypUserPreloadMemFiles[i]),
+        .TimingModel  ("S27KS0641DPBHI020")
       ) dut (
-        .DQ7      ( pad_hyper_dq[i][7]  ),
-        .DQ6      ( pad_hyper_dq[i][6]  ),
-        .DQ5      ( pad_hyper_dq[i][5]  ),
-        .DQ4      ( pad_hyper_dq[i][4]  ),
-        .DQ3      ( pad_hyper_dq[i][3]  ),
-        .DQ2      ( pad_hyper_dq[i][2]  ),
-        .DQ1      ( pad_hyper_dq[i][1]  ),
-        .DQ0      ( pad_hyper_dq[i][0]  ),
-        .RWDS     ( pad_hyper_rwds[i]   ),
-        .CSNeg    ( pad_hyper_csn[i][j] ),
-        .CK       ( pad_hyper_ck[i]     ),
-        .CKNeg    ( pad_hyper_ckn[i]    ),
-        .RESETNeg ( pad_hyper_resetn[i] )
+        .DQ7     (pad_hyper_dq[i][7]),
+        .DQ6     (pad_hyper_dq[i][6]),
+        .DQ5     (pad_hyper_dq[i][5]),
+        .DQ4     (pad_hyper_dq[i][4]),
+        .DQ3     (pad_hyper_dq[i][3]),
+        .DQ2     (pad_hyper_dq[i][2]),
+        .DQ1     (pad_hyper_dq[i][1]),
+        .DQ0     (pad_hyper_dq[i][0]),
+        .RWDS    (pad_hyper_rwds[i]),
+        .CSNeg   (pad_hyper_csn[i][j]),
+        .CK      (pad_hyper_ck[i]),
+        .CKNeg   (pad_hyper_ckn[i]),
+        .RESETNeg(pad_hyper_resetn[i])
       );
     end
   end
 
-  for (genvar p=0; p<HypNumPhys; p++) begin : sdf_annotation
-     for (genvar l=0; l<HypNumChips; l++) begin : sdf_annotation
-        initial begin
+  for (genvar p = 0; p < HypNumPhys; p++) begin : sdf_annotation
+    for (genvar l = 0; l < HypNumChips; l++) begin : sdf_annotation
+      initial begin
 `ifndef PATH_TO_HYP_SDF
-           automatic string sdf_file_path = "../../../hyperbus/models/s27ks0641/s27ks0641.sdf";
+        automatic string sdf_file_path = "../../../hyperbus/models/s27ks0641/s27ks0641.sdf";
 `else
-           automatic string sdf_file_path = `PATH_TO_HYP_SDF;
+        automatic string sdf_file_path = `PATH_TO_HYP_SDF;
 `endif
-           $sdf_annotate(sdf_file_path, hyperrams[p].chips[l].dut);
-           $display("Mem (%d,%d)",p,l);
-        end
+        $sdf_annotate(sdf_file_path, hyperrams[p].chips[l].dut);
+        $display("Mem (%d,%d)", p, l);
+      end
     end
   end
 
@@ -622,27 +625,27 @@ module vip_cheshire_soc_tristate
   parameter int unsigned HypNumChips = 2
 ) (
   // I2C pad IO
-  output logic                 i2c_sda_i,
-  input  logic                 i2c_sda_o,
-  input  logic                 i2c_sda_en,
-  output logic                 i2c_scl_i,
-  input  logic                 i2c_scl_o,
-  input  logic                 i2c_scl_en,
+  output logic                                   i2c_sda_i,
+  input  logic                                   i2c_sda_o,
+  input  logic                                   i2c_sda_en,
+  output logic                                   i2c_scl_i,
+  input  logic                                   i2c_scl_o,
+  input  logic                                   i2c_scl_en,
   // SPI host pad IO
-  input  logic                 spih_sck_o,
-  input  logic                 spih_sck_en,
-  input  logic [SpihNumCs-1:0] spih_csb_o,
-  input  logic [SpihNumCs-1:0] spih_csb_en,
-  output logic [          3:0] spih_sd_i,
-  input  logic [          3:0] spih_sd_o,
-  input  logic [          3:0] spih_sd_en,
+  input  logic                                   spih_sck_o,
+  input  logic                                   spih_sck_en,
+  input  logic [ SpihNumCs-1:0]                  spih_csb_o,
+  input  logic [ SpihNumCs-1:0]                  spih_csb_en,
+  output logic [           3:0]                  spih_sd_i,
+  input  logic [           3:0]                  spih_sd_o,
+  input  logic [           3:0]                  spih_sd_en,
   // I2C wires
-  inout  wire                  i2c_sda,
-  inout  wire                  i2c_scl,
+  inout  wire                                    i2c_sda,
+  inout  wire                                    i2c_scl,
   // SPI host wires
-  inout  wire                  spih_sck,
-  inout  wire  [SpihNumCs-1:0] spih_csb,
-  inout  wire  [          3:0] spih_sd,
+  inout  wire                                    spih_sck,
+  inout  wire  [ SpihNumCs-1:0]                  spih_csb,
+  inout  wire  [           3:0]                  spih_sd,
   // Hyperbus pad IO
   input  logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
   output logic [HypNumPhys-1:0]                  hyper_ck_i,
@@ -652,17 +655,17 @@ module vip_cheshire_soc_tristate
   input  logic [HypNumPhys-1:0]                  hyper_rwds_o,
   output logic [HypNumPhys-1:0]                  hyper_rwds_i,
   input  logic [HypNumPhys-1:0]                  hyper_rwds_oe_o,
-  output logic [HypNumPhys-1:0][7:0]             hyper_dq_i,
-  input  logic [HypNumPhys-1:0][7:0]             hyper_dq_o,
+  output logic [HypNumPhys-1:0][            7:0] hyper_dq_i,
+  input  logic [HypNumPhys-1:0][            7:0] hyper_dq_o,
   input  logic [HypNumPhys-1:0]                  hyper_dq_oe_o,
   input  logic [HypNumPhys-1:0]                  hyper_reset_no,
   // Hyperbus wires
-  wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
-  wire [HypNumPhys-1:0]                  pad_hyper_ck,
-  wire [HypNumPhys-1:0]                  pad_hyper_ckn,
-  wire [HypNumPhys-1:0]                  pad_hyper_rwds,
-  wire [HypNumPhys-1:0]                  pad_hyper_resetn,
-  wire [HypNumPhys-1:0][7:0]             pad_hyper_dq
+         wire  [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
+         wire  [HypNumPhys-1:0]                  pad_hyper_ck,
+         wire  [HypNumPhys-1:0]                  pad_hyper_ckn,
+         wire  [HypNumPhys-1:0]                  pad_hyper_rwds,
+         wire  [HypNumPhys-1:0]                  pad_hyper_resetn,
+         wire  [HypNumPhys-1:0][            7:0] pad_hyper_dq
 );
 
   // I2C
@@ -688,51 +691,51 @@ module vip_cheshire_soc_tristate
     pullup (spih_csb[i]);
   end
 
-  for (genvar i = 0 ; i<HypNumPhys; i++) begin : gen_hyper_phy
-    for (genvar j = 0; j<HypNumChips; j++) begin : gen_hyper_cs
+  for (genvar i = 0; i < HypNumPhys; i++) begin : gen_hyper_phy
+    for (genvar j = 0; j < HypNumChips; j++) begin : gen_hyper_cs
       pad_functional_pd padinst_hyper_csno (
-        .OEN ( 1'b0                 ),
-        .I   ( hyper_cs_no[i][j]    ),
-        .O   (                      ),
-        .PEN (                      ),
-        .PAD ( pad_hyper_csn[i][j]  )
+        .OEN(1'b0),
+        .I  (hyper_cs_no[i][j]),
+        .O  (),
+        .PEN(),
+        .PAD(pad_hyper_csn[i][j])
       );
     end
     pad_functional_pd padinst_hyper_ck (
-      .OEN ( 1'b0            ),
-      .I   ( hyper_ck_o[i]   ),
-      .O   (                 ),
-      .PEN (                 ),
-      .PAD ( pad_hyper_ck[i] )
+      .OEN(1'b0),
+      .I  (hyper_ck_o[i]),
+      .O  (),
+      .PEN(),
+      .PAD(pad_hyper_ck[i])
     );
-    pad_functional_pd padinst_hyper_ckno   (
-      .OEN ( 1'b0              ),
-      .I   ( hyper_ck_no[i]    ),
-      .O   (                   ),
-      .PEN (                   ),
-      .PAD ( pad_hyper_ckn[i]  )
+    pad_functional_pd padinst_hyper_ckno (
+      .OEN(1'b0),
+      .I  (hyper_ck_no[i]),
+      .O  (),
+      .PEN(),
+      .PAD(pad_hyper_ckn[i])
     );
-    pad_functional_pd padinst_hyper_rwds0  (
-      .OEN (~hyper_rwds_oe_o[i] ),
-      .I   ( hyper_rwds_o[i]    ),
-      .O   ( hyper_rwds_i[i]    ),
-      .PEN (                    ),
-      .PAD ( pad_hyper_rwds[i]  )
+    pad_functional_pd padinst_hyper_rwds0 (
+      .OEN(~hyper_rwds_oe_o[i]),
+      .I  (hyper_rwds_o[i]),
+      .O  (hyper_rwds_i[i]),
+      .PEN(),
+      .PAD(pad_hyper_rwds[i])
     );
     pad_functional_pd padinst_hyper_resetn (
-      .OEN ( 1'b0               ),
-      .I   ( hyper_reset_no[i]  ),
-      .O   (                    ),
-      .PEN (                    ),
-      .PAD ( pad_hyper_resetn[i] )
+      .OEN(1'b0),
+      .I  (hyper_reset_no[i]),
+      .O  (),
+      .PEN(),
+      .PAD(pad_hyper_resetn[i])
     );
     for (genvar j = 0; j < 8; j++) begin : gen_hyper_dq
-      pad_functional_pd padinst_hyper_dqio0  (
-        .OEN (~hyper_dq_oe_o[i]   ),
-        .I   ( hyper_dq_o[i][j]   ),
-        .O   ( hyper_dq_i[i][j]   ),
-        .PEN (                    ),
-        .PAD ( pad_hyper_dq[i][j] )
+      pad_functional_pd padinst_hyper_dqio0 (
+        .OEN(~hyper_dq_oe_o[i]),
+        .I  (hyper_dq_o[i][j]),
+        .O  (hyper_dq_i[i][j]),
+        .PEN(),
+        .PAD(pad_hyper_dq[i][j])
       );
     end
   end : gen_hyper_phy