From 3c376b04b56c3300056050a59fadfcd62eae9d9e Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Thu, 19 Sep 2024 18:45:57 +0200 Subject: [PATCH] Makefile: Integrate HyperRAM VIP in build flow --- .gitignore | 2 ++ Bender.lock | 18 ++++++++++++++---- Bender.yml | 3 +++ Makefile | 1 + bender.mk | 2 +- target/sim/sim.mk | 32 +++++++++++++++++++++++++------- 6 files changed, 46 insertions(+), 12 deletions(-) diff --git a/.gitignore b/.gitignore index 9eef0bc..edecb35 100644 --- a/.gitignore +++ b/.gitignore @@ -4,6 +4,7 @@ transcript .venv cheshire idma +hyperbus # EMACS @@ -30,6 +31,7 @@ utils/verible-verilog # SIM +target/sim/src/hyp_vip target/sim/vsim/work target/sim/vsim/transcript target/sim/vsim/trace* diff --git a/Bender.lock b/Bender.lock index 229d989..84c1deb 100644 --- a/Bender.lock +++ b/Bender.lock @@ -60,8 +60,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 - version: 0.1.3 + revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e + version: 0.1.4 source: Git: https://github.com/pulp-platform/axi_vga.git dependencies: @@ -165,6 +165,16 @@ packages: Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells + hyperbus: + revision: f039e601c8b6590181734e6d26ff8b77aa380412 + version: null + source: + Git: https://github.com/pulp-platform/hyperbus.git + dependencies: + - axi + - common_cells + - register_interface + - tech_cells_generic idma: revision: 9edf489f57389dce5e71252c79e337f527d3aded version: null @@ -215,8 +225,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d - version: 0.4.4 + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index 8f7a1d3..7438a6a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -15,11 +15,13 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh workspace: package_links: cheshire: cheshire idma: idma + hyperbus: hyperbus sources: - hw/chimera_pkg.sv @@ -34,6 +36,7 @@ sources: - target: any(simulation, test) files: + - hyperbus/models/s27ks0641/s27ks0641.v - target/sim/src/vip_chimera_soc.sv - target/sim/src/fixture_chimera_soc.sv - target/sim/src/tb_chimera_soc.sv diff --git a/Makefile b/Makefile index c38ccb3..05db9e1 100644 --- a/Makefile +++ b/Makefile @@ -14,6 +14,7 @@ VERIBLE_VERILOG_FORMAT ?= $(CHIM_UTILS_DIR)/verible-verilog/verible-verilog-form CHS_ROOT ?= $(shell $(BENDER) path cheshire) SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster) IDMA_ROOT ?= $(shell $(BENDER) path idma) +HYPERB_ROOT ?= $(shell $(BENDER) path hyperbus) CHS_XLEN ?= 32 diff --git a/bender.mk b/bender.mk index 3a7350a..9652ccf 100644 --- a/bender.mk +++ b/bender.mk @@ -7,4 +7,4 @@ COMMON_TARGS ?= COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl -SIM_TARGS = -t test -t sim +SIM_TARGS = $(COMMON_TARGS) -t test -t sim diff --git a/target/sim/sim.mk b/target/sim/sim.mk index fa5ba1d..3ac2a4c 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -3,23 +3,41 @@ # SPDX-License-Identifier: Apache-2.0 # # Moritz Scherer +# Sergio Mazzola ifndef chim_sim_mk chim_sim_mk=1 CHIM_SIM_DIR ?= $(CHIM_ROOT)/target/sim -.PHONY: sim sim-clean +# Init vsim compilation +.PHONY: chim-sim +chim-sim: chim-hyperram-model $(CHIM_SIM_DIR)/vsim/compile.tcl -chim-sim-clean: - @rm -rf $(CHIM_SIM_DIR)/vsim/work - @rm -rf $(CHIM_SIM_DIR)/vsim/transcript - @rm -f $(CHIM_SIM_DIR)/vsim/compile.tcl +# Get HyperRAM verification IP (VIP) for simulation +.PHONY: chim-hyperram-model +chim-hyperram-model: + make -C $(HYPERB_ROOT) models/s27ks0641 + +# Defines for hyperram model preload at time 0 +HYP_USER_PRELOAD ?= 0 +HYP0_PRELOAD_MEM_FILE ?= "" +HYP1_PRELOAD_MEM_FILE ?= "" -chim-sim: $(CHIM_SIM_DIR)/vsim/compile.tcl +CHIM_VLOG_ARGS += +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)" +CHIM_VLOG_ARGS += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\" +CHIM_VLOG_ARGS += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\" +# Generate vsim compilation script $(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init - @bender script vsim $(COMMON_TARGS) $(SIM_TARGS) --vlog-arg="$(VLOG_ARGS)"> $@ + @bender script vsim $(SIM_TARGS) --vlog-arg="$(CHIM_VLOG_ARGS)" > $@ echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ +# Clean +.PHONY: chim-sim-clean +chim-sim-clean: + @rm -rf $(CHIM_SIM_DIR)/vsim/work + @rm -rf $(CHIM_SIM_DIR)/vsim/transcript + @rm -f $(CHIM_SIM_DIR)/vsim/compile.tcl + endif # chim_sim_mk