From 4fe94d4a03da3f99e758bb3b93846fca9fec51d6 Mon Sep 17 00:00:00 2001 From: Lorenzo Leone Date: Mon, 9 Sep 2024 16:34:49 +0200 Subject: [PATCH] HW: Add rst for each ecternal cluster to be driven by PMU controller --- hw/chimera_clu_domain.sv | 4 +- hw/chimera_top_wrapper.sv | 87 ++++++++++++++++++++------------------- 2 files changed, 47 insertions(+), 44 deletions(-) diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index f7c083d..0fe0c3b 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -25,7 +25,7 @@ module chimera_clu_domain ) ( input logic soc_clk_i, input logic [ ExtClusters-1:0] clu_clk_i, - input logic rst_ni, + input logic [ ExtClusters-1:0] rst_ni, input logic [ ExtClusters-1:0] widemem_bypass_i, //----------------------------- // Interrupt ports @@ -62,7 +62,7 @@ module chimera_clu_domain ) i_chimera_cluster ( .soc_clk_i (soc_clk_i), .clu_clk_i (clu_clk_i[extClusterIdx]), - .rst_ni, + .rst_ni (rst_ni[extClusterIdx]), .widemem_bypass_i (widemem_bypass_i[extClusterIdx]), .debug_req_i (debug_req_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), .meip_i (xeip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index 60b64ce..f279e20 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -11,55 +11,58 @@ module chimera_top_wrapper #( parameter int unsigned SelectedCfg = 0 ) ( - input logic soc_clk_i, - input logic clu_clk_i, - input logic rst_ni, - input logic test_mode_i, - input logic [ 1:0] boot_mode_i, - input logic rtc_i, + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic test_mode_i, + input logic [ 1:0] boot_mode_i, + input logic rtc_i, // JTAG interface - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - output logic jtag_tdo_oe_o, + input logic jtag_tck_i, + input logic jtag_trst_ni, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o, + output logic jtag_tdo_oe_o, // UART interface - output logic uart_tx_o, - input logic uart_rx_i, + output logic uart_tx_o, + input logic uart_rx_i, // UART modem flow control - output logic uart_rts_no, - output logic uart_dtr_no, - input logic uart_cts_ni, - input logic uart_dsr_ni, - input logic uart_dcd_ni, - input logic uart_rin_ni, + output logic uart_rts_no, + output logic uart_dtr_no, + input logic uart_cts_ni, + input logic uart_dsr_ni, + input logic uart_dcd_ni, + input logic uart_rin_ni, // I2C interface - output logic i2c_sda_o, - input logic i2c_sda_i, - output logic i2c_sda_en_o, - output logic i2c_scl_o, - input logic i2c_scl_i, - output logic i2c_scl_en_o, + output logic i2c_sda_o, + input logic i2c_sda_i, + output logic i2c_sda_en_o, + output logic i2c_scl_o, + input logic i2c_scl_i, + output logic i2c_scl_en_o, // SPI host interface - output logic spih_sck_o, - output logic spih_sck_en_o, - output logic [SpihNumCs-1:0] spih_csb_o, - output logic [SpihNumCs-1:0] spih_csb_en_o, - output logic [ 3:0] spih_sd_o, - output logic [ 3:0] spih_sd_en_o, - input logic [ 3:0] spih_sd_i, + output logic spih_sck_o, + output logic spih_sck_en_o, + output logic [ SpihNumCs-1:0] spih_csb_o, + output logic [ SpihNumCs-1:0] spih_csb_en_o, + output logic [ 3:0] spih_sd_o, + output logic [ 3:0] spih_sd_en_o, + input logic [ 3:0] spih_sd_i, // GPIO interface - input logic [ 31:0] gpio_i, - output logic [ 31:0] gpio_o, - output logic [ 31:0] gpio_en_o, + input logic [ 31:0] gpio_i, + output logic [ 31:0] gpio_o, + output logic [ 31:0] gpio_en_o, // APB interface - input apb_resp_t apb_rsp_i, - output apb_req_t apb_req_o, + input apb_resp_t apb_rsp_i, + output apb_req_t apb_req_o, // PMU Host control signals - input logic pmu_rst_host_ni, - input logic pmu_clkgate_en_host_i, - output logic [ 31:0] pmu_interrupts_o + input logic pmu_rst_host_ni, + input logic pmu_clkgate_en_host_i, + output logic [ 31:0] pmu_interrupts_o, + // PMU Clusters control signals + input logic [ExtClusters-1:0] pmu_rst_clusters_ni, + input logic [ExtClusters-1:0] pmu_clkgate_en_clusters_i ); @@ -320,7 +323,7 @@ module chimera_top_wrapper ) i_cluster_domain ( .soc_clk_i (soc_clk_i), .clu_clk_i (clu_clk_gated), - .rst_ni, + .rst_ni (pmu_rst_clusters_ni), .widemem_bypass_i (wide_mem_bypass_mode), .debug_req_i (dbg_ext_req), .xeip_i (xeip_ext),