From 5c62a11484f6cd7d966f56d69a200b8151921969 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 20 Sep 2024 18:18:40 +0200 Subject: [PATCH] Sim: Integrate HyperRAM VIP in Chimera tb (HyperBus still not in SoC) --- Bender.yml | 1 + target/sim/sim.mk | 1 + target/sim/src/fixture_chimera_soc.sv | 42 ++++++++ target/sim/src/tb_chimera_pkg.sv | 8 ++ target/sim/src/tb_chimera_soc.sv | 15 +++ target/sim/src/vip_chimera_soc.sv | 141 ++++++++++++++++++++++++-- 6 files changed, 202 insertions(+), 6 deletions(-) diff --git a/Bender.yml b/Bender.yml index 7438a6a..2358de4 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,6 +16,7 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 } workspace: package_links: diff --git a/target/sim/sim.mk b/target/sim/sim.mk index b9df5bb..cecda9f 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -46,6 +46,7 @@ HYP1_PRELOAD_MEM_FILE ?= "" CHIM_VLOG_ARGS += +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)" CHIM_VLOG_ARGS += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\" CHIM_VLOG_ARGS += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\" +CHIM_VLOG_ARGS += +define+PATH_TO_HYP_SDF=\"$(realpath $(HYPERB_ROOT)/models/s27ks0641/s27ks0641.sdf)\" # Generate vsim compilation script $(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init diff --git a/target/sim/src/fixture_chimera_soc.sv b/target/sim/src/fixture_chimera_soc.sv index 7f50aaf..033335a 100644 --- a/target/sim/src/fixture_chimera_soc.sv +++ b/target/sim/src/fixture_chimera_soc.sv @@ -17,6 +17,7 @@ module fixture_chimera_soc #( import cheshire_pkg::*; import tb_cheshire_pkg::*; import chimera_pkg::*; + import tb_chimera_pkg::*; localparam cheshire_cfg_t DutCfg = ChimeraCfg[SelectedCfg]; @@ -58,8 +59,31 @@ module fixture_chimera_soc #( logic [ 3:0] spih_sd_i; logic [ 3:0] spih_sd_en; + logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no; + logic [HypNumPhys-1:0] hyper_ck_i; + logic [HypNumPhys-1:0] hyper_ck_o; + logic [HypNumPhys-1:0] hyper_ck_ni; + logic [HypNumPhys-1:0] hyper_ck_no; + logic [HypNumPhys-1:0] hyper_rwds_o; + logic [HypNumPhys-1:0] hyper_rwds_i; + logic [HypNumPhys-1:0] hyper_rwds_oe_o; + logic [HypNumPhys-1:0][7:0] hyper_dq_i; + logic [HypNumPhys-1:0][7:0] hyper_dq_o; + logic [HypNumPhys-1:0] hyper_dq_oe_o; + logic [HypNumPhys-1:0] hyper_reset_no; + + wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn; + wire [HypNumPhys-1:0] pad_hyper_ck; + wire [HypNumPhys-1:0] pad_hyper_ckn; + wire [HypNumPhys-1:0] pad_hyper_rwds; + wire [HypNumPhys-1:0] pad_hyper_resetn; + wire [HypNumPhys-1:0][7:0] pad_hyper_dq; + chimera_top_wrapper #( .SelectedCfg(SelectedCfg) + //TODO(smazzola): Add HyperBus parameters + // .HypNumPhys ( HypNumPhys ), + // .HypNumChips ( HypNumChips ), ) dut ( .soc_clk_i (soc_clk), .clu_clk_i (clu_clk), @@ -97,6 +121,17 @@ module fixture_chimera_soc #( .gpio_i ('0), .gpio_o (), .gpio_en_o () + //TODO(smazzola): Add HyperBus signals + // .hyper_cs_no ( hyper_cs_no ), + // .hyper_ck_o ( hyper_ck_o ), + // .hyper_ck_no ( hyper_ck_no ), + // .hyper_rwds_o ( hyper_rwds_o ), + // .hyper_rwds_i ( hyper_rwds_i ), + // .hyper_rwds_oe_o ( hyper_rwds_oe_o ), + // .hyper_dq_i ( hyper_dq_i ), + // .hyper_dq_o ( hyper_dq_o ), + // .hyper_dq_oe_o ( hyper_dq_oe_o ), + // .hyper_reset_no ( hyper_reset_no ), ); //////////////////////// @@ -118,6 +153,13 @@ module fixture_chimera_soc #( vip_chimera_soc #( .DutCfg (DutCfg), + // Determine whether we preload the hyperram model or not User preload. If 0, the memory model + // is not preloaded at time 0. + .HypUserPreload ( `HYP_USER_PRELOAD ), + // Mem files for hyperram model. The argument is considered only if HypUserPreload==1 in the + // memory model. + .Hyp0UserPreloadMemFile ( `HYP0_PRELOAD_MEM_FILE ), + .Hyp1UserPreloadMemFile ( `HYP1_PRELOAD_MEM_FILE ), .axi_ext_mst_req_t(axi_mst_req_t), .axi_ext_mst_rsp_t(axi_mst_rsp_t) ) vip ( diff --git a/target/sim/src/tb_chimera_pkg.sv b/target/sim/src/tb_chimera_pkg.sv index fc5e432..2c5a09f 100644 --- a/target/sim/src/tb_chimera_pkg.sv +++ b/target/sim/src/tb_chimera_pkg.sv @@ -42,4 +42,12 @@ package tb_chimera_pkg; DefaultCfg // 0: Default configuration }; + // HyperBus + localparam int HypNumPhys = 2; + localparam int HypNumChips = 2; + + //TODO(smazzola): define correct parameters after HyperBus integration + // localparam int unsigned HyperbusTburstMax = 32'h20009008; + // parameter int unsigned HyperRstCycles = 120100; + endpackage diff --git a/target/sim/src/tb_chimera_soc.sv b/target/sim/src/tb_chimera_soc.sv index c35548a..38d4005 100644 --- a/target/sim/src/tb_chimera_soc.sv +++ b/target/sim/src/tb_chimera_soc.sv @@ -17,6 +17,8 @@ module tb_chimera_soc #( logic [ 1:0] boot_mode; logic [ 1:0] preload_mode; bit [31:0] exit_code; + //TODO(smazzola): is this needed? + // bit is_dram; initial begin // Fetch plusargs or use safe (fail-fast) defaults @@ -33,11 +35,24 @@ module tb_chimera_soc #( // Wait for reset fix.vip.wait_for_reset(); + //TODO(smazzola): is this needed? + // Writing max burst length in Hyperbus configuration registers to + // prevent the Verification IPs from triggering timing checks. + // $display("[TB] INFO: Configuring Hyperbus through serial link."); + // fix.vip.jtag_write_reg32(HyperbusTburstMax, 32'd128, 1'b1); + // Preload in idle mode or wait for completion in autonomous boot if (boot_mode == 0) begin // Idle boot: preload with the specified mode case (preload_mode) 0: begin // JTAG + //TODO(smazzola): is this needed? + // is_dram = uvm_re_match("dram", preload_elf); + // if(~is_dram) begin + // $display("[TB] %t - Wait for HyperRAM", $realtime); + // repeat(HyperRstCycles) + // @(posedge fix.clk); + // end fix.vip.jtag_init(); fix.vip.jtag_elf_run(preload_elf); fix.vip.jtag_wait_for_eoc(exit_code); diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv index 5f70920..000c747 100644 --- a/target/sim/src/vip_chimera_soc.sv +++ b/target/sim/src/vip_chimera_soc.sv @@ -14,10 +14,12 @@ module vip_chimera_soc #( // DUT (must be set) parameter cheshire_cfg_t DutCfg = '0, - // Timing - parameter type axi_ext_mst_req_t = logic, - parameter type axi_ext_mst_rsp_t = logic, + parameter int unsigned HypNumPhys = 2, + parameter int unsigned HypNumChips = 2, + parameter type axi_ext_mst_req_t = logic, + parameter type axi_ext_mst_rsp_t = logic, + // Timing parameter time ClkPeriodClu = 2ns, parameter time ClkPeriodSys = 5ns, parameter time ClkPeriodJtag = 20ns, @@ -38,6 +40,10 @@ module vip_chimera_soc parameter int unsigned SlinkMaxTxns = 32, parameter int unsigned SlinkMaxTxnsPerId = 16, parameter bit SlinkAxiDebug = 0, + // HyperRAM (hardcoded to HypNumPhys = 2) + parameter int unsigned HypUserPreload = 0, + parameter string Hyp0UserPreloadMemFile = "", + parameter string Hyp1UserPreloadMemFile = "", // Derived Parameters; *do not override* parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth / 8, parameter int unsigned AxiStrbBits = $clog2(DutCfg.AxiDataWidth / 8) @@ -63,7 +69,14 @@ module vip_chimera_soc // SPI host interface inout wire spih_sck, inout wire [SpihNumCs-1:0] spih_csb, - inout wire [ 3:0] spih_sd + inout wire [ 3:0] spih_sd, + // Hyperbus interface + wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn, + wire [HypNumPhys-1:0] pad_hyper_ck, + wire [HypNumPhys-1:0] pad_hyper_ckn, + wire [HypNumPhys-1:0] pad_hyper_rwds, + wire [HypNumPhys-1:0] pad_hyper_resetn, + wire [HypNumPhys-1:0][7:0] pad_hyper_dq ); `include "cheshire/typedef.svh" @@ -554,13 +567,60 @@ module vip_chimera_soc if (image != "") $readmemh(image, i_spi_norflash.Mem); endtask + ////////////// + // Hyperbus // + ////////////// + + localparam string HypUserPreloadMemFiles [HypNumPhys] = '{Hyp0UserPreloadMemFile, Hyp1UserPreloadMemFile}; + + for (genvar i=0; i