From 5f5a5a5c9d4e7953a3b6b65bbe8cc47ee9221733 Mon Sep 17 00:00:00 2001 From: Lorenzo Leone Date: Tue, 5 Nov 2024 14:47:12 +0100 Subject: [PATCH] [TB]: Extend testbench to improve debugging --- target/sim/src/vip_chimera_soc.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv index d08d4ca..306f24f 100644 --- a/target/sim/src/vip_chimera_soc.sv +++ b/target/sim/src/vip_chimera_soc.sv @@ -22,7 +22,7 @@ module vip_chimera_soc // Timing parameter time ClkPeriodClu = 2ns, parameter time ClkPeriodSys = 5ns, - parameter time ClkPeriodJtag = 20ns, + parameter time ClkPeriodJtag = 100ns, parameter time ClkPeriodRtc = 30518ns, parameter int unsigned RstCycles = 5, parameter real TAppl = 0.1, @@ -329,7 +329,7 @@ module vip_chimera_soc // Wait for termination signal and get return code task automatic jtag_wait_for_eoc(output word_bt exit_code); - jtag_poll_bit0(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_2_OFFSET, exit_code, 800); + jtag_poll_bit0(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_2_OFFSET, exit_code, 8000); exit_code >>= 1; if (exit_code) $error("[JTAG] FAILED: return code %0d", exit_code); else $display("[JTAG] SUCCESS"); @@ -426,6 +426,7 @@ module vip_chimera_soc uart_boot_eoc = 1; end else begin uart_read_buf.push_back(bite); + $display("Read Byte: %s", bite); end end end