From 829ac71dea6928bd1ab9bdc16067d14895c6bb87 Mon Sep 17 00:00:00 2001 From: Lorenzo Leone Date: Mon, 23 Sep 2024 19:34:40 +0200 Subject: [PATCH] Integrate Memory Island into chimera Hw: - Add memory island domain wrapper - chimera_cfg_t struct & typedef for AXI signals - New Memory island address mappin Sw: Add support to build chehsire bootrom for mem island integration --- Bender.lock | 3 +- Bender.yml | 8 +- README.md | 16 ++- chimera.mk | 12 +- hw/chimera_clu_domain.sv | 96 +++++++-------- hw/chimera_cluster.sv | 55 +++++---- hw/chimera_memisland_domain.sv | 83 +++++++++++++ hw/chimera_pkg.sv | 70 ++++++++--- hw/chimera_top_wrapper.sv | 167 +++++++++++++++----------- hw/include/chimera/typedef.svh | 31 +++++ sw/link/common.ldh | 55 +++++++++ sw/link/memisl.ld | 46 +++++++ sw/sw.mk | 29 ++++- target/sim/src/fixture_chimera_soc.sv | 10 +- target/sim/src/tb_chimera_pkg.sv | 30 ++--- 15 files changed, 521 insertions(+), 190 deletions(-) create mode 100644 hw/chimera_memisland_domain.sv create mode 100644 hw/include/chimera/typedef.svh create mode 100644 sw/link/common.ldh create mode 100644 sw/link/memisl.ld diff --git a/Bender.lock b/Bender.lock index 3f38e4b..0178d60 100644 --- a/Bender.lock +++ b/Bender.lock @@ -69,7 +69,7 @@ packages: - common_cells - register_interface cheshire: - revision: f28e91b4d2172c3c98ec8672a9c9225c0b45363c + revision: f9b9a1066143b8319c427bd790ab4729321b9f20 version: null source: Git: https://github.com/pulp-platform/cheshire.git @@ -87,7 +87,6 @@ packages: - cva6 - idma - irq_router - - memory_island - opentitan_peripherals - register_interface - riscv-dbg diff --git a/Bender.yml b/Bender.yml index bab8f8f..3f15ea3 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,16 +6,21 @@ package: name: chimera authors: - "Moritz Scherer " + - "Lorenzo Leone " dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } - cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: f28e91b4d2172c3c98ec8672a9c9225c0b45363c} + cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: f9b9a1066143b8319c427bd790ab4729321b9f20} snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225} common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} + memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } +export_include_dirs: + - hw/include + workspace: package_links: cheshire: cheshire @@ -30,6 +35,7 @@ sources: - hw/chimera_cluster_adapter.sv - hw/chimera_cluster.sv - hw/chimera_clu_domain.sv + - hw/chimera_memisland_domain.sv - hw/chimera_top_wrapper.sv - target: any(simulation, test) diff --git a/README.md b/README.md index dc63d23..4526f4d 100644 --- a/README.md +++ b/README.md @@ -35,16 +35,22 @@ bender checkout make chs-hw-init make snitch-hw-init -make chs-sim-all ``` -To build files for modelsim: +To regenerate software tests and libraries: -`make chim-sim` +`make chim-sw` +This step must be executed before building the hardware to ensure the correct generation of the bootrom. -To regenerate software tests: +To build the host device bootrom: +`make chim-bootrom-init` + +To build Chehsire simulation files for ModelSim: +`make chs-sim-all` + +To build Chimera simulation files for ModelSim: +`make chim-sim` -`make chim-sw` ## Making Register modifications diff --git a/chimera.mk b/chimera.mk index e7ca428..417e2c1 100644 --- a/chimera.mk +++ b/chimera.mk @@ -4,6 +4,7 @@ # # Moritz Scherer + CLINTCORES = 46 PLICCORES = 92 PLIC_NUM_INTRS = 92 @@ -17,9 +18,11 @@ update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson gen_idma_hw: make -C $(IDMA_ROOT) idma_hw_all +CHS_SW_LD_DIR = $(CHIM_ROOT)/sw/link + .PHONY: chs-hw-init -chs-hw-init: update_plic gen_idma_hw - make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) +chs-hw-init: update_plic gen_idma_hw $(CHIM_SW_LIB) + make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_SW_LD_DIR=$(CHS_SW_LD_DIR) .PHONY: snitch-hw-init snitch-hw-init: @@ -73,8 +76,11 @@ chim-nonfree-init: -include $(CHIM_ROOT)/bender.mk -# Include subdir Makefiles +# Necessary to build libchimera.a for bootrom.elf +# TODO: Here the make chim-sw cannot work properly FIND SOLUTION !!!!! -include $(CHIM_ROOT)/sw/sw.mk + +# Include subdir Makefiles -include $(CHIM_ROOT)/utils/utils.mk # Include target makefiles -include $(CHIM_ROOT)/target/sim/sim.mk diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index e80ff20..83943e3 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -15,62 +15,62 @@ module chimera_clu_domain import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, - parameter type narrow_in_req_t = logic, - parameter type narrow_in_resp_t = logic, - parameter type narrow_out_req_t = logic, - parameter type narrow_out_resp_t = logic, - parameter type wide_out_req_t = logic, - parameter type wide_out_resp_t = logic + parameter chimera_cfg_t Cfg = '0, + parameter type narrow_in_req_t = logic, + parameter type narrow_in_resp_t = logic, + parameter type narrow_out_req_t = logic, + parameter type narrow_out_resp_t = logic, + parameter type wide_out_req_t = logic, + parameter type wide_out_resp_t = logic ) ( - input logic soc_clk_i, - input logic [ ExtClusters-1:0] clu_clk_i, - input logic [ ExtClusters-1:0] rst_sync_ni, - input logic [ ExtClusters-1:0] widemem_bypass_i, + input logic soc_clk_i, + input logic [ ExtClusters-1:0] clu_clk_i, + input logic [ ExtClusters-1:0] rst_sync_ni, + input logic [ ExtClusters-1:0] widemem_bypass_i, //----------------------------- // Interrupt ports //----------------------------- - input logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_i, - input logic [ iomsb(Cfg.NumExtIrqHarts):0] mtip_i, - input logic [ iomsb(Cfg.NumExtIrqHarts):0] msip_i, - input logic [ iomsb(Cfg.NumExtDbgHarts):0] debug_req_i, + input logic [iomsb(NumIrqCtxts*Cfg.ChsCfg.NumExtIrqHarts):0] xeip_i, + input logic [ iomsb(Cfg.ChsCfg.NumExtIrqHarts):0] mtip_i, + input logic [ iomsb(Cfg.ChsCfg.NumExtIrqHarts):0] msip_i, + input logic [ iomsb(Cfg.ChsCfg.NumExtDbgHarts):0] debug_req_i, //----------------------------- // Narrow AXI ports //----------------------------- - input narrow_in_req_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_req_i, - output narrow_in_resp_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_resp_o, - output narrow_out_req_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_req_o, - input narrow_out_resp_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_resp_i, + input narrow_in_req_t [ ExtClusters-1:0] narrow_in_req_i, + output narrow_in_resp_t [ ExtClusters-1:0] narrow_in_resp_o, + output narrow_out_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_req_o, + input narrow_out_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_resp_i, //----------------------------- // Wide AXI ports //----------------------------- - output wide_out_req_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_req_o, - input wide_out_resp_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_resp_i, + output wide_out_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_req_o, + input wide_out_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_resp_i, //----------------------------- // Isolation control ports //----------------------------- - input logic [ ExtClusters-1:0] isolate_i, - output logic [ ExtClusters-1:0] isolate_o + input logic [ ExtClusters-1:0] isolate_i, + output logic [ ExtClusters-1:0] isolate_o ); // Axi parameters - localparam int unsigned AxiWideDataWidth = Cfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; + localparam int unsigned AxiWideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; localparam int unsigned AxiWideSlvIdWidth = Cfg.MemIslAxiMstIdWidth + $clog2(Cfg.MemIslWidePorts); - localparam int unsigned AxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2( + localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2( cheshire_pkg::gen_axi_in(Cfg).num_in ); // Isolated AXI signals - narrow_in_req_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_isolated_req; - narrow_in_resp_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_isolated_resp; - narrow_out_req_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_isolated_req; - narrow_out_resp_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_isolated_resp; - wide_out_req_t [iomsb(Cfg.AxiExtNumWideMst):0] wide_out_isolated_req; - wide_out_resp_t [iomsb(Cfg.AxiExtNumWideMst):0] wide_out_isolated_resp; + narrow_in_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] narrow_in_isolated_req; + narrow_in_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] narrow_in_isolated_resp; + narrow_out_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_isolated_req; + narrow_out_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_isolated_resp; + wide_out_req_t [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_isolated_req; + wide_out_resp_t [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_isolated_resp; - logic [ iomsb(Cfg.AxiExtNumSlv):0] isolated_narrow_in; - logic [ iomsb(Cfg.AxiExtNumMst):0] isolated_narrow_out; - logic [iomsb(Cfg.AxiExtNumWideMst):0] isolated_wide_out; + logic [ iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] isolated_narrow_in; + logic [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] isolated_narrow_out; + logic [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] isolated_wide_out; @@ -79,13 +79,13 @@ module chimera_clu_domain if (IsolateClusters == 1) begin : gen_cluster_iso // Add AXI isolation at the Narrow Input Interface axi_isolate #( - .NumPending (Cfg.AxiMaxSlvTrans), + .NumPending (Cfg.ChsCfg.AxiMaxSlvTrans), .TerminateTransaction(0), .AtopSupport (1), - .AxiAddrWidth (Cfg.AddrWidth), - .AxiDataWidth (Cfg.AxiDataWidth), + .AxiAddrWidth (Cfg.ChsCfg.AddrWidth), + .AxiDataWidth (Cfg.ChsCfg.AxiDataWidth), .AxiIdWidth (AxiSlvIdWidth), - .AxiUserWidth (Cfg.AxiUserWidth), + .AxiUserWidth (Cfg.ChsCfg.AxiUserWidth), .axi_req_t (narrow_in_req_t), .axi_resp_t (narrow_in_resp_t) ) i_iso_narrow_in_cluster ( @@ -107,13 +107,13 @@ module chimera_clu_domain narrowOutIdx++ ) begin : gen_iso_narrow_out axi_isolate #( - .NumPending (Cfg.AxiMaxSlvTrans), + .NumPending (Cfg.ChsCfg.AxiMaxSlvTrans), .TerminateTransaction(0), .AtopSupport (1), - .AxiAddrWidth (Cfg.AddrWidth), - .AxiDataWidth (Cfg.AxiDataWidth), - .AxiIdWidth (Cfg.AxiMstIdWidth), - .AxiUserWidth (Cfg.AxiUserWidth), + .AxiAddrWidth (Cfg.ChsCfg.AddrWidth), + .AxiDataWidth (Cfg.ChsCfg.AxiDataWidth), + .AxiIdWidth (Cfg.ChsCfg.AxiMstIdWidth), + .AxiUserWidth (Cfg.ChsCfg.AxiUserWidth), .axi_req_t (narrow_out_req_t), .axi_resp_t (narrow_out_resp_t) ) i_iso_narrow_out_cluster ( @@ -130,13 +130,13 @@ module chimera_clu_domain // Add AXI isolation at the Wide Interface axi_isolate #( - .NumPending (Cfg.AxiMaxSlvTrans), + .NumPending (Cfg.ChsCfg.AxiMaxSlvTrans), .TerminateTransaction(0), .AtopSupport (1), - .AxiAddrWidth (Cfg.AddrWidth), + .AxiAddrWidth (Cfg.ChsCfg.AddrWidth), .AxiDataWidth (AxiWideDataWidth), - .AxiIdWidth (Cfg.MemIslAxiMstIdWidth), // To Check - .AxiUserWidth (Cfg.AxiUserWidth), + .AxiIdWidth (Cfg.MemIslAxiMstIdWidth), // To Check + .AxiUserWidth (Cfg.ChsCfg.AxiUserWidth), .axi_req_t (wide_out_req_t), .axi_resp_t (wide_out_resp_t) ) i_iso_wide_cluster ( @@ -191,7 +191,7 @@ module chimera_clu_domain .mtip_i (mtip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), .msip_i (msip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), .hart_base_id_i (10'(`PREVNRCORES(extClusterIdx) + 1)), - .cluster_base_addr_i(Cfg.AxiExtRegionStart[extClusterIdx][Cfg.AddrWidth-1:0]), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[extClusterIdx][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), .narrow_in_req_i (narrow_in_isolated_req[extClusterIdx]), diff --git a/hw/chimera_cluster.sv b/hw/chimera_cluster.sv index 25283a4..ba45bc2 100644 --- a/hw/chimera_cluster.sv +++ b/hw/chimera_cluster.sv @@ -9,7 +9,7 @@ module chimera_cluster import chimera_pkg::*; import cheshire_pkg::*; #( - parameter cheshire_cfg_t Cfg = '0, + parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 9, parameter type narrow_in_req_t = logic, @@ -19,36 +19,35 @@ module chimera_cluster parameter type wide_out_req_t = logic, parameter type wide_out_resp_t = logic ) ( - - input logic soc_clk_i, - input logic clu_clk_i, - input logic rst_ni, - input logic widemem_bypass_i, + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, //----------------------------- // Interrupt ports //----------------------------- - input logic [ NrCores-1:0] debug_req_i, - input logic [ NrCores-1:0] meip_i, - input logic [ NrCores-1:0] mtip_i, - input logic [ NrCores-1:0] msip_i, + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, //----------------------------- // Cluster base addressing //----------------------------- - input logic [ 9:0] hart_base_id_i, - input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i, - input logic [ 31:0] boot_addr_i, + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports //----------------------------- - input narrow_in_req_t narrow_in_req_i, - output narrow_in_resp_t narrow_in_resp_o, - output narrow_out_req_t [ 1:0] narrow_out_req_o, - input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, //----------------------------- //Wide AXI ports //----------------------------- - output wide_out_req_t wide_out_req_o, - input wide_out_resp_t wide_out_resp_i + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i ); `include "axi/typedef.svh" @@ -56,16 +55,16 @@ module chimera_cluster localparam int WideDataWidth = $bits(wide_out_req_o.w.data); localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); - localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1; + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - typedef logic [Cfg.AddrWidth-1:0] axi_addr_t; - typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; - typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; - typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; @@ -119,7 +118,7 @@ module chimera_cluster axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; - if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter narrow_adapter #( .narrow_in_req_t (axi_soc_out_narrow_req_t), @@ -221,13 +220,13 @@ module chimera_cluster localparam int unsigned NumIntOutstandingMem[NrCores] = '{NrCores{32'h4}}; snitch_cluster #( - .PhysicalAddrWidth(Cfg.AddrWidth), + .PhysicalAddrWidth(Cfg.ChsCfg.AddrWidth), .NarrowDataWidth (ClusterDataWidth), // SCHEREMO: Convolve needs this... .WideDataWidth (WideDataWidth), .NarrowIdWidthIn (ClusterNarrowAxiMstIdWidth), .WideIdWidthIn (WideMasterIdWidth), - .NarrowUserWidth (Cfg.AxiUserWidth), - .WideUserWidth (Cfg.AxiUserWidth), + .NarrowUserWidth (Cfg.ChsCfg.AxiUserWidth), + .WideUserWidth (Cfg.ChsCfg.AxiUserWidth), .BootAddr(SnitchBootROMRegionStart), diff --git a/hw/chimera_memisland_domain.sv b/hw/chimera_memisland_domain.sv new file mode 100644 index 0000000..0f4ae38 --- /dev/null +++ b/hw/chimera_memisland_domain.sv @@ -0,0 +1,83 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Lorenzo Leone + +module chimera_memisland_domain + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + parameter int unsigned NumWideMst = '0, + parameter type axi_narrow_req_t = logic, + parameter type axi_narrow_rsp_t = logic, + parameter type axi_wide_req_t = logic, + parameter type axi_wide_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_narrow_req_t axi_narrow_req_i, + output axi_narrow_rsp_t axi_narrow_rsp_o, + input axi_wide_req_t [NumWideMst-1:0] axi_wide_req_i, + output axi_wide_rsp_t [NumWideMst-1:0] axi_wide_rsp_o +); + + // Define needed parameters + localparam axi_in_t AxiIn = gen_axi_in(Cfg.ChsCfg); // lleone: TODO: find a better solution + localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + localparam int unsigned WideSlaveIdWidth = $clog2(Cfg.MemIslWidePorts); + localparam int unsigned WideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; + + axi_narrow_req_t axi_memory_island_amo_req; + axi_narrow_rsp_t axi_memory_island_amo_rsp; + + axi_riscv_atomics_structs #( + .AxiAddrWidth(Cfg.ChsCfg.AddrWidth), + .AxiDataWidth(Cfg.ChsCfg.AxiDataWidth), + .AxiIdWidth(AxiSlvIdWidth), // lleone: TODO: solve issue wiyth declaration on top + .AxiUserWidth(Cfg.ChsCfg.AxiUserWidth), + .AxiMaxReadTxns(Cfg.ChsCfg.LlcMaxReadTxns), + .AxiMaxWriteTxns(Cfg.ChsCfg.LlcMaxWriteTxns), + .AxiUserAsId(1), + .AxiUserIdMsb(Cfg.ChsCfg.AxiUserAmoMsb), + .AxiUserIdLsb(Cfg.ChsCfg.AxiUserAmoLsb), + .RiscvWordWidth(riscv::XLEN), + .NAxiCuts(Cfg.ChsCfg.LlcAmoNumCuts), + .axi_req_t(axi_narrow_req_t), + .axi_rsp_t(axi_narrow_rsp_t) + ) i_memory_island_atomics ( + .clk_i (clk_i), + .rst_ni, + .axi_slv_req_i(axi_narrow_req_i), + .axi_slv_rsp_o(axi_narrow_rsp_o), + .axi_mst_req_o(axi_memory_island_amo_req), + .axi_mst_rsp_i(axi_memory_island_amo_rsp) + ); + + axi_memory_island_wrap #( + .AddrWidth(Cfg.ChsCfg.AddrWidth), + .NarrowDataWidth(Cfg.ChsCfg.AxiDataWidth), + .WideDataWidth(WideDataWidth), + .AxiNarrowIdWidth(AxiSlvIdWidth), // lleone: TODO: solve issue wiyth declaration on top + .AxiWideIdWidth(WideSlaveIdWidth), + .axi_narrow_req_t(axi_narrow_req_t), + .axi_narrow_rsp_t(axi_narrow_rsp_t), + .axi_wide_req_t(axi_wide_req_t), + .axi_wide_rsp_t(axi_wide_rsp_t), + .NumNarrowReq(Cfg.MemIslNarrowPorts), + .NumWideReq(Cfg.MemIslWidePorts), + .NumWideBanks(Cfg.MemIslNumWideBanks), + .NarrowExtraBF(1), + .WordsPerBank(Cfg.MemIslWordsPerBank) + ) i_memory_island ( + .clk_i (clk_i), + .rst_ni, + .axi_narrow_req_i(axi_memory_island_amo_req), + .axi_narrow_rsp_o(axi_memory_island_amo_rsp), + // SCHEREMO: TODO: Demux wide accesses to go over narrow ports iff address not in memory island range + .axi_wide_req_i (axi_wide_req_i), + .axi_wide_rsp_o (axi_wide_rsp_o) + ); + +endmodule : chimera_memisland_domain diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index 8a6a9ff..a673d4e 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -12,6 +12,13 @@ package chimera_pkg; // ACCEL CFG localparam int ExtClusters = 5; + localparam int ExtClustersBaseIdx = 0; + + // Bit vector types for parameters. + //We limit range to keep parameters sane. + typedef bit [7:0] byte_bt; + typedef bit [63:0] doub_bt; + typedef bit [15:0] shrt_bt; typedef struct packed { logic [iomsb(ExtClusters):0] hasWideMasterPort; @@ -31,6 +38,18 @@ package chimera_pkg; return sum; endfunction + // Configuration struct for Chimer: it includes the Cheshire Cfg + typedef struct packed { + cheshire_cfg_t ChsCfg; + doub_bt MemIslRegionStart; + doub_bt MemIslRegionEnd; + aw_bt MemIslAxiMstIdWidth; + byte_bt MemIslNarrowToWideFactor; + byte_bt MemIslNarrowPorts; + byte_bt MemIslWidePorts; + byte_bt MemIslNumWideBanks; + shrt_bt MemIslWordsPerBank; + } chimera_cfg_t; localparam int ExtCores = _sumVector(ChimeraClusterCfg.NrCores, ExtClusters); @@ -56,15 +75,28 @@ package chimera_pkg; localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000; localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000; + // Parameters for Memory Island + localparam int MemIslandIdx = ExtClustersBaseIdx + ExtClusters; + + localparam doub_bt MemIslRegionStart = 64'h4800_0000; + localparam doub_bt MemIslRegionEnd = 64'h4804_0000; + localparam aw_bt MemIslAxiMstIdWidth = 1; + localparam byte_bt MemIslNarrowToWideFactor = 4; + localparam byte_bt MemIslNarrowPorts = 1; + localparam byte_bt MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); + localparam byte_bt MemIslNumWideBanks = 2; + localparam shrt_bt MemIslWordsPerBank = 1024; localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; // Isolate Clusters from SoC localparam int unsigned IsolateClusters = 0; - function automatic cheshire_cfg_t gen_chimera_cfg(); + function automatic chimera_cfg_t gen_chimera_cfg(); localparam int AddrWidth = DefaultCfg.AddrWidth; + localparam int MemoryIsland = 1; + chimera_cfg_t chimera_cfg; cheshire_cfg_t cfg = DefaultCfg; // Global CFG @@ -74,32 +106,29 @@ package chimera_pkg; cfg.Vga = 0; cfg.SerialLink = 0; - cfg.MemoryIsland = 1; // SCHEREMO: Fully remove LLC cfg.LlcNotBypass = 0; cfg.LlcOutConnect = 0; // AXI CFG cfg.AxiMstIdWidth = 2; - cfg.MemIslAxiMstIdWidth = 1; cfg.AxiDataWidth = 32; cfg.AddrWidth = 32; cfg.LlcOutRegionEnd = 'hFFFF_FFFF; - cfg.MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.MemIslNarrowToWideFactor = 4; - cfg.AxiExtNumWideMst = $countones(ChimeraClusterCfg.hasWideMasterPort); + // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow cfg.AxiExtNumMst = ExtClusters + $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.AxiExtNumSlv = ExtClusters; - cfg.AxiExtNumRules = ExtClusters; - cfg.AxiExtRegionIdx = {8'h4, 8'h3, 8'h2, 8'h1, 8'h0}; + cfg.AxiExtNumSlv = ExtClusters + MemoryIsland; + cfg.AxiExtNumRules = ExtClusters + MemoryIsland; + + cfg.AxiExtRegionIdx = {8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0}; cfg.AxiExtRegionStart = { - 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000 + MemIslRegionStart, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000 }; cfg.AxiExtRegionEnd = { - 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 + MemIslRegionEnd, 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 }; // REG CFG @@ -116,16 +145,29 @@ package chimera_pkg; cfg.NumExtDbgHarts = ExtCores; cfg.NumExtOutIntrTgts = ExtCores; - return cfg; + chimera_cfg = '{ + ChsCfg : cfg, + MemIslRegionStart : MemIslRegionStart, + MemIslRegionEnd : MemIslRegionEnd, + MemIslAxiMstIdWidth : MemIslAxiMstIdWidth, + MemIslNarrowToWideFactor : MemIslNarrowToWideFactor, + MemIslNarrowPorts : MemIslNarrowPorts, + MemIslWidePorts : MemIslWidePorts, + MemIslNumWideBanks : MemIslNumWideBanks, + MemIslWordsPerBank : MemIslWordsPerBank, + default: '0 + }; + + return chimera_cfg; endfunction : gen_chimera_cfg localparam int NumCfgs = 1; - localparam cheshire_cfg_t [NumCfgs-1:0] ChimeraCfg = {gen_chimera_cfg()}; + localparam chimera_cfg_t [NumCfgs-1:0] ChimeraCfg = {gen_chimera_cfg()}; // To move into cheshire TYPEDEF localparam int unsigned RegDataWidth = 32; - localparam type addr_t = logic [ChimeraCfg[0].AddrWidth-1:0]; + localparam type addr_t = logic [ChimeraCfg[0].ChsCfg.AddrWidth-1:0]; localparam type data_t = logic [RegDataWidth-1:0]; localparam type strb_t = logic [RegDataWidth/8-1:0]; diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index cb66857..3e237e0 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -67,10 +67,14 @@ module chimera_top_wrapper `include "common_cells/registers.svh" `include "common_cells/assertions.svh" `include "cheshire/typedef.svh" + `include "chimera/typedef.svh" // Cheshire config - localparam cheshire_cfg_t Cfg = ChimeraCfg[SelectedCfg]; - `CHESHIRE_TYPEDEF_ALL(, Cfg) + localparam chimera_cfg_t Cfg = ChimeraCfg[SelectedCfg]; + localparam cheshire_cfg_t ChsCfg = Cfg.ChsCfg; + + `CHESHIRE_TYPEDEF_ALL(, ChsCfg) + `CHIMERA_TYPEDEF_ALL(, Cfg) localparam type axi_wide_mst_req_t = mem_isl_wide_axi_mst_req_t; localparam type axi_wide_mst_rsp_t = mem_isl_wide_axi_mst_rsp_t; @@ -80,74 +84,80 @@ module chimera_top_wrapper chimera_reg2hw_t reg2hw; // External AXI crossbar ports - axi_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_mst_req; - axi_mst_rsp_t [iomsb(Cfg.AxiExtNumMst):0] axi_mst_rsp; - axi_wide_mst_req_t [iomsb(Cfg.AxiExtNumWideMst):0] axi_wide_mst_req; - axi_wide_mst_rsp_t [iomsb(Cfg.AxiExtNumWideMst):0] axi_wide_mst_rsp; - axi_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_slv_req; - axi_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_slv_rsp; + axi_mst_req_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_req; + axi_mst_rsp_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_rsp; + axi_wide_mst_req_t [iomsb(ChsCfg.AxiExtNumWideMst):0] axi_wide_mst_req; + axi_wide_mst_rsp_t [iomsb(ChsCfg.AxiExtNumWideMst):0] axi_wide_mst_rsp; + axi_slv_req_t [iomsb(ChsCfg.AxiExtNumSlv):0] axi_slv_req; + axi_slv_rsp_t [iomsb(ChsCfg.AxiExtNumSlv):0] axi_slv_rsp; // External reg demux slaves - reg_req_t [iomsb(Cfg.RegExtNumSlv):0] reg_slv_req; - reg_rsp_t [iomsb(Cfg.RegExtNumSlv):0] reg_slv_rsp; + reg_req_t [iomsb(ChsCfg.RegExtNumSlv):0] reg_slv_req; + reg_rsp_t [iomsb(ChsCfg.RegExtNumSlv):0] reg_slv_rsp; // Interrupts from and to clusters - logic [iomsb(Cfg.NumExtInIntrs):0] intr_ext_in; - logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_out; + logic [iomsb(ChsCfg.NumExtInIntrs):0] intr_ext_in; + logic [iomsb(ChsCfg.NumExtOutIntrTgts):0][iomsb(ChsCfg.NumExtOutIntrs):0] intr_ext_out; // Interrupt requests to cluster cores - logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext; - logic [iomsb(Cfg.NumExtIrqHarts):0] mtip_ext; - logic [iomsb(Cfg.NumExtIrqHarts):0] msip_ext; + logic [iomsb(NumIrqCtxts*ChsCfg.NumExtIrqHarts):0] xeip_ext; + logic [iomsb(ChsCfg.NumExtIrqHarts):0] mtip_ext; + logic [iomsb(ChsCfg.NumExtIrqHarts):0] msip_ext; // Debug interface to cluster cores logic dbg_active; - logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req; - logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail; + logic [iomsb(ChsCfg.NumExtDbgHarts):0] dbg_ext_req; + logic [iomsb(ChsCfg.NumExtDbgHarts):0] dbg_ext_unavail; + + // --------------------------------------- + // | Cheshire SoC | + // --------------------------------------- cheshire_soc #( - .Cfg (Cfg), - .ExtHartinfo ('0), - .axi_ext_llc_req_t (axi_mst_req_t), - .axi_ext_llc_rsp_t (axi_mst_rsp_t), - .axi_ext_mst_req_t (axi_mst_req_t), - .axi_ext_mst_rsp_t (axi_mst_rsp_t), - .axi_ext_wide_mst_req_t(axi_wide_mst_req_t), - .axi_ext_wide_mst_rsp_t(axi_wide_mst_rsp_t), - .axi_ext_slv_req_t (axi_slv_req_t), - .axi_ext_slv_rsp_t (axi_slv_rsp_t), - .reg_ext_req_t (reg_req_t), - .reg_ext_rsp_t (reg_rsp_t) + .Cfg (ChsCfg), + .ExtHartinfo ('0), + .axi_ext_llc_req_t(axi_mst_req_t), + .axi_ext_llc_rsp_t(axi_mst_rsp_t), + .axi_ext_mst_req_t(axi_mst_req_t), + .axi_ext_mst_rsp_t(axi_mst_rsp_t), + // lleone: TODO: remove from here + // .axi_ext_wide_mst_req_t(axi_wide_mst_req_t), + // .axi_ext_wide_mst_rsp_t(axi_wide_mst_rsp_t), + .axi_ext_slv_req_t(axi_slv_req_t), + .axi_ext_slv_rsp_t(axi_slv_rsp_t), + .reg_ext_req_t (reg_req_t), + .reg_ext_rsp_t (reg_rsp_t) ) i_cheshire ( - .clk_i (soc_clk_i), + .clk_i (soc_clk_i), .rst_ni, .test_mode_i, .boot_mode_i, .rtc_i, // External AXI LLC (DRAM) port - .axi_llc_mst_req_o (), - .axi_llc_mst_rsp_i ('0), + .axi_llc_mst_req_o(), + .axi_llc_mst_rsp_i('0), // External AXI crossbar ports - .axi_ext_mst_req_i (axi_mst_req), - .axi_ext_mst_rsp_o (axi_mst_rsp), - .axi_ext_wide_mst_req_i(axi_wide_mst_req), - .axi_ext_wide_mst_rsp_o(axi_wide_mst_rsp), - .axi_ext_slv_req_o (axi_slv_req), - .axi_ext_slv_rsp_i (axi_slv_rsp), + .axi_ext_mst_req_i(axi_mst_req), + .axi_ext_mst_rsp_o(axi_mst_rsp), + // lleone: TOOD: delet wide ports + // .axi_ext_wide_mst_req_i(axi_wide_mst_req), + // .axi_ext_wide_mst_rsp_o(axi_wide_mst_rsp), + .axi_ext_slv_req_o(axi_slv_req), + .axi_ext_slv_rsp_i(axi_slv_rsp), // External reg demux slaves - .reg_ext_slv_req_o (reg_slv_req), - .reg_ext_slv_rsp_i (reg_slv_rsp), + .reg_ext_slv_req_o(reg_slv_req), + .reg_ext_slv_rsp_i(reg_slv_rsp), // Interrupts from and to external targets - .intr_ext_i (intr_ext_in), - .intr_ext_o (intr_ext_out), + .intr_ext_i (intr_ext_in), + .intr_ext_o (intr_ext_out), // Interrupt requests to external harts - .xeip_ext_o (xeip_ext), - .mtip_ext_o (mtip_ext), - .msip_ext_o (msip_ext), + .xeip_ext_o (xeip_ext), + .mtip_ext_o (mtip_ext), + .msip_ext_o (msip_ext), // Debug interface to external harts - .dbg_active_o (dbg_active), - .dbg_ext_req_o (dbg_ext_req), - .dbg_ext_unavail_i (dbg_ext_unavail), + .dbg_active_o (dbg_active), + .dbg_ext_req_o (dbg_ext_req), + .dbg_ext_unavail_i(dbg_ext_unavail), // JTAG interface .jtag_tck_i, .jtag_trst_ni, @@ -185,24 +195,24 @@ module chimera_top_wrapper .gpio_o, .gpio_en_o, // Serial link interface - .slink_rcv_clk_i ('0), - .slink_rcv_clk_o (), - .slink_i ('0), - .slink_o (), + .slink_rcv_clk_i ('0), + .slink_rcv_clk_o (), + .slink_i ('0), + .slink_o (), // VGA interface - .vga_hsync_o (), - .vga_vsync_o (), - .vga_red_o (), - .vga_green_o (), - .vga_blue_o (), - .usb_clk_i ('0), - .usb_rst_ni ('1), - .usb_dm_i ('0), - .usb_dm_o (), - .usb_dm_oe_o (), - .usb_dp_i ('0), - .usb_dp_o (), - .usb_dp_oe_o () + .vga_hsync_o (), + .vga_vsync_o (), + .vga_red_o (), + .vga_green_o (), + .vga_blue_o (), + .usb_clk_i ('0), + .usb_rst_ni ('1), + .usb_dm_i ('0), + .usb_dm_o (), + .usb_dm_oe_o (), + .usb_dp_i ('0), + .usb_dp_o (), + .usb_dp_oe_o () ); @@ -310,6 +320,9 @@ module chimera_top_wrapper ); end + // --------------------------------------- + // | Clusters Domain | + // --------------------------------------- chimera_clu_domain #( .Cfg (Cfg), .narrow_in_req_t (axi_slv_req_t), @@ -327,8 +340,8 @@ module chimera_top_wrapper .xeip_i (xeip_ext), .mtip_i (mtip_ext), .msip_i (msip_ext), - .narrow_in_req_i (axi_slv_req), - .narrow_in_resp_o (axi_slv_rsp), + .narrow_in_req_i (axi_slv_req[ExtClustersBaseIdx+:ExtClusters]), + .narrow_in_resp_o (axi_slv_rsp[ExtClustersBaseIdx+:ExtClusters]), .narrow_out_req_o (axi_mst_req), .narrow_out_resp_i(axi_mst_rsp), .wide_out_req_o (axi_wide_mst_req), @@ -337,4 +350,24 @@ module chimera_top_wrapper .isolate_o (pmu_iso_ack_clusters_o) ); + // --------------------------------------- + // | Memory Island | + // --------------------------------------- + + chimera_memisland_domain #( + .Cfg (Cfg), + .NumWideMst (Cfg.ChsCfg.AxiExtNumWideMst), + .axi_narrow_req_t(axi_slv_req_t), + .axi_narrow_rsp_t(axi_slv_rsp_t), + .axi_wide_req_t (axi_wide_mst_req_t), + .axi_wide_rsp_t (axi_wide_mst_rsp_t) + ) i_memisland_domain ( + .clk_i (soc_clk_i), + .rst_ni, + .axi_narrow_req_i(axi_slv_req[MemIslandIdx]), + .axi_narrow_rsp_o(axi_slv_rsp[MemIslandIdx]), + .axi_wide_req_i (axi_wide_mst_req), + .axi_wide_rsp_o (axi_wide_mst_rsp) + ); + endmodule diff --git a/hw/include/chimera/typedef.svh b/hw/include/chimera/typedef.svh new file mode 100644 index 0000000..f725322 --- /dev/null +++ b/hw/include/chimera/typedef.svh @@ -0,0 +1,31 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +`ifndef CHIMERA_TYPEDEF_SVH_ +`define CHIMERA_TYPEDEF_SVH_ + +`include "axi/typedef.svh" +`include "register_interface/typedef.svh" +`include "cheshire/typedef.svh" + +`define CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(__prefix, __cfg) \ + localparam type __prefix``addr_t = logic [__cfg.ChsCfg.AddrWidth-1:0]; \ + localparam int wideDataWidth = __cfg.ChsCfg.AxiDataWidth*__cfg.MemIslNarrowToWideFactor; \ + localparam type __prefix``_axi_data_t = logic [wideDataWidth -1:0]; \ + localparam type __prefix``_axi_strb_t = logic [wideDataWidth/8 -1:0]; \ + localparam type __prefix``_axi_user_t = logic [__cfg.ChsCfg.AxiUserWidth -1:0]; \ + localparam type __prefix``_axi_mst_id_t = logic [__cfg.MemIslAxiMstIdWidth-1:0]; \ + localparam type __prefix``_axi_slv_id_t = logic [__cfg.MemIslAxiMstIdWidth + $clog2(__cfg.MemIslWidePorts)-1:0]; \ + `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_mst, __prefix``addr_t, \ + __prefix``_axi_mst_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ + `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_slv, __prefix``addr_t, \ + __prefix``_axi_slv_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ + +// Note that the prefix does *not* include a leading underscore. +`define CHIMERA_TYPEDEF_ALL(__prefix, __cfg) \ + `CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(mem_isl_wide, __cfg) + +`endif diff --git a/sw/link/common.ldh b/sw/link/common.ldh new file mode 100644 index 0000000..f2b3fae --- /dev/null +++ b/sw/link/common.ldh @@ -0,0 +1,55 @@ +/* Copyright 2022 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* Nicole Narr */ +/* Christopher Reinwardt */ +/* Paul Scheffler */ + +/* This header defines symbols and rules universal to bare-metal execution */ + +ENTRY(_start) + +MEMORY { + bootrom (rx) : ORIGIN = 0x02000000, LENGTH = 16K + /* We assume at least 64 KiB SPM, same minus stack for ROMs. */ + /* If more SPM is available, CRT0 repoints the stack. */ + extrom (rx) : ORIGIN = 0x00000000, LENGTH = 48K + spm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + memisl (rwx) : ORIGIN = 0x48000000, LENGTH = 64K + /* We assume at least 8 MiB of DRAM (minimum for Linux). */ + dram (rwx) : ORIGIN = 0x80000000, LENGTH = 8M +} + +SECTIONS { + /* Keep binaries lean */ + /DISCARD/ : { *(.riscv.attributes) *(.comment) } + + /* Global and stack pointer */ + /* By default, keep the calling context (boot ROM) stack pointer */ + __global_pointer$ = ADDR(.misc) + SIZEOF(.misc) / 2; + __stack_pointer$ = 0; + + /* Further addresses */ + __base_dma = 0x01000000; + __base_bootrom = 0x02000000; + __base_clint = 0x02040000; + __base_axirt = 0x020C0000; + __base_axirtgrd = 0x020C1ffc; + __base_regs = 0x03000000; + __base_llc = 0x03001000; + __base_uart = 0x03002000; + __base_i2c = 0x03003000; + __base_spih = 0x03004000; + __base_gpio = 0x03005000; + __base_slink = 0x03006000; + __base_vga = 0x03007000; + __base_usb = 0x03008000; + __base_bus_err = 0x03009000; + __base_plic = 0x04000000; + __base_clic = 0x08000000; + __base_spm = ORIGIN(spm); + __base_dram = ORIGIN(dram); + __base_memisl = ORIGIN(memisl); + __stack_start = ORIGIN(memisl) + LENGTH(memisl); +} diff --git a/sw/link/memisl.ld b/sw/link/memisl.ld new file mode 100644 index 0000000..6dcf16c --- /dev/null +++ b/sw/link/memisl.ld @@ -0,0 +1,46 @@ +/* Copyright 2022 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* Nicole Narr */ +/* Christopher Reinwardt */ +/* Paul Scheffler */ +/* Lorenzo Leone */ + + +INCLUDE common.ldh + +SECTIONS { + .text : { + *(.text._start) + *(.text) + *(.text.*) + } > memisl + + .misc : ALIGN(16) { + *(.rodata) + *(.rodata.*) + *(.data) + *(.data.*) + *(.srodata) + *(.srodata.*) + *(.sdata) + *(.sdata.*) + } > memisl + + . = ALIGN(32); + __bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } > memisl + . = ALIGN(32); + __bss_end = .; + + .bulk : ALIGN(16) { + *(.bulk) + *(.bulk.*) + } > memisl +} diff --git a/sw/sw.mk b/sw/sw.mk index 2979756..b15dadb 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -8,7 +8,13 @@ ifndef chim_sw_mk chim_sw_mk=1 CHS_SW_INCLUDES += -I$(CHIM_SW_DIR)/include + + +# SCHEREMO: use im for platform-level SW, as the smallest common denominator between CVA6 and the Snitch cluster. +# CVA6's bootrom however needs imc, so override that for this specific case. CHS_SW_FLAGS += -falign-functions=64 -march=rv32im +CHS_BROM_FLAGS += -march=rv32imc + CHS_SW_LDFLAGS += -L$(CHIM_SW_DIR)/lib CHIM_SW_LIB_SRCS_C = $(wildcard $(CHIM_SW_DIR)/lib/*.c $(CHIM_SW_DIR)/lib/**/*.c) @@ -27,10 +33,31 @@ CHIM_SW_TEST_SRCS_C = $(wildcard $(CHIM_SW_DIR)/tests/*.c) CHIM_SW_TEST_MEMISL_DUMP = $(CHIM_SW_TEST_SRCS_S:.S=.memisl.dump) $(CHIM_SW_TEST_SRCS_C:.c=.memisl.dump) -CHIM_SW_TESTS += $(CHIM_SW_TEST_DRAM_DUMP) $(CHIM_SW_TEST_SPM_DUMP) $(CHIM_SW_TEST_MEMISL_DUMP) $(CHIM_SW_TEST_SPM_ROMH) $(CHIM_SW_TEST_SPM_GPTH) +CHIM_SW_TESTS += $(CHIM_SW_TEST_MEMISL_DUMP) + +# All objects require up-to-date patches and headers +%.o: %.c + $(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@ + +%.o: %.S + $(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@ + +define chim_sw_ld_elf_rule +.PRECIOUS: %.$(1).elf + +%.$(1).elf: $$(CHS_SW_LD_DIR)/$(1).ld %.o $$(CHS_SW_LIBS) + $$(CHS_SW_CC) $$(CHS_SW_INCLUDES) -T$$< $$(CHS_SW_LDFLAGS) -o $$@ $$*.o $$(CHS_SW_LIBS) +endef + +$(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*.ld)),$(eval $(call chim_sw_ld_elf_rule,$(link)))) chim-sw: $(CHIM_SW_LIB) $(CHIM_SW_TESTS) +.PHONY: chim-bootrom-init +chim-bootrom-init: chs-hw-init chim-sw + make -B chs-bootrom-all CHS_XLEN=$(CHS_XLEN) CHS_SW_LD_DIR=$(CHS_SW_LD_DIR) + + chim-sw-clean: @find sw/tests | grep ".*\.elf" | xargs -I ! rm ! @find sw/tests | grep ".*\.dump" | xargs -I ! rm ! diff --git a/target/sim/src/fixture_chimera_soc.sv b/target/sim/src/fixture_chimera_soc.sv index ab4676a..e2ec0d1 100644 --- a/target/sim/src/fixture_chimera_soc.sv +++ b/target/sim/src/fixture_chimera_soc.sv @@ -13,15 +13,17 @@ module fixture_chimera_soc #( ); `include "cheshire/typedef.svh" + `include "chimera/typedef.svh" import cheshire_pkg::*; import tb_cheshire_pkg::*; import chimera_pkg::*; - localparam cheshire_cfg_t DutCfg = ChimeraCfg[SelectedCfg]; - - `CHESHIRE_TYPEDEF_ALL(, DutCfg) + localparam chimera_cfg_t DutCfg = ChimeraCfg[SelectedCfg]; + localparam cheshire_cfg_t ChsCfg = DutCfg.ChsCfg; + `CHESHIRE_TYPEDEF_ALL(, ChsCfg) + `CHIMERA_TYPEDEF_ALL(, DutCfg) /////////// // DUT // @@ -121,7 +123,7 @@ module fixture_chimera_soc #( /////////// vip_chimera_soc #( - .DutCfg (DutCfg), + .DutCfg (ChsCfg), .axi_ext_mst_req_t(axi_mst_req_t), .axi_ext_mst_rsp_t(axi_mst_rsp_t) ) vip ( diff --git a/target/sim/src/tb_chimera_pkg.sv b/target/sim/src/tb_chimera_pkg.sv index fc5e432..48068ae 100644 --- a/target/sim/src/tb_chimera_pkg.sv +++ b/target/sim/src/tb_chimera_pkg.sv @@ -7,36 +7,32 @@ /// This package contains parameters used in the simulation environment package tb_chimera_pkg; + import chimera_pkg::*; import cheshire_pkg::*; // A dedicated RT config - function automatic cheshire_cfg_t gen_cheshire_rt_cfg(); - cheshire_cfg_t ret = DefaultCfg; - ret.AxiRt = 1; + function automatic chimera_cfg_t gen_cheshire_rt_cfg(); + cheshire_cfg_t ChsCfg = DefaultCfg; + chimera_cfg_t ret; + ret.ChsCfg.AxiRt = 1; return ret; endfunction // An embedded 32 bit config - function automatic cheshire_cfg_t gen_cheshire_emb_cfg(); - cheshire_cfg_t ret = DefaultCfg; - ret.Vga = 0; - ret.SerialLink = 0; - ret.AxiUserWidth = 64; + function automatic chimera_cfg_t gen_cheshire_emb_cfg(); + cheshire_cfg_t ChsCfg = DefaultCfg; + chimera_cfg_t ret; + ret.ChsCfg.Vga = 0; + ret.ChsCfg.SerialLink = 0; + ret.ChsCfg.AxiUserWidth = 64; return ret; endfunction : gen_cheshire_emb_cfg - function automatic cheshire_cfg_t gen_cheshire_memisl_cfg(); - cheshire_cfg_t ret = gen_cheshire_emb_cfg(); - ret.MemoryIsland = 1; - return ret; - endfunction : gen_cheshire_memisl_cfg - // Number of Cheshire configurations - localparam int unsigned NumCheshireConfigs = 32'd4; + localparam int unsigned NumCheshireConfigs = 32'd3; // Assemble a configuration array indexed by a numeric parameter - localparam cheshire_cfg_t [NumCheshireConfigs-1:0] TbCheshireConfigs = { - gen_cheshire_memisl_cfg(), // 3: Embedded + Memory Island configuration + localparam chimera_cfg_t [NumCheshireConfigs-1:0] TbCheshireConfigs = { gen_cheshire_emb_cfg(), // 2: Embedded configuration gen_cheshire_rt_cfg(), // 1: RT-enabled configuration DefaultCfg // 0: Default configuration