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HW: Update cluster_domain and tb_chimera_pkg to chimera_cfg_t struct
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@Lore0599
Lore0599 committed Sep 26, 2024
1 parent e225e7a commit 8cdec1c
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Showing 4 changed files with 64 additions and 67 deletions.
44 changes: 22 additions & 22 deletions hw/chimera_clu_domain.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,37 +15,37 @@ module chimera_clu_domain
import chimera_pkg::*;
import cheshire_pkg::*;
#(
parameter cheshire_cfg_t Cfg = '0,
parameter type narrow_in_req_t = logic,
parameter type narrow_in_resp_t = logic,
parameter type narrow_out_req_t = logic,
parameter type narrow_out_resp_t = logic,
parameter type wide_out_req_t = logic,
parameter type wide_out_resp_t = logic
parameter chimera_cfg_t Cfg = '0,
parameter type narrow_in_req_t = logic,
parameter type narrow_in_resp_t = logic,
parameter type narrow_out_req_t = logic,
parameter type narrow_out_resp_t = logic,
parameter type wide_out_req_t = logic,
parameter type wide_out_resp_t = logic
) (
input logic soc_clk_i,
input logic [ ExtClusters-1:0] clu_clk_i,
input logic rst_ni,
input logic [ ExtClusters-1:0] widemem_bypass_i,
input logic soc_clk_i,
input logic [ ExtClusters-1:0] clu_clk_i,
input logic rst_ni,
input logic [ ExtClusters-1:0] widemem_bypass_i,
//-----------------------------
// Interrupt ports
//-----------------------------
input logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_i,
input logic [ iomsb(Cfg.NumExtIrqHarts):0] mtip_i,
input logic [ iomsb(Cfg.NumExtIrqHarts):0] msip_i,
input logic [ iomsb(Cfg.NumExtDbgHarts):0] debug_req_i,
input logic [iomsb(NumIrqCtxts*Cfg.ChsCfg.NumExtIrqHarts):0] xeip_i,
input logic [ iomsb(Cfg.ChsCfg.NumExtIrqHarts):0] mtip_i,
input logic [ iomsb(Cfg.ChsCfg.NumExtIrqHarts):0] msip_i,
input logic [ iomsb(Cfg.ChsCfg.NumExtDbgHarts):0] debug_req_i,
//-----------------------------
// Narrow AXI ports
//-----------------------------
input narrow_in_req_t [ ExtClusters-1:0] narrow_in_req_i,
output narrow_in_resp_t [ ExtClusters-1:0] narrow_in_resp_o,
output narrow_out_req_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_req_o,
input narrow_out_resp_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_resp_i,
input narrow_in_req_t [ ExtClusters-1:0] narrow_in_req_i,
output narrow_in_resp_t [ ExtClusters-1:0] narrow_in_resp_o,
output narrow_out_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_req_o,
input narrow_out_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_resp_i,
//-----------------------------
// Wide AXI ports
//-----------------------------
output wide_out_req_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_req_o,
input wide_out_resp_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_resp_i
output wide_out_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_req_o,
input wide_out_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_resp_i
);

for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_clusters
Expand All @@ -69,7 +69,7 @@ module chimera_clu_domain
.mtip_i (mtip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]),
.msip_i (msip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]),
.hart_base_id_i (10'(`PREVNRCORES(extClusterIdx) + 1)),
.cluster_base_addr_i(Cfg.AxiExtRegionStart[extClusterIdx][Cfg.AddrWidth-1:0]),
.cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[extClusterIdx][Cfg.ChsCfg.AddrWidth-1:0]),
.boot_addr_i (SnitchBootROMRegionStart[31:0]),

.narrow_in_req_i (narrow_in_req_i[extClusterIdx]),
Expand Down
54 changes: 27 additions & 27 deletions hw/chimera_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ module chimera_cluster
import chimera_pkg::*;
import cheshire_pkg::*;
#(
parameter cheshire_cfg_t Cfg = '0,
parameter chimera_cfg_t Cfg = '0,

parameter int unsigned NrCores = 9,
parameter type narrow_in_req_t = logic,
Expand All @@ -25,35 +25,35 @@ module chimera_cluster
parameter type wide_out_req_flat_t = logic [ $bits(wide_out_req_t)-1:0]
) (

input logic soc_clk_i,
input logic clu_clk_i,
input logic rst_ni,
input logic widemem_bypass_i,
input logic soc_clk_i,
input logic clu_clk_i,
input logic rst_ni,
input logic widemem_bypass_i,
//-----------------------------
// Interrupt ports
//-----------------------------
input logic [ NrCores-1:0] debug_req_i,
input logic [ NrCores-1:0] meip_i,
input logic [ NrCores-1:0] mtip_i,
input logic [ NrCores-1:0] msip_i,
input logic [ NrCores-1:0] debug_req_i,
input logic [ NrCores-1:0] meip_i,
input logic [ NrCores-1:0] mtip_i,
input logic [ NrCores-1:0] msip_i,
//-----------------------------
// Cluster base addressing
//-----------------------------
input logic [ 9:0] hart_base_id_i,
input logic [Cfg.AddrWidth-1:0] cluster_base_addr_i,
input logic [ 31:0] boot_addr_i,
input logic [ 9:0] hart_base_id_i,
input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i,
input logic [ 31:0] boot_addr_i,
//-----------------------------
// Narrow AXI ports
//-----------------------------
input narrow_in_req_t narrow_in_req_i,
output narrow_in_resp_flat_t narrow_in_resp_flat_o,
output narrow_out_req_flat_t [ 1:0] narrow_out_req_flat_o,
input narrow_out_resp_t [ 1:0] narrow_out_resp_i,
input narrow_in_req_t narrow_in_req_i,
output narrow_in_resp_flat_t narrow_in_resp_flat_o,
output narrow_out_req_flat_t [ 1:0] narrow_out_req_flat_o,
input narrow_out_resp_t [ 1:0] narrow_out_resp_i,
//-----------------------------
//Wide AXI ports
//-----------------------------
output wide_out_req_flat_t wide_out_req_flat_o,
input wide_out_resp_t wide_out_resp_i
output wide_out_req_flat_t wide_out_req_flat_o,
input wide_out_resp_t wide_out_resp_i
);

`include "axi/typedef.svh"
Expand Down Expand Up @@ -82,16 +82,16 @@ module chimera_cluster
localparam int WideDataWidth = $bits(wide_out_req_s.w.data);

localparam int WideMasterIdWidth = $bits(wide_out_req_s.aw.id);
localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1;
localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1;

localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id);
localparam int NarrowMasterIdWidth = $bits(narrow_out_req_s[0].aw.id);

typedef logic [Cfg.AddrWidth-1:0] axi_addr_t;
typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t;
typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t;
typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t;

typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t;
typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t;
typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t;
typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t;

typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t;
typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t;
Expand Down Expand Up @@ -145,7 +145,7 @@ module chimera_cluster
axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp;


if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter
if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter

narrow_adapter #(
.narrow_in_req_t (axi_soc_out_narrow_req_t),
Expand Down Expand Up @@ -247,13 +247,13 @@ module chimera_cluster
localparam int unsigned NumIntOutstandingMem[NrCores] = '{NrCores{32'h4}};

snitch_cluster #(
.PhysicalAddrWidth(Cfg.AddrWidth),
.PhysicalAddrWidth(Cfg.ChsCfg.AddrWidth),
.NarrowDataWidth (ClusterDataWidth), // SCHEREMO: Convolve needs this...
.WideDataWidth (WideDataWidth),
.NarrowIdWidthIn (ClusterNarrowAxiMstIdWidth),
.WideIdWidthIn (WideMasterIdWidth),
.NarrowUserWidth (Cfg.AxiUserWidth),
.WideUserWidth (Cfg.AxiUserWidth),
.NarrowUserWidth (Cfg.ChsCfg.AxiUserWidth),
.WideUserWidth (Cfg.ChsCfg.AxiUserWidth),

.BootAddr(SnitchBootROMRegionStart),

Expand Down
3 changes: 2 additions & 1 deletion hw/chimera_top_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -319,7 +319,7 @@ module chimera_top_wrapper
// | Clusters Domain |
// ---------------------------------------
chimera_clu_domain #(
.Cfg (ChsCfg),
.Cfg (Cfg),
.narrow_in_req_t (axi_slv_req_t),
.narrow_in_resp_t (axi_slv_rsp_t),
.narrow_out_req_t (axi_mst_req_t),
Expand Down Expand Up @@ -350,6 +350,7 @@ module chimera_top_wrapper

chimera_memisland_domain #(
.Cfg (Cfg),
.NumWideMst (Cfg.ChsCfg.AxiExtNumWideMst),
.axi_narrow_req_t(axi_slv_req_t),
.axi_narrow_rsp_t(axi_slv_rsp_t),
.axi_wide_req_t (axi_wide_mst_req_t),
Expand Down
30 changes: 13 additions & 17 deletions target/sim/src/tb_chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,36 +7,32 @@
/// This package contains parameters used in the simulation environment
package tb_chimera_pkg;

import chimera_pkg::*;
import cheshire_pkg::*;

// A dedicated RT config
function automatic cheshire_cfg_t gen_cheshire_rt_cfg();
cheshire_cfg_t ret = DefaultCfg;
ret.AxiRt = 1;
function automatic chimera_cfg_t gen_cheshire_rt_cfg();
cheshire_cfg_t ChsCfg = DefaultCfg;
chimera_cfg_t ret;
ret.ChsCfg.AxiRt = 1;
return ret;
endfunction

// An embedded 32 bit config
function automatic cheshire_cfg_t gen_cheshire_emb_cfg();
cheshire_cfg_t ret = DefaultCfg;
ret.Vga = 0;
ret.SerialLink = 0;
ret.AxiUserWidth = 64;
function automatic chimera_cfg_t gen_cheshire_emb_cfg();
cheshire_cfg_t ChsCfg = DefaultCfg;
chimera_cfg_t ret;
ret.ChsCfg.Vga = 0;
ret.ChsCfg.SerialLink = 0;
ret.ChsCfg.AxiUserWidth = 64;
return ret;
endfunction : gen_cheshire_emb_cfg

function automatic cheshire_cfg_t gen_cheshire_memisl_cfg();
cheshire_cfg_t ret = gen_cheshire_emb_cfg();
ret.MemoryIsland = 1;
return ret;
endfunction : gen_cheshire_memisl_cfg

// Number of Cheshire configurations
localparam int unsigned NumCheshireConfigs = 32'd4;
localparam int unsigned NumCheshireConfigs = 32'd3;

// Assemble a configuration array indexed by a numeric parameter
localparam cheshire_cfg_t [NumCheshireConfigs-1:0] TbCheshireConfigs = {
gen_cheshire_memisl_cfg(), // 3: Embedded + Memory Island configuration
localparam chimera_cfg_t [NumCheshireConfigs-1:0] TbCheshireConfigs = {
gen_cheshire_emb_cfg(), // 2: Embedded configuration
gen_cheshire_rt_cfg(), // 1: RT-enabled configuration
DefaultCfg // 0: Default configuration
Expand Down

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