From 979b6cae8849925aff258995c44ef6bb86c12217 Mon Sep 17 00:00:00 2001 From: MoritzScherer Date: Mon, 29 Jul 2024 12:22:22 +0200 Subject: [PATCH] Make the CI slightly happer (#18) * CI: Fix linting errors --- .clang-format | 7 + .github/workflows/lint.yml | 6 +- Makefile | 25 +- README.md | 16 + bender.mk | 25 +- chimera.mk | 27 +- hw/bootrom/snitch/snitch_bootrom.S | 20 +- hw/bootrom/snitch/snitch_startup.c | 111 +++--- hw/chimera_cluster_adapter.sv | 411 ++++++++++---------- hw/chimera_pkg.sv | 44 +-- hw/chimera_top_wrapper.sv | 527 +++++++++++++------------- scripts/run_clang_format.py | 394 +++++++++++++++++++ sim.mk | 25 +- sw/include/offload.h | 35 +- sw/include/regs/soc_ctrl.h | 8 +- sw/include/soc_addr_map.h | 31 +- sw/lib/offload.c | 107 +++--- sw/sw.mk | 25 +- sw/tests/testCluster.c | 78 ++-- sw/tests/testClusterGating.c | 51 +-- sw/tests/testClusterOffload.c | 73 ++-- target/sim/vsim/setup.chimera_soc.tcl | 25 +- 22 files changed, 1111 insertions(+), 960 deletions(-) create mode 100644 .clang-format create mode 100755 scripts/run_clang_format.py diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..ef85309 --- /dev/null +++ b/.clang-format @@ -0,0 +1,7 @@ +IndentWidth: 4 +ColumnLimit: 100 +AlignEscapedNewlines: DontAlign +SortIncludes: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: true +AllowShortLoopsOnASingleLine: true diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index 01d5d56..9a4eacd 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -26,7 +26,9 @@ jobs: SPDX-License-Identifier: (SHL-0.51|Apache-2.0) exclude_paths: | utils/* - # sw/include/regs/*.h + sw/include/regs/* + scripts/run_clang_format.py + lint-sv: runs-on: ubuntu-latest @@ -55,7 +57,7 @@ jobs: uses: DoozyX/clang-format-lint-action@v0.14 with: extensions: 'c,h,cpp' - clangFormatVersion: 14 + clangFormatVersion: 12 style: > { IndentWidth: 4, diff --git a/Makefile b/Makefile index 8289e2b..3c364b7 100644 --- a/Makefile +++ b/Makefile @@ -1,27 +1,8 @@ -# ---------------------------------------------------------------------- -# -# File: Makefile -# -# Created: 25.06.2024 -# -# Copyright (C) 2024, ETH Zurich and University of Bologna. -# -# Author: Moritz Scherer, ETH Zurich -# -# ---------------------------------------------------------------------- +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. +# Moritz Scherer CHIM_ROOT ?= $(shell pwd) BENDER ?= bender -d $(CHIM_ROOT) diff --git a/README.md b/README.md index b8cc2ad..f377a6e 100644 --- a/README.md +++ b/README.md @@ -68,3 +68,19 @@ source setup.chimera_soc.tcl source compile.tcl source start.chimera_soc.tcl ``` + +## CXX Formatting + +To format all files within the `sw` directory, run +``` +python scripts/run_clang_format.py -ir sw/ +``` + +Our CI uses llvm-12 for clang-format, so on IIS machines you may run +``` +python scripts/run_clang_format.py -ir sw/ --clang-format-executable=/usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang-format + +python scripts/run_clang_format.py -ir hw/ --clang-format-executable=/usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang-format +``` + +otherwise you should specify a valid clang-format-12 binary instead. diff --git a/bender.mk b/bender.mk index 4da9e5b..3a7350a 100644 --- a/bender.mk +++ b/bender.mk @@ -1,27 +1,8 @@ -# ---------------------------------------------------------------------- -# -# File: bender.mk -# -# Created: 25.06.2024 -# -# Copyright (C) 2024, ETH Zurich and University of Bologna. -# -# Author: Moritz Scherer, ETH Zurich -# -# ---------------------------------------------------------------------- +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. +# Moritz Scherer COMMON_TARGS ?= COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl diff --git a/chimera.mk b/chimera.mk index 32834d0..fce6342 100644 --- a/chimera.mk +++ b/chimera.mk @@ -1,29 +1,8 @@ -# ---------------------------------------------------------------------- -# -# File: chimera.mk -# -# Created: 26.06.2024 -# -# Copyright (C) 2024, ETH Zurich and University of Bologna. -# -# Author: Moritz Scherer, ETH Zurich -# -# ---------------------------------------------------------------------- +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# SCHEREMO: This is a test config; change to something reasonable! +# Moritz Scherer CLINTCORES = 46 PLICCORES = 92 diff --git a/hw/bootrom/snitch/snitch_bootrom.S b/hw/bootrom/snitch/snitch_bootrom.S index 52d5450..907f69e 100644 --- a/hw/bootrom/snitch/snitch_bootrom.S +++ b/hw/bootrom/snitch/snitch_bootrom.S @@ -1,9 +1,11 @@ -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer #include - + .global _start _start: @@ -13,7 +15,7 @@ _start: la t0, _trap_handler_initial csrrw x0, mtvec, t0 -_rerun: +_rerun: li x5, 0 li x6, 0 li x7, 0 @@ -41,7 +43,7 @@ _rerun: li x29, 0 li x30, 0 li x31, 0 - + wfi run_from_reg: @@ -51,10 +53,10 @@ run_from_reg: _return: call cluster_return // By calling immediately after return, register contents in a0 are passed as the first argument - -_exit: + +_exit: j _rerun - + .align 4 _trap_handler_initial: la t0, __chim_regs // CHIMERA REGS Base Addr diff --git a/hw/bootrom/snitch/snitch_startup.c b/hw/bootrom/snitch/snitch_startup.c index eab4853..27d8032 100644 --- a/hw/bootrom/snitch/snitch_startup.c +++ b/hw/bootrom/snitch/snitch_startup.c @@ -1,77 +1,64 @@ -/* ===================================================================== - * Title: snitch_startup.c - * Description: - * - * $Date: 28.06.2024 - * - * ===================================================================== */ -/* - * Copyright (C) 2020 ETH Zurich and University of Bologna. - * - * Author: Moritz Scherer, ETH Zurich - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Moritz Scherer #include #include #include -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) +#define set_csr(reg, bit) \ + ({ \ + unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; \ + }) -#define IRQ_M_SOFT 3 +#define IRQ_M_SOFT 3 -#define MSTATUS_MIE 0x00000008 -#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MSTATUS_MIE 0x00000008 +#define MIP_MSIP (1 << IRQ_M_SOFT) -void cluster_startup(){ - set_csr(mie, MIP_MSIP); - set_csr(mstatus, MSTATUS_MIE); // set M global interrupt enable - return; +void cluster_startup() { + set_csr(mie, MIP_MSIP); + set_csr(mstatus, MSTATUS_MIE); // set M global interrupt enable + return; } -void cluster_return(uint32_t ret){ +void cluster_return(uint32_t ret) { - uint32_t retVal = ret | 0x000000001; - - uint8_t hartId; - asm ("csrr %0, mhartid" : "=r" (hartId) ::); + uint32_t retVal = ret | 0x000000001; - switch(hartId){ + uint8_t hartId; + asm("csrr %0, mhartid" : "=r"(hartId)::); - case 1: - *((volatile uint32_t*)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET)) = retVal; - break; - case 10: - *((volatile uint32_t*)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET)) = retVal; - break; - case 19: - *((volatile uint32_t*)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET)) = retVal; - break; - case 28: - *((volatile uint32_t*)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET)) = retVal; - break; - case 37: - *((volatile uint32_t*)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_5_RETURN_REG_OFFSET)) = retVal; - break; - } + switch (hartId) { - return; + case 1: + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET)) = + retVal; + break; + case 10: + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET)) = + retVal; + break; + case 19: + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET)) = + retVal; + break; + case 28: + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET)) = + retVal; + break; + case 37: + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_5_RETURN_REG_OFFSET)) = + retVal; + break; + } + + return; } diff --git a/hw/chimera_cluster_adapter.sv b/hw/chimera_cluster_adapter.sv index c8d8fbd..00d6f22 100644 --- a/hw/chimera_cluster_adapter.sv +++ b/hw/chimera_cluster_adapter.sv @@ -1,33 +1,22 @@ -// ---------------------------------------------------------------------- -// -// File: chimera_cluster.sv -// -// Created: 26.06.2024 -// -// Copyright (C) 2024, ETH Zurich and University of Bologna. -// -// Author: Moritz Scherer, ETH Zurich -// +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // -// Copyright and related rights are licensed under the Solderpad Hardware License, -// Version 0.51 (the "License"); you may not use this file except in compliance with -// the License. You may obtain a copy of the License at http://solderpad.org/licenses/SHL-0.51. -// Unless required by applicable law or agreed to in writing, software, hardware and materials -// distributed under this License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and limitations under the License. -// -// ---------------------------------------------------------------------- +// Moritz Scherer -// Wraps a cluster's AXI ports with AXI CDCs on all narrow and wide ports, and converts axi id widths to match; takes care of demux wide requests to memory island / narrow crossbar +// Wraps a cluster's AXI ports with AXI CDCs on all narrow and wide ports, +// and converts axi id widths to match; takes care of demux wide requests +// to memory island / narrow crossbar module chimera_cluster_adapter #( - parameter int WideSlaveIdWidth = 0, // Needs to be defined since there is no wide slave port + // Needs to be defined since there is no wide slave port + parameter int WideSlaveIdWidth = 0, - parameter int WidePassThroughRegionStart = '0, // Start address of Memory Island - parameter int WidePassThroughRegionEnd = '0, // End address of Memory Island + // Start address of Memory Island + parameter int WidePassThroughRegionStart = '0, + // End address of Memory Island + parameter int WidePassThroughRegionEnd = '0, parameter type narrow_in_req_t = logic, parameter type narrow_in_resp_t = logic, @@ -69,17 +58,17 @@ module chimera_cluster_adapter // SCHEREMO: Define AXI helper types for downstream iw/dw conversion - localparam int WideDataWidth = $bits(wide_out_req_o.w.data); - localparam int NarrowDataWidth = $bits(narrow_out_req_o[0].w.data); - localparam int AddrWidth = $bits(narrow_out_req_o[0].aw.addr); - localparam int UserWidth = $bits(narrow_out_req_o[0].aw.user); + localparam int WideDataWidth = $bits(wide_out_req_o.w.data); + localparam int NarrowDataWidth = $bits(narrow_out_req_o[0].w.data); + localparam int AddrWidth = $bits(narrow_out_req_o[0].aw.addr); + localparam int UserWidth = $bits(narrow_out_req_o[0].aw.user); - localparam int ClusterNarrowMasterIdWidth = $bits(clu_narrow_out_req_i.aw.id); - localparam int ClusterWideMasterIdWidth = $bits(clu_wide_out_req_i.aw.id); + localparam int ClusterNarrowMasterIdWidth = $bits(clu_narrow_out_req_i.aw.id); + localparam int ClusterWideMasterIdWidth = $bits(clu_wide_out_req_i.aw.id); - localparam int SocNarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); - localparam int SocNarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); - localparam int SocWideMasterIdWidth = $bits(wide_out_req_o.aw.id); + localparam int SocNarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + localparam int SocNarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); + localparam int SocWideMasterIdWidth = $bits(wide_out_req_o.aw.id); typedef logic [UserWidth-1:0] axi_user_width_t; typedef logic [AddrWidth-1:0] axi_addr_width_t; @@ -87,17 +76,22 @@ module chimera_cluster_adapter typedef logic [NarrowDataWidth-1:0] axi_narrow_data_width_t; typedef logic [NarrowDataWidth/8-1:0] axi_narrow_strb_width_t; - typedef logic [WideDataWidth-1:0] axi_wide_data_width_t; - typedef logic [WideDataWidth/8-1:0] axi_wide_strb_width_t; + typedef logic [WideDataWidth-1:0] axi_wide_data_width_t; + typedef logic [WideDataWidth/8-1:0] axi_wide_strb_width_t; typedef logic [SocNarrowMasterIdWidth-1:0] axi_soc_narrow_mst_id_width_t; typedef logic [SocNarrowSlaveIdWidth-1:0] axi_soc_narrow_slv_id_width_t; typedef logic [SocWideMasterIdWidth-1:0] axi_soc_wide_mst_id_width_y; - `AXI_TYPEDEF_ALL(axi_clu_wide_out, axi_addr_width_t, axi_soc_wide_mst_id_width_y, axi_wide_data_width_t, axi_wide_strb_width_t, axi_user_width_t) - `AXI_TYPEDEF_ALL(axi_narrow_in, axi_addr_width_t, axi_soc_narrow_slv_id_width_t, axi_narrow_data_width_t, axi_narrow_strb_width_t, axi_user_width_t) - `AXI_TYPEDEF_ALL(axi_narrow_out, axi_addr_width_t, axi_soc_narrow_mst_id_width_t, axi_narrow_data_width_t, axi_narrow_strb_width_t, axi_user_width_t) - `AXI_TYPEDEF_ALL(axi_chimera_cluster_wrapper_out_wide_to_narrow, axi_addr_width_t, axi_soc_narrow_mst_id_width_t, axi_wide_data_width_t, axi_wide_strb_width_t, axi_user_width_t) + `AXI_TYPEDEF_ALL(axi_clu_wide_out, axi_addr_width_t, axi_soc_wide_mst_id_width_y, + axi_wide_data_width_t, axi_wide_strb_width_t, axi_user_width_t) + `AXI_TYPEDEF_ALL(axi_narrow_in, axi_addr_width_t, axi_soc_narrow_slv_id_width_t, + axi_narrow_data_width_t, axi_narrow_strb_width_t, axi_user_width_t) + `AXI_TYPEDEF_ALL(axi_narrow_out, axi_addr_width_t, axi_soc_narrow_mst_id_width_t, + axi_narrow_data_width_t, axi_narrow_strb_width_t, axi_user_width_t) + `AXI_TYPEDEF_ALL(axi_chimera_cluster_wrapper_out_wide_to_narrow, axi_addr_width_t, + axi_soc_narrow_mst_id_width_t, axi_wide_data_width_t, + axi_wide_strb_width_t, axi_user_width_t) // Direct mst outputs of cluster -> has extra id bits on mst, gets iw converted @@ -115,8 +109,11 @@ module chimera_cluster_adapter // Wide mst is demuxed to memory island and rest of SoC - wide_out_req_t axi_from_cluster_wide_premux_req, axi_from_cluster_wide_memisl_req, axi_from_cluster_wide_to_narrow_req; - wide_out_resp_t axi_from_cluster_wide_premux_resp, axi_from_cluster_wide_memisl_resp, axi_from_cluster_wide_to_narrow_resp; + wide_out_req_t axi_from_cluster_wide_premux_req, axi_from_cluster_wide_memisl_req, + axi_from_cluster_wide_to_narrow_req; + + wide_out_resp_t axi_from_cluster_wide_premux_resp, axi_from_cluster_wide_memisl_resp, + axi_from_cluster_wide_to_narrow_resp; // Rest of SoC is width converted from wide to narrow @@ -137,7 +134,8 @@ module chimera_cluster_adapter assign clu_wide_out_resp_o = axi_from_cluster_wide_iwc_resp; // WIDE-TO-NARROW CONVERSION - // Catch requests over the wide port which do not go to the memory island; reroute them over the narrow AXI bus. + // Catch requests over the wide port which do not go to the memory island; + // reroute them over the narrow AXI bus. logic ar_wide_sel, aw_wide_sel; @@ -148,77 +146,80 @@ module chimera_cluster_adapter assign aw_wide_sel = '0; axi_demux_simple #( - .AxiIdWidth(WideSlaveIdWidth), - .AtopSupport(0), - .axi_req_t(wide_out_req_t), - .axi_resp_t(wide_out_resp_t), - .NoMstPorts(2), - .MaxTrans(2), - .AxiLookBits(WideSlaveIdWidth), - .UniqueIds('1) - ) + .AxiIdWidth(WideSlaveIdWidth), + .AtopSupport(0), + .axi_req_t(wide_out_req_t), + .axi_resp_t(wide_out_resp_t), + .NoMstPorts(2), + .MaxTrans(2), + .AxiLookBits(WideSlaveIdWidth), + .UniqueIds('1) + ) i_wide_demux ( - .clk_i(soc_clk_i), - .rst_ni, - .test_i('0), - .slv_req_i(axi_from_cluster_wide_premux_req), - .slv_aw_select_i(aw_wide_sel), - .slv_ar_select_i(ar_wide_sel), - .slv_resp_o(axi_from_cluster_wide_premux_resp), - .mst_reqs_o({axi_from_cluster_wide_memisl_req, axi_from_cluster_wide_to_narrow_req}), - .mst_resps_i({axi_from_cluster_wide_memisl_resp, axi_from_cluster_wide_to_narrow_resp}) - ); + .clk_i(soc_clk_i), + .rst_ni, + .test_i('0), + .slv_req_i(axi_from_cluster_wide_premux_req), + .slv_aw_select_i(aw_wide_sel), + .slv_ar_select_i(ar_wide_sel), + .slv_resp_o(axi_from_cluster_wide_premux_resp), + .mst_reqs_o({axi_from_cluster_wide_memisl_req, + axi_from_cluster_wide_to_narrow_req}), + .mst_resps_i({axi_from_cluster_wide_memisl_resp, + axi_from_cluster_wide_to_narrow_resp}) + ); assign wide_out_req_o = axi_from_cluster_wide_memisl_req; assign axi_from_cluster_wide_memisl_resp = wide_out_resp_i; axi_iw_converter #( - .AxiSlvPortIdWidth ( WideSlaveIdWidth ), - .AxiMstPortIdWidth ( SocNarrowMasterIdWidth ), - .AxiSlvPortMaxUniqIds ( 1 ), - .AxiSlvPortMaxTxnsPerId ( 1 ), - .AxiSlvPortMaxTxns ( 2 ), - .AxiMstPortMaxUniqIds ( 2 ), - .AxiMstPortMaxTxnsPerId ( 2 ), - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( WideDataWidth ), - .AxiUserWidth ( UserWidth ), - .slv_req_t ( wide_out_req_t ), - .slv_resp_t ( wide_out_resp_t ), - .mst_req_t ( axi_chimera_cluster_wrapper_out_wide_to_narrow_req_t ), - .mst_resp_t ( axi_chimera_cluster_wrapper_out_wide_to_narrow_resp_t ) - ) + .AxiSlvPortIdWidth ( WideSlaveIdWidth ), + .AxiMstPortIdWidth ( SocNarrowMasterIdWidth ), + .AxiSlvPortMaxUniqIds ( 1 ), + .AxiSlvPortMaxTxnsPerId ( 1 ), + .AxiSlvPortMaxTxns ( 2 ), + .AxiMstPortMaxUniqIds ( 2 ), + .AxiMstPortMaxTxnsPerId ( 2 ), + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( WideDataWidth ), + .AxiUserWidth ( UserWidth ), + + .slv_req_t ( wide_out_req_t ), + .slv_resp_t ( wide_out_resp_t ), + .mst_req_t (axi_chimera_cluster_wrapper_out_wide_to_narrow_req_t), + .mst_resp_t (axi_chimera_cluster_wrapper_out_wide_to_narrow_resp_t) + ) wide_to_narrow_mst_iw_converter( - .clk_i ( soc_clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_from_cluster_wide_to_narrow_req ), - .slv_resp_o ( axi_from_cluster_wide_to_narrow_resp ), - .mst_req_o ( axi_from_cluster_wide_to_narrow_iwc_req ), - .mst_resp_i ( axi_from_cluster_wide_to_narrow_iwc_resp ) - ); + .clk_i ( soc_clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_from_cluster_wide_to_narrow_req ), + .slv_resp_o ( axi_from_cluster_wide_to_narrow_resp ), + .mst_req_o ( axi_from_cluster_wide_to_narrow_iwc_req ), + .mst_resp_i ( axi_from_cluster_wide_to_narrow_iwc_resp ) + ); axi_dw_converter #( - .AxiMaxReads(2), - - .AxiSlvPortDataWidth( WideDataWidth ), - .AxiMstPortDataWidth( NarrowDataWidth ), - .AxiAddrWidth( AddrWidth ), - .AxiIdWidth( SocNarrowMasterIdWidth ), - - .aw_chan_t(axi_narrow_out_aw_chan_t), - .b_chan_t(axi_narrow_out_b_chan_t), - .ar_chan_t(axi_narrow_out_ar_chan_t), - - .slv_r_chan_t(axi_chimera_cluster_wrapper_out_wide_to_narrow_r_chan_t), - .slv_w_chan_t(axi_chimera_cluster_wrapper_out_wide_to_narrow_w_chan_t), - .mst_r_chan_t(axi_narrow_out_r_chan_t), - .mst_w_chan_t(axi_narrow_out_w_chan_t), - - .axi_mst_req_t ( narrow_out_req_t ), - .axi_mst_resp_t ( narrow_out_resp_t ), - .axi_slv_req_t ( axi_chimera_cluster_wrapper_out_wide_to_narrow_req_t ), - .axi_slv_resp_t ( axi_chimera_cluster_wrapper_out_wide_to_narrow_resp_t ) - ) + .AxiMaxReads(2), + + .AxiSlvPortDataWidth( WideDataWidth ), + .AxiMstPortDataWidth( NarrowDataWidth ), + .AxiAddrWidth( AddrWidth ), + .AxiIdWidth( SocNarrowMasterIdWidth ), + + .aw_chan_t(axi_narrow_out_aw_chan_t), + .b_chan_t(axi_narrow_out_b_chan_t), + .ar_chan_t(axi_narrow_out_ar_chan_t), + + .slv_r_chan_t(axi_chimera_cluster_wrapper_out_wide_to_narrow_r_chan_t), + .slv_w_chan_t(axi_chimera_cluster_wrapper_out_wide_to_narrow_w_chan_t), + .mst_r_chan_t(axi_narrow_out_r_chan_t), + .mst_w_chan_t(axi_narrow_out_w_chan_t), + + .axi_mst_req_t( narrow_out_req_t ), + .axi_mst_resp_t( narrow_out_resp_t ), + .axi_slv_req_t( axi_chimera_cluster_wrapper_out_wide_to_narrow_req_t ), + .axi_slv_resp_t( axi_chimera_cluster_wrapper_out_wide_to_narrow_resp_t ) + ) i_wide_to_narrow_dw_converter ( .clk_i(soc_clk_i), @@ -232,127 +233,127 @@ module chimera_cluster_adapter // NARROW MASTER PORT ID WIDTH CONVERSION axi_iw_converter #( - .AxiSlvPortIdWidth ( ClusterNarrowMasterIdWidth), - .AxiMstPortIdWidth ( SocNarrowMasterIdWidth ), - - .AxiSlvPortMaxUniqIds ( 2 ), - .AxiSlvPortMaxTxnsPerId ( 2 ), - .AxiSlvPortMaxTxns ( 4 ), - - .AxiMstPortMaxUniqIds ( 2 ), - .AxiMstPortMaxTxnsPerId ( 4 ), - - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( NarrowDataWidth ), - .AxiUserWidth ( UserWidth ), - .slv_req_t ( clu_narrow_out_req_t ), - .slv_resp_t ( clu_narrow_out_resp_t ), - .mst_req_t ( narrow_out_req_t ), - .mst_resp_t ( narrow_out_resp_t ) - ) + .AxiSlvPortIdWidth ( ClusterNarrowMasterIdWidth), + .AxiMstPortIdWidth ( SocNarrowMasterIdWidth ), + + .AxiSlvPortMaxUniqIds ( 2 ), + .AxiSlvPortMaxTxnsPerId ( 2 ), + .AxiSlvPortMaxTxns ( 4 ), + + .AxiMstPortMaxUniqIds ( 2 ), + .AxiMstPortMaxTxnsPerId ( 4 ), + + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( NarrowDataWidth ), + .AxiUserWidth ( UserWidth ), + .slv_req_t ( clu_narrow_out_req_t ), + .slv_resp_t ( clu_narrow_out_resp_t ), + .mst_req_t ( narrow_out_req_t ), + .mst_resp_t ( narrow_out_resp_t ) + ) narrow_mst_iw_converter ( - .clk_i ( clu_clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_from_cluster_iwc_req ), - .slv_resp_o ( axi_from_cluster_iwc_resp ), - .mst_req_o ( axi_from_cluster_req ), - .mst_resp_i ( axi_from_cluster_resp ) - ); + .clk_i ( clu_clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_from_cluster_iwc_req ), + .slv_resp_o ( axi_from_cluster_iwc_resp ), + .mst_req_o ( axi_from_cluster_req ), + .mst_resp_i ( axi_from_cluster_resp ) + ); // WIDE MASTER PORT ID WIDTH CONVERSION axi_iw_converter #( - .AxiSlvPortIdWidth ( ClusterWideMasterIdWidth), - .AxiMstPortIdWidth ( WideSlaveIdWidth), - - .AxiSlvPortMaxUniqIds ( 2 ), - .AxiSlvPortMaxTxnsPerId ( 2 ), - .AxiSlvPortMaxTxns ( 4 ), - - .AxiMstPortMaxUniqIds ( 2 ), - .AxiMstPortMaxTxnsPerId ( 4 ), - - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( WideDataWidth ), - .AxiUserWidth ( UserWidth ), - .slv_req_t ( clu_wide_out_req_t ), - .slv_resp_t ( clu_wide_out_resp_t ), - .mst_req_t ( wide_out_req_t ), - .mst_resp_t ( wide_out_resp_t ) - ) + .AxiSlvPortIdWidth ( ClusterWideMasterIdWidth), + .AxiMstPortIdWidth ( WideSlaveIdWidth), + + .AxiSlvPortMaxUniqIds ( 2 ), + .AxiSlvPortMaxTxnsPerId ( 2 ), + .AxiSlvPortMaxTxns ( 4 ), + + .AxiMstPortMaxUniqIds ( 2 ), + .AxiMstPortMaxTxnsPerId ( 4 ), + + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( WideDataWidth ), + .AxiUserWidth ( UserWidth ), + .slv_req_t ( clu_wide_out_req_t ), + .slv_resp_t ( clu_wide_out_resp_t ), + .mst_req_t ( wide_out_req_t ), + .mst_resp_t ( wide_out_resp_t ) + ) wide_mst_iw_converter ( - .clk_i ( clu_clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_from_cluster_wide_iwc_req ), - .slv_resp_o ( axi_from_cluster_wide_iwc_resp ), - .mst_req_o ( axi_from_cluster_wide_req ), - .mst_resp_i ( axi_from_cluster_wide_resp ) - ); + .clk_i ( clu_clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_from_cluster_wide_iwc_req ), + .slv_resp_o ( axi_from_cluster_wide_iwc_resp ), + .mst_req_o ( axi_from_cluster_wide_req ), + .mst_resp_i ( axi_from_cluster_wide_resp ) + ); // AXI CDCS axi_cdc #( - .aw_chan_t(axi_narrow_in_aw_chan_t), - .w_chan_t(axi_narrow_in_w_chan_t), - .b_chan_t(axi_narrow_in_b_chan_t), - .ar_chan_t(axi_narrow_in_ar_chan_t), - .r_chan_t(axi_narrow_in_r_chan_t), - .axi_req_t(narrow_in_req_t), - .axi_resp_t(narrow_in_resp_t) - ) + .aw_chan_t(axi_narrow_in_aw_chan_t), + .w_chan_t(axi_narrow_in_w_chan_t), + .b_chan_t(axi_narrow_in_b_chan_t), + .ar_chan_t(axi_narrow_in_ar_chan_t), + .r_chan_t(axi_narrow_in_r_chan_t), + .axi_req_t(narrow_in_req_t), + .axi_resp_t(narrow_in_resp_t) + ) narrow_slv_cdc ( - .src_clk_i(soc_clk_i), - .src_rst_ni(rst_ni), - .src_req_i(narrow_in_req_i), - .src_resp_o(narrow_in_resp_o), + .src_clk_i(soc_clk_i), + .src_rst_ni(rst_ni), + .src_req_i(narrow_in_req_i), + .src_resp_o(narrow_in_resp_o), - .dst_clk_i(clu_clk_i), - .dst_rst_ni(rst_ni), - .dst_req_o(axi_to_cluster_req), - .dst_resp_i(axi_to_cluster_resp) - ); + .dst_clk_i(clu_clk_i), + .dst_rst_ni(rst_ni), + .dst_req_o(axi_to_cluster_req), + .dst_resp_i(axi_to_cluster_resp) + ); axi_cdc #( - .aw_chan_t(axi_narrow_out_aw_chan_t), - .w_chan_t(axi_narrow_out_w_chan_t), - .b_chan_t(axi_narrow_out_b_chan_t), - .ar_chan_t(axi_narrow_out_ar_chan_t), - .r_chan_t(axi_narrow_out_r_chan_t), - .axi_req_t(narrow_out_req_t), - .axi_resp_t(narrow_out_resp_t) - ) + .aw_chan_t(axi_narrow_out_aw_chan_t), + .w_chan_t(axi_narrow_out_w_chan_t), + .b_chan_t(axi_narrow_out_b_chan_t), + .ar_chan_t(axi_narrow_out_ar_chan_t), + .r_chan_t(axi_narrow_out_r_chan_t), + .axi_req_t(narrow_out_req_t), + .axi_resp_t(narrow_out_resp_t) + ) narrow_mst_cdc ( - .src_clk_i(clu_clk_i), - .src_rst_ni(rst_ni), - .src_req_i(axi_from_cluster_req), - .src_resp_o(axi_from_cluster_resp), + .src_clk_i(clu_clk_i), + .src_rst_ni(rst_ni), + .src_req_i(axi_from_cluster_req), + .src_resp_o(axi_from_cluster_resp), - .dst_clk_i(soc_clk_i), - .dst_rst_ni(rst_ni), - .dst_req_o(narrow_out_req_o[0]), - .dst_resp_i(narrow_out_resp_i[0]) - ); + .dst_clk_i(soc_clk_i), + .dst_rst_ni(rst_ni), + .dst_req_o(narrow_out_req_o[0]), + .dst_resp_i(narrow_out_resp_i[0]) + ); axi_cdc #( - .aw_chan_t(axi_clu_wide_out_aw_chan_t), - .w_chan_t(axi_clu_wide_out_w_chan_t), - .b_chan_t(axi_clu_wide_out_b_chan_t), - .ar_chan_t(axi_clu_wide_out_ar_chan_t), - .r_chan_t(axi_clu_wide_out_r_chan_t), - .axi_req_t(wide_out_req_t), - .axi_resp_t(wide_out_resp_t) - ) + .aw_chan_t(axi_clu_wide_out_aw_chan_t), + .w_chan_t(axi_clu_wide_out_w_chan_t), + .b_chan_t(axi_clu_wide_out_b_chan_t), + .ar_chan_t(axi_clu_wide_out_ar_chan_t), + .r_chan_t(axi_clu_wide_out_r_chan_t), + .axi_req_t(wide_out_req_t), + .axi_resp_t(wide_out_resp_t) + ) wide_mst_cdc ( - .src_clk_i(clu_clk_i), - .src_rst_ni(rst_ni), - .src_req_i(axi_from_cluster_wide_req), - .src_resp_o(axi_from_cluster_wide_resp), - - .dst_clk_i(soc_clk_i), - .dst_rst_ni(rst_ni), - .dst_req_o(axi_from_cluster_wide_premux_req), - .dst_resp_i(axi_from_cluster_wide_premux_resp) - ); + .src_clk_i(clu_clk_i), + .src_rst_ni(rst_ni), + .src_req_i(axi_from_cluster_wide_req), + .src_resp_o(axi_from_cluster_wide_resp), + + .dst_clk_i(soc_clk_i), + .dst_rst_ni(rst_ni), + .dst_req_o(axi_from_cluster_wide_premux_req), + .dst_resp_i(axi_from_cluster_wide_premux_resp) + ); endmodule: chimera_cluster_adapter diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index c8a7756..5dc727e 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -1,24 +1,8 @@ -// ---------------------------------------------------------------------- -// -// File: chimera_pkg.sv -// -// Created: 24.06.2024 -// -// Copyright (C) 2024, ETH Zurich and University of Bologna. -// -// Author: Moritz Scherer, ETH Zurich -// +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // -// Copyright and related rights are licensed under the Solderpad Hardware License, -// Version 0.51 (the "License"); you may not use this file except in compliance with -// the License. You may obtain a copy of the License at http://solderpad.org/licenses/SHL-0.51. -// Unless required by applicable law or agreed to in writing, software, hardware and materials -// distributed under this License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and limitations under the License. -// -// ---------------------------------------------------------------------- +// Moritz Scherer package chimera_pkg; @@ -33,14 +17,14 @@ package chimera_pkg; } ClusterConfig; localparam ClusterConfig ChimeraClusterCfg = { - hasWideMasterPort: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1}, - NrCores: {8'h9, 8'h9, 8'h9, 8'h9, 8'h9} - }; + hasWideMasterPort: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1}, + NrCores: {8'h9, 8'h9, 8'h9, 8'h9, 8'h9} + }; function automatic int _sumVector(byte_bt [iomsb(ExtClusters):0] vector, int vectorLen); int sum = 0; for(int i=0; i module chimera_top_wrapper import cheshire_pkg::*; @@ -28,59 +12,59 @@ module chimera_top_wrapper parameter int unsigned SelectedCfg = 0 ) ( - input logic soc_clk_i, - input logic clu_clk_i, - input logic rst_ni, - input logic test_mode_i, - input logic [1:0] boot_mode_i, - input logic rtc_i, + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic test_mode_i, + input logic [1:0] boot_mode_i, + input logic rtc_i, // JTAG interface - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - output logic jtag_tdo_oe_o, + input logic jtag_tck_i, + input logic jtag_trst_ni, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o, + output logic jtag_tdo_oe_o, // UART interface - output logic uart_tx_o, - input logic uart_rx_i, + output logic uart_tx_o, + input logic uart_rx_i, // UART modem flow control - output logic uart_rts_no, - output logic uart_dtr_no, - input logic uart_cts_ni, - input logic uart_dsr_ni, - input logic uart_dcd_ni, - input logic uart_rin_ni, + output logic uart_rts_no, + output logic uart_dtr_no, + input logic uart_cts_ni, + input logic uart_dsr_ni, + input logic uart_dcd_ni, + input logic uart_rin_ni, // I2C interface - output logic i2c_sda_o, - input logic i2c_sda_i, - output logic i2c_sda_en_o, - output logic i2c_scl_o, - input logic i2c_scl_i, - output logic i2c_scl_en_o, + output logic i2c_sda_o, + input logic i2c_sda_i, + output logic i2c_sda_en_o, + output logic i2c_scl_o, + input logic i2c_scl_i, + output logic i2c_scl_en_o, // SPI host interface - output logic spih_sck_o, - output logic spih_sck_en_o, - output logic [SpihNumCs-1:0] spih_csb_o, - output logic [SpihNumCs-1:0] spih_csb_en_o, - output logic [ 3:0] spih_sd_o, - output logic [ 3:0] spih_sd_en_o, - input logic [ 3:0] spih_sd_i, + output logic spih_sck_o, + output logic spih_sck_en_o, + output logic [SpihNumCs-1:0] spih_csb_o, + output logic [SpihNumCs-1:0] spih_csb_en_o, + output logic [ 3:0] spih_sd_o, + output logic [ 3:0] spih_sd_en_o, + input logic [ 3:0] spih_sd_i, // GPIO interface - input logic [31:0] gpio_i, - output logic [31:0] gpio_o, - output logic [31:0] gpio_en_o, + input logic [31:0] gpio_i, + output logic [31:0] gpio_o, + output logic [31:0] gpio_en_o, // Serial link interface - input logic [SlinkNumChan-1:0] slink_rcv_clk_i, - output logic [SlinkNumChan-1:0] slink_rcv_clk_o, - input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i, - output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o, + input logic [SlinkNumChan-1:0] slink_rcv_clk_i, + output logic [SlinkNumChan-1:0] slink_rcv_clk_o, + input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i, + output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o, // VGA interface - output logic vga_hsync_o, - output logic vga_vsync_o, - output logic [Cfg.VgaRedWidth -1:0] vga_red_o, - output logic [Cfg.VgaGreenWidth-1:0] vga_green_o, - output logic [Cfg.VgaBlueWidth -1:0] vga_blue_o + output logic vga_hsync_o, + output logic vga_vsync_o, + output logic [Cfg.VgaRedWidth -1:0] vga_red_o, + output logic [Cfg.VgaGreenWidth-1:0] vga_green_o, + output logic [Cfg.VgaBlueWidth -1:0] vga_blue_o ); `include "axi/typedef.svh" @@ -113,32 +97,32 @@ module chimera_top_wrapper // Interrupts from and to clusters logic [iomsb(Cfg.NumExtInIntrs):0] intr_ext_in; - logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_out; + logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_out; // Interrupt requests to cluster cores - logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext; - logic [iomsb(Cfg.NumExtIrqHarts):0] mtip_ext; - logic [iomsb(Cfg.NumExtIrqHarts):0] msip_ext; + logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext; + logic [iomsb(Cfg.NumExtIrqHarts):0] mtip_ext; + logic [iomsb(Cfg.NumExtIrqHarts):0] msip_ext; // Debug interface to cluster cores - logic dbg_active; - logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req; - logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail; + logic dbg_active; + logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req; + logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail; cheshire_soc #( - .Cfg(Cfg), - .ExtHartinfo('0), - .axi_ext_llc_req_t(axi_mst_req_t), - .axi_ext_llc_rsp_t(axi_mst_rsp_t), - .axi_ext_mst_req_t(axi_mst_req_t), - .axi_ext_mst_rsp_t(axi_mst_rsp_t), - .axi_ext_wide_mst_req_t(axi_wide_mst_req_t), - .axi_ext_wide_mst_rsp_t(axi_wide_mst_rsp_t), - .axi_ext_slv_req_t(axi_slv_req_t), - .axi_ext_slv_rsp_t(axi_slv_rsp_t), - .reg_ext_req_t(reg_req_t), - .reg_ext_rsp_t(reg_rsp_t) - ) i_cheshire + .Cfg(Cfg), + .ExtHartinfo('0), + .axi_ext_llc_req_t(axi_mst_req_t), + .axi_ext_llc_rsp_t(axi_mst_rsp_t), + .axi_ext_mst_req_t(axi_mst_req_t), + .axi_ext_mst_rsp_t(axi_mst_rsp_t), + .axi_ext_wide_mst_req_t(axi_wide_mst_req_t), + .axi_ext_wide_mst_rsp_t(axi_wide_mst_rsp_t), + .axi_ext_slv_req_t(axi_slv_req_t), + .axi_ext_slv_rsp_t(axi_slv_rsp_t), + .reg_ext_req_t(reg_req_t), + .reg_ext_rsp_t(reg_rsp_t) + ) i_cheshire ( .clk_i(soc_clk_i), .rst_ni, @@ -221,25 +205,25 @@ module chimera_top_wrapper // TOP-LEVEL REG chimera_reg_top #( - .reg_req_t(reg_req_t), - .reg_rsp_t(reg_rsp_t) - ) + .reg_req_t(reg_req_t), + .reg_rsp_t(reg_rsp_t) + ) i_reg_top ( - .clk_i(soc_clk_i), - .rst_ni, - .reg_req_i(reg_slv_req[TopLevelIdx]), - .reg_rsp_o(reg_slv_rsp[TopLevelIdx]), - .reg2hw(reg2hw), - .devmode_i('1) - ); + .clk_i(soc_clk_i), + .rst_ni, + .reg_req_i(reg_slv_req[TopLevelIdx]), + .reg_rsp_o(reg_slv_rsp[TopLevelIdx]), + .reg2hw(reg2hw), + .devmode_i('1) + ); // SNITCH BOOTROM logic [31:0] snitch_bootrom_addr; - logic [31:0] snitch_bootrom_data, snitch_bootrom_data_q; - logic snitch_bootrom_req, snitch_bootrom_req_q; - logic snitch_bootrom_we, snitch_bootrom_we_q; + logic [31:0] snitch_bootrom_data, snitch_bootrom_data_q; + logic snitch_bootrom_req, snitch_bootrom_req_q; + logic snitch_bootrom_we, snitch_bootrom_we_q; // Delay response by one cycle to fulfill mem protocol @@ -248,62 +232,66 @@ module chimera_top_wrapper `FF(snitch_bootrom_we_q, snitch_bootrom_we, '0, soc_clk_i, rst_ni) reg_to_mem #( - .AW ( 32 ), - .DW ( 32 ), - .req_t ( reg_req_t ), - .rsp_t ( reg_rsp_t ) - ) i_reg_to_snitch_bootrom ( - .clk_i(soc_clk_i), - .rst_ni, - .reg_req_i ( reg_slv_req[SnitchBootROMIdx] ), - .reg_rsp_o ( reg_slv_rsp[SnitchBootROMIdx] ), - .req_o ( snitch_bootrom_req ), - .gnt_i ( snitch_bootrom_req ), - .we_o ( snitch_bootrom_we ), - .addr_o ( snitch_bootrom_addr ), - .wdata_o ( ), - .wstrb_o ( ), - .rdata_i ( snitch_bootrom_data_q ), - .rvalid_i ( snitch_bootrom_req_q ), - .rerror_i ( snitch_bootrom_we_q ) - ); + .AW ( 32 ), + .DW ( 32 ), + .req_t ( reg_req_t ), + .rsp_t ( reg_rsp_t ) + ) i_reg_to_snitch_bootrom ( + .clk_i(soc_clk_i), + .rst_ni, + .reg_req_i ( reg_slv_req[SnitchBootROMIdx] ), + .reg_rsp_o ( reg_slv_rsp[SnitchBootROMIdx] ), + .req_o ( snitch_bootrom_req ), + .gnt_i ( snitch_bootrom_req ), + .we_o ( snitch_bootrom_we ), + .addr_o ( snitch_bootrom_addr ), + .wdata_o ( ), + .wstrb_o ( ), + .rdata_i ( snitch_bootrom_data_q ), + .rvalid_i ( snitch_bootrom_req_q ), + .rerror_i ( snitch_bootrom_we_q ) + ); snitch_bootrom #( - .AddrWidth ( 32 ), - .DataWidth ( 32 ) - ) i_snitch_bootrom ( - .clk_i(soc_clk_i), - .rst_ni, - .req_i ( snitch_bootrom_req ), - .addr_i ( snitch_bootrom_addr ), - .data_o ( snitch_bootrom_data ) - ); + .AddrWidth ( 32 ), + .DataWidth ( 32 ) + ) i_snitch_bootrom ( + .clk_i(soc_clk_i), + .rst_ni, + .req_i ( snitch_bootrom_req ), + .addr_i ( snitch_bootrom_addr ), + .data_o ( snitch_bootrom_data ) + ); // Cluster clock gates logic [ExtClusters-1:0] cluster_clock_gate_en; logic [ExtClusters-1:0] clu_clk_gated; - assign cluster_clock_gate_en = {reg2hw.cluster_5_clk_gate_en, reg2hw.cluster_4_clk_gate_en, reg2hw.cluster_3_clk_gate_en, reg2hw.cluster_2_clk_gate_en, reg2hw.cluster_1_clk_gate_en}; + assign cluster_clock_gate_en = {reg2hw.cluster_5_clk_gate_en, + reg2hw.cluster_4_clk_gate_en, + reg2hw.cluster_3_clk_gate_en, + reg2hw.cluster_2_clk_gate_en, + reg2hw.cluster_1_clk_gate_en}; genvar extClusterIdx; generate - for(extClusterIdx=0; extClusterIdx Adding Translations to Clang + # > + # > Not possible yet! + # > Diagnostic strings should be written in UTF-8, + # > the client can translate to the relevant code page if needed. + # > Each translation completely replaces the format string + # > for the diagnostic. + # > -- http://clang.llvm.org/docs/InternalsManual.html#internals-diag-translation + # + # It's not pretty, due to Python 2 & 3 compatibility. + encoding_py3 = {} + if sys.version_info[0] >= 3: + encoding_py3['encoding'] = 'utf-8' + + try: + proc = subprocess.Popen(invocation, + stdout = subprocess.PIPE, + stderr = subprocess.PIPE, + universal_newlines = True, + **encoding_py3) + except OSError as exc: + raise DiffError("Command '{}' failed to start: {}".format(subprocess.list2cmdline(invocation), exc)) + proc_stdout = proc.stdout + proc_stderr = proc.stderr + if sys.version_info[0] < 3: + # make the pipes compatible with Python 3, + # reading lines should output unicode + encoding = 'utf-8' + proc_stdout = codecs.getreader(encoding)(proc_stdout) + proc_stderr = codecs.getreader(encoding)(proc_stderr) + # hopefully the stderr pipe won't get full and block the process + outs = list(proc_stdout.readlines()) + errs = list(proc_stderr.readlines()) + proc.wait() + if proc.returncode: + raise DiffError( + "Command '{}' returned non-zero exit status {}".format(subprocess.list2cmdline(invocation), + proc.returncode), + errs, + ) + if args.in_place: + return [], errs + return make_diff(file, original, outs), errs + + +def bold_red(s): + return '\x1b[1m\x1b[31m' + s + '\x1b[0m' + + +def colorize(diff_lines): + + def bold(s): + return '\x1b[1m' + s + '\x1b[0m' + + def cyan(s): + return '\x1b[36m' + s + '\x1b[0m' + + def green(s): + return '\x1b[32m' + s + '\x1b[0m' + + def red(s): + return '\x1b[31m' + s + '\x1b[0m' + + for line in diff_lines: + if line[:4] in ['--- ', '+++ ']: + yield bold(line) + elif line.startswith('@@ '): + yield cyan(line) + elif line.startswith('+'): + yield green(line) + elif line.startswith('-'): + yield red(line) + else: + yield line + + +def print_diff(diff_lines, use_color): + if use_color: + diff_lines = colorize(diff_lines) + if sys.version_info[0] < 3: + sys.stdout.writelines((l.encode('utf-8') for l in diff_lines)) + else: + sys.stdout.writelines(diff_lines) + + +def print_trouble(prog, message, use_colors): + error_text = 'error:' + if use_colors: + error_text = bold_red(error_text) + print("{}: {} {}".format(prog, error_text, message), file = sys.stderr) + + +def main(): + parser = argparse.ArgumentParser(description = __doc__) + parser.add_argument('--clang-format-executable', + metavar = 'EXECUTABLE', + help = 'path to the clang-format executable', + default = 'clang-format') + parser.add_argument('--extensions', + help = 'comma separated list of file extensions (default: {})'.format(DEFAULT_EXTENSIONS), + default = DEFAULT_EXTENSIONS) + parser.add_argument('-r', '--recursive', action = 'store_true', help = 'run recursively over directories') + parser.add_argument('-d', '--dry-run', action = 'store_true', help = 'just print the list of files') + parser.add_argument('-i', '--in-place', action = 'store_true', help = 'format file instead of printing differences') + parser.add_argument('files', metavar = 'file', nargs = '+') + parser.add_argument('-q', '--quiet', action = 'store_true', help = "disable output, useful for the exit code") + parser.add_argument('-j', + metavar = 'N', + type = int, + default = 0, + help = 'run N clang-format jobs in parallel' + ' (default number of cpus + 1)') + parser.add_argument('--color', + default = 'auto', + choices = ['auto', 'always', 'never'], + help = 'show colored diff (default: auto)') + parser.add_argument('-e', + '--exclude', + metavar = 'PATTERN', + action = 'append', + default = [], + help = 'exclude paths matching the given glob-like pattern(s)' + ' from recursive search') + parser.add_argument('--style', help = 'formatting style to apply (LLVM, Google, Chromium, Mozilla, WebKit)') + + args = parser.parse_args() + + # use default signal handling, like diff return SIGINT value on ^C + # https://bugs.python.org/issue14229#msg156446 + signal.signal(signal.SIGINT, signal.SIG_DFL) + try: + signal.SIGPIPE + except AttributeError: + # compatibility, SIGPIPE does not exist on Windows + pass + else: + signal.signal(signal.SIGPIPE, signal.SIG_DFL) + + colored_stdout = False + colored_stderr = False + if args.color == 'always': + colored_stdout = True + colored_stderr = True + elif args.color == 'auto': + colored_stdout = sys.stdout.isatty() + colored_stderr = sys.stderr.isatty() + + version_invocation = [args.clang_format_executable, str("--version")] + try: + subprocess.check_call(version_invocation, stdout = DEVNULL) + except subprocess.CalledProcessError as e: + print_trouble(parser.prog, str(e), use_colors = colored_stderr) + return ExitStatus.TROUBLE + except OSError as e: + print_trouble( + parser.prog, + "Command '{}' failed to start: {}".format(subprocess.list2cmdline(version_invocation), e), + use_colors = colored_stderr, + ) + return ExitStatus.TROUBLE + + retcode = ExitStatus.SUCCESS + + excludes = excludes_from_file(DEFAULT_CLANG_FORMAT_IGNORE) + excludes.extend(args.exclude) + + files = list_files(args.files, + recursive = args.recursive, + exclude = excludes, + extensions = args.extensions.split(',')) + + if not files: + return + + njobs = args.j + if njobs == 0: + njobs = multiprocessing.cpu_count() + 1 + njobs = min(len(files), njobs) + + if njobs == 1: + # execute directly instead of in a pool, + # less overhead, simpler stacktraces + it = (run_clang_format_diff_wrapper(args, file) for file in files) + pool = None + else: + pool = multiprocessing.Pool(njobs) + it = pool.imap_unordered(partial(run_clang_format_diff_wrapper, args), files) + pool.close() + while True: + try: + outs, errs = next(it) + except StopIteration: + break + except DiffError as e: + print_trouble(parser.prog, str(e), use_colors = colored_stderr) + retcode = ExitStatus.TROUBLE + sys.stderr.writelines(e.errs) + except UnexpectedError as e: + print_trouble(parser.prog, str(e), use_colors = colored_stderr) + sys.stderr.write(e.formatted_traceback) + retcode = ExitStatus.TROUBLE + # stop at the first unexpected error, + # something could be very wrong, + # don't process all files unnecessarily + if pool: + pool.terminate() + break + else: + sys.stderr.writelines(errs) + if outs == []: + continue + if not args.quiet: + print_diff(outs, use_color = colored_stdout) + if retcode == ExitStatus.SUCCESS: + retcode = ExitStatus.DIFF + if pool: + pool.join() + return retcode + + +if __name__ == '__main__': + sys.exit(main()) diff --git a/sim.mk b/sim.mk index 8ca3fe3..8c43fd7 100644 --- a/sim.mk +++ b/sim.mk @@ -1,27 +1,8 @@ -# ---------------------------------------------------------------------- -# -# File: sim.mk -# -# Created: 25.06.2024 -# -# Copyright (C) 2024, ETH Zurich and University of Bologna. -# -# Author: Moritz Scherer, ETH Zurich -# -# ---------------------------------------------------------------------- +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. +# Moritz Scherer .PHONY: sim sim-clean diff --git a/sw/include/offload.h b/sw/include/offload.h index e866a57..2fc02d3 100644 --- a/sw/include/offload.h +++ b/sw/include/offload.h @@ -1,32 +1,11 @@ -/* ===================================================================== - * Title: offload.h - * Description: - * - * $Date: 23.07.2024 - * - * ===================================================================== */ -/* - * Copyright (C) 2020 ETH Zurich and University of Bologna. - * - * Author: Moritz Scherer, ETH Zurich - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Moritz Scherer #include -void setupInterruptHandler(void* handler); -void offloadToCluster(void* function, uint8_t hartId); +void setupInterruptHandler(void *handler); +void offloadToCluster(void *function, uint8_t hartId); uint32_t waitForCluster(uint8_t clusterId); diff --git a/sw/include/regs/soc_ctrl.h b/sw/include/regs/soc_ctrl.h index af175c7..8d7f7c4 100644 --- a/sw/include/regs/soc_ctrl.h +++ b/sw/include/regs/soc_ctrl.h @@ -4,7 +4,7 @@ // Copyright 2024 ETH Zurich and University of Bologna. // Licensing information found in source file: -// +// // SPDX-License-Identifier: SHL-0.51 #ifndef _CHIMERA_REG_DEFS_ @@ -58,7 +58,7 @@ extern "C" { #define CHIMERA_CLUSTER_5_CLK_GATE_EN_CLUSTER_5_CLK_GATE_EN_BIT 0 #ifdef __cplusplus -} // extern "C" +} // extern "C" #endif -#endif // _CHIMERA_REG_DEFS_ -// End generated register defines for chimera \ No newline at end of file +#endif // _CHIMERA_REG_DEFS_ + // End generated register defines for chimera \ No newline at end of file diff --git a/sw/include/soc_addr_map.h b/sw/include/soc_addr_map.h index 4f2c982..ec03845 100644 --- a/sw/include/soc_addr_map.h +++ b/sw/include/soc_addr_map.h @@ -1,29 +1,8 @@ -/* ===================================================================== - * Title: addr_map.h - * Description: - * - * $Date: 23.07.2024 - * - * ===================================================================== */ -/* - * Copyright (C) 2020 ETH Zurich and University of Bologna. - * - * Author: Moritz Scherer, ETH Zurich - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Moritz Scherer #define CLINT_CTRL_BASE 0x02040000 diff --git a/sw/lib/offload.c b/sw/lib/offload.c index 9bbce7e..29d07ea 100644 --- a/sw/lib/offload.c +++ b/sw/lib/offload.c @@ -1,75 +1,60 @@ -/* ===================================================================== - * Title: offload.c - * Description: - * - * $Date: 23.07.2024 - * - * ===================================================================== */ -/* - * Copyright (C) 2020 ETH Zurich and University of Bologna. - * - * Author: Moritz Scherer, ETH Zurich - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Moritz Scherer #include "regs/soc_ctrl.h" #include "soc_addr_map.h" #include -void setupInterruptHandler(void* handler){ - volatile void** snitchTrapHandlerAddr = (volatile void**) (SOC_CTRL_BASE + CHIMERA_SNITCH_INTR_HANDLER_ADDR_REG_OFFSET); +void setupInterruptHandler(void *handler) { + volatile void **snitchTrapHandlerAddr = + (volatile void **)(SOC_CTRL_BASE + CHIMERA_SNITCH_INTR_HANDLER_ADDR_REG_OFFSET); - *snitchTrapHandlerAddr = handler; + *snitchTrapHandlerAddr = handler; } - /* Offloads a void function pointer to the specified cluster's core 0 */ -void offloadToCluster(void* function, uint8_t clusterId){ +void offloadToCluster(void *function, uint8_t clusterId) { + + volatile void **snitchBootAddr = + (volatile void **)(SOC_CTRL_BASE + CHIMERA_SNITCH_BOOT_ADDR_REG_OFFSET); + + *snitchBootAddr = function; - volatile void** snitchBootAddr = (volatile void**) (SOC_CTRL_BASE + CHIMERA_SNITCH_BOOT_ADDR_REG_OFFSET); - - *snitchBootAddr = function; + uint32_t hartId = clusterId * 9 + 1; - uint32_t hartId = clusterId * 9 + 1; - - volatile uint32_t* interruptTarget = ((uint32_t*) CLINT_CTRL_BASE) + hartId; - *interruptTarget = 1; + volatile uint32_t *interruptTarget = ((uint32_t *)CLINT_CTRL_BASE) + hartId; + *interruptTarget = 1; } -/* Busy waits for the return of a cluster, clears the return register, and returns the return value */ -uint32_t waitForCluster(uint8_t clusterId){ - volatile int32_t* snitchReturnAddr; - if (clusterId == 0){ - snitchReturnAddr = (volatile int32_t*) (SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET); - } else if(clusterId == 1) { - snitchReturnAddr = (volatile int32_t*) (SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET); - } else if(clusterId == 2) { - snitchReturnAddr = (volatile int32_t*) (SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET); - } else if(clusterId == 3) { - snitchReturnAddr = (volatile int32_t*) (SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET); - } else if(clusterId == 4) { - snitchReturnAddr = (volatile int32_t*) (SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_5_RETURN_REG_OFFSET); - } - - while(*snitchReturnAddr == 0){ - - } - - uint32_t retVal = *snitchReturnAddr; - *snitchReturnAddr = 0; - - return retVal; +/* Busy waits for the return of a cluster, clears the return register, and + * returns the return value */ +uint32_t waitForCluster(uint8_t clusterId) { + volatile int32_t *snitchReturnAddr; + if (clusterId == 0) { + snitchReturnAddr = + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET); + } else if (clusterId == 1) { + snitchReturnAddr = + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET); + } else if (clusterId == 2) { + snitchReturnAddr = + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET); + } else if (clusterId == 3) { + snitchReturnAddr = + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET); + } else if (clusterId == 4) { + snitchReturnAddr = + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_5_RETURN_REG_OFFSET); + } + + while (*snitchReturnAddr == 0) { + } + + uint32_t retVal = *snitchReturnAddr; + *snitchReturnAddr = 0; + + return retVal; } diff --git a/sw/sw.mk b/sw/sw.mk index cfd28d5..00dfc4c 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -1,27 +1,8 @@ -# ---------------------------------------------------------------------- -# -# File: sw.mk -# -# Created: 26.06.2024 -# -# Copyright (C) 2024, ETH Zurich and University of Bologna. -# -# Author: Moritz Scherer, ETH Zurich -# -# ---------------------------------------------------------------------- +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. +# Moritz Scherer CHS_SW_INCLUDES += -I$(CHIM_SW_DIR)/include CHS_SW_FLAGS += -falign-functions=64 -march=rv32im diff --git a/sw/tests/testCluster.c b/sw/tests/testCluster.c index 90ee55d..a3a6c1d 100644 --- a/sw/tests/testCluster.c +++ b/sw/tests/testCluster.c @@ -1,32 +1,11 @@ -/* ===================================================================== - * Title: testCluster.c - * Description: - * - * $Date: 26.06.2024 - * - * ===================================================================== */ -/* - * Copyright (C) 2020 ETH Zurich and University of Bologna. - * - * Author: Moritz Scherer, ETH Zurich - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Moritz Scherer -#include #include +#include #define CLUSTERMEMORYSTART CLUSTER_1_BASE #define CLUSTERDISTANCE CLUSTER_2_BASE - CLUSTER_1_BASE @@ -34,27 +13,26 @@ #define TESTVAL 0x00E0D0C0 -int main(){ - volatile int32_t* clusterMemPtr = (volatile int32_t*)CLUSTERMEMORYSTART; - volatile int32_t result; - - uint8_t ret = 0; - for (int i=0; i -#include #include "regs/soc_ctrl.h" #include "soc_addr_map.h" +#include + +int main() { + volatile uint8_t *regPtr = (volatile uint8_t *)SOC_CTRL_BASE; -int main(){ - volatile uint8_t* regPtr = (volatile uint8_t*) SOC_CTRL_BASE; + *(regPtr + CHIMERA_CLUSTER_1_CLK_GATE_EN_REG_OFFSET) = 1; + *(regPtr + CHIMERA_CLUSTER_4_CLK_GATE_EN_REG_OFFSET) = 1; + *(regPtr + CHIMERA_CLUSTER_5_CLK_GATE_EN_REG_OFFSET) = 1; - *(regPtr + CHIMERA_CLUSTER_1_CLK_GATE_EN_REG_OFFSET) = 1; - *(regPtr + CHIMERA_CLUSTER_4_CLK_GATE_EN_REG_OFFSET) = 1; - *(regPtr + CHIMERA_CLUSTER_5_CLK_GATE_EN_REG_OFFSET) = 1; + while (1) { + } - while(1){} - - return 0; - + return 0; } diff --git a/sw/tests/testClusterOffload.c b/sw/tests/testClusterOffload.c index e56fab7..83f0bfe 100644 --- a/sw/tests/testClusterOffload.c +++ b/sw/tests/testClusterOffload.c @@ -1,58 +1,39 @@ -/* ===================================================================== - * Title: testClusterOffload.c - * Description: - * - * $Date: 28.06.2024 - * - * ===================================================================== */ -/* - * Copyright (C) 2020 ETH Zurich and University of Bologna. - * - * Author: Moritz Scherer, ETH Zurich - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -// Simple offload test. Set the trap handler first, offload a function, retrieve return value from cluster. Does not currently take care of stack initialization and bss initialization on cluster. +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Moritz Scherer + +// Simple offload test. Set the trap handler first, offload a function, retrieve +// return value from cluster. Does not currently take care of stack +// initialization and bss initialization on cluster. -#include -#include -#include "soc_addr_map.h" #include "offload.h" +#include "soc_addr_map.h" +#include +#include #define TESTVAL 0x050CCE55 -static uint32_t* clintPointer = (uint32_t*) CLINT_CTRL_BASE; +static uint32_t *clintPointer = (uint32_t *)CLINT_CTRL_BASE; -void clusterTrapHandler(){ - uint8_t hartId; - asm ("csrr %0, mhartid" : "=r" (hartId) ::); +void clusterTrapHandler() { + uint8_t hartId; + asm("csrr %0, mhartid" : "=r"(hartId)::); - volatile uint32_t* interruptTarget = clintPointer + hartId; - *interruptTarget = 0; - return; + volatile uint32_t *interruptTarget = clintPointer + hartId; + *interruptTarget = 0; + return; } -int32_t testReturn(){ - return TESTVAL; +int32_t testReturn() { + return TESTVAL; } -int main(){ - setupInterruptHandler(clusterTrapHandler); - offloadToCluster(testReturn, 1); - uint32_t retVal = waitForCluster(1); - - return (retVal != (TESTVAL | 0x000000001)); +int main() { + setupInterruptHandler(clusterTrapHandler); + offloadToCluster(testReturn, 1); + uint32_t retVal = waitForCluster(1); + + return (retVal != (TESTVAL | 0x000000001)); } diff --git a/target/sim/vsim/setup.chimera_soc.tcl b/target/sim/vsim/setup.chimera_soc.tcl index 103c912..0876587 100644 --- a/target/sim/vsim/setup.chimera_soc.tcl +++ b/target/sim/vsim/setup.chimera_soc.tcl @@ -1,27 +1,8 @@ -# ---------------------------------------------------------------------- -# -# File: setup.chimera_soc.tcl -# -# Created: 25.06.2024 -# -# Copyright (C) 2024, ETH Zurich and University of Bologna. -# -# Author: Moritz Scherer, ETH Zurich -# -# ---------------------------------------------------------------------- +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. +# Moritz Scherer set BINARY ../../../sw/tests/testCluster.memisl.elf set SELCFG 0