diff --git a/hw/chimera_cluster.sv b/hw/chimera_cluster.sv index 3ce1865..94564c2 100644 --- a/hw/chimera_cluster.sv +++ b/hw/chimera_cluster.sv @@ -60,6 +60,9 @@ module chimera_cluster localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + localparam int ClusterNarrowIdWidthIn = ClusterNarrowAxiMstIdWidth; + localparam int ClusterNarrowIdWidthOut = ClusterNarrowAxiMstIdWidth + 2; + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; @@ -72,8 +75,8 @@ module chimera_cluster typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t; typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; - typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; - typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + typedef logic [ClusterNarrowIdWidthIn-1:0] axi_cluster_slv_id_width_narrow_t; + typedef logic [ClusterNarrowIdWidthOut-1:0] axi_cluster_mst_id_width_narrow_t; typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; @@ -91,9 +94,9 @@ module chimera_cluster `AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t, axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) - `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) - `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) `AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t, @@ -164,6 +167,9 @@ module chimera_cluster //////////////////////////////////////////////////////////////////////// // Complement chimera_cluster_adapter with CDC slice for PULP cluster // //////////////////////////////////////////////////////////////////////// + + localparam int LOG_DEPTH = 3; + `include "axi/assign.svh" `include "axi/typedef.svh" //TODO(smazzola): move all of this in a customized cluster adapter for PULP Cluster @@ -172,23 +178,23 @@ module chimera_cluster AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ), .AXI_DATA_WIDTH ( ClusterDataWidth ), - .AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_WIDTH ( ClusterNarrowIdWidthIn ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ) ) soc_to_cluster_axi_bus(); AXI_BUS_ASYNC_GRAY #( .AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ), .AXI_DATA_WIDTH ( ClusterDataWidth ), - .AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_WIDTH ( ClusterNarrowIdWidthIn ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( LOG_DEPTH ) ) async_soc_to_cluster_axi_bus(); axi_cdc_src_intf #( .AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ), .AXI_DATA_WIDTH ( ClusterDataWidth ), - .AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_WIDTH ( ClusterNarrowIdWidthIn ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( LOG_DEPTH ) ) soc_to_cluster_src_cdc_fifo_i ( .src_clk_i ( soc_clk_i ), .src_rst_ni ( rst_ni ), @@ -203,23 +209,23 @@ module chimera_cluster AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ), .AXI_DATA_WIDTH ( ClusterDataWidth ), - .AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_WIDTH ( ClusterNarrowIdWidthOut ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ) ) cluster_to_soc_axi_bus(); AXI_BUS_ASYNC_GRAY #( .AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ), .AXI_DATA_WIDTH ( ClusterDataWidth ), - .AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_WIDTH ( ClusterNarrowIdWidthOut ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( LOG_DEPTH ) ) async_cluster_to_soc_axi_bus(); axi_cdc_dst_intf #( .AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ), .AXI_DATA_WIDTH ( ClusterDataWidth ), - .AXI_ID_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_WIDTH ( ClusterNarrowIdWidthOut ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( LOG_DEPTH ) ) cluster_to_soc_dst_cdc_fifo_i ( .dst_clk_i ( clu_clk_i ), .dst_rst_ni ( rst_ni ), @@ -242,7 +248,7 @@ module chimera_cluster .AXI_DATA_WIDTH ( WideDataWidth ), .AXI_ID_WIDTH ( WideMasterIdWidth ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( LOG_DEPTH ) ) async_dma_axi_bus(); axi_cdc_dst_intf #( @@ -250,7 +256,7 @@ module chimera_cluster .AXI_DATA_WIDTH ( WideDataWidth ), .AXI_ID_WIDTH ( WideMasterIdWidth ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( LOG_DEPTH ) ) dma_dst_cdc_fifo_i ( .dst_clk_i ( clu_clk_i ), .dst_rst_ni ( rst_ni ), @@ -306,24 +312,11 @@ module chimera_cluster .wide_mem_bypass_mode_i(widemem_bypass_i) ); - typedef struct packed { - logic [2:0] ema; - logic [1:0] emaw; - logic [0:0] emas; - } sram_cfg_t; - - typedef struct packed { - sram_cfg_t icache_tag; - sram_cfg_t icache_data; - sram_cfg_t tcdm; - } sram_cfgs_t; - - localparam int unsigned NumIntOutstandingLoads[NrCores] = '{NrCores{32'h1}}; - localparam int unsigned NumIntOutstandingMem[NrCores] = '{NrCores{32'h4}}; + //////////////////////////////////////////////////////////////////////// pulp_cluster #( .NB_CORES ( 8 ), // snitch_cluster had 9 because 1 was DMA - .HWPE_WIDTH_FAC ( 9 ), // ??? + .HWPE_WIDTH_FAC ( 9 ), // ??? .NB_DMA_PORTS ( 2 ), // ??? .N_HWPE ( 1 ), // ??? .TCDM_SIZE ( 128*1024 ), // ??? @@ -349,10 +342,10 @@ module chimera_cluster .AXI_DATA_C2S_WIDTH ( ClusterDataWidth ), .AXI_DMA_DATA_C2S_WIDTH ( WideDataWidth ), .AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth), - .AXI_ID_IN_WIDTH ( ClusterNarrowAxiMstIdWidth ), - .AXI_ID_OUT_WIDTH ( ClusterNarrowAxiMstIdWidth ), + .AXI_ID_IN_WIDTH ( ClusterNarrowIdWidthIn ), + .AXI_ID_OUT_WIDTH ( ClusterNarrowIdWidthOut ), .AXI_DMA_ID_OUT_WIDTH ( WideMasterIdWidth ), - .LOG_DEPTH ( 3 ), + .LOG_DEPTH ( LOG_DEPTH ), .DATA_WIDTH ( 32 ), // ??? .ADDR_WIDTH ( 32 ), .LOG_CLUSTER ( 3 ), diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index 34b8bdb..abff607 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -61,18 +61,15 @@ package chimera_pkg; int unsigned IsolateClusters; } chimera_cfg_t; - // SoC Config - localparam bit SnitchBootROM = 1; - localparam bit TopLevelCfgRegs = 1; - localparam bit ExtCfgRegs = 1; - // ------------------------------- // | External Register Interface | // ------------------------------- + localparam bit SnitchBootROM = 1; + localparam bit TopLevelCfgRegs = 1; + localparam bit ExtCfgRegs = 1; // SCHEREMO: Shared Snitch bootrom, one clock gate per cluster, External regs (PADs, FLLs etc...) localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs; - localparam int ClusterDataWidth = 64; localparam byte_bt SnitchBootROMIdx = 8'h0; localparam doub_bt SnitchBootROMRegionStart = 64'h3000_0000; @@ -104,7 +101,8 @@ ExtClusters 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 }; - localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; + localparam int ClusterDataWidth = 64; + localparam aw_bt ClusterNarrowAxiMstIdWidth = 2; // Parameters for Memory Island localparam int MemIslandIdx = ClusterIdx[ExtClusters-1] + 1;