diff --git a/Bender.lock b/Bender.lock index 0178d60..ff67ed7 100644 --- a/Bender.lock +++ b/Bender.lock @@ -44,8 +44,8 @@ packages: - common_cells - common_verification axi_rt: - revision: d5f857e74d0a5db4e4a2cc3652ca4f40f29a1484 - version: 0.0.0-alpha.8 + revision: 641ea950e24722af747033f2ab85f0e48ea8d7f8 + version: 0.0.0-alpha.9 source: Git: https://github.com/pulp-platform/axi_rt.git dependencies: @@ -149,6 +149,12 @@ packages: - common_cells - fpnew - tech_cells_generic + ethcluster: + revision: 8ab985c7965ec0c3c4dd7e99227439d23804a157 + version: null + source: + Git: git@gitlab.tue.nl:es/convolve-private/ethcluster.git + dependencies: [] fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -185,6 +191,12 @@ packages: - axi - common_cells - register_interface + kulcluster: + revision: e348b6275c79e1b20510f2ee6d497a49fb2699b6 + version: null + source: + Git: git@gitlab.tue.nl:es/convolve-private/kulcluster.git + dependencies: [] memory_island: revision: 64828cb7a9ccc1f1656ec92d06129072f445c319 version: null @@ -268,6 +280,24 @@ packages: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: - common_verification + tuddcim: + revision: 5254a92569a24d1eac28cb8093ea2a8f81a855d5 + version: null + source: + Git: git@gitlab.tue.nl:es/convolve-private/tuddcim.git + dependencies: [] + tuedcim: + revision: 8b3ec32ffe3487a59b45fa49391e8a36196a64c9 + version: null + source: + Git: git@gitlab.tue.nl:es/convolve-private/tuedcim.git + dependencies: [] + tuemega: + revision: b0b1fd2ba0733edb1ecdf6bdb758c005ee385499 + version: null + source: + Git: git@gitlab.tue.nl:es/convolve-private/tuemega.git + dependencies: [] unbent: revision: e9c9d5cfb635f2d4668c816ce9235798cfecb297 version: 0.1.6 diff --git a/Bender.yml b/Bender.yml index 3f15ea3..5afe4db 100644 --- a/Bender.yml +++ b/Bender.yml @@ -17,6 +17,11 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + TUEDCIM: { git: "git@gitlab.tue.nl:es/convolve-private/tuedcim.git", rev: 10102024} + TUEMEGA: { git: "git@gitlab.tue.nl:es/convolve-private/tuemega.git", rev: 11102024} + TUDDCIM: { git: "git@gitlab.tue.nl:es/convolve-private/tuddcim.git", rev: 11102024-6} + KULCLUSTER: { git: "git@gitlab.tue.nl:es/convolve-private/kulcluster.git", rev: 11102024} + ETHCluster: { git: "git@gitlab.tue.nl:es/convolve-private/ethcluster.git", rev: 8ab985c} export_include_dirs: - hw/include @@ -45,6 +50,26 @@ sources: - target/sim/src/tb_chimera_soc.sv - target/sim/src/tb_chimera_pkg.sv + - target: tuedcim + files: + - hw/convolve/chimera_cluster_tuedcim.sv + + - target: tuemega + files: + - hw/convolve/chimera_cluster_tuemega.sv + + - target: tuddcim + files: + - hw/convolve/chimera_cluster_tuddcim.sv + + - target: kulcluster + files: + - hw/convolve/chimera_cluster_kulcluster.sv + + - target: ethcluster + files: + - hw/convolve/chimera_cluster_ethcluster.sv + vendor_package: - name: reggen target_dir: "utils" diff --git a/bender.mk b/bender.mk index 5984911..cf835f3 100644 --- a/bender.mk +++ b/bender.mk @@ -9,3 +9,4 @@ COMMON_TARGS ?= COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl SIM_TARGS = -t test -t sim +EXT_TARGS = -t tuedcim -t tuemega -t kulcluster -t tuddcim diff --git a/chimera.mk b/chimera.mk index 365f213..ceb0eac 100644 --- a/chimera.mk +++ b/chimera.mk @@ -6,9 +6,9 @@ # Lorenzo Leone -CLINTCORES = 46 -PLICCORES = 92 -PLIC_NUM_INTRS = 92 +CLINTCORES = 19 +PLICCORES = 38 +PLIC_NUM_INTRS = 38 .PHONY: update_plic update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson @@ -66,7 +66,7 @@ $(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv $(CHIM_ROOT)/hw/regs/chimera_reg_top.sv: # Nonfree components CHIM_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/chimera-nonfree.git CHIM_NONFREE_DIR ?= $(CHIM_ROOT)/nonfree -CHIM_NONFREE_COMMIT ?= deploy # to deploy `chimera-nonfree` repo changes, push to `deploy` tag +CHIM_NONFREE_COMMIT ?= deploy_convolve # to deploy `chimera-nonfree` repo changes, push to `deploy` tag .PHONY: chim-nonfree-init chim-nonfree-init: diff --git a/hw/bootrom/snitch/snitch_bootrom.bin b/hw/bootrom/snitch/snitch_bootrom.bin index 83f13a5..52c5076 100755 Binary files a/hw/bootrom/snitch/snitch_bootrom.bin and b/hw/bootrom/snitch/snitch_bootrom.bin differ diff --git a/hw/bootrom/snitch/snitch_bootrom.sv b/hw/bootrom/snitch/snitch_bootrom.sv index b5ad550..4d2ecf5 100644 --- a/hw/bootrom/snitch/snitch_bootrom.sv +++ b/hw/bootrom/snitch/snitch_bootrom.sv @@ -30,7 +30,7 @@ module snitch_bootrom #( data_o = '0; unique case (word) 000: data_o = 32'h30057073 /* 0x0000 */; - 001: data_o = 32'h244000ef /* 0x0004 */; + 001: data_o = 32'h21c000ef /* 0x0004 */; 002: data_o = 32'h00000297 /* 0x0008 */; 003: data_o = 32'h0a828293 /* 0x000c */; 004: data_o = 32'h30529073 /* 0x0010 */; @@ -61,14 +61,14 @@ module snitch_bootrom #( 029: data_o = 32'h00000e93 /* 0x0074 */; 030: data_o = 32'h00000f13 /* 0x0078 */; 031: data_o = 32'h00000f93 /* 0x007c */; - 032: data_o = 32'h0d4000ef /* 0x0080 */; + 032: data_o = 32'h0cc000ef /* 0x0080 */; 033: data_o = 32'h10500073 /* 0x0084 */; 034: data_o = 32'h048000ef /* 0x0088 */; 035: data_o = 32'h00001297 /* 0x008c */; 036: data_o = 32'hf7428293 /* 0x0090 */; 037: data_o = 32'h0002a283 /* 0x0094 */; 038: data_o = 32'h000280e7 /* 0x0098 */; - 039: data_o = 32'h130000ef /* 0x009c */; + 039: data_o = 32'h118000ef /* 0x009c */; 040: data_o = 32'hf75ff06f /* 0x00a0 */; 041: data_o = 32'h00000013 /* 0x00a4 */; 042: data_o = 32'h00000013 /* 0x00a8 */; @@ -82,122 +82,122 @@ module snitch_bootrom #( 050: data_o = 32'h00000000 /* 0x00c8 */; 051: data_o = 32'h00000000 /* 0x00cc */; 052: data_o = 32'hf14027f3 /* 0x00d0 */; - 053: data_o = 32'h01300713 /* 0x00d4 */; + 053: data_o = 32'hfff78793 /* 0x00d4 */; 054: data_o = 32'h0ff7f793 /* 0x00d8 */; - 055: data_o = 32'h04e78463 /* 0x00dc */; - 056: data_o = 32'h00f76c63 /* 0x00e0 */; - 057: data_o = 32'h00100713 /* 0x00e4 */; - 058: data_o = 32'h02e78263 /* 0x00e8 */; - 059: data_o = 32'h00a00693 /* 0x00ec */; - 060: data_o = 32'h02d78463 /* 0x00f0 */; - 061: data_o = 32'h00008067 /* 0x00f4 */; - 062: data_o = 32'h01c00713 /* 0x00f8 */; - 063: data_o = 32'h02e78c63 /* 0x00fc */; - 064: data_o = 32'h02500713 /* 0x0100 */; - 065: data_o = 32'h04e78063 /* 0x0104 */; + 055: data_o = 32'h00900713 /* 0x00dc */; + 056: data_o = 32'h06f76463 /* 0x00e0 */; + 057: data_o = 32'h30000737 /* 0x00e4 */; + 058: data_o = 32'h00279793 /* 0x00e8 */; + 059: data_o = 32'h22c70713 /* 0x00ec */; + 060: data_o = 32'h00e787b3 /* 0x00f0 */; + 061: data_o = 32'h0007a783 /* 0x00f4 */; + 062: data_o = 32'h00078067 /* 0x00f8 */; + 063: data_o = 32'h300017b7 /* 0x00fc */; + 064: data_o = 32'h00100713 /* 0x0100 */; + 065: data_o = 32'h04e7a223 /* 0x0104 */; 066: data_o = 32'h00008067 /* 0x0108 */; - 067: data_o = 32'h30001737 /* 0x010c */; - 068: data_o = 32'h04f72223 /* 0x0110 */; - 069: data_o = 32'h00008067 /* 0x0114 */; - 070: data_o = 32'h300017b7 /* 0x0118 */; - 071: data_o = 32'h04e7a423 /* 0x011c */; - 072: data_o = 32'h00008067 /* 0x0120 */; - 073: data_o = 32'h300017b7 /* 0x0124 */; - 074: data_o = 32'h00100713 /* 0x0128 */; - 075: data_o = 32'h04e7a623 /* 0x012c */; - 076: data_o = 32'h00008067 /* 0x0130 */; - 077: data_o = 32'h300017b7 /* 0x0134 */; - 078: data_o = 32'h00100713 /* 0x0138 */; - 079: data_o = 32'h04e7a823 /* 0x013c */; - 080: data_o = 32'h00008067 /* 0x0140 */; - 081: data_o = 32'h300017b7 /* 0x0144 */; - 082: data_o = 32'h00100713 /* 0x0148 */; - 083: data_o = 32'h04e7aa23 /* 0x014c */; - 084: data_o = 32'h00008067 /* 0x0150 */; - 085: data_o = 32'hf14027f3 /* 0x0154 */; - 086: data_o = 32'h01300713 /* 0x0158 */; - 087: data_o = 32'h0ff7f793 /* 0x015c */; - 088: data_o = 32'h04e78463 /* 0x0160 */; - 089: data_o = 32'h00f76c63 /* 0x0164 */; - 090: data_o = 32'h00100713 /* 0x0168 */; - 091: data_o = 32'h02e78263 /* 0x016c */; - 092: data_o = 32'h00a00713 /* 0x0170 */; - 093: data_o = 32'h02e78463 /* 0x0174 */; - 094: data_o = 32'h00008067 /* 0x0178 */; - 095: data_o = 32'h01c00713 /* 0x017c */; - 096: data_o = 32'h02e78a63 /* 0x0180 */; - 097: data_o = 32'h02500713 /* 0x0184 */; - 098: data_o = 32'h02e78c63 /* 0x0188 */; + 067: data_o = 32'h300017b7 /* 0x010c */; + 068: data_o = 32'h00100713 /* 0x0110 */; + 069: data_o = 32'h04e7a423 /* 0x0114 */; + 070: data_o = 32'h00008067 /* 0x0118 */; + 071: data_o = 32'h300017b7 /* 0x011c */; + 072: data_o = 32'h00100713 /* 0x0120 */; + 073: data_o = 32'h04e7a623 /* 0x0124 */; + 074: data_o = 32'h00008067 /* 0x0128 */; + 075: data_o = 32'h300017b7 /* 0x012c */; + 076: data_o = 32'h00100713 /* 0x0130 */; + 077: data_o = 32'h04e7a823 /* 0x0134 */; + 078: data_o = 32'h00008067 /* 0x0138 */; + 079: data_o = 32'h300017b7 /* 0x013c */; + 080: data_o = 32'h00100713 /* 0x0140 */; + 081: data_o = 32'h04e7aa23 /* 0x0144 */; + 082: data_o = 32'h00008067 /* 0x0148 */; + 083: data_o = 32'hf14027f3 /* 0x014c */; + 084: data_o = 32'hfff78793 /* 0x0150 */; + 085: data_o = 32'h0ff7f793 /* 0x0154 */; + 086: data_o = 32'h00900713 /* 0x0158 */; + 087: data_o = 32'h04f76a63 /* 0x015c */; + 088: data_o = 32'h30000737 /* 0x0160 */; + 089: data_o = 32'h00279793 /* 0x0164 */; + 090: data_o = 32'h25470713 /* 0x0168 */; + 091: data_o = 32'h00e787b3 /* 0x016c */; + 092: data_o = 32'h0007a783 /* 0x0170 */; + 093: data_o = 32'h00078067 /* 0x0174 */; + 094: data_o = 32'h300017b7 /* 0x0178 */; + 095: data_o = 32'h0407a223 /* 0x017c */; + 096: data_o = 32'h00008067 /* 0x0180 */; + 097: data_o = 32'h300017b7 /* 0x0184 */; + 098: data_o = 32'h0407a423 /* 0x0188 */; 099: data_o = 32'h00008067 /* 0x018c */; 100: data_o = 32'h300017b7 /* 0x0190 */; - 101: data_o = 32'h0407a223 /* 0x0194 */; + 101: data_o = 32'h0407a623 /* 0x0194 */; 102: data_o = 32'h00008067 /* 0x0198 */; 103: data_o = 32'h300017b7 /* 0x019c */; - 104: data_o = 32'h0407a423 /* 0x01a0 */; + 104: data_o = 32'h0407a823 /* 0x01a0 */; 105: data_o = 32'h00008067 /* 0x01a4 */; 106: data_o = 32'h300017b7 /* 0x01a8 */; - 107: data_o = 32'h0407a623 /* 0x01ac */; + 107: data_o = 32'h0407aa23 /* 0x01ac */; 108: data_o = 32'h00008067 /* 0x01b0 */; - 109: data_o = 32'h300017b7 /* 0x01b4 */; - 110: data_o = 32'h0407a823 /* 0x01b8 */; - 111: data_o = 32'h00008067 /* 0x01bc */; - 112: data_o = 32'h300017b7 /* 0x01c0 */; - 113: data_o = 32'h0407aa23 /* 0x01c4 */; - 114: data_o = 32'h00008067 /* 0x01c8 */; - 115: data_o = 32'hf14027f3 /* 0x01cc */; - 116: data_o = 32'h01300713 /* 0x01d0 */; - 117: data_o = 32'h0ff7f793 /* 0x01d4 */; - 118: data_o = 32'h00156513 /* 0x01d8 */; - 119: data_o = 32'h04e78463 /* 0x01dc */; - 120: data_o = 32'h00f76c63 /* 0x01e0 */; - 121: data_o = 32'h00100713 /* 0x01e4 */; - 122: data_o = 32'h02e78263 /* 0x01e8 */; - 123: data_o = 32'h00a00713 /* 0x01ec */; - 124: data_o = 32'h02e78463 /* 0x01f0 */; - 125: data_o = 32'h00008067 /* 0x01f4 */; - 126: data_o = 32'h01c00713 /* 0x01f8 */; - 127: data_o = 32'h02e78a63 /* 0x01fc */; - 128: data_o = 32'h02500713 /* 0x0200 */; - 129: data_o = 32'h02e78c63 /* 0x0204 */; - 130: data_o = 32'h00008067 /* 0x0208 */; - 131: data_o = 32'h300017b7 /* 0x020c */; - 132: data_o = 32'h00a7a423 /* 0x0210 */; - 133: data_o = 32'h00008067 /* 0x0214 */; - 134: data_o = 32'h300017b7 /* 0x0218 */; - 135: data_o = 32'h00a7a623 /* 0x021c */; - 136: data_o = 32'h00008067 /* 0x0220 */; - 137: data_o = 32'h300017b7 /* 0x0224 */; - 138: data_o = 32'h00a7a823 /* 0x0228 */; - 139: data_o = 32'h00008067 /* 0x022c */; - 140: data_o = 32'h300017b7 /* 0x0230 */; - 141: data_o = 32'h00a7aa23 /* 0x0234 */; - 142: data_o = 32'h00008067 /* 0x0238 */; - 143: data_o = 32'h300017b7 /* 0x023c */; - 144: data_o = 32'h00a7ac23 /* 0x0240 */; - 145: data_o = 32'h00008067 /* 0x0244 */; - 146: data_o = 32'h304467f3 /* 0x0248 */; - 147: data_o = 32'h300467f3 /* 0x024c */; - 148: data_o = 32'h00008067 /* 0x0250 */; - 149: data_o = 32'h00000000 /* 0x0254 */; - 150: data_o = 32'h00000000 /* 0x0258 */; - 151: data_o = 32'h00000000 /* 0x025c */; - 152: data_o = 32'h00000000 /* 0x0260 */; - 153: data_o = 32'h00000000 /* 0x0264 */; - 154: data_o = 32'h00000000 /* 0x0268 */; - 155: data_o = 32'h00000000 /* 0x026c */; - 156: data_o = 32'h00000000 /* 0x0270 */; - 157: data_o = 32'h00000000 /* 0x0274 */; - 158: data_o = 32'h00000000 /* 0x0278 */; - 159: data_o = 32'h00000000 /* 0x027c */; - 160: data_o = 32'h00000000 /* 0x0280 */; - 161: data_o = 32'h00000000 /* 0x0284 */; - 162: data_o = 32'h00000000 /* 0x0288 */; - 163: data_o = 32'h00000000 /* 0x028c */; - 164: data_o = 32'h00000000 /* 0x0290 */; - 165: data_o = 32'h00000000 /* 0x0294 */; - 166: data_o = 32'h00000000 /* 0x0298 */; - 167: data_o = 32'h00000000 /* 0x029c */; - 168: data_o = 32'h00000000 /* 0x02a0 */; + 109: data_o = 32'hf14027f3 /* 0x01b4 */; + 110: data_o = 32'hfff78793 /* 0x01b8 */; + 111: data_o = 32'h0ff7f793 /* 0x01bc */; + 112: data_o = 32'h00900713 /* 0x01c0 */; + 113: data_o = 32'h00156513 /* 0x01c4 */; + 114: data_o = 32'h04f76a63 /* 0x01c8 */; + 115: data_o = 32'h30000737 /* 0x01cc */; + 116: data_o = 32'h00279793 /* 0x01d0 */; + 117: data_o = 32'h27c70713 /* 0x01d4 */; + 118: data_o = 32'h00e787b3 /* 0x01d8 */; + 119: data_o = 32'h0007a783 /* 0x01dc */; + 120: data_o = 32'h00078067 /* 0x01e0 */; + 121: data_o = 32'h300017b7 /* 0x01e4 */; + 122: data_o = 32'h00a7a423 /* 0x01e8 */; + 123: data_o = 32'h00008067 /* 0x01ec */; + 124: data_o = 32'h300017b7 /* 0x01f0 */; + 125: data_o = 32'h00a7a623 /* 0x01f4 */; + 126: data_o = 32'h00008067 /* 0x01f8 */; + 127: data_o = 32'h300017b7 /* 0x01fc */; + 128: data_o = 32'h00a7a823 /* 0x0200 */; + 129: data_o = 32'h00008067 /* 0x0204 */; + 130: data_o = 32'h300017b7 /* 0x0208 */; + 131: data_o = 32'h00a7aa23 /* 0x020c */; + 132: data_o = 32'h00008067 /* 0x0210 */; + 133: data_o = 32'h300017b7 /* 0x0214 */; + 134: data_o = 32'h00a7ac23 /* 0x0218 */; + 135: data_o = 32'h00008067 /* 0x021c */; + 136: data_o = 32'h304467f3 /* 0x0220 */; + 137: data_o = 32'h300467f3 /* 0x0224 */; + 138: data_o = 32'h00008067 /* 0x0228 */; + 139: data_o = 32'h300000fc /* 0x022c */; + 140: data_o = 32'h30000148 /* 0x0230 */; + 141: data_o = 32'h3000010c /* 0x0234 */; + 142: data_o = 32'h30000148 /* 0x0238 */; + 143: data_o = 32'h3000011c /* 0x023c */; + 144: data_o = 32'h30000148 /* 0x0240 */; + 145: data_o = 32'h3000012c /* 0x0244 */; + 146: data_o = 32'h30000148 /* 0x0248 */; + 147: data_o = 32'h30000148 /* 0x024c */; + 148: data_o = 32'h3000013c /* 0x0250 */; + 149: data_o = 32'h30000178 /* 0x0254 */; + 150: data_o = 32'h300001b0 /* 0x0258 */; + 151: data_o = 32'h30000184 /* 0x025c */; + 152: data_o = 32'h300001b0 /* 0x0260 */; + 153: data_o = 32'h30000190 /* 0x0264 */; + 154: data_o = 32'h300001b0 /* 0x0268 */; + 155: data_o = 32'h3000019c /* 0x026c */; + 156: data_o = 32'h300001b0 /* 0x0270 */; + 157: data_o = 32'h300001b0 /* 0x0274 */; + 158: data_o = 32'h300001a8 /* 0x0278 */; + 159: data_o = 32'h300001e4 /* 0x027c */; + 160: data_o = 32'h3000021c /* 0x0280 */; + 161: data_o = 32'h300001f0 /* 0x0284 */; + 162: data_o = 32'h3000021c /* 0x0288 */; + 163: data_o = 32'h300001fc /* 0x028c */; + 164: data_o = 32'h3000021c /* 0x0290 */; + 165: data_o = 32'h30000208 /* 0x0294 */; + 166: data_o = 32'h3000021c /* 0x0298 */; + 167: data_o = 32'h3000021c /* 0x029c */; + 168: data_o = 32'h30000214 /* 0x02a0 */; 169: data_o = 32'h00000000 /* 0x02a4 */; 170: data_o = 32'h00000000 /* 0x02a8 */; 171: data_o = 32'h00000000 /* 0x02ac */; diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index d208b13..995eb24 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -26,7 +26,7 @@ module chimera_clu_domain ) ( input logic soc_clk_i, input logic [ ExtClusters-1:0] clu_clk_i, - input logic [ ExtClusters-1:0] rst_sync_ni, + input logic rst_ni, input logic [ ExtClusters-1:0] widemem_bypass_i, //----------------------------- // Interrupt ports @@ -54,157 +54,338 @@ module chimera_clu_domain output logic [ ExtClusters-1:0] isolate_o ); - // Axi parameters - localparam int unsigned AxiWideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; - localparam int unsigned AxiWideSlvIdWidth = Cfg.MemIslAxiMstIdWidth + $clog2(Cfg.MemIslWidePorts); - localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2( - cheshire_pkg::gen_axi_in(Cfg.ChsCfg).num_in +`ifdef TARGET_TUEDCIM + + chimera_cluster_tuedcim #( + .Cfg (Cfg), + .NrCores (`NRCORES(TUEDCIMIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_tuedcim ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[TUEDCIMIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[TUEDCIMIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .meip_i (xeip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .msip_i (msip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(TUEDCIMIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[TUEDCIMIDX]), + .narrow_in_resp_o (narrow_in_resp_o[TUEDCIMIDX]), + .narrow_out_req_o (narrow_out_req_o[2*TUEDCIMIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*TUEDCIMIDX+:2]), + .wide_out_req_o (wide_out_req_o[TUEDCIMIDX]), + .wide_out_resp_i (wide_out_resp_i[TUEDCIMIDX]) + ); + +`else + + chimera_cluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(TUEDCIMIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_0 ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[TUEDCIMIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[TUEDCIMIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .meip_i (xeip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .msip_i (msip_i[`PREVNRCORES(TUEDCIMIDX)+:`NRCORES(TUEDCIMIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(TUEDCIMIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[TUEDCIMIDX]), + .narrow_in_resp_o (narrow_in_resp_o[TUEDCIMIDX]), + .narrow_out_req_o (narrow_out_req_o[2*TUEDCIMIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*TUEDCIMIDX+:2]), + .wide_out_req_o (wide_out_req_o[TUEDCIMIDX]), + .wide_out_resp_i (wide_out_resp_i[TUEDCIMIDX]) ); - // Isolated AXI signals - narrow_in_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] narrow_in_isolated_req; - narrow_in_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] narrow_in_isolated_resp; - narrow_out_req_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_isolated_req; - narrow_out_resp_t [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_isolated_resp; - wide_out_req_t [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_isolated_req; - wide_out_resp_t [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_isolated_resp; - - logic [ iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] isolated_narrow_in; - logic [ iomsb(Cfg.ChsCfg.AxiExtNumMst):0] isolated_narrow_out; - logic [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] isolated_wide_out; - - - - for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_clusters - - if (Cfg.IsolateClusters == 1) begin : gen_cluster_iso - // Add AXI isolation at the Narrow Input Interface - axi_isolate #( - .NumPending (Cfg.ChsCfg.AxiMaxSlvTrans), - .TerminateTransaction(0), - .AtopSupport (1), - .AxiAddrWidth (Cfg.ChsCfg.AddrWidth), - .AxiDataWidth (Cfg.ChsCfg.AxiDataWidth), - .AxiIdWidth (AxiSlvIdWidth), - .AxiUserWidth (Cfg.ChsCfg.AxiUserWidth), - .axi_req_t (narrow_in_req_t), - .axi_resp_t (narrow_in_resp_t) - ) i_iso_narrow_in_cluster ( - .clk_i (soc_clk_i), - .rst_ni (rst_sync_ni[extClusterIdx]), - .slv_req_i (narrow_in_req_i[extClusterIdx]), - .slv_resp_o(narrow_in_resp_o[extClusterIdx]), - .mst_req_o (narrow_in_isolated_req[extClusterIdx]), - .mst_resp_i(narrow_in_isolated_resp[extClusterIdx]), - .isolate_i (isolate_i[extClusterIdx]), - .isolated_o(isolated_narrow_in[extClusterIdx]) - ); - - // Add AXI isolation at the Narrow Output Interface. - // Two ports for each cluster: one to convert stray wides, one for the original narrow - for ( - genvar narrowOutIdx = 2 * extClusterIdx; - narrowOutIdx < 2 * extClusterIdx + 2; - narrowOutIdx++ - ) begin : gen_iso_narrow_out - axi_isolate #( - .NumPending (Cfg.ChsCfg.AxiMaxSlvTrans), - .TerminateTransaction(0), - .AtopSupport (1), - .AxiAddrWidth (Cfg.ChsCfg.AddrWidth), - .AxiDataWidth (Cfg.ChsCfg.AxiDataWidth), - .AxiIdWidth (Cfg.ChsCfg.AxiMstIdWidth), - .AxiUserWidth (Cfg.ChsCfg.AxiUserWidth), - .axi_req_t (narrow_out_req_t), - .axi_resp_t (narrow_out_resp_t) - ) i_iso_narrow_out_cluster ( - .clk_i (soc_clk_i), - .rst_ni (rst_sync_ni[extClusterIdx]), - .slv_req_i (narrow_out_isolated_req[narrowOutIdx]), - .slv_resp_o(narrow_out_isolated_resp[narrowOutIdx]), - .mst_req_o (narrow_out_req_o[narrowOutIdx]), - .mst_resp_i(narrow_out_resp_i[narrowOutIdx]), - .isolate_i (isolate_i[extClusterIdx]), - .isolated_o(isolated_narrow_out[narrowOutIdx]) - ); - end : gen_iso_narrow_out - - // Add AXI isolation at the Wide Interface - axi_isolate #( - .NumPending (Cfg.ChsCfg.AxiMaxSlvTrans), - .TerminateTransaction(0), - .AtopSupport (1), - .AxiAddrWidth (Cfg.ChsCfg.AddrWidth), - .AxiDataWidth (AxiWideDataWidth), - .AxiIdWidth (Cfg.MemIslAxiMstIdWidth), // To Check - .AxiUserWidth (Cfg.ChsCfg.AxiUserWidth), - .axi_req_t (wide_out_req_t), - .axi_resp_t (wide_out_resp_t) - ) i_iso_wide_cluster ( - .clk_i (soc_clk_i), - .rst_ni (rst_sync_ni[extClusterIdx]), - .slv_req_i (wide_out_isolated_req[extClusterIdx]), - .slv_resp_o(wide_out_isolated_resp[extClusterIdx]), - .mst_req_o (wide_out_req_o[extClusterIdx]), - .mst_resp_i(wide_out_resp_i[extClusterIdx]), - .isolate_i (isolate_i[extClusterIdx]), - .isolated_o(isolated_wide_out[extClusterIdx]) - ); - - assign isolate_o[extClusterIdx] = isolated_narrow_in[extClusterIdx] & - isolated_narrow_out[2*extClusterIdx+:2] & - isolated_wide_out[extClusterIdx]; - - end else begin : gen_no_cluster_iso // bypass isolate if not required - - assign narrow_in_isolated_req[extClusterIdx] = narrow_in_req_i[extClusterIdx]; - assign narrow_in_resp_o[extClusterIdx] = narrow_in_isolated_resp[extClusterIdx]; - - assign narrow_out_req_o[2*extClusterIdx] = narrow_out_isolated_req[2*extClusterIdx]; - assign narrow_out_isolated_resp[2*extClusterIdx] = narrow_out_resp_i[2*extClusterIdx]; - - assign narrow_out_req_o[2*extClusterIdx+1] = narrow_out_isolated_req[2*extClusterIdx+1]; - assign narrow_out_isolated_resp[2*extClusterIdx+1] = narrow_out_resp_i[2*extClusterIdx+1]; - - assign wide_out_req_o[extClusterIdx] = wide_out_isolated_req[extClusterIdx]; - assign wide_out_isolated_resp[extClusterIdx] = wide_out_resp_i[extClusterIdx]; - - assign isolate_o[extClusterIdx] = '0; - - end : gen_no_cluster_iso - - chimera_cluster #( - .Cfg (Cfg), - .NrCores (`NRCORES(extClusterIdx)), - .narrow_in_req_t (narrow_in_req_t), - .narrow_in_resp_t (narrow_in_resp_t), - .narrow_out_req_t (narrow_out_req_t), - .narrow_out_resp_t(narrow_out_resp_t), - .wide_out_req_t (wide_out_req_t), - .wide_out_resp_t (wide_out_resp_t) - ) i_chimera_cluster ( - .soc_clk_i (soc_clk_i), - .clu_clk_i (clu_clk_i[extClusterIdx]), - .rst_ni (rst_sync_ni[extClusterIdx]), - .widemem_bypass_i (widemem_bypass_i[extClusterIdx]), - .debug_req_i (debug_req_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), - .meip_i (xeip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), - .mtip_i (mtip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), - .msip_i (msip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), - .hart_base_id_i (10'(`PREVNRCORES(extClusterIdx) + 1)), - .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[extClusterIdx][Cfg.ChsCfg.AddrWidth-1:0]), - .boot_addr_i (SnitchBootROMRegionStart[31:0]), - - .narrow_in_req_i (narrow_in_isolated_req[extClusterIdx]), - .narrow_in_resp_o (narrow_in_isolated_resp[extClusterIdx]), - .narrow_out_req_o (narrow_out_isolated_req[2*extClusterIdx+:2]), - .narrow_out_resp_i(narrow_out_isolated_resp[2*extClusterIdx+:2]), - - .wide_out_req_o (wide_out_isolated_req[extClusterIdx]), - .wide_out_resp_i(wide_out_isolated_resp[extClusterIdx]) - ); - - end : gen_clusters +`endif +`ifdef TARGET_TUEMEGA + + chimera_cluster_tuemega #( + .Cfg (Cfg), + .NrCores (`NRCORES(TUEMEGAIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_tuemega ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[TUEMEGAIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[TUEMEGAIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .meip_i (xeip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .msip_i (msip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(TUEMEGAIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEMEGAIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[TUEMEGAIDX]), + .narrow_in_resp_o (narrow_in_resp_o[TUEMEGAIDX]), + .narrow_out_req_o (narrow_out_req_o[2*TUEMEGAIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*TUEMEGAIDX+:2]), + .wide_out_req_o (wide_out_req_o[TUEMEGAIDX]), + .wide_out_resp_i (wide_out_resp_i[TUEMEGAIDX]) + ); + +`else + + chimera_cluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(TUEMEGAIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_1 ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[TUEMEGAIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[TUEMEGAIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .meip_i (xeip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .msip_i (msip_i[`PREVNRCORES(TUEMEGAIDX)+:`NRCORES(TUEMEGAIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(TUEMEGAIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUEMEGAIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[TUEMEGAIDX]), + .narrow_in_resp_o (narrow_in_resp_o[TUEMEGAIDX]), + .narrow_out_req_o (narrow_out_req_o[2*TUEMEGAIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*TUEMEGAIDX+:2]), + .wide_out_req_o (wide_out_req_o[TUEMEGAIDX]), + .wide_out_resp_i (wide_out_resp_i[TUEMEGAIDX]) + ); + + +`endif + +`ifdef TARGET_TUDDCIM + + chimera_cluster_tuddcim #( + .Cfg (Cfg), + .NrCores (`NRCORES(TUDDCIMIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_tuddcim ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[TUDDCIMIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[TUDDCIMIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .meip_i (xeip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .msip_i (msip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(TUDDCIMIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUDDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[TUDDCIMIDX]), + .narrow_in_resp_o (narrow_in_resp_o[TUDDCIMIDX]), + .narrow_out_req_o (narrow_out_req_o[2*TUDDCIMIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*TUDDCIMIDX+:2]), + .wide_out_req_o (wide_out_req_o[TUDDCIMIDX]), + .wide_out_resp_i (wide_out_resp_i[TUDDCIMIDX]) + ); + +`else + + chimera_cluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(TUDDCIMIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_2 ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[TUDDCIMIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[TUDDCIMIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .meip_i (xeip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .msip_i (msip_i[`PREVNRCORES(TUDDCIMIDX)+:`NRCORES(TUDDCIMIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(TUDDCIMIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[TUDDCIMIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[TUDDCIMIDX]), + .narrow_in_resp_o (narrow_in_resp_o[TUDDCIMIDX]), + .narrow_out_req_o (narrow_out_req_o[2*TUDDCIMIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*TUDDCIMIDX+:2]), + .wide_out_req_o (wide_out_req_o[TUDDCIMIDX]), + .wide_out_resp_i (wide_out_resp_i[TUDDCIMIDX]) + ); + + +`endif + +`ifdef TARGET_KULCLUSTER + + chimera_cluster_kulcluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(KULCLUSTERIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_kulcluster ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[KULCLUSTERIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[KULCLUSTERIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .meip_i (xeip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .msip_i (msip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(KULCLUSTERIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[KULCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[KULCLUSTERIDX]), + .narrow_in_resp_o (narrow_in_resp_o[KULCLUSTERIDX]), + .narrow_out_req_o (narrow_out_req_o[2*KULCLUSTERIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*KULCLUSTERIDX+:2]), + .wide_out_req_o (wide_out_req_o[KULCLUSTERIDX]), + .wide_out_resp_i (wide_out_resp_i[KULCLUSTERIDX]) + ); + +`else + + chimera_cluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(KULCLUSTERIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_3 ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[KULCLUSTERIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[KULCLUSTERIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .meip_i (xeip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .msip_i (msip_i[`PREVNRCORES(KULCLUSTERIDX)+:`NRCORES(KULCLUSTERIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(KULCLUSTERIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[KULCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[KULCLUSTERIDX]), + .narrow_in_resp_o (narrow_in_resp_o[KULCLUSTERIDX]), + .narrow_out_req_o (narrow_out_req_o[2*KULCLUSTERIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*KULCLUSTERIDX+:2]), + .wide_out_req_o (wide_out_req_o[KULCLUSTERIDX]), + .wide_out_resp_i (wide_out_resp_i[KULCLUSTERIDX]) + ); + + +`endif + +`ifdef TARGET_ETHCLUSTER + + chimera_cluster_ethcluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(ETHCLUSTERIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_ethcluster ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[ETHCLUSTERIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[ETHCLUSTERIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .meip_i (xeip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .msip_i (msip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(ETHCLUSTERIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[ETHCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[ETHCLUSTERIDX]), + .narrow_in_resp_o (narrow_in_resp_o[ETHCLUSTERIDX]), + .narrow_out_req_o (narrow_out_req_o[2*ETHCLUSTERIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*ETHCLUSTERIDX+:2]), + .wide_out_req_o (wide_out_req_o[ETHCLUSTERIDX]), + .wide_out_resp_i (wide_out_resp_i[ETHCLUSTERIDX]) + ); + +`else + + chimera_cluster #( + .Cfg (Cfg), + .NrCores (`NRCORES(ETHCLUSTERIDX)), + .narrow_in_req_t (narrow_in_req_t), + .narrow_in_resp_t (narrow_in_resp_t), + .narrow_out_req_t (narrow_out_req_t), + .narrow_out_resp_t(narrow_out_resp_t), + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t (wide_out_resp_t) + ) i_chimera_cluster_4 ( + .soc_clk_i (soc_clk_i), + .clu_clk_i (clu_clk_i[ETHCLUSTERIDX]), + .rst_ni, + .widemem_bypass_i (widemem_bypass_i[ETHCLUSTERIDX]), + .debug_req_i (debug_req_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .meip_i (xeip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .mtip_i (mtip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .msip_i (msip_i[`PREVNRCORES(ETHCLUSTERIDX)+:`NRCORES(ETHCLUSTERIDX)]), + .hart_base_id_i (10'(`PREVNRCORES(ETHCLUSTERIDX) + 1)), + .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[ETHCLUSTERIDX][Cfg.ChsCfg.AddrWidth-1:0]), + .boot_addr_i (SnitchBootROMRegionStart[31:0]), + + .narrow_in_req_i (narrow_in_req_i[ETHCLUSTERIDX]), + .narrow_in_resp_o (narrow_in_resp_o[ETHCLUSTERIDX]), + .narrow_out_req_o (narrow_out_req_o[2*ETHCLUSTERIDX+:2]), + .narrow_out_resp_i(narrow_out_resp_i[2*ETHCLUSTERIDX+:2]), + .wide_out_req_o (wide_out_req_o[ETHCLUSTERIDX]), + .wide_out_resp_i (wide_out_resp_i[ETHCLUSTERIDX]) + ); + + +`endif endmodule diff --git a/hw/chimera_memisland_domain.sv b/hw/chimera_memisland_domain.sv index 350514c..09af2ca 100644 --- a/hw/chimera_memisland_domain.sv +++ b/hw/chimera_memisland_domain.sv @@ -24,9 +24,7 @@ module chimera_memisland_domain ); // Define needed parameters - localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2( - cheshire_pkg::gen_axi_in(Cfg.ChsCfg).num_in - ); + localparam int unsigned AxiSlvIdWidth = $bits(axi_narrow_req_i.aw.id); localparam int unsigned WideSlaveIdWidth = $clog2(Cfg.MemIslWidePorts); localparam int unsigned WideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index 34b8bdb..cc35b77 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -28,9 +28,15 @@ package chimera_pkg; byte_bt [iomsb(ExtClusters):0] NrCores; } cluster_config_t; + localparam int unsigned TUEDCIMIDX = 0; + localparam int unsigned TUEMEGAIDX = 1; + localparam int unsigned TUDDCIMIDX = 2; + localparam int unsigned KULCLUSTERIDX = 3; + localparam int unsigned ETHCLUSTERIDX = 4; + localparam cluster_config_t ChimeraClusterCfg = '{ hasWideMasterPort: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1}, - NrCores: {8'h9, 8'h9, 8'h9, 8'h9, 8'h9} + NrCores: {8'h9, 8'h3, 8'h2, 8'h2, 8'h2} }; function automatic int _sumVector(byte_bt [iomsb(ExtClusters):0] vector, int vectorLen); @@ -104,15 +110,13 @@ ExtClusters 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 }; - localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; - // Parameters for Memory Island localparam int MemIslandIdx = ClusterIdx[ExtClusters-1] + 1; localparam doub_bt MemIslRegionStart = 64'h4800_0000; localparam doub_bt MemIslRegionEnd = 64'h4804_0000; localparam aw_bt MemIslAxiMstIdWidth = 1; - localparam byte_bt MemIslNarrowToWideFactor = 4; + localparam byte_bt MemIslNarrowToWideFactor = 16; localparam byte_bt MemIslNarrowPorts = 1; localparam byte_bt MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); localparam byte_bt MemIslNumWideBanks = 2; @@ -121,6 +125,7 @@ ExtClusters // ------------------- // | Generate Cfg | // -------------------- + localparam aw_bt ClusterNarrowAxiMstIdWidth = 2; function automatic chimera_cfg_t gen_chimera_cfg(); localparam int AddrWidth = DefaultCfg.AddrWidth; @@ -143,7 +148,8 @@ ExtClusters // AXI CFG cfg.AxiMstIdWidth = 2; cfg.AxiDataWidth = 32; - cfg.AddrWidth = 32; + cfg.AxiUserWidth = 2; + cfg.AddrWidth = 48; cfg.LlcOutRegionEnd = 'hFFFF_FFFF; cfg.AxiExtNumWideMst = $countones(ChimeraClusterCfg.hasWideMasterPort); diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index d060e68..08f0cd6 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -336,7 +336,7 @@ module chimera_top_wrapper ) i_cluster_domain ( .soc_clk_i (soc_clk_i), .clu_clk_i (clu_clk_gated), - .rst_sync_ni (pmu_rst_clusters_ni), + .rst_ni (rst_ni), .widemem_bypass_i (wide_mem_bypass_mode), .debug_req_i (dbg_ext_req), .xeip_i (xeip_ext), diff --git a/hw/convolve/chimera_cluster_ethcluster.sv b/hw/convolve/chimera_cluster_ethcluster.sv new file mode 100644 index 0000000..5149481 --- /dev/null +++ b/hw/convolve/chimera_cluster_ethcluster.sv @@ -0,0 +1,230 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +module chimera_cluster_ethcluster + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + + parameter int unsigned NrCores = 2, + parameter type narrow_in_req_t = logic, + parameter type narrow_in_resp_t = logic, + parameter type narrow_out_req_t = logic, + parameter type narrow_out_resp_t = logic, + parameter type wide_out_req_t = logic, + parameter type wide_out_resp_t = logic +) ( + + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, + //----------------------------- + // Interrupt ports + //----------------------------- + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, + //----------------------------- + // Cluster base addressing + //----------------------------- + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, + //----------------------------- + // Narrow AXI ports + //----------------------------- + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + //----------------------------- + //Wide AXI ports + //----------------------------- + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i +); + + `include "axi/typedef.svh" + + localparam int WideDataWidth = $bits(wide_out_req_o.w.data); + + localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; + + localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); + localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; + + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + + typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; + typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; + + typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t; + typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; + + typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; + typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + + typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; + typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; + + typedef logic [WideMasterIdWidth-1:0] axi_mst_id_width_wide_t; + typedef logic [WideMasterIdWidth-1+2:0] axi_slv_id_width_wide_t; + + `AXI_TYPEDEF_ALL(axi_cluster_out_wide, axi_addr_t, axi_slv_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_wide, axi_addr_t, axi_mst_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_soc_out_narrow, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow_socIW, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + // Cluster-side in- and out- narrow ports used in chimera adapter + axi_cluster_in_narrow_req_t clu_axi_adapter_slv_req; + axi_cluster_in_narrow_resp_t clu_axi_adapter_slv_resp; + axi_cluster_out_narrow_req_t clu_axi_adapter_mst_req; + axi_cluster_out_narrow_resp_t clu_axi_adapter_mst_resp; + + // Cluster-side in- and out- narrow ports used in narrow adapter + axi_cluster_in_narrow_socIW_req_t clu_axi_narrow_slv_req; + axi_cluster_in_narrow_socIW_resp_t clu_axi_narrow_slv_rsp; + axi_cluster_out_narrow_socIW_req_t [1:0] clu_axi_narrow_mst_req; + axi_cluster_out_narrow_socIW_resp_t [1:0] clu_axi_narrow_mst_rsp; + + // Cluster-side out wide ports + axi_cluster_out_wide_req_t clu_axi_wide_mst_req; + axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; + + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter + + narrow_adapter #( + .narrow_in_req_t (axi_soc_out_narrow_req_t), + .narrow_in_resp_t (axi_soc_out_narrow_resp_t), + .narrow_out_req_t (axi_soc_in_narrow_req_t), + .narrow_out_resp_t(axi_soc_in_narrow_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .MstPorts(2), + .SlvPorts(1) + + ) i_cluster_narrow_adapter ( + .soc_clk_i(soc_clk_i), + .rst_ni, + + // SoC side narrow. + .narrow_in_req_i (narrow_in_req_i), + .narrow_in_resp_o (narrow_in_resp_o), + .narrow_out_req_o (narrow_out_req_o), + .narrow_out_resp_i(narrow_out_resp_i), + + // Cluster side narrow + .clu_narrow_in_req_o (clu_axi_narrow_slv_req), + .clu_narrow_in_resp_i (clu_axi_narrow_slv_rsp), + .clu_narrow_out_req_i (clu_axi_narrow_mst_req), + .clu_narrow_out_resp_o(clu_axi_narrow_mst_rsp) + + ); + + end else begin : gen_skip_narrow_adapter // if (ClusterDataWidth != Cfg.AxiDataWidth) + + assign clu_axi_narrow_slv_req = narrow_in_req_i; + assign narrow_in_resp_o = clu_axi_narrow_slv_rsp; + assign narrow_out_req_o = clu_axi_narrow_mst_req; + assign clu_axi_narrow_mst_rsp = narrow_out_resp_i; + + end + + chimera_cluster_adapter #( + .WidePassThroughRegionStart(Cfg.MemIslRegionStart), + .WidePassThroughRegionEnd (Cfg.MemIslRegionEnd), + + .narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_resp_t), + + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t(wide_out_resp_t), + + .clu_wide_out_req_t (axi_cluster_out_wide_req_t), + .clu_wide_out_resp_t(axi_cluster_out_wide_resp_t) + + ) i_cluster_axi_adapter ( + .soc_clk_i(soc_clk_i), + .clu_clk_i(clu_clk_i), + .rst_ni, + + .narrow_in_req_i (clu_axi_narrow_slv_req), + .narrow_in_resp_o (clu_axi_narrow_slv_rsp), + .narrow_out_req_o (clu_axi_narrow_mst_req), + .narrow_out_resp_i(clu_axi_narrow_mst_rsp), + + .clu_narrow_in_req_o (clu_axi_adapter_slv_req), + .clu_narrow_in_resp_i (clu_axi_adapter_slv_resp), + .clu_narrow_out_req_i (clu_axi_adapter_mst_req), + .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), + + .wide_out_req_o (wide_out_req_o), + .wide_out_resp_i (wide_out_resp_i), + .clu_wide_out_req_i (clu_axi_wide_mst_req), + .clu_wide_out_resp_o(clu_axi_wide_mst_resp), + + .wide_mem_bypass_mode_i(widemem_bypass_i) + ); + + + ETHCluster_snitch_cluster_wrapper #( + ) i_test_cluster ( + .clk_i(clu_clk_i), + .rst_ni, + + .debug_req_i(debug_req_i), + .meip_i (meip_i), + .mtip_i (mtip_i), + .msip_i (msip_i), + + .hart_base_id_i (hart_base_id_i), + .cluster_base_addr_i(cluster_base_addr_i), + + .narrow_in_req_i (clu_axi_adapter_slv_req), + .narrow_in_resp_o (clu_axi_adapter_slv_resp), + .narrow_out_req_o (clu_axi_adapter_mst_req), + .narrow_out_resp_i(clu_axi_adapter_mst_resp), + .wide_in_req_i ('0), + .wide_in_resp_o (), + .wide_out_req_o (clu_axi_wide_mst_req), + .wide_out_resp_i (clu_axi_wide_mst_resp) + + ); +endmodule diff --git a/hw/convolve/chimera_cluster_kulcluster.sv b/hw/convolve/chimera_cluster_kulcluster.sv new file mode 100644 index 0000000..758503b --- /dev/null +++ b/hw/convolve/chimera_cluster_kulcluster.sv @@ -0,0 +1,230 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +module chimera_cluster_kulcluster + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + + parameter int unsigned NrCores = 2, + parameter type narrow_in_req_t = logic, + parameter type narrow_in_resp_t = logic, + parameter type narrow_out_req_t = logic, + parameter type narrow_out_resp_t = logic, + parameter type wide_out_req_t = logic, + parameter type wide_out_resp_t = logic +) ( + + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, + //----------------------------- + // Interrupt ports + //----------------------------- + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, + //----------------------------- + // Cluster base addressing + //----------------------------- + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, + //----------------------------- + // Narrow AXI ports + //----------------------------- + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + //----------------------------- + //Wide AXI ports + //----------------------------- + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i +); + + `include "axi/typedef.svh" + + localparam int WideDataWidth = $bits(wide_out_req_o.w.data); + + localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; + + localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); + localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; + + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + + typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; + typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; + + typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t; + typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; + + typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; + typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + + typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; + typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; + + typedef logic [WideMasterIdWidth-1:0] axi_mst_id_width_wide_t; + typedef logic [WideMasterIdWidth-1+2:0] axi_slv_id_width_wide_t; + + `AXI_TYPEDEF_ALL(axi_cluster_out_wide, axi_addr_t, axi_slv_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_wide, axi_addr_t, axi_mst_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_soc_out_narrow, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow_socIW, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + // Cluster-side in- and out- narrow ports used in chimera adapter + axi_cluster_in_narrow_req_t clu_axi_adapter_slv_req; + axi_cluster_in_narrow_resp_t clu_axi_adapter_slv_resp; + axi_cluster_out_narrow_req_t clu_axi_adapter_mst_req; + axi_cluster_out_narrow_resp_t clu_axi_adapter_mst_resp; + + // Cluster-side in- and out- narrow ports used in narrow adapter + axi_cluster_in_narrow_socIW_req_t clu_axi_narrow_slv_req; + axi_cluster_in_narrow_socIW_resp_t clu_axi_narrow_slv_rsp; + axi_cluster_out_narrow_socIW_req_t [1:0] clu_axi_narrow_mst_req; + axi_cluster_out_narrow_socIW_resp_t [1:0] clu_axi_narrow_mst_rsp; + + // Cluster-side out wide ports + axi_cluster_out_wide_req_t clu_axi_wide_mst_req; + axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; + + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter + + narrow_adapter #( + .narrow_in_req_t (axi_soc_out_narrow_req_t), + .narrow_in_resp_t (axi_soc_out_narrow_resp_t), + .narrow_out_req_t (axi_soc_in_narrow_req_t), + .narrow_out_resp_t(axi_soc_in_narrow_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .MstPorts(2), + .SlvPorts(1) + + ) i_cluster_narrow_adapter ( + .soc_clk_i(soc_clk_i), + .rst_ni, + + // SoC side narrow. + .narrow_in_req_i (narrow_in_req_i), + .narrow_in_resp_o (narrow_in_resp_o), + .narrow_out_req_o (narrow_out_req_o), + .narrow_out_resp_i(narrow_out_resp_i), + + // Cluster side narrow + .clu_narrow_in_req_o (clu_axi_narrow_slv_req), + .clu_narrow_in_resp_i (clu_axi_narrow_slv_rsp), + .clu_narrow_out_req_i (clu_axi_narrow_mst_req), + .clu_narrow_out_resp_o(clu_axi_narrow_mst_rsp) + + ); + + end else begin : gen_skip_narrow_adapter // if (ClusterDataWidth != Cfg.AxiDataWidth) + + assign clu_axi_narrow_slv_req = narrow_in_req_i; + assign narrow_in_resp_o = clu_axi_narrow_slv_rsp; + assign narrow_out_req_o = clu_axi_narrow_mst_req; + assign clu_axi_narrow_mst_rsp = narrow_out_resp_i; + + end + + chimera_cluster_adapter #( + .WidePassThroughRegionStart(Cfg.MemIslRegionStart), + .WidePassThroughRegionEnd (Cfg.MemIslRegionEnd), + + .narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_resp_t), + + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t(wide_out_resp_t), + + .clu_wide_out_req_t (axi_cluster_out_wide_req_t), + .clu_wide_out_resp_t(axi_cluster_out_wide_resp_t) + + ) i_cluster_axi_adapter ( + .soc_clk_i(soc_clk_i), + .clu_clk_i(clu_clk_i), + .rst_ni, + + .narrow_in_req_i (clu_axi_narrow_slv_req), + .narrow_in_resp_o (clu_axi_narrow_slv_rsp), + .narrow_out_req_o (clu_axi_narrow_mst_req), + .narrow_out_resp_i(clu_axi_narrow_mst_rsp), + + .clu_narrow_in_req_o (clu_axi_adapter_slv_req), + .clu_narrow_in_resp_i (clu_axi_adapter_slv_resp), + .clu_narrow_out_req_i (clu_axi_adapter_mst_req), + .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), + + .wide_out_req_o (wide_out_req_o), + .wide_out_resp_i (wide_out_resp_i), + .clu_wide_out_req_i (clu_axi_wide_mst_req), + .clu_wide_out_resp_o(clu_axi_wide_mst_resp), + + .wide_mem_bypass_mode_i(widemem_bypass_i) + ); + + + KULCluster_snax_KUL_cluster_wrapper i_test_cluster ( + .clk_i(clu_clk_i), + .rst_ni, + + .debug_req_i(debug_req_i), + .meip_i (meip_i), + .mtip_i (mtip_i), + .msip_i (msip_i), + + .hart_base_id_i (hart_base_id_i), + .cluster_base_addr_i(cluster_base_addr_i), + .boot_addr_i (boot_addr_i), + + .narrow_in_req_i (clu_axi_adapter_slv_req), + .narrow_in_resp_o (clu_axi_adapter_slv_resp), + .narrow_out_req_o (clu_axi_adapter_mst_req), + .narrow_out_resp_i(clu_axi_adapter_mst_resp), + .wide_in_req_i ('0), + .wide_in_resp_o (), + .wide_out_req_o (clu_axi_wide_mst_req), + .wide_out_resp_i (clu_axi_wide_mst_resp) + + ); +endmodule diff --git a/hw/convolve/chimera_cluster_tuddcim.sv b/hw/convolve/chimera_cluster_tuddcim.sv new file mode 100644 index 0000000..b075566 --- /dev/null +++ b/hw/convolve/chimera_cluster_tuddcim.sv @@ -0,0 +1,230 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +module chimera_cluster_tuddcim + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + + parameter int unsigned NrCores = 2, + parameter type narrow_in_req_t = logic, + parameter type narrow_in_resp_t = logic, + parameter type narrow_out_req_t = logic, + parameter type narrow_out_resp_t = logic, + parameter type wide_out_req_t = logic, + parameter type wide_out_resp_t = logic +) ( + + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, + //----------------------------- + // Interrupt ports + //----------------------------- + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, + //----------------------------- + // Cluster base addressing + //----------------------------- + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, + //----------------------------- + // Narrow AXI ports + //----------------------------- + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + //----------------------------- + //Wide AXI ports + //----------------------------- + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i +); + + `include "axi/typedef.svh" + + localparam int WideDataWidth = $bits(wide_out_req_o.w.data); + + localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; + + localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); + localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; + + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + + typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; + typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; + + typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t; + typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; + + typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; + typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + + typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; + typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; + + typedef logic [WideMasterIdWidth-1:0] axi_mst_id_width_wide_t; + typedef logic [WideMasterIdWidth-1+2:0] axi_slv_id_width_wide_t; + + `AXI_TYPEDEF_ALL(axi_cluster_out_wide, axi_addr_t, axi_slv_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_wide, axi_addr_t, axi_mst_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_soc_out_narrow, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow_socIW, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + // Cluster-side in- and out- narrow ports used in chimera adapter + axi_cluster_in_narrow_req_t clu_axi_adapter_slv_req; + axi_cluster_in_narrow_resp_t clu_axi_adapter_slv_resp; + axi_cluster_out_narrow_req_t clu_axi_adapter_mst_req; + axi_cluster_out_narrow_resp_t clu_axi_adapter_mst_resp; + + // Cluster-side in- and out- narrow ports used in narrow adapter + axi_cluster_in_narrow_socIW_req_t clu_axi_narrow_slv_req; + axi_cluster_in_narrow_socIW_resp_t clu_axi_narrow_slv_rsp; + axi_cluster_out_narrow_socIW_req_t [1:0] clu_axi_narrow_mst_req; + axi_cluster_out_narrow_socIW_resp_t [1:0] clu_axi_narrow_mst_rsp; + + // Cluster-side out wide ports + axi_cluster_out_wide_req_t clu_axi_wide_mst_req; + axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; + + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter + + narrow_adapter #( + .narrow_in_req_t (axi_soc_out_narrow_req_t), + .narrow_in_resp_t (axi_soc_out_narrow_resp_t), + .narrow_out_req_t (axi_soc_in_narrow_req_t), + .narrow_out_resp_t(axi_soc_in_narrow_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .MstPorts(2), + .SlvPorts(1) + + ) i_cluster_narrow_adapter ( + .soc_clk_i(soc_clk_i), + .rst_ni, + + // SoC side narrow. + .narrow_in_req_i (narrow_in_req_i), + .narrow_in_resp_o (narrow_in_resp_o), + .narrow_out_req_o (narrow_out_req_o), + .narrow_out_resp_i(narrow_out_resp_i), + + // Cluster side narrow + .clu_narrow_in_req_o (clu_axi_narrow_slv_req), + .clu_narrow_in_resp_i (clu_axi_narrow_slv_rsp), + .clu_narrow_out_req_i (clu_axi_narrow_mst_req), + .clu_narrow_out_resp_o(clu_axi_narrow_mst_rsp) + + ); + + end else begin : gen_skip_narrow_adapter // if (ClusterDataWidth != Cfg.AxiDataWidth) + + assign clu_axi_narrow_slv_req = narrow_in_req_i; + assign narrow_in_resp_o = clu_axi_narrow_slv_rsp; + assign narrow_out_req_o = clu_axi_narrow_mst_req; + assign clu_axi_narrow_mst_rsp = narrow_out_resp_i; + + end + + chimera_cluster_adapter #( + .WidePassThroughRegionStart(Cfg.MemIslRegionStart), + .WidePassThroughRegionEnd (Cfg.MemIslRegionEnd), + + .narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_resp_t), + + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t(wide_out_resp_t), + + .clu_wide_out_req_t (axi_cluster_out_wide_req_t), + .clu_wide_out_resp_t(axi_cluster_out_wide_resp_t) + + ) i_cluster_axi_adapter ( + .soc_clk_i(soc_clk_i), + .clu_clk_i(clu_clk_i), + .rst_ni, + + .narrow_in_req_i (clu_axi_narrow_slv_req), + .narrow_in_resp_o (clu_axi_narrow_slv_rsp), + .narrow_out_req_o (clu_axi_narrow_mst_req), + .narrow_out_resp_i(clu_axi_narrow_mst_rsp), + + .clu_narrow_in_req_o (clu_axi_adapter_slv_req), + .clu_narrow_in_resp_i (clu_axi_adapter_slv_resp), + .clu_narrow_out_req_i (clu_axi_adapter_mst_req), + .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), + + .wide_out_req_o (wide_out_req_o), + .wide_out_resp_i (wide_out_resp_i), + .clu_wide_out_req_i (clu_axi_wide_mst_req), + .clu_wide_out_resp_o(clu_axi_wide_mst_resp), + + .wide_mem_bypass_mode_i(widemem_bypass_i) + ); + + + TUDDCIM_snax_dream_cluster_wrapper i_test_cluster ( + .clk_i(clu_clk_i), + .rst_ni, + + .debug_req_i(debug_req_i), + .meip_i (meip_i), + .mtip_i (mtip_i), + .msip_i (msip_i), + + .hart_base_id_i (hart_base_id_i), + .cluster_base_addr_i(cluster_base_addr_i), + .boot_addr_i (boot_addr_i), + + .narrow_in_req_i (clu_axi_adapter_slv_req), + .narrow_in_resp_o (clu_axi_adapter_slv_resp), + .narrow_out_req_o (clu_axi_adapter_mst_req), + .narrow_out_resp_i(clu_axi_adapter_mst_resp), + .wide_in_req_i ('0), + .wide_in_resp_o (), + .wide_out_req_o (clu_axi_wide_mst_req), + .wide_out_resp_i (clu_axi_wide_mst_resp) + + ); +endmodule diff --git a/hw/convolve/chimera_cluster_tuedcim.sv b/hw/convolve/chimera_cluster_tuedcim.sv new file mode 100644 index 0000000..52b1880 --- /dev/null +++ b/hw/convolve/chimera_cluster_tuedcim.sv @@ -0,0 +1,230 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +module chimera_cluster_tuedcim + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + + parameter int unsigned NrCores = 2, + parameter type narrow_in_req_t = logic, + parameter type narrow_in_resp_t = logic, + parameter type narrow_out_req_t = logic, + parameter type narrow_out_resp_t = logic, + parameter type wide_out_req_t = logic, + parameter type wide_out_resp_t = logic +) ( + + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, + //----------------------------- + // Interrupt ports + //----------------------------- + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, + //----------------------------- + // Cluster base addressing + //----------------------------- + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, + //----------------------------- + // Narrow AXI ports + //----------------------------- + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + //----------------------------- + //Wide AXI ports + //----------------------------- + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i +); + + `include "axi/typedef.svh" + + localparam int WideDataWidth = $bits(wide_out_req_o.w.data); + + localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; + + localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); + localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; + + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + + typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; + typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; + + typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t; + typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; + + typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; + typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + + typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; + typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; + + typedef logic [WideMasterIdWidth-1:0] axi_mst_id_width_wide_t; + typedef logic [WideMasterIdWidth-1+2:0] axi_slv_id_width_wide_t; + + `AXI_TYPEDEF_ALL(axi_cluster_out_wide, axi_addr_t, axi_slv_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_wide, axi_addr_t, axi_mst_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_soc_out_narrow, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow_socIW, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + // Cluster-side in- and out- narrow ports used in chimera adapter + axi_cluster_in_narrow_req_t clu_axi_adapter_slv_req; + axi_cluster_in_narrow_resp_t clu_axi_adapter_slv_resp; + axi_cluster_out_narrow_req_t clu_axi_adapter_mst_req; + axi_cluster_out_narrow_resp_t clu_axi_adapter_mst_resp; + + // Cluster-side in- and out- narrow ports used in narrow adapter + axi_cluster_in_narrow_socIW_req_t clu_axi_narrow_slv_req; + axi_cluster_in_narrow_socIW_resp_t clu_axi_narrow_slv_rsp; + axi_cluster_out_narrow_socIW_req_t [1:0] clu_axi_narrow_mst_req; + axi_cluster_out_narrow_socIW_resp_t [1:0] clu_axi_narrow_mst_rsp; + + // Cluster-side out wide ports + axi_cluster_out_wide_req_t clu_axi_wide_mst_req; + axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; + + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter + + narrow_adapter #( + .narrow_in_req_t (axi_soc_out_narrow_req_t), + .narrow_in_resp_t (axi_soc_out_narrow_resp_t), + .narrow_out_req_t (axi_soc_in_narrow_req_t), + .narrow_out_resp_t(axi_soc_in_narrow_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .MstPorts(2), + .SlvPorts(1) + + ) i_cluster_narrow_adapter ( + .soc_clk_i(soc_clk_i), + .rst_ni, + + // SoC side narrow. + .narrow_in_req_i (narrow_in_req_i), + .narrow_in_resp_o (narrow_in_resp_o), + .narrow_out_req_o (narrow_out_req_o), + .narrow_out_resp_i(narrow_out_resp_i), + + // Cluster side narrow + .clu_narrow_in_req_o (clu_axi_narrow_slv_req), + .clu_narrow_in_resp_i (clu_axi_narrow_slv_rsp), + .clu_narrow_out_req_i (clu_axi_narrow_mst_req), + .clu_narrow_out_resp_o(clu_axi_narrow_mst_rsp) + + ); + + end else begin : gen_skip_narrow_adapter // if (ClusterDataWidth != Cfg.AxiDataWidth) + + assign clu_axi_narrow_slv_req = narrow_in_req_i; + assign narrow_in_resp_o = clu_axi_narrow_slv_rsp; + assign narrow_out_req_o = clu_axi_narrow_mst_req; + assign clu_axi_narrow_mst_rsp = narrow_out_resp_i; + + end + + chimera_cluster_adapter #( + .WidePassThroughRegionStart(Cfg.MemIslRegionStart), + .WidePassThroughRegionEnd (Cfg.MemIslRegionEnd), + + .narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_resp_t), + + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t(wide_out_resp_t), + + .clu_wide_out_req_t (axi_cluster_out_wide_req_t), + .clu_wide_out_resp_t(axi_cluster_out_wide_resp_t) + + ) i_cluster_axi_adapter ( + .soc_clk_i(soc_clk_i), + .clu_clk_i(clu_clk_i), + .rst_ni, + + .narrow_in_req_i (clu_axi_narrow_slv_req), + .narrow_in_resp_o (clu_axi_narrow_slv_rsp), + .narrow_out_req_o (clu_axi_narrow_mst_req), + .narrow_out_resp_i(clu_axi_narrow_mst_rsp), + + .clu_narrow_in_req_o (clu_axi_adapter_slv_req), + .clu_narrow_in_resp_i (clu_axi_adapter_slv_resp), + .clu_narrow_out_req_i (clu_axi_adapter_mst_req), + .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), + + .wide_out_req_o (wide_out_req_o), + .wide_out_resp_i (wide_out_resp_i), + .clu_wide_out_req_i (clu_axi_wide_mst_req), + .clu_wide_out_resp_o(clu_axi_wide_mst_resp), + + .wide_mem_bypass_mode_i(widemem_bypass_i) + ); + + + TUEDCIM_snax_DCIM_cluster_wrapper i_test_cluster ( + .clk_i(clu_clk_i), + .rst_ni, + + .debug_req_i(debug_req_i), + .meip_i (meip_i), + .mtip_i (mtip_i), + .msip_i (msip_i), + + .hart_base_id_i (hart_base_id_i), + .cluster_base_addr_i(cluster_base_addr_i), + .boot_addr_i (boot_addr_i), + + .narrow_in_req_i (clu_axi_adapter_slv_req), + .narrow_in_resp_o (clu_axi_adapter_slv_resp), + .narrow_out_req_o (clu_axi_adapter_mst_req), + .narrow_out_resp_i(clu_axi_adapter_mst_resp), + .wide_in_req_i ('0), + .wide_in_resp_o (), + .wide_out_req_o (clu_axi_wide_mst_req), + .wide_out_resp_i (clu_axi_wide_mst_resp) + + ); +endmodule diff --git a/hw/convolve/chimera_cluster_tuemega.sv b/hw/convolve/chimera_cluster_tuemega.sv new file mode 100644 index 0000000..944a2b9 --- /dev/null +++ b/hw/convolve/chimera_cluster_tuemega.sv @@ -0,0 +1,230 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +module chimera_cluster_tuemega + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + + parameter int unsigned NrCores = 2, + parameter type narrow_in_req_t = logic, + parameter type narrow_in_resp_t = logic, + parameter type narrow_out_req_t = logic, + parameter type narrow_out_resp_t = logic, + parameter type wide_out_req_t = logic, + parameter type wide_out_resp_t = logic +) ( + + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, + //----------------------------- + // Interrupt ports + //----------------------------- + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, + //----------------------------- + // Cluster base addressing + //----------------------------- + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, + //----------------------------- + // Narrow AXI ports + //----------------------------- + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_t narrow_in_resp_o, + output narrow_out_req_t [ 1:0] narrow_out_req_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + //----------------------------- + //Wide AXI ports + //----------------------------- + output wide_out_req_t wide_out_req_o, + input wide_out_resp_t wide_out_resp_i +); + + `include "axi/typedef.svh" + + localparam int WideDataWidth = $bits(wide_out_req_o.w.data); + + localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); + localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; + + localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); + localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + + typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; + + typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t; + typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t; + + typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t; + typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t; + + typedef logic [WideDataWidth-1:0] axi_cluster_data_wide_t; + typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; + + typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; + typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + + typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; + typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; + + typedef logic [WideMasterIdWidth-1:0] axi_mst_id_width_wide_t; + typedef logic [WideMasterIdWidth-1+2:0] axi_slv_id_width_wide_t; + + `AXI_TYPEDEF_ALL(axi_cluster_out_wide, axi_addr_t, axi_slv_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_wide, axi_addr_t, axi_mst_id_width_wide_t, + axi_cluster_data_wide_t, axi_cluster_strb_wide_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_soc_out_narrow, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_soc_in_narrow, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_soc_data_narrow_t, axi_soc_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow, axi_addr_t, axi_cluster_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow, axi_addr_t, axi_cluster_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + `AXI_TYPEDEF_ALL(axi_cluster_out_narrow_socIW, axi_addr_t, axi_soc_mst_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + `AXI_TYPEDEF_ALL(axi_cluster_in_narrow_socIW, axi_addr_t, axi_soc_slv_id_width_narrow_t, + axi_cluster_data_narrow_t, axi_cluster_strb_narrow_t, axi_user_t) + + // Cluster-side in- and out- narrow ports used in chimera adapter + axi_cluster_in_narrow_req_t clu_axi_adapter_slv_req; + axi_cluster_in_narrow_resp_t clu_axi_adapter_slv_resp; + axi_cluster_out_narrow_req_t clu_axi_adapter_mst_req; + axi_cluster_out_narrow_resp_t clu_axi_adapter_mst_resp; + + // Cluster-side in- and out- narrow ports used in narrow adapter + axi_cluster_in_narrow_socIW_req_t clu_axi_narrow_slv_req; + axi_cluster_in_narrow_socIW_resp_t clu_axi_narrow_slv_rsp; + axi_cluster_out_narrow_socIW_req_t [1:0] clu_axi_narrow_mst_req; + axi_cluster_out_narrow_socIW_resp_t [1:0] clu_axi_narrow_mst_rsp; + + // Cluster-side out wide ports + axi_cluster_out_wide_req_t clu_axi_wide_mst_req; + axi_cluster_out_wide_resp_t clu_axi_wide_mst_resp; + + if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter + + narrow_adapter #( + .narrow_in_req_t (axi_soc_out_narrow_req_t), + .narrow_in_resp_t (axi_soc_out_narrow_resp_t), + .narrow_out_req_t (axi_soc_in_narrow_req_t), + .narrow_out_resp_t(axi_soc_in_narrow_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .MstPorts(2), + .SlvPorts(1) + + ) i_cluster_narrow_adapter ( + .soc_clk_i(soc_clk_i), + .rst_ni, + + // SoC side narrow. + .narrow_in_req_i (narrow_in_req_i), + .narrow_in_resp_o (narrow_in_resp_o), + .narrow_out_req_o (narrow_out_req_o), + .narrow_out_resp_i(narrow_out_resp_i), + + // Cluster side narrow + .clu_narrow_in_req_o (clu_axi_narrow_slv_req), + .clu_narrow_in_resp_i (clu_axi_narrow_slv_rsp), + .clu_narrow_out_req_i (clu_axi_narrow_mst_req), + .clu_narrow_out_resp_o(clu_axi_narrow_mst_rsp) + + ); + + end else begin : gen_skip_narrow_adapter // if (ClusterDataWidth != Cfg.AxiDataWidth) + + assign clu_axi_narrow_slv_req = narrow_in_req_i; + assign narrow_in_resp_o = clu_axi_narrow_slv_rsp; + assign narrow_out_req_o = clu_axi_narrow_mst_req; + assign clu_axi_narrow_mst_rsp = narrow_out_resp_i; + + end + + chimera_cluster_adapter #( + .WidePassThroughRegionStart(Cfg.MemIslRegionStart), + .WidePassThroughRegionEnd (Cfg.MemIslRegionEnd), + + .narrow_in_req_t (axi_cluster_in_narrow_socIW_req_t), + .narrow_in_resp_t (axi_cluster_in_narrow_socIW_resp_t), + .narrow_out_req_t (axi_cluster_out_narrow_socIW_req_t), + .narrow_out_resp_t(axi_cluster_out_narrow_socIW_resp_t), + + .clu_narrow_in_req_t (axi_cluster_in_narrow_req_t), + .clu_narrow_in_resp_t (axi_cluster_in_narrow_resp_t), + .clu_narrow_out_req_t (axi_cluster_out_narrow_req_t), + .clu_narrow_out_resp_t(axi_cluster_out_narrow_resp_t), + + .wide_out_req_t (wide_out_req_t), + .wide_out_resp_t(wide_out_resp_t), + + .clu_wide_out_req_t (axi_cluster_out_wide_req_t), + .clu_wide_out_resp_t(axi_cluster_out_wide_resp_t) + + ) i_cluster_axi_adapter ( + .soc_clk_i(soc_clk_i), + .clu_clk_i(clu_clk_i), + .rst_ni, + + .narrow_in_req_i (clu_axi_narrow_slv_req), + .narrow_in_resp_o (clu_axi_narrow_slv_rsp), + .narrow_out_req_o (clu_axi_narrow_mst_req), + .narrow_out_resp_i(clu_axi_narrow_mst_rsp), + + .clu_narrow_in_req_o (clu_axi_adapter_slv_req), + .clu_narrow_in_resp_i (clu_axi_adapter_slv_resp), + .clu_narrow_out_req_i (clu_axi_adapter_mst_req), + .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), + + .wide_out_req_o (wide_out_req_o), + .wide_out_resp_i (wide_out_resp_i), + .clu_wide_out_req_i (clu_axi_wide_mst_req), + .clu_wide_out_resp_o(clu_axi_wide_mst_resp), + + .wide_mem_bypass_mode_i(widemem_bypass_i) + ); + + + TUEMega_snax_mega_cluster_wrapper i_test_cluster ( + .clk_i(clu_clk_i), + .rst_ni, + + .debug_req_i(debug_req_i), + .meip_i (meip_i), + .mtip_i (mtip_i), + .msip_i (msip_i), + + .hart_base_id_i (hart_base_id_i), + .cluster_base_addr_i(cluster_base_addr_i), + .boot_addr_i (boot_addr_i), + + .narrow_in_req_i (clu_axi_adapter_slv_req), + .narrow_in_resp_o (clu_axi_adapter_slv_resp), + .narrow_out_req_o (clu_axi_adapter_mst_req), + .narrow_out_resp_i(clu_axi_adapter_mst_resp), + .wide_in_req_i ('0), + .wide_in_resp_o (), + .wide_out_req_o (clu_axi_wide_mst_req), + .wide_out_resp_i (clu_axi_wide_mst_resp) + + ); +endmodule diff --git a/hw/rv_plic.cfg.hjson b/hw/rv_plic.cfg.hjson index 402bb1a..b70974e 100644 --- a/hw/rv_plic.cfg.hjson +++ b/hw/rv_plic.cfg.hjson @@ -7,8 +7,8 @@ { instance_name: "rv_plic", param_values: { - src: 92, - target: 92, + src: 38, + target: 19, prio: 7, nonstd_regs: 0 // Do *not* include these: MSIPs are not used and we use a 64 MiB address space }, diff --git a/sw/include/soc_addr_map.h b/sw/include/soc_addr_map.h index 8141c6f..a99808d 100644 --- a/sw/include/soc_addr_map.h +++ b/sw/include/soc_addr_map.h @@ -19,10 +19,10 @@ #define CLUSTER_3_BASE 0x40600000 #define CLUSTER_4_BASE 0x40800000 -#define CLUSTER_0_NUMCORES 9 -#define CLUSTER_1_NUMCORES 9 -#define CLUSTER_2_NUMCORES 9 -#define CLUSTER_3_NUMCORES 9 +#define CLUSTER_0_NUMCORES 2 +#define CLUSTER_1_NUMCORES 2 +#define CLUSTER_2_NUMCORES 2 +#define CLUSTER_3_NUMCORES 3 #define CLUSTER_4_NUMCORES 9 static uint8_t _chimera_numCores[] = {CLUSTER_0_NUMCORES, CLUSTER_1_NUMCORES, CLUSTER_2_NUMCORES, diff --git a/target/sim/sim.mk b/target/sim/sim.mk index fa5ba1d..b0e7f27 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -18,8 +18,9 @@ chim-sim-clean: chim-sim: $(CHIM_SIM_DIR)/vsim/compile.tcl + $(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init - @bender script vsim $(COMMON_TARGS) $(SIM_TARGS) --vlog-arg="$(VLOG_ARGS)"> $@ + @bender script vsim $(COMMON_TARGS) $(SIM_TARGS) $(EXT_TARGS) --vlog-arg="$(VLOG_ARGS)"> $@ echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ endif # chim_sim_mk