From b47f35408ab387779c7e55fd979e02b0b91aaebd Mon Sep 17 00:00:00 2001
From: Lorenzo Leone <lleone@iis.ee.ethz.ch>
Date: Wed, 25 Sep 2024 17:34:10 +0200
Subject: [PATCH] HW: Fixed misisng rst_syn_i port in chimera_clu_domain

---
 hw/chimera_top_wrapper.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv
index 0c236df..cb66857 100644
--- a/hw/chimera_top_wrapper.sv
+++ b/hw/chimera_top_wrapper.sv
@@ -321,7 +321,7 @@ module chimera_top_wrapper
   ) i_cluster_domain (
     .soc_clk_i        (soc_clk_i),
     .clu_clk_i        (clu_clk_gated),
-    .rst_ni           (pmu_rst_clusters_ni),
+    .rst_sync_ni      (pmu_rst_clusters_ni),
     .widemem_bypass_i (wide_mem_bypass_mode),
     .debug_req_i      (dbg_ext_req),
     .xeip_i           (xeip_ext),