From b4fd201c9547763f64b5283a18605392f390826a Mon Sep 17 00:00:00 2001
From: Arpan Suravi Prasad <prasadar@iis.ee.ethz.ch>
Date: Thu, 12 Dec 2024 15:20:34 +0100
Subject: [PATCH] [TB] Cosmetic changes

---
 target/sim/src/tb_chimera_soc.sv  | 24 ++++++++++++------------
 target/sim/src/vip_chimera_soc.sv |  4 ++--
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/sim/src/tb_chimera_soc.sv b/target/sim/src/tb_chimera_soc.sv
index ff46bf6..538cd1e 100644
--- a/target/sim/src/tb_chimera_soc.sv
+++ b/target/sim/src/tb_chimera_soc.sv
@@ -33,16 +33,16 @@ module tb_chimera_soc
 
   // Load a binary
   task automatic force_write(doub_bt addr, doub_bt data);
-    static doub_bt write_address;
-    static doub_bt write_data;
-    write_address = addr;
-    write_data    = data;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_addr_i[1] = write_address;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_req_i[1] = 1'b1;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_we_i[1] = 1'b1;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_wdata_i[1] = write_data;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_strb_i[1] = 4'hf;
-    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_gnt_o[1] = 1'b0;
+    doub_bt write_addr;
+    doub_bt write_data;
+    write_addr  = addr;
+    write_data  = data;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_addr_i[1]   = write_addr;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_req_i[1]    = 1'b1;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_we_i[1]     = 1'b1;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_wdata_i[1]  = write_data;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_strb_i[1]   = 4'hf;
+    force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_gnt_o[1]    = 1'b0;
     force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_rvalid_o[1] = 1'b0;
   endtask
 
@@ -115,11 +115,11 @@ module tb_chimera_soc
           // Initialize JTAG 
           fix.vip.jtag_init();
           // Halt the core
-          fix.vip.jtag_elf_halt();
+          fix.vip.jtag_halt_hart();
           // Preload the binary through FAST PRELOAD
           fast_elf_preload(preload_elf);
           // Unhalt the core
-          fix.vip.jtag_elf_unhalt();
+          fix.vip.jtag_resume_hart();
           // Wait for the end of computation
           fix.vip.jtag_wait_for_eoc(exit_code);
         end
diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv
index 2339fa5..0fd65e6 100644
--- a/target/sim/src/vip_chimera_soc.sv
+++ b/target/sim/src/vip_chimera_soc.sv
@@ -311,7 +311,7 @@ module vip_chimera_soc
   endtask
 
   // Halt the core
-  task automatic jtag_elf_halt();
+  task automatic jtag_halt_hart();
     dm::dmstatus_t status;
     // Halt hart 0
     jtag_write(dm::DMControl, dm::dmcontrol_t'{haltreq: 1, dmactive: 1, default: '0});
@@ -321,7 +321,7 @@ module vip_chimera_soc
   endtask
 
   // Unhalt the core
-  task automatic jtag_elf_unhalt();
+  task automatic jtag_resume_hart();
     doub_bt entry;
     repeat (2) @(posedge jtag_tck);
     void'(get_entry(entry));