diff --git a/Bender.lock b/Bender.lock index a3bb472..43725aa 100644 --- a/Bender.lock +++ b/Bender.lock @@ -69,7 +69,7 @@ packages: - common_cells - register_interface cheshire: - revision: 222efeb8122d47b7794e880dd21078dabaf4e966 + revision: e9fbb914f4f13cb8a52f86780570a292d8aed647 version: null source: Git: https://github.com/pulp-platform/cheshire.git diff --git a/Bender.yml b/Bender.yml index 511e613..5640418 100644 --- a/Bender.yml +++ b/Bender.yml @@ -11,7 +11,7 @@ package: dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } - cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: 222efeb8122d47b7794e880dd21078dabaf4e966} + cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: e9fbb914f4f13cb8a52f86780570a292d8aed647} snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225} common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} diff --git a/Makefile b/Makefile index 8befd56..c38ccb3 100644 --- a/Makefile +++ b/Makefile @@ -16,7 +16,6 @@ SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster) IDMA_ROOT ?= $(shell $(BENDER) path idma) CHS_XLEN ?= 32 -CHS_MEMISL ?= 1 CHIM_HW_DIR ?= $(CHIM_ROOT)/hw CHIM_SW_DIR ?= $(CHIM_ROOT)/sw diff --git a/chimera.mk b/chimera.mk index c05014f..c5d59fd 100644 --- a/chimera.mk +++ b/chimera.mk @@ -4,6 +4,7 @@ # # Moritz Scherer + CLINTCORES = 46 PLICCORES = 92 PLIC_NUM_INTRS = 92 @@ -17,9 +18,11 @@ update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson gen_idma_hw: make -C $(IDMA_ROOT) idma_hw_all +CHS_SW_LD_DIR = $(CHIM_ROOT)/sw/link + .PHONY: chs-hw-init -chs-hw-init: update_plic gen_idma_hw - make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_MEMISL=$(CHS_MEMISL) +chs-hw-init: update_plic gen_idma_hw $(CHIM_SW_LIB) + make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_SW_LD_DIR=$(CHS_SW_LD_DIR) .PHONY: snitch-hw-init snitch-hw-init: @@ -62,7 +65,7 @@ $(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv $(CHIM_ROOT)/hw/regs/chimera_reg_top.sv: # Nonfree components CHIM_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/chimera-nonfree.git CHIM_NONFREE_DIR ?= $(CHIM_ROOT)/nonfree -CHIM_NONFREE_COMMIT ?= deploy # to deploy `chimera-nonfree` repo changes, push to `deploy` tag +CHIM_NONFREE_COMMIT ?= 0825231dfb56fb1ab387d86c4b13bcad7c2fbee9 # to deploy `chimera-nonfree` repo changes, push to `deploy` tag .PHONY: chim-nonfree-init chim-nonfree-init: @@ -73,8 +76,11 @@ chim-nonfree-init: -include $(CHIM_ROOT)/bender.mk -# Include subdir Makefiles +# Necessary to build libchimera.a for bootrom.elf +# TODO: Here the make chim-sw cannot work properly FIND SOLUTION !!!!! -include $(CHIM_ROOT)/sw/sw.mk + +# Include subdir Makefiles -include $(CHIM_ROOT)/utils/utils.mk # Include target makefiles -include $(CHIM_ROOT)/target/sim/sim.mk diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index b33159b..edfcf4c 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -78,8 +78,8 @@ package chimera_pkg; // Parameters for Memory Island localparam int MemIslandIdx = ExtClustersBaseIdx + ExtClusters; - localparam doub_bt MemIslRegionStart = 64'h1800_0000; - localparam doub_bt MemIslRegionEnd = 64'h1804_0000; + localparam doub_bt MemIslRegionStart = 64'h4800_0000; + localparam doub_bt MemIslRegionEnd = 64'h4804_0000; localparam aw_bt MemIslAxiMstIdWidth = 1; localparam byte_bt MemIslNarrowToWideFactor = 4; localparam byte_bt MemIslNarrowPorts = 1; @@ -120,7 +120,6 @@ package chimera_pkg; cfg.AxiExtNumSlv = ExtClusters + MemoryIsland; cfg.AxiExtNumRules = ExtClusters + MemoryIsland; - // lleone: TODO: Use index 0 for memory island cfg.AxiExtRegionIdx = {8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0}; cfg.AxiExtRegionStart = { MemIslRegionStart, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000 diff --git a/hw/include/chimera/typedef.svh b/hw/include/chimera/typedef.svh new file mode 100644 index 0000000..f725322 --- /dev/null +++ b/hw/include/chimera/typedef.svh @@ -0,0 +1,31 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +`ifndef CHIMERA_TYPEDEF_SVH_ +`define CHIMERA_TYPEDEF_SVH_ + +`include "axi/typedef.svh" +`include "register_interface/typedef.svh" +`include "cheshire/typedef.svh" + +`define CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(__prefix, __cfg) \ + localparam type __prefix``addr_t = logic [__cfg.ChsCfg.AddrWidth-1:0]; \ + localparam int wideDataWidth = __cfg.ChsCfg.AxiDataWidth*__cfg.MemIslNarrowToWideFactor; \ + localparam type __prefix``_axi_data_t = logic [wideDataWidth -1:0]; \ + localparam type __prefix``_axi_strb_t = logic [wideDataWidth/8 -1:0]; \ + localparam type __prefix``_axi_user_t = logic [__cfg.ChsCfg.AxiUserWidth -1:0]; \ + localparam type __prefix``_axi_mst_id_t = logic [__cfg.MemIslAxiMstIdWidth-1:0]; \ + localparam type __prefix``_axi_slv_id_t = logic [__cfg.MemIslAxiMstIdWidth + $clog2(__cfg.MemIslWidePorts)-1:0]; \ + `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_mst, __prefix``addr_t, \ + __prefix``_axi_mst_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ + `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_slv, __prefix``addr_t, \ + __prefix``_axi_slv_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ + +// Note that the prefix does *not* include a leading underscore. +`define CHIMERA_TYPEDEF_ALL(__prefix, __cfg) \ + `CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(mem_isl_wide, __cfg) + +`endif diff --git a/sw/link/common.ldh b/sw/link/common.ldh new file mode 100644 index 0000000..f2b3fae --- /dev/null +++ b/sw/link/common.ldh @@ -0,0 +1,55 @@ +/* Copyright 2022 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* Nicole Narr */ +/* Christopher Reinwardt */ +/* Paul Scheffler */ + +/* This header defines symbols and rules universal to bare-metal execution */ + +ENTRY(_start) + +MEMORY { + bootrom (rx) : ORIGIN = 0x02000000, LENGTH = 16K + /* We assume at least 64 KiB SPM, same minus stack for ROMs. */ + /* If more SPM is available, CRT0 repoints the stack. */ + extrom (rx) : ORIGIN = 0x00000000, LENGTH = 48K + spm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + memisl (rwx) : ORIGIN = 0x48000000, LENGTH = 64K + /* We assume at least 8 MiB of DRAM (minimum for Linux). */ + dram (rwx) : ORIGIN = 0x80000000, LENGTH = 8M +} + +SECTIONS { + /* Keep binaries lean */ + /DISCARD/ : { *(.riscv.attributes) *(.comment) } + + /* Global and stack pointer */ + /* By default, keep the calling context (boot ROM) stack pointer */ + __global_pointer$ = ADDR(.misc) + SIZEOF(.misc) / 2; + __stack_pointer$ = 0; + + /* Further addresses */ + __base_dma = 0x01000000; + __base_bootrom = 0x02000000; + __base_clint = 0x02040000; + __base_axirt = 0x020C0000; + __base_axirtgrd = 0x020C1ffc; + __base_regs = 0x03000000; + __base_llc = 0x03001000; + __base_uart = 0x03002000; + __base_i2c = 0x03003000; + __base_spih = 0x03004000; + __base_gpio = 0x03005000; + __base_slink = 0x03006000; + __base_vga = 0x03007000; + __base_usb = 0x03008000; + __base_bus_err = 0x03009000; + __base_plic = 0x04000000; + __base_clic = 0x08000000; + __base_spm = ORIGIN(spm); + __base_dram = ORIGIN(dram); + __base_memisl = ORIGIN(memisl); + __stack_start = ORIGIN(memisl) + LENGTH(memisl); +} diff --git a/sw/link/memisl.ld b/sw/link/memisl.ld new file mode 100644 index 0000000..6dcf16c --- /dev/null +++ b/sw/link/memisl.ld @@ -0,0 +1,46 @@ +/* Copyright 2022 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* Nicole Narr */ +/* Christopher Reinwardt */ +/* Paul Scheffler */ +/* Lorenzo Leone */ + + +INCLUDE common.ldh + +SECTIONS { + .text : { + *(.text._start) + *(.text) + *(.text.*) + } > memisl + + .misc : ALIGN(16) { + *(.rodata) + *(.rodata.*) + *(.data) + *(.data.*) + *(.srodata) + *(.srodata.*) + *(.sdata) + *(.sdata.*) + } > memisl + + . = ALIGN(32); + __bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } > memisl + . = ALIGN(32); + __bss_end = .; + + .bulk : ALIGN(16) { + *(.bulk) + *(.bulk.*) + } > memisl +} diff --git a/sw/sw.mk b/sw/sw.mk index 7d0ba1c..4bf42de 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -33,7 +33,23 @@ CHIM_SW_TEST_SRCS_C = $(wildcard $(CHIM_SW_DIR)/tests/*.c) CHIM_SW_TEST_MEMISL_DUMP = $(CHIM_SW_TEST_SRCS_S:.S=.memisl.dump) $(CHIM_SW_TEST_SRCS_C:.c=.memisl.dump) -CHIM_SW_TESTS += $(CHIM_SW_TEST_DRAM_DUMP) $(CHIM_SW_TEST_SPM_DUMP) $(CHIM_SW_TEST_MEMISL_DUMP) $(CHIM_SW_TEST_SPM_ROMH) $(CHIM_SW_TEST_SPM_GPTH) +CHIM_SW_TESTS += $(CHIM_SW_TEST_MEMISL_DUMP) + +# All objects require up-to-date patches and headers +%.o: %.c + $(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@ + +%.o: %.S + $(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@ + +define chim_sw_ld_elf_rule +.PRECIOUS: %.$(1).elf + +%.$(1).elf: $$(CHS_SW_LD_DIR)/$(1).ld %.o $$(CHS_SW_LIBS) + $$(CHS_SW_CC) $$(CHS_SW_INCLUDES) -T$$< $$(CHS_SW_LDFLAGS) -o $$@ $$*.o $$(CHS_SW_LIBS) +endef + +$(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*.ld)),$(eval $(call chim_sw_ld_elf_rule,$(link)))) chim-sw: $(CHIM_SW_LIB) $(CHIM_SW_TESTS)