From c960e74dbbaf4669ca54a990d2b124975ad40bd9 Mon Sep 17 00:00:00 2001 From: Lorenzo Leone Date: Thu, 26 Sep 2024 17:10:30 +0200 Subject: [PATCH] HW: Add include files for the memory island AXI signals SW: Add linker scripts to build chimera boot --- Bender.lock | 2 +- Bender.yml | 2 +- Makefile | 1 - chimera.mk | 4 ++- hw/include/chimera/typedef.svh | 31 +++++++++++++++++++ sw/link/common.ldh | 55 ++++++++++++++++++++++++++++++++++ sw/link/memisl.ld | 46 ++++++++++++++++++++++++++++ 7 files changed, 137 insertions(+), 4 deletions(-) create mode 100644 hw/include/chimera/typedef.svh create mode 100644 sw/link/common.ldh create mode 100644 sw/link/memisl.ld diff --git a/Bender.lock b/Bender.lock index 89e456d..43725aa 100644 --- a/Bender.lock +++ b/Bender.lock @@ -69,7 +69,7 @@ packages: - common_cells - register_interface cheshire: - revision: e07e827412730c507d077ac5d0c42c4a8c26001b + revision: e9fbb914f4f13cb8a52f86780570a292d8aed647 version: null source: Git: https://github.com/pulp-platform/cheshire.git diff --git a/Bender.yml b/Bender.yml index 68982b8..5640418 100644 --- a/Bender.yml +++ b/Bender.yml @@ -11,7 +11,7 @@ package: dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } - cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: e07e827412730c507d077ac5d0c42c4a8c26001b} + cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: e9fbb914f4f13cb8a52f86780570a292d8aed647} snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225} common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} diff --git a/Makefile b/Makefile index 8befd56..c38ccb3 100644 --- a/Makefile +++ b/Makefile @@ -16,7 +16,6 @@ SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster) IDMA_ROOT ?= $(shell $(BENDER) path idma) CHS_XLEN ?= 32 -CHS_MEMISL ?= 1 CHIM_HW_DIR ?= $(CHIM_ROOT)/hw CHIM_SW_DIR ?= $(CHIM_ROOT)/sw diff --git a/chimera.mk b/chimera.mk index c05014f..07b76be 100644 --- a/chimera.mk +++ b/chimera.mk @@ -17,9 +17,11 @@ update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson gen_idma_hw: make -C $(IDMA_ROOT) idma_hw_all +CHS_SW_LD_DIR = $(CHIM_ROOT)/sw/link + .PHONY: chs-hw-init chs-hw-init: update_plic gen_idma_hw - make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_MEMISL=$(CHS_MEMISL) + make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_SW_LD_DIR=$(CHS_SW_LD_DIR) .PHONY: snitch-hw-init snitch-hw-init: diff --git a/hw/include/chimera/typedef.svh b/hw/include/chimera/typedef.svh new file mode 100644 index 0000000..f725322 --- /dev/null +++ b/hw/include/chimera/typedef.svh @@ -0,0 +1,31 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Moritz Scherer + +`ifndef CHIMERA_TYPEDEF_SVH_ +`define CHIMERA_TYPEDEF_SVH_ + +`include "axi/typedef.svh" +`include "register_interface/typedef.svh" +`include "cheshire/typedef.svh" + +`define CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(__prefix, __cfg) \ + localparam type __prefix``addr_t = logic [__cfg.ChsCfg.AddrWidth-1:0]; \ + localparam int wideDataWidth = __cfg.ChsCfg.AxiDataWidth*__cfg.MemIslNarrowToWideFactor; \ + localparam type __prefix``_axi_data_t = logic [wideDataWidth -1:0]; \ + localparam type __prefix``_axi_strb_t = logic [wideDataWidth/8 -1:0]; \ + localparam type __prefix``_axi_user_t = logic [__cfg.ChsCfg.AxiUserWidth -1:0]; \ + localparam type __prefix``_axi_mst_id_t = logic [__cfg.MemIslAxiMstIdWidth-1:0]; \ + localparam type __prefix``_axi_slv_id_t = logic [__cfg.MemIslAxiMstIdWidth + $clog2(__cfg.MemIslWidePorts)-1:0]; \ + `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_mst, __prefix``addr_t, \ + __prefix``_axi_mst_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ + `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_slv, __prefix``addr_t, \ + __prefix``_axi_slv_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ + +// Note that the prefix does *not* include a leading underscore. +`define CHIMERA_TYPEDEF_ALL(__prefix, __cfg) \ + `CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(mem_isl_wide, __cfg) + +`endif diff --git a/sw/link/common.ldh b/sw/link/common.ldh new file mode 100644 index 0000000..4c3dac2 --- /dev/null +++ b/sw/link/common.ldh @@ -0,0 +1,55 @@ +/* Copyright 2022 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* Nicole Narr */ +/* Christopher Reinwardt */ +/* Paul Scheffler */ + +/* This header defines symbols and rules universal to bare-metal execution */ + +ENTRY(_start) + +MEMORY { + bootrom (rx) : ORIGIN = 0x02000000, LENGTH = 16K + /* We assume at least 64 KiB SPM, same minus stack for ROMs. */ + /* If more SPM is available, CRT0 repoints the stack. */ + extrom (rx) : ORIGIN = 0x00000000, LENGTH = 48K + spm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + memisl (rwx) : ORIGIN = 0x18000000, LENGTH = 64K + /* We assume at least 8 MiB of DRAM (minimum for Linux). */ + dram (rwx) : ORIGIN = 0x80000000, LENGTH = 8M +} + +SECTIONS { + /* Keep binaries lean */ + /DISCARD/ : { *(.riscv.attributes) *(.comment) } + + /* Global and stack pointer */ + /* By default, keep the calling context (boot ROM) stack pointer */ + __global_pointer$ = ADDR(.misc) + SIZEOF(.misc) / 2; + __stack_pointer$ = 0; + + /* Further addresses */ + __base_dma = 0x01000000; + __base_bootrom = 0x02000000; + __base_clint = 0x02040000; + __base_axirt = 0x020C0000; + __base_axirtgrd = 0x020C1ffc; + __base_regs = 0x03000000; + __base_llc = 0x03001000; + __base_uart = 0x03002000; + __base_i2c = 0x03003000; + __base_spih = 0x03004000; + __base_gpio = 0x03005000; + __base_slink = 0x03006000; + __base_vga = 0x03007000; + __base_usb = 0x03008000; + __base_bus_err = 0x03009000; + __base_plic = 0x04000000; + __base_clic = 0x08000000; + __base_spm = ORIGIN(spm); + __base_dram = ORIGIN(dram); + __base_memisl = ORIGIN(memisl); + __stack_start = ORIGIN(memisl) + LENGTH(memisl); +} diff --git a/sw/link/memisl.ld b/sw/link/memisl.ld new file mode 100644 index 0000000..6dcf16c --- /dev/null +++ b/sw/link/memisl.ld @@ -0,0 +1,46 @@ +/* Copyright 2022 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/* Nicole Narr */ +/* Christopher Reinwardt */ +/* Paul Scheffler */ +/* Lorenzo Leone */ + + +INCLUDE common.ldh + +SECTIONS { + .text : { + *(.text._start) + *(.text) + *(.text.*) + } > memisl + + .misc : ALIGN(16) { + *(.rodata) + *(.rodata.*) + *(.data) + *(.data.*) + *(.srodata) + *(.srodata.*) + *(.sdata) + *(.sdata.*) + } > memisl + + . = ALIGN(32); + __bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } > memisl + . = ALIGN(32); + __bss_end = .; + + .bulk : ALIGN(16) { + *(.bulk) + *(.bulk.*) + } > memisl +}