From e225e7a1f086cdb49552ea2323a2a08bdf07eeec Mon Sep 17 00:00:00 2001 From: Lorenzo Leone Date: Wed, 25 Sep 2024 19:32:45 +0200 Subject: [PATCH] Integrate Memory Island into chimera Hw: Add memory island domain wrapper Sw: Add support to build chehsire bootrom for mem island integration --- Bender.lock | 2 +- Bender.yml | 7 +- Makefile | 1 + chimera.mk | 2 +- hw/chimera_memisland_domain.sv | 83 +++++++++++++++++++++++ hw/chimera_pkg.sv | 67 +++++++++++++----- hw/chimera_top_wrapper.sv | 98 ++++++++------------------- sw/sw.mk | 6 ++ target/sim/src/fixture_chimera_soc.sv | 10 +-- 9 files changed, 184 insertions(+), 92 deletions(-) create mode 100644 hw/chimera_memisland_domain.sv diff --git a/Bender.lock b/Bender.lock index 093a0b1..a3bb472 100644 --- a/Bender.lock +++ b/Bender.lock @@ -69,7 +69,7 @@ packages: - common_cells - register_interface cheshire: - revision: dca1909834d6294d1e189046edaa47efde3279f1 + revision: 222efeb8122d47b7794e880dd21078dabaf4e966 version: null source: Git: https://github.com/pulp-platform/cheshire.git diff --git a/Bender.yml b/Bender.yml index 33c0ca6..511e613 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,17 +6,21 @@ package: name: chimera authors: - "Moritz Scherer " + - "Lorenzo Leone " dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } - cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: dca1909834d6294d1e189046edaa47efde3279f1} + cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: 222efeb8122d47b7794e880dd21078dabaf4e966} snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225} common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } +export_include_dirs: + - hw/include + workspace: package_links: cheshire: cheshire @@ -31,6 +35,7 @@ sources: - hw/chimera_cluster_adapter.sv - hw/chimera_cluster.sv - hw/chimera_clu_domain.sv + - hw/chimera_memisland_domain.sv - hw/chimera_top_wrapper.sv - target: any(simulation, test) diff --git a/Makefile b/Makefile index c38ccb3..8befd56 100644 --- a/Makefile +++ b/Makefile @@ -16,6 +16,7 @@ SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster) IDMA_ROOT ?= $(shell $(BENDER) path idma) CHS_XLEN ?= 32 +CHS_MEMISL ?= 1 CHIM_HW_DIR ?= $(CHIM_ROOT)/hw CHIM_SW_DIR ?= $(CHIM_ROOT)/sw diff --git a/chimera.mk b/chimera.mk index e7ca428..c05014f 100644 --- a/chimera.mk +++ b/chimera.mk @@ -19,7 +19,7 @@ gen_idma_hw: .PHONY: chs-hw-init chs-hw-init: update_plic gen_idma_hw - make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) + make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_MEMISL=$(CHS_MEMISL) .PHONY: snitch-hw-init snitch-hw-init: diff --git a/hw/chimera_memisland_domain.sv b/hw/chimera_memisland_domain.sv new file mode 100644 index 0000000..0f4ae38 --- /dev/null +++ b/hw/chimera_memisland_domain.sv @@ -0,0 +1,83 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Lorenzo Leone + +module chimera_memisland_domain + import chimera_pkg::*; + import cheshire_pkg::*; +#( + parameter chimera_cfg_t Cfg = '0, + parameter int unsigned NumWideMst = '0, + parameter type axi_narrow_req_t = logic, + parameter type axi_narrow_rsp_t = logic, + parameter type axi_wide_req_t = logic, + parameter type axi_wide_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_narrow_req_t axi_narrow_req_i, + output axi_narrow_rsp_t axi_narrow_rsp_o, + input axi_wide_req_t [NumWideMst-1:0] axi_wide_req_i, + output axi_wide_rsp_t [NumWideMst-1:0] axi_wide_rsp_o +); + + // Define needed parameters + localparam axi_in_t AxiIn = gen_axi_in(Cfg.ChsCfg); // lleone: TODO: find a better solution + localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + localparam int unsigned WideSlaveIdWidth = $clog2(Cfg.MemIslWidePorts); + localparam int unsigned WideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; + + axi_narrow_req_t axi_memory_island_amo_req; + axi_narrow_rsp_t axi_memory_island_amo_rsp; + + axi_riscv_atomics_structs #( + .AxiAddrWidth(Cfg.ChsCfg.AddrWidth), + .AxiDataWidth(Cfg.ChsCfg.AxiDataWidth), + .AxiIdWidth(AxiSlvIdWidth), // lleone: TODO: solve issue wiyth declaration on top + .AxiUserWidth(Cfg.ChsCfg.AxiUserWidth), + .AxiMaxReadTxns(Cfg.ChsCfg.LlcMaxReadTxns), + .AxiMaxWriteTxns(Cfg.ChsCfg.LlcMaxWriteTxns), + .AxiUserAsId(1), + .AxiUserIdMsb(Cfg.ChsCfg.AxiUserAmoMsb), + .AxiUserIdLsb(Cfg.ChsCfg.AxiUserAmoLsb), + .RiscvWordWidth(riscv::XLEN), + .NAxiCuts(Cfg.ChsCfg.LlcAmoNumCuts), + .axi_req_t(axi_narrow_req_t), + .axi_rsp_t(axi_narrow_rsp_t) + ) i_memory_island_atomics ( + .clk_i (clk_i), + .rst_ni, + .axi_slv_req_i(axi_narrow_req_i), + .axi_slv_rsp_o(axi_narrow_rsp_o), + .axi_mst_req_o(axi_memory_island_amo_req), + .axi_mst_rsp_i(axi_memory_island_amo_rsp) + ); + + axi_memory_island_wrap #( + .AddrWidth(Cfg.ChsCfg.AddrWidth), + .NarrowDataWidth(Cfg.ChsCfg.AxiDataWidth), + .WideDataWidth(WideDataWidth), + .AxiNarrowIdWidth(AxiSlvIdWidth), // lleone: TODO: solve issue wiyth declaration on top + .AxiWideIdWidth(WideSlaveIdWidth), + .axi_narrow_req_t(axi_narrow_req_t), + .axi_narrow_rsp_t(axi_narrow_rsp_t), + .axi_wide_req_t(axi_wide_req_t), + .axi_wide_rsp_t(axi_wide_rsp_t), + .NumNarrowReq(Cfg.MemIslNarrowPorts), + .NumWideReq(Cfg.MemIslWidePorts), + .NumWideBanks(Cfg.MemIslNumWideBanks), + .NarrowExtraBF(1), + .WordsPerBank(Cfg.MemIslWordsPerBank) + ) i_memory_island ( + .clk_i (clk_i), + .rst_ni, + .axi_narrow_req_i(axi_memory_island_amo_req), + .axi_narrow_rsp_o(axi_memory_island_amo_rsp), + // SCHEREMO: TODO: Demux wide accesses to go over narrow ports iff address not in memory island range + .axi_wide_req_i (axi_wide_req_i), + .axi_wide_rsp_o (axi_wide_rsp_o) + ); + +endmodule : chimera_memisland_domain diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index a4526fe..b33159b 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -14,6 +14,11 @@ package chimera_pkg; localparam int ExtClusters = 5; localparam int ExtClustersBaseIdx = 0; + // Bit vector types for parameters. + //We limit range to keep parameters sane. + typedef bit [7:0] byte_bt; + typedef bit [63:0] doub_bt; + typedef bit [15:0] shrt_bt; typedef struct packed { logic [iomsb(ExtClusters):0] hasWideMasterPort; @@ -33,12 +38,21 @@ package chimera_pkg; return sum; endfunction + // Configuration struct for Chimer: it includes the Cheshire Cfg + typedef struct packed { + cheshire_cfg_t ChsCfg; + doub_bt MemIslRegionStart; + doub_bt MemIslRegionEnd; + aw_bt MemIslAxiMstIdWidth; + byte_bt MemIslNarrowToWideFactor; + byte_bt MemIslNarrowPorts; + byte_bt MemIslWidePorts; + byte_bt MemIslNumWideBanks; + shrt_bt MemIslWordsPerBank; + } chimera_cfg_t; localparam int ExtCores = _sumVector(ChimeraClusterCfg.NrCores, ExtClusters); - // Memory Island - localparam int MemIslandIdx = ExtClustersBaseIdx + ExtClusters; - // SoC Config localparam bit SnitchBootROM = 1; localparam bit TopLevelCfgRegs = 1; @@ -61,12 +75,25 @@ package chimera_pkg; localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000; localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000; + // Parameters for Memory Island + localparam int MemIslandIdx = ExtClustersBaseIdx + ExtClusters; + + localparam doub_bt MemIslRegionStart = 64'h1800_0000; + localparam doub_bt MemIslRegionEnd = 64'h1804_0000; + localparam aw_bt MemIslAxiMstIdWidth = 1; + localparam byte_bt MemIslNarrowToWideFactor = 4; + localparam byte_bt MemIslNarrowPorts = 1; + localparam byte_bt MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); + localparam byte_bt MemIslNumWideBanks = 2; + localparam shrt_bt MemIslWordsPerBank = 1024; localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; - function automatic cheshire_cfg_t gen_chimera_cfg(); + function automatic chimera_cfg_t gen_chimera_cfg(); localparam int AddrWidth = DefaultCfg.AddrWidth; + localparam int MemoryIsland = 1; + chimera_cfg_t chimera_cfg; cheshire_cfg_t cfg = DefaultCfg; // Global CFG @@ -76,35 +103,30 @@ package chimera_pkg; cfg.Vga = 0; cfg.SerialLink = 0; - cfg.MemoryIsland = 1; // SCHEREMO: Fully remove LLC cfg.LlcNotBypass = 0; cfg.LlcOutConnect = 0; // AXI CFG cfg.AxiMstIdWidth = 2; - cfg.MemIslAxiMstIdWidth = 1; cfg.AxiDataWidth = 32; cfg.AddrWidth = 32; cfg.LlcOutRegionEnd = 'hFFFF_FFFF; - cfg.MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.MemIslNarrowToWideFactor = 4; - cfg.AxiExtNumWideMst = $countones(ChimeraClusterCfg.hasWideMasterPort); // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow cfg.AxiExtNumMst = ExtClusters + $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.AxiExtNumSlv = ExtClusters + cfg.MemoryIsland; - cfg.AxiExtNumRules = ExtClusters + cfg.MemoryIsland; + cfg.AxiExtNumSlv = ExtClusters + MemoryIsland; + cfg.AxiExtNumRules = ExtClusters + MemoryIsland; // lleone: TODO: Use index 0 for memory island cfg.AxiExtRegionIdx = {8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0}; cfg.AxiExtRegionStart = { - 64'h1800_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000 + MemIslRegionStart, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000 }; cfg.AxiExtRegionEnd = { - 64'h1804_0000, 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 + MemIslRegionEnd, 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 }; // REG CFG @@ -121,16 +143,29 @@ package chimera_pkg; cfg.NumExtDbgHarts = ExtCores; cfg.NumExtOutIntrTgts = ExtCores; - return cfg; + chimera_cfg = '{ + ChsCfg : cfg, + MemIslRegionStart : MemIslRegionStart, + MemIslRegionEnd : MemIslRegionEnd, + MemIslAxiMstIdWidth : MemIslAxiMstIdWidth, + MemIslNarrowToWideFactor : MemIslNarrowToWideFactor, + MemIslNarrowPorts : MemIslNarrowPorts, + MemIslWidePorts : MemIslWidePorts, + MemIslNumWideBanks : MemIslNumWideBanks, + MemIslWordsPerBank : MemIslWordsPerBank, + default: '0 + }; + + return chimera_cfg; endfunction : gen_chimera_cfg localparam int NumCfgs = 1; - localparam cheshire_cfg_t [NumCfgs-1:0] ChimeraCfg = {gen_chimera_cfg()}; + localparam chimera_cfg_t [NumCfgs-1:0] ChimeraCfg = {gen_chimera_cfg()}; // To move into cheshire TYPEDEF localparam int unsigned RegDataWidth = 32; - localparam type addr_t = logic [ChimeraCfg[0].AddrWidth-1:0]; + localparam type addr_t = logic [ChimeraCfg[0].ChsCfg.AddrWidth-1:0]; localparam type data_t = logic [RegDataWidth-1:0]; localparam type strb_t = logic [RegDataWidth/8-1:0]; diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index 1494255..92aedf3 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -62,15 +62,14 @@ module chimera_top_wrapper `include "common_cells/registers.svh" `include "common_cells/assertions.svh" `include "cheshire/typedef.svh" + `include "chimera/typedef.svh" // Cheshire config - localparam cheshire_cfg_t Cfg = ChimeraCfg[SelectedCfg]; - `CHESHIRE_TYPEDEF_ALL(, Cfg) + localparam chimera_cfg_t Cfg = ChimeraCfg[SelectedCfg]; + localparam cheshire_cfg_t ChsCfg = Cfg.ChsCfg; - // Define needed parameters - localparam axi_in_t AxiIn = gen_axi_in(Cfg); // lleone: TODO: find a better solution - localparam int unsigned AxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in); - localparam int unsigned WideSlaveIdWidth = $clog2(Cfg.MemIslWidePorts); + `CHESHIRE_TYPEDEF_ALL(, ChsCfg) + `CHIMERA_TYPEDEF_ALL(, Cfg) localparam type axi_wide_mst_req_t = mem_isl_wide_axi_mst_req_t; localparam type axi_wide_mst_rsp_t = mem_isl_wide_axi_mst_rsp_t; @@ -80,37 +79,37 @@ module chimera_top_wrapper chimera_reg2hw_t reg2hw; // External AXI crossbar ports - axi_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_mst_req; - axi_mst_rsp_t [iomsb(Cfg.AxiExtNumMst):0] axi_mst_rsp; - axi_wide_mst_req_t [iomsb(Cfg.AxiExtNumWideMst):0] axi_wide_mst_req; - axi_wide_mst_rsp_t [iomsb(Cfg.AxiExtNumWideMst):0] axi_wide_mst_rsp; - axi_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_slv_req; - axi_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_slv_rsp; + axi_mst_req_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_req; + axi_mst_rsp_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_rsp; + axi_wide_mst_req_t [iomsb(ChsCfg.AxiExtNumWideMst):0] axi_wide_mst_req; + axi_wide_mst_rsp_t [iomsb(ChsCfg.AxiExtNumWideMst):0] axi_wide_mst_rsp; + axi_slv_req_t [iomsb(ChsCfg.AxiExtNumSlv):0] axi_slv_req; + axi_slv_rsp_t [iomsb(ChsCfg.AxiExtNumSlv):0] axi_slv_rsp; // External reg demux slaves - reg_req_t [iomsb(Cfg.RegExtNumSlv):0] reg_slv_req; - reg_rsp_t [iomsb(Cfg.RegExtNumSlv):0] reg_slv_rsp; + reg_req_t [iomsb(ChsCfg.RegExtNumSlv):0] reg_slv_req; + reg_rsp_t [iomsb(ChsCfg.RegExtNumSlv):0] reg_slv_rsp; // Interrupts from and to clusters - logic [iomsb(Cfg.NumExtInIntrs):0] intr_ext_in; - logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_out; + logic [iomsb(ChsCfg.NumExtInIntrs):0] intr_ext_in; + logic [iomsb(ChsCfg.NumExtOutIntrTgts):0][iomsb(ChsCfg.NumExtOutIntrs):0] intr_ext_out; // Interrupt requests to cluster cores - logic [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_ext; - logic [iomsb(Cfg.NumExtIrqHarts):0] mtip_ext; - logic [iomsb(Cfg.NumExtIrqHarts):0] msip_ext; + logic [iomsb(NumIrqCtxts*ChsCfg.NumExtIrqHarts):0] xeip_ext; + logic [iomsb(ChsCfg.NumExtIrqHarts):0] mtip_ext; + logic [iomsb(ChsCfg.NumExtIrqHarts):0] msip_ext; // Debug interface to cluster cores logic dbg_active; - logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_req; - logic [iomsb(Cfg.NumExtDbgHarts):0] dbg_ext_unavail; + logic [iomsb(ChsCfg.NumExtDbgHarts):0] dbg_ext_req; + logic [iomsb(ChsCfg.NumExtDbgHarts):0] dbg_ext_unavail; // --------------------------------------- // | Cheshire SoC | // --------------------------------------- cheshire_soc #( - .Cfg (Cfg), + .Cfg (ChsCfg), .ExtHartinfo ('0), .axi_ext_llc_req_t(axi_mst_req_t), .axi_ext_llc_rsp_t(axi_mst_rsp_t), @@ -320,7 +319,7 @@ module chimera_top_wrapper // | Clusters Domain | // --------------------------------------- chimera_clu_domain #( - .Cfg (Cfg), + .Cfg (ChsCfg), .narrow_in_req_t (axi_slv_req_t), .narrow_in_resp_t (axi_slv_rsp_t), .narrow_out_req_t (axi_mst_req_t), @@ -348,57 +347,18 @@ module chimera_top_wrapper // --------------------------------------- // | Memory Island | // --------------------------------------- - localparam int WideDataWidth = Cfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor; - - axi_slv_req_t axi_memory_island_amo_req; - axi_slv_rsp_t axi_memory_island_amo_rsp; - - // Shim atomics, which are not supported by LLC - // TODO: This should be a filter, but how do we filter RISC-V atomics? - axi_riscv_atomics_structs #( - .AxiAddrWidth (Cfg.AddrWidth), - .AxiDataWidth (Cfg.AxiDataWidth), - .AxiIdWidth (AxiSlvIdWidth), // lleone: TODO: solve issue wiyth declaration on top - .AxiUserWidth (Cfg.AxiUserWidth), - .AxiMaxReadTxns (Cfg.LlcMaxReadTxns), - .AxiMaxWriteTxns(Cfg.LlcMaxWriteTxns), - .AxiUserAsId (1), - .AxiUserIdMsb (Cfg.AxiUserAmoMsb), - .AxiUserIdLsb (Cfg.AxiUserAmoLsb), - .RiscvWordWidth (riscv::XLEN), - .NAxiCuts (Cfg.LlcAmoNumCuts), - .axi_req_t (axi_slv_req_t), - .axi_rsp_t (axi_slv_rsp_t) - ) i_memory_island_atomics ( - .clk_i (soc_clk_i), - .rst_ni, - .axi_slv_req_i(axi_slv_req[MemIslandIdx]), - .axi_slv_rsp_o(axi_slv_rsp[MemIslandIdx]), - .axi_mst_req_o(axi_memory_island_amo_req), - .axi_mst_rsp_i(axi_memory_island_amo_rsp) - ); - axi_memory_island_wrap #( - .AddrWidth(Cfg.AddrWidth), - .NarrowDataWidth(Cfg.AxiDataWidth), - .WideDataWidth(WideDataWidth), - .AxiNarrowIdWidth(AxiSlvIdWidth), // lleone: TODO: solve issue wiyth declaration on top - .AxiWideIdWidth(WideSlaveIdWidth), + chimera_memisland_domain #( + .Cfg (Cfg), .axi_narrow_req_t(axi_slv_req_t), .axi_narrow_rsp_t(axi_slv_rsp_t), - .axi_wide_req_t(axi_wide_mst_req_t), - .axi_wide_rsp_t(axi_wide_mst_rsp_t), - .NumNarrowReq(Cfg.MemIslNarrowPorts), - .NumWideReq(Cfg.MemIslWidePorts), - .NumWideBanks(Cfg.MemIslNumWideBanks), - .NarrowExtraBF(1), - .WordsPerBank(Cfg.MemIslWordsPerBank) - ) i_memory_island ( + .axi_wide_req_t (axi_wide_mst_req_t), + .axi_wide_rsp_t (axi_wide_mst_rsp_t) + ) i_memisland_domain ( .clk_i (soc_clk_i), .rst_ni, - .axi_narrow_req_i(axi_memory_island_amo_req), - .axi_narrow_rsp_o(axi_memory_island_amo_rsp), - // SCHEREMO: TODO: Demux wide accesses to go over narrow ports iff address not in memory island range + .axi_narrow_req_i(axi_slv_req[MemIslandIdx]), + .axi_narrow_rsp_o(axi_slv_rsp[MemIslandIdx]), .axi_wide_req_i (axi_wide_mst_req), .axi_wide_rsp_o (axi_wide_mst_rsp) ); diff --git a/sw/sw.mk b/sw/sw.mk index 2979756..7d0ba1c 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -8,7 +8,13 @@ ifndef chim_sw_mk chim_sw_mk=1 CHS_SW_INCLUDES += -I$(CHIM_SW_DIR)/include + + +# SCHEREMO: use im for platform-level SW, as the smallest common denominator between CVA6 and the Snitch cluster. +# CVA6's bootrom however needs imc, so override that for this specific case. CHS_SW_FLAGS += -falign-functions=64 -march=rv32im +CHS_BROM_FLAGS += -march=rv32imc + CHS_SW_LDFLAGS += -L$(CHIM_SW_DIR)/lib CHIM_SW_LIB_SRCS_C = $(wildcard $(CHIM_SW_DIR)/lib/*.c $(CHIM_SW_DIR)/lib/**/*.c) diff --git a/target/sim/src/fixture_chimera_soc.sv b/target/sim/src/fixture_chimera_soc.sv index 7f50aaf..6b7afaf 100644 --- a/target/sim/src/fixture_chimera_soc.sv +++ b/target/sim/src/fixture_chimera_soc.sv @@ -13,15 +13,17 @@ module fixture_chimera_soc #( ); `include "cheshire/typedef.svh" + `include "chimera/typedef.svh" import cheshire_pkg::*; import tb_cheshire_pkg::*; import chimera_pkg::*; - localparam cheshire_cfg_t DutCfg = ChimeraCfg[SelectedCfg]; - - `CHESHIRE_TYPEDEF_ALL(, DutCfg) + localparam chimera_cfg_t DutCfg = ChimeraCfg[SelectedCfg]; + localparam cheshire_cfg_t ChsCfg = DutCfg.ChsCfg; + `CHESHIRE_TYPEDEF_ALL(, ChsCfg) + `CHIMERA_TYPEDEF_ALL(, DutCfg) /////////// // DUT // @@ -117,7 +119,7 @@ module fixture_chimera_soc #( /////////// vip_chimera_soc #( - .DutCfg (DutCfg), + .DutCfg (ChsCfg), .axi_ext_mst_req_t(axi_mst_req_t), .axi_ext_mst_rsp_t(axi_mst_rsp_t) ) vip (