diff --git a/Bender.lock b/Bender.lock index 0178d60..57cc107 100644 --- a/Bender.lock +++ b/Bender.lock @@ -186,7 +186,7 @@ packages: - common_cells - register_interface memory_island: - revision: 64828cb7a9ccc1f1656ec92d06129072f445c319 + revision: db228c506bf9a321aa6f4e3f9ef2b3084ba518ff version: null source: Git: https://github.com/pulp-platform/memory_island.git diff --git a/Bender.yml b/Bender.yml index 3f15ea3..cf334ac 100644 --- a/Bender.yml +++ b/Bender.yml @@ -15,7 +15,7 @@ dependencies: snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225} common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} - memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch + memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: lleone/pmu } # main branch apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } export_include_dirs: diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index 83943e3..6aa68fe 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -26,6 +26,7 @@ module chimera_clu_domain input logic soc_clk_i, input logic [ ExtClusters-1:0] clu_clk_i, input logic [ ExtClusters-1:0] rst_sync_ni, + input logic rst_ni, input logic [ ExtClusters-1:0] widemem_bypass_i, //----------------------------- // Interrupt ports @@ -90,7 +91,7 @@ module chimera_clu_domain .axi_resp_t (narrow_in_resp_t) ) i_iso_narrow_in_cluster ( .clk_i (soc_clk_i), - .rst_ni (rst_sync_ni[extClusterIdx]), + .rst_ni, .slv_req_i (narrow_in_req_i[extClusterIdx]), .slv_resp_o(narrow_in_resp_o[extClusterIdx]), .mst_req_o (narrow_in_isolated_req[extClusterIdx]), @@ -118,7 +119,7 @@ module chimera_clu_domain .axi_resp_t (narrow_out_resp_t) ) i_iso_narrow_out_cluster ( .clk_i (soc_clk_i), - .rst_ni (rst_sync_ni[extClusterIdx]), + .rst_ni, .slv_req_i (narrow_out_isolated_req[narrowOutIdx]), .slv_resp_o(narrow_out_isolated_resp[narrowOutIdx]), .mst_req_o (narrow_out_req_o[narrowOutIdx]), @@ -141,7 +142,7 @@ module chimera_clu_domain .axi_resp_t (wide_out_resp_t) ) i_iso_wide_cluster ( .clk_i (soc_clk_i), - .rst_ni (rst_sync_ni[extClusterIdx]), + .rst_ni, .slv_req_i (wide_out_isolated_req[extClusterIdx]), .slv_resp_o(wide_out_isolated_resp[extClusterIdx]), .mst_req_o (wide_out_req_o[extClusterIdx]), @@ -194,13 +195,13 @@ module chimera_clu_domain .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[extClusterIdx][Cfg.ChsCfg.AddrWidth-1:0]), .boot_addr_i (SnitchBootROMRegionStart[31:0]), - .narrow_in_req_i (narrow_in_isolated_req[extClusterIdx]), - .narrow_in_resp_o (narrow_in_isolated_resp[extClusterIdx]), - .narrow_out_req_o (narrow_out_isolated_req[2*extClusterIdx+:2]), - .narrow_out_resp_i(narrow_out_isolated_resp[2*extClusterIdx+:2]), + .narrow_in_req_i (narrow_in_isolated_req[extClusterIdx]), + .narrow_in_resp_flat_o(narrow_in_isolated_resp[extClusterIdx]), + .narrow_out_req_flat_o(narrow_out_isolated_req[2*extClusterIdx+:2]), + .narrow_out_resp_i (narrow_out_isolated_resp[2*extClusterIdx+:2]), - .wide_out_req_o (wide_out_isolated_req[extClusterIdx]), - .wide_out_resp_i(wide_out_isolated_resp[extClusterIdx]) + .wide_out_req_flat_o(wide_out_isolated_req[extClusterIdx]), + .wide_out_resp_i (wide_out_isolated_resp[extClusterIdx]) ); end : gen_clusters diff --git a/hw/chimera_cluster.sv b/hw/chimera_cluster.sv index ba45bc2..b2a10a6 100644 --- a/hw/chimera_cluster.sv +++ b/hw/chimera_cluster.sv @@ -17,48 +17,72 @@ module chimera_cluster parameter type narrow_out_req_t = logic, parameter type narrow_out_resp_t = logic, parameter type wide_out_req_t = logic, - parameter type wide_out_resp_t = logic + parameter type wide_out_resp_t = logic, + + // !! DO NOT OVERWRITE THESE PARAMETERS + // These parameters are used to provide a flattened interface for the AXI ports (see comments below). + parameter type narrow_in_resp_flat_t = logic [$bits(narrow_in_resp_t)-1:0], + parameter type narrow_out_req_flat_t = logic [$bits(narrow_out_req_t)-1:0], + parameter type wide_out_req_flat_t = logic [ $bits(wide_out_req_t)-1:0] ) ( - input logic soc_clk_i, - input logic clu_clk_i, - input logic rst_ni, - input logic widemem_bypass_i, + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic widemem_bypass_i, //----------------------------- // Interrupt ports //----------------------------- - input logic [ NrCores-1:0] debug_req_i, - input logic [ NrCores-1:0] meip_i, - input logic [ NrCores-1:0] mtip_i, - input logic [ NrCores-1:0] msip_i, + input logic [ NrCores-1:0] debug_req_i, + input logic [ NrCores-1:0] meip_i, + input logic [ NrCores-1:0] mtip_i, + input logic [ NrCores-1:0] msip_i, //----------------------------- // Cluster base addressing //----------------------------- - input logic [ 9:0] hart_base_id_i, - input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, - input logic [ 31:0] boot_addr_i, + input logic [ 9:0] hart_base_id_i, + input logic [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i, + input logic [ 31:0] boot_addr_i, //----------------------------- // Narrow AXI ports //----------------------------- - input narrow_in_req_t narrow_in_req_i, - output narrow_in_resp_t narrow_in_resp_o, - output narrow_out_req_t [ 1:0] narrow_out_req_o, - input narrow_out_resp_t [ 1:0] narrow_out_resp_i, + input narrow_in_req_t narrow_in_req_i, + output narrow_in_resp_flat_t narrow_in_resp_flat_o, + output narrow_out_req_flat_t [ 1:0] narrow_out_req_flat_o, + input narrow_out_resp_t [ 1:0] narrow_out_resp_i, //----------------------------- //Wide AXI ports //----------------------------- - output wide_out_req_t wide_out_req_o, - input wide_out_resp_t wide_out_resp_i + output wide_out_req_flat_t wide_out_req_flat_o, + input wide_out_resp_t wide_out_resp_i ); `include "axi/typedef.svh" - localparam int WideDataWidth = $bits(wide_out_req_o.w.data); - - localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id); + /* ------------------------------------------------------------------------------- */ + /* Flattened interface signals for UPF structure workaround */ + /* ------------------------------------------------------------------------------- */ + // + // The UPF standard supported by QuestaSim cannot apply isolation strategies to + // ports with "complex" types, such as AXI ports, which are structures. + // To address this issue, at the interface of each power domain, signals are flattened + // (e.g., narrow_in_resp_flat_o) and then internally reassigned to new structured signals + // (e.g., narrow_in_resp_s), which can be propagated to downstream modules. + // + narrow_out_req_t [1:0] narrow_out_req_s; + narrow_in_resp_t narrow_in_resp_s; + wide_out_req_t wide_out_req_s; + + assign narrow_out_req_flat_o = narrow_out_req_s; + assign narrow_in_resp_flat_o = narrow_in_resp_s; + assign wide_out_req_flat_o = wide_out_req_s; + + localparam int WideDataWidth = $bits(wide_out_req_s.w.data); + + localparam int WideMasterIdWidth = $bits(wide_out_req_s.aw.id); localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1; localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id); - localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id); + localparam int NarrowMasterIdWidth = $bits(narrow_out_req_s[0].aw.id); typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t; typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t; @@ -140,8 +164,8 @@ module chimera_cluster // SoC side narrow. .narrow_in_req_i (narrow_in_req_i), - .narrow_in_resp_o (narrow_in_resp_o), - .narrow_out_req_o (narrow_out_req_o), + .narrow_in_resp_o (narrow_in_resp_s), + .narrow_out_req_o (narrow_out_req_s), .narrow_out_resp_i(narrow_out_resp_i), // Cluster side narrow @@ -155,8 +179,8 @@ module chimera_cluster end else begin : gen_skip_narrow_adapter // if (ClusterDataWidth != Cfg.AxiDataWidth) assign clu_axi_narrow_slv_req = narrow_in_req_i; - assign narrow_in_resp_o = clu_axi_narrow_slv_rsp; - assign narrow_out_req_o = clu_axi_narrow_mst_req; + assign narrow_in_resp_s = clu_axi_narrow_slv_rsp; + assign narrow_out_req_s = clu_axi_narrow_mst_req; assign clu_axi_narrow_mst_rsp = narrow_out_resp_i; end @@ -196,7 +220,7 @@ module chimera_cluster .clu_narrow_out_req_i (clu_axi_adapter_mst_req), .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), - .wide_out_req_o (wide_out_req_o), + .wide_out_req_o (wide_out_req_s), .wide_out_resp_i (wide_out_resp_i), .clu_wide_out_req_i (clu_axi_wide_mst_req), .clu_wide_out_resp_o(clu_axi_wide_mst_resp), diff --git a/hw/chimera_memisland_domain.sv b/hw/chimera_memisland_domain.sv index 0f4ae38..f28d343 100644 --- a/hw/chimera_memisland_domain.sv +++ b/hw/chimera_memisland_domain.sv @@ -15,12 +15,13 @@ module chimera_memisland_domain parameter type axi_wide_req_t = logic, parameter type axi_wide_rsp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input axi_narrow_req_t axi_narrow_req_i, - output axi_narrow_rsp_t axi_narrow_rsp_o, - input axi_wide_req_t [NumWideMst-1:0] axi_wide_req_i, - output axi_wide_rsp_t [NumWideMst-1:0] axi_wide_rsp_o + input logic clk_i, + input logic rst_ni, + input logic [Cfg.MemIslNumWideBanks-1:0] rst_sync_ni, + input axi_narrow_req_t axi_narrow_req_i, + output axi_narrow_rsp_t axi_narrow_rsp_o, + input axi_wide_req_t [ NumWideMst-1:0] axi_wide_req_i, + output axi_wide_rsp_t [ NumWideMst-1:0] axi_wide_rsp_o ); // Define needed parameters @@ -73,6 +74,7 @@ module chimera_memisland_domain ) i_memory_island ( .clk_i (clk_i), .rst_ni, + .rst_sync_ni (rst_sync_ni), .axi_narrow_req_i(axi_memory_island_amo_req), .axi_narrow_rsp_o(axi_memory_island_amo_rsp), // SCHEREMO: TODO: Demux wide accesses to go over narrow ports iff address not in memory island range diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index 3e237e0..53571a7 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -11,56 +11,62 @@ module chimera_top_wrapper #( parameter int unsigned SelectedCfg = 0 ) ( - input logic soc_clk_i, - input logic clu_clk_i, - input logic rst_ni, - input logic test_mode_i, - input logic [ 1:0] boot_mode_i, - input logic rtc_i, + input logic soc_clk_i, + input logic clu_clk_i, + input logic rst_ni, + input logic test_mode_i, + input logic [ 1:0] boot_mode_i, + input logic rtc_i, // JTAG interface - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - output logic jtag_tdo_oe_o, + input logic jtag_tck_i, + input logic jtag_trst_ni, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o, + output logic jtag_tdo_oe_o, // UART interface - output logic uart_tx_o, - input logic uart_rx_i, + output logic uart_tx_o, + input logic uart_rx_i, // UART modem flow control - output logic uart_rts_no, - output logic uart_dtr_no, - input logic uart_cts_ni, - input logic uart_dsr_ni, - input logic uart_dcd_ni, - input logic uart_rin_ni, + output logic uart_rts_no, + output logic uart_dtr_no, + input logic uart_cts_ni, + input logic uart_dsr_ni, + input logic uart_dcd_ni, + input logic uart_rin_ni, // I2C interface - output logic i2c_sda_o, - input logic i2c_sda_i, - output logic i2c_sda_en_o, - output logic i2c_scl_o, - input logic i2c_scl_i, - output logic i2c_scl_en_o, + output logic i2c_sda_o, + input logic i2c_sda_i, + output logic i2c_sda_en_o, + output logic i2c_scl_o, + input logic i2c_scl_i, + output logic i2c_scl_en_o, // SPI host interface - output logic spih_sck_o, - output logic spih_sck_en_o, - output logic [ SpihNumCs-1:0] spih_csb_o, - output logic [ SpihNumCs-1:0] spih_csb_en_o, - output logic [ 3:0] spih_sd_o, - output logic [ 3:0] spih_sd_en_o, - input logic [ 3:0] spih_sd_i, + output logic spih_sck_o, + output logic spih_sck_en_o, + output logic [ SpihNumCs-1:0] spih_csb_o, + output logic [ SpihNumCs-1:0] spih_csb_en_o, + output logic [ 3:0] spih_sd_o, + output logic [ 3:0] spih_sd_en_o, + input logic [ 3:0] spih_sd_i, // GPIO interface - input logic [ 31:0] gpio_i, - output logic [ 31:0] gpio_o, - output logic [ 31:0] gpio_en_o, + input logic [ 31:0] gpio_i, + output logic [ 31:0] gpio_o, + output logic [ 31:0] gpio_en_o, // APB interface - input apb_resp_t apb_rsp_i, - output apb_req_t apb_req_o, + input apb_resp_t apb_rsp_i, + output apb_req_t apb_req_o, // PMU Clusters control signals - input logic [ExtClusters-1:0] pmu_rst_clusters_ni, - input logic [ExtClusters-1:0] pmu_clkgate_en_clusters_i, // TODO: lleone - input logic [ExtClusters-1:0] pmu_iso_en_clusters_i, - output logic [ExtClusters-1:0] pmu_iso_ack_clusters_o + input logic [ ExtClusters-1:0] pmu_rst_clusters_ni, + input logic [ ExtClusters-1:0] pmu_clkgate_en_clusters_i, // TODO: lleone + input logic [ ExtClusters-1:0] pmu_iso_en_clusters_i, + output logic [ ExtClusters-1:0] pmu_iso_ack_clusters_o, + // PMU Memory Island control signals + input logic [MemIslNumWideBanks-1:0] pmu_rst_memisland_ni, + input logic [MemIslNumWideBanks-1:0] pmu_clkgate_en_memisland_i, // TODO: lleone + input logic [MemIslNumWideBanks-1:0] pmu_iso_en_memisland_i, + output logic [MemIslNumWideBanks-1:0] pmu_iso_ack_memisland_o + ); @@ -335,6 +341,7 @@ module chimera_top_wrapper .soc_clk_i (soc_clk_i), .clu_clk_i (clu_clk_gated), .rst_sync_ni (pmu_rst_clusters_ni), + .rst_ni, .widemem_bypass_i (wide_mem_bypass_mode), .debug_req_i (dbg_ext_req), .xeip_i (xeip_ext), @@ -364,6 +371,7 @@ module chimera_top_wrapper ) i_memisland_domain ( .clk_i (soc_clk_i), .rst_ni, + .rst_sync_ni (pmu_rst_memisland_ni), .axi_narrow_req_i(axi_slv_req[MemIslandIdx]), .axi_narrow_rsp_o(axi_slv_rsp[MemIslandIdx]), .axi_wide_req_i (axi_wide_mst_req), diff --git a/target/sim/src/fixture_chimera_soc.sv b/target/sim/src/fixture_chimera_soc.sv index e2ec0d1..4065937 100644 --- a/target/sim/src/fixture_chimera_soc.sv +++ b/target/sim/src/fixture_chimera_soc.sv @@ -63,46 +63,51 @@ module fixture_chimera_soc #( chimera_top_wrapper #( .SelectedCfg(SelectedCfg) ) dut ( - .soc_clk_i (soc_clk), - .clu_clk_i (clu_clk), - .rst_ni (rst_n), - .test_mode_i (test_mode), - .boot_mode_i (boot_mode), - .rtc_i (rtc), - .jtag_tck_i (jtag_tck), - .jtag_trst_ni (jtag_trst_n), - .jtag_tms_i (jtag_tms), - .jtag_tdi_i (jtag_tdi), - .jtag_tdo_o (jtag_tdo), - .jtag_tdo_oe_o (), - .uart_tx_o (uart_tx), - .uart_rx_i (uart_rx), - .uart_rts_no (), - .uart_dtr_no (), - .uart_cts_ni (1'b0), - .uart_dsr_ni (1'b0), - .uart_dcd_ni (1'b0), - .uart_rin_ni (1'b0), - .i2c_sda_o (i2c_sda_o), - .i2c_sda_i (i2c_sda_i), - .i2c_sda_en_o (i2c_sda_en), - .i2c_scl_o (i2c_scl_o), - .i2c_scl_i (i2c_scl_i), - .i2c_scl_en_o (i2c_scl_en), - .spih_sck_o (spih_sck_o), - .spih_sck_en_o (spih_sck_en), - .spih_csb_o (spih_csb_o), - .spih_csb_en_o (spih_csb_en), - .spih_sd_o (spih_sd_o), - .spih_sd_en_o (spih_sd_en), - .spih_sd_i (spih_sd_i), - .gpio_i ('0), - .gpio_o (), - .gpio_en_o (), - .pmu_rst_clusters_ni ({ExtClusters{rst_n}}), - .pmu_clkgate_en_clusters_i(), - .pmu_iso_en_clusters_i ('0), // Never Isolate - .pmu_iso_ack_clusters_o () + .soc_clk_i (soc_clk), + .clu_clk_i (clu_clk), + .rst_ni (rst_n), + .test_mode_i (test_mode), + .boot_mode_i (boot_mode), + .rtc_i (rtc), + .jtag_tck_i (jtag_tck), + .jtag_trst_ni (jtag_trst_n), + .jtag_tms_i (jtag_tms), + .jtag_tdi_i (jtag_tdi), + .jtag_tdo_o (jtag_tdo), + .jtag_tdo_oe_o (), + .uart_tx_o (uart_tx), + .uart_rx_i (uart_rx), + .uart_rts_no (), + .uart_dtr_no (), + .uart_cts_ni (1'b0), + .uart_dsr_ni (1'b0), + .uart_dcd_ni (1'b0), + .uart_rin_ni (1'b0), + .i2c_sda_o (i2c_sda_o), + .i2c_sda_i (i2c_sda_i), + .i2c_sda_en_o (i2c_sda_en), + .i2c_scl_o (i2c_scl_o), + .i2c_scl_i (i2c_scl_i), + .i2c_scl_en_o (i2c_scl_en), + .spih_sck_o (spih_sck_o), + .spih_sck_en_o (spih_sck_en), + .spih_csb_o (spih_csb_o), + .spih_csb_en_o (spih_csb_en), + .spih_sd_o (spih_sd_o), + .spih_sd_en_o (spih_sd_en), + .spih_sd_i (spih_sd_i), + .gpio_i ('0), + .gpio_o (), + .gpio_en_o (), + .pmu_rst_clusters_ni ({ExtClusters{rst_n}}), + .pmu_clkgate_en_clusters_i (), + .pmu_iso_en_clusters_i ('0), // Never Isolate + .pmu_iso_ack_clusters_o (), + .pmu_rst_memisland_ni ({DutCfg.MemIslNumWideBanks{rst_n}}), + .pmu_clkgate_en_memisland_i(), + .pmu_iso_en_memisland_i ('0), // Never Isolate, + .pmu_iso_ack_memisland_o () + ); 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