From 46ecf0894d2de7d63ed4f6dd77d723a4d80b4c42 Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Tue, 27 Feb 2024 17:59:34 +0100 Subject: [PATCH] Various snitch-related fixes --- src/frontend/inst64/idma_inst64_top.sv | 72 +++++++++++++--------- src/future/idma_legalizer_page_splitter.sv | 2 +- src/midend/idma_nd_midend.sv | 2 +- 3 files changed, 46 insertions(+), 30 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index a67a4fdd..c950b201 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -49,7 +49,7 @@ module idma_inst64_top #( // constants localparam int unsigned TfIdWidth = 32'd32; - localparam int unsigned TFLenWidth = 32'd64; + localparam int unsigned TFLenWidth = AxiAddrWidth; localparam int unsigned RepWidth = 32'd32; localparam int unsigned NumDim = 32'd2; localparam int unsigned BufferDepth = 32'd3; @@ -116,10 +116,15 @@ module idma_inst64_top #( logic idma_nd_rsp_ready; // frontend - idma_nd_req_t idma_fe_req_d, idma_fe_req_q; + idma_nd_req_t idma_fe_req_d, idma_fe_req_q, idma_fe_req; logic idma_fe_req_valid; logic idma_fe_req_ready; + // frontend state + logic [1:0] idma_fe_cfg; + logic [1:0] idma_fe_status; + logic idma_fe_twod; + // busy signals idma_pkg::idma_busy_t idma_busy; logic idma_nd_busy; @@ -238,7 +243,7 @@ module idma_inst64_top #( .testmode_i, .flush_i ( 1'b0 ), .usage_o ( /* NC */ ), - .data_i ( idma_fe_req_q ), + .data_i ( idma_fe_req ), .valid_i ( idma_fe_req_valid ), .ready_o ( idma_fe_req_ready ), .data_o ( idma_nd_req ), @@ -261,6 +266,8 @@ module idma_inst64_top #( .completed_o ( completed_id ) ); + // we are always ready to accept responses + assign idma_nd_rsp_ready = 1'b1; assign issue_id = idma_nd_req_valid & idma_nd_req_ready; assign retire_id = idma_nd_rsp_valid & idma_nd_rsp_ready; @@ -334,6 +341,10 @@ module idma_inst64_top #( idma_fe_req_d.burst_req.opt.beo.dst_reduce_len = 1'b0; idma_fe_req_d.burst_req.opt.last = 1'b0; + // frontend config + idma_fe_cfg = '0; + idma_fe_status = '0; + // default handshaking idma_fe_req_valid = 1'b0; acc_req_ready_o = 1'b0; @@ -373,15 +384,13 @@ module idma_inst64_top #( // start the DMA idma_inst64_snitch_pkg::DMCPYI, idma_inst64_snitch_pkg::DMCPY : begin - // automatic logic [1:0] cfg; - // - // // Parse the transfer parameters from the register or immediate. - // cfg = '0; - // unique casez (acc_qdata_op_i) - // idma_inst64_snitch_pkg::DMCPYI : cfg = acc_qdata_op_i[24:20]; - // idma_inst64_snitch_pkg::DMCPY : cfg = acc_qdata_argb_i; - // default:; - // endcase + // Parse the transfer parameters from the register or immediate. + unique casez (acc_req_i.data_op) + idma_inst64_snitch_pkg::DMCPYI : idma_fe_cfg = acc_req_i.data_op[24:20]; + idma_inst64_snitch_pkg::DMCPY : idma_fe_cfg = acc_req_i.data_arga; + default:; + endcase + dma_op_name = "DMCPY"; is_dma_op = 1'b1; idma_fe_req_d.burst_req.length = acc_req_i.data_arga; @@ -407,28 +416,25 @@ module idma_inst64_top #( // status of the DMA idma_inst64_snitch_pkg::DMSTATI, idma_inst64_snitch_pkg::DMSTAT: begin - // automatic logic [1:0] status; - // // Parse the status index from the register or immediate. - // status = '0; - // unique casez (acc_qdata_op_i) - // idma_inst64_snitch_pkg::DMSTATI: status = acc_qdata_op_i[24:20]; - // idma_inst64_snitch_pkg::DMSTAT: status = acc_qdata_argb_i; - // default:; - // endcase + // Parse the status index from the register or immediate. + unique casez (acc_req_i.data_op) + idma_inst64_snitch_pkg::DMSTATI: idma_fe_status = acc_req_i.data_op[24:20]; + idma_inst64_snitch_pkg::DMSTAT: idma_fe_status = acc_req_i.data_arga; + default:; + endcase dma_op_name = "DMSTAT"; is_dma_op = 1'b1; // Compose the response acc_res.id = acc_req_i.id; acc_res.error = 1'b0; - acc_res.data = completed_id; - //case (status) - // 2'b00 : acc_pdata_spill.data = completed_id; - // 2'b01 : acc_pdata_spill.data = next_id; - // 2'b10 : acc_pdata_spill.data = {{{8'd63}{1'b0}}, dma_busy_o}; - // 2'b11 : acc_pdata_spill.data = {{{8'd63}{1'b0}}, !twod_req_ready}; - // default:; - //endcase + case (idma_fe_status) + 2'b00 : acc_res.data = completed_id; + 2'b01 : acc_res.data = next_id; + 2'b10 : acc_res.data = {{{8'd63}{1'b0}}, busy_o}; + 2'b11 : acc_res.data = {{{8'd63}{1'b0}}, !idma_fe_req_ready}; + default:; + endcase // Wait for acc response channel to become ready, then ack the // request. @@ -460,6 +466,16 @@ module idma_inst64_top #( end end + // twod handling + assign idma_fe_twod = idma_fe_cfg[1]; + always_comb begin : gen_twod_bypass + // default: pass-through + idma_fe_req = idma_fe_req_d; + if (!idma_fe_twod) begin + idma_fe_req.d_req[0].reps = 'd1; + end + end + //-------------------------------------- // State //-------------------------------------- diff --git a/src/future/idma_legalizer_page_splitter.sv b/src/future/idma_legalizer_page_splitter.sv index 9de74e3c..049c289a 100644 --- a/src/future/idma_legalizer_page_splitter.sv +++ b/src/future/idma_legalizer_page_splitter.sv @@ -36,7 +36,7 @@ module idma_legalizer_page_splitter #( // smaller chunks than the AXI page size? page_addr_width = OffsetWidth + (reduce_len_i ? max_llen_i : 'd8); // a page can be a maximum of 4kB (12 bit) - page_addr_width = page_addr_width > PageAddrWidth ? PageAddrWidth : page_addr_width; + page_addr_width = page_addr_width > 'd12 ? 'd12 : page_addr_width; end end diff --git a/src/midend/idma_nd_midend.sv b/src/midend/idma_nd_midend.sv index 63501fa0..86bfd461 100644 --- a/src/midend/idma_nd_midend.sv +++ b/src/midend/idma_nd_midend.sv @@ -118,7 +118,7 @@ module idma_nd_midend #( assign stage_clear[d-2] = &(stage_done[d-1:0]) & burst_req_ready_i; // size conversion - assign local_rep = nd_req_i.d_req[d-2].reps[RepWidth-1:0]; + assign local_rep = nd_req_valid_i ? nd_req_i.d_req[d-2].reps[RepWidth-1:0] : '0; // bypass if num iterations is 0, mark stage as 0 stage: always_comb begin : proc_zero_bypass