Bender.yml

# Copyright 2021 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

package:
  name: mempool

dependencies:
  axi:                  { git: "https://github.com/pulp-platform/axi.git",                  version: 0.39.2  }
  cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.2.1   }
  common_cells:         { git: "https://github.com/pulp-platform/common_cells.git",         version: 1.33.0  }
  idma:                 { path: "hardware/deps/idma"                                                         }
  register_interface:   { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.3   }
  reqrsp_interface:     { path: "hardware/deps/reqrsp_interface"                                             }
  snitch:               { path: "hardware/deps/snitch"                                                       }
  tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13  }
  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: pulp-v0.1.3 }
  cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }

workspace:
  checkout_dir: "./hardware/deps"

export_include_dirs:
  - hardware/include

sources:
  # Level 0
  - hardware/src/mempool_pkg.sv
  - hardware/src/axi_hier_interco.sv
  - hardware/src/mempool_cc.sv
  - hardware/src/snitch_addr_demux.sv
  - hardware/src/tcdm_adapter.sv
  - hardware/src/tcdm_shim.sv
  - hardware/src/tcdm_wide_narrow_mux.sv
  - hardware/src/address_scrambler.sv
  - hardware/src/axi2mem.sv
  - hardware/src/bootrom.sv
  - hardware/src/control_registers/control_registers_reg_pkg.sv
  - hardware/src/control_registers/control_registers_reg_top.sv
  # Level 1
  - hardware/src/mempool_tile.sv
  # Level 2
  - hardware/src/mempool_sub_group.sv
  # Level 3
  - hardware/src/mempool_group.sv
  # Level 4
  - hardware/src/mempool_cluster.sv
  # Level 5
  - hardware/src/ctrl_registers.sv
  # Level 6
  - hardware/src/mempool_system.sv

  - target: mempool_vsim
    files:
      # Level 0
      - hardware/src/mempool_pkg.sv
      # Level 1
      - hardware/tb/axi_uart.sv
      - hardware/tb/traffic_generator.sv
      # Level 2
      - hardware/tb/mempool_tb.sv
      # DRAMsys
      - hardware/deps/dram_rtl_sim/src/sim_dram.sv
      - hardware/deps/dram_rtl_sim/src/axi_dram_sim.sv
      - hardware/deps/dram_rtl_sim/src/dram_sim_engine.sv

  - target: mempool_verilator
    files:
      # Level 1
      - hardware/tb/axi_uart.sv
      - hardware/tb/traffic_generator.sv
      # Level 2
      - hardware/tb/mempool_tb_verilator.sv

  - target: fpga
    files:
      # Level 1
    - hardware/src/axi_rab_wrap.sv