From 0c8ec8a909946d72bdf3413f68b6753e15318959 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Wed, 21 Feb 2024 15:10:13 +0100 Subject: [PATCH] [readme] Add publications --- README.md | 178 +++++++++++++++++++++++++++++++----------------------- 1 file changed, 101 insertions(+), 77 deletions(-) diff --git a/README.md b/README.md index e615e61c5..a3d30874a 100644 --- a/README.md +++ b/README.md @@ -187,53 +187,6 @@ To get a visualization of the traces, check out the `scripts/tracevis.py` script We also provide Synopsys Spyglass linting scripts in the `hardware/spyglass`. Run `make lint` in the `hardware` folder, with a specific MemPool configuration, to run the tests associated with the `lint_rtl` target. -## License -MemPool is released under permissive open source licenses. Most of MemPool's source code is released under the Apache License 2.0 (`Apache-2.0`) see [`LICENSE`](LICENSE). The code in `hardware` is released under Solderpad v0.51 (`SHL-0.51`) see [`hardware/LICENSE`](hardware/LICENSE). - -Note, MemPool includes several third-party packages with their own licenses: - -
-Note, MemPool includes several third-party packages with their own licenses: -

- -### Software - -- `software/runtime/printf.{c,h}` is licensed under the MIT license. -- `software/runtime/omp/libgomp.h` is licensed under the GPL license. -- `software/riscv-tests` is an extended version of RISC-V's [riscv-tests](https://github.com/riscv/riscv-tests/) repository licensed under a BSD license. See [`software/riscv-tests/LICENSE`](software/riscv-tests/LICENSE) for details. - -### Hardware - -The `hardware` folder is licensed under Solderpad v0.51 see [`hardware/LICENSE`](hardware/LICENSE). We use the following exceptions: - -- `hardware/tb/dpi/elfloader.cpp` is licensed under a BSD license. -- `hardware/tb/verilator/*` is licensed under Apache License 2.0 see [`LICENSE`](LICENSE) -- `hardware/tb/verilator/lowrisc_*` contain modified versions of lowRISC's helper libraries. They are licensed under Apache License 2.0. - -### Scripts - -- `scripts/run_clang_format.py` is licensed under the MIT license. - -### Toolchains - -The following compilers can be used to build applications for MemPool: - -- `toolchain/halide` is licensed under the MIT license. See [Halide's license](https://github.com/halide/Halide/blob/master/LICENSE.txt) for details. -- `toolchain/llvm-project`is licensed under the Apache License v2.0 with LLVM Exceptions. See [LLVM's DeveloperPolicy](https://llvm.org/docs/DeveloperPolicy.html#new-llvm-project-license-framework) for more details. -- `toolchain/riscv-gnu-toolchain`'s licensing information is available [here](https://github.com/pulp-platform/pulp-riscv-gnu-toolchain/blob/master/LICENSE) - -We use the following RISC-V tools to parse simulation traces and keep opcodes consistent throughout the project. - -- `toolchain/riscv-isa-sim` is licensed under a BSD license. See [riscv-isa-sim's license](https://github.com/riscv/riscv-isa-sim/blob/master/LICENSE) for details. -- `toolchain/riscv-opcodes` contains an extended version of [riscv-opcodes](https://github.com/riscv/riscv-opcodes) licensed under the BSD license. See [`toolchain/riscv-opcodes/LICENSE`](toolchain/riscv-opcodes/LICENSE) for details. - -The open-source simulator [Verilator](https://www.veripool.org/verilator) can be used for RTL simulation. - -- `toolchain/verilator` is licensed under GPL. See [Verilator's license](https://github.com/verilator/verilator/blob/master/LICENSE) for more details. - -

-
- ## Publications If you use MemPool in your work or research, you can cite us: @@ -252,15 +205,15 @@ If you use MemPool in your work or research, you can cite us: doi = {10.1109/TC.2023.3307796} } ``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10227739) and is also available on [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000643341). -This paper is also available at arXiv, at the following link: [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742). The following publications give more details about MemPool, its extensions, and use cases: ### 2021
-MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect +MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect

``` @@ -276,15 +229,14 @@ The following publications give more details about MemPool, its extensions, and doi = {10.23919/DATE51398.2021.9474087} } ``` - -This paper is also available at arXiv, at the following link: [arXiv:2012.02973 [cs.AR]](https://arxiv.org/abs/2012.02973). +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9474087) and is also available on [arXiv:2012.02973 [cs.AR]](https://arxiv.org/abs/2012.02973).

-3D SoC integration, beyond 2.5D chiplets +3D SoC integration, beyond 2.5D chiplets

``` @@ -298,6 +250,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973 doi = {10.1109/IEDM19574.2021.9720614} } ``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9720614).

@@ -306,7 +259,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973 ### 2022
-MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration +MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration

``` @@ -322,15 +275,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973 doi = {10.23919/DATE54114.2022.9774726} } ``` - -This paper is also available at arXiv, at the following link: [arXiv:2112.01168 [cs.AR]](https://arxiv.org/abs/2112.01168). +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9774726) and is also available on [arXiv:2112.01168 [cs.AR]](https://arxiv.org/abs/2112.01168).

-Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs +Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs

``` @@ -345,13 +297,15 @@ This paper is also available at arXiv, at the following link: [arXiv:2112.01168 doi = {10.1145/3531437.3539702} } ``` +This paper was published on [ACM DL](https://dl.acm.org/doi/10.1145/3531437.3539702). +

-Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters +Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters

``` @@ -367,15 +321,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2112.01168 doi = {10.1145/3508352.3549367} } ``` - -This paper is also available at arXiv, at the following link: [arXiv:2207.07970 [cs.AR]](https://arxiv.org/abs/2207.07970). +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10069431) and is also available on [arXiv:2207.07970 [cs.AR]](https://arxiv.org/abs/2207.07970).

-Thermal Performance Analysis of Mempool RISC-V Multicore SoC +Thermal Performance Analysis of Mempool RISC-V Multicore SoC

``` @@ -391,6 +344,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970 doi = {10.1109/TVLSI.2022.3207553} } ``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9905665).

@@ -399,7 +353,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970 ### 2023
-Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs) +Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)

``` @@ -414,13 +368,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970 doi = {10.1109/IRPS48203.2023.10117979} } ``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10117979).

-Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor +Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor

``` @@ -436,15 +391,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970 doi = {10.23919/DATE56975.2023.10137247} } ``` - -This paper is also available at arXiv, at the following link: [arXiv:2210.09196 [cs.DC]](https://arxiv.org/abs/2210.09196). +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10137247) and is also available on [arXiv:2210.09196 [cs.DC]](https://arxiv.org/abs/2210.09196).

-MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster +MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster

``` @@ -460,13 +414,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2210.09196 doi = {10.23919/DATE56975.2023.10136909} } ``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10136909).

-Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster +Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster

``` @@ -483,15 +438,37 @@ This paper is also available at arXiv, at the following link: [arXiv:2210.09196 doi = {10.1007/978-3-031-46077-7_16} } ``` +This paper was published on [Springer Link](https://link.springer.com/chapter/10.1007/978-3-031-46077-7_16) and is also available on [arXiv:2307.10248 [cs.DC]](https://arxiv.org/abs/2307.10248) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000648454). + +

+
-This paper is also available at arXiv, at the following link: [arXiv:2307.10248 [cs.DC]](https://arxiv.org/abs/2307.10248). + +
+MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory +

+ +``` +@article{Riedel2023MemPool, + title = {{MemPool}: A Scalable Manycore Architecture with a Low-Latency Shared {L1} Memory}, + author = {Riedel, Samuel and Cavalcante, Matheus and Andri, Renzo and Benini, Luca}, + journal = {IEEE Transactions on Computers}, + year = {2023}, + volume = {72}, + number = {12}, + pages = {3561--3575}, + publisher = {IEEE Computer Society}, + doi = {10.1109/TC.2023.3307796} +} +``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10227739) and is also available on [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000643341).

-Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC +Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC

``` @@ -507,13 +484,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248 doi = {10.1109/TVLSI.2023.3314135} } ``` +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10261872).

-MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS +MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS

``` @@ -529,8 +507,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248 doi={10.1109/ICECS58634.2023.10382925} } ``` - -This paper is also available at ETH Research Collection, at the following link: [https://doi.org/10.3929/ethz-b-000653598](https://doi.org/10.3929/ethz-b-000653598). +This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10382925) and is also available on the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000653598).

@@ -538,7 +515,7 @@ This paper is also available at ETH Research Collection, at the following link: ### 2024
-LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation +LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation

``` @@ -550,15 +527,14 @@ This paper is also available at ETH Research Collection, at the following link: month=jan } ``` - -This paper is also available at arXiv, at the following link: [arXiv:2401.09359 [cs.AR]](https://arxiv.org/abs/2401.09359). +This paper is available on [arXiv:2401.09359 [cs.AR]](https://arxiv.org/abs/2401.09359).

-Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters +Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters

``` @@ -570,13 +546,61 @@ This paper is also available at arXiv, at the following link: [arXiv:2401.09359 month=feb } ``` - -This paper is also available at arXiv, at the following link: [arXiv:2402.12986 [cs.AR]](https://arxiv.org/abs/2402.12986). +This paper is available on [arXiv:2402.12986 [cs.AR]](https://arxiv.org/abs/2402.12986).

## Chips +The MemPool architecture has been taped out in the following chips: + - 2021 [**MinPool**](http://asic.ethz.ch/2021/Minpool.html): A 16-core prototype of MemPool. - 2024 [**Heartstream**](http://asic.ethz.ch/2024/Heartstream.html): A 64-core version of MemPool with systolic and FPU support. + +## License +MemPool is released under permissive open source licenses. Most of MemPool's source code is released under the Apache License 2.0 (`Apache-2.0`) see [`LICENSE`](LICENSE). The code in `hardware` is released under Solderpad v0.51 (`SHL-0.51`) see [`hardware/LICENSE`](hardware/LICENSE). + +Note, MemPool includes several third-party packages with their own licenses: + +
+Note, MemPool includes several third-party packages with their own licenses: +

+ +### Software + +- `software/runtime/printf.{c,h}` is licensed under the MIT license. +- `software/runtime/omp/libgomp.h` is licensed under the GPL license. +- `software/riscv-tests` is an extended version of RISC-V's [riscv-tests](https://github.com/riscv/riscv-tests/) repository licensed under a BSD license. See [`software/riscv-tests/LICENSE`](software/riscv-tests/LICENSE) for details. + +### Hardware + +The `hardware` folder is licensed under Solderpad v0.51 see [`hardware/LICENSE`](hardware/LICENSE). We use the following exceptions: + +- `hardware/tb/dpi/elfloader.cpp` is licensed under a BSD license. +- `hardware/tb/verilator/*` is licensed under Apache License 2.0 see [`LICENSE`](LICENSE) +- `hardware/tb/verilator/lowrisc_*` contain modified versions of lowRISC's helper libraries. They are licensed under Apache License 2.0. + +### Scripts + +- `scripts/run_clang_format.py` is licensed under the MIT license. + +### Toolchains + +The following compilers can be used to build applications for MemPool: + +- `toolchain/halide` is licensed under the MIT license. See [Halide's license](https://github.com/halide/Halide/blob/master/LICENSE.txt) for details. +- `toolchain/llvm-project`is licensed under the Apache License v2.0 with LLVM Exceptions. See [LLVM's DeveloperPolicy](https://llvm.org/docs/DeveloperPolicy.html#new-llvm-project-license-framework) for more details. +- `toolchain/riscv-gnu-toolchain`'s licensing information is available [here](https://github.com/pulp-platform/pulp-riscv-gnu-toolchain/blob/master/LICENSE) + +We use the following RISC-V tools to parse simulation traces and keep opcodes consistent throughout the project. + +- `toolchain/riscv-isa-sim` is licensed under a BSD license. See [riscv-isa-sim's license](https://github.com/riscv/riscv-isa-sim/blob/master/LICENSE) for details. +- `toolchain/riscv-opcodes` contains an extended version of [riscv-opcodes](https://github.com/riscv/riscv-opcodes) licensed under the BSD license. See [`toolchain/riscv-opcodes/LICENSE`](toolchain/riscv-opcodes/LICENSE) for details. + +The open-source simulator [Verilator](https://www.veripool.org/verilator) can be used for RTL simulation. + +- `toolchain/verilator` is licensed under GPL. See [Verilator's license](https://github.com/verilator/verilator/blob/master/LICENSE) for more details. + +

+