From 1cf1107714249f0ba77e51fc92f93028696cbe2d Mon Sep 17 00:00:00 2001 From: Yichao Zhang Date: Mon, 11 Dec 2023 16:58:24 +0100 Subject: [PATCH] [Env] Update some configurations, include the fifo size and DRAM configuration --- config/config.mk | 4 ++-- .../resources/configs/mcconfigs/fr_fcfs_grp.json | 2 +- .../dramsys_lib/resources/configs/simulator/hbm2e.json | 4 ++-- hardware/dram_rtl_sim/src/axi_dram_sim.sv | 4 ++-- hardware/src/mempool_group.sv | 8 ++++---- hardware/src/mempool_sub_group.sv | 2 +- hardware/tb/mempool_tb.sv | 4 ++-- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/config/config.mk b/config/config.mk index 9edd3bbb0..d8a6e9c6a 100644 --- a/config/config.mk +++ b/config/config.mk @@ -34,12 +34,12 @@ ifeq ($(config), terapool) l2_size ?= 16777216 # 1000000 l2_banks ?= 16 dmas_per_group ?= 4 # Brust Length = 16 - dram_axi_width_interleaved ?= 256 + dram_axi_width_interleaved ?= 16 else l2_size ?= 4194304 # 400000 l2_banks ?= 4 dmas_per_group ?= 1 # Brust Length = 16 - dram_axi_width_interleaved ?= 256 + dram_axi_width_interleaved ?= 16 endif # Size of sequential memory per core (in bytes) diff --git a/hardware/dram_rtl_sim/dramsys_lib/resources/configs/mcconfigs/fr_fcfs_grp.json b/hardware/dram_rtl_sim/dramsys_lib/resources/configs/mcconfigs/fr_fcfs_grp.json index 0c6f693fe..6981f93be 100644 --- a/hardware/dram_rtl_sim/dramsys_lib/resources/configs/mcconfigs/fr_fcfs_grp.json +++ b/hardware/dram_rtl_sim/dramsys_lib/resources/configs/mcconfigs/fr_fcfs_grp.json @@ -1,6 +1,6 @@ { "mcconfig": { - "PagePolicy": "Open", + "PagePolicy": "Open", "Scheduler": "FrFcfsGrp", "SchedulerBuffer": "Bankwise", "RequestBufferSize": 128, diff --git a/hardware/dram_rtl_sim/dramsys_lib/resources/configs/simulator/hbm2e.json b/hardware/dram_rtl_sim/dramsys_lib/resources/configs/simulator/hbm2e.json index 66e7f36ea..3b6b819de 100644 --- a/hardware/dram_rtl_sim/dramsys_lib/resources/configs/simulator/hbm2e.json +++ b/hardware/dram_rtl_sim/dramsys_lib/resources/configs/simulator/hbm2e.json @@ -5,7 +5,7 @@ "DatabaseRecording": true, "Debug": false, "ECCControllerMode": "Disabled", - "EnableWindowing": false, + "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, "PowerAnalysis": false, @@ -14,6 +14,6 @@ "StoreMode": "Store", "ThermalSimulation": false, "UseMalloc": false, - "WindowSize": 1000 + "WindowSize": 300 } } diff --git a/hardware/dram_rtl_sim/src/axi_dram_sim.sv b/hardware/dram_rtl_sim/src/axi_dram_sim.sv index 541850168..3fae4f198 100644 --- a/hardware/dram_rtl_sim/src/axi_dram_sim.sv +++ b/hardware/dram_rtl_sim/src/axi_dram_sim.sv @@ -89,8 +89,8 @@ module axi_dram_sim #( .AxiDataWidth (DramDataWidth ), .AxiIdWidth (AxiIdWidth ), .AxiUserWidth (AxiUserWidth ), - .AxiMaxWriteTxns(32 ), - .AxiMaxReadTxns (32 ), + .AxiMaxWriteTxns(64 ), + .AxiMaxReadTxns (64 ), .FallThrough (0 ), .full_req_t (dram_axi_req_t ), .full_resp_t (dram_axi_resp_t ), diff --git a/hardware/src/mempool_group.sv b/hardware/src/mempool_group.sv index b51969bf8..14b019a63 100644 --- a/hardware/src/mempool_group.sv +++ b/hardware/src/mempool_group.sv @@ -565,7 +565,7 @@ module mempool_group .DmaRegionWidth (NumBanksPerGroup*4/NumDmasPerGroup ), .DmaRegionStart (TCDMBaseAddr ), .DmaRegionEnd (TCDMBaseAddr+TCDMSize ), - .TransFifoDepth (8 ), + .TransFifoDepth (16 ), .burst_req_t (dma_req_t ), .meta_t (dma_meta_t ) ) i_idma_distributed_midend ( @@ -975,7 +975,7 @@ module mempool_group .DmaRegionWidth (NumBanksPerGroup*4/NumDmasPerGroup), .DmaRegionStart (TCDMBaseAddr ), .DmaRegionEnd (TCDMBaseAddr+TCDMSize ), - .TransFifoDepth (8 ), + .TransFifoDepth (16 ), .burst_req_t (dma_req_t ), .meta_t (dma_meta_t ) ) i_idma_distributed_midend ( @@ -1025,8 +1025,8 @@ module mempool_group .DataWidth (AxiDataWidth ), .AddrWidth (AddrWidth ), .IdWidth (AxiTileIdWidth ), - .AxReqFifoDepth (2 ), - .TransFifoDepth (1 ), + .AxReqFifoDepth (8 ), + .TransFifoDepth (4 ), .BufferDepth (4 ), .axi_req_t (axi_tile_req_t ), .axi_res_t (axi_tile_resp_t), diff --git a/hardware/src/mempool_sub_group.sv b/hardware/src/mempool_sub_group.sv index 555fd60db..408dbe441 100644 --- a/hardware/src/mempool_sub_group.sv +++ b/hardware/src/mempool_sub_group.sv @@ -515,7 +515,7 @@ module mempool_sub_group .AddrWidth (AddrWidth ), .IdWidth (AxiTileIdWidth ), .AxReqFifoDepth (8 ), - .TransFifoDepth (1 ), + .TransFifoDepth (4 ), .BufferDepth (4 ), .axi_req_t (axi_tile_req_t ), .axi_res_t (axi_tile_resp_t), diff --git a/hardware/tb/mempool_tb.sv b/hardware/tb/mempool_tb.sv index 142199f26..8eddd1e9c 100644 --- a/hardware/tb/mempool_tb.sv +++ b/hardware/tb/mempool_tb.sv @@ -30,7 +30,7 @@ module mempool_tb; localparam BootAddr = 0; `endif - localparam ClockPeriod = 2ns; + localparam ClockPeriod = 1ns; localparam TA = 0.2ns; localparam TT = 0.8ns; @@ -58,7 +58,7 @@ module mempool_tb; end `ifdef DRAM - dram_sim_engine #(.ClkPeriodNs(2)) i_dram_sim_engine (.clk_i(clk), .rst_ni(rst_n)); + dram_sim_engine #(.ClkPeriodNs(ClockPeriod)) i_dram_sim_engine (.clk_i(clk), .rst_ni(rst_n)); `endif /*********