+ +``` +@inproceedings{Cavalcante2021MemPool, + title = {{MemPool}: A Shared-{L1} Memory Many-Core Cluster with a Low-Latency Interconnect}, + author = {Cavalcante, Matheus and Riedel, Samuel and Pullini, Antonio and Benini, Luca}, + booktitle = {2021 Design, Automation, and Test in Europe Conference and Exhibition}, + address = {Grenoble, France}, + year = {2021}, + month = mar, + pages = {701--706}, + publisher = {IEEE}, + doi = {10.23919/DATE51398.2021.9474087} } ``` This paper is also available at arXiv, at the following link: [arXiv:2012.02973 [cs.AR]](https://arxiv.org/abs/2012.02973). + +
++ +``` +@inproceedings{Beyne2021, + title = {{3D} {SoC} integration, beyond {2.5D} chiplets}, + author = {Beyne, Eric and Milojevic, Dragomir and {Van Der Plas}, Geert and Beyer, Gerald}, + booktitle = {Technical Digest - International Electron Devices Meeting, IEDM}, + year = {2021}, + pages = {79--82}, + publisher = {IEEE}, + doi = {10.1109/IEDM19574.2021.9720614} +} +``` + +
++ +``` +@inproceedings{Cavalcante2022MemPool3D, + title = {{MemPool-3D}: Boosting Performance and Efficiency of Shared-{L1} Memory Many-Core Clusters with {3D} Integration}, + author = {Cavalcante, Matheus and Agnesina, Anthony and Riedel, Samuel and Brunion, Moritz and Garcia-Ortiz, Alberto and Milojevic, Dragomir and Catthoor, Francky and Lim, Sung Kyu and Benini, Luca}, + booktitle = {2022 Design, Automation, and Test in Europe Conference and Exhibition}, + address = {Online}, + year = {2022}, + month = mar, + pages = {394--399}, + publisher = {IEEE}, + doi = {10.23919/DATE54114.2022.9774726} +} +``` + +This paper is also available at arXiv, at the following link: [arXiv:2112.01168 [cs.AR]](https://arxiv.org/abs/2112.01168). + +
++ +``` +@inproceedings{Agnesina2022, + title = {{Hier-3D}: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded {3D} ICs}, + author = {Agnesina, Anthony and Brunion, Moritz and Garcia-Ortiz, Alberto and Catthoor, Francky and Milojevic, Dragomir and Komalan, Manu and Cavalcante, Matheus and Riedel, Samuel and Benini, Luca and Lim, Sung Kyu}, + booktitle = {Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design}, + address = {New York, NY, USA}, + year = {2022}, + month = aug, + publisher = {Association for Computing Machinery}, + doi = {10.1145/3531437.3539702} +} +``` + +
++ +``` +@inproceedings{Cavalcante2022Spatz, + title = {Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-{L1} Clusters}, + author = {Cavalcante, Matheus and W{\"{u}}thrich, Domenic and Perotti, Matteo and Riedel, Samuel and Benini, Luca}, + booktitle = {2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, + address = {San Diego, California, USA}, + year = {2022}, + month = oct, + pages = {159--167}, + publisher = {Association for Computing Machinery}, + doi = {10.1145/3508352.3549367} +} +``` + +This paper is also available at arXiv, at the following link: [arXiv:2207.07970 [cs.AR]](https://arxiv.org/abs/2207.07970). + +
++ +``` +@article{Venkateswarlu2022, + title = {Thermal Performance Analysis of Mempool RISC-V Multicore {SoC}}, + author = {Venkateswarlu, Sankatali and Mishra, Subrat and Oprins, Herman and Vermeersch, Bjorn and Brunion, Moritz and Han, Jun Han and Stan, Mircea R. and Weckx, Pieter and Catthoor, Francky}, + journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + year = {2022}, + volume = {30}, + number = {11}, + pages = {1668--1676}, + publisher = {IEEE}, + doi = {10.1109/TVLSI.2022.3207553} +} +``` + +
++ +``` +@inproceedings{Mishra2023, + title = {Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)}, + author = {Mishra, S. and Sankatali, V. and Vermeersch, B. and Brunion, M. and Lofrano, M. and Abdi, D. and Oprins, H. and Biswas, D. and Zografos, O. and Hiblot, G. and {Van Der Plas}, G. and Weckx, P. and Hellings, G. and Myers, J. and Catthoor, F. and Ryckaert, J.}, + booktitle = {IEEE International Reliability Physics Symposium Proceedings}, + address = {Monterey, CA, USA}, + year = {2023}, + month = mar, + publisher = {IEEE}, + doi = {10.1109/IRPS48203.2023.10117979} +} +``` + +
++ +``` +@inproceedings{Bertuletti2023PUSCH, + title = {Efficient Parallelization of {5G-PUSCH} on a Scalable {RISC-V} Many-Core Processor}, + author = {Bertuletti, Marco and Zhang, Yichao and Vanelli-Coralli, Alessandro and Benini, Luca}, + booktitle = {2023 Design, Automation, and Test in Europe Conference and Exhibition}, + address = {Antwerp, Belgium}, + year = {2023}, + month = apr, + pages = {396--401}, + publisher = {IEEE}, + doi = {10.23919/DATE56975.2023.10137247} +} +``` + +This paper is also available at arXiv, at the following link: [arXiv:2210.09196 [cs.DC]](https://arxiv.org/abs/2210.09196). + +
++ +``` +@inproceedings{Riedel2023MmS, + title = {{MemPool} Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster}, + author = {Riedel, Samuel and Khov, Gua Hao and Mazzola, Sergio and Cavalcante, Matheus and Andri, Renzo and Benini, Luca}, + booktitle = {2023 Design, Automation, and Test in Europe Conference and Exhibition}, + address = {Antwerp, Belgium}, + year = {2023} + month = apr, + pages = {503--504}, + publisher = {IEEE}, + doi = {10.23919/DATE56975.2023.10136909}, +} +``` + +
++ +``` +@inproceedings{Bertuletti2023Barrier, + title = {Fast Shared-Memory Barrier Synchronization for a 1024-Cores {RISC-V} Many-Core Cluster}, + author = {Bertuletti, Marco and Riedel, Samuel and Zhang, Yichao and Vanelli-Coralli, Alessandro and Benini, Luca}, + booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation}, + editor = {Silvano, Cristina and Pilato, Christian and Reichenbach, Marc}, + address = {Samos}, + year = {2023}, + month = jul, + pages = {241--254}, + publisher = {Springer Nature Switzerland}, + doi = {10.1007/978-3-031-46077-7_16} +} +``` + +This paper is also available at arXiv, at the following link: [arXiv:2307.10248 [cs.DC]](https://arxiv.org/abs/2307.10248). + +
++ +``` +@article{Venkateswarlu2023, + title = {Impact of 3-D Integration on Thermal Performance of {RISC-V} {MemPool} Multicore {SOC}}, + author = {Venkateswarlu, Sankatali and Mishra, Subrat and Oprins, Herman and Vermeersch, Bjorn and Brunion, Moritz and Han, Jun Han and Stan, Mircea R. and Biswas, Dwaipayan and Weckx, Pieter and Catthoor, Francky}, + journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + year = {2023}, + volume = {Early Access}, + publisher = {IEEE}, + doi = {10.1109/TVLSI.2023.3314135} +} +``` + +
+