diff --git a/Bender.lock b/Bender.lock index f2704947b..ce595230a 100644 --- a/Bender.lock +++ b/Bender.lock @@ -85,7 +85,7 @@ packages: dependencies: - common_cells spatz: - revision: fa75ec560c4518bdac4c350481e6474188f88ecc + revision: 5e854f1fd9e82df236565a61a710d3092059f471 version: null source: Git: git@iis-git.ee.ethz.ch:spatz/spatz.git diff --git a/Bender.yml b/Bender.yml index eb93d0848..0153cf8f4 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,7 +14,7 @@ dependencies: reqrsp_interface: { path: "hardware/deps/reqrsp_interface" } snitch: { path: "hardware/deps/snitch" } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.5 } - spatz: { git: "git@iis-git.ee.ethz.ch:spatz/spatz.git", rev: fa75ec56 } + spatz: { git: "git@iis-git.ee.ethz.ch:spatz/spatz.git", rev: 5e854f1f } FPnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.3 } workspace: diff --git a/config/mempool.mk b/config/mempool.mk index 2eb9e80c0..f95e0508f 100644 --- a/config/mempool.mk +++ b/config/mempool.mk @@ -26,4 +26,4 @@ axi_hier_radix ?= 20 # Number of AXI masters per group axi_masters_per_group ?= 1 -xpulpimg ?= 0 +xpulpimg ?= 1 diff --git a/hardware/deps/snitch/Bender.yml b/hardware/deps/snitch/Bender.yml index 5b0597a64..24427e910 100644 --- a/hardware/deps/snitch/Bender.yml +++ b/hardware/deps/snitch/Bender.yml @@ -21,8 +21,7 @@ sources: - src/snitch_axi_pkg.sv - src/snitch_icache/snitch_icache_pkg.sv # rest of RTL - # - src/snitch.sv - - src/snitch_md.sv + - src/snitch.sv - src/snitch_regfile_ff.sv # - src/snitch_regfile_latch.sv - src/snitch_lsu.sv diff --git a/hardware/deps/snitch/src/snitch.sv b/hardware/deps/snitch/src/snitch.sv index 3b5fdb356..f2fb7c358 100644 --- a/hardware/deps/snitch/src/snitch.sv +++ b/hardware/deps/snitch/src/snitch.sv @@ -19,7 +19,25 @@ module snitch parameter logic [31:0] MTVEC = BootAddr, // Exception Base Address (see privileged spec 3.1.7) parameter bit RVE = 0, // Reduced-register Extension parameter bit RVM = 1, // Enable IntegerMmultiplication & Division Extension - parameter int RegNrWritePorts = 2 // Implement one or two write ports into the register file + + parameter bit RVV = 0, // Enable Vector Extension + parameter bit XFVEC = 0, + parameter bit XFDOTP = 0, + parameter bit XFAUX = 0, + /// Enable F Extension. + parameter bit RVF = 0, + /// Enable D Extension. + parameter bit RVD = 0, + parameter bit XF16 = 0, + parameter bit XF16ALT = 0, + parameter bit XF8 = 0, + parameter bit XF8ALT = 0, + /// Enable div/sqrt unit (buggy - use with caution) + parameter bit XDivSqrt = 0, + parameter int RegNrWritePorts = 2, // Implement one or two write ports into the register file + parameter type acc_issue_rsp_t = logic, + // Dependant parameters. + localparam bit FP_EN = RVF || RVD // Enable FP in general, ) ( input logic clk_i, input logic rst_i, @@ -56,7 +74,13 @@ module snitch /// AXI-like handshaking. /// Same IDs need to be handled in-order. output logic [31:0] acc_qaddr_o, +`ifdef TARGET_SPATZ + output logic [5:0] acc_qid_o, + input logic [5:0] acc_pid_i, +`else output logic [4:0] acc_qid_o, + input logic [4:0] acc_pid_i, +`endif output logic [31:0] acc_qdata_op_o, output logic [31:0] acc_qdata_arga_o, output logic [31:0] acc_qdata_argb_o, @@ -64,10 +88,13 @@ module snitch output logic acc_qvalid_o, input logic acc_qready_i, input logic [31:0] acc_pdata_i, - input logic [4:0] acc_pid_i, + input logic acc_pwrite_i, input logic acc_perror_i, input logic acc_pvalid_i, output logic acc_pready_o, + input acc_issue_rsp_t acc_qdata_rsp_i, + input logic [1:0] acc_mem_finished_i, + input logic [1:0] acc_mem_str_finished_i, /// TCDM Data Interface /// Write transactions do not return data on the `P Channel` /// Transactions need to be handled strictly in-order. @@ -85,6 +112,10 @@ module snitch input logic data_pvalid_i, output logic data_pready_o, input logic wake_up_sync_i, // synchronous wake-up interrupt + // FPU **un-timed** Side-channel + output fpnew_pkg::roundmode_e fpu_rnd_mode_o, + output fpnew_pkg::fmt_mode_t fpu_fmt_mode_o, + input fpnew_pkg::status_t fpu_status_i, // Core event strobes output snitch_pkg::core_events_t core_events_o ); @@ -164,6 +195,7 @@ module snitch logic [RegWidth-1:0] lsu_rd; logic [31:0] lsu_qaddr; + logic retire_load; // retire a load instruction logic retire_p; // retire from post-increment instructions logic retire_i; // retire the rest of the base instruction set @@ -192,7 +224,7 @@ module snitch None, Reg, IImmediate, UImmediate, JImmediate, SImmediate, SFImmediate, PC, CSR, CSRImmediate, PBImmediate, RegRd, RegRs2 } opa_select, opb_select, opc_select; - logic write_rd; // write rd desitnation this cycle + logic write_rd; // write rd destination this cycle logic uses_rd; logic write_rs1; // write rs1 destination this cycle logic uses_rs1; @@ -206,11 +238,24 @@ module snitch logic [31:0] csr_rvalue; logic csr_en; + typedef struct packed { + fpnew_pkg::fmt_mode_t fmode; + fpnew_pkg::roundmode_e frm; + fpnew_pkg::status_t fflags; + } fcsr_t; + fcsr_t fcsr_d, fcsr_q; + // Current instruction needs fcsr + logic read_fcsr; + + assign fpu_rnd_mode_o = fcsr_q.frm; + assign fpu_fmt_mode_o = fcsr_q.fmode; + // Registers `FFAR(pc_q, pc_d, BootAddr, clk_i, rst_i) `FFAR(wfi_q, wfi_d, '0, clk_i, rst_i) `FFAR(wake_up_q, wake_up_d, '0, clk_i, rst_i) `FFAR(sb_q, sb_d, '0, clk_i, rst_i) + `FFAR(fcsr_q, fcsr_d, '0, clk_i, rst_i) always_comb begin core_events_o = '0; @@ -220,13 +265,25 @@ module snitch // accelerator offloading interface // register int destination in scoreboard logic acc_register_rd; + // LSU stalling due to accelerator memory requests + logic acc_mem_stall; + // Offloaded mem operation is a store operation + logic acc_mem_store; assign acc_qaddr_o = hart_id_i; assign acc_qid_o = rd; assign acc_qdata_op_o = inst_data_i; assign acc_qdata_arga_o = {{32{gpr_rdata[0][31]}}, gpr_rdata[0]}; - assign acc_qdata_argb_o = {{32{gpr_rdata[1][31]}}, gpr_rdata[1]}; - assign acc_qdata_argc_o = {{32{gpr_rdata[2][31]}}, gpr_rdata[2]}; + // assign acc_qdata_argb_o = {{32{gpr_rdata[1][31]}}, gpr_rdata[1]}; + assign acc_qdata_argb_o = opb_select inside {IImmediate, SImmediate} ? + {{32{alu_result[31]}}, alu_result} : {{32{gpr_rdata[1][31]}}, gpr_rdata[1]}; + +`ifdef XPULPIMG_EXTENSION + assign acc_qdata_argc_o = gpr_rdata[2]}; +`else + assign acc_qdata_argc_o = '0; +`endif + // instruction fetch interface assign inst_addr_o = pc_q; @@ -261,10 +318,18 @@ module snitch assign dst_ready = dstrd_ready & dstrs1_ready; assign valid_instr = (inst_ready_i & inst_valid_o) & operands_ready & dst_ready; + +`ifdef TARGET_SPATZ // the accelerator interface stalled us - assign acc_stall = (acc_qvalid_o & ~acc_qready_i); + assign acc_stall = (acc_qvalid_o & ~acc_qready_i) || (read_fcsr && acc_qdata_rsp_i.isfloat); // the LSU Interface didn't accept our request yet + assign lsu_stall = (lsu_qvalid & ~lsu_qready) | acc_mem_stall; +`else + assign acc_stall = (acc_qvalid_o & ~acc_qready_i); assign lsu_stall = (lsu_qvalid & ~lsu_qready); +`endif + + // Stall the stage if we either didn't get a valid instruction or the LSU/Accelerator is not ready assign stall = ~valid_instr | lsu_stall | acc_stall; @@ -346,10 +411,11 @@ module snitch acc_qvalid_o = 1'b0; acc_register_rd = 1'b0; + acc_mem_store = 1'b0; csr_en = 1'b0; // Wake up if a wake-up is incoming or pending - wfi_d = (wake_up_q || wake_up_sync_i) ? 1'b0 : wfi_q; + wfi_d = ((|wake_up_q) | wake_up_sync_i) ? 1'b0 : wfi_q; // Only store a pending wake-up if we are not asleep wake_up_d = (wake_up_sync_i && !wfi_q) ? wake_up_q + 1 : wake_up_q; @@ -577,61 +643,193 @@ module snitch end // CSR Instructions riscv_instr::CSRRW: begin // Atomic Read/Write CSR - opa_select = Reg; - opb_select = None; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; + unique case (inst_data_i[31:20]) +`ifdef TARGET_SPATZ + riscv_instr::CSR_VSTART, + riscv_instr::CSR_VL, + riscv_instr::CSR_VTYPE, + riscv_instr::CSR_VLENB, + riscv_instr::CSR_VXSAT, + riscv_instr::CSR_VXRM, + riscv_instr::CSR_VCSR: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = rd != 0; + acc_qvalid_o = valid_instr; + opa_select = Reg; + acc_register_rd = rd != 0; + end else begin + illegal_inst = 1'b1; + end + end +`endif + default: begin + opa_select = Reg; + opb_select = None; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + endcase end riscv_instr::CSRRWI: begin - opa_select = CSRImmediate; - opb_select = None; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; + unique case (inst_data_i[31:20]) +`ifdef TARGET_SPATZ + riscv_instr::CSR_VSTART, + riscv_instr::CSR_VL, + riscv_instr::CSR_VTYPE, + riscv_instr::CSR_VLENB, + riscv_instr::CSR_VXSAT, + riscv_instr::CSR_VXRM, + riscv_instr::CSR_VCSR: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = rd != 0; + acc_qvalid_o = valid_instr; + acc_register_rd = rd != 0; + end else begin + illegal_inst = 1'b1; + end + end +`endif + default: begin + opa_select = CSRImmediate; + opb_select = None; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + endcase end riscv_instr::CSRRS: begin // Atomic Read and Set Bits in CSR - alu_op = LOr; - opa_select = Reg; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; + unique case (inst_data_i[31:20]) +`ifdef TARGET_SPATZ + riscv_instr::CSR_VSTART, + riscv_instr::CSR_VL, + riscv_instr::CSR_VTYPE, + riscv_instr::CSR_VLENB, + riscv_instr::CSR_VXSAT, + riscv_instr::CSR_VXRM, + riscv_instr::CSR_VCSR: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end +`endif + default: begin + alu_op = LOr; + opa_select = Reg; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + endcase end riscv_instr::CSRRSI: begin - // offload CSR enable to FP SS - if (inst_data_i[31:20] != snitch_pkg::CSR_SSR) begin - alu_op = LOr; - opa_select = CSRImmediate; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end else begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end + unique case (inst_data_i[31:20]) +`ifdef TARGET_SPATZ + riscv_instr::CSR_VSTART, + riscv_instr::CSR_VL, + riscv_instr::CSR_VTYPE, + riscv_instr::CSR_VLENB, + riscv_instr::CSR_VXSAT, + riscv_instr::CSR_VXRM, + riscv_instr::CSR_VCSR: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end +`endif + snitch_pkg::CSR_SSR: begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end + default: begin + alu_op = LOr; + opa_select = CSRImmediate; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + endcase end riscv_instr::CSRRC: begin // Atomic Read and Clear Bits in CSR - alu_op = LNAnd; - opa_select = Reg; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; + unique case (inst_data_i[31:20]) +`ifdef TARGET_SPATZ + riscv_instr::CSR_VSTART, + riscv_instr::CSR_VL, + riscv_instr::CSR_VTYPE, + riscv_instr::CSR_VLENB, + riscv_instr::CSR_VXSAT, + riscv_instr::CSR_VXRM, + riscv_instr::CSR_VCSR: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end +`endif + default: begin + alu_op = LNAnd; + opa_select = Reg; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + endcase end riscv_instr::CSRRCI: begin - if (inst_data_i[31:20] != snitch_pkg::CSR_SSR) begin - alu_op = LNAnd; - opa_select = CSRImmediate; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end else begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end + unique case (inst_data_i[31:20]) +`ifdef TARGET_SPATZ + riscv_instr::CSR_VSTART, + riscv_instr::CSR_VL, + riscv_instr::CSR_VTYPE, + riscv_instr::CSR_VLENB, + riscv_instr::CSR_VXSAT, + riscv_instr::CSR_VXRM, + riscv_instr::CSR_VCSR: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end +`endif + snitch_pkg::CSR_SSR: begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end + default: begin + alu_op = LNAnd; + opa_select = CSRImmediate; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + endcase end riscv_instr::ECALL, riscv_instr::EBREAK: begin @@ -645,10 +843,10 @@ module snitch riscv_instr::WFI: begin if (valid_instr) begin wfi_d = 1'b1; - if (wake_up_q || wake_up_sync_i) begin + if ((|wake_up_q)| wake_up_sync_i) begin // Do not sleep if a wake-up is pending wfi_d = 1'b0; - if (wake_up_q) begin + if (|wake_up_q) begin // Decrement outstanding wake_up pulses wake_up_d = wake_up_q - 1; end @@ -803,7 +1001,377 @@ module snitch acc_register_rd = 1'b1; end +/* RVV extension */ +`ifdef TARGET_SPATZ + // Off-load to RVV coprocessor + // 1 destination register (rd) + riscv_instr::VSETIVLI: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 1 source register (rs1) and 1 destination register (rd) + riscv_instr::VSETVLI: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 2 source registers (rs1, rs2) and one destination register (rd) + riscv_instr::VSETVL: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + opb_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 0 source register and 1 destination register + riscv_instr::VMV_X_S: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 0 source register and 0 destination register + riscv_instr::VADD_VV, + riscv_instr::VADD_VI, + riscv_instr::VSUB_VV, + riscv_instr::VRSUB_VI, + riscv_instr::VAND_VV, + riscv_instr::VAND_VI, + riscv_instr::VOR_VV, + riscv_instr::VOR_VI, + riscv_instr::VXOR_VV, + riscv_instr::VXOR_VI, + riscv_instr::VADC_VVM, + riscv_instr::VADC_VIM, + riscv_instr::VMADC_VV, + riscv_instr::VMADC_VI, + riscv_instr::VMADC_VVM, + riscv_instr::VMADC_VIM, + riscv_instr::VSBC_VVM, + riscv_instr::VMSBC_VV, + riscv_instr::VMSBC_VVM, + riscv_instr::VSLL_VV, + riscv_instr::VSLL_VI, + riscv_instr::VSRL_VV, + riscv_instr::VSRL_VI, + riscv_instr::VSRA_VV, + riscv_instr::VSRA_VI, + riscv_instr::VREDSUM_VS, + riscv_instr::VREDAND_VS, + riscv_instr::VREDOR_VS, + riscv_instr::VREDXOR_VS, + riscv_instr::VREDMIN_VS, + riscv_instr::VREDMINU_VS, + riscv_instr::VREDMAX_VS, + riscv_instr::VREDMAXU_VS, + riscv_instr::VMSEQ_VV, + riscv_instr::VMSEQ_VI, + riscv_instr::VMSNE_VV, + riscv_instr::VMSNE_VI, + riscv_instr::VMSLTU_VV, + riscv_instr::VMSLT_VV, + riscv_instr::VMSLEU_VV, + riscv_instr::VMSLEU_VI, + riscv_instr::VMSLE_VV, + riscv_instr::VMSLE_VI, + riscv_instr::VMSGTU_VI, + riscv_instr::VMSGT_VI, + riscv_instr::VMIN_VV, + riscv_instr::VMINU_VV, + riscv_instr::VMAX_VV, + riscv_instr::VMAXU_VV, + riscv_instr::VMUL_VV, + riscv_instr::VMULH_VV, + riscv_instr::VMULHU_VV, + riscv_instr::VMULHSU_VV, + riscv_instr::VMACC_VV, + riscv_instr::VNMSAC_VV, + riscv_instr::VMADD_VV, + riscv_instr::VNMSUB_VV, + riscv_instr::VDIV_VV, + riscv_instr::VDIVU_VV, + riscv_instr::VREM_VV, + riscv_instr::VREMU_VV, + riscv_instr::VWMUL_VV, + riscv_instr::VWMULU_VV, + riscv_instr::VWMULSU_VV, + riscv_instr::VWMACC_VV, + riscv_instr::VWMACCU_VV, + riscv_instr::VWMACCSU_VV, + riscv_instr::VMV_V_V, + riscv_instr::VMV_V_I, + riscv_instr::VFMV_F_S, + riscv_instr::VSLIDEUP_VI, + riscv_instr::VSLIDEDOWN_VI: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b0; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::VFADD_VV, + riscv_instr::VFSUB_VV, + riscv_instr::VFMIN_VV, + riscv_instr::VFMAX_VV, + riscv_instr::VFSGNJ_VV, + riscv_instr::VFSGNJN_VV, + riscv_instr::VFSGNJX_VV, + riscv_instr::VFMUL_VV, + riscv_instr::VFMADD_VV, + riscv_instr::VFNMADD_VV, + riscv_instr::VFMSUB_VV, + riscv_instr::VFNMSUB_VV, + riscv_instr::VFMACC_VV, + riscv_instr::VFNMACC_VV, + riscv_instr::VFMSAC_VV, + riscv_instr::VFNMSAC_VV, + riscv_instr::VFCVT_F_X_V, + riscv_instr::VFCVT_F_XU_V, + riscv_instr::VFCVT_X_F_V, + riscv_instr::VFCVT_XU_F_V, + riscv_instr::VFCVT_RTZ_X_F_V, + riscv_instr::VFCVT_RTZ_XU_F_V, + riscv_instr::VFNCVT_XU_F_W, + riscv_instr::VFNCVT_X_F_W, + riscv_instr::VFNCVT_RTZ_XU_F_W, + riscv_instr::VFNCVT_RTZ_X_F_W, + riscv_instr::VFNCVT_F_XU_W, + riscv_instr::VFNCVT_F_X_W, + riscv_instr::VFNCVT_F_F_W, + riscv_instr::VFREDOSUM_VS, + riscv_instr::VFREDUSUM_VS, + riscv_instr::VFREDMAX_VS, + riscv_instr::VFREDMIN_VS, + riscv_instr::VFWADD_VV, + riscv_instr::VFWADD_WV, + riscv_instr::VFWSUB_VV, + riscv_instr::VFWSUB_WV, + riscv_instr::VFWMUL_VV, + riscv_instr::VFWDOTP_VV, + riscv_instr::VFWMACC_VV, + riscv_instr::VFWNMACC_VV, + riscv_instr::VFWMSAC_VV, + riscv_instr::VFWNMSAC_VV: begin + if (RVV && RVF) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b0; + end else begin + illegal_inst = 1'b1; + end + end + // 1 source register (rs1) + riscv_instr::VADD_VX, + riscv_instr::VSUB_VX, + riscv_instr::VRSUB_VX, + riscv_instr::VAND_VX, + riscv_instr::VOR_VX, + riscv_instr::VXOR_VX, + riscv_instr::VADC_VXM, + riscv_instr::VMADC_VX, + riscv_instr::VMADC_VXM, + riscv_instr::VSBC_VXM, + riscv_instr::VMSBC_VX, + riscv_instr::VMSBC_VXM, + riscv_instr::VSLL_VX, + riscv_instr::VSRL_VX, + riscv_instr::VSRA_VX, + riscv_instr::VMSEQ_VX, + riscv_instr::VMSNE_VX, + riscv_instr::VMSLTU_VX, + riscv_instr::VMSLT_VX, + riscv_instr::VMSLEU_VX, + riscv_instr::VMSLE_VX, + riscv_instr::VMSGTU_VX, + riscv_instr::VMSGT_VX, + riscv_instr::VMIN_VX, + riscv_instr::VMINU_VX, + riscv_instr::VMAX_VX, + riscv_instr::VMAXU_VX, + riscv_instr::VMUL_VX, + riscv_instr::VMULH_VX, + riscv_instr::VMULHU_VX, + riscv_instr::VMULHSU_VX, + riscv_instr::VMACC_VX, + riscv_instr::VNMSAC_VX, + riscv_instr::VMADD_VX, + riscv_instr::VNMSUB_VX, + riscv_instr::VDIV_VX, + riscv_instr::VDIVU_VX, + riscv_instr::VREM_VX, + riscv_instr::VREMU_VX, + riscv_instr::VWMUL_VX, + riscv_instr::VWMULU_VX, + riscv_instr::VWMULSU_VX, + riscv_instr::VWMACC_VX, + riscv_instr::VWMACCU_VX, + riscv_instr::VWMACCSU_VX, + riscv_instr::VWMACCUS_VX, + riscv_instr::VMV_V_X, + riscv_instr::VMV_S_X, + riscv_instr::VSLIDEUP_VX, + riscv_instr::VSLIDEDOWN_VX, + riscv_instr::VSLIDE1UP_VX, + riscv_instr::VSLIDE1DOWN_VX: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr; + opa_select = Reg; + acc_register_rd = 1'b0; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::VFADD_VF, + riscv_instr::VFSUB_VF, + riscv_instr::VFMIN_VF, + riscv_instr::VFMAX_VF, + riscv_instr::VFSGNJ_VF, + riscv_instr::VFSGNJN_VF, + riscv_instr::VFSGNJX_VF, + riscv_instr::VFSLIDE1UP_VF, + riscv_instr::VFSLIDE1DOWN_VF, + riscv_instr::VFMV_V_F, + riscv_instr::VFMV_S_F, + riscv_instr::VFMUL_VF, + riscv_instr::VFRSUB_VF, + riscv_instr::VFMADD_VF, + riscv_instr::VFNMADD_VF, + riscv_instr::VFMSUB_VF, + riscv_instr::VFNMSUB_VF, + riscv_instr::VFMACC_VF, + riscv_instr::VFNMACC_VF, + riscv_instr::VFMSAC_VF, + riscv_instr::VFNMSAC_VF, + riscv_instr::VFWADD_VF, + riscv_instr::VFWADD_WF, + riscv_instr::VFWSUB_VF, + riscv_instr::VFWSUB_WF, + riscv_instr::VFWMUL_VF, + riscv_instr::VFWDOTP_VF, + riscv_instr::VFWMACC_VF, + riscv_instr::VFWNMACC_VF, + riscv_instr::VFWMSAC_VF, + riscv_instr::VFWNMSAC_VF: begin + if (RVV && RVF) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b0; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::VLE8_V, + riscv_instr::VLE16_V, + riscv_instr::VLE32_V, + riscv_instr::VLE64_V, + riscv_instr::VLOXEI8_V, + riscv_instr::VLOXEI16_V, + riscv_instr::VLOXEI32_V, + riscv_instr::VLOXEI64_V, + riscv_instr::VLUXEI8_V, + riscv_instr::VLUXEI16_V, + riscv_instr::VLUXEI32_V, + riscv_instr::VLUXEI64_V: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + opa_select = Reg; + acc_register_rd = 1'b0; + end else begin + illegal_inst = 1'b1; + end + end + // 1 source register (rs1) and memory store operation + riscv_instr::VSE8_V, + riscv_instr::VSE16_V, + riscv_instr::VSE32_V, + riscv_instr::VSE64_V, + riscv_instr::VSOXEI8_V, + riscv_instr::VSOXEI16_V, + riscv_instr::VSOXEI32_V, + riscv_instr::VSOXEI64_V, + riscv_instr::VSUXEI8_V, + riscv_instr::VSUXEI16_V, + riscv_instr::VSUXEI32_V, + riscv_instr::VSUXEI64_V: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + opa_select = Reg; + acc_register_rd = 1'b0; + acc_mem_store = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 2 source registers (rs1, rs2) + riscv_instr::VLSE8_V, + riscv_instr::VLSE16_V, + riscv_instr::VLSE32_V, + riscv_instr::VLSE64_V: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + opa_select = Reg; + opb_select = Reg; + acc_register_rd = 1'b0; + end else begin + illegal_inst = 1'b1; + end + end + // 2 source registers (rs1, rs2) and memory store opeeration + riscv_instr::VSSE8_V, + riscv_instr::VSSE16_V, + riscv_instr::VSSE32_V, + riscv_instr::VSSE64_V: begin + if (RVV) begin + write_rd = 1'b0; + uses_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + opa_select = Reg; + opb_select = Reg; + acc_register_rd = 1'b0; + acc_mem_store = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end +`endif +/* end of RVV extension */ + /* Xpulpimg extension */ +`ifdef XPULPIMG_EXTENSION // Post-increment loads/stores riscv_instr::P_LB_IRPOST: begin // Xpulpimg: p.lb rd,iimm(rs1!) if (snitch_pkg::XPULPIMG) begin @@ -1347,7 +1915,447 @@ module snitch illegal_inst = 1'b1; end end +`endif /* end of Xpulpimg extension */ + +/* Floating point instructions */ + + // Offload FP-FP Instructions - fire and forget + // TODO (smach): Check legal rounding modes and issue illegal isn if needed + // Single Precision Floating-Point + riscv_instr::FADD_S, + riscv_instr::FSUB_S, + riscv_instr::FMUL_S, + riscv_instr::FDIV_S, + riscv_instr::FSQRT_S, + riscv_instr::FSGNJ_S, + riscv_instr::FSGNJN_S, + riscv_instr::FSGNJX_S, + riscv_instr::FMIN_S, + riscv_instr::FMAX_S, + riscv_instr::FMADD_S, + riscv_instr::FMSUB_S, + riscv_instr::FNMSUB_S, + riscv_instr::FNMADD_S: begin + if (FP_EN && RVF && (!(inst_data_i inside {riscv_instr::FDIV_S, riscv_instr::FSQRT_S}) || XDivSqrt)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Double Precision Floating-Point + riscv_instr::FADD_D, + riscv_instr::FSUB_D, + riscv_instr::FMUL_D, + riscv_instr::FDIV_D, + riscv_instr::FSQRT_D, + riscv_instr::FSGNJ_D, + riscv_instr::FSGNJN_D, + riscv_instr::FSGNJX_D, + riscv_instr::FMIN_D, + riscv_instr::FMAX_D, + riscv_instr::FMADD_D, + riscv_instr::FMSUB_D, + riscv_instr::FNMSUB_D, + riscv_instr::FNMADD_D: begin + if (FP_EN && RVD && (!(inst_data_i inside {riscv_instr::FDIV_D, riscv_instr::FSQRT_D}) || XDivSqrt)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FCVT_S_D, + riscv_instr::FCVT_D_S: begin + if (FP_EN && RVF && (!(inst_data_i inside {riscv_instr::FDIV_S, riscv_instr::FSQRT_S}) || XDivSqrt)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Half Precision Floating-Point + riscv_instr::FADD_H, + riscv_instr::FSUB_H, + riscv_instr::FMUL_H, + riscv_instr::FDIV_H, + riscv_instr::FSQRT_H, + riscv_instr::FMADD_H, + riscv_instr::FMSUB_H, + riscv_instr::FNMSUB_H, + riscv_instr::FNMADD_H, + riscv_instr::FSGNJ_H, + riscv_instr::FSGNJN_H, + riscv_instr::FSGNJX_H, + riscv_instr::FMIN_H, + riscv_instr::FMAX_H: begin + if (FP_EN && XF16 && fcsr_q.fmode.dst == 1'b0 && + (!(inst_data_i inside {riscv_instr::FDIV_H, riscv_instr::FSQRT_H}) || XDivSqrt)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && XF16ALT && fcsr_q.fmode.dst == 1'b1 && + (!(inst_data_i inside {riscv_instr::FDIV_H, riscv_instr::FSQRT_H}) || XDivSqrt)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FCVT_S_H: begin + if (FP_EN && RVF && XF16 && fcsr_q.fmode.src == 1'b0) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && RVF && XF16ALT && fcsr_q.fmode.src == 1'b1) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FCVT_H_S: begin + if (FP_EN && RVF && XF16 && fcsr_q.fmode.dst == 1'b0) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && RVF && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FCVT_D_H: begin + if (FP_EN && RVD && XF16 && fcsr_q.fmode.src == 1'b0) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && RVD && XF16ALT && fcsr_q.fmode.src == 1'b1) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FCVT_H_D: begin + if (FP_EN && RVD && XF16 && fcsr_q.fmode.dst == 1'b0) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && RVD && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Byte Precision Floating-Point + riscv_instr::FADD_B, + riscv_instr::FSUB_B, + riscv_instr::FMUL_B, + riscv_instr::FDIV_B, + riscv_instr::FSQRT_B, + riscv_instr::FSGNJ_B, + riscv_instr::FSGNJN_B, + riscv_instr::FSGNJX_B, + riscv_instr::FMIN_B, + riscv_instr::FMAX_B, + riscv_instr::FMADD_B, + riscv_instr::FMSUB_B, + riscv_instr::FNMSUB_B, + riscv_instr::FNMADD_B: begin + if (FP_EN && XF8 && fcsr_q.fmode.dst == 1'b0 && (!(inst_data_i inside {riscv_instr::FDIV_B, riscv_instr::FSQRT_B}) || XDivSqrt)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + riscv_instr::FCVT_B_H: begin + if (FP_EN) begin + if ((XF16 && fcsr_q.fmode.src == 1'b0) || + (XF16ALT && fcsr_q.fmode.src == 1'b1)) begin + if ((XF8 && fcsr_q.fmode.dst == 1'b0) || + (XF8ALT && fcsr_q.fmode.dst == 1'b1)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end else begin + illegal_inst = 1'b1; + end + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FCVT_H_B: begin + if (FP_EN) begin + if ((XF8 && fcsr_q.fmode.src == 1'b0) || + (XF8ALT && fcsr_q.fmode.src == 1'b1)) begin + if ((XF16 && fcsr_q.fmode.dst == 1'b0) || + (XF16ALT && fcsr_q.fmode.dst == 1'b1)) begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end else begin + illegal_inst = 1'b1; + end + end else begin + illegal_inst = 1'b1; + end + end + + // double precision floating-point + riscv_instr::FCLASS_D, + riscv_instr::FLE_D, + riscv_instr::FLT_D, + riscv_instr::FEQ_D, + riscv_instr::FCVT_W_D, + riscv_instr::FCVT_WU_D: begin + if (FP_EN && RVD) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_register_rd = 1'b1; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // single precision floating-point + riscv_instr::FCLASS_S, + riscv_instr::FLE_S, + riscv_instr::FLT_S, + riscv_instr::FEQ_S, + riscv_instr::FMV_X_S, + riscv_instr::FCVT_W_S, + riscv_instr::FCVT_WU_S, + riscv_instr::FMV_X_W: begin + if (FP_EN && RVF) begin + acc_register_rd = 1'b1; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // half precision floating-point + riscv_instr::FCLASS_H, + riscv_instr::FLE_H, + riscv_instr::FLT_H, + riscv_instr::FEQ_H, + riscv_instr::FMV_X_H, + riscv_instr::FCVT_W_H, + riscv_instr::FCVT_WU_H: begin + if (FP_EN && XF16 && fcsr_q.fmode.src == 1'b0) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_register_rd = 1'b1; + acc_qvalid_o = valid_instr; + end else if (FP_EN && XF16ALT && fcsr_q.fmode.src == 1'b1) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard + end else begin + illegal_inst = 1'b1; + end + end + + // Byte Precision Floating-Point + riscv_instr::FCLASS_B, + riscv_instr::FLE_B, + riscv_instr::FLT_B, + riscv_instr::FEQ_B, + riscv_instr::FMV_X_B, + riscv_instr::FCVT_W_B, + riscv_instr::FCVT_WU_B: begin + if (FP_EN && XF8 && fcsr_q.fmode.src == 1'b0) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard + end else if (FP_EN && XF8ALT && fcsr_q.fmode.src == 1'b1) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard + end else begin + illegal_inst = 1'b1; + end + end + + // Double Precision Floating-Point + riscv_instr::FMV_D_X, + riscv_instr::FCVT_D_W, + riscv_instr::FCVT_D_WU: begin + if (FP_EN && RVD) begin + opa_select = Reg; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Single Precision Floating-Point + // riscv_instr::FMV_S_X, + riscv_instr::FMV_W_X, + riscv_instr::FCVT_S_W, + riscv_instr::FCVT_S_WU: begin + if (FP_EN && RVF) begin + opa_select = Reg; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Half Precision Floating-Point + riscv_instr::FMV_H_X, + riscv_instr::FCVT_H_W, + riscv_instr::FCVT_H_WU: begin + if (FP_EN && XF16 && (fcsr_q.fmode.dst == 1'b0)) begin + opa_select = Reg; + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && XF16ALT && (fcsr_q.fmode.dst == 1'b1)) begin + opa_select = Reg; + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Byte Precision Floating-Point + riscv_instr::FMV_B_X, + riscv_instr::FCVT_B_W, + riscv_instr::FCVT_B_WU: begin + if (FP_EN && XF8 && fcsr_q.fmode.dst == 1'b0) begin + opa_select = Reg; + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else if (FP_EN && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin + opa_select = Reg; + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end else begin + illegal_inst = 1'b1; + end + end + + // Floating-Point Load/Store + // Single Precision Floating-Point + riscv_instr::FLW: begin + if (FP_EN && RVF) begin + opa_select = Reg; + opb_select = IImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = Word; + is_fp_load = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FSW: begin + if (FP_EN && RVF) begin + opa_select = Reg; + opb_select = SFImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = Word; + is_fp_store = 1'b1; + acc_mem_store = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // Double Precision Floating-Point + riscv_instr::FLD: begin + if (FP_EN && (RVD || XFVEC)) begin + opa_select = Reg; + opb_select = IImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = Double; + is_fp_load = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FSD: begin + if (FP_EN && (RVD || XFVEC)) begin + opa_select = Reg; + opb_select = SFImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = Double; + is_fp_store = 1'b1; + acc_mem_store = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // Half Precision Floating-Point + riscv_instr::FLH: begin + if (FP_EN && (XF16 || XF16ALT)) begin + opa_select = Reg; + opb_select = IImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = HalfWord; + is_fp_load = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FSH: begin + if (FP_EN && (XF16 || XF16ALT)) begin + opa_select = Reg; + opb_select = SFImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = HalfWord; + is_fp_store = 1'b1; + acc_mem_store = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // Quarter Precision Floating-Point + riscv_instr::FLB: begin + if (FP_EN && (XF8 || XF8ALT)) begin + opa_select = Reg; + opb_select = IImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = Byte; + is_fp_load = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::FSB: begin + if (FP_EN && (XF8 || XF8ALT)) begin + opa_select = Reg; + opb_select = SFImmediate; + write_rd = 1'b0; + acc_qvalid_o = valid_instr && !acc_mem_stall; + ls_size = Byte; + is_fp_store = 1'b1; + acc_mem_store = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + +/* end of floating point instructions */ + // TODO(zarubaf): Illegal Instructions default: begin @@ -1392,6 +2400,12 @@ module snitch csr_dump = 1'b0; csr_trace_en = 1'b0; csr_stack_limit_en = 1'b0; + read_fcsr = 1'b0; + + fcsr_d = fcsr_q; + if (FP_EN) begin + fcsr_d.fflags = fcsr_q.fflags | fpu_status_i; + end // TODO(zarubaf): Needs some more input handling, like illegal instruction exceptions. // Right now we skip this due to simplicity. @@ -1433,6 +2447,37 @@ module snitch csr_rvalue = stall_raw_q[31:0]; end `endif + `ifdef TARGET_SPATZ + // F/D Extension + riscv_instr::CSR_FFLAGS: begin + if (FP_EN) begin + csr_rvalue = {27'b0, fcsr_d.fflags}; + read_fcsr = 1'b1; + if (!exception && !acc_stall) fcsr_d.fflags = fpnew_pkg::status_t'(alu_result[4:0]); + end + end + riscv_instr::CSR_FRM: begin + if (FP_EN) begin + csr_rvalue = {29'b0, fcsr_d.frm}; + read_fcsr = 1'b1; + if (!exception && !acc_stall) fcsr_d.frm = fpnew_pkg::roundmode_e'(alu_result[2:0]); + end + end + riscv_instr::CSR_FMODE: begin + if (FP_EN) begin + csr_rvalue = {30'b0, fcsr_q.fmode}; + read_fcsr = 1'b1; + if (!exception && !acc_stall) fcsr_d.fmode = fpnew_pkg::fmt_mode_t'(alu_result[1:0]); + end + end + riscv_instr::CSR_FCSR: begin + if (FP_EN) begin + csr_rvalue = {22'b0, fcsr_d}; + read_fcsr = 1'b1; + if (!exception && !acc_stall) fcsr_d = fcsr_t'(alu_result[9:0]); + end + end + `endif default: begin csr_rvalue = '0; csr_dump = 1'b1; @@ -1498,7 +2543,9 @@ module snitch PC: opb = pc_q; CSR: opb = csr_rvalue; PBImmediate: opb = pbimm; +`ifdef XPULPIMG_EXTENSION RegRd: opb = gpr_rdata[2]; +`endif default: opb = '0; endcase end @@ -1606,8 +2653,8 @@ module snitch .clk_i , .rst_i , .lsu_qtag_i ( rd ), - .lsu_qwrite ( is_store ), - .lsu_qsigned ( is_signed ), + .lsu_qwrite_i ( is_store ), + .lsu_qsigned_i( is_signed ), .lsu_qaddr_i ( lsu_qaddr ), .lsu_qdata_i ( gpr_rdata[1] ), .lsu_qsize_i ( ls_size ), @@ -1634,10 +2681,50 @@ module snitch .data_pready_o ); +`ifdef TARGET_SPATZ + // Number of memory operations in the accelerator + logic [2:0] acc_mem_cnt_q, acc_mem_cnt_d; + `FFAR(acc_mem_cnt_q, acc_mem_cnt_d, '0, clk_i, rst_i) + + // Number of store operations in the accelerator + logic [2:0] acc_mem_str_cnt_q, acc_mem_str_cnt_d; + `FFAR(acc_mem_str_cnt_q, acc_mem_str_cnt_d, '0, clk_i, rst_i) + + assign acc_mem_stall = (is_store && acc_mem_cnt_q != '0) || (is_load && acc_mem_str_cnt_q != 0) || acc_mem_cnt_q == '1; + + always_comb begin + acc_mem_cnt_d = acc_mem_cnt_q; + acc_mem_str_cnt_d = acc_mem_str_cnt_q; + + if (acc_qdata_rsp_i.loadstore && acc_qready_i && acc_qvalid_o) + acc_mem_cnt_d += 1; + if (acc_mem_finished_i[0]) + acc_mem_cnt_d -= 1; + if (acc_mem_finished_i[1]) + acc_mem_cnt_d -= 1; + + if (acc_qdata_rsp_i.loadstore && acc_qready_i && acc_qvalid_o && acc_mem_store) + acc_mem_str_cnt_d += 1; + if (acc_mem_finished_i[0] && acc_mem_str_finished_i[0]) + acc_mem_str_cnt_d -= 1; + if (acc_mem_finished_i[1] && acc_mem_str_finished_i[1]) + acc_mem_str_cnt_d -= 1; + end + + `ASSERT(MemoryOperationCounterRollover, + acc_mem_cnt_q == '0 |=> acc_mem_cnt_q != '1, clk_i, rst_i) + + `ASSERT(MemoryStoreOperationCounterRollover, + acc_mem_str_cnt_q == '0 |=> acc_mem_str_cnt_q != '1, clk_i, rst_i) + + // address can be alu_result (i.e. rs1 + iimm/simm) or rs1 (for post-increment load/stores) + assign lsu_qaddr = is_postincr ? gpr_rdata[0] : alu_result; + assign lsu_qvalid = valid_instr & (is_load | is_store) & ~(ld_addr_misaligned | st_addr_misaligned) & ~acc_mem_stall; +`else // address can be alu_result (i.e. rs1 + iimm/simm) or rs1 (for post-increment load/stores) assign lsu_qaddr = is_postincr ? gpr_rdata[0] : alu_result; - assign lsu_qvalid = valid_instr & (is_load | is_store) & ~(ld_addr_misaligned | st_addr_misaligned); +`endif // NOTE(smazzola): write-backs "on rd from non-load or non-acc instructions" and "on rs1 from // post-increment instructions" in the same cycle should be mutually exclusive (currently valid @@ -1713,7 +2800,7 @@ module snitch gpr_we[0] = 1'b1; gpr_waddr[0] = lsu_rd; gpr_wdata[0] = ld_result[31:0]; - end else if (acc_pvalid_i) begin + end else if (acc_pvalid_i & acc_pwrite_i) begin // if we are not retiring another instruction retire the accelerated one now retire_acc = 1'b1; gpr_we[0] = 1'b1; @@ -1734,8 +2821,12 @@ module snitch gpr_waddr[1] = lsu_rd; gpr_wdata[1] = ld_result[31:0]; // external interfaces - // Snitch and LSU have priority + // Snitch and LSU have priority if Spatz is not used + `ifdef TARGET_SPATZ + lsu_pready = 1'b0; + `else lsu_pready = 1'b1; + `endif acc_pready_o = 1'b0; retire_acc = 1'b0; retire_load = 1'b0; @@ -1745,7 +2836,8 @@ module snitch if (lsu_pvalid) begin retire_load = 1'b1; gpr_we[1] = 1'b1; - end else if (acc_pvalid_i) begin + lsu_pready = 1'b1; + end else if (acc_pvalid_i & acc_pwrite_i) begin retire_acc = 1'b1; gpr_we[1] = 1'b1; gpr_waddr[1] = acc_pid_i; @@ -1754,7 +2846,7 @@ module snitch end // if we are not retiring another instruction retire the load now end else begin - if (acc_pvalid_i) begin + if (acc_pvalid_i & acc_pwrite_i) begin retire_acc = 1'b1; gpr_we[0] = 1'b1; gpr_waddr[0] = acc_pid_i; @@ -1764,6 +2856,7 @@ module snitch if (lsu_pvalid) begin retire_load = 1'b1; gpr_we[1] = 1'b1; + lsu_pready = 1'b1; end end end diff --git a/hardware/deps/snitch/src/snitch_lsu.sv b/hardware/deps/snitch/src/snitch_lsu.sv index 5496b07a6..7344b0c62 100644 --- a/hardware/deps/snitch/src/snitch_lsu.sv +++ b/hardware/deps/snitch/src/snitch_lsu.sv @@ -14,6 +14,8 @@ module snitch_lsu parameter type dreq_t = logic, parameter type drsp_t = logic, parameter int unsigned NumOutstandingLoads = 1, + // unused here, always 32 in MemPool + parameter int unsigned DataWidth = 32, parameter bit NaNBox = 0, // Dependent parameters. DO NOT CHANGE. localparam int unsigned IdWidth = idx_width(NumOutstandingLoads) diff --git a/hardware/deps/snitch/src/snitch_md.sv b/hardware/deps/snitch/src/snitch_md.sv deleted file mode 100644 index 1f89bf764..000000000 --- a/hardware/deps/snitch/src/snitch_md.sv +++ /dev/null @@ -1,2937 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: Florian Zaruba -// Sergio Mazzola -// Description: Top-Level of Snitch Integer Core RV32E - -`include "common_cells/registers.svh" -`include "common_cells/assertions.svh" - -// `SNITCH_ENABLE_PERF Enables mcycle, minstret performance counters (read only) -// `SNITCH_ENABLE_STALL_COUNTER Enables stall_ins, stall_raw, stall_lsu performance counters (read only) - -module snitch_md - import snitch_pkg::meta_id_t; -#( - parameter logic [31:0] BootAddr = 32'h0000_1000, - parameter logic [31:0] MTVEC = BootAddr, // Exception Base Address (see privileged spec 3.1.7) - parameter bit RVE = 0, // Reduced-register Extension - parameter bit RVM = 1, // Enable IntegerMmultiplication & Division Extension - - parameter bit RVV = 1, // Enable Vector Extension - parameter bit XFVEC = 0, - parameter bit XFDOTP = 0, - parameter bit XFAUX = 0, - /// Enable F Extension. - parameter bit RVF = 0, - /// Enable D Extension. - parameter bit RVD = 0, - parameter bit XF16 = 0, - parameter bit XF16ALT = 0, - parameter bit XF8 = 0, - parameter bit XF8ALT = 0, - /// Enable div/sqrt unit (buggy - use with caution) - parameter bit XDivSqrt = 0, - parameter int RegNrWritePorts = 2, // Implement one or two write ports into the register file - parameter type acc_issue_rsp_t = logic, - // Dependant parameters. - localparam bit FP_EN = RVF || RVD // Enable FP in general -) ( - input logic clk_i, - input logic rst_i, - input logic [31:0] hart_id_i, - // Instruction Refill Port - output logic [31:0] inst_addr_o, - input logic [31:0] inst_data_i, - output logic inst_valid_o, - input logic inst_ready_i, -`ifdef RISCV_FORMAL - output logic [0:0] rvfi_valid, - output logic [0:0][63:0] rvfi_order, - output logic [0:0][31:0] rvfi_insn, - output logic [0:0] rvfi_trap, - output logic [0:0] rvfi_halt, - output logic [0:0] rvfi_intr, - output logic [0:0][1:0] rvfi_mode, - output logic [0:0][4:0] rvfi_rs1_addr, - output logic [0:0][4:0] rvfi_rs2_addr, - output logic [0:0][31:0] rvfi_rs1_rdata, - output logic [0:0][31:0] rvfi_rs2_rdata, - output logic [0:0][4:0] rvfi_rd_addr, - output logic [0:0][31:0] rvfi_rd_wdata, - output logic [0:0][31:0] rvfi_pc_rdata, - output logic [0:0][31:0] rvfi_pc_wdata, - output logic [0:0][31:0] rvfi_mem_addr, - output logic [0:0][3:0] rvfi_mem_rmask, - output logic [0:0][3:0] rvfi_mem_wmask, - output logic [0:0][31:0] rvfi_mem_rdata, - output logic [0:0][31:0] rvfi_mem_wdata, -`endif - /// Accelerator Interface - Master Port - /// Independent channels for transaction request and read completion. - /// AXI-like handshaking. - /// Same IDs need to be handled in-order. - output logic [31:0] acc_qaddr_o, -`ifdef TARGET_SPATZ - output logic [5:0] acc_qid_o, // what should be the id width, 5 or 6? - input logic [5:0] acc_pid_i, -`else - output logic [4:0] acc_qid_o, // what should be the id width, 5 or 6? - input logic [4:0] acc_pid_i, -`endif - output logic [31:0] acc_qdata_op_o, - output logic [31:0] acc_qdata_arga_o, - output logic [31:0] acc_qdata_argb_o, - output logic [31:0] acc_qdata_argc_o, - output logic acc_qvalid_o, - input logic acc_qready_i, - input logic [31:0] acc_pdata_i, - input logic acc_pwrite_i, - input logic acc_perror_i, - input logic acc_pvalid_i, - output logic acc_pready_o, - input acc_issue_rsp_t acc_qdata_rsp_i, - input logic [1:0] acc_mem_finished_i, - input logic [1:0] acc_mem_str_finished_i, - /// TCDM Data Interface - /// Write transactions do not return data on the `P Channel` - /// Transactions need to be handled strictly in-order. - output logic [31:0] data_qaddr_o, - output logic data_qwrite_o, - output logic [3:0] data_qamo_o, - output logic [31:0] data_qdata_o, - output logic [3:0] data_qstrb_o, - output meta_id_t data_qid_o, - output logic data_qvalid_o, - input logic data_qready_i, - input logic [31:0] data_pdata_i, - input logic data_perror_i, - input meta_id_t data_pid_i, - input logic data_pvalid_i, - output logic data_pready_o, - input logic wake_up_sync_i, // synchronous wake-up interrupt - // FPU **un-timed** Side-channel - output fpnew_pkg::roundmode_e fpu_rnd_mode_o, - output fpnew_pkg::fmt_mode_t fpu_fmt_mode_o, - input fpnew_pkg::status_t fpu_status_i, - // Core event strobes - output snitch_pkg::core_events_t core_events_o -); - - localparam int RegWidth = RVE ? 4 : 5; - localparam int RegNrReadPorts = snitch_pkg::XPULPIMG ? 3 : 2; - localparam logic [RegWidth-1:0] SP = 2; - localparam int OutstandingWfi = 8; - - logic illegal_inst; - logic zero_lsb; - - // Instruction fetch - logic [31:0] pc_d, pc_q; - logic wfi_d, wfi_q; - logic [$clog2(OutstandingWfi)-1:0] wake_up_d, wake_up_q; - logic [31:0] consec_pc; - // Immediates - logic [31:0] iimm, uimm, jimm, bimm, simm, pbimm; - /* verilator lint_off WIDTH */ - assign iimm = $signed({inst_data_i[31:20]}); - assign uimm = {inst_data_i[31:12], 12'b0}; - assign jimm = $signed({inst_data_i[31], - inst_data_i[19:12], inst_data_i[20], inst_data_i[30:21], 1'b0}); - assign bimm = $signed({inst_data_i[31], - inst_data_i[7], inst_data_i[30:25], inst_data_i[11:8], 1'b0}); - assign simm = $signed({inst_data_i[31:25], inst_data_i[11:7]}); - assign pbimm = $signed(inst_data_i[24:20]); // Xpulpimg immediate branching signed immediate - /* verilator lint_on WIDTH */ - - logic [31:0] opa, opb; - logic [32:0] adder_result; - logic [31:0] alu_result; - - logic [RegWidth-1:0] rd, rs1, rs2; - logic stall, lsu_stall; - // Register connections - logic [RegNrReadPorts-1:0][RegWidth-1:0] gpr_raddr; - logic [RegNrReadPorts-1:0][31:0] gpr_rdata; - logic [RegNrWritePorts-1:0][RegWidth-1:0] gpr_waddr; - logic [RegNrWritePorts-1:0][31:0] gpr_wdata; - logic [RegNrWritePorts-1:0] gpr_we; - logic [2**RegWidth-1:0] sb_d, sb_q; - - // Load/Store Defines - logic is_load, is_store, is_signed, is_postincr; - logic is_fp_load, is_fp_store; - logic ls_misaligned; - logic ld_addr_misaligned; - logic st_addr_misaligned; - - enum logic [1:0] { - Byte = 2'b00, - HalfWord = 2'b01, - Word = 2'b10, - Double = 2'b11 - } ls_size; - - enum logic [3:0] { - AMONone = 4'h0, - AMOSwap = 4'h1, - AMOAdd = 4'h2, - AMOAnd = 4'h3, - AMOOr = 4'h4, - AMOXor = 4'h5, - AMOMax = 4'h6, - AMOMaxu = 4'h7, - AMOMin = 4'h8, - AMOMinu = 4'h9, - AMOLR = 4'hA, - AMOSC = 4'hB - } ls_amo; - - logic [31:0] ld_result; - logic lsu_qready, lsu_qvalid; - logic lsu_pvalid, lsu_pready; - logic [RegWidth-1:0] lsu_rd; - logic [31:0] lsu_qaddr; - - - logic retire_load; // retire a load instruction - logic retire_p; // retire from post-increment instructions - logic retire_i; // retire the rest of the base instruction set - logic retire_acc; // retire an instruction we offloaded - - logic acc_stall; - logic valid_instr; - logic exception; - - // ALU Operations - enum logic [3:0] { - // Arithmetical operations - Add, Sub, - // Shifts - Sll, Srl, Sra, - // Logical operations - LXor, LOr, LAnd, LNAnd, - // Comparisons - Eq, Neq, Ge, Geu, - Slt, Sltu, - // Miscellaneous - BypassA - } alu_op; - - enum logic [3:0] { - None, Reg, IImmediate, UImmediate, JImmediate, SImmediate, SFImmediate, PC, CSR, CSRImmediate, PBImmediate, RegRd, RegRs2 - } opa_select, opb_select, opc_select; - - logic write_rd; // write rd destination this cycle - logic uses_rd; - logic write_rs1; // write rs1 destination this cycle - logic uses_rs1; - enum logic [1:0] {Consec, Alu, Exception} next_pc; - - enum logic [1:0] {RdAlu, RdConsecPC, RdBypass} rd_select; - logic [31:0] rd_bypass; - - logic is_branch; - - logic [31:0] csr_rvalue; - logic csr_en; - - typedef struct packed { - fpnew_pkg::fmt_mode_t fmode; - fpnew_pkg::roundmode_e frm; - fpnew_pkg::status_t fflags; - } fcsr_t; - fcsr_t fcsr_d, fcsr_q; - // Current instruction needs fcsr - logic read_fcsr; - - assign fpu_rnd_mode_o = fcsr_q.frm; - assign fpu_fmt_mode_o = fcsr_q.fmode; - - // Registers - `FFAR(pc_q, pc_d, BootAddr, clk_i, rst_i) - `FFAR(wfi_q, wfi_d, '0, clk_i, rst_i) - `FFAR(wake_up_q, wake_up_d, '0, clk_i, rst_i) - `FFAR(sb_q, sb_d, '0, clk_i, rst_i) - `FFAR(fcsr_q, fcsr_d, '0, clk_i, rst_i) - - always_comb begin - core_events_o = '0; - core_events_o.retired_insts = ~stall; - end - - // accelerator offloading interface - // register int destination in scoreboard - logic acc_register_rd; - // LSU stalling due to accelerator memory requests - logic acc_mem_stall; - // Offloaded mem operation is a store operation - logic acc_mem_store; - - assign acc_qaddr_o = hart_id_i; - assign acc_qid_o = rd; - assign acc_qdata_op_o = inst_data_i; - assign acc_qdata_arga_o = {{32{gpr_rdata[0][31]}}, gpr_rdata[0]}; - // assign acc_qdata_argb_o = {{32{gpr_rdata[1][31]}}, gpr_rdata[1]}; - assign acc_qdata_argb_o = opb_select inside {IImmediate, SImmediate} ? - {{32{alu_result[31]}}, alu_result} : {{32{gpr_rdata[1][31]}}, gpr_rdata[1]}; - -`ifdef XPULPIMG_EXTENSION - assign acc_qdata_argc_o = gpr_rdata[2]}; -`else - assign acc_qdata_argc_o = '0; -`endif - - - // instruction fetch interface - assign inst_addr_o = pc_q; - assign inst_valid_o = ~wfi_q; - - // -------------------- - // Control - // -------------------- - // Scoreboard: Keep track of rd dependencies (only loads at the moment) - logic operands_ready; - logic dst_ready; - logic opa_ready, opb_ready, opc_ready; - logic dstrd_ready, dstrs1_ready; - - always_comb begin - sb_d = sb_q; - if (retire_load) sb_d[lsu_rd] = 1'b0; - // only place the reservation if we actually executed the load or offload instruction - if ((is_load | acc_register_rd) && !stall && !exception) sb_d[rd] = 1'b1; - if (retire_acc) sb_d[acc_pid_i[RegWidth-1:0]] = 1'b0; - sb_d[0] = 1'b0; - end - // TODO(zarubaf): This can probably be described a bit more efficient - assign opa_ready = (opa_select != Reg) | ~sb_q[rs1]; - assign opb_ready = ((opb_select != Reg & opb_select != SImmediate) | ~sb_q[rs2]) & ((opb_select != RegRd) | ~sb_q[rd]); - assign opc_ready = ((opc_select != Reg) | ~sb_q[rd]) & ((opc_select != RegRs2) | ~sb_q[rs2]); - assign operands_ready = opa_ready & opb_ready & opc_ready; - // either we are not using the destination register or we need to make - // sure that its destination operand is not marked busy in the scoreboard. - assign dstrd_ready = ~uses_rd | (uses_rd & ~sb_q[rd]); - assign dstrs1_ready = ~uses_rs1 | (uses_rs1 & ~sb_q[rs1]); - assign dst_ready = dstrd_ready & dstrs1_ready; - - assign valid_instr = (inst_ready_i & inst_valid_o) & operands_ready & dst_ready; - // the accelerator interface stalled us - assign acc_stall = (acc_qvalid_o & ~acc_qready_i) || (read_fcsr && acc_qdata_rsp_i.isfloat); - // the LSU Interface didn't accept our request yet - assign lsu_stall = (lsu_qvalid & ~lsu_qready) | acc_mem_stall; - // Stall the stage if we either didn't get a valid instruction or the LSU/Accelerator is not ready - assign stall = ~valid_instr | lsu_stall | acc_stall; - - // -------------------- - // Instruction Frontend - // -------------------- - assign consec_pc = pc_q + ((is_branch & alu_result[0]) ? bimm : 'd4); - - always_comb begin - pc_d = pc_q; - // if we got a valid instruction word increment the PC unless we are waiting for an event - if (!stall && !wfi_q) begin - casez (next_pc) - Consec: pc_d = consec_pc; - Alu: pc_d = alu_result & {{31{1'b1}}, ~zero_lsb}; - Exception: pc_d = MTVEC; - endcase - end - end - - // -------------------- - // Performance Counter - // -------------------- - - `ifdef SNITCH_ENABLE_PERF - logic [63:0] cycle_q; - logic [63:0] instret_q; - `FFAR(cycle_q, cycle_q + 1, '0, clk_i, rst_i); - `FFLAR(instret_q, instret_q + 1, !stall, '0, clk_i, rst_i); - `endif - - `ifdef SNITCH_ENABLE_STALL_COUNTER - logic [31:0] stall_ins_q; - logic [31:0] stall_raw_q; - logic [31:0] stall_lsu_q; - `FFLAR(stall_ins_q, stall_ins_q + 1, stall && (!inst_ready_i) && inst_valid_o, '0, clk_i, rst_i) - `FFLAR(stall_raw_q, stall_raw_q + 1, (!operands_ready) || (!dst_ready), '0, clk_i, rst_i) - `FFLAR(stall_lsu_q, stall_lsu_q + 1, lsu_stall, '0, clk_i, rst_i) - `endif - - - // -------------------- - // Decoder - // -------------------- - assign rd = inst_data_i[7 + RegWidth - 1:7]; - assign rs1 = inst_data_i[15 + RegWidth - 1:15]; - assign rs2 = inst_data_i[20 + RegWidth - 1:20]; - - always_comb begin - illegal_inst = 1'b0; - alu_op = Add; - opa_select = None; - opb_select = None; - opc_select = None; - - next_pc = Consec; - - // set up rd destination - rd_select = RdAlu; - write_rd = 1'b1; - // if we are writing the field this cycle we need an int destination register - uses_rd = write_rd; - // set up rs1 destination - write_rs1 = 1'b0; - uses_rs1 = write_rs1; - - rd_bypass = '0; - zero_lsb = 1'b0; - is_branch = 1'b0; - // LSU interface - is_load = 1'b0; - is_store = 1'b0; - is_postincr = 1'b0; - is_fp_load = 1'b0; - is_fp_store = 1'b0; - is_signed = 1'b0; - ls_size = Byte; - ls_amo = AMONone; - - acc_qvalid_o = 1'b0; - acc_register_rd = 1'b0; - acc_mem_store = 1'b0; - - csr_en = 1'b0; - // Wake up if a wake-up is incoming or pending - wfi_d = (wake_up_q || wake_up_sync_i) ? 1'b0 : wfi_q; - // Only store a pending wake-up if we are not asleep - wake_up_d = (wake_up_sync_i && !wfi_q) ? wake_up_q + 1 : wake_up_q; - - unique casez (inst_data_i) - riscv_instr::ADD: begin - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::ADDI: begin - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::SUB: begin - alu_op = Sub; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::XOR: begin - opa_select = Reg; - opb_select = Reg; - alu_op = LXor; - end - riscv_instr::XORI: begin - alu_op = LXor; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::OR: begin - opa_select = Reg; - opb_select = Reg; - alu_op = LOr; - end - riscv_instr::ORI: begin - alu_op = LOr; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::AND: begin - alu_op = LAnd; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::ANDI: begin - alu_op = LAnd; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::SLT: begin - alu_op = Slt; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::SLTI: begin - alu_op = Slt; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::SLTU: begin - alu_op = Sltu; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::SLTIU: begin - alu_op = Sltu; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::SLL: begin - alu_op = Sll; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::SRL: begin - alu_op = Srl; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::SRA: begin - alu_op = Sra; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::SLLI: begin - alu_op = Sll; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::SRLI: begin - alu_op = Srl; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::SRAI: begin - alu_op = Sra; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::LUI: begin - opa_select = None; - opb_select = None; - rd_select = RdBypass; - rd_bypass = uimm; - end - riscv_instr::AUIPC: begin - opa_select = UImmediate; - opb_select = PC; - end - riscv_instr::JAL: begin - rd_select = RdConsecPC; - opa_select = JImmediate; - opb_select = PC; - next_pc = Alu; - end - riscv_instr::JALR: begin - rd_select = RdConsecPC; - opa_select = Reg; - opb_select = IImmediate; - next_pc = Alu; - zero_lsb = 1'b1; - end - // use the ALU for comparisons - riscv_instr::BEQ: begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Eq; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::BNE: begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Neq; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::BLT: begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Slt; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::BLTU: begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Sltu; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::BGE: begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Ge; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::BGEU: begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Geu; - opa_select = Reg; - opb_select = Reg; - end - // Load/Stores - riscv_instr::SB: begin - write_rd = 1'b0; - is_store = 1'b1; - opa_select = Reg; - opb_select = SImmediate; - end - riscv_instr::SH: begin - write_rd = 1'b0; - is_store = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = SImmediate; - end - riscv_instr::SW: begin - write_rd = 1'b0; - is_store = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = SImmediate; - end - riscv_instr::LB: begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::LH: begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::LW: begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::LBU: begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - opa_select = Reg; - opb_select = IImmediate; - end - riscv_instr::LHU: begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = IImmediate; - end - // CSR Instructions - riscv_instr::CSRRW: begin // Atomic Read/Write CSR - unique case (inst_data_i[31:20]) -`ifdef TARGET_SPATZ - riscv_instr::CSR_VSTART, - riscv_instr::CSR_VL, - riscv_instr::CSR_VTYPE, - riscv_instr::CSR_VLENB, - riscv_instr::CSR_VXSAT, - riscv_instr::CSR_VXRM, - riscv_instr::CSR_VCSR: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = rd != 0; - acc_qvalid_o = valid_instr; - opa_select = Reg; - acc_register_rd = rd != 0; - end else begin - illegal_inst = 1'b1; - end - end -`endif - default: begin - opa_select = Reg; - opb_select = None; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end - endcase - end - riscv_instr::CSRRWI: begin - unique case (inst_data_i[31:20]) -`ifdef TARGET_SPATZ - riscv_instr::CSR_VSTART, - riscv_instr::CSR_VL, - riscv_instr::CSR_VTYPE, - riscv_instr::CSR_VLENB, - riscv_instr::CSR_VXSAT, - riscv_instr::CSR_VXRM, - riscv_instr::CSR_VCSR: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = rd != 0; - acc_qvalid_o = valid_instr; - acc_register_rd = rd != 0; - end else begin - illegal_inst = 1'b1; - end - end -`endif - default: begin - opa_select = CSRImmediate; - opb_select = None; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end - endcase - end - riscv_instr::CSRRS: begin // Atomic Read and Set Bits in CSR - unique case (inst_data_i[31:20]) -`ifdef TARGET_SPATZ - riscv_instr::CSR_VSTART, - riscv_instr::CSR_VL, - riscv_instr::CSR_VTYPE, - riscv_instr::CSR_VLENB, - riscv_instr::CSR_VXSAT, - riscv_instr::CSR_VXRM, - riscv_instr::CSR_VCSR: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end -`endif - default: begin - alu_op = LOr; - opa_select = Reg; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end - endcase - end - riscv_instr::CSRRSI: begin - unique case (inst_data_i[31:20]) -`ifdef TARGET_SPATZ - riscv_instr::CSR_VSTART, - riscv_instr::CSR_VL, - riscv_instr::CSR_VTYPE, - riscv_instr::CSR_VLENB, - riscv_instr::CSR_VXSAT, - riscv_instr::CSR_VXRM, - riscv_instr::CSR_VCSR: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end -`endif - snitch_pkg::CSR_SSR: begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end - default: begin - alu_op = LOr; - opa_select = CSRImmediate; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end - endcase - end - riscv_instr::CSRRC: begin // Atomic Read and Clear Bits in CSR - unique case (inst_data_i[31:20]) -`ifdef TARGET_SPATZ - riscv_instr::CSR_VSTART, - riscv_instr::CSR_VL, - riscv_instr::CSR_VTYPE, - riscv_instr::CSR_VLENB, - riscv_instr::CSR_VXSAT, - riscv_instr::CSR_VXRM, - riscv_instr::CSR_VCSR: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end -`endif - default: begin - alu_op = LNAnd; - opa_select = Reg; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end - endcase - end - riscv_instr::CSRRCI: begin - unique case (inst_data_i[31:20]) -`ifdef TARGET_SPATZ - riscv_instr::CSR_VSTART, - riscv_instr::CSR_VL, - riscv_instr::CSR_VTYPE, - riscv_instr::CSR_VLENB, - riscv_instr::CSR_VXSAT, - riscv_instr::CSR_VXRM, - riscv_instr::CSR_VCSR: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end -`endif - snitch_pkg::CSR_SSR: begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end - default: begin - alu_op = LNAnd; - opa_select = CSRImmediate; - opb_select = CSR; - rd_select = RdBypass; - rd_bypass = csr_rvalue; - csr_en = 1'b1; - end - endcase - end - riscv_instr::ECALL, - riscv_instr::EBREAK: begin - // TODO(zarubaf): Trap to precise address - write_rd = 1'b0; - end - // NOP Instructions - riscv_instr::FENCE: begin - write_rd = 1'b0; - end - riscv_instr::WFI: begin - if (valid_instr) begin - wfi_d = 1'b1; - if (wake_up_q || wake_up_sync_i) begin - // Do not sleep if a wake-up is pending - wfi_d = 1'b0; - if (wake_up_q) begin - // Decrement outstanding wake_up pulses - wake_up_d = wake_up_q - 1; - end - if (wake_up_sync_i) begin - // Keep counter constant due to simultaneous pulse - wake_up_d = wake_up_q; - end - end - end - end - // Atomics - riscv_instr::AMOADD_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOAdd; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOXOR_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOXor; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOOR_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOOr; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOAND_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOAnd; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOMIN_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOMin; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOMAX_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOMax; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOMINU_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOMinu; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOMAXU_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOMaxu; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::AMOSWAP_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOSwap; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::LR_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOLR; - opa_select = Reg; - opb_select = Reg; - end - riscv_instr::SC_W: begin - alu_op = BypassA; - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - ls_amo = AMOSC; - opa_select = Reg; - opb_select = Reg; - end - // Off-load to IPU coprocessor - riscv_instr::MUL, - riscv_instr::MULH, - riscv_instr::MULHSU, - riscv_instr::MULHU, - riscv_instr::DIV, - riscv_instr::DIVU, - riscv_instr::REM, - riscv_instr::REMU, - riscv_instr::MULW, - riscv_instr::DIVW, - riscv_instr::DIVUW, - riscv_instr::REMW, - riscv_instr::REMUW: begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - opb_select = Reg; - acc_register_rd = 1'b1; - end - -/* RVV extension */ -`ifdef TARGET_SPATZ - // Off-load to RVV coprocessor - // 1 destination register (rd) - riscv_instr::VSETIVLI: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 1 source register (rs1) and 1 destination register (rd) - riscv_instr::VSETVLI: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 2 source registers (rs1, rs2) and one destination register (rd) - riscv_instr::VSETVL: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - opb_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 0 source register and 1 destination register - riscv_instr::VMV_X_S: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 0 source register and 0 destination register - riscv_instr::VADD_VV, - riscv_instr::VADD_VI, - riscv_instr::VSUB_VV, - riscv_instr::VRSUB_VI, - riscv_instr::VAND_VV, - riscv_instr::VAND_VI, - riscv_instr::VOR_VV, - riscv_instr::VOR_VI, - riscv_instr::VXOR_VV, - riscv_instr::VXOR_VI, - riscv_instr::VADC_VVM, - riscv_instr::VADC_VIM, - riscv_instr::VMADC_VV, - riscv_instr::VMADC_VI, - riscv_instr::VMADC_VVM, - riscv_instr::VMADC_VIM, - riscv_instr::VSBC_VVM, - riscv_instr::VMSBC_VV, - riscv_instr::VMSBC_VVM, - riscv_instr::VSLL_VV, - riscv_instr::VSLL_VI, - riscv_instr::VSRL_VV, - riscv_instr::VSRL_VI, - riscv_instr::VSRA_VV, - riscv_instr::VSRA_VI, - riscv_instr::VREDSUM_VS, - riscv_instr::VREDAND_VS, - riscv_instr::VREDOR_VS, - riscv_instr::VREDXOR_VS, - riscv_instr::VREDMIN_VS, - riscv_instr::VREDMINU_VS, - riscv_instr::VREDMAX_VS, - riscv_instr::VREDMAXU_VS, - riscv_instr::VMSEQ_VV, - riscv_instr::VMSEQ_VI, - riscv_instr::VMSNE_VV, - riscv_instr::VMSNE_VI, - riscv_instr::VMSLTU_VV, - riscv_instr::VMSLT_VV, - riscv_instr::VMSLEU_VV, - riscv_instr::VMSLEU_VI, - riscv_instr::VMSLE_VV, - riscv_instr::VMSLE_VI, - riscv_instr::VMSGTU_VI, - riscv_instr::VMSGT_VI, - riscv_instr::VMIN_VV, - riscv_instr::VMINU_VV, - riscv_instr::VMAX_VV, - riscv_instr::VMAXU_VV, - riscv_instr::VMUL_VV, - riscv_instr::VMULH_VV, - riscv_instr::VMULHU_VV, - riscv_instr::VMULHSU_VV, - riscv_instr::VMACC_VV, - riscv_instr::VNMSAC_VV, - riscv_instr::VMADD_VV, - riscv_instr::VNMSUB_VV, - riscv_instr::VDIV_VV, - riscv_instr::VDIVU_VV, - riscv_instr::VREM_VV, - riscv_instr::VREMU_VV, - riscv_instr::VWMUL_VV, - riscv_instr::VWMULU_VV, - riscv_instr::VWMULSU_VV, - riscv_instr::VWMACC_VV, - riscv_instr::VWMACCU_VV, - riscv_instr::VWMACCSU_VV, - riscv_instr::VMV_V_V, - riscv_instr::VMV_V_I, - riscv_instr::VFMV_F_S, - riscv_instr::VSLIDEUP_VI, - riscv_instr::VSLIDEDOWN_VI: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b0; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::VFADD_VV, - riscv_instr::VFSUB_VV, - riscv_instr::VFMIN_VV, - riscv_instr::VFMAX_VV, - riscv_instr::VFSGNJ_VV, - riscv_instr::VFSGNJN_VV, - riscv_instr::VFSGNJX_VV, - riscv_instr::VFMUL_VV, - riscv_instr::VFMADD_VV, - riscv_instr::VFNMADD_VV, - riscv_instr::VFMSUB_VV, - riscv_instr::VFNMSUB_VV, - riscv_instr::VFMACC_VV, - riscv_instr::VFNMACC_VV, - riscv_instr::VFMSAC_VV, - riscv_instr::VFNMSAC_VV, - riscv_instr::VFCVT_F_X_V, - riscv_instr::VFCVT_F_XU_V, - riscv_instr::VFCVT_X_F_V, - riscv_instr::VFCVT_XU_F_V, - riscv_instr::VFCVT_RTZ_X_F_V, - riscv_instr::VFCVT_RTZ_XU_F_V, - riscv_instr::VFNCVT_XU_F_W, - riscv_instr::VFNCVT_X_F_W, - riscv_instr::VFNCVT_RTZ_XU_F_W, - riscv_instr::VFNCVT_RTZ_X_F_W, - riscv_instr::VFNCVT_F_XU_W, - riscv_instr::VFNCVT_F_X_W, - riscv_instr::VFNCVT_F_F_W, - riscv_instr::VFREDOSUM_VS, - riscv_instr::VFREDUSUM_VS, - riscv_instr::VFREDMAX_VS, - riscv_instr::VFREDMIN_VS, - riscv_instr::VFWADD_VV, - riscv_instr::VFWADD_WV, - riscv_instr::VFWSUB_VV, - riscv_instr::VFWSUB_WV, - riscv_instr::VFWMUL_VV, - riscv_instr::VFWDOTP_VV, - riscv_instr::VFWMACC_VV, - riscv_instr::VFWNMACC_VV, - riscv_instr::VFWMSAC_VV, - riscv_instr::VFWNMSAC_VV: begin - if (RVV && RVF) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b0; - end else begin - illegal_inst = 1'b1; - end - end - // 1 source register (rs1) - riscv_instr::VADD_VX, - riscv_instr::VSUB_VX, - riscv_instr::VRSUB_VX, - riscv_instr::VAND_VX, - riscv_instr::VOR_VX, - riscv_instr::VXOR_VX, - riscv_instr::VADC_VXM, - riscv_instr::VMADC_VX, - riscv_instr::VMADC_VXM, - riscv_instr::VSBC_VXM, - riscv_instr::VMSBC_VX, - riscv_instr::VMSBC_VXM, - riscv_instr::VSLL_VX, - riscv_instr::VSRL_VX, - riscv_instr::VSRA_VX, - riscv_instr::VMSEQ_VX, - riscv_instr::VMSNE_VX, - riscv_instr::VMSLTU_VX, - riscv_instr::VMSLT_VX, - riscv_instr::VMSLEU_VX, - riscv_instr::VMSLE_VX, - riscv_instr::VMSGTU_VX, - riscv_instr::VMSGT_VX, - riscv_instr::VMIN_VX, - riscv_instr::VMINU_VX, - riscv_instr::VMAX_VX, - riscv_instr::VMAXU_VX, - riscv_instr::VMUL_VX, - riscv_instr::VMULH_VX, - riscv_instr::VMULHU_VX, - riscv_instr::VMULHSU_VX, - riscv_instr::VMACC_VX, - riscv_instr::VNMSAC_VX, - riscv_instr::VMADD_VX, - riscv_instr::VNMSUB_VX, - riscv_instr::VDIV_VX, - riscv_instr::VDIVU_VX, - riscv_instr::VREM_VX, - riscv_instr::VREMU_VX, - riscv_instr::VWMUL_VX, - riscv_instr::VWMULU_VX, - riscv_instr::VWMULSU_VX, - riscv_instr::VWMACC_VX, - riscv_instr::VWMACCU_VX, - riscv_instr::VWMACCSU_VX, - riscv_instr::VWMACCUS_VX, - riscv_instr::VMV_V_X, - riscv_instr::VMV_S_X, - riscv_instr::VSLIDEUP_VX, - riscv_instr::VSLIDEDOWN_VX, - riscv_instr::VSLIDE1UP_VX, - riscv_instr::VSLIDE1DOWN_VX: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr; - opa_select = Reg; - acc_register_rd = 1'b0; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::VFADD_VF, - riscv_instr::VFSUB_VF, - riscv_instr::VFMIN_VF, - riscv_instr::VFMAX_VF, - riscv_instr::VFSGNJ_VF, - riscv_instr::VFSGNJN_VF, - riscv_instr::VFSGNJX_VF, - riscv_instr::VFSLIDE1UP_VF, - riscv_instr::VFSLIDE1DOWN_VF, - riscv_instr::VFMV_V_F, - riscv_instr::VFMV_S_F, - riscv_instr::VFMUL_VF, - riscv_instr::VFRSUB_VF, - riscv_instr::VFMADD_VF, - riscv_instr::VFNMADD_VF, - riscv_instr::VFMSUB_VF, - riscv_instr::VFNMSUB_VF, - riscv_instr::VFMACC_VF, - riscv_instr::VFNMACC_VF, - riscv_instr::VFMSAC_VF, - riscv_instr::VFNMSAC_VF, - riscv_instr::VFWADD_VF, - riscv_instr::VFWADD_WF, - riscv_instr::VFWSUB_VF, - riscv_instr::VFWSUB_WF, - riscv_instr::VFWMUL_VF, - riscv_instr::VFWDOTP_VF, - riscv_instr::VFWMACC_VF, - riscv_instr::VFWNMACC_VF, - riscv_instr::VFWMSAC_VF, - riscv_instr::VFWNMSAC_VF: begin - if (RVV && RVF) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b0; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::VLE8_V, - riscv_instr::VLE16_V, - riscv_instr::VLE32_V, - riscv_instr::VLE64_V, - riscv_instr::VLOXEI8_V, - riscv_instr::VLOXEI16_V, - riscv_instr::VLOXEI32_V, - riscv_instr::VLOXEI64_V, - riscv_instr::VLUXEI8_V, - riscv_instr::VLUXEI16_V, - riscv_instr::VLUXEI32_V, - riscv_instr::VLUXEI64_V: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - opa_select = Reg; - acc_register_rd = 1'b0; - end else begin - illegal_inst = 1'b1; - end - end - // 1 source register (rs1) and memory store operation - riscv_instr::VSE8_V, - riscv_instr::VSE16_V, - riscv_instr::VSE32_V, - riscv_instr::VSE64_V, - riscv_instr::VSOXEI8_V, - riscv_instr::VSOXEI16_V, - riscv_instr::VSOXEI32_V, - riscv_instr::VSOXEI64_V, - riscv_instr::VSUXEI8_V, - riscv_instr::VSUXEI16_V, - riscv_instr::VSUXEI32_V, - riscv_instr::VSUXEI64_V: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - opa_select = Reg; - acc_register_rd = 1'b0; - acc_mem_store = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 2 source registers (rs1, rs2) - riscv_instr::VLSE8_V, - riscv_instr::VLSE16_V, - riscv_instr::VLSE32_V, - riscv_instr::VLSE64_V: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - opa_select = Reg; - opb_select = Reg; - acc_register_rd = 1'b0; - end else begin - illegal_inst = 1'b1; - end - end - // 2 source registers (rs1, rs2) and memory store opeeration - riscv_instr::VSSE8_V, - riscv_instr::VSSE16_V, - riscv_instr::VSSE32_V, - riscv_instr::VSSE64_V: begin - if (RVV) begin - write_rd = 1'b0; - uses_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - opa_select = Reg; - opb_select = Reg; - acc_register_rd = 1'b0; - acc_mem_store = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end -`endif -/* end of RVV extension */ - -/* Xpulpimg extension */ -`ifdef XPULPIMG_EXTENSION - // Post-increment loads/stores - riscv_instr::P_LB_IRPOST: begin // Xpulpimg: p.lb rd,iimm(rs1!) - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - is_signed = 1'b1; - opa_select = Reg; - opb_select = IImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LBU_IRPOST: begin // Xpulpimg: p.lbu - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - opa_select = Reg; - opb_select = IImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LH_IRPOST: begin // Xpulpimg: p.lh - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - is_signed = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = IImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LHU_IRPOST: begin // Xpulpimg: p.lhu - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = IImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LW_IRPOST: begin // Xpulpimg: p.lw - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - is_signed = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = IImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LB_RRPOST: begin // Xpulpimg: p.lb rd,rs2(rs1!) - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - is_signed = 1'b1; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LBU_RRPOST: begin // Xpulpimg: p.lbu - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LH_RRPOST: begin // Xpulpimg: p.lh - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - is_signed = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LHU_RRPOST: begin // Xpulpimg: p.lhu - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LW_RRPOST: begin // Xpulpimg: p.lw - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - write_rs1 = 1'b1; - is_load = 1'b1; - is_postincr = 1'b1; - is_signed = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LB_RR: begin // Xpulpimg: p.lb rd,rs2(rs1) - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LBU_RR: begin // Xpulpimg: p.lbu - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LH_RR: begin // Xpulpimg: p.lh - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LHU_RR: begin // Xpulpimg: p.lhu - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_LW_RR: begin // Xpulpimg: p.lw - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - is_load = 1'b1; - is_signed = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = Reg; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SB_IRPOST: begin // Xpulpimg: p.sb rs2,simm(rs1!) - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - write_rs1 = 1'b1; - is_store = 1'b1; - is_postincr = 1'b1; - opa_select = Reg; - opb_select = SImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SH_IRPOST: begin // Xpulpimg: p.sh - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - write_rs1 = 1'b1; - is_store = 1'b1; - is_postincr = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = SImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SW_IRPOST: begin // Xpulpimg: p.sw - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - write_rs1 = 1'b1; - is_store = 1'b1; - is_postincr = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = SImmediate; - end else begin - illegal_inst = 1'b1; - end - end - // opb is usually assigned with the content of rs2; in stores with reg-reg - // addressing mode, however, the offset is stored in rd, so rd content is - // instead assigned to opb: if we cross such signals now (rd -> opb, - // rs2 -> opc) we don't have to do that in the ALU, with bigger muxes - riscv_instr::P_SB_RRPOST: begin // Xpulpimg: p.sb rs2,rs3(rs1!) - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - write_rs1 = 1'b1; - is_store = 1'b1; - is_postincr = 1'b1; - opa_select = Reg; // rs1 base address - opb_select = RegRd; // rs3 (i.e. rd) offset - opc_select = RegRs2; // rs2 source data - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SH_RRPOST: begin // Xpulpimg: p.sh - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - write_rs1 = 1'b1; - is_store = 1'b1; - is_postincr = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = RegRd; - opc_select = RegRs2; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SW_RRPOST: begin // Xpulpimg: p.sw - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - write_rs1 = 1'b1; - is_store = 1'b1; - is_postincr = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = RegRd; - opc_select = RegRs2; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SB_RR: begin // Xpulpimg: p.sb rs2,rs3(rs1) - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - is_store = 1'b1; - opa_select = Reg; - opb_select = RegRd; - opc_select = RegRs2; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SH_RR: begin // Xpulpimg: p.sh - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - is_store = 1'b1; - ls_size = HalfWord; - opa_select = Reg; - opb_select = RegRd; - opc_select = RegRs2; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_SW_RR: begin // Xpulpimg: p.sw - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - is_store = 1'b1; - ls_size = Word; - opa_select = Reg; - opb_select = RegRd; - opc_select = RegRs2; - end else begin - illegal_inst = 1'b1; - end - end - // Immediate branching - riscv_instr::P_BEQIMM: begin // Xpulpimg: p.beqimm - if (snitch_pkg::XPULPIMG) begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Eq; - opa_select = Reg; - opb_select = PBImmediate; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::P_BNEIMM: begin // Xpulpimg: p.bneimm - if (snitch_pkg::XPULPIMG) begin - is_branch = 1'b1; - write_rd = 1'b0; - alu_op = Neq; - opa_select = Reg; - opb_select = PBImmediate; - end else begin - illegal_inst = 1'b1; - end - end - // Off-load to IPU coprocessor - // 1 source register (rs1) - riscv_instr::P_ABS, // Xpulpimg: p.abs - riscv_instr::P_EXTHS, // Xpulpimg: p.exths - riscv_instr::P_EXTHZ, // Xpulpimg: p.exthz - riscv_instr::P_EXTBS, // Xpulpimg: p.extbs - riscv_instr::P_EXTBZ, // Xpulpimg: p.extbz - riscv_instr::P_CLIP, // Xpulpimg: p.clip - riscv_instr::P_CLIPU, // Xpulpimg: p.clipu - riscv_instr::PV_ADD_SCI_H, // Xpulpimg: pv.add.sci.h - riscv_instr::PV_ADD_SCI_B, // Xpulpimg: pv.add.sci.b - riscv_instr::PV_SUB_SCI_H, // Xpulpimg: pv.sub.sci.h - riscv_instr::PV_SUB_SCI_B, // Xpulpimg: pv.sub.sci.b - riscv_instr::PV_AVG_SCI_H, // Xpulpimg: pv.avg.sci.h - riscv_instr::PV_AVG_SCI_B, // Xpulpimg: pv.avg.sci.b - riscv_instr::PV_AVGU_SCI_H, // Xpulpimg: pv.avgu.sci.h - riscv_instr::PV_AVGU_SCI_B, // Xpulpimg: pv.avgu.sci.b - riscv_instr::PV_MIN_SCI_H, // Xpulpimg: pv.min.sci.h - riscv_instr::PV_MIN_SCI_B, // Xpulpimg: pv.min.sci.b - riscv_instr::PV_MINU_SCI_H, // Xpulpimg: pv.minu.sci.h - riscv_instr::PV_MINU_SCI_B, // Xpulpimg: pv.minu.sci.b - riscv_instr::PV_MAX_SCI_H, // Xpulpimg: pv.max.sci.h - riscv_instr::PV_MAX_SCI_B, // Xpulpimg: pv.max.sci.b - riscv_instr::PV_MAXU_SCI_H, // Xpulpimg: pv.maxu.sci.h - riscv_instr::PV_MAXU_SCI_B, // Xpulpimg: pv.maxu.sci.b - riscv_instr::PV_SRL_SCI_H, // Xpulpimg: pv.srl.sci.h - riscv_instr::PV_SRL_SCI_B, // Xpulpimg: pv.srl.sci.b - riscv_instr::PV_SRA_SCI_H, // Xpulpimg: pv.sra.sci.h - riscv_instr::PV_SRA_SCI_B, // Xpulpimg: pv.sra.sci.b - riscv_instr::PV_SLL_SCI_H, // Xpulpimg: pv.sll.sci.h - riscv_instr::PV_SLL_SCI_B, // Xpulpimg: pv.sll.sci.b - riscv_instr::PV_OR_SCI_H, // Xpulpimg: pv.or.sci.h - riscv_instr::PV_OR_SCI_B, // Xpulpimg: pv.or.sci.b - riscv_instr::PV_XOR_SCI_H, // Xpulpimg: pv.xor.sci.h - riscv_instr::PV_XOR_SCI_B, // Xpulpimg: pv.xor.sci.b - riscv_instr::PV_AND_SCI_B, // Xpulpimg: pv.and.sci.b - riscv_instr::PV_AND_SCI_H, // Xpulpimg: pv.and.sci.h - riscv_instr::PV_ABS_H, // Xpulpimg: pv.abs.h - riscv_instr::PV_ABS_B, // Xpulpimg: pv.abs.b - riscv_instr::PV_EXTRACT_H, // Xpulpimg: pv.extract.h - riscv_instr::PV_EXTRACT_B, // Xpulpimg: pv.extract.b - riscv_instr::PV_EXTRACTU_H, // Xpulpimg: pv.extractu.h - riscv_instr::PV_EXTRACTU_B, // Xpulpimg: pv.extractu.b - riscv_instr::PV_DOTUP_SCI_H, // Xpulpimg: pv.dotup.sci.h - riscv_instr::PV_DOTUP_SCI_B, // Xpulpimg: pv.dotup.sci.b - riscv_instr::PV_DOTUSP_SCI_H, // Xpulpimg: pv.dotusp.sci.h - riscv_instr::PV_DOTUSP_SCI_B, // Xpulpimg: pv.dotusp.sci.b - riscv_instr::PV_DOTSP_SCI_H, // Xpulpimg: pv.dotsp.sci.h - riscv_instr::PV_DOTSP_SCI_B: begin // Xpulpimg: pv.dotsp.sci.b - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 2 source registers (rs1, rs2) - riscv_instr::P_SLET, // Xpulpimg: p.slet - riscv_instr::P_SLETU, // Xpulpimg: p.sletu - riscv_instr::P_MIN, // Xpulpimg: p.min - riscv_instr::P_MINU, // Xpulpimg: p.minu - riscv_instr::P_MAX, // Xpulpimg: p.max - riscv_instr::P_MAXU, // Xpulpimg: p.maxu - riscv_instr::P_CLIPR, // Xpulpimg: p.clipr - riscv_instr::P_CLIPUR, // Xpulpimg: p.clipur - riscv_instr::PV_ADD_H, // Xpulpimg: pv.add.h - riscv_instr::PV_ADD_SC_H, // Xpulpimg: pv.add.sc.h - riscv_instr::PV_ADD_B, // Xpulpimg: pv.add.b - riscv_instr::PV_ADD_SC_B, // Xpulpimg: pv.add.sc.b - riscv_instr::PV_SUB_H, // Xpulpimg: pv.sub.h - riscv_instr::PV_SUB_SC_H, // Xpulpimg: pv.sub.sc.h - riscv_instr::PV_SUB_B, // Xpulpimg: pv.sub.b - riscv_instr::PV_SUB_SC_B, // Xpulpimg: pv.sub.sc.b - riscv_instr::PV_AVG_H, // Xpulpimg: pv.avg.h - riscv_instr::PV_AVG_SC_H, // Xpulpimg: pv.avg.sc.h - riscv_instr::PV_AVG_B, // Xpulpimg: pv.avg.b - riscv_instr::PV_AVG_SC_B, // Xpulpimg: pv.avg.sc.b - riscv_instr::PV_AVGU_H, // Xpulpimg: pv.avgu.h - riscv_instr::PV_AVGU_SC_H, // Xpulpimg: pv.avgu.sc.h - riscv_instr::PV_AVGU_B, // Xpulpimg: pv.avgu.b - riscv_instr::PV_AVGU_SC_B, // Xpulpimg: pv.avgu.sc.b - riscv_instr::PV_MIN_H, // Xpulpimg: pv.min.h - riscv_instr::PV_MIN_SC_H, // Xpulpimg: pv.min.sc.h - riscv_instr::PV_MIN_B, // Xpulpimg: pv.min.b - riscv_instr::PV_MIN_SC_B, // Xpulpimg: pv.min.sc.b - riscv_instr::PV_MINU_H, // Xpulpimg: pv.minu.h - riscv_instr::PV_MINU_SC_H, // Xpulpimg: pv.minu.sc.h - riscv_instr::PV_MINU_B, // Xpulpimg: pv.minu.b - riscv_instr::PV_MINU_SC_B, // Xpulpimg: pv.minu.sc.b - riscv_instr::PV_MAX_H, // Xpulpimg: pv.max.h - riscv_instr::PV_MAX_SC_H, // Xpulpimg: pv.max.sc.h - riscv_instr::PV_MAX_B, // Xpulpimg: pv.max.b - riscv_instr::PV_MAX_SC_B, // Xpulpimg: pv.max.sc.b - riscv_instr::PV_MAXU_H, // Xpulpimg: pv.maxu.h - riscv_instr::PV_MAXU_SC_H, // Xpulpimg: pv.maxu.sc.h - riscv_instr::PV_MAXU_B, // Xpulpimg: pv.maxu.b - riscv_instr::PV_MAXU_SC_B, // Xpulpimg: pv.maxu.sc.b - riscv_instr::PV_SRL_H, // Xpulpimg: pv.srl.h - riscv_instr::PV_SRL_SC_H, // Xpulpimg: pv.srl.sc.h - riscv_instr::PV_SRL_B, // Xpulpimg: pv.srl.b - riscv_instr::PV_SRL_SC_B, // Xpulpimg: pv.srl.sc.b - riscv_instr::PV_SRA_H, // Xpulpimg: pv.sra.h - riscv_instr::PV_SRA_SC_H, // Xpulpimg: pv.sra.sc.h - riscv_instr::PV_SRA_B, // Xpulpimg: pv.sra.b - riscv_instr::PV_SRA_SC_B, // Xpulpimg: pv.sra.sc.b - riscv_instr::PV_SLL_H, // Xpulpimg: pv.sll.h - riscv_instr::PV_SLL_SC_H, // Xpulpimg: pv.sll.sc.h - riscv_instr::PV_SLL_B, // Xpulpimg: pv.sll.b - riscv_instr::PV_SLL_SC_B, // Xpulpimg: pv.sll.sc.b - riscv_instr::PV_OR_H, // Xpulpimg: pv.or.h - riscv_instr::PV_OR_SC_H, // Xpulpimg: pv.or.sc.h - riscv_instr::PV_OR_B, // Xpulpimg: pv.or.b - riscv_instr::PV_OR_SC_B, // Xpulpimg: pv.or.sc.b - riscv_instr::PV_XOR_H, // Xpulpimg: pv.xor.h - riscv_instr::PV_XOR_SC_H, // Xpulpimg: pv.xor.sc.h - riscv_instr::PV_XOR_B, // Xpulpimg: pv.xor.b - riscv_instr::PV_XOR_SC_B, // Xpulpimg: pv.xor.sc.b - riscv_instr::PV_AND_H, // Xpulpimg: pv.and.h - riscv_instr::PV_AND_SC_H, // Xpulpimg: pv.and.sc.h - riscv_instr::PV_AND_B, // Xpulpimg: pv.and.b - riscv_instr::PV_AND_SC_B, // Xpulpimg: pv.and.sc.b - riscv_instr::PV_DOTUP_H, // Xpulpimg: pv.dotup.h - riscv_instr::PV_DOTUP_SC_H, // Xpulpimg: pv.dotup.sc.h - riscv_instr::PV_DOTUP_B, // Xpulpimg: pv.dotup.b - riscv_instr::PV_DOTUP_SC_B, // Xpulpimg: pv.dotup.sc.b - riscv_instr::PV_DOTUSP_H, // Xpulpimg: pv.dotusp.h - riscv_instr::PV_DOTUSP_SC_H, // Xpulpimg: pv.dotusp.sc.h - riscv_instr::PV_DOTUSP_B, // Xpulpimg: pv.dotusp.b - riscv_instr::PV_DOTUSP_SC_B, // Xpulpimg: pv.dotusp.sc.b - riscv_instr::PV_DOTSP_H, // Xpulpimg: pv.dotsp.h - riscv_instr::PV_DOTSP_SC_H, // Xpulpimg: pv.dotsp.sc.h - riscv_instr::PV_DOTSP_B, // Xpulpimg: pv.dotsp.b - riscv_instr::PV_DOTSP_SC_B: begin // Xpulpimg: pv.dotsp.sc.b - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - opb_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 2 source registers (rs1, rd) - riscv_instr::PV_INSERT_H, // Xpulpimg: pv.insert.h - riscv_instr::PV_INSERT_B, // Xpulpimg: pv.insert.b - riscv_instr::PV_SDOTUP_SCI_H, // Xpulpimg: pv.sdotup.sci.h - riscv_instr::PV_SDOTUP_SCI_B, // Xpulpimg: pv.sdotup.sci.b - riscv_instr::PV_SDOTUSP_SCI_H, // Xpulpimg: pv.sdotusp.sci.h - riscv_instr::PV_SDOTUSP_SCI_B, // Xpulpimg: pv.sdotusp.sci.b - riscv_instr::PV_SDOTSP_SCI_H, // Xpulpimg: pv.sdotsp.sci.h - riscv_instr::PV_SDOTSP_SCI_B: begin // Xpulpimg: pv.sdotsp.sci.b - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - opc_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // 3 source registers (rs1, rs2, rd) - riscv_instr::P_MAC, // Xpulpimg: p.mac - riscv_instr::P_MSU, // Xpulpimg: p.msu - riscv_instr::PV_SDOTUP_H, // Xpulpimg: pv.sdotup.h - riscv_instr::PV_SDOTUP_SC_H, // Xpulpimg: pv.sdotup.sc.h - riscv_instr::PV_SDOTUP_B, // Xpulpimg: pv.sdotup.b - riscv_instr::PV_SDOTUP_SC_B, // Xpulpimg: pv.sdotup.sc.b - riscv_instr::PV_SDOTUSP_H, // Xpulpimg: pv.sdotusp.h - riscv_instr::PV_SDOTUSP_SC_H, // Xpulpimg: pv.sdotusp.sc.h - riscv_instr::PV_SDOTUSP_B, // Xpulpimg: pv.sdotusp.b - riscv_instr::PV_SDOTUSP_SC_B, // Xpulpimg: pv.sdotusp.sc.b - riscv_instr::PV_SDOTSP_H, // Xpulpimg: pv.sdotsp.h - riscv_instr::PV_SDOTSP_SC_H, // Xpulpimg: pv.sdotsp.sc.h - riscv_instr::PV_SDOTSP_B, // Xpulpimg: pv.sdotsp.b - riscv_instr::PV_SDOTSP_SC_B, // Xpulpimg: pv.sdotsp.sc.b - riscv_instr::PV_SHUFFLE2_H, // Xpulpimg: pv.shuffle2.h - riscv_instr::PV_SHUFFLE2_B, // Xpulpimg: pv.shuffle2.b - riscv_instr::PV_PACK, // Xpulpimg: pv.pack - riscv_instr::PV_PACK_H: begin // Xpulpimg: pv.pack.h - if (snitch_pkg::XPULPIMG) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - opa_select = Reg; - opb_select = Reg; - opc_select = Reg; - acc_register_rd = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end -`endif -/* end of Xpulpimg extension */ - -/* Floating point instructions */ - - // Offload FP-FP Instructions - fire and forget - // TODO (smach): Check legal rounding modes and issue illegal isn if needed - // Single Precision Floating-Point - riscv_instr::FADD_S, - riscv_instr::FSUB_S, - riscv_instr::FMUL_S, - riscv_instr::FDIV_S, - riscv_instr::FSQRT_S, - riscv_instr::FSGNJ_S, - riscv_instr::FSGNJN_S, - riscv_instr::FSGNJX_S, - riscv_instr::FMIN_S, - riscv_instr::FMAX_S, - riscv_instr::FMADD_S, - riscv_instr::FMSUB_S, - riscv_instr::FNMSUB_S, - riscv_instr::FNMADD_S: begin - if (FP_EN && RVF && (!(inst_data_i inside {riscv_instr::FDIV_S, riscv_instr::FSQRT_S}) || XDivSqrt)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Double Precision Floating-Point - riscv_instr::FADD_D, - riscv_instr::FSUB_D, - riscv_instr::FMUL_D, - riscv_instr::FDIV_D, - riscv_instr::FSQRT_D, - riscv_instr::FSGNJ_D, - riscv_instr::FSGNJN_D, - riscv_instr::FSGNJX_D, - riscv_instr::FMIN_D, - riscv_instr::FMAX_D, - riscv_instr::FMADD_D, - riscv_instr::FMSUB_D, - riscv_instr::FNMSUB_D, - riscv_instr::FNMADD_D: begin - if (FP_EN && RVD && (!(inst_data_i inside {riscv_instr::FDIV_D, riscv_instr::FSQRT_D}) || XDivSqrt)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FCVT_S_D, - riscv_instr::FCVT_D_S: begin - if (FP_EN && RVF && (!(inst_data_i inside {riscv_instr::FDIV_S, riscv_instr::FSQRT_S}) || XDivSqrt)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Half Precision Floating-Point - riscv_instr::FADD_H, - riscv_instr::FSUB_H, - riscv_instr::FMUL_H, - riscv_instr::FDIV_H, - riscv_instr::FSQRT_H, - riscv_instr::FMADD_H, - riscv_instr::FMSUB_H, - riscv_instr::FNMSUB_H, - riscv_instr::FNMADD_H, - riscv_instr::FSGNJ_H, - riscv_instr::FSGNJN_H, - riscv_instr::FSGNJX_H, - riscv_instr::FMIN_H, - riscv_instr::FMAX_H: begin - if (FP_EN && XF16 && fcsr_q.fmode.dst == 1'b0 && - (!(inst_data_i inside {riscv_instr::FDIV_H, riscv_instr::FSQRT_H}) || XDivSqrt)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && XF16ALT && fcsr_q.fmode.dst == 1'b1 && - (!(inst_data_i inside {riscv_instr::FDIV_H, riscv_instr::FSQRT_H}) || XDivSqrt)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FCVT_S_H: begin - if (FP_EN && RVF && XF16 && fcsr_q.fmode.src == 1'b0) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && RVF && XF16ALT && fcsr_q.fmode.src == 1'b1) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FCVT_H_S: begin - if (FP_EN && RVF && XF16 && fcsr_q.fmode.dst == 1'b0) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && RVF && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FCVT_D_H: begin - if (FP_EN && RVD && XF16 && fcsr_q.fmode.src == 1'b0) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && RVD && XF16ALT && fcsr_q.fmode.src == 1'b1) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FCVT_H_D: begin - if (FP_EN && RVD && XF16 && fcsr_q.fmode.dst == 1'b0) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && RVD && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Byte Precision Floating-Point - riscv_instr::FADD_B, - riscv_instr::FSUB_B, - riscv_instr::FMUL_B, - riscv_instr::FDIV_B, - riscv_instr::FSQRT_B, - riscv_instr::FSGNJ_B, - riscv_instr::FSGNJN_B, - riscv_instr::FSGNJX_B, - riscv_instr::FMIN_B, - riscv_instr::FMAX_B, - riscv_instr::FMADD_B, - riscv_instr::FMSUB_B, - riscv_instr::FNMSUB_B, - riscv_instr::FNMADD_B: begin - if (FP_EN && XF8 && fcsr_q.fmode.dst == 1'b0 && (!(inst_data_i inside {riscv_instr::FDIV_B, riscv_instr::FSQRT_B}) || XDivSqrt)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - riscv_instr::FCVT_B_H: begin - if (FP_EN) begin - if ((XF16 && fcsr_q.fmode.src == 1'b0) || - (XF16ALT && fcsr_q.fmode.src == 1'b1)) begin - if ((XF8 && fcsr_q.fmode.dst == 1'b0) || - (XF8ALT && fcsr_q.fmode.dst == 1'b1)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end else begin - illegal_inst = 1'b1; - end - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FCVT_H_B: begin - if (FP_EN) begin - if ((XF8 && fcsr_q.fmode.src == 1'b0) || - (XF8ALT && fcsr_q.fmode.src == 1'b1)) begin - if ((XF16 && fcsr_q.fmode.dst == 1'b0) || - (XF16ALT && fcsr_q.fmode.dst == 1'b1)) begin - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end else begin - illegal_inst = 1'b1; - end - end else begin - illegal_inst = 1'b1; - end - end - - // double precision floating-point - riscv_instr::FCLASS_D, - riscv_instr::FLE_D, - riscv_instr::FLT_D, - riscv_instr::FEQ_D, - riscv_instr::FCVT_W_D, - riscv_instr::FCVT_WU_D: begin - if (FP_EN && RVD) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_register_rd = 1'b1; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // single precision floating-point - riscv_instr::FCLASS_S, - riscv_instr::FLE_S, - riscv_instr::FLT_S, - riscv_instr::FEQ_S, - riscv_instr::FMV_X_S, - riscv_instr::FCVT_W_S, - riscv_instr::FCVT_WU_S, - riscv_instr::FMV_X_W: begin - if (FP_EN && RVF) begin - acc_register_rd = 1'b1; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // half precision floating-point - riscv_instr::FCLASS_H, - riscv_instr::FLE_H, - riscv_instr::FLT_H, - riscv_instr::FEQ_H, - riscv_instr::FMV_X_H, - riscv_instr::FCVT_W_H, - riscv_instr::FCVT_WU_H: begin - if (FP_EN && XF16 && fcsr_q.fmode.src == 1'b0) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_register_rd = 1'b1; - acc_qvalid_o = valid_instr; - end else if (FP_EN && XF16ALT && fcsr_q.fmode.src == 1'b1) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard - end else begin - illegal_inst = 1'b1; - end - end - - // Byte Precision Floating-Point - riscv_instr::FCLASS_B, - riscv_instr::FLE_B, - riscv_instr::FLT_B, - riscv_instr::FEQ_B, - riscv_instr::FMV_X_B, - riscv_instr::FCVT_W_B, - riscv_instr::FCVT_WU_B: begin - if (FP_EN && XF8 && fcsr_q.fmode.src == 1'b0) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard - end else if (FP_EN && XF8ALT && fcsr_q.fmode.src == 1'b1) begin - write_rd = 1'b0; - uses_rd = 1'b1; - acc_qvalid_o = valid_instr; - acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard - end else begin - illegal_inst = 1'b1; - end - end - - // Double Precision Floating-Point - riscv_instr::FMV_D_X, - riscv_instr::FCVT_D_W, - riscv_instr::FCVT_D_WU: begin - if (FP_EN && RVD) begin - opa_select = Reg; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Single Precision Floating-Point - // riscv_instr::FMV_S_X, - riscv_instr::FMV_W_X, - riscv_instr::FCVT_S_W, - riscv_instr::FCVT_S_WU: begin - if (FP_EN && RVF) begin - opa_select = Reg; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Half Precision Floating-Point - riscv_instr::FMV_H_X, - riscv_instr::FCVT_H_W, - riscv_instr::FCVT_H_WU: begin - if (FP_EN && XF16 && (fcsr_q.fmode.dst == 1'b0)) begin - opa_select = Reg; - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && XF16ALT && (fcsr_q.fmode.dst == 1'b1)) begin - opa_select = Reg; - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Byte Precision Floating-Point - riscv_instr::FMV_B_X, - riscv_instr::FCVT_B_W, - riscv_instr::FCVT_B_WU: begin - if (FP_EN && XF8 && fcsr_q.fmode.dst == 1'b0) begin - opa_select = Reg; - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else if (FP_EN && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin - opa_select = Reg; - write_rd = 1'b0; - acc_qvalid_o = valid_instr; - end else begin - illegal_inst = 1'b1; - end - end - - // Floating-Point Load/Store - // Single Precision Floating-Point - riscv_instr::FLW: begin - if (FP_EN && RVF) begin - opa_select = Reg; - opb_select = IImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = Word; - is_fp_load = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FSW: begin - if (FP_EN && RVF) begin - opa_select = Reg; - opb_select = SFImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = Word; - is_fp_store = 1'b1; - acc_mem_store = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // Double Precision Floating-Point - riscv_instr::FLD: begin - if (FP_EN && (RVD || XFVEC)) begin - opa_select = Reg; - opb_select = IImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = Double; - is_fp_load = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FSD: begin - if (FP_EN && (RVD || XFVEC)) begin - opa_select = Reg; - opb_select = SFImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = Double; - is_fp_store = 1'b1; - acc_mem_store = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // Half Precision Floating-Point - riscv_instr::FLH: begin - if (FP_EN && (XF16 || XF16ALT)) begin - opa_select = Reg; - opb_select = IImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = HalfWord; - is_fp_load = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FSH: begin - if (FP_EN && (XF16 || XF16ALT)) begin - opa_select = Reg; - opb_select = SFImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = HalfWord; - is_fp_store = 1'b1; - acc_mem_store = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - // Quarter Precision Floating-Point - riscv_instr::FLB: begin - if (FP_EN && (XF8 || XF8ALT)) begin - opa_select = Reg; - opb_select = IImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = Byte; - is_fp_load = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - riscv_instr::FSB: begin - if (FP_EN && (XF8 || XF8ALT)) begin - opa_select = Reg; - opb_select = SFImmediate; - write_rd = 1'b0; - acc_qvalid_o = valid_instr && !acc_mem_stall; - ls_size = Byte; - is_fp_store = 1'b1; - acc_mem_store = 1'b1; - end else begin - illegal_inst = 1'b1; - end - end - -/* end of floating point instructions */ - - - // TODO(zarubaf): Illegal Instructions - default: begin - illegal_inst = 1'b1; - end - endcase - - // Sanitize illegal instructions so that they don't exert any side-effects. - if (exception) begin - write_rd = 1'b0; - uses_rd = 1'b0; - write_rs1 = 1'b0; - uses_rs1 = 1'b0; - acc_qvalid_o = 1'b0; - next_pc = Exception; - end - end - - assign exception = illegal_inst | ld_addr_misaligned | st_addr_misaligned; - - // pragma translate_off - always_ff @(posedge clk_i or posedge rst_i) begin - if (!rst_i && illegal_inst && inst_valid_o && inst_ready_i) begin - $display("[Illegal Instruction Core %0d] PC: %h Data: %h", hart_id_i, inst_addr_o, inst_data_i); - end - if (!rst_i && wake_up_sync_i && &wake_up_q) begin - $display("[Missed wake-up Core %0d] Cycle: %d, Time: %t", hart_id_i, cycle_q, $time); - end - end - // pragma translate_on - - // CSR logic - logic csr_dump; - logic csr_trace_en, csr_stack_limit_en; - logic [31:0] csr_trace_q, csr_stack_limit_q; - logic [11:0] csr_source_dest; - - assign csr_source_dest = inst_data_i[31:20]; - - always_comb begin - csr_rvalue = '0; - csr_dump = 1'b0; - csr_trace_en = 1'b0; - csr_stack_limit_en = 1'b0; - read_fcsr = 1'b0; - - fcsr_d = fcsr_q; - if (FP_EN) begin - fcsr_d.fflags = fcsr_q.fflags | fpu_status_i; - end - - // TODO(zarubaf): Needs some more input handling, like illegal instruction exceptions. - // Right now we skip this due to simplicity. - if (csr_en) begin - unique case (csr_source_dest) - riscv_instr::CSR_MHARTID: begin - csr_rvalue = hart_id_i; - end - riscv_instr::CSR_TRACE: begin - csr_rvalue = csr_trace_q; - csr_trace_en = 1'b1; - end - riscv_instr::CSR_STACKLIMIT: begin - csr_rvalue = csr_stack_limit_q; - csr_stack_limit_en = 1'b1; - end - `ifdef SNITCH_ENABLE_PERF - riscv_instr::CSR_MCYCLE: begin - csr_rvalue = cycle_q[31:0]; - end - riscv_instr::CSR_MINSTRET: begin - csr_rvalue = instret_q[31:0]; - end - riscv_instr::CSR_MCYCLEH: begin - csr_rvalue = cycle_q[63:32]; - end - riscv_instr::CSR_MINSTRETH: begin - csr_rvalue = instret_q[63:32]; - end - `endif - `ifdef SNITCH_ENABLE_STALL_COUNTER - riscv_instr::CSR_MHPMCOUNTER3: begin - csr_rvalue = stall_ins_q[31:0]; - end - riscv_instr::CSR_MHPMCOUNTER4: begin - csr_rvalue = stall_lsu_q[31:0]; - end - riscv_instr::CSR_MHPMCOUNTER5: begin - csr_rvalue = stall_raw_q[31:0]; - end - `endif - // F/D Extension - riscv_instr::CSR_FFLAGS: begin - if (FP_EN) begin - csr_rvalue = {27'b0, fcsr_d.fflags}; - read_fcsr = 1'b1; - if (!exception && !acc_stall) fcsr_d.fflags = fpnew_pkg::status_t'(alu_result[4:0]); - end - end - riscv_instr::CSR_FRM: begin - if (FP_EN) begin - csr_rvalue = {29'b0, fcsr_d.frm}; - read_fcsr = 1'b1; - if (!exception && !acc_stall) fcsr_d.frm = fpnew_pkg::roundmode_e'(alu_result[2:0]); - end - end - riscv_instr::CSR_FMODE: begin - if (FP_EN) begin - csr_rvalue = {30'b0, fcsr_q.fmode}; - read_fcsr = 1'b1; - if (!exception && !acc_stall) fcsr_d.fmode = fpnew_pkg::fmt_mode_t'(alu_result[1:0]); - end - end - riscv_instr::CSR_FCSR: begin - if (FP_EN) begin - csr_rvalue = {22'b0, fcsr_d}; - read_fcsr = 1'b1; - if (!exception && !acc_stall) fcsr_d = fcsr_t'(alu_result[9:0]); - end - end - default: begin - csr_rvalue = '0; - csr_dump = 1'b1; - end - endcase - end - end - - // CSR registers - `ifdef TARGET_ASIC - assign csr_trace_q = '0; - assign csr_stack_limit_q = '0; - `else - `FFLAR(csr_trace_q, alu_result, csr_trace_en, '0, clk_i, rst_i); - `FFLAR(csr_stack_limit_q, alu_result, csr_stack_limit_en, 32'hFFFF_FFFF, clk_i, rst_i); - `endif - - // pragma translate_off - always_ff @(posedge clk_i or posedge rst_i) begin - // Display CSR write if the CSR does not exist - if (!rst_i && csr_dump && inst_valid_o && inst_ready_i && !stall) begin - $timeformat(-9, 0, " ns", 0); - $display("[DUMP] %t Core %3d: 0x%3h = 0x%08h, %d", $time, hart_id_i, inst_data_i[31:20], alu_result, alu_result); - end - end - // pragma translate_on - - snitch_regfile #( - .DATA_WIDTH ( 32 ), - .NR_READ_PORTS ( RegNrReadPorts ), - .NR_WRITE_PORTS ( RegNrWritePorts ), - .ZERO_REG_ZERO ( 1 ), - .ADDR_WIDTH ( RegWidth ) - ) i_snitch_regfile ( - .clk_i, - .raddr_i ( gpr_raddr ), - .rdata_o ( gpr_rdata ), - .waddr_i ( gpr_waddr ), - .wdata_i ( gpr_wdata ), - .we_i ( gpr_we ) - ); - - // -------------------- - // Operand Select - // -------------------- - always_comb begin - unique case (opa_select) - None: opa = '0; - Reg: opa = gpr_rdata[0]; - UImmediate: opa = uimm; - JImmediate: opa = jimm; - CSRImmediate: opa = {{{32-RegWidth}{1'b0}}, rs1}; - default: opa = '0; - endcase - end - - always_comb begin - unique case (opb_select) - None: opb = '0; - Reg: opb = gpr_rdata[1]; - IImmediate: opb = iimm; - SFImmediate, SImmediate: opb = simm; - PC: opb = pc_q; - CSR: opb = csr_rvalue; - PBImmediate: opb = pbimm; -`ifdef XPULPIMG_EXTENSION - RegRd: opb = (RegNrReadPorts < 3) ? '0 : gpr_rdata[2]; -`endif - default: opb = '0; - endcase - end - - assign gpr_raddr[0] = rs1; - assign gpr_raddr[1] = rs2; - // connect third read port only if present - if (RegNrReadPorts >= 3) begin : gpr_raddr_2 - assign gpr_raddr[2] = rd; - end - - // -------------------- - // ALU - // -------------------- - // Main Shifter - logic [31:0] shift_opa, shift_opa_reversed; - logic [31:0] shift_right_result, shift_left_result; - logic [32:0] shift_opa_ext, shift_right_result_ext; - logic shift_left, shift_arithmetic; // shift control - for (genvar i = 0; i < 32; i++) begin : gen_reverse_opa - assign shift_opa_reversed[i] = opa[31-i]; - assign shift_left_result[i] = shift_right_result[31-i]; - end - assign shift_opa = shift_left ? shift_opa_reversed : opa; - assign shift_opa_ext = {shift_opa[31] & shift_arithmetic, shift_opa}; - assign shift_right_result_ext = $unsigned($signed(shift_opa_ext) >>> opb[4:0]); - assign shift_right_result = shift_right_result_ext[31:0]; - - // Main Adder - logic [32:0] alu_opa, alu_opb; - assign adder_result = alu_opa + alu_opb; - - // ALU - /* verilator lint_off WIDTH */ - always_comb begin - alu_opa = $signed(opa); - alu_opb = $signed(opb); - - alu_result = adder_result[31:0]; - shift_left = 1'b0; - shift_arithmetic = 1'b0; - - unique case (alu_op) - // Arithmetical operations - Sub: alu_opb = -$signed(opb); - // Comparisons - Slt: begin - alu_opb = -$signed(opb); - alu_result = {30'b0, adder_result[32]}; - end - Ge: begin - alu_opb = -$signed(opb); - alu_result = {30'b0, ~adder_result[32]}; - end - Sltu: begin - alu_opa = $unsigned(opa); - alu_opb = -$unsigned(opb); - alu_result = {30'b0, adder_result[32]}; - end - Geu: begin - alu_opa = $unsigned(opa); - alu_opb = -$unsigned(opb); - alu_result = {30'b0, ~adder_result[32]}; - end - // Shifts - Sll: begin - shift_left = 1'b1; - alu_result = shift_left_result; - end - Srl: alu_result = shift_right_result; - Sra: begin - shift_arithmetic = 1'b1; - alu_result = shift_right_result; - end - // Logical operations - LXor: alu_result = opa ^ opb; - LAnd: alu_result = opa & opb; - LNAnd: alu_result = (~opa) & opb; - LOr: alu_result = opa | opb; - // Equal, not equal - Eq: begin - alu_opb = -$signed(opb); - alu_result = ~|adder_result; - end - Neq: begin - alu_opb = -$signed(opb); - alu_result = |adder_result; - end - // Miscellaneous - BypassA: begin - alu_result = opa; - end - default: alu_result = adder_result[31:0]; - endcase - end - /* verilator lint_on WIDTH */ - - // -------------------- - // LSU - // -------------------- - snitch_lsu #( - .tag_t ( logic[RegWidth-1:0] ), - .NumOutstandingLoads ( snitch_pkg::NumIntOutstandingLoads ) - ) i_snitch_lsu ( - .clk_i , - .rst_i , - .lsu_qtag_i ( rd ), - .lsu_qwrite_i ( is_store ), - .lsu_qsigned_i( is_signed ), - .lsu_qaddr_i ( lsu_qaddr ), - .lsu_qdata_i ( gpr_rdata[1] ), - .lsu_qsize_i ( ls_size ), - .lsu_qamo_i ( ls_amo ), - .lsu_qvalid_i ( lsu_qvalid ), - .lsu_qready_o ( lsu_qready ), - .lsu_pdata_o ( ld_result ), - .lsu_ptag_o ( lsu_rd ), - .lsu_perror_o ( ), // ignored for the moment - .lsu_pvalid_o ( lsu_pvalid ), - .lsu_pready_i ( lsu_pready ), - .data_qaddr_o , - .data_qwrite_o , - .data_qdata_o , - .data_qamo_o , - .data_qstrb_o , - .data_qid_o , - .data_qvalid_o , - .data_qready_i , - .data_pdata_i , - .data_perror_i , - .data_pid_i , - .data_pvalid_i , - .data_pready_o - ); - - // Number of memory operations in the accelerator - logic [2:0] acc_mem_cnt_q, acc_mem_cnt_d; - `FFAR(acc_mem_cnt_q, acc_mem_cnt_d, '0, clk_i, rst_i) - - // Number of store operations in the accelerator - logic [2:0] acc_mem_str_cnt_q, acc_mem_str_cnt_d; - `FFAR(acc_mem_str_cnt_q, acc_mem_str_cnt_d, '0, clk_i, rst_i) - - assign acc_mem_stall = (is_store && acc_mem_cnt_q != '0) || (is_load && acc_mem_str_cnt_q != 0) || acc_mem_cnt_q == '1; - - always_comb begin - acc_mem_cnt_d = acc_mem_cnt_q; - acc_mem_str_cnt_d = acc_mem_str_cnt_q; - - if (acc_qdata_rsp_i.loadstore && acc_qready_i && acc_qvalid_o) - acc_mem_cnt_d += 1; - if (acc_mem_finished_i[0]) - acc_mem_cnt_d -= 1; - if (acc_mem_finished_i[1]) - acc_mem_cnt_d -= 1; - - if (acc_qdata_rsp_i.loadstore && acc_qready_i && acc_qvalid_o && acc_mem_store) - acc_mem_str_cnt_d += 1; - if (acc_mem_finished_i[0] && acc_mem_str_finished_i[0]) - acc_mem_str_cnt_d -= 1; - if (acc_mem_finished_i[1] && acc_mem_str_finished_i[1]) - acc_mem_str_cnt_d -= 1; - end - - `ASSERT(MemoryOperationCounterRollover, - acc_mem_cnt_q == '0 |=> acc_mem_cnt_q != '1, clk_i, rst_i) - - `ASSERT(MemoryStoreOperationCounterRollover, - acc_mem_str_cnt_q == '0 |=> acc_mem_str_cnt_q != '1, clk_i, rst_i) - - // address can be alu_result (i.e. rs1 + iimm/simm) or rs1 (for post-increment load/stores) - assign lsu_qaddr = is_postincr ? gpr_rdata[0] : alu_result; - - assign lsu_qvalid = valid_instr & (is_load | is_store) & ~(ld_addr_misaligned | st_addr_misaligned) & ~acc_mem_stall; - - // NOTE(smazzola): write-backs "on rd from non-load or non-acc instructions" and "on rs1 from - // post-increment instructions" in the same cycle should be mutually exclusive (currently valid - // assumption since write-back to rs1 happens on the cycle in which the post-increment load/store - // is issued, if that cycle is not a stall, and it is not postponed like offloaded instructions, - // so no other instructions writing back on rd can be issued in the same cycle) - // retire post-incremented address on rs1 if valid postincr instruction and LSU not stalling - assign retire_p = write_rs1 & ~stall & (rs1 != 0); - // we can retire if we are not stalling and if the instruction is writing a register - assign retire_i = write_rd & valid_instr & (rd != 0); - - // ----------------------- - // Unaligned Address Check - // ----------------------- - always_comb begin - ls_misaligned = 1'b0; - unique case (ls_size) - HalfWord: if (alu_result[0] != 1'b0) ls_misaligned = 1'b1; - Word: if (alu_result[1:0] != 2'b00) ls_misaligned = 1'b1; - Double: if (alu_result[2:0] != 3'b000) ls_misaligned = 1'b1; - default: ls_misaligned = 1'b0; - endcase - end - - assign st_addr_misaligned = ls_misaligned & (is_store | is_fp_store); - assign ld_addr_misaligned = ls_misaligned & (is_load | is_fp_load); - - // pragma translate_off - always_ff @(posedge clk_i or posedge rst_i) begin - if (!rst_i && (ld_addr_misaligned || st_addr_misaligned) && valid_instr && inst_ready_i) begin - $display("%t: [Misaligned Load/Store Core %0d] PC: %h Address: %h Data: %h", $time, hart_id_i, inst_addr_o, alu_result, inst_data_i); - end - end - // pragma translate_on - - // -------------------- - // Write-Back - // -------------------- - // Write-back data, can come from: - // 1. ALU/Jump Target/Bypass - // 2. LSU - // 3. Accelerator Bus - logic [31:0] alu_writeback; - always_comb begin - casez (rd_select) - RdAlu: alu_writeback = alu_result; - RdConsecPC: alu_writeback = consec_pc; - RdBypass: alu_writeback = rd_bypass; - default: alu_writeback = alu_result; - endcase - end - - if (RegNrWritePorts == 1) begin - always_comb begin - gpr_we[0] = 1'b0; - // NOTE(smazzola): this works because write-backs on rd and rs1 in the same cycle are mutually - // exclusive; if this should change, the following statement has to be written in another form - gpr_waddr[0] = retire_p ? rs1 : rd; // choose whether to writeback at RF[rs1] for post-increment load/stores - gpr_wdata[0] = alu_writeback; - // external interfaces - lsu_pready = 1'b0; - acc_pready_o = 1'b0; - retire_acc = 1'b0; - retire_load = 1'b0; - - if (retire_i | retire_p) begin - gpr_we[0] = 1'b1; - end else begin - // if we are not retiring another instruction retire the load now - lsu_pready = 1'b1; - if (lsu_pvalid) begin - retire_load = 1'b1; - gpr_we[0] = 1'b1; - gpr_waddr[0] = lsu_rd; - gpr_wdata[0] = ld_result[31:0]; - end else if (acc_pvalid_i & acc_pwrite_i) begin - // if we are not retiring another instruction retire the accelerated one now - retire_acc = 1'b1; - gpr_we[0] = 1'b1; - gpr_waddr[0] = acc_pid_i; - gpr_wdata[0] = acc_pdata_i[31:0]; - acc_pready_o = 1'b1; - end - end - end - end else if (RegNrWritePorts == 2) begin - always_comb begin - gpr_we[0] = 1'b0; - // NOTE(smazzola): this works because write-backs on rd and rs1 in the same cycle are mutually - // exclusive; if this should change, the following statement has to be written in another form - gpr_waddr[0] = retire_p ? rs1 : rd; // choose whether to writeback at RF[rs1] for post-increment load/stores - gpr_wdata[0] = alu_writeback; - gpr_we[1] = 1'b0; - gpr_waddr[1] = lsu_rd; - gpr_wdata[1] = ld_result[31:0]; - // external interfaces - // Snitch and LSU have priority - // lsu_pready = 1'b1; - lsu_pready = 1'b0; - acc_pready_o = 1'b0; - retire_acc = 1'b0; - retire_load = 1'b0; - - if (retire_i | retire_p) begin - gpr_we[0] = 1'b1; - if (lsu_pvalid) begin - retire_load = 1'b1; - gpr_we[1] = 1'b1; - lsu_pready = 1'b1; - end else if (acc_pvalid_i & acc_pwrite_i) begin - retire_acc = 1'b1; - gpr_we[1] = 1'b1; - gpr_waddr[1] = acc_pid_i; - gpr_wdata[1] = acc_pdata_i[31:0]; - acc_pready_o = 1'b1; - end - // if we are not retiring another instruction retire the load now - end else begin - if (acc_pvalid_i & acc_pwrite_i) begin - retire_acc = 1'b1; - gpr_we[0] = 1'b1; - gpr_waddr[0] = acc_pid_i; - gpr_wdata[0] = acc_pdata_i[31:0]; - acc_pready_o = 1'b1; - end - if (lsu_pvalid) begin - retire_load = 1'b1; - gpr_we[1] = 1'b1; - lsu_pready = 1'b1; - end - end - end - end else begin - $fatal(1, "[snitch] Unsupported RegNrWritePorts."); - end - - // -------------------- - // Stack overflow check - // -------------------- - - // pragma translate_off - for (genvar i = 0; i < RegNrWritePorts; i++) begin : gen_stack_overflow_check - logic [31:0] sp_new_value; - assign sp_new_value = gpr_wdata[i]; - always_ff @(posedge clk_i or posedge rst_i) begin - if (!rst_i && gpr_we[i] && gpr_waddr[i] == SP && csr_stack_limit_q != 32'hFFFF_FFFF && ($signed(sp_new_value) < $signed(csr_stack_limit_q))) begin - $warning("[Stackoverflow: Core %0d] Set SP to 0x%08h, limit is 0x%08h", hart_id_i, sp_new_value, csr_stack_limit_q); - end - end - end - // pragma translate_on - - // -------------------------- - // RISC-V Formal Interface - // -------------------------- - `ifdef RISCV_FORMAL - logic instr_addr_misaligned; - logic ld_addr_misaligned_q; - // check that the instruction is a control transfer instruction - assign instr_addr_misaligned = (inst_data_i inside { - riscv_instr::JAL, - riscv_instr::JALR, - riscv_instr::BEQ, - riscv_instr::BNE, - riscv_instr::BLT, - riscv_instr::BLTU, - riscv_instr::BGE, - riscv_instr::BGEU - }) && (pc_d[1:0] != 2'b0); - - - // retire an instruction and increase ordering bit - `FFLAR(rvfi_order[0], rvfi_order[0] + 1, rvfi_valid[0], '0, clk_i, rst_i) - - logic [31:0] ld_instr_q; - logic [31:0] ld_addr_q; - logic [4:0] rs1_q; - logic [31:0] rs1_data_q; - logic [31:0] pc_qq; - // we need to latch the load - `FFLAR(ld_instr_q, inst_data_i, latch_load, '0, clk_i, rst_i) - `FFLAR(ld_addr_q, data_qaddr_o, latch_load, '0, clk_i, rst_i) - `FFLAR(rs1_q, rs1, latch_load, '0, clk_i, rst_i) - `FFLAR(rs1_data_q, gpr_rdata[0], latch_load, '0, clk_i, rst_i) - `FFLAR(pc_qq, pc_d, latch_load, '0, clk_i, rst_i) - `FFLAR(ld_addr_misaligned_q, ld_addr_misaligned, latch_load, '0, clk_i, rst_i) - - // in case we don't retire another instruction on port 1 we can use it for loads - logic retire_load_port1; - - assign retire_load_port1 = retire_load & stall; - // NRET: 1 - assign rvfi_halt[0] = 1'b0; - assign rvfi_mode[0] = 2'b11; - assign rvfi_intr[0] = 1'b0; - assign rvfi_valid[0] = !stall | retire_load; - assign rvfi_insn[0] = retire_load_port1 ? ld_instr_q : (is_load ? '0 : inst_data_i); - assign rvfi_trap[0] = retire_load_port1 ? ld_addr_misaligned_q : illegal_inst - | instr_addr_misaligned - | st_addr_misaligned; - assign rvfi_rs1_addr[0] = (retire_load_port1) ? rs1_q : rs1; - assign rvfi_rs1_rdata[0] = (retire_load_port1) ? rs1_data_q : gpr_rdata[0]; - assign rvfi_rs2_addr[0] = (retire_load_port1) ? '0 : rs2; - assign rvfi_rs2_rdata[0] = (retire_load_port1) ? '0 : gpr_rdata[1]; - assign rvfi_rd_addr[0] = (retire_load_port1) ? lsu_rd : ((gpr_we[0] && write_rd) ? rd : '0); - assign rvfi_rd_wdata[0] = (retire_load_port1) ? (lsu_rd != 0 ? ld_result[31:0] : '0) : (rd != 0 && gpr_we[0] && write_rd) ? gpr_wdata[0] : 0; - assign rvfi_pc_rdata[0] = (retire_load_port1) ? pc_qq : pc_q; - assign rvfi_pc_wdata[0] = (retire_load_port1) ? (pc_qq + 4) : pc_d; - assign rvfi_mem_addr[0] = (retire_load_port1) ? ld_addr_q : data_qaddr_o; - assign rvfi_mem_wmask[0] = (retire_load_port1) ? '0 : ((data_qvalid_o && data_qready_i) ? data_qstrb_o[3:0] : '0); - assign rvfi_mem_rmask[0] = (retire_load_port1) ? 4'hf : '0; - assign rvfi_mem_rdata[0] = (retire_load_port1) ? data_pdata_i[31:0] : '0; - assign rvfi_mem_wdata[0] = (retire_load_port1) ? '0 : data_qdata_o[31:0]; - `endif - - // ---------- - // Assertions - // ---------- - // Make sure the instruction interface is stable. Otherwise, Snitch might violate the protocol at - // the LSU or accelerator interface by withdrawing the valid signal. - `ASSERT(InstructionInterfaceStable, - (inst_valid_o && inst_ready_i) ##1 (inst_valid_o && $stable(inst_addr_o)) - |-> inst_ready_i && $stable(inst_data_i), clk_i, rst_i) - -endmodule diff --git a/hardware/deps/snitch/src/snitch_pkg.sv b/hardware/deps/snitch/src/snitch_pkg.sv index a79f183cc..970840756 100644 --- a/hardware/deps/snitch/src/snitch_pkg.sv +++ b/hardware/deps/snitch/src/snitch_pkg.sv @@ -10,6 +10,7 @@ package snitch_pkg; localparam DataWidth = 32; localparam StrbWidth = DataWidth/8; localparam int NumFPOutstandingLoads = 4; + localparam int AccIdWidth = `ifdef TARGET_SPATZ 6 `else 5 `endif; // Use a high number of outstanding loads, if running a latency-throughput analysis localparam int NumIntOutstandingLoads = `ifdef TRAFFIC_GEN 2048 `else 8 `endif; localparam MetaIdWidth = idx_width(NumIntOutstandingLoads); @@ -48,7 +49,7 @@ package snitch_pkg; typedef struct packed { addr_t addr; - logic [5:0] id; + logic [AccIdWidth-1:0] id; logic [31:0] data_op; data_t data_arga; data_t data_argb; @@ -56,7 +57,7 @@ package snitch_pkg; } acc_req_t; typedef struct packed { - logic [5:0] id; + logic [AccIdWidth-1:0] id; logic error; data_t data; logic write; diff --git a/hardware/spyglass/scripts/run_lint.tcl b/hardware/spyglass/scripts/run_lint.tcl index 0ca6eaede..c1fcdfc74 100644 --- a/hardware/spyglass/scripts/run_lint.tcl +++ b/hardware/spyglass/scripts/run_lint.tcl @@ -26,6 +26,22 @@ sdc_data -file sdc/func.sdc # Link Design compile_design +# Initial assignment for [] is ignored by synthesis. automatic logic +waive -rule "SYNTH_89" +# Unsigned element [] passed to the $unsigned() function call. +waive -rule "WRN_1024" +# Enable pin EN on Flop [] (master RTL_FDCE) is always disabled (tied low) +waive -rule "FlopEConst" +# Based number [] contains a dont care. riscv_instr.sv +waive -rule "W467" +# Rhs width with shift is less than lhs width. +waive -rule "W486" +# Variable [] set but not read. +waive -rule "W528" +# Signal [] is being assigned multiple times in the same block. +waive -rule "W415a" + + # Set lint_rtl goal and run current_goal lint/lint_rtl run_goal diff --git a/hardware/src/mempool_cc.sv b/hardware/src/mempool_cc.sv index 17b957e4b..170c5696c 100644 --- a/hardware/src/mempool_cc.sv +++ b/hardware/src/mempool_cc.sv @@ -115,64 +115,56 @@ module mempool_cc logic [1:0] spatz_mem_finished; logic [1:0] spatz_mem_str_finished; - - snitch_md #( + // Snitch Integer Core + snitch #( .BootAddr ( BootAddr ), .MTVEC ( MTVEC ), .RVE ( RVE ), .RVM ( RVM ), - .XFVEC ( 0 ), - .XFDOTP ( 0 ), - .XFAUX ( 0 ), - .RVF ( 0 ), - .RVD ( 0 ), - .XF16 ( 0 ), - .XF16ALT ( 0 ), - .XF8 ( 0 ), - .XF8ALT ( 0 ), .acc_issue_rsp_t ( acc_issue_rsp_t ) ) i_snitch ( - .clk_i ( clk_i ), // checked - .rst_i ( rst_i ), // checked - .hart_id_i ( hart_id_i ), // checked - .inst_addr_o ( inst_addr_o ), // checked - .inst_data_i ( inst_data_i ), // checked - .inst_valid_o ( inst_valid_o ), // checked - .inst_ready_i ( inst_ready_i ), // checked - .acc_qaddr_o ( acc_req_d.addr ), // checked - .acc_qid_o ( acc_req_d.id ), // checked - .acc_qdata_op_o ( acc_req_d.data_op ), // checked, 32 bits, HW - .acc_qdata_arga_o ( acc_req_d.data_arga ), // checked, 32 bits, HW - .acc_qdata_argb_o ( acc_req_d.data_argb ), // checked, 32 bits, HW - .acc_qdata_argc_o ( acc_req_d.data_argc ), // checked, 32 bits, HW - .acc_qvalid_o ( acc_req_d_valid ), // checked - .acc_qready_i ( acc_req_d_ready ), // checked - .acc_pdata_i ( acc_resp_q.data ), // checked, 32 bits, HW - .acc_pid_i ( acc_resp_q.id ), // checked, 4:0 - .acc_perror_i ( acc_resp_q.error ), // checked - .acc_pvalid_i ( acc_resp_q_valid ), // checked - .acc_pready_o ( acc_resp_q_ready ), // checked - .acc_qdata_rsp_i ( acc_req_rsp ), // used by spatz decoder - .acc_mem_finished_i ( spatz_mem_finished ), // used by spatz mem - .acc_mem_str_finished_i ( spatz_mem_str_finished ), // used by spatz mem - .data_qaddr_o ( data_req_d.addr ), // checked, 32 bits, HW - .data_qwrite_o ( data_req_d.write ), // checked - .data_qamo_o ( data_req_d.amo ), // checked - .data_qdata_o ( data_req_d.data ), // checked, 32 bits, HW - .data_qstrb_o ( data_req_d.strb ), // checked - .data_qid_o ( data_req_d.id ), // MetaIdWidth - .data_qvalid_o ( data_req_d_valid ), // checked - .data_qready_i ( data_req_d_ready ), // checked - .data_pdata_i ( data_resp_q.data ), // checked, 32 bits, HW - .data_perror_i ( data_resp_q.error ), // chekced - .data_pid_i ( data_resp_q.id ), // MetaIdWidth - .data_pvalid_i ( data_resp_q_valid ), // checked - .data_pready_o ( data_resp_q_ready ), // checked - .wake_up_sync_i ( wake_up_sync_i ), // checked - .fpu_fmt_mode_o ( fpu_fmt_mode ), // checked - .fpu_rnd_mode_o ( fpu_rnd_mode ), // used by spatz, FPU - .fpu_status_i ( fpu_status ), // used by spatz, FPU - .core_events_o ( core_events_o ) // checked + .clk_i ( clk_i ), + .rst_i ( rst_i ), + .hart_id_i ( hart_id_i ), + .inst_addr_o ( inst_addr_o ), + .inst_data_i ( inst_data_i ), + .inst_valid_o ( inst_valid_o ), + .inst_ready_i ( inst_ready_i ), + .acc_qaddr_o ( acc_req_d.addr ), + .acc_qid_o ( acc_req_d.id ), + .acc_qdata_op_o ( acc_req_d.data_op ), + .acc_qdata_arga_o ( acc_req_d.data_arga ), + .acc_qdata_argb_o ( acc_req_d.data_argb ), + .acc_qdata_argc_o ( acc_req_d.data_argc ), + .acc_qvalid_o ( acc_req_d_valid ), + .acc_qready_i ( acc_req_d_ready ), + .acc_pdata_i ( acc_resp_q.data ), + .acc_pid_i ( acc_resp_q.id ), + .acc_pwrite_i ( 1'b1 ), // only used for Spatz, tie to 1 here + .acc_perror_i ( acc_resp_q.error ), + .acc_pvalid_i ( acc_resp_q_valid ), + .acc_pready_o ( acc_resp_q_ready ), + .acc_qdata_rsp_i ( acc_req_rsp ), + .acc_mem_finished_i ( spatz_mem_finished ), + .acc_mem_str_finished_i ( spatz_mem_str_finished ), + .data_qaddr_o ( data_req_d.addr ), + .data_qwrite_o ( data_req_d.write ), + .data_qamo_o ( data_req_d.amo ), + .data_qdata_o ( data_req_d.data ), + .data_qstrb_o ( data_req_d.strb ), + .data_qid_o ( data_req_d.id ), + .data_qvalid_o ( data_req_d_valid ), + .data_qready_i ( data_req_d_ready ), + .data_pdata_i ( data_resp_q.data ), + .data_perror_i ( data_resp_q.error ), + .data_pid_i ( data_resp_q.id ), + .data_pvalid_i ( data_resp_q_valid ), + .data_pready_o ( data_resp_q_ready ), + .wake_up_sync_i ( wake_up_sync_i ), + .fpu_fmt_mode_o ( fpu_fmt_mode ), + .fpu_rnd_mode_o ( fpu_rnd_mode ), + .fpu_status_i ( fpu_status ), + .core_events_o ( core_events_o ) ); assign spatz_mem_finished = '0; @@ -346,7 +338,9 @@ module mempool_cc extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "writeback", i_snitch.alu_writeback); // Load/Store extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "gpr_rdata_1", i_snitch.gpr_rdata[1]); +`ifdef XPULPIMG_EXTENSION extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "gpr_rdata_2", i_snitch.gpr_rdata[2]); +`endif extras_str = $sformatf("%s'%s': 0x%1x, ", extras_str, "ls_size", i_snitch.ls_size); extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "ld_result_32",i_snitch.ld_result[31:0]); extras_str = $sformatf("%s'%s': 0x%2x, ", extras_str, "lsu_rd", i_snitch.lsu_rd); diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv index b8bf9b2e3..3fe8b70b0 100644 --- a/hardware/src/mempool_pkg.sv +++ b/hardware/src/mempool_pkg.sv @@ -28,9 +28,18 @@ package mempool_pkg; localparam integer unsigned AxiLiteDataWidth = 32; // Extension support - localparam bit RVV = `ifdef RVV `RVV `else 0 `endif; - localparam bit RVF = `ifdef RVF `RVF `else 0 `endif; - localparam bit RVD = `ifdef RVD `RVD `else 0 `endif; + localparam bit RVV = `ifdef RVV `RVV `else 0 `endif; + localparam bit RVF = `ifdef RVF `RVF `else 0 `endif; + localparam bit RVD = `ifdef RVD `RVD `else 0 `endif; + localparam bit XFVEC = 0; + localparam bit XFDOTP = (RVF|RVD) ? 1 : 0; + localparam bit XFAUX = 0; + localparam bit XF16 = (RVF|RVD) ? 1 : 0; + localparam bit XF16ALT = 0; + localparam bit XF8 = (RVF|RVD) ? 1 : 0; + localparam bit XF8ALT = 0; + /// Enable div/sqrt unit (buggy - use with caution) + localparam bit XDivSqrt = 0; // Derived parameters localparam integer unsigned NumIPUsPerCore = `ifdef N_IPU `N_IPU `else 1 `endif; diff --git a/hardware/src/mempool_tile.sv b/hardware/src/mempool_tile.sv index 03cd65d08..c24c2c1ad 100644 --- a/hardware/src/mempool_tile.sv +++ b/hardware/src/mempool_tile.sv @@ -127,8 +127,18 @@ module mempool_tile `else spatz_mempool_cc #( .BootAddr ( BootAddr ), - .RVE ( 0 ), - .RVM ( 1 ), + .RVE ( 0 ), + .RVM ( 1 ), + .RVV ( RVV ), + .XFVEC ( XFVEC ), + .XFDOTP ( XFDOTP ), + .XFAUX ( XFAUX ), + .RVF ( RVF ), + .RVD ( RVD ), + .XF16 ( XF16 ), + .XF16ALT ( XF16ALT ), + .XF8 ( XF8 ), + .XDivSqrt ( XDivSqrt ), .NumMemPortsPerSpatz ( NumMemPortsPerSpatz ), .TCDMPorts ( NumDataPortsPerCore ) ) diff --git a/software/apps/sp-axpy-simple/data/data_axpy-vsim-backup.h b/software/apps/sp-axpy-simple/data/data_axpy-vsim-backup.h deleted file mode 100644 index a52818f09..000000000 --- a/software/apps/sp-axpy-simple/data/data_axpy-vsim-backup.h +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "layer.h" - -const axpy_layer axpy_l = { - .M = 512, - .dtype = FP32, -}; - - -static const float axpy_X_dram [512] = {1.9269152879714966, 1.4872840642929077, 0.9007171988487244, -2.1055209636688232, 0.6784184575080872, -1.2345448732376099, -0.04306747764348984, -1.6046669483184814, -0.7521352767944336, 1.6487230062484741, -0.3924786448478699, -1.4036071300506592, -0.7278813123703003, -0.5594301819801331, -0.7688388824462891, 0.7624453902244568, 1.6423169374465942, -0.1595974713563919, -0.4973975419998169, 0.439589262008667, -0.7581311464309692, 1.078317642211914, 0.8008005619049072, 1.680620551109314, 1.27912437915802, 1.2964228391647339, 0.610466480255127, 1.334737777709961, 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0.575005054473877, -0.6417241096496582, -2.2063984870910645, -0.7508030533790588, 0.01086814422160387, -0.33874234557151794, -1.3406795263290405, -0.5853705406188965, 0.5361881256103516, 0.5246226191520691, 1.1412016153335571, 0.05164359509944916, 0.7439519762992859, -0.4815843999385834, -1.0494661331176758, 0.603898823261261, -1.7222950458526611, -0.827768862247467, 1.334702968597412, 0.48353928327560425, -2.5095443725585938, 0.4880010485649109, 0.7845868468284607, 0.02864718623459339, 0.640755295753479, 0.5832474231719971, 1.0669267177581787, -0.4501533806324005, -0.18526747822761536, 0.7527588605880737, 0.4047577977180481, 0.17846599221229553, 0.2649095058441162, 1.2731683254241943, -0.0013108636485412717, -0.30360376834869385, -1.457029104232788, -0.10233523696660995, -0.5991530418395996, 0.4770564138889313, 0.7261772155761719, 0.09115186333656311, -0.3890652060508728, 0.5279164910316467, -0.012685478664934635, 0.24083632230758667, 0.13253536820411682, 0.7642406225204468, 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0.6214459538459778, 0.42318588495254517, -0.33889833092689514, 0.5179733633995056}; - - -static const float axpy_Y_dram [512] = {-1.363769769668579, 0.1929578185081482, -0.6103342771530151, 0.16323445737361908, 1.51017165184021, 0.21230429410934448, -0.7252011299133301, -0.9527732729911804, 0.5216943025588989, -0.46386733651161194, 0.18237744271755219, -0.38666075468063354, -1.7906768321990967, 0.09329313784837723, -1.9152568578720093, -0.6421752572059631, 1.3438509702682495, -1.2922308444976807, 0.766244113445282, 0.64540034532547, 0.353316068649292, -2.6474881172180176, -1.4575366973876953, -0.9712379574775696, 0.25403109192848206, -0.1790592074394226, 1.1992844343185425, -0.4292171895503998, 1.010284185409546, 0.6110401153564453, 1.2208385467529297, -0.6076440215110779, -1.7376028299331665, -0.12535162270069122, -1.3658148050308228, 1.111746072769165, -0.6227966547012329, -0.7891808748245239, -0.167823925614357, 1.6433145999908447, 2.0070879459381104, -1.2531019449234009, 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-#include "layer.h" - -const axpy_layer axpy_l = { - .M = 256, - .dtype = FP32, -}; - - -static float axpy_X_dram [256] __attribute__((section(".data"))) = {1.9269152879714966, 1.4872840642929077, 0.9007171988487244, -2.1055209636688232, 0.6784184575080872, -1.2345448732376099, -0.04306747764348984, -1.6046669483184814, -0.7521352767944336, 1.6487230062484741, -0.3924786448478699, -1.4036071300506592, -0.7278813123703003, -0.5594301819801331, -0.7688388824462891, 0.7624453902244568, 1.6423169374465942, -0.1595974713563919, -0.4973975419998169, 0.439589262008667, -0.7581311464309692, 1.078317642211914, 0.8008005619049072, 1.680620551109314, 1.27912437915802, 1.2964228391647339, 0.610466480255127, 1.334737777709961, -0.2316243201494217, 0.041759490966796875, -0.2515752911567688, 0.859858512878418, -1.3846737146377563, -0.8712361454963684, -0.223365917801857, 1.7173614501953125, 0.3188803195953369, -0.42451897263526917, 0.3057209253311157, -0.7745925188064575, -1.5575724840164185, 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-1.5012763738632202, -1.9266542196273804, 0.1278512328863144, 1.0229133367538452, -0.5557951331138611, 0.7042727470397949, 0.7098760008811951, 1.7743884325027466, -0.921550989151001, 0.9624499082565308, -0.33701515197753906, -1.1753336191177368, 0.35805708169937134, 0.47876790165901184, 1.353700041770935, 0.5260620713233948, 2.1120378971099854, -0.5207571387290955, -0.9320061206817627, 0.18516133725643158, 1.0686918497085571, 1.3065344095230103, 0.4598345160484314, -0.8146268725395203, -1.0212392807006836, -0.49492356181144714, -0.5922516584396362, 0.15431594848632812, 0.4407670795917511, -0.14829230308532715, -2.3184432983398438, -0.39799532294273376, 1.0804862976074219, -1.7808643579483032, 1.5080454349517822, 0.30942854285240173, -0.5003090500831604, 1.0350031852722168, 1.6896470785140991, -0.004505051765590906, 1.666792392730713, 0.15392017364501953, -1.0602530241012573, -0.572657585144043, 0.0835680365562439, 0.39990535378456116, 1.989207148551941, -0.07198750972747803, -0.906094491481781, -2.0487122535705566, -1.0810555219650269, 0.01762307994067669, 0.0782259851694107, 0.19315829873085022, 0.40967342257499695, -0.9291303157806396, 0.2761908769607544, -0.5388752818107605, 0.4625823199748993, -0.8718891143798828, -0.027118360623717308, -0.3532457649707794, 1.4638569355010986, 1.255434274673462, -0.7149558067321777, 0.8539193272590637, 0.512991189956665, 0.5397310256958008, 0.5655050277709961, 0.5057917237281799, 0.22245365381240845}; - - -static float axpy_Y_dram [256] __attribute__((section(".data"))) = {-0.685481607913971, 0.5635589957237244, -1.507175087928772, -1.610666036605835, -1.4790465831756592, 0.4322742819786072, -0.1250254064798355, 0.7821183800697327, -1.598767638206482, -0.10912995040416718, 0.7151994705200195, 0.03913922235369682, 1.305860161781311, 0.24659274518489838, -1.9775909185409546, 0.01789604313671589, -1.3793021440505981, 0.625802755355835, -2.5849502086639404, -0.02399955503642559, -0.1221928745508194, -0.7469954490661621, 1.7093087434768677, 0.05792269483208656, 1.1929805278778076, 1.9372931718826294, 0.7287133932113647, 0.9808937907218933, 0.41459226608276367, 1.15656316280365, 0.2690545618534088, -0.036629438400268555, 0.9732939004898071, -1.0150787830352783, -0.5419175624847412, -0.44102486968040466, -0.3136177957057953, -0.12925422191619873, -0.7149624228477478, -0.047562163323163986, 2.0207436084747314, 0.25391900539398193, 0.9364385008811951, 0.7122363448143005, -0.031765542924404144, 0.10164086520671844, 1.3433040380477905, 0.7132695913314819, 0.4038029611110687, -0.7139783501625061, 0.8337291479110718, -0.9585452079772949, 0.45363426208496094, 1.2460919618606567, -2.3065085411071777, -1.2868918180465698, 0.17988650500774384, -2.126762628555298, -0.13408313691616058, -1.0407685041427612, -0.7647228837013245, -0.05528254434466362, 1.204850673675537, -0.982473611831665, 0.4334380030632019, -0.7171905636787415, 1.055369257926941, -1.4533969163894653, 0.46515071392059326, 0.37139150500297546, -0.004656785633414984, 0.07954943925142288, 0.3781784772872925, 0.7051141262054443, -1.7236974239349365, -0.8434810638427734, 0.4351435601711273, 0.26588720083236694, -0.5870985388755798, 0.0826888456940651, 0.8853808045387268, 0.1824439913034439, 0.7863810062408447, -0.057920295745134354, 0.5666652917861938, -0.7097623348236084, -0.4875054359436035, 0.050095997750759125, 0.6084084510803223, 1.6308681964874268, -0.08472306281328201, 1.0844124555587769, 0.9477656483650208, -0.676629364490509, -0.5730168223381042, -0.3303174376487732, -0.7939430475234985, 0.3752319812774658, 0.08790969103574753, -1.241483449935913, -0.32025346159935, -0.844377875328064, -0.5513465404510498, 1.9889612197875977, 1.900311827659607, 1.6950805187225342, 0.028089528903365135, -0.17536965012550354, -1.7734959125518799, -0.7046414017677307, -0.39465200901031494, 1.8868111371994019, -0.21844321489334106, 0.16629981994628906, 2.1441681385040283, 1.7045671939849854, 0.3459012508392334, 0.6424751281738281, -0.20395424962043762, 0.6853673458099365, -0.13968797028064728, -1.1807502508163452, -1.282929539680481, 0.448485791683197, -0.590737521648407, 0.8540631532669067, -0.4900680184364319, -0.35945725440979004, 0.6663737893104553, -0.07426456362009048, -0.20960482954978943, 0.16632132232189178, 1.4703037738800049, -0.9390866756439209, -0.6013189554214478, -0.09964022785425186, -0.9851518273353577, -2.488459348678589, -0.33131900429725647, 0.8435799479484558, 0.9874473810195923, -0.33197471499443054, -0.8076189756393433, 0.824364185333252, 0.024699924513697624, -1.0641486644744873, -0.7601934671401978, -0.4075061082839966, 0.9623646140098572, -0.14264194667339325, 0.15271379053592682, -0.0388023778796196, 0.9446058869361877, -1.5824053287506104, 0.9871290922164917, 1.1456739902496338, -0.14181147515773773, -0.2763414680957794, -0.19321373105049133, 0.7767809629440308, 0.6838752627372742, -1.3245893716812134, -0.5160817503929138, 0.6001842617988586, -0.4702208340167999, -0.6086435317993164, -0.046192023903131485, -1.6457397937774658, -0.4833274185657501, -0.740294337272644, 0.31428107619285583, 0.1415553092956543, 1.0348176956176758, -0.626437783241272, -0.5150922536849976, 0.6902899742126465, -0.4939993619918823, 1.1366126537322998, -0.46184006333351135, 1.419979453086853, 0.848518967628479, -0.047891248017549515, 0.6685602068901062, 1.0429801940917969, 0.6899017095565796, -1.3129348754882812, 0.03780364990234375, -1.1702114343643188, -0.10318559408187866, 1.1894739866256714, 0.7606944441795349, -0.7463049292564392, -1.3838845491409302, 0.4868715703487396, -1.0020296573638916, 0.0329488180577755, -0.42919591069221497, -0.9817978739738464, -0.6420586109161377, 0.8265887498855591, 1.591395616531372, -0.1208132952451706, -0.48302069306373596, 0.11329790204763412, 0.0771508663892746, -0.9228128790855408, -1.2619991302490234, 1.0860532522201538, 1.096641182899475, -0.6836934685707092, 0.06604336202144623, -0.0007737990817986429, 0.1620604395866394, 1.195958137512207, -1.3061535358428955, -1.4039719104766846, -1.0597201585769653, 0.3057299852371216, 0.4150581359863281, -0.7174144983291626, 2.833967924118042, 1.9534740447998047, 2.0486814975738525, -1.0880382061004639, 1.621694564819336, 0.8512656688690186, -0.40046969056129456, -0.6088271737098694, -0.508095383644104, -0.6184902191162109, -1.647040605545044, -1.0362098217010498, -0.4503057301044464, -0.0729660615324974, -0.5479549169540405, -1.1425532102584839, -0.44875210523605347, -0.03045438416302204, 0.3830311596393585, -0.04476971551775932, 1.179942011833191, -0.33142781257629395, 0.6495042443275452, 0.09495851397514343, -0.7525874376296997, -0.647229790687561, -1.2822614908218384, 1.96529221534729, -0.9638485312461853, -2.5667941570281982, 0.7096128463745117, 0.8198426961898804, 0.6214459538459778, 0.42318588495254517, -0.33889833092689514, 0.5179733633995056}; - - -static float axpy_alpha_dram __attribute__((section(".data"))) = {0.0354895144701004}; - - -static const float axpy_GR_dram[256] = {-0.6170963048934937, 0.6163420081138611, -1.47520911693573, -1.6853899955749512, -1.454969882965088, 0.3884608745574951, -0.12655384838581085, 0.7251695394515991, -1.6254605054855347, -0.05061757192015648, 0.701270580291748, -0.010674111545085907, 1.280027985572815, 0.226738840341568, -2.0048766136169434, 0.04495485872030258, -1.3210171461105347, 0.6201387047767639, -2.60260272026062, -0.008398745208978653, -0.14909857511520386, -0.7087264657020569, 1.7377287149429321, 0.11756710708141327, 1.2383760213851929, 1.9833025932312012, 0.7503785490989685, 1.028262972831726, 0.4063720405101776, 1.1580451726913452, 0.2601262629032135, -0.006113477051258087, 0.9241524934768677, -1.0459985733032227, -0.5498446822166443, -0.3800765573978424, -0.30230090022087097, -0.14432018995285034, -0.7041125297546387, -0.07505207508802414, 1.9654661417007446, 0.2892536520957947, 0.905215322971344, 0.6909021139144897, -0.07698455452919006, 0.1769774854183197, 1.299486756324768, 0.6959537863731384, 0.3713718354701996, -0.7373353242874146, 0.8364982008934021, -0.9398844838142395, 0.4363156855106354, 1.2883731126785278, -2.335397243499756, -1.313011884689331, 0.13008591532707214, -2.1254849433898926, -0.13633590936660767, -1.0167912244796753, -0.7681940197944641, 0.010181199759244919, 1.1628119945526123, -0.9333721399307251, 0.48472508788108826, -0.6867969036102295, 1.1340876817703247, -1.4348300695419312, 0.4774530231952667, 0.3643883168697357, -0.042083632200956345, 0.12490488588809967, 0.37206754088401794, 0.723703145980835, -1.721687912940979, -0.8283520340919495, 0.4555502235889435, 0.2431127279996872, -0.6654025316238403, 0.05604320764541626, 0.8857665061950684, 0.17042219638824463, 0.7388009428977966, -0.07869481295347214, 0.5856943726539612, -0.6911437511444092, -0.4470047354698181, 0.0519288033246994, 0.6348109245300293, 1.6137770414352417, -0.1219681054353714, 1.105844497680664, 0.8866422176361084, -0.7060064673423767, -0.525648832321167, -0.3131568729877472, -0.8830055594444275, 0.39255091547966003, 0.11575429886579514, -1.240466833114624, -0.29751336574554443, -0.823678731918335, -0.513481855392456, 1.9729855060577393, 1.893736720085144, 1.7217955589294434, 0.04245418682694435, -0.16903597116470337, -1.764094352722168, -0.659457266330719, -0.39469853043556213, 1.8760364055633545, -0.2701524794101715, 0.16266798973083496, 2.1229045391082764, 1.721497654914856, 0.37167292833328247, 0.6457100510597229, -0.21776197850704193, 0.7041028738021851, -0.140138179063797, -1.1722030639648438, -1.2782258987426758, 0.47560831904411316, -0.5518761873245239, 0.8661257028579712, -0.4645167291164398, -0.3448565900325775, 0.7349097728729248, -0.03835400938987732, -0.26058220863342285, 0.1262231469154358, 1.4654759168624878, -0.8810467720031738, -0.5780825018882751, -0.07919810712337494, -0.9446402788162231, -2.4878005981445312, -0.39540615677833557, 0.876423180103302, 0.9741265773773193, -0.29531094431877136, -0.8319878578186035, 0.846964418888092, -0.009819800034165382, -1.0301334857940674, -0.702728807926178, -0.35602468252182007, 0.9719283580780029, -0.15010808408260345, 0.12670697271823883, -0.03510089963674545, 0.9569829106330872, -1.5480659008026123, 0.9706020355224609, 1.202627420425415, -0.22982972860336304, -0.29115989804267883, -0.2356398105621338, 0.8056104183197021, 0.6164255738258362, -1.3164772987365723, -0.5151994824409485, 0.5879066586494446, -0.4600412845611572, -0.6345807909965515, -0.03998773917555809, -1.6845628023147583, -0.5401872992515564, -0.6922807097434998, 0.3600209355354309, 0.14341124892234802, 0.9799207448959351, -0.5995826721191406, -0.4875694513320923, 0.7622107267379761, -0.49272820353507996, 1.1408922672271729, -0.4904326796531677, 1.4126126766204834, 0.8154445886611938, -0.10435386747121811, 0.6282449960708618, 1.0244334936141968, 0.6714906692504883, -1.366214394569397, -0.030572369694709778, -1.165674090385437, -0.0668828934431076, 1.169749140739441, 0.7856887578964233, -0.7211117744445801, -1.3209123611450195, 0.4541661739349365, -0.9678727984428406, 0.020988313481211662, -0.47090792655944824, -0.9690905809402466, -0.6250673532485962, 0.8746309280395508, 1.6100653409957886, -0.04585809260606766, -0.5015020966529846, 0.08022145926952362, 0.08372215181589127, -0.8848855495452881, -1.2156308889389038, 1.1023725271224976, 1.06773042678833, -0.719936728477478, 0.04847876727581024, -0.021792521700263023, 0.16753703355789185, 1.2116007804870605, -1.3114163875579834, -1.4862523078918457, -1.0738447904586792, 0.34407591819763184, 0.3518561124801636, -0.6638947129249573, 2.84494948387146, 1.935718297958374, 2.0854132175445557, -1.0280734300613403, 1.6215347051620483, 0.9104193449020386, -0.3950071334838867, -0.6464550495147705, -0.5284187197685242, -0.615524411201477, -1.6328481435775757, -0.965613842010498, -0.4528605341911316, -0.10512291640043259, -0.6206626892089844, -1.1809192895889282, -0.4481266736984253, -0.02767818234860897, 0.3898862600326538, -0.030230604112148285, 1.1469676494598389, -0.3216259181499481, 0.6303797960281372, 0.11137533187866211, -0.7835303544998169, -0.6481922268867493, -1.2947980165481567, 2.0172438621520996, -0.9192937612533569, -2.592167615890503, 0.739918053150177, 0.83804851770401, 0.6406007409095764, 0.44325539469718933, -0.3209480345249176, 0.5258681178092957}; - - diff --git a/software/apps/sp-axpy-simple/main-vsim-backup.c b/software/apps/sp-axpy-simple/main-vsim-backup.c deleted file mode 100644 index c62be40e9..000000000 --- a/software/apps/sp-axpy-simple/main-vsim-backup.c +++ /dev/null @@ -1,206 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Domenic Wüthrich - -#include -#include -#include - -#include "data/data_axpy.h" -#include "printf.h" -#ifdef MEMPOOL -#include "alloc.h" -#include "runtime.h" -#include "synchronization.h" -#endif - -// dump(result, 1); -const unsigned int csize = 32; -const unsigned int core_count = 16; -const unsigned int esize = csize*core_count; - -float x[esize]; -float y[esize]; - -// Initialize the matrices -void init_matrix(float *matrix, const float *src, - const unsigned int num_columns, unsigned int cid) { - for (unsigned int j = cid*num_columns; j < (cid+1)*num_columns; ++j) - matrix[j] = src[j]; -} - -// Verify the matrices -int verify_matrix(float *matrix, const float *golden, - const unsigned int num_columns, unsigned int cid) { - int error = 0; - for (unsigned int j = cid*num_columns; j < (cid+1)*num_columns; ++j) { - float diff = matrix[j] - golden[j]; - if (diff < 0) - diff = -diff; - if (diff > 0.1f) - error ++; - } - return error; -} - -int main() { - const unsigned int num_cores = mempool_get_core_count(); - const unsigned int cores_per_group = num_cores / NUM_GROUPS; - const unsigned int cid = mempool_get_core_id(); - - unsigned int timer_start, timer_end, timer; - - // Initialize MemPool - mempool_init(cid); - - // Initialize multicore barrier - mempool_barrier_init(cid); - - // Reset timer - timer = (unsigned int)-1; - - // Wait for all cores to finish - mempool_barrier(num_cores); - - if (cid < core_count) { - if (cid == 0) - printf("initialize matrix\n"); - // for (unsigned int j = cid*csize; j < (cid+1)*csize; ++j) { - // x[j] = axpy_X_dram[j]; - // y[j] = axpy_Y_dram[j]; - // } - init_matrix(x, axpy_X_dram, csize, cid); - init_matrix(y, axpy_Y_dram, csize, cid); - } - - // Calculate local pointers - float *x_ = x + cid * csize; - float *y_ = y + cid * csize; - - // Initialize alpha - float alpha = axpy_alpha_dram; - - unsigned int remaining_elem = csize; - - mempool_barrier(num_cores); - - // if (cid != 0) { - // mempool_wfi(); - // } - - // printf("S:%d\n", cid); - // wake_up(cid + 1); - - // if (cid == 0) { - // printf("start kernel\n"); - // } - // Wait for all cores to finish - - // int32_t count = 0; - if (cid < core_count) { - while (remaining_elem > 0) { - timer_start = mempool_get_timer(); - // Set the VL - uint32_t actual_elem; - asm volatile("vsetvli %[gvl], %[vl], e32, m1, ta, ma" - : [gvl] "=r"(actual_elem) - : [vl] "r"(remaining_elem)); - - // if (cid == 0) - // printf("Start Load\n"); - // Load vectors - asm volatile("vle32.v v0, (%0)" ::"r"(x_)); - asm volatile("vle32.v v8, (%0)" ::"r"(y_)); - // if (cid == 0) - // printf("Finish Load\n"); - - // Multiply-accumulate - asm volatile("vfmacc.vf v8, %0, v0" ::"f"(alpha)); - // if (cid == 0) - // printf("Finish MACC\n"); - - // Store results - asm volatile("vse32.v v8, (%0)" ::"r"(y_)); - // if (cid == 15) - // printf("Finish Store\n"); - - // Bump pointers - remaining_elem -= actual_elem; - x_ += actual_elem; - y_ += actual_elem; - } - // printf("cid:%u count %d", cid, count); - } - - // if (cid != 0) { - // mempool_wfi(); - // } - - // printf("F:%d\n", cid); - // wake_up(cid + 1); - - // Wait for all cores to finish matmul - mempool_barrier(num_cores); - if(cid == 0) - printf("count\n"); - - // End timer and check if new best runtime - timer_end = mempool_get_timer(); - if (cid == 0) { - unsigned int timer_temp = timer_end - timer_start; - if (timer_temp < timer) { - timer = timer_temp; - } - } - - // Check and display results - if (cid == 0) { - unsigned int performance = 1000 * 2 * 16 / timer; - unsigned int utilization = performance / (2 * core_count * N_FPU); - - printf("\n----- (%u) axpy -----\n", esize); - printf("The execution took %u cycles.\n", timer); - printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", - performance, utilization); - } - - mempool_barrier(num_cores); - if (cid < core_count) { - int error = verify_matrix(y, axpy_GR_dram, csize, cid); - if (cid == 0) - printf("Errors: %d\n", error); - - // if (error != 0) { - // printf("Error: y[%d]=%04x\n", error, *(uint32_t *)(y + error)); - // return error; - // } - // for (int k = 0; k < 16; k ++) { - // if (ptr_vec_res[k] != axpy_GR_dram[k]) - // } - } - - // // Free the matrices - // if (cid == 0) { - // domain_free(get_alloc_tile(0), x); - // domain_free(get_alloc_tile(0), y); - // } - - // Wait for core 0 to finish displaying results - mempool_barrier(num_cores); - - return 0; -} diff --git a/software/apps/sp-axpy/data/data_axpy.h b/software/apps/sp-axpy/data/data_axpy.h new file mode 100644 index 000000000..3077dd228 --- /dev/null +++ b/software/apps/sp-axpy/data/data_axpy.h @@ -0,0 +1,24 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "layer.h" + +const axpy_layer axpy_l = { + .M = 4096, + .dtype = FP32, +}; + + +static float axpy_X_dram [4096] __attribute__((section(".data"))) = {1.9269152879714966, 1.4872840642929077, 0.9007171988487244, -2.1055209636688232, 0.6784184575080872, -1.2345448732376099, -0.04306747764348984, -1.6046669483184814, -0.7521352767944336, 1.6487230062484741, -0.3924786448478699, -1.4036071300506592, -0.7278813123703003, -0.5594301819801331, -0.7688388824462891, 0.7624453902244568, 1.6423169374465942, -0.1595974713563919, -0.4973975419998169, 0.439589262008667, -0.7581311464309692, 1.078317642211914, 0.8008005619049072, 1.680620551109314, 1.27912437915802, 1.2964228391647339, 0.610466480255127, 1.334737777709961, -0.2316243201494217, 0.041759490966796875, -0.2515752911567688, 0.859858512878418, -1.3846737146377563, -0.8712361454963684, -0.223365917801857, 1.7173614501953125, 0.3188803195953369, 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0.8184614777565002, -0.9922939538955688, -0.11898970603942871, 1.0721518993377686, 0.4724682867527008, 1.1534063816070557, 1.8505539894104004}; + + diff --git a/software/apps/sp-axpy-simple/data/layer.h b/software/apps/sp-axpy/data/layer.h similarity index 100% rename from software/apps/sp-axpy-simple/data/layer.h rename to software/apps/sp-axpy/data/layer.h diff --git a/software/apps/sp-axpy-simple/main.c b/software/apps/sp-axpy/main.c similarity index 55% rename from software/apps/sp-axpy-simple/main.c rename to software/apps/sp-axpy/main.c index 23de34716..14ddc0ab7 100644 --- a/software/apps/sp-axpy-simple/main.c +++ b/software/apps/sp-axpy/main.c @@ -29,29 +29,58 @@ #endif // dump(result, 1); -const unsigned int csize = 32; -const unsigned int core_count = 8; +const unsigned int csize = 256; +const unsigned int core_count = 16; const unsigned int esize = csize*core_count; float x[esize]; float y[esize]; +float r[esize]; +float alpha; + +// 32-bit AXPY: y = a * x + y +void faxpy_v32b(const float a, const float *x, const float *y, + unsigned int avl) { + unsigned int vl; + + // Stripmine and accumulate a partial vector + do { + // Set the vl + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + + // Load vectors + asm volatile("vle32.v v0, (%0)" ::"r"(x)); + asm volatile("vle32.v v8, (%0)" ::"r"(y)); + + // Multiply-accumulate + asm volatile("vfmacc.vf v8, %0, v0" ::"f"(a)); + + // Store results + asm volatile("vse32.v v8, (%0)" ::"r"(y)); + + // Bump pointers + x += vl; + y += vl; + avl -= vl; + } while (avl > 0); +} // Initialize the matrices void init_matrix(float *matrix, const float *src, - const unsigned int num_columns, unsigned int cid) { - for (unsigned int j = cid*num_columns; j < (cid+1)*num_columns; ++j) + const unsigned int size, unsigned int cid) { + for (unsigned int j = cid*size; j < (cid+1)*size; ++j) matrix[j] = src[j]; } // Verify the matrices int verify_matrix(float *matrix, const float *golden, - const unsigned int num_columns, unsigned int cid) { + const unsigned int size, unsigned int cid) { int error = 0; - for (unsigned int j = cid*num_columns; j < (cid+1)*num_columns; ++j) { + for (unsigned int j = cid*size; j < (cid+1)*size; ++j) { float diff = matrix[j] - golden[j]; if (diff < 0) diff = -diff; - if (diff > 0.01f) + if (diff > 0.001f) error ++; } return error; @@ -76,87 +105,31 @@ int main() { // Wait for all cores to finish mempool_barrier(num_cores); + float *x_, *y_; + alpha = axpy_alpha_dram; + unsigned int remaining_elem; + + if (cid < core_count) { - if (cid == 0) - printf("initialize matrix\n"); - // for (unsigned int j = cid*csize; j < (cid+1)*csize; ++j) { - // x[j] = axpy_X_dram[j]; - // y[j] = axpy_Y_dram[j]; - // } init_matrix(x, axpy_X_dram, csize, cid); init_matrix(y, axpy_Y_dram, csize, cid); + init_matrix(r, axpy_GR_dram, csize, cid); + x_ = x + cid * csize; + y_ = y + cid * csize; } - // Calculate local pointers - float *x_ = x + cid * csize; - float *y_ = y + cid * csize; - - // Initialize alpha - float alpha = axpy_alpha_dram; - - unsigned int remaining_elem = csize; + if (cid == 0) + printf("start calc\n"); mempool_barrier(num_cores); - // if (cid != 0) { - // mempool_wfi(); - // } - - // printf("S:%d\n", cid); - // wake_up(cid + 1); - - // if (cid == 0) { - // printf("start kernel\n"); - // } - // Wait for all cores to finish - - // int32_t count = 0; if (cid < core_count) { - while (remaining_elem > 0) { - timer_start = mempool_get_timer(); - // Set the VL - uint32_t actual_elem; - asm volatile("vsetvli %[gvl], %[vl], e32, m1, ta, ma" - : [gvl] "=r"(actual_elem) - : [vl] "r"(remaining_elem)); - - // if (cid == 0) - // printf("Start Load\n"); - // Load vectors - asm volatile("vle32.v v0, (%0)" ::"r"(x_)); - asm volatile("vle32.v v8, (%0)" ::"r"(y_)); - // if (cid == 0) - // printf("Finish Load\n"); - - // Multiply-accumulate - asm volatile("vfmacc.vf v8, %0, v0" ::"f"(alpha)); - // if (cid == 0) - // printf("Finish MACC\n"); - - // Store results - asm volatile("vse32.v v8, (%0)" ::"r"(y_)); - // if (cid == 7) - // printf("Finish Store\n"); - - // Bump pointers - remaining_elem -= actual_elem; - x_ += actual_elem; - y_ += actual_elem; - } - // printf("cid:%u count %d", cid, count); + timer_start = mempool_get_timer(); + faxpy_v32b(alpha, x_, y_, csize); } - // if (cid != 0) { - // mempool_wfi(); - // } - - // printf("F:%d\n", cid); - // wake_up(cid + 1); - // Wait for all cores to finish matmul mempool_barrier(num_cores); - if(cid == 0) - printf("finish calc\n"); // End timer and check if new best runtime timer_end = mempool_get_timer(); @@ -182,18 +155,13 @@ int main() { if (cid == 0) printf("start check\n"); - // if (cid < core_count) { - // int error = verify_matrix(y, axpy_GR_dram, csize, cid); - // if (error > 0) - // printf("%d,Errors: %d\n", cid, error); - // } if (cid == 0) { - int error = verify_matrix(y, axpy_GR_dram, esize, cid); + int error = verify_matrix(y, r, esize, cid); printf("Errors: %d\n", error); } // Wait for core 0 to finish displaying results mempool_barrier(num_cores); - return 0; + return error; } diff --git a/software/apps/sp-axpy-simple/script/axpy.json b/software/apps/sp-axpy/script/axpy.json similarity index 94% rename from software/apps/sp-axpy-simple/script/axpy.json rename to software/apps/sp-axpy/script/axpy.json index 7b7cad730..fd83adc33 100644 --- a/software/apps/sp-axpy-simple/script/axpy.json +++ b/software/apps/sp-axpy/script/axpy.json @@ -6,6 +6,6 @@ { kernel: "AXPY" - M: 256, + M: 4096, prec: 32 } diff --git a/software/apps/sp-axpy-simple/script/gen_data.py b/software/apps/sp-axpy/script/gen_data.py similarity index 99% rename from software/apps/sp-axpy-simple/script/gen_data.py rename to software/apps/sp-axpy/script/gen_data.py index 45084cdd2..92102e86f 100755 --- a/software/apps/sp-axpy-simple/script/gen_data.py +++ b/software/apps/sp-axpy/script/gen_data.py @@ -95,7 +95,7 @@ def emit_axpy_layer(name='axpy', **kwargs): layer_str += f'static {dtype} {name}_X_dram [{m}] __attribute__((section(".data"))) = ' + array_to_cstr(vec_X) + ';\n\n\n' layer_str += f'static {dtype} {name}_Y_dram [{m}] __attribute__((section(".data"))) = ' + array_to_cstr(vec_Y) + ';\n\n\n' layer_str += f'static {dtype} {name}_alpha_dram __attribute__((section(".data"))) = ' + array_to_cstr(alpha) + ';\n\n\n' - layer_str += f'static const {dtype} {name}_GR_dram[{m}] = ' + array_to_cstr(result) + ';\n\n\n' + layer_str += f'static {dtype} {name}_GR_dram[{m}] __attribute__((section(".data"))) = ' + array_to_cstr(result) + ';\n\n\n' else: layer_str += f'static {dtype} {name}_X_dram [{m}] = ' + \ array_to_cstr(kwargs['bits_X'], fmt='char') + ';\n\n\n'