From afb0d69a467a5ac76699ce232c5fbbe79afc5e95 Mon Sep 17 00:00:00 2001 From: mbertuletti Date: Fri, 5 Jan 2024 16:46:14 +0100 Subject: [PATCH] [tests] Add fp8 and smallfloat wDotp tests --- software/riscv-tests/isa/Makefile | 2 +- .../riscv-tests/isa/rv32uzvechalfinx/Makefrag | 1 + .../isa/rv32uzvechalfinx/vfcpka_h.S | 2 +- .../isa/rv32uzvechalfinx/vfdotpex_h.S | 38 ++++++++++++++++ .../isa/rv32uzvecquarterinx/Makefrag | 7 ++- .../isa/rv32uzvecquarterinx/vfcpka_b.S | 4 +- .../isa/rv32uzvecquarterinx/vfdotpex_b.S | 45 +++++++++++++++++++ .../isa/rv32uzvecquarterinx/vfmac_b.S | 3 +- .../isa/rv32uzvecquarterinx/vfmin_b.S | 8 +++- .../isa/rv32uzvecquarterinx/vfsgnj_b.S | 13 +++++- software/riscv-tests/isa/snitch_isa.mk | 8 +++- 11 files changed, 123 insertions(+), 8 deletions(-) create mode 100644 software/riscv-tests/isa/rv32uzvechalfinx/vfdotpex_h.S create mode 100644 software/riscv-tests/isa/rv32uzvecquarterinx/vfdotpex_b.S diff --git a/software/riscv-tests/isa/Makefile b/software/riscv-tests/isa/Makefile index 9c75fb7c3..06ea0aa22 100644 --- a/software/riscv-tests/isa/Makefile +++ b/software/riscv-tests/isa/Makefile @@ -128,7 +128,7 @@ $(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) -RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zvecquarterinx_zexpauxvechalfinx +RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zvecquarterinx_zexpauxvechalfinx_zexpauxvecquarterinx RISCV_ARCH := $(RISCV_ARCH)_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool $(eval $(call compile_template,rv32uzfinx,-march=$(RISCV_ARCH) -mabi=ilp32)) $(eval $(call compile_template,rv32uzhinx,-march=$(RISCV_ARCH) -mabi=ilp32)) diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag b/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag index 262c1de7d..e199c0381 100644 --- a/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag +++ b/software/riscv-tests/isa/rv32uzvechalfinx/Makefrag @@ -9,6 +9,7 @@ rv32uzvechalfinx_sc_tests = \ vfmin_h \ vfsgnj_h \ vfcpka_h \ + vfdotpex_h \ fcdotpex_h endif diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S index 60b340109..3c7f01926 100644 --- a/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfcpka_h.S @@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN # 0xFFFFBE79; // -1.618 TEST_RR_OP( 2, vfcpka.h.s, 0x3E794248, 0x4048F5C3, 0x3FCF1AA0 ); - TEST_RR_OP( 3, vfcpka.h.s, 0xBE79C248, 0xC048F5C3, 0xBFCF1AA0 ) + TEST_RR_OP( 3, vfcpka.h.s, 0xBE79C248, 0xC048F5C3, 0xBFCF1AA0 ); TEST_PASSFAIL diff --git a/software/riscv-tests/isa/rv32uzvechalfinx/vfdotpex_h.S b/software/riscv-tests/isa/rv32uzvechalfinx/vfdotpex_h.S new file mode 100644 index 000000000..9a24c2157 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvechalfinx/vfdotpex_h.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfdotpex_h.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + # 4100 2.5 + # E4D3 -1235 + # 3C00 1 + + # CHECK RS1 RS2 RD + TEST_RRR_OP( 2, vfdotpex.s.h, 0xC49A1000, 0x3C003C00, 0x4100E4D3, 0x00000000 ); + TEST_RRR_OP( 3, vfdotpex.s.h, 0xC50B8800, 0x3C003C00, 0x4100E4D3, 0xC47A0000 ); + TEST_RRR_OP( 4, vfndotpex.s.h, 0x43688000, 0x3C003C00, 0x4100E4D3, 0xC47A0000 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/Makefrag b/software/riscv-tests/isa/rv32uzvecquarterinx/Makefrag index 77145a317..1d252284f 100644 --- a/software/riscv-tests/isa/rv32uzvecquarterinx/Makefrag +++ b/software/riscv-tests/isa/rv32uzvecquarterinx/Makefrag @@ -4,7 +4,12 @@ ifeq ($(COMPILER), llvm) rv32uzvecquarterinx_sc_tests = \ - vfadd_b + vfadd_b \ + vfcpka_b \ + vfdotpex_b \ + vfmac_b \ + vfmin_b \ + vfsgnj_b endif rv32uzvecquarterinx_p_tests = $(addprefix rv32uzvecquarterinx-p-, $(rv32uzvecquarterinx_sc_tests)) diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfcpka_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfcpka_b.S index f7ea24378..712cc9249 100644 --- a/software/riscv-tests/isa/rv32uzvecquarterinx/vfcpka_b.S +++ b/software/riscv-tests/isa/rv32uzvecquarterinx/vfcpka_b.S @@ -17,7 +17,9 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - # TO DO + TEST_RR_OP( 2, vfcpkb.b.s, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, vfcpka.b.s, 0x00003E42, 0x4048F5C3, 0x3FCF1AA0 ); + #TEST_RR_OP( 4, vfcpkb.b.s, 0x3E420000, 0x4048F5C3, 0x3FCF1AA0 ); TEST_PASSFAIL diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfdotpex_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfdotpex_b.S new file mode 100644 index 000000000..3365167c6 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzvecquarterinx/vfdotpex_b.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# vfdotpex_b.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + + # 0xFFFFFF42; // 3.14 + # 0xFFFFFF3C; // 1 + # 0xFFFFFFBC; // -1 + + # CHECK RS1 RS2 RD + TEST_RRR_OP( 2, vfdotpex.h.b, 0x00000000, 0x00004242, 0x0000BC3C, 0x00000000 ); + TEST_RRR_OP( 3, vfdotpex.h.b, 0x0000C600, 0x00004242, 0x0000BCBC, 0x00000000 ); + TEST_RRR_OP( 4, vfdotpex.h.b, 0x0000C500, 0x00004242, 0x0000BCBC, 0x00003C00 ); + TEST_RRR_OP( 5, vfndotpex.h.b, 0x00004700, 0x00004242, 0x0000BCBC, 0x00003C00 ); + + TEST_RRR_OP( 6, vfdotpexa.s.b, 0x00000000, 0x00004242, 0x0000BC3C, 0x00000000 ); + TEST_RRR_OP( 7, vfdotpexa.s.b, 0xC0C00000, 0x00004242, 0x0000BCBC, 0x00000000 ); + TEST_RRR_OP( 8, vfdotpexa.s.b, 0xC0A00000, 0x00004242, 0x0000BCBC, 0x3F800000 ); + TEST_RRR_OP( 9, vfdotpexb.s.b, 0xC0A00000, 0x42420000, 0xBCBC0000, 0x3F800000 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfmac_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfmac_b.S index c18dcb1f0..df87fb174 100644 --- a/software/riscv-tests/isa/rv32uzvecquarterinx/vfmac_b.S +++ b/software/riscv-tests/isa/rv32uzvecquarterinx/vfmac_b.S @@ -17,7 +17,8 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - # TO DO + # CHECK RS1 RS2 RD + TEST_RRR_OP( 2, vfmac.b, 0x45564F45, 0x423E3442, 0x3E34563E, 0x34564234 ); TEST_PASSFAIL diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfmin_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfmin_b.S index 4cafc38e8..4c8275baa 100644 --- a/software/riscv-tests/isa/rv32uzvecquarterinx/vfmin_b.S +++ b/software/riscv-tests/isa/rv32uzvecquarterinx/vfmin_b.S @@ -17,7 +17,13 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - # TO DO + # 0xFFFFFF42; // 3.14 + # 0xFFFFFF3E; // 1.618 + # 0xFFFFFF34; // 0.250244 + # 0xFFFFFF56; // 100.123456789 + + TEST_RR_OP( 2, vfmin.b, 0x3E343442, 0x423E3456, 0x3E345642 ); + TEST_RR_OP( 3, vfmax.b, 0x423E5656, 0x423E3456, 0x3E345642 ); TEST_PASSFAIL diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfsgnj_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfsgnj_b.S index 2836377f4..46d6a4430 100644 --- a/software/riscv-tests/isa/rv32uzvecquarterinx/vfsgnj_b.S +++ b/software/riscv-tests/isa/rv32uzvecquarterinx/vfsgnj_b.S @@ -17,7 +17,18 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - # TO DO + #0xFFFFFF42; // 3.14 + #0xFFFFFFC2; // -3.14 + #0xFFFFFF3E; // 1.618 + #0xFFFFFFBE; // -1.618 + #0xFFFFFF41; // 2.39062 + #0xFFFFFFC1; // -2.39062 + #0xFFFFFF34; // 0.250244 + #0xFFFFFFB4; // -0.250244 + + TEST_RR_OP( 2, vfsgnj.b, 0xC2BEC1B4, 0x423E4134, 0xC2BEC1B4 ); + TEST_RR_OP( 3, vfsgnjn.b, 0x423E4134, 0x423E4134, 0xC2BEC1B4 ); + TEST_RR_OP( 4, vfsgnjx.b, 0xC2BEC1B4, 0x423E4134, 0xC2BEC1B4 ); TEST_PASSFAIL diff --git a/software/riscv-tests/isa/snitch_isa.mk b/software/riscv-tests/isa/snitch_isa.mk index 9629d4a87..c895da215 100644 --- a/software/riscv-tests/isa/snitch_isa.mk +++ b/software/riscv-tests/isa/snitch_isa.mk @@ -135,9 +135,15 @@ ifeq ($(zfinx_rv),1) vfmac_h \ vfmin_h \ vfsgnj_h \ + vfdotpex_h \ fcdotpex_h rv32uzvecquarterinx_snitch_sc_tests = \ - vfadd_b + vfadd_b \ + vfcpka_b \ + vfdotpex_b \ + vfmac_b \ + vfmin_b \ + vfsgnj_b rv32uzfinx_mempool_tests = $(addprefix rv32uzfinx-mempool-, $(rv32uzfinx_snitch_sc_tests)) rv32uzhinx_mempool_tests = $(addprefix rv32uzhinx-mempool-, $(rv32uzhinx_snitch_sc_tests))