From f80cac9faa59900d4892dc66afd2d2963de8cb5b Mon Sep 17 00:00:00 2001 From: mbertuletti Date: Fri, 8 Dec 2023 14:32:41 +0100 Subject: [PATCH] [tests] Add zquarterinx hardware tests --- software/Makefile | 1 + software/riscv-tests/isa/Makefile | 2 + .../riscv-tests/isa/rv32uzquarterinx/Makefrag | 15 ++++++ .../riscv-tests/isa/rv32uzquarterinx/fadd_b.S | 47 +++++++++++++++++ .../isa/rv32uzquarterinx/fmadd_b.S | 50 +++++++++++++++++++ .../riscv-tests/isa/rv32uzquarterinx/fmin_b.S | 39 +++++++++++++++ .../isa/rv32uzquarterinx/fsgnj_b.S | 46 +++++++++++++++++ software/riscv-tests/isa/snitch_isa.mk | 7 +++ 8 files changed, 207 insertions(+) create mode 100644 software/riscv-tests/isa/rv32uzquarterinx/Makefrag create mode 100644 software/riscv-tests/isa/rv32uzquarterinx/fadd_b.S create mode 100644 software/riscv-tests/isa/rv32uzquarterinx/fmadd_b.S create mode 100644 software/riscv-tests/isa/rv32uzquarterinx/fmin_b.S create mode 100644 software/riscv-tests/isa/rv32uzquarterinx/fsgnj_b.S diff --git a/software/Makefile b/software/Makefile index f83402daa..b58e81c4c 100644 --- a/software/Makefile +++ b/software/Makefile @@ -50,6 +50,7 @@ $(eval $(call rtl_mempool_tests_template,rv32um)) $(eval $(call rtl_mempool_tests_template,rv32ua)) $(eval $(call rtl_mempool_tests_template,rv32uzfinx)) $(eval $(call rtl_mempool_tests_template,rv32uzhinx)) +$(eval $(call rtl_mempool_tests_template,rv32uzquarterinx)) else $(eval $(call rtl_mempool_tests_template,rv32ui)) $(eval $(call rtl_mempool_tests_template,rv32um)) diff --git a/software/riscv-tests/isa/Makefile b/software/riscv-tests/isa/Makefile index 2939c36a8..08fceb1e5 100644 --- a/software/riscv-tests/isa/Makefile +++ b/software/riscv-tests/isa/Makefile @@ -28,6 +28,7 @@ include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfinx/Makefrag include $(src_dir)/rv32uzhinx/Makefrag +include $(src_dir)/rv32uzquarterinx/Makefrag ifneq ($(COMPILER), llvm) include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -129,6 +130,7 @@ RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zexpauxvechalfinx RISCV_ARCH := $(RISCV_ARCH)_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool $(eval $(call compile_template,rv32uzfinx,-march=$(RISCV_ARCH) -mabi=ilp32)) $(eval $(call compile_template,rv32uzhinx,-march=$(RISCV_ARCH) -mabi=ilp32)) +$(eval $(call compile_template,rv32uzquarterinx,-march=$(RISCV_ARCH) -mabi=ilp32)) $(eval $(call compile_template,rv32uxpulpimg,-march=$(RISCV_ARCH) -mabi=ilp32)) else $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32)) diff --git a/software/riscv-tests/isa/rv32uzquarterinx/Makefrag b/software/riscv-tests/isa/rv32uzquarterinx/Makefrag new file mode 100644 index 000000000..224f863be --- /dev/null +++ b/software/riscv-tests/isa/rv32uzquarterinx/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32uzquarterinx tests +#----------------------------------------------------------------------- + +ifeq ($(COMPILER), llvm) +rv32uzquarterinx_sc_tests = \ + fadd_b \ + fmadd_b \ + fmin_b \ + fsgnj_b +endif + +rv32uzquarterinx_p_tests = $(addprefix rv32uzquarterinx-p-, $(rv32uzquarterinx_sc_tests)) + +# Zquarterinx extensions are not tested on Spike diff --git a/software/riscv-tests/isa/rv32uzquarterinx/fadd_b.S b/software/riscv-tests/isa/rv32uzquarterinx/fadd_b.S new file mode 100644 index 000000000..5c6dd6e27 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzquarterinx/fadd_b.S @@ -0,0 +1,47 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd_b.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + + # 0xFFFFFF42; // 3.14 + # 0xFFFFFF3E; // 1.618 + # 0xFFFFFF34; // 0.250244 + # 0xFFFFFF56; // 100.123456789 + + TEST_RR_OP( 2, fadd.b, 0xFFFFFF44, 0xFFFFFF42, 0xFFFFFF3E ); + TEST_RR_OP( 3, fadd.b, 0xFFFFFF3F, 0xFFFFFF3E, 0xFFFFFF34 ); + TEST_RR_OP( 4, fadd.b, 0xFFFFFF56, 0xFFFFFF34, 0xFFFFFF56 ); + + TEST_RR_OP( 5, fsub.b, 0xFFFFFF3E, 0xFFFFFF42, 0xFFFFFF3E ); + TEST_RR_OP( 6, fsub.b, 0xFFFFFF3D, 0xFFFFFF3E, 0xFFFFFF34 ); + TEST_RR_OP( 7, fsub.b, 0xFFFFFFD6, 0xFFFFFF34, 0xFFFFFF56 ); + + TEST_RR_OP( 8, fmul.b, 0xFFFFFF44, 0xFFFFFF42, 0xFFFFFF3E ); + TEST_RR_OP( 9, fmul.b, 0xFFFFFF36, 0xFFFFFF3E, 0xFFFFFF34 ); + TEST_RR_OP(10, fmul.b, 0xFFFFFF4E, 0xFFFFFF34, 0xFFFFFF56 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzquarterinx/fmadd_b.S b/software/riscv-tests/isa/rv32uzquarterinx/fmadd_b.S new file mode 100644 index 000000000..6599828c0 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzquarterinx/fmadd_b.S @@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd_b.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + # 0xFFFFFF42; // 3.14 + # 0xFFFFFF3E; // 1.618 + # 0xFFFFFF34; // 0.250244 + # 0xFFFFFF56; // 100.123456789 + + TEST_RRR_PLUSD_OP( 2, fmadd.b, 0xFFFFFF45, 0xFFFFFF42, 0xFFFFFF3E, 0xFFFFFF34 ); + TEST_RRR_PLUSD_OP( 3, fmadd.b, 0xFFFFFF56, 0xFFFFFF3E, 0xFFFFFF34, 0xFFFFFF56 ); + TEST_RRR_PLUSD_OP( 4, fmadd.b, 0xFFFFFF4F, 0xFFFFFF34, 0xFFFFFF56, 0xFFFFFF42); + + #TEST_RRR_PLUSD_OP( 5, fnmadd.b, 0xFFFFFFC5, 0xFFFFFF42, 0xFFFFFF3E, 0xFFFFFF34 ); + #TEST_RRR_PLUSD_OP( 6, fnmadd.b, 0xFFFFFFD6, 0xFFFFFF3E, 0xFFFFFF34, 0xFFFFFF56 ); + #TEST_RRR_PLUSD_OP( 7, fnmadd.b, 0xFFFFFFCF, 0xFFFFFF34, 0xFFFFFF56, 0xFFFFFF42 ); + + TEST_RRR_PLUSD_OP( 8, fmsub.b, 0xFFFFFF44, 0xFFFFFF42, 0xFFFFFF3E, 0xFFFFFF34 ); + TEST_RRR_PLUSD_OP( 9, fmsub.b, 0xFFFFFFD6, 0xFFFFFF3E, 0xFFFFFF34, 0xFFFFFF56); + TEST_RRR_PLUSD_OP(10, fmsub.b, 0xFFFFFF4D, 0xFFFFFF34, 0xFFFFFF56, 0xFFFFFF42); + + TEST_RRR_PLUSD_OP(11, fnmsub.b, 0xFFFFFFC4, 0xFFFFFF42, 0xFFFFFF3E, 0xFFFFFF34 ); + TEST_RRR_PLUSD_OP(12, fnmsub.b, 0xFFFFFF56, 0xFFFFFF3E, 0xFFFFFF34, 0xFFFFFF56 ); + TEST_RRR_PLUSD_OP(13, fnmsub.b, 0xFFFFFFCD, 0xFFFFFF34, 0xFFFFFF56, 0xFFFFFF42 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzquarterinx/fmin_b.S b/software/riscv-tests/isa/rv32uzquarterinx/fmin_b.S new file mode 100644 index 000000000..be7875f63 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzquarterinx/fmin_b.S @@ -0,0 +1,39 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin_b.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + # 0xFFFFFF42; // 3.14 + # 0xFFFFFF56; // 100.123456789 + # 0xFFFFFFD6; // -100.123456789 + + TEST_RR_OP( 2, fmin.b, 0xFFFFFF42, 0xFFFFFF56, 0xFFFFFF42 ); + TEST_RR_OP( 3, fmin.b, 0xFFFFFFD6, 0xFFFFFFD6, 0xFFFFFF42 ); + + TEST_RR_OP( 8, fmax.b, 0xFFFFFF56, 0xFFFFFF56, 0xFFFFFF42 ); + TEST_RR_OP( 9, fmax.b, 0xFFFFFF42, 0xFFFFFFD6, 0xFFFFFF42 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/rv32uzquarterinx/fsgnj_b.S b/software/riscv-tests/isa/rv32uzquarterinx/fsgnj_b.S new file mode 100644 index 000000000..ac6f2fff4 --- /dev/null +++ b/software/riscv-tests/isa/rv32uzquarterinx/fsgnj_b.S @@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fsgnj_b.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + # 0xFFFFFF42; // 3.14 + # 0xFFFFFFC2; // -3.14 + # 0xFFFFFF3E; // 1.618 + # 0xFFFFFFBE; // -1.618 + + TEST_RR_OP( 2, fsgnj.b, 0xFFFFFFC2, 0xFFFFFF42, 0xFFFFFFC2 ); #3.14 -3.14 + TEST_RR_OP( 3, fsgnj.b, 0xFFFFFF3E, 0xFFFFFF3E, 0xFFFFFF42 ); #1.618 3.14 + TEST_RR_OP( 4, fsgnj.b, 0xFFFFFFBE, 0xFFFFFFBE, 0xFFFFFFC2 ); #-1.618 -3.14 + + TEST_RR_OP( 5, fsgnjn.b, 0xFFFFFF42, 0xFFFFFF42, 0xFFFFFFC2 ); + TEST_RR_OP( 6, fsgnjn.b, 0xFFFFFFBE, 0xFFFFFF3E, 0xFFFFFF42 ); + TEST_RR_OP( 7, fsgnjn.b, 0xFFFFFF3E, 0xFFFFFFBE, 0xFFFFFFC2 ); + + TEST_RR_OP( 8, fsgnjx.b, 0xFFFFFFC2, 0xFFFFFF42, 0xFFFFFFC2 ); + TEST_RR_OP( 9, fsgnjx.b, 0xFFFFFF3E, 0xFFFFFF3E, 0xFFFFFF42 ); + TEST_RR_OP(10, fsgnjx.b, 0xFFFFFF3E, 0xFFFFFFBE, 0xFFFFFFC2 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/software/riscv-tests/isa/snitch_isa.mk b/software/riscv-tests/isa/snitch_isa.mk index 3bd7cb8bb..212114de2 100644 --- a/software/riscv-tests/isa/snitch_isa.mk +++ b/software/riscv-tests/isa/snitch_isa.mk @@ -124,10 +124,17 @@ ifeq ($(zfinx_rv),1) fmadd_h \ fmin_h \ fsgnj_h + rv32uzquarterinx_snitch_sc_tests = \ + fadd_b \ + fmadd_b \ + fmin_b \ + fsgnj_b rv32uzfinx_mempool_tests = $(addprefix rv32uzfinx-mempool-, $(rv32uzfinx_snitch_sc_tests)) rv32uzhinx_mempool_tests = $(addprefix rv32uzhinx-mempool-, $(rv32uzhinx_snitch_sc_tests)) + rv32uzquarterinx_mempool_tests = $(addprefix rv32uzquarterinx-mempool-, $(rv32uzquarterinx_snitch_sc_tests)) rtl_mempool_tests += $(rv32uzfinx_mempool_tests) rtl_mempool_tests += $(rv32uzhinx_mempool_tests) + rtl_mempool_tests += $(rv32uzquarterinx_mempool_tests) endif endif