diff --git a/CHANGELOG.md b/CHANGELOG.md
index e8e986d04..19ebac70b 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Fixed
 - Fix type issue in `snitch_addr_demux`
 - Properly disable the debugging CSRs in ASIC implementations
+- Fix a bug in the  DMA's distributed midend
 
 ## 0.6.0 - 2023-01-09
 
diff --git a/hardware/deps/idma/src/midends/idma_distributed_midend.sv b/hardware/deps/idma/src/midends/idma_distributed_midend.sv
index d27cad499..88bd176cb 100644
--- a/hardware/deps/idma/src/midends/idma_distributed_midend.sv
+++ b/hardware/deps/idma/src/midends/idma_distributed_midend.sv
@@ -118,6 +118,7 @@ module idma_distributed_midend #(
     // Do not interfere with metadata per default
     tie_off_trans_complete_d = '0;
     for (int i = 0; i < NoMstPorts; i++) begin
+      tie_off_trans_complete_d[i] = tie_off_trans_complete_q[i] && meta_i[i].trans_complete;
       // Feed metadata through directly
       burst_req_o[i] = burst_req_i;
       // Feed through the address bits
@@ -133,7 +134,7 @@ module idma_distributed_midend #(
         valid_o[i] = 1'b0;
         ready[i] = 1'b1;
         // Inject trans complete
-        if (valid) begin
+        if (valid[i]) begin
           tie_off_trans_complete_d[i] = 1'b1;
         end
       end else if (($unsigned(start_addr) >= i*DmaRegionWidth)) begin
diff --git a/hardware/src/mempool_cluster.sv b/hardware/src/mempool_cluster.sv
index f4f7cf9e7..c4805752d 100644
--- a/hardware/src/mempool_cluster.sv
+++ b/hardware/src/mempool_cluster.sv
@@ -77,9 +77,9 @@ module mempool_cluster
   logic      dma_req_split_valid;
   logic      dma_req_split_ready;
   dma_meta_t dma_meta_split;
-  dma_req_t  [NumGroups-1:0] dma_req;
-  logic      [NumGroups-1:0] dma_req_valid;
-  logic      [NumGroups-1:0] dma_req_ready;
+  dma_req_t  [NumGroups-1:0] dma_req_group, dma_req_group_q;
+  logic      [NumGroups-1:0] dma_req_group_valid, dma_req_group_q_valid;
+  logic      [NumGroups-1:0] dma_req_group_ready, dma_req_group_q_ready;
   dma_meta_t [NumGroups-1:0] dma_meta, dma_meta_q;
 
   `FF(dma_meta_q, dma_meta, '0, clk_i, rst_ni);
@@ -119,12 +119,27 @@ module mempool_cluster
     .valid_i     (dma_req_split_valid),
     .ready_o     (dma_req_split_ready),
     .meta_o      (dma_meta_split     ),
-    .burst_req_o (dma_req            ),
-    .valid_o     (dma_req_valid      ),
-    .ready_i     (dma_req_ready      ),
+    .burst_req_o (dma_req_group      ),
+    .valid_o     (dma_req_group_valid),
+    .ready_i     (dma_req_group_ready),
     .meta_i      (dma_meta_q         )
   );
 
+  for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_dma_req_group_register
+    spill_register #(
+      .T(dma_req_t)
+    ) i_dma_req_group_register (
+      .clk_i  (clk_i                   ),
+      .rst_ni (rst_ni                  ),
+      .data_i (dma_req_group[g]        ),
+      .valid_i(dma_req_group_valid[g]  ),
+      .ready_o(dma_req_group_ready[g]  ),
+      .data_o (dma_req_group_q[g]      ),
+      .valid_o(dma_req_group_q_valid[g]),
+      .ready_i(dma_req_group_q_ready[g])
+    );
+  end : gen_dma_req_group_register
+
   /************
    *  Groups  *
    ************/
@@ -172,9 +187,9 @@ module mempool_cluster
       .wake_up_i               (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup]               ),
       .ro_cache_ctrl_i         (ro_cache_ctrl_q[g]                                              ),
       // DMA request
-      .dma_req_i               (dma_req[g]                                                      ),
-      .dma_req_valid_i         (dma_req_valid[g]                                                ),
-      .dma_req_ready_o         (dma_req_ready[g]                                                ),
+      .dma_req_i               (dma_req_group_q[g]                                              ),
+      .dma_req_valid_i         (dma_req_group_q_valid[g]                                        ),
+      .dma_req_ready_o         (dma_req_group_q_ready[g]                                        ),
       // DMA status
       .dma_meta_o              (dma_meta[g]                                                     ),
       // AXI interface