From 29645e22ac0f1c4eac056d616c2e19572b491894 Mon Sep 17 00:00:00 2001
From: Luca Colagrande <luca.colagrande3@gmail.com>
Date: Fri, 15 Sep 2023 10:14:51 +0200
Subject: [PATCH] sw: Add `.wide_spm` section

---
 target/sim/sw/host/runtime/host.c  | 10 ++++++++++
 target/sim/sw/host/runtime/host.ld |  9 +++++++++
 target/sim/sw/host/runtime/start.S |  1 +
 3 files changed, 20 insertions(+)

diff --git a/target/sim/sw/host/runtime/host.c b/target/sim/sw/host/runtime/host.c
index 454cf4a3d..eefe75675 100644
--- a/target/sim/sw/host/runtime/host.c
+++ b/target/sim/sw/host/runtime/host.c
@@ -90,6 +90,16 @@ void initialize_bss() {
                            bss_size);
 }
 
+void initialize_wide_spm() {
+    extern volatile uint64_t __wide_spm_start, __wide_spm_end;
+
+    size_t wide_spm_size =
+        (size_t)(&__wide_spm_end) - (size_t)(&__wide_spm_start);
+    if (wide_spm_size)
+        sys_dma_blk_memcpy(SPM_WIDE_BASE_ADDR, (uint64_t)(&__wide_spm_start),
+                           wide_spm_size);
+}
+
 void enable_fpu() {
     uint64_t mstatus;
 
diff --git a/target/sim/sw/host/runtime/host.ld b/target/sim/sw/host/runtime/host.ld
index b72e72e29..b7af9a411 100644
--- a/target/sim/sw/host/runtime/host.ld
+++ b/target/sim/sw/host/runtime/host.ld
@@ -41,6 +41,15 @@ SECTIONS
     __bss_end = . ;
   } > DRAM
 
+  .wide_spm :
+  {
+    . = ALIGN(8);
+    __wide_spm_start = . ;
+    *(.wide_spm)
+    . = ALIGN(8);
+    __wide_spm_end = . ;
+  } > DRAM
+
   __end = .;
 
   .devicebin : { *(.devicebin) } > DRAM
diff --git a/target/sim/sw/host/runtime/start.S b/target/sim/sw/host/runtime/start.S
index 7c1754dbf..19f43ce16 100644
--- a/target/sim/sw/host/runtime/start.S
+++ b/target/sim/sw/host/runtime/start.S
@@ -43,6 +43,7 @@ _start:
     la      gp, __global_pointer$
     .option pop
     call initialize_bss
+    call initialize_wide_spm
     call enable_fpu
     call main