From 45d06ab43bcec7a10a7673eadc59ec47a8124490 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Fri, 9 Feb 2024 14:57:32 +0100 Subject: [PATCH] Replace AXI interfaces with structs --- rtl/axi2mem_wrap.sv | 101 +++++---- rtl/axi2per_wrap.sv | 101 +++++---- rtl/cluster_bus_wrap.sv | 160 +++++++------ rtl/dmac_wrap.sv | 97 ++++---- rtl/per2axi_wrap.sv | 103 ++++----- rtl/pulp_cluster.sv | 482 ++++++++++++++++++++-------------------- 6 files changed, 549 insertions(+), 495 deletions(-) diff --git a/rtl/axi2mem_wrap.sv b/rtl/axi2mem_wrap.sv index d8daa1ef..1984f171 100644 --- a/rtl/axi2mem_wrap.sv +++ b/rtl/axi2mem_wrap.sv @@ -22,13 +22,16 @@ module axi2mem_wrap parameter int unsigned AXI_ADDR_WIDTH = 32, parameter int unsigned AXI_DATA_WIDTH = 64, parameter int unsigned AXI_USER_WIDTH = 6, - parameter int unsigned AXI_ID_WIDTH = 6 + parameter int unsigned AXI_ID_WIDTH = 6, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - AXI_BUS.Slave axi_slave, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input axi_req_t axi_slave_req_i, + output axi_resp_t axi_slave_resp_o, hci_core_intf.master tcdm_master[NB_DMAS-1:0], output logic busy_o ); @@ -81,54 +84,54 @@ module axi2mem_wrap .busy_o ( busy_o ), .test_en_i ( test_en_i ), - .axi_slave_aw_valid_i ( axi_slave.aw_valid ), - .axi_slave_aw_addr_i ( axi_slave.aw_addr ), - .axi_slave_aw_prot_i ( axi_slave.aw_prot ), - .axi_slave_aw_region_i ( axi_slave.aw_region ), - .axi_slave_aw_len_i ( axi_slave.aw_len ), - .axi_slave_aw_size_i ( axi_slave.aw_size ), - .axi_slave_aw_burst_i ( axi_slave.aw_burst ), - .axi_slave_aw_lock_i ( axi_slave.aw_lock ), - .axi_slave_aw_cache_i ( axi_slave.aw_cache ), - .axi_slave_aw_qos_i ( axi_slave.aw_qos ), - .axi_slave_aw_id_i ( axi_slave.aw_id ), - .axi_slave_aw_user_i ( axi_slave.aw_user ), - .axi_slave_aw_ready_o ( axi_slave.aw_ready ), + .axi_slave_aw_valid_i ( axi_slave_req_i.aw_valid ), + .axi_slave_aw_addr_i ( axi_slave_req_i.aw.addr ), + .axi_slave_aw_prot_i ( axi_slave_req_i.aw.prot ), + .axi_slave_aw_region_i ( axi_slave_req_i.aw.region ), + .axi_slave_aw_len_i ( axi_slave_req_i.aw.len ), + .axi_slave_aw_size_i ( axi_slave_req_i.aw.size ), + .axi_slave_aw_burst_i ( axi_slave_req_i.aw.burst ), + .axi_slave_aw_lock_i ( axi_slave_req_i.aw.lock ), + .axi_slave_aw_cache_i ( axi_slave_req_i.aw.cache ), + .axi_slave_aw_qos_i ( axi_slave_req_i.aw.qos ), + .axi_slave_aw_id_i ( axi_slave_req_i.aw.id ), + .axi_slave_aw_user_i ( axi_slave_req_i.aw.user ), + .axi_slave_aw_ready_o ( axi_slave_resp_o.aw_ready ), - .axi_slave_ar_valid_i ( axi_slave.ar_valid ), - .axi_slave_ar_addr_i ( axi_slave.ar_addr ), - .axi_slave_ar_prot_i ( axi_slave.ar_prot ), - .axi_slave_ar_region_i ( axi_slave.ar_region ), - .axi_slave_ar_len_i ( axi_slave.ar_len ), - .axi_slave_ar_size_i ( axi_slave.ar_size ), - .axi_slave_ar_burst_i ( axi_slave.ar_burst ), - .axi_slave_ar_lock_i ( axi_slave.ar_lock ), - .axi_slave_ar_cache_i ( axi_slave.ar_cache ), - .axi_slave_ar_qos_i ( axi_slave.ar_qos ), - .axi_slave_ar_id_i ( axi_slave.ar_id ), - .axi_slave_ar_user_i ( axi_slave.ar_user ), - .axi_slave_ar_ready_o ( axi_slave.ar_ready ), + .axi_slave_ar_valid_i ( axi_slave_req_i.ar_valid ), + .axi_slave_ar_addr_i ( axi_slave_req_i.ar.addr ), + .axi_slave_ar_prot_i ( axi_slave_req_i.ar.prot ), + .axi_slave_ar_region_i ( axi_slave_req_i.ar.region ), + .axi_slave_ar_len_i ( axi_slave_req_i.ar.len ), + .axi_slave_ar_size_i ( axi_slave_req_i.ar.size ), + .axi_slave_ar_burst_i ( axi_slave_req_i.ar.burst ), + .axi_slave_ar_lock_i ( axi_slave_req_i.ar.lock ), + .axi_slave_ar_cache_i ( axi_slave_req_i.ar.cache ), + .axi_slave_ar_qos_i ( axi_slave_req_i.ar.qos ), + .axi_slave_ar_id_i ( axi_slave_req_i.ar.id ), + .axi_slave_ar_user_i ( axi_slave_req_i.ar.user ), + .axi_slave_ar_ready_o ( axi_slave_resp_o.ar_ready ), - .axi_slave_w_valid_i ( axi_slave.w_valid ), - .axi_slave_w_data_i ( axi_slave.w_data ), - .axi_slave_w_strb_i ( axi_slave.w_strb ), - .axi_slave_w_user_i ( axi_slave.w_user ), - .axi_slave_w_last_i ( axi_slave.w_last ), - .axi_slave_w_ready_o ( axi_slave.w_ready ), + .axi_slave_w_valid_i ( axi_slave_req_i.w_valid ), + .axi_slave_w_data_i ( axi_slave_req_i.w.data ), + .axi_slave_w_strb_i ( axi_slave_req_i.w.strb ), + .axi_slave_w_user_i ( axi_slave_req_i.w.user ), + .axi_slave_w_last_i ( axi_slave_req_i.w.last ), + .axi_slave_w_ready_o ( axi_slave_resp_o.w_ready ), - .axi_slave_r_valid_o ( axi_slave.r_valid ), - .axi_slave_r_data_o ( axi_slave.r_data ), - .axi_slave_r_resp_o ( axi_slave.r_resp ), - .axi_slave_r_last_o ( axi_slave.r_last ), - .axi_slave_r_id_o ( axi_slave.r_id ), - .axi_slave_r_user_o ( axi_slave.r_user ), - .axi_slave_r_ready_i ( axi_slave.r_ready ), + .axi_slave_r_valid_o ( axi_slave_resp_o.r_valid ), + .axi_slave_r_data_o ( axi_slave_resp_o.r.data ), + .axi_slave_r_resp_o ( axi_slave_resp_o.r.resp ), + .axi_slave_r_last_o ( axi_slave_resp_o.r.last ), + .axi_slave_r_id_o ( axi_slave_resp_o.r.id ), + .axi_slave_r_user_o ( axi_slave_resp_o.r.user ), + .axi_slave_r_ready_i ( axi_slave_req_i.r_ready ), - .axi_slave_b_valid_o ( axi_slave.b_valid ), - .axi_slave_b_resp_o ( axi_slave.b_resp ), - .axi_slave_b_id_o ( axi_slave.b_id ), - .axi_slave_b_user_o ( axi_slave.b_user ), - .axi_slave_b_ready_i ( axi_slave.b_ready ) + .axi_slave_b_valid_o ( axi_slave_resp_o.b_valid ), + .axi_slave_b_resp_o ( axi_slave_resp_o.b.resp ), + .axi_slave_b_id_o ( axi_slave_resp_o.b.id ), + .axi_slave_b_user_o ( axi_slave_resp_o.b.user ), + .axi_slave_b_ready_i ( axi_slave_req_i.b_ready ) ); endmodule diff --git a/rtl/axi2per_wrap.sv b/rtl/axi2per_wrap.sv index 08cfc4a5..67dffcdc 100644 --- a/rtl/axi2per_wrap.sv +++ b/rtl/axi2per_wrap.sv @@ -25,13 +25,16 @@ module axi2per_wrap parameter int unsigned AXI_USER_WIDTH = 6, parameter int unsigned AXI_ID_WIDTH = 6, parameter int unsigned BUFFER_DEPTH = 2, - parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - AXI_BUS.Slave axi_slave, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input axi_req_t axi_slave_req_i, + output axi_resp_t axi_slave_resp_o, XBAR_TCDM_BUS.Master periph_master, output logic busy_o ); @@ -49,54 +52,54 @@ module axi2per_wrap .rst_ni ( rst_ni ), .test_en_i ( test_en_i ), - .axi_slave_aw_valid_i ( axi_slave.aw_valid ), - .axi_slave_aw_addr_i ( axi_slave.aw_addr ), - .axi_slave_aw_prot_i ( axi_slave.aw_prot ), - .axi_slave_aw_region_i ( axi_slave.aw_region ), - .axi_slave_aw_len_i ( axi_slave.aw_len ), - .axi_slave_aw_size_i ( axi_slave.aw_size ), - .axi_slave_aw_burst_i ( axi_slave.aw_burst ), - .axi_slave_aw_lock_i ( axi_slave.aw_lock ), - .axi_slave_aw_cache_i ( axi_slave.aw_cache ), - .axi_slave_aw_qos_i ( axi_slave.aw_qos ), - .axi_slave_aw_id_i ( axi_slave.aw_id ), - .axi_slave_aw_user_i ( axi_slave.aw_user ), - .axi_slave_aw_ready_o ( axi_slave.aw_ready ), + .axi_slave_aw_valid_i ( axi_slave_req_i.aw_valid ), + .axi_slave_aw_addr_i ( axi_slave_req_i.aw.addr ), + .axi_slave_aw_prot_i ( axi_slave_req_i.aw.prot ), + .axi_slave_aw_region_i ( axi_slave_req_i.aw.region ), + .axi_slave_aw_len_i ( axi_slave_req_i.aw.len ), + .axi_slave_aw_size_i ( axi_slave_req_i.aw.size ), + .axi_slave_aw_burst_i ( axi_slave_req_i.aw.burst ), + .axi_slave_aw_lock_i ( axi_slave_req_i.aw.lock ), + .axi_slave_aw_cache_i ( axi_slave_req_i.aw.cache ), + .axi_slave_aw_qos_i ( axi_slave_req_i.aw.qos ), + .axi_slave_aw_id_i ( axi_slave_req_i.aw.id ), + .axi_slave_aw_user_i ( axi_slave_req_i.aw.user ), + .axi_slave_aw_ready_o ( axi_slave_resp_o.aw_ready ), - .axi_slave_ar_valid_i ( axi_slave.ar_valid ), - .axi_slave_ar_addr_i ( axi_slave.ar_addr ), - .axi_slave_ar_prot_i ( axi_slave.ar_prot ), - .axi_slave_ar_region_i ( axi_slave.ar_region ), - .axi_slave_ar_len_i ( axi_slave.ar_len ), - .axi_slave_ar_size_i ( axi_slave.ar_size ), - .axi_slave_ar_burst_i ( axi_slave.ar_burst ), - .axi_slave_ar_lock_i ( axi_slave.ar_lock ), - .axi_slave_ar_cache_i ( axi_slave.ar_cache ), - .axi_slave_ar_qos_i ( axi_slave.ar_qos ), - .axi_slave_ar_id_i ( axi_slave.ar_id ), - .axi_slave_ar_user_i ( axi_slave.ar_user ), - .axi_slave_ar_ready_o ( axi_slave.ar_ready ), + .axi_slave_ar_valid_i ( axi_slave_req_i.ar_valid ), + .axi_slave_ar_addr_i ( axi_slave_req_i.ar.addr ), + .axi_slave_ar_prot_i ( axi_slave_req_i.ar.prot ), + .axi_slave_ar_region_i ( axi_slave_req_i.ar.region ), + .axi_slave_ar_len_i ( axi_slave_req_i.ar.len ), + .axi_slave_ar_size_i ( axi_slave_req_i.ar.size ), + .axi_slave_ar_burst_i ( axi_slave_req_i.ar.burst ), + .axi_slave_ar_lock_i ( axi_slave_req_i.ar.lock ), + .axi_slave_ar_cache_i ( axi_slave_req_i.ar.cache ), + .axi_slave_ar_qos_i ( axi_slave_req_i.ar.qos ), + .axi_slave_ar_id_i ( axi_slave_req_i.ar.id ), + .axi_slave_ar_user_i ( axi_slave_req_i.ar.user ), + .axi_slave_ar_ready_o ( axi_slave_resp_o.ar_ready ), - .axi_slave_w_valid_i ( axi_slave.w_valid ), - .axi_slave_w_data_i ( axi_slave.w_data ), - .axi_slave_w_strb_i ( axi_slave.w_strb ), - .axi_slave_w_user_i ( axi_slave.w_user ), - .axi_slave_w_last_i ( axi_slave.w_last ), - .axi_slave_w_ready_o ( axi_slave.w_ready ), + .axi_slave_w_valid_i ( axi_slave_req_i.w_valid ), + .axi_slave_w_data_i ( axi_slave_req_i.w.data ), + .axi_slave_w_strb_i ( axi_slave_req_i.w.strb ), + .axi_slave_w_user_i ( axi_slave_req_i.w.user ), + .axi_slave_w_last_i ( axi_slave_req_i.w.last ), + .axi_slave_w_ready_o ( axi_slave_resp_o.w_ready ), - .axi_slave_r_valid_o ( axi_slave.r_valid ), - .axi_slave_r_data_o ( axi_slave.r_data ), - .axi_slave_r_resp_o ( axi_slave.r_resp ), - .axi_slave_r_last_o ( axi_slave.r_last ), - .axi_slave_r_id_o ( axi_slave.r_id ), - .axi_slave_r_user_o ( axi_slave.r_user ), - .axi_slave_r_ready_i ( axi_slave.r_ready ), + .axi_slave_r_valid_o ( axi_slave_resp_o.r_valid ), + .axi_slave_r_data_o ( axi_slave_resp_o.r.data ), + .axi_slave_r_resp_o ( axi_slave_resp_o.r.resp ), + .axi_slave_r_last_o ( axi_slave_resp_o.r.last ), + .axi_slave_r_id_o ( axi_slave_resp_o.r.id ), + .axi_slave_r_user_o ( axi_slave_resp_o.r.user ), + .axi_slave_r_ready_i ( axi_slave_req_i.r_ready ), - .axi_slave_b_valid_o ( axi_slave.b_valid ), - .axi_slave_b_resp_o ( axi_slave.b_resp ), - .axi_slave_b_id_o ( axi_slave.b_id ), - .axi_slave_b_user_o ( axi_slave.b_user ), - .axi_slave_b_ready_i ( axi_slave.b_ready ), + .axi_slave_b_valid_o ( axi_slave_resp_o.b_valid ), + .axi_slave_b_resp_o ( axi_slave_resp_o.b.resp ), + .axi_slave_b_id_o ( axi_slave_resp_o.b.id ), + .axi_slave_b_user_o ( axi_slave_resp_o.b.user ), + .axi_slave_b_ready_i ( axi_slave_req_i.b_ready ), .per_master_req_o ( periph_master.req ), .per_master_add_o ( periph_master.add ), diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 9f16bbdb..11f3d816 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -33,22 +33,41 @@ module cluster_bus_wrap parameter int unsigned AXI_ID_OUT_WIDTH = 6 , parameter int unsigned AXI_USER_WIDTH = 6 , parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , - parameter int unsigned TCDM_SIZE = 0 - + parameter int unsigned TCDM_SIZE = 0, + parameter type slave_req_t = logic, + parameter type slave_resp_t = logic, + parameter type master_req_t = logic, + parameter type master_resp_t = logic, + parameter type slave_aw_chan_t = logic, + parameter type master_aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type slave_b_chan_t = logic, + parameter type master_b_chan_t = logic, + parameter type slave_ar_chan_t = logic, + parameter type master_ar_chan_t = logic, + parameter type slave_r_chan_t = logic, + parameter type master_r_chan_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - input logic [5:0] cluster_id_i, - AXI_BUS.Slave data_slave, - AXI_BUS.Slave instr_slave, - AXI_BUS.Slave dma_slave, - AXI_BUS.Slave ext_slave, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input logic [5:0] cluster_id_i, + input slave_req_t data_slave_req_i, + output slave_resp_t data_slave_resp_o, + input slave_req_t instr_slave_req_i, + output slave_resp_t instr_slave_resp_o, + input slave_req_t dma_slave_req_i, + output slave_resp_t dma_slave_resp_o, + input slave_req_t ext_slave_req_i, + output slave_resp_t ext_slave_resp_o, //INITIATOR - AXI_BUS.Master tcdm_master, - AXI_BUS.Master periph_master, - AXI_BUS.Master ext_master + output master_req_t tcdm_master_req_o, + input master_resp_t tcdm_master_resp_i, + output master_req_t periph_master_req_o, + input master_resp_t periph_master_resp_i, + output master_req_t ext_master_req_o, + input master_resp_t ext_master_resp_i ); @@ -71,30 +90,29 @@ module cluster_bus_wrap // Crossbar - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi_slaves [NB_SLAVE-1:0](); + slave_req_t [NB_SLAVE-1:0] axi_slave_reqs; + slave_resp_t [NB_SLAVE-1:0] axi_slave_resps; // assign here your axi slaves - `AXI_ASSIGN(axi_slaves[0] , data_slave ) - `AXI_ASSIGN(axi_slaves[1] , instr_slave) - `AXI_ASSIGN(axi_slaves[2] , dma_slave ) - `AXI_ASSIGN(axi_slaves[3] , ext_slave ) - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi_masters [NB_MASTER-1:0](); - + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[0], data_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(data_slave_resp_o, axi_slave_resps[0]) + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[1], instr_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(instr_slave_resp_o, axi_slave_resps[1]) + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[2], dma_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(dma_slave_resp_o, axi_slave_resps[2]) + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[3], ext_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(ext_slave_resp_o, axi_slave_resps[3]) + + master_req_t [NB_MASTER-1:0] axi_master_reqs; + master_resp_t [NB_MASTER-1:0] axi_master_resps; + // assign here your axi masters - `AXI_ASSIGN(tcdm_master , axi_masters[0]) - `AXI_ASSIGN(periph_master, axi_masters[1]) - `AXI_ASSIGN(ext_master , axi_masters[2]) + `AXI_ASSIGN_REQ_STRUCT(tcdm_master_req_o, axi_master_reqs[0]) + `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[0], tcdm_master_resp_i) + `AXI_ASSIGN_REQ_STRUCT(periph_master_req_o, axi_master_reqs[1]) + `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[1], periph_master_resp_i) + `AXI_ASSIGN_REQ_STRUCT(ext_master_req_o, axi_master_reqs[2]) + `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[2], ext_master_resp_i) // address map logic [31:0] cluster_base_addr; @@ -123,38 +141,54 @@ module cluster_bus_wrap DMA_NB_OUTSND_BURSTS : NB_CORES; - localparam xbar_cfg_t AXI_XBAR_CFG = '{ - NoSlvPorts: NB_SLAVE, - NoMstPorts: NB_MASTER, - MaxMstTrans: MAX_TXNS_PER_SLV_PORT, //The TCDM ports do not support - //outstanding transactiions anyways - MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions - //per slave port - FallThrough: 1'b0, //Use the reccomended default config - LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, - PipelineStages: 0, - AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, - AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, - UniqueIds: 1'b0, - AxiAddrWidth: AXI_ADDR_WIDTH, - AxiDataWidth: AXI_DATA_WIDTH, - NoAddrRules: N_RULES - }; - - - axi_xbar_intf #( - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .Cfg ( AXI_XBAR_CFG ), - .rule_t ( addr_map_rule_t ) + localparam xbar_cfg_t AXI_XBAR_CFG = '{ + NoSlvPorts: NB_SLAVE, + NoMstPorts: NB_MASTER, + MaxMstTrans: MAX_TXNS_PER_SLV_PORT, //The TCDM ports do not support + //outstanding transactiions anyways + MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions + //per slave port + FallThrough: 1'b0, //Use the reccomended default config + LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, + PipelineStages: 0, + AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, + AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, + UniqueIds: 1'b0, + AxiAddrWidth: AXI_ADDR_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: N_RULES + }; + + + axi_xbar #( + .Cfg ( AXI_XBAR_CFG ), + .ATOPs ( 1'b0 ), + .Connectivity ( '1 ), + .slv_aw_chan_t ( slave_aw_chan_t ), + .mst_aw_chan_t ( master_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slave_b_chan_t ), + .mst_b_chan_t ( master_b_chan_t ), + .slv_ar_chan_t ( slave_ar_chan_t ), + .mst_ar_chan_t ( master_ar_chan_t ), + .slv_r_chan_t ( slave_r_chan_t ), + .mst_r_chan_t ( master_r_chan_t ), + .slv_req_t ( slave_req_t ), + .slv_resp_t ( slave_resp_t ), + .mst_req_t ( master_req_t ), + .mst_resp_t ( master_resp_t ), + .rule_t ( addr_map_rule_t ) ) i_xbar ( .clk_i, .rst_ni, - .test_i (test_en_i), - .slv_ports (axi_slaves), - .mst_ports (axi_masters), - .addr_map_i (addr_map), - .en_default_mst_port_i ('0), // disable default master port for all slave ports - .default_mst_port_i ('0) + .test_i ( test_en_i ), + .slv_ports_req_i ( axi_slave_reqs ), + .slv_ports_resp_o ( axi_slave_resps ), + .mst_ports_req_o ( axi_master_reqs ), + .mst_ports_resp_i ( axi_master_resps ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), // disable default master port for all slave ports + .default_mst_port_i ( '0 ) ); endmodule diff --git a/rtl/dmac_wrap.sv b/rtl/dmac_wrap.sv index 3826a638..939dad36 100644 --- a/rtl/dmac_wrap.sv +++ b/rtl/dmac_wrap.sv @@ -30,7 +30,9 @@ module dmac_wrap parameter int unsigned TCDM_ADD_WIDTH = 13, parameter int unsigned DATA_WIDTH = 32, parameter int unsigned ADDR_WIDTH = 32, - parameter int unsigned BE_WIDTH = DATA_WIDTH/8 + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( input logic clk_i, @@ -42,7 +44,8 @@ module dmac_wrap XBAR_PERIPH_BUS.Slave fc_ctrl_slave, hci_core_intf.master tcdm_master[3:0], - AXI_BUS.Master ext_master, + output axi_req_t ext_master_req_o, + input axi_resp_t ext_master_resp_i, output logic term_event_cl_o, output logic term_irq_cl_o, output logic term_event_pe_o, @@ -215,54 +218,54 @@ module dmac_wrap // EXTERNAL INITIATOR //*************************************** - .axi_master_aw_valid_o ( ext_master.aw_valid ), - .axi_master_aw_addr_o ( ext_master.aw_addr ), - .axi_master_aw_prot_o ( ext_master.aw_prot ), - .axi_master_aw_region_o ( ext_master.aw_region ), - .axi_master_aw_len_o ( ext_master.aw_len ), - .axi_master_aw_size_o ( ext_master.aw_size ), - .axi_master_aw_burst_o ( ext_master.aw_burst ), - .axi_master_aw_lock_o ( ext_master.aw_lock ), - .axi_master_aw_cache_o ( ext_master.aw_cache ), - .axi_master_aw_qos_o ( ext_master.aw_qos ), - .axi_master_aw_id_o ( ext_master.aw_id[AXI_ID_WIDTH-1:0] ), - .axi_master_aw_user_o ( ext_master.aw_user ), - .axi_master_aw_ready_i ( ext_master.aw_ready ), + .axi_master_aw_valid_o ( ext_master_req_o.aw_valid ), + .axi_master_aw_addr_o ( ext_master_req_o.aw.addr ), + .axi_master_aw_prot_o ( ext_master_req_o.aw.prot ), + .axi_master_aw_region_o ( ext_master_req_o.aw.region ), + .axi_master_aw_len_o ( ext_master_req_o.aw.len ), + .axi_master_aw_size_o ( ext_master_req_o.aw.size ), + .axi_master_aw_burst_o ( ext_master_req_o.aw.burst ), + .axi_master_aw_lock_o ( ext_master_req_o.aw.lock ), + .axi_master_aw_cache_o ( ext_master_req_o.aw.cache ), + .axi_master_aw_qos_o ( ext_master_req_o.aw.qos ), + .axi_master_aw_id_o ( ext_master_req_o.aw.id[AXI_ID_WIDTH-1:0] ), + .axi_master_aw_user_o ( ext_master_req_o.aw.user ), + .axi_master_aw_ready_i ( ext_master_resp_i.aw_ready ), - .axi_master_ar_valid_o ( ext_master.ar_valid ), - .axi_master_ar_addr_o ( ext_master.ar_addr ), - .axi_master_ar_prot_o ( ext_master.ar_prot ), - .axi_master_ar_region_o ( ext_master.ar_region ), - .axi_master_ar_len_o ( ext_master.ar_len ), - .axi_master_ar_size_o ( ext_master.ar_size ), - .axi_master_ar_burst_o ( ext_master.ar_burst ), - .axi_master_ar_lock_o ( ext_master.ar_lock ), - .axi_master_ar_cache_o ( ext_master.ar_cache ), - .axi_master_ar_qos_o ( ext_master.ar_qos ), - .axi_master_ar_id_o ( ext_master.ar_id[AXI_ID_WIDTH-1:0] ), - .axi_master_ar_user_o ( ext_master.ar_user ), - .axi_master_ar_ready_i ( ext_master.ar_ready ), + .axi_master_ar_valid_o ( ext_master_req_o.ar_valid ), + .axi_master_ar_addr_o ( ext_master_req_o.ar.addr ), + .axi_master_ar_prot_o ( ext_master_req_o.ar.prot ), + .axi_master_ar_region_o ( ext_master_req_o.ar.region ), + .axi_master_ar_len_o ( ext_master_req_o.ar.len ), + .axi_master_ar_size_o ( ext_master_req_o.ar.size ), + .axi_master_ar_burst_o ( ext_master_req_o.ar.burst ), + .axi_master_ar_lock_o ( ext_master_req_o.ar.lock ), + .axi_master_ar_cache_o ( ext_master_req_o.ar.cache ), + .axi_master_ar_qos_o ( ext_master_req_o.ar.qos ), + .axi_master_ar_id_o ( ext_master_req_o.ar.id[AXI_ID_WIDTH-1:0] ), + .axi_master_ar_user_o ( ext_master_req_o.ar.user ), + .axi_master_ar_ready_i ( ext_master_resp_i.ar_ready ), - .axi_master_w_valid_o ( ext_master.w_valid ), - .axi_master_w_data_o ( ext_master.w_data ), - .axi_master_w_strb_o ( ext_master.w_strb ), - .axi_master_w_user_o ( ext_master.w_user ), - .axi_master_w_last_o ( ext_master.w_last ), - .axi_master_w_ready_i ( ext_master.w_ready ), + .axi_master_w_valid_o ( ext_master_req_o.w_valid ), + .axi_master_w_data_o ( ext_master_req_o.w.data ), + .axi_master_w_strb_o ( ext_master_req_o.w.strb ), + .axi_master_w_user_o ( ext_master_req_o.w.user ), + .axi_master_w_last_o ( ext_master_req_o.w.last ), + .axi_master_w_ready_i ( ext_master_resp_i.w_ready ), - .axi_master_r_valid_i ( ext_master.r_valid ), - .axi_master_r_data_i ( ext_master.r_data ), - .axi_master_r_resp_i ( ext_master.r_resp ), - .axi_master_r_last_i ( ext_master.r_last ), - .axi_master_r_id_i ( ext_master.r_id[AXI_ID_WIDTH-1:0] ), - .axi_master_r_user_i ( ext_master.r_user ), - .axi_master_r_ready_o ( ext_master.r_ready ), + .axi_master_r_valid_i ( ext_master_resp_i.r_valid ), + .axi_master_r_data_i ( ext_master_resp_i.r.data ), + .axi_master_r_resp_i ( ext_master_resp_i.r.resp ), + .axi_master_r_last_i ( ext_master_resp_i.r.last ), + .axi_master_r_id_i ( ext_master_resp_i.r.id[AXI_ID_WIDTH-1:0] ), + .axi_master_r_user_i ( ext_master_resp_i.r.user ), + .axi_master_r_ready_o ( ext_master_req_o.r_ready ), - .axi_master_b_valid_i ( ext_master.b_valid ), - .axi_master_b_resp_i ( ext_master.b_resp ), - .axi_master_b_id_i ( ext_master.b_id[AXI_ID_WIDTH-1:0] ), - .axi_master_b_user_i ( ext_master.b_user ), - .axi_master_b_ready_o ( ext_master.b_ready ), + .axi_master_b_valid_i ( ext_master_resp_i.b_valid ), + .axi_master_b_resp_i ( ext_master_resp_i.b.resp ), + .axi_master_b_id_i ( ext_master_resp_i.b.id[AXI_ID_WIDTH-1:0] ), + .axi_master_b_user_i ( ext_master_resp_i.b.user ), + .axi_master_b_ready_o ( ext_master_req_o.b_ready ), .term_evt_o ( {term_event_pe_o,term_event_cl_o,term_event_o} ), .term_int_o ( {term_irq_pe_o,term_irq_cl_o,term_irq_o } ), @@ -270,6 +273,6 @@ module dmac_wrap .busy_o ( busy_o ) ); - assign ext_master.aw_atop = '0; + assign ext_master_req_o.aw.atop = '0; endmodule diff --git a/rtl/per2axi_wrap.sv b/rtl/per2axi_wrap.sv index 2c6a71dc..42b9088e 100644 --- a/rtl/per2axi_wrap.sv +++ b/rtl/per2axi_wrap.sv @@ -26,14 +26,17 @@ module per2axi_wrap parameter int unsigned AXI_USER_WIDTH = 6, parameter int unsigned AXI_ID_WIDTH = 4, parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8, - parameter int unsigned ID_WIDTH = PER_ID_WIDTH // required for XBAR_PERIPH_BUS interface + parameter int unsigned ID_WIDTH = PER_ID_WIDTH, // required for XBAR_PERIPH_BUS interface + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, XBAR_PERIPH_BUS.Slave periph_slave, - AXI_BUS.Master axi_master, + output axi_req_t axi_master_req_o, + input axi_resp_t axi_master_resp_i, output logic busy_o ); @@ -63,58 +66,58 @@ module per2axi_wrap .per_slave_r_id_o ( periph_slave.r_id[PER_ID_WIDTH-1:0] ), .per_slave_r_rdata_o ( periph_slave.r_rdata ), - .axi_master_aw_valid_o ( axi_master.aw_valid ), - .axi_master_aw_addr_o ( axi_master.aw_addr ), - .axi_master_aw_prot_o ( axi_master.aw_prot ), - .axi_master_aw_region_o ( axi_master.aw_region ), - .axi_master_aw_len_o ( axi_master.aw_len ), - .axi_master_aw_size_o ( axi_master.aw_size ), - .axi_master_aw_burst_o ( axi_master.aw_burst ), - .axi_master_aw_lock_o ( axi_master.aw_lock ), - .axi_master_aw_cache_o ( axi_master.aw_cache ), - .axi_master_aw_qos_o ( axi_master.aw_qos ), - .axi_master_aw_id_o ( axi_master.aw_id[AXI_ID_WIDTH-1:0] ), - .axi_master_aw_user_o ( axi_master.aw_user ), - .axi_master_aw_ready_i ( axi_master.aw_ready ), + .axi_master_aw_valid_o ( axi_master_req_o.aw_valid ), + .axi_master_aw_addr_o ( axi_master_req_o.aw.addr ), + .axi_master_aw_prot_o ( axi_master_req_o.aw.prot ), + .axi_master_aw_region_o ( axi_master_req_o.aw.region ), + .axi_master_aw_len_o ( axi_master_req_o.aw.len ), + .axi_master_aw_size_o ( axi_master_req_o.aw.size ), + .axi_master_aw_burst_o ( axi_master_req_o.aw.burst ), + .axi_master_aw_lock_o ( axi_master_req_o.aw.lock ), + .axi_master_aw_cache_o ( axi_master_req_o.aw.cache ), + .axi_master_aw_qos_o ( axi_master_req_o.aw.qos ), + .axi_master_aw_id_o ( axi_master_req_o.aw.id[AXI_ID_WIDTH-1:0] ), + .axi_master_aw_user_o ( axi_master_req_o.aw.user ), + .axi_master_aw_ready_i ( axi_master_resp_i.aw_ready ), - .axi_master_ar_valid_o ( axi_master.ar_valid ), - .axi_master_ar_addr_o ( axi_master.ar_addr ), - .axi_master_ar_prot_o ( axi_master.ar_prot ), - .axi_master_ar_region_o ( axi_master.ar_region ), - .axi_master_ar_len_o ( axi_master.ar_len ), - .axi_master_ar_size_o ( axi_master.ar_size ), - .axi_master_ar_burst_o ( axi_master.ar_burst ), - .axi_master_ar_lock_o ( axi_master.ar_lock ), - .axi_master_ar_cache_o ( axi_master.ar_cache ), - .axi_master_ar_qos_o ( axi_master.ar_qos ), - .axi_master_ar_id_o ( axi_master.ar_id[AXI_ID_WIDTH-1:0] ), - .axi_master_ar_user_o ( axi_master.ar_user ), - .axi_master_ar_ready_i ( axi_master.ar_ready ), + .axi_master_ar_valid_o ( axi_master_req_o.ar_valid ), + .axi_master_ar_addr_o ( axi_master_req_o.ar.addr ), + .axi_master_ar_prot_o ( axi_master_req_o.ar.prot ), + .axi_master_ar_region_o ( axi_master_req_o.ar.region ), + .axi_master_ar_len_o ( axi_master_req_o.ar.len ), + .axi_master_ar_size_o ( axi_master_req_o.ar.size ), + .axi_master_ar_burst_o ( axi_master_req_o.ar.burst ), + .axi_master_ar_lock_o ( axi_master_req_o.ar.lock ), + .axi_master_ar_cache_o ( axi_master_req_o.ar.cache ), + .axi_master_ar_qos_o ( axi_master_req_o.ar.qos ), + .axi_master_ar_id_o ( axi_master_req_o.ar.id[AXI_ID_WIDTH-1:0] ), + .axi_master_ar_user_o ( axi_master_req_o.ar.user ), + .axi_master_ar_ready_i ( axi_master_resp_i.ar_ready ), - .axi_master_w_valid_o ( axi_master.w_valid ), - .axi_master_w_data_o ( axi_master.w_data ), - .axi_master_w_strb_o ( axi_master.w_strb ), - .axi_master_w_user_o ( axi_master.w_user ), - .axi_master_w_last_o ( axi_master.w_last ), - .axi_master_w_ready_i ( axi_master.w_ready ), + .axi_master_w_valid_o ( axi_master_req_o.w_valid ), + .axi_master_w_data_o ( axi_master_req_o.w.data ), + .axi_master_w_strb_o ( axi_master_req_o.w.strb ), + .axi_master_w_user_o ( axi_master_req_o.w.user ), + .axi_master_w_last_o ( axi_master_req_o.w.last ), + .axi_master_w_ready_i ( axi_master_resp_i.w_ready ), - .axi_master_r_valid_i ( axi_master.r_valid ), - .axi_master_r_data_i ( axi_master.r_data ), - .axi_master_r_resp_i ( axi_master.r_resp ), - .axi_master_r_last_i ( axi_master.r_last ), - .axi_master_r_id_i ( axi_master.r_id[AXI_ID_WIDTH-1:0] ), - .axi_master_r_user_i ( axi_master.r_user ), - .axi_master_r_ready_o ( axi_master.r_ready ), + .axi_master_r_valid_i ( axi_master_resp_i.r_valid ), + .axi_master_r_data_i ( axi_master_resp_i.r.data ), + .axi_master_r_resp_i ( axi_master_resp_i.r.resp ), + .axi_master_r_last_i ( axi_master_resp_i.r.last ), + .axi_master_r_id_i ( axi_master_resp_i.r.id[AXI_ID_WIDTH-1:0] ), + .axi_master_r_user_i ( axi_master_resp_i.r.user ), + .axi_master_r_ready_o ( axi_master_req_o.r_ready ), - .axi_master_b_valid_i ( axi_master.b_valid ), - .axi_master_b_resp_i ( axi_master.b_resp ), - .axi_master_b_id_i ( axi_master.b_id[AXI_ID_WIDTH-1:0] ), - .axi_master_b_user_i ( axi_master.b_user ), - .axi_master_b_ready_o ( axi_master.b_ready ), + .axi_master_b_valid_i ( axi_master_resp_i.b_valid ), + .axi_master_b_resp_i ( axi_master_resp_i.b.resp ), + .axi_master_b_id_i ( axi_master_resp_i.b.id[AXI_ID_WIDTH-1:0] ), + .axi_master_b_user_i ( axi_master_resp_i.b.user ), + .axi_master_b_ready_o ( axi_master_req_o.b_ready ), .busy_o ( busy_o ) ); - assign axi_master.aw_atop = '0; + assign axi_master_req_o.aw.atop = '0; endmodule diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 16bc5ebc..a2015997 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -433,78 +433,73 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; //*************************************************** /* synchronous AXI interfaces at CLUSTER/SOC interface */ //*************************************************** - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_slave_64(); + `AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_DATA_C2S_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_slave_32(); + `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_DATA_S2C_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_master(); + typedef s2c_aw_chan_t c2s_in_aw_chan_t; + typedef c2s_w_chan_t c2s_in_w_chan_t; + typedef s2c_b_chan_t c2s_in_b_chan_t; + typedef s2c_ar_chan_t c2s_in_ar_chan_t; + `AXI_TYPEDEF_R_CHAN_T(c2s_in_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_core_instr_bus(); + `AXI_TYPEDEF_REQ_T(c2s_req_t, c2s_aw_chan_t, c2s_w_chan_t, c2s_ar_chan_t) + `AXI_TYPEDEF_RESP_T(c2s_resp_t, c2s_b_chan_t, c2s_r_chan_t) + + `AXI_TYPEDEF_REQ_T(c2s_in_req_t, c2s_in_aw_chan_t, c2s_in_w_chan_t, c2s_in_ar_chan_t) + `AXI_TYPEDEF_RESP_T(c2s_in_resp_t, c2s_in_b_chan_t, c2s_in_r_chan_t) + + `AXI_TYPEDEF_REQ_T(s2c_req_t, s2c_aw_chan_t, s2c_w_chan_t, s2c_ar_chan_t) + `AXI_TYPEDEF_RESP_T(s2c_resp_t, s2c_b_chan_t, s2c_r_chan_t) + + c2s_in_req_t s_data_slave_64_req; + c2s_in_resp_t s_data_slave_64_resp; + + s2c_req_t s_data_slave_32_req; + s2c_resp_t s_data_slave_32_resp; + + c2s_req_t s_data_master_req; + c2s_resp_t s_data_master_resp; + + c2s_in_req_t s_core_instr_bus_req; + c2s_in_resp_t s_core_instr_bus_resp; + + // ***********************************************************************************************+ + // ***********************************************************************************************+ + // ***********************************************************************************************+ + // ***********************************************************************************************+ + // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - //*************************************************** /* synchronous AXI interfaces internal to the cluster */ //*************************************************** - + + // core per2axi -> ext - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_core_ext_bus(); + c2s_in_req_t s_core_ext_bus_req; + c2s_in_resp_t s_core_ext_bus_resp; // DMA -> ext - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_dma_ext_bus(); + c2s_in_req_t s_dma_ext_bus_req; + c2s_in_resp_t s_dma_ext_bus_resp; // ext -> axi2mem - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_ext_tcdm_bus(); + c2s_req_t s_ext_tcdm_bus_req; + c2s_resp_t s_ext_tcdm_bus_resp; // cluster bus -> axi2per - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_ext_mperiph_bus(); + c2s_req_t s_ext_mperiph_bus_req; + c2s_resp_t s_ext_mperiph_bus_resp; /* reset generator */ rstgen rstgen_i ( @@ -529,19 +524,39 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ) + .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), + .slave_req_t ( c2s_in_req_t ), + .slave_resp_t ( c2s_in_resp_t ), + .master_req_t ( c2s_req_t ), + .master_resp_t ( c2s_resp_t ), + .slave_aw_chan_t ( c2s_in_aw_chan_t ), + .master_aw_chan_t ( c2s_aw_chan_t ), + .w_chan_t ( c2s_w_chan_t ), + .slave_b_chan_t ( c2s_in_b_chan_t ), + .master_b_chan_t ( c2s_b_chan_t ), + .slave_ar_chan_t ( c2s_in_ar_chan_t ), + .master_ar_chan_t ( c2s_ar_chan_t ), + .slave_r_chan_t ( c2s_in_r_chan_t ), + .master_r_chan_t ( c2s_r_chan_t ) ) cluster_bus_wrap_i ( .clk_i ( clk_cluster ), .rst_ni ( s_rst_n ), .test_en_i ( test_mode_i ), .cluster_id_i ( cluster_id_i ), - .instr_slave ( s_core_instr_bus ), - .data_slave ( s_core_ext_bus ), - .dma_slave ( s_dma_ext_bus ), - .ext_slave ( s_data_slave_64 ), - .tcdm_master ( s_ext_tcdm_bus ), - .periph_master ( s_ext_mperiph_bus ), - .ext_master ( s_data_master ) + .data_slave_req_i ( s_core_ext_bus_req ), + .data_slave_resp_o ( s_core_ext_bus_resp ), + .instr_slave_req_i ( s_core_intr_bus_req ), + .instr_slave_resp_o ( s_core_instr_bus_resp ), + .dma_slave_req_i ( s_dma_ext_bus_req ), + .dma_slave_resp_o ( s_dma_ext_bus_resp ), + .ext_slave_req_i ( s_data_slave_64_req ), + .ext_slave_resp_o ( s_data_slave_64_resp ), + .tcdm_master_req_o ( s_ext_tcdm_bus_req ), + .tcdm_master_resp_i ( s_ext_tcdm_bus_resp ), + .periph_master_req_o ( s_ext_mperiph_bus_req ), + .periph_master_resp_i( s_ext_mperiph_bus_resp), + .ext_master_req_o ( s_data_master_req ), + .ext_master_resp_i ( s_data_master_resp ) ); axi2mem_wrap #( @@ -549,28 +564,34 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ) + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) ) axi2mem_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave ( s_ext_tcdm_bus ), - .tcdm_master ( s_hci_ext ), - .busy_o ( s_axi2mem_busy ) + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .axi_slave_req_i ( s_ext_tcdm_bus_req ), + .axi_slave_resp_o ( s_ext_tcdm_bus_resp ), + .tcdm_master ( s_hci_ext ), + .busy_o ( s_axi2mem_busy ) ); axi2per_wrap #( .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) ) axi2per_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave ( s_ext_mperiph_bus ), - .periph_master ( s_mperiph_bus ), - .busy_o ( s_axi2per_busy ) + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .axi_slave_req_i ( s_ext_mperiph_bus_req ), + .axi_slave_resp_o ( s_ext_mperiph_bus_resp ), + .periph_master ( s_mperiph_bus ), + .busy_o ( s_axi2per_busy ) ); per_demux_wrap #( @@ -614,14 +635,17 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) ) per2axi_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), - .axi_master ( s_core_ext_bus ), - .busy_o ( s_per2axi_busy ) + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), + .axi_master_req_o ( s_core_ext_bus_req ), + .axi_master_resp_i ( s_core_ext_bus_resp ), + .busy_o ( s_per2axi_busy ) ); @@ -685,7 +709,9 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), .DATA_WIDTH ( DATA_WIDTH ), .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ) + .BE_WIDTH ( BE_WIDTH ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) ) dmac_wrap_i ( .clk_i ( clk_cluster ), .rst_ni ( s_rst_n ), @@ -694,7 +720,8 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .cl_ctrl_slave ( s_periph_dma_bus[0]), .fc_ctrl_slave ( s_periph_dma_bus[1]), .tcdm_master ( s_hci_dma ), - .ext_master ( s_dma_ext_bus ), + .ext_master_req_o ( s_dma_ext_bus_req ), + .ext_master_resp_i ( s_dma_ext_bus_resp ), .term_event_cl_o ( s_dma_cl_event ), .term_irq_cl_o ( s_dma_cl_irq ), .term_event_pe_o ( s_dma_fc_event ), @@ -1064,66 +1091,66 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .enable_l1_l15_prefetch_i ( s_enable_l1_l15_prefetch ), // set it to 1 to use prefetch feature //AXI read address bus ------------------------------------------- - .axi_master_arid_o ( s_core_instr_bus.ar_id ), - .axi_master_araddr_o ( s_core_instr_bus.ar_addr ), - .axi_master_arlen_o ( s_core_instr_bus.ar_len ), //burst length - 1 to 16 - .axi_master_arsize_o ( s_core_instr_bus.ar_size ), //size of each transfer in burst - .axi_master_arburst_o ( s_core_instr_bus.ar_burst ), //accept only incr burst=01 - .axi_master_arlock_o ( s_core_instr_bus.ar_lock ), //only normal access supported axs_awlock=00 - .axi_master_arcache_o ( s_core_instr_bus.ar_cache ), - .axi_master_arprot_o ( s_core_instr_bus.ar_prot ), - .axi_master_arregion_o ( s_core_instr_bus.ar_region ), // - .axi_master_aruser_o ( s_core_instr_bus.ar_user ), // - .axi_master_arqos_o ( s_core_instr_bus.ar_qos ), // - .axi_master_arvalid_o ( s_core_instr_bus.ar_valid ), //master addr valid - .axi_master_arready_i ( s_core_instr_bus.ar_ready ), //slave ready to accept + .axi_master_arid_o ( s_core_instr_bus_req.ar.id ), + .axi_master_araddr_o ( s_core_instr_bus_req.ar.addr ), + .axi_master_arlen_o ( s_core_instr_bus_req.ar.len ), //burst length - 1 to 16 + .axi_master_arsize_o ( s_core_instr_bus_req.ar.size ), //size of each transfer in burst + .axi_master_arburst_o ( s_core_instr_bus_req.ar.burst ), //accept only incr burst=01 + .axi_master_arlock_o ( s_core_instr_bus_req.ar.lock ), //only normal access supported axs_awlock=00 + .axi_master_arcache_o ( s_core_instr_bus_req.ar.cache ), + .axi_master_arprot_o ( s_core_instr_bus_req.ar.prot ), + .axi_master_arregion_o ( s_core_instr_bus_req.ar.region ), // + .axi_master_aruser_o ( s_core_instr_bus_req.ar.user ), // + .axi_master_arqos_o ( s_core_instr_bus_req.ar.qos ), // + .axi_master_arvalid_o ( s_core_instr_bus_req.ar_valid ), //master addr valid + .axi_master_arready_i ( s_core_instr_bus_resp.ar_ready ), //slave ready to accept // --------------------------------------------------------------- //AXI BACKWARD read data bus ---------------------------------------------- - .axi_master_rid_i ( s_core_instr_bus.r_id ), - .axi_master_rdata_i ( s_core_instr_bus.r_data ), - .axi_master_rresp_i ( s_core_instr_bus.r_resp ), - .axi_master_rlast_i ( s_core_instr_bus.r_last ), //last transfer in burst - .axi_master_ruser_i ( s_core_instr_bus.r_user ), - .axi_master_rvalid_i ( s_core_instr_bus.r_valid ), //slave data valid - .axi_master_rready_o ( s_core_instr_bus.r_ready ), //master ready to accept + .axi_master_rid_i ( s_core_instr_bus_resp.r.id ), + .axi_master_rdata_i ( s_core_instr_bus_resp.r.data ), + .axi_master_rresp_i ( s_core_instr_bus_resp.r.resp ), + .axi_master_rlast_i ( s_core_instr_bus_resp.r.last ), //last transfer in burst + .axi_master_ruser_i ( s_core_instr_bus_resp.r.user ), + .axi_master_rvalid_i ( s_core_instr_bus_resp.r_valid ), //slave data valid + .axi_master_rready_o ( s_core_instr_bus_req.r_ready ), //master ready to accept // NOT USED ---------------------------------------------- - .axi_master_awid_o ( s_core_instr_bus.aw_id ), - .axi_master_awaddr_o ( s_core_instr_bus.aw_addr ), - .axi_master_awlen_o ( s_core_instr_bus.aw_len ), - .axi_master_awsize_o ( s_core_instr_bus.aw_size ), - .axi_master_awburst_o ( s_core_instr_bus.aw_burst ), - .axi_master_awlock_o ( s_core_instr_bus.aw_lock ), - .axi_master_awcache_o ( s_core_instr_bus.aw_cache ), - .axi_master_awprot_o ( s_core_instr_bus.aw_prot ), - .axi_master_awregion_o ( s_core_instr_bus.aw_region ), - .axi_master_awuser_o ( s_core_instr_bus.aw_user ), - .axi_master_awqos_o ( s_core_instr_bus.aw_qos ), - .axi_master_awvalid_o ( s_core_instr_bus.aw_valid ), - .axi_master_awready_i ( s_core_instr_bus.aw_ready ), + .axi_master_awid_o ( s_core_instr_bus_req.aw.id ), + .axi_master_awaddr_o ( s_core_instr_bus_req.aw.addr ), + .axi_master_awlen_o ( s_core_instr_bus_req.aw.len ), + .axi_master_awsize_o ( s_core_instr_bus_req.aw.size ), + .axi_master_awburst_o ( s_core_instr_bus_req.aw.burst ), + .axi_master_awlock_o ( s_core_instr_bus_req.aw.lock ), + .axi_master_awcache_o ( s_core_instr_bus_req.aw.cache ), + .axi_master_awprot_o ( s_core_instr_bus_req.aw.prot ), + .axi_master_awregion_o ( s_core_instr_bus_req.aw.region ), + .axi_master_awuser_o ( s_core_instr_bus_req.aw.user ), + .axi_master_awqos_o ( s_core_instr_bus_req.aw.qos ), + .axi_master_awvalid_o ( s_core_instr_bus_req.aw_valid ), + .axi_master_awready_i ( s_core_instr_bus_resp.aw_ready ), // NOT USED ---------------------------------------------- - .axi_master_wdata_o ( s_core_instr_bus.w_data ), - .axi_master_wstrb_o ( s_core_instr_bus.w_strb ), - .axi_master_wlast_o ( s_core_instr_bus.w_last ), - .axi_master_wuser_o ( s_core_instr_bus.w_user ), - .axi_master_wvalid_o ( s_core_instr_bus.w_valid ), - .axi_master_wready_i ( s_core_instr_bus.w_ready ), + .axi_master_wdata_o ( s_core_instr_bus_req.w.data ), + .axi_master_wstrb_o ( s_core_instr_bus_req.w.strb ), + .axi_master_wlast_o ( s_core_instr_bus_req.w.last ), + .axi_master_wuser_o ( s_core_instr_bus_req.w.user ), + .axi_master_wvalid_o ( s_core_instr_bus_req.w_valid ), + .axi_master_wready_i ( s_core_instr_bus_resp.w_ready ), // --------------------------------------------------------------- // NOT USED ---------------------------------------------- - .axi_master_bid_i ( s_core_instr_bus.b_id ), - .axi_master_bresp_i ( s_core_instr_bus.b_resp ), - .axi_master_buser_i ( s_core_instr_bus.b_user ), - .axi_master_bvalid_i ( s_core_instr_bus.b_valid ), - .axi_master_bready_o ( s_core_instr_bus.b_ready ), + .axi_master_bid_i ( s_core_instr_bus_resp.b.id ), + .axi_master_bresp_i ( s_core_instr_bus_resp.b.resp ), + .axi_master_buser_i ( s_core_instr_bus_resp.b.user ), + .axi_master_bvalid_i ( s_core_instr_bus_resp.b_valid ), + .axi_master_bready_o ( s_core_instr_bus_req.b_ready ), // --------------------------------------------------------------- .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ) ); - assign s_core_instr_bus.aw_atop = '0; + assign s_core_instr_bus_req.aw.atop = '0; /* TCDM banks */ tcdm_banks_wrap #( @@ -1141,118 +1168,99 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; ); /* AXI interconnect infrastructure (slices, size conversion) */ - //******************************************************** - //**************** AXI REGISTER SLICES ******************* - //******************************************************** - // CLUSTER TO SOC - - `AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_DATA_C2S_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - - `AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t) - `AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t) - - c2s_req_t src_req ; - c2s_resp_t src_resp; - - `AXI_ASSIGN_TO_REQ(src_req,s_data_master) - `AXI_ASSIGN_FROM_RESP(s_data_master,src_resp) + //******************************************************** + //**************** AXI REGISTER SLICES ******************* + //******************************************************** + // CLUSTER TO SOC axi_cdc_src #( - .aw_chan_t (c2s_aw_chan_t), - .w_chan_t (c2s_w_chan_t), - .b_chan_t (c2s_b_chan_t), - .r_chan_t (c2s_r_chan_t), - .ar_chan_t (c2s_ar_chan_t), - .axi_req_t (c2s_req_t ), - .axi_resp_t(c2s_resp_t ), + .aw_chan_t (c2s_aw_chan_t), + .w_chan_t (c2s_w_chan_t), + .b_chan_t (c2s_b_chan_t), + .r_chan_t (c2s_r_chan_t), + .ar_chan_t (c2s_ar_chan_t), + .axi_req_t (c2s_req_t ), + .axi_resp_t(c2s_resp_t ), .LogDepth ( LOG_DEPTH ) - ) axi_master_cdc_i ( - .src_rst_ni ( s_rst_n ), - .src_clk_i ( clk_cluster ), - .src_req_i ( src_req ), - .src_resp_o ( src_resp ), - .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), - .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), - .async_data_master_aw_data_o ( async_data_master_aw_data_o ), - .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), - .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), - .async_data_master_w_data_o ( async_data_master_w_data_o ), - .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), - .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), - .async_data_master_ar_data_o ( async_data_master_ar_data_o ), - .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), - .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), - .async_data_master_b_data_i ( async_data_master_b_data_i ), - .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), - .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), - .async_data_master_r_data_i ( async_data_master_r_data_i ) - ); - - // SOC TO CLUSTER - + ) axi_master_cdc_i ( + .src_rst_ni ( s_rst_n ), + .src_clk_i ( clk_cluster ), + .src_req_i ( s_data_master_req ), + .src_resp_o ( s_data_master_resp ), + .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), + .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), + .async_data_master_aw_data_o ( async_data_master_aw_data_o ), + .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), + .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), + .async_data_master_w_data_o ( async_data_master_w_data_o ), + .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), + .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), + .async_data_master_ar_data_o ( async_data_master_ar_data_o ), + .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), + .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), + .async_data_master_b_data_i ( async_data_master_b_data_i ), + .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), + .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), + .async_data_master_r_data_i ( async_data_master_r_data_i ) + ); - `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_DATA_S2C_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - - `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) - `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) + // SOC TO CLUSTER - s2c_req_t dst_req; - s2c_resp_t dst_resp; - - `AXI_ASSIGN_FROM_REQ(s_data_slave_32,dst_req) - `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_32) - axi_cdc_dst #( - .aw_chan_t (s2c_aw_chan_t), - .w_chan_t (s2c_w_chan_t ), - .b_chan_t (s2c_b_chan_t ), - .r_chan_t (s2c_r_chan_t ), - .ar_chan_t (s2c_ar_chan_t), - .axi_req_t (s2c_req_t ), - .axi_resp_t(s2c_resp_t ), - .LogDepth ( LOG_DEPTH ) - ) axi_slave_cdc_i ( - .dst_rst_ni ( s_rst_n ), - .dst_clk_i ( clk_i ), - .dst_req_o ( dst_req ), - .dst_resp_i ( dst_resp ), - .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), - .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), - .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), - .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), - .async_data_slave_w_data_i ( async_data_slave_w_data_i ), - .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), - .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), - .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), - .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), - .async_data_slave_b_data_o ( async_data_slave_b_data_o ), - .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), - .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), - .async_data_slave_r_data_o ( async_data_slave_r_data_o ) - ); - - axi_dw_converter_intf #( - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_SLV_PORT_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_MST_PORT_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_MAX_READS ( 1 ) + .aw_chan_t (s2c_aw_chan_t), + .w_chan_t (s2c_w_chan_t ), + .b_chan_t (s2c_b_chan_t ), + .r_chan_t (s2c_r_chan_t ), + .ar_chan_t (s2c_ar_chan_t), + .axi_req_t (s2c_req_t ), + .axi_resp_t(s2c_resp_t ), + .LogDepth ( LOG_DEPTH ) + ) axi_slave_cdc_i ( + .dst_rst_ni ( s_rst_n ), + .dst_clk_i ( clk_i ), + .dst_req_o ( s_data_slave_32_req ), + .dst_resp_i ( s_data_slave_32_resp ), + .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), + .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), + .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), + .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), + .async_data_slave_w_data_i ( async_data_slave_w_data_i ), + .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), + .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), + .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), + .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), + .async_data_slave_b_data_o ( async_data_slave_b_data_o ), + .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), + .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), + .async_data_slave_r_data_o ( async_data_slave_r_data_o ) + ); + + axi_dw_converter #( + .AxiMaxReads ( 1 ), + .AxiSlvPortDataWidth ( AXI_DATA_S2C_WIDTH ), + .AxiMstPortDataWidth ( AXI_DATA_C2S_WIDTH ), + .AxiIdWidth ( AXI_ID_IN_WIDTH ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .aw_chan_t ( s2c_aw_chan_t ), + .mst_w_chan_t ( c2s_w_chan_t ), + .slv_w_chan_t ( s2c_w_chan_t ), + .b_chan_t ( s2c_b_chan_t ), + .ar_chan_t ( s2c_ar_chan_t ), + .mst_r_chan_t ( c2s_in_r_chan_t ), + .slv_r_chan_t ( s2c_r_chan_t ), + .axi_mst_req_t ( s2c_req_t ), + .axi_mst_resp_t ( s2c_resp_t ), + .axi_slv_req_t ( c2s_in_req_t ), + .axi_slv_resp_t ( c2s_in_resp_t ) ) axi_dw_UPSIZE_32_64_wrap_i ( - .clk_i ( clk_i ), - .rst_ni ( s_rst_n ), - .slv ( s_data_slave_32 ), - .mst ( s_data_slave_64 ) + .clk_i ( clk_i ), + .rst_ni ( s_rst_n ), + .slv_req_i ( s_data_slave_32_req ), + .slv_resp_o( s_data_slave_32_resp ), + .mst_req_o ( s_data_slave_64_req ), + .mst_resp_i( s_data_slave_64_resp ) ); /* event synchronizers */