diff --git a/rtl/core_region.sv b/rtl/core_region.sv
index 63365ef4..eb73d2ea 100644
--- a/rtl/core_region.sv
+++ b/rtl/core_region.sv
@@ -24,6 +24,7 @@
 //`define DUMP_INSTR_FETCH
 
 module core_region
+import rapid_recovery_pkg::*;
 #(
   // CORE PARAMETERS
   parameter CORE_TYPE_CL            = 0,  // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC
@@ -89,6 +90,18 @@ module core_region
   output logic                           debug_running_o,
   output logic                           debug_halted_o,
 
+  // // Recovery Ports for RF
+  // input logic                            recover_i        ,
+  // // Write Port A
+  // input logic [5:0]                      regfile_waddr_a_i,
+  // input logic [31:0]                     regfile_wdata_a_i,
+  // input logic                            regfile_we_a_i   ,
+  // // Write Port B
+  // input logic [5:0]                      regfile_waddr_b_i,
+  // input logic [31:0]                     regfile_wdata_b_i,
+  // input logic                            regfile_we_b_i   ,
+  input rapid_recovery_pkg::rapid_recovery_t recovery_bus_i,
+
   input logic [N_EXT_PERF_COUNTERS-1:0]  ext_perf_i,
 
   output core_data_req_t                 core_data_req_o,
@@ -285,18 +298,56 @@ module core_region
         .sec_lvl_o             (                             ),
         // Debug Interface
         .debug_req_i           ( debug_req_i                 ),
-        // .debug_havereset_o     ( debug_havereset_o           ), // Useful for HMR
-        // .debug_running_o       ( debug_running_o             ), // Useful for HMR
-        // .debug_halted_o        ( debug_halted_o              ), // Useful for HMR
+        .debug_mode_o          ( debug_halted_o              ),
         // Yet other control signals
         .fetch_enable_i        ( fetch_en_i                  ),
         .core_busy_o           ( core_busy_o                 ),
         // External performance monitoring signals
-        .ext_perf_counters_i   ( ext_perf_i                  )
+        .ext_perf_counters_i   ( ext_perf_i                  ),
+        .external_perf_i       ( perf_counters_i             ),
+        // RF recovery ports
+        .recover_i         ( recovery_bus_i.rf_recovery_en            ),
+        // Write port A
+        .regfile_waddr_a_i ( recovery_bus_i.rf_recovery_wdata.waddr_a ),
+        .regfile_wdata_a_i ( recovery_bus_i.rf_recovery_wdata.wdata_a ),
+        .regfile_we_a_i    ( recovery_bus_i.rf_recovery_wdata.we_a    ),
+        // Write port B
+        .regfile_waddr_b_i ( recovery_bus_i.rf_recovery_wdata.waddr_b ),
+        .regfile_wdata_b_i ( recovery_bus_i.rf_recovery_wdata.wdata_b ),
+        .regfile_we_b_i    ( recovery_bus_i.rf_recovery_wdata.we_b    ),
+        // Outputs from RF
+        // Port A
+        .regfile_we_a_o    ( /*backup_bus_o.*/ ),
+        .regfile_waddr_a_o ( /*backup_bus_o.*/ ),
+        .regfile_wdata_a_o ( /*backup_bus_o.*/ ),
+        // Port B
+        .regfile_we_b_o    ( /*backup_bus_o.*/ ),
+        .regfile_waddr_b_o ( /*backup_bus_o.*/ ),
+        .regfile_wdata_b_o ( /*backup_bus_o.*/ ),
+        // Program Counter Backup
+        .backup_program_counter_o   ( /*backup_bus_o.*/ ),
+        .backup_branch_o            ( /*backup_bus_o.*/ ),
+        .backup_branch_addr_o       ( /*backup_bus_o.*/ ),
+        // Program Counter Recovery
+        .pc_recover_i               ( recovery_bus_i.pc_recovery_en              ),
+        .recovery_program_counter_i ( recovery_bus_i.pc_recovery.program_counter ),
+        .recovery_branch_i          ( recovery_bus_i.pc_recovery.is_branch       ),
+        .recovery_branch_addr_i     ( recovery_bus_i.pc_recovery.branch_addr     ),
+        // CSRs Backup
+        .backup_mstatus_o  ( /*backup_bus_o.*/ ),
+        .backup_mtvec_o    ( /*backup_bus_o.*/ ),
+        .backup_mscratch_o ( /*backup_bus_o.*/ ),
+        .backup_mepc_o     ( /*backup_bus_o.*/ ),
+        .backup_mcause_o   ( /*backup_bus_o.*/ ),
+        // CSRs Recovery
+        .recovery_mstatus_i  ( recovery_bus_i.csr_recovery.csr_mstatus  ),
+        .recovery_mtvec_i    ( recovery_bus_i.csr_recovery.csr_mtvec    ),
+        .recovery_mscratch_i ( recovery_bus_i.csr_recovery.csr_mscratch ),
+        .recovery_mepc_i     ( recovery_bus_i.csr_recovery.csr_mepc     ),
+        .recovery_mcause_i   ( recovery_bus_i.csr_recovery.csr_mcause   )
       );
       assign debug_havereset_o = '0;
       assign debug_running_o   = '0;
-      assign debug_halted_o    = '0;
     end else begin: IBEX_CORE
       assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally)
       // Core busy
diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv
index 751f5e13..2ddcf465 100644
--- a/rtl/pulp_cluster.sv
+++ b/rtl/pulp_cluster.sv
@@ -941,6 +941,8 @@ generate
       .core_data_rsp_i     ( core_data_rsp[i]          ),
       // .debug_resume_i   ( recovery_bus[i].debug_resume       ), // Useful for HMR, consider keeping
       //HMR Recovery Bus
+      .recovery_bus_i      ( recovery_bus[i]           ),
+      /*.debug_bus_o         ( debug_bus[i]              ),*/
       // .csr_recovery_i    ( recovery_bus[i].csr_recovery      ),
       // .pc_recovery_i     ( recovery_bus[i].pc_recovery       ),
       // .instr_lock_i      ( recovery_bus[i].instr_lock        ),