diff --git a/Bender.yml b/Bender.yml index 8f05ce6a..12353bcf 100644 --- a/Bender.yml +++ b/Bender.yml @@ -72,7 +72,6 @@ sources: - target: test files: - tb/mock_uart.sv - - tb/axi2apb_64_32.sv - tb/mock_uart_axi.sv - tb/pulp_cluster_tb.sv diff --git a/Makefile b/Makefile index bc8df231..5492c720 100644 --- a/Makefile +++ b/Makefile @@ -32,7 +32,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= e327fb9f8cb4a583d219862e81245405f22283bb +NONFREE_COMMIT ?= f069d0a234e5d33e6971d2fdd590b5df22ea6bd8 nonfree-init: git clone $(NONFREE_REMOTE) nonfree @@ -59,11 +59,13 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: - git clone https://github.com/pulp-platform/pulp-runtime.git -b lv/pulp_cluster $@ + git clone https://github.com/pulp-platform/pulp-runtime.git $@ + cd $@; git checkout 38ae6be6e28ff39f79218d333c41632a935bd584; cd .. ## Clone regression tests for bare-metal verification regression-tests: - git clone https://github.com/pulp-platform/regression_tests $@ + git clone https://github.com/pulp-platform/regression_tests.git $@ + cd $@; git checkout 7343d39bb9d1137b6eb3f2561777df546cd1e421; cd .. ######################## # Build and simulation # @@ -86,7 +88,7 @@ compile: $(library) scripts/compile.tcl $(VSIM) -c -do 'source scripts/compile.tcl; quit' build: compile - $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc + $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized -debug run: @@ -96,7 +98,6 @@ run: .PHONY: test-rt-par-bare ## Run only parallel tests on pulp-runtime test-rt-par-bare: pulp-runtime regression-tests - source env/env.sh; \ cd regression-tests && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ -o runtime-parallel.xml parallel-bare-tests.yaml @@ -105,7 +106,6 @@ test-rt-par-bare: pulp-runtime regression-tests .PHONY: test-rt-mchan ## Run mchan tests on pulp-runtime test-rt-mchan: pulp-runtime regression-tests - source env/env.sh; \ cd regression-tests && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ -o runtime-mchan.xml pulp_cluster-mchan-tests.yaml diff --git a/README.md b/README.md index da8a4387..57f97422 100644 --- a/README.md +++ b/README.md @@ -26,7 +26,7 @@ Warning: requires QuestaSim 2022.3 or newer. 1. Make sure the PULP RV32 toolchain is in your `PATH`. Please refer to [PULP RISCV GCC toolchain](https://github.com/pulp-platform/pulp-riscv-gcc) to use - a pre-built release. + a pre-built release. (At IIS, this is set up by the env script in step 4.) 2. Compile the hw: ``` @@ -45,6 +45,7 @@ Warning: requires QuestaSim 2022.3 or newer. ``` source env/env.sh ``` + (At IIS, this sets up a proper QuestaSim environment, and links the toolchain.) 5. Run the tests. Choose any test among the `parallel_bare_tests` and the `mchan_tests`, move into the related folder and do: diff --git a/env/env.sh b/env/env.sh index 80caa63b..28c3ce75 100644 --- a/env/env.sh +++ b/env/env.sh @@ -16,6 +16,7 @@ if test -f /etc/iis.version; then export VSIM="$QUESTA vsim" export QUESTA_HOME=/usr/pack/${QUESTA}/questasim export QUESTASIM_HOME=/usr/pack/${QUESTA}/questasim + export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 fi source "$ROOTD/pulp-runtime/configs/pulp_cluster.sh" diff --git a/rtl/axi2mem_wrap.sv b/rtl/axi2mem_wrap.sv index fe0bcf11..1984f171 100644 --- a/rtl/axi2mem_wrap.sv +++ b/rtl/axi2mem_wrap.sv @@ -18,17 +18,20 @@ module axi2mem_wrap #( - parameter NB_DMAS = 4, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_WIDTH = 64, - parameter AXI_USER_WIDTH = 6, - parameter AXI_ID_WIDTH = 6 + parameter int unsigned NB_DMAS = 4, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 6, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - AXI_BUS.Slave axi_slave, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input axi_req_t axi_slave_req_i, + output axi_resp_t axi_slave_resp_o, hci_core_intf.master tcdm_master[NB_DMAS-1:0], output logic busy_o ); @@ -81,54 +84,54 @@ module axi2mem_wrap .busy_o ( busy_o ), .test_en_i ( test_en_i ), - .axi_slave_aw_valid_i ( axi_slave.aw_valid ), - .axi_slave_aw_addr_i ( axi_slave.aw_addr ), - .axi_slave_aw_prot_i ( axi_slave.aw_prot ), - .axi_slave_aw_region_i ( axi_slave.aw_region ), - .axi_slave_aw_len_i ( axi_slave.aw_len ), - .axi_slave_aw_size_i ( axi_slave.aw_size ), - .axi_slave_aw_burst_i ( axi_slave.aw_burst ), - .axi_slave_aw_lock_i ( axi_slave.aw_lock ), - .axi_slave_aw_cache_i ( axi_slave.aw_cache ), - .axi_slave_aw_qos_i ( axi_slave.aw_qos ), - .axi_slave_aw_id_i ( axi_slave.aw_id ), - .axi_slave_aw_user_i ( axi_slave.aw_user ), - .axi_slave_aw_ready_o ( axi_slave.aw_ready ), + .axi_slave_aw_valid_i ( axi_slave_req_i.aw_valid ), + .axi_slave_aw_addr_i ( axi_slave_req_i.aw.addr ), + .axi_slave_aw_prot_i ( axi_slave_req_i.aw.prot ), + .axi_slave_aw_region_i ( axi_slave_req_i.aw.region ), + .axi_slave_aw_len_i ( axi_slave_req_i.aw.len ), + .axi_slave_aw_size_i ( axi_slave_req_i.aw.size ), + .axi_slave_aw_burst_i ( axi_slave_req_i.aw.burst ), + .axi_slave_aw_lock_i ( axi_slave_req_i.aw.lock ), + .axi_slave_aw_cache_i ( axi_slave_req_i.aw.cache ), + .axi_slave_aw_qos_i ( axi_slave_req_i.aw.qos ), + .axi_slave_aw_id_i ( axi_slave_req_i.aw.id ), + .axi_slave_aw_user_i ( axi_slave_req_i.aw.user ), + .axi_slave_aw_ready_o ( axi_slave_resp_o.aw_ready ), - .axi_slave_ar_valid_i ( axi_slave.ar_valid ), - .axi_slave_ar_addr_i ( axi_slave.ar_addr ), - .axi_slave_ar_prot_i ( axi_slave.ar_prot ), - .axi_slave_ar_region_i ( axi_slave.ar_region ), - .axi_slave_ar_len_i ( axi_slave.ar_len ), - .axi_slave_ar_size_i ( axi_slave.ar_size ), - .axi_slave_ar_burst_i ( axi_slave.ar_burst ), - .axi_slave_ar_lock_i ( axi_slave.ar_lock ), - .axi_slave_ar_cache_i ( axi_slave.ar_cache ), - .axi_slave_ar_qos_i ( axi_slave.ar_qos ), - .axi_slave_ar_id_i ( axi_slave.ar_id ), - .axi_slave_ar_user_i ( axi_slave.ar_user ), - .axi_slave_ar_ready_o ( axi_slave.ar_ready ), + .axi_slave_ar_valid_i ( axi_slave_req_i.ar_valid ), + .axi_slave_ar_addr_i ( axi_slave_req_i.ar.addr ), + .axi_slave_ar_prot_i ( axi_slave_req_i.ar.prot ), + .axi_slave_ar_region_i ( axi_slave_req_i.ar.region ), + .axi_slave_ar_len_i ( axi_slave_req_i.ar.len ), + .axi_slave_ar_size_i ( axi_slave_req_i.ar.size ), + .axi_slave_ar_burst_i ( axi_slave_req_i.ar.burst ), + .axi_slave_ar_lock_i ( axi_slave_req_i.ar.lock ), + .axi_slave_ar_cache_i ( axi_slave_req_i.ar.cache ), + .axi_slave_ar_qos_i ( axi_slave_req_i.ar.qos ), + .axi_slave_ar_id_i ( axi_slave_req_i.ar.id ), + .axi_slave_ar_user_i ( axi_slave_req_i.ar.user ), + .axi_slave_ar_ready_o ( axi_slave_resp_o.ar_ready ), - .axi_slave_w_valid_i ( axi_slave.w_valid ), - .axi_slave_w_data_i ( axi_slave.w_data ), - .axi_slave_w_strb_i ( axi_slave.w_strb ), - .axi_slave_w_user_i ( axi_slave.w_user ), - .axi_slave_w_last_i ( axi_slave.w_last ), - .axi_slave_w_ready_o ( axi_slave.w_ready ), + .axi_slave_w_valid_i ( axi_slave_req_i.w_valid ), + .axi_slave_w_data_i ( axi_slave_req_i.w.data ), + .axi_slave_w_strb_i ( axi_slave_req_i.w.strb ), + .axi_slave_w_user_i ( axi_slave_req_i.w.user ), + .axi_slave_w_last_i ( axi_slave_req_i.w.last ), + .axi_slave_w_ready_o ( axi_slave_resp_o.w_ready ), - .axi_slave_r_valid_o ( axi_slave.r_valid ), - .axi_slave_r_data_o ( axi_slave.r_data ), - .axi_slave_r_resp_o ( axi_slave.r_resp ), - .axi_slave_r_last_o ( axi_slave.r_last ), - .axi_slave_r_id_o ( axi_slave.r_id ), - .axi_slave_r_user_o ( axi_slave.r_user ), - .axi_slave_r_ready_i ( axi_slave.r_ready ), + .axi_slave_r_valid_o ( axi_slave_resp_o.r_valid ), + .axi_slave_r_data_o ( axi_slave_resp_o.r.data ), + .axi_slave_r_resp_o ( axi_slave_resp_o.r.resp ), + .axi_slave_r_last_o ( axi_slave_resp_o.r.last ), + .axi_slave_r_id_o ( axi_slave_resp_o.r.id ), + .axi_slave_r_user_o ( axi_slave_resp_o.r.user ), + .axi_slave_r_ready_i ( axi_slave_req_i.r_ready ), - .axi_slave_b_valid_o ( axi_slave.b_valid ), - .axi_slave_b_resp_o ( axi_slave.b_resp ), - .axi_slave_b_id_o ( axi_slave.b_id ), - .axi_slave_b_user_o ( axi_slave.b_user ), - .axi_slave_b_ready_i ( axi_slave.b_ready ) + .axi_slave_b_valid_o ( axi_slave_resp_o.b_valid ), + .axi_slave_b_resp_o ( axi_slave_resp_o.b.resp ), + .axi_slave_b_id_o ( axi_slave_resp_o.b.id ), + .axi_slave_b_user_o ( axi_slave_resp_o.b.user ), + .axi_slave_b_ready_i ( axi_slave_req_i.b_ready ) ); endmodule diff --git a/rtl/axi2per_wrap.sv b/rtl/axi2per_wrap.sv index b20b4d5c..67dffcdc 100644 --- a/rtl/axi2per_wrap.sv +++ b/rtl/axi2per_wrap.sv @@ -18,20 +18,23 @@ module axi2per_wrap #( - parameter PER_ADDR_WIDTH = 32, - parameter PER_ID_WIDTH = 5, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_WIDTH = 64, - parameter AXI_USER_WIDTH = 6, - parameter AXI_ID_WIDTH = 6, - parameter BUFFER_DEPTH = 2, - parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8 + parameter int unsigned PER_ADDR_WIDTH = 32, + parameter int unsigned PER_ID_WIDTH = 5, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 6, + parameter int unsigned BUFFER_DEPTH = 2, + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - AXI_BUS.Slave axi_slave, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input axi_req_t axi_slave_req_i, + output axi_resp_t axi_slave_resp_o, XBAR_TCDM_BUS.Master periph_master, output logic busy_o ); @@ -49,54 +52,54 @@ module axi2per_wrap .rst_ni ( rst_ni ), .test_en_i ( test_en_i ), - .axi_slave_aw_valid_i ( axi_slave.aw_valid ), - .axi_slave_aw_addr_i ( axi_slave.aw_addr ), - .axi_slave_aw_prot_i ( axi_slave.aw_prot ), - .axi_slave_aw_region_i ( axi_slave.aw_region ), - .axi_slave_aw_len_i ( axi_slave.aw_len ), - .axi_slave_aw_size_i ( axi_slave.aw_size ), - .axi_slave_aw_burst_i ( axi_slave.aw_burst ), - .axi_slave_aw_lock_i ( axi_slave.aw_lock ), - .axi_slave_aw_cache_i ( axi_slave.aw_cache ), - .axi_slave_aw_qos_i ( axi_slave.aw_qos ), - .axi_slave_aw_id_i ( axi_slave.aw_id ), - .axi_slave_aw_user_i ( axi_slave.aw_user ), - .axi_slave_aw_ready_o ( axi_slave.aw_ready ), + .axi_slave_aw_valid_i ( axi_slave_req_i.aw_valid ), + .axi_slave_aw_addr_i ( axi_slave_req_i.aw.addr ), + .axi_slave_aw_prot_i ( axi_slave_req_i.aw.prot ), + .axi_slave_aw_region_i ( axi_slave_req_i.aw.region ), + .axi_slave_aw_len_i ( axi_slave_req_i.aw.len ), + .axi_slave_aw_size_i ( axi_slave_req_i.aw.size ), + .axi_slave_aw_burst_i ( axi_slave_req_i.aw.burst ), + .axi_slave_aw_lock_i ( axi_slave_req_i.aw.lock ), + .axi_slave_aw_cache_i ( axi_slave_req_i.aw.cache ), + .axi_slave_aw_qos_i ( axi_slave_req_i.aw.qos ), + .axi_slave_aw_id_i ( axi_slave_req_i.aw.id ), + .axi_slave_aw_user_i ( axi_slave_req_i.aw.user ), + .axi_slave_aw_ready_o ( axi_slave_resp_o.aw_ready ), - .axi_slave_ar_valid_i ( axi_slave.ar_valid ), - .axi_slave_ar_addr_i ( axi_slave.ar_addr ), - .axi_slave_ar_prot_i ( axi_slave.ar_prot ), - .axi_slave_ar_region_i ( axi_slave.ar_region ), - .axi_slave_ar_len_i ( axi_slave.ar_len ), - .axi_slave_ar_size_i ( axi_slave.ar_size ), - .axi_slave_ar_burst_i ( axi_slave.ar_burst ), - .axi_slave_ar_lock_i ( axi_slave.ar_lock ), - .axi_slave_ar_cache_i ( axi_slave.ar_cache ), - .axi_slave_ar_qos_i ( axi_slave.ar_qos ), - .axi_slave_ar_id_i ( axi_slave.ar_id ), - .axi_slave_ar_user_i ( axi_slave.ar_user ), - .axi_slave_ar_ready_o ( axi_slave.ar_ready ), + .axi_slave_ar_valid_i ( axi_slave_req_i.ar_valid ), + .axi_slave_ar_addr_i ( axi_slave_req_i.ar.addr ), + .axi_slave_ar_prot_i ( axi_slave_req_i.ar.prot ), + .axi_slave_ar_region_i ( axi_slave_req_i.ar.region ), + .axi_slave_ar_len_i ( axi_slave_req_i.ar.len ), + .axi_slave_ar_size_i ( axi_slave_req_i.ar.size ), + .axi_slave_ar_burst_i ( axi_slave_req_i.ar.burst ), + .axi_slave_ar_lock_i ( axi_slave_req_i.ar.lock ), + .axi_slave_ar_cache_i ( axi_slave_req_i.ar.cache ), + .axi_slave_ar_qos_i ( axi_slave_req_i.ar.qos ), + .axi_slave_ar_id_i ( axi_slave_req_i.ar.id ), + .axi_slave_ar_user_i ( axi_slave_req_i.ar.user ), + .axi_slave_ar_ready_o ( axi_slave_resp_o.ar_ready ), - .axi_slave_w_valid_i ( axi_slave.w_valid ), - .axi_slave_w_data_i ( axi_slave.w_data ), - .axi_slave_w_strb_i ( axi_slave.w_strb ), - .axi_slave_w_user_i ( axi_slave.w_user ), - .axi_slave_w_last_i ( axi_slave.w_last ), - .axi_slave_w_ready_o ( axi_slave.w_ready ), + .axi_slave_w_valid_i ( axi_slave_req_i.w_valid ), + .axi_slave_w_data_i ( axi_slave_req_i.w.data ), + .axi_slave_w_strb_i ( axi_slave_req_i.w.strb ), + .axi_slave_w_user_i ( axi_slave_req_i.w.user ), + .axi_slave_w_last_i ( axi_slave_req_i.w.last ), + .axi_slave_w_ready_o ( axi_slave_resp_o.w_ready ), - .axi_slave_r_valid_o ( axi_slave.r_valid ), - .axi_slave_r_data_o ( axi_slave.r_data ), - .axi_slave_r_resp_o ( axi_slave.r_resp ), - .axi_slave_r_last_o ( axi_slave.r_last ), - .axi_slave_r_id_o ( axi_slave.r_id ), - .axi_slave_r_user_o ( axi_slave.r_user ), - .axi_slave_r_ready_i ( axi_slave.r_ready ), + .axi_slave_r_valid_o ( axi_slave_resp_o.r_valid ), + .axi_slave_r_data_o ( axi_slave_resp_o.r.data ), + .axi_slave_r_resp_o ( axi_slave_resp_o.r.resp ), + .axi_slave_r_last_o ( axi_slave_resp_o.r.last ), + .axi_slave_r_id_o ( axi_slave_resp_o.r.id ), + .axi_slave_r_user_o ( axi_slave_resp_o.r.user ), + .axi_slave_r_ready_i ( axi_slave_req_i.r_ready ), - .axi_slave_b_valid_o ( axi_slave.b_valid ), - .axi_slave_b_resp_o ( axi_slave.b_resp ), - .axi_slave_b_id_o ( axi_slave.b_id ), - .axi_slave_b_user_o ( axi_slave.b_user ), - .axi_slave_b_ready_i ( axi_slave.b_ready ), + .axi_slave_b_valid_o ( axi_slave_resp_o.b_valid ), + .axi_slave_b_resp_o ( axi_slave_resp_o.b.resp ), + .axi_slave_b_id_o ( axi_slave_resp_o.b.id ), + .axi_slave_b_user_o ( axi_slave_resp_o.b.user ), + .axi_slave_b_ready_i ( axi_slave_req_i.b_ready ), .per_master_req_o ( periph_master.req ), .per_master_add_o ( periph_master.add ), diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 3cf9895d..11f3d816 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -26,29 +26,48 @@ module cluster_bus_wrap import axi_pkg::xbar_cfg_t; import pulp_cluster_package::addr_map_rule_t; #( - parameter NB_CORES = 4 , - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_WIDTH = 64, - parameter AXI_ID_IN_WIDTH = 4 , - parameter AXI_ID_OUT_WIDTH = 6 , - parameter AXI_USER_WIDTH = 6 , - parameter DMA_NB_OUTSND_BURSTS = 8 , - parameter TCDM_SIZE = 0 - + parameter int unsigned NB_CORES = 4 , + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_ID_IN_WIDTH = 4 , + parameter int unsigned AXI_ID_OUT_WIDTH = 6 , + parameter int unsigned AXI_USER_WIDTH = 6 , + parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , + parameter int unsigned TCDM_SIZE = 0, + parameter type slave_req_t = logic, + parameter type slave_resp_t = logic, + parameter type master_req_t = logic, + parameter type master_resp_t = logic, + parameter type slave_aw_chan_t = logic, + parameter type master_aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type slave_b_chan_t = logic, + parameter type master_b_chan_t = logic, + parameter type slave_ar_chan_t = logic, + parameter type master_ar_chan_t = logic, + parameter type slave_r_chan_t = logic, + parameter type master_r_chan_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - input logic [5:0] cluster_id_i, - AXI_BUS.Slave data_slave, - AXI_BUS.Slave instr_slave, - AXI_BUS.Slave dma_slave, - AXI_BUS.Slave ext_slave, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + input logic [5:0] cluster_id_i, + input slave_req_t data_slave_req_i, + output slave_resp_t data_slave_resp_o, + input slave_req_t instr_slave_req_i, + output slave_resp_t instr_slave_resp_o, + input slave_req_t dma_slave_req_i, + output slave_resp_t dma_slave_resp_o, + input slave_req_t ext_slave_req_i, + output slave_resp_t ext_slave_resp_o, //INITIATOR - AXI_BUS.Master tcdm_master, - AXI_BUS.Master periph_master, - AXI_BUS.Master ext_master + output master_req_t tcdm_master_req_o, + input master_resp_t tcdm_master_resp_i, + output master_req_t periph_master_req_o, + input master_resp_t periph_master_resp_i, + output master_req_t ext_master_req_o, + input master_resp_t ext_master_resp_i ); @@ -71,30 +90,29 @@ module cluster_bus_wrap // Crossbar - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi_slaves [NB_SLAVE-1:0](); + slave_req_t [NB_SLAVE-1:0] axi_slave_reqs; + slave_resp_t [NB_SLAVE-1:0] axi_slave_resps; // assign here your axi slaves - `AXI_ASSIGN(axi_slaves[0] , data_slave ) - `AXI_ASSIGN(axi_slaves[1] , instr_slave) - `AXI_ASSIGN(axi_slaves[2] , dma_slave ) - `AXI_ASSIGN(axi_slaves[3] , ext_slave ) - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi_masters [NB_MASTER-1:0](); - + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[0], data_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(data_slave_resp_o, axi_slave_resps[0]) + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[1], instr_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(instr_slave_resp_o, axi_slave_resps[1]) + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[2], dma_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(dma_slave_resp_o, axi_slave_resps[2]) + `AXI_ASSIGN_REQ_STRUCT(axi_slave_reqs[3], ext_slave_req_i) + `AXI_ASSIGN_RESP_STRUCT(ext_slave_resp_o, axi_slave_resps[3]) + + master_req_t [NB_MASTER-1:0] axi_master_reqs; + master_resp_t [NB_MASTER-1:0] axi_master_resps; + // assign here your axi masters - `AXI_ASSIGN(tcdm_master , axi_masters[0]) - `AXI_ASSIGN(periph_master, axi_masters[1]) - `AXI_ASSIGN(ext_master , axi_masters[2]) + `AXI_ASSIGN_REQ_STRUCT(tcdm_master_req_o, axi_master_reqs[0]) + `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[0], tcdm_master_resp_i) + `AXI_ASSIGN_REQ_STRUCT(periph_master_req_o, axi_master_reqs[1]) + `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[1], periph_master_resp_i) + `AXI_ASSIGN_REQ_STRUCT(ext_master_req_o, axi_master_reqs[2]) + `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[2], ext_master_resp_i) // address map logic [31:0] cluster_base_addr; @@ -123,38 +141,54 @@ module cluster_bus_wrap DMA_NB_OUTSND_BURSTS : NB_CORES; - localparam xbar_cfg_t AXI_XBAR_CFG = '{ - NoSlvPorts: NB_SLAVE, - NoMstPorts: NB_MASTER, - MaxMstTrans: MAX_TXNS_PER_SLV_PORT, //The TCDM ports do not support - //outstanding transactiions anyways - MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions - //per slave port - FallThrough: 1'b0, //Use the reccomended default config - LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, - PipelineStages: 0, - AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, - AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, - UniqueIds: 1'b0, - AxiAddrWidth: AXI_ADDR_WIDTH, - AxiDataWidth: AXI_DATA_WIDTH, - NoAddrRules: N_RULES - }; - - - axi_xbar_intf #( - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .Cfg ( AXI_XBAR_CFG ), - .rule_t ( addr_map_rule_t ) + localparam xbar_cfg_t AXI_XBAR_CFG = '{ + NoSlvPorts: NB_SLAVE, + NoMstPorts: NB_MASTER, + MaxMstTrans: MAX_TXNS_PER_SLV_PORT, //The TCDM ports do not support + //outstanding transactiions anyways + MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions + //per slave port + FallThrough: 1'b0, //Use the reccomended default config + LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, + PipelineStages: 0, + AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, + AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, + UniqueIds: 1'b0, + AxiAddrWidth: AXI_ADDR_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: N_RULES + }; + + + axi_xbar #( + .Cfg ( AXI_XBAR_CFG ), + .ATOPs ( 1'b0 ), + .Connectivity ( '1 ), + .slv_aw_chan_t ( slave_aw_chan_t ), + .mst_aw_chan_t ( master_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slave_b_chan_t ), + .mst_b_chan_t ( master_b_chan_t ), + .slv_ar_chan_t ( slave_ar_chan_t ), + .mst_ar_chan_t ( master_ar_chan_t ), + .slv_r_chan_t ( slave_r_chan_t ), + .mst_r_chan_t ( master_r_chan_t ), + .slv_req_t ( slave_req_t ), + .slv_resp_t ( slave_resp_t ), + .mst_req_t ( master_req_t ), + .mst_resp_t ( master_resp_t ), + .rule_t ( addr_map_rule_t ) ) i_xbar ( .clk_i, .rst_ni, - .test_i (test_en_i), - .slv_ports (axi_slaves), - .mst_ports (axi_masters), - .addr_map_i (addr_map), - .en_default_mst_port_i ('0), // disable default master port for all slave ports - .default_mst_port_i ('0) + .test_i ( test_en_i ), + .slv_ports_req_i ( axi_slave_reqs ), + .slv_ports_resp_o ( axi_slave_resps ), + .mst_ports_req_o ( axi_master_reqs ), + .mst_ports_resp_i ( axi_master_resps ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), // disable default master port for all slave ports + .default_mst_port_i ( '0 ) ); endmodule diff --git a/rtl/cluster_clock_gate.sv b/rtl/cluster_clock_gate.sv index c519d9f0..37cc7468 100644 --- a/rtl/cluster_clock_gate.sv +++ b/rtl/cluster_clock_gate.sv @@ -18,7 +18,7 @@ module cluster_clock_gate #( - parameter NB_CORES = 4 + parameter int unsigned NB_CORES = 4 ) ( input logic clk_i, input logic rstn_i, diff --git a/rtl/cluster_event_map.sv b/rtl/cluster_event_map.sv index 758f26e5..8a5c6ae1 100644 --- a/rtl/cluster_event_map.sv +++ b/rtl/cluster_event_map.sv @@ -15,7 +15,7 @@ module cluster_event_map #( - parameter NB_CORES = 4 + parameter int unsigned NB_CORES = 4 ) ( // events generated inside event unit diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 1e32a79d..d8921b39 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -20,27 +20,27 @@ import hci_package::*; module cluster_interconnect_wrap #( - parameter NB_CORES = 8, - parameter HWPE_PRESENT = 1, - parameter NB_HWPE_PORTS = 4, - parameter NB_DMAS = 4, - parameter NB_MPERIPHS = 1, - parameter NB_TCDM_BANKS = 16, - parameter NB_SPERIPHS = 8, //differ - - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 32, - parameter BE_WIDTH = DATA_WIDTH/8, + parameter int unsigned NB_CORES = 8, + parameter int unsigned HWPE_PRESENT = 1, + parameter int unsigned NB_HWPE_PORTS = 4, + parameter int unsigned NB_DMAS = 4, + parameter int unsigned NB_MPERIPHS = 1, + parameter int unsigned NB_TCDM_BANKS = 16, + parameter int unsigned NB_SPERIPHS = 8, //differ + + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, //TCDM PARAMETERS - parameter TEST_SET_BIT = 20, - parameter ADDR_MEM_WIDTH = 11, - parameter LOG_CLUSTER = 5, - parameter PE_ROUTING_LSB = 16, - parameter PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ - parameter CLUSTER_ALIAS_BASE = 12'h000, - - parameter USE_HETEROGENEOUS_INTERCONNECT = 1 + parameter int unsigned TEST_SET_BIT = 20, + parameter int unsigned ADDR_MEM_WIDTH = 11, + parameter int unsigned LOG_CLUSTER = 5, + parameter int unsigned PE_ROUTING_LSB = 16, + parameter int unsigned PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ + parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, + + parameter bit USE_HETEROGENEOUS_INTERCONNECT = 1 ) ( input logic clk_i, diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 782f37d3..81ee3ffd 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -22,17 +22,17 @@ import pulp_cluster_package::*; module cluster_peripherals #( - parameter NB_CORES = 8, - parameter NB_MPERIPHS = 1, - parameter NB_CACHE_BANKS = 4, - parameter NB_SPERIPHS = 8, - parameter NB_TCDM_BANKS = 8, - parameter ROM_BOOT_ADDR = 32'h1A000000, - parameter BOOT_ADDR = 32'h1C000000, - parameter EVNT_WIDTH = 8, - parameter FEATURE_DEMUX_MAPPED = 1, - parameter int unsigned NB_L1_CUTS = 16, - parameter int unsigned RW_MARGIN_WIDTH = 4 + parameter int unsigned NB_CORES = 8, + parameter int unsigned NB_MPERIPHS = 1, + parameter int unsigned NB_CACHE_BANKS = 4, + parameter int unsigned NB_SPERIPHS = 8, + parameter int unsigned NB_TCDM_BANKS = 8, + parameter bit [31:0] ROM_BOOT_ADDR = 32'h1A000000, + parameter bit [31:0] BOOT_ADDR = 32'h1C000000, + parameter int unsigned EVNT_WIDTH = 8, + parameter int unsigned FEATURE_DEMUX_MAPPED = 1, + parameter int unsigned NB_L1_CUTS = 16, + parameter int unsigned RW_MARGIN_WIDTH = 4 ) ( input logic clk_i, diff --git a/rtl/cluster_timer_wrap.sv b/rtl/cluster_timer_wrap.sv index a0ba706b..09b2e320 100644 --- a/rtl/cluster_timer_wrap.sv +++ b/rtl/cluster_timer_wrap.sv @@ -18,7 +18,7 @@ module cluster_timer_wrap #( - parameter ID_WIDTH = 2 + parameter int unsigned ID_WIDTH = 2 ) ( input logic clk_i, diff --git a/rtl/core_demux.sv b/rtl/core_demux.sv index cec08d0a..6b575732 100644 --- a/rtl/core_demux.sv +++ b/rtl/core_demux.sv @@ -19,10 +19,10 @@ module core_demux #( - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32, - parameter BYTE_ENABLE_BIT = DATA_WIDTH/8, - parameter CLUSTER_ALIAS_BASE = 12'h000 + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned BYTE_ENABLE_BIT = DATA_WIDTH/8, + parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000 ) ( input logic clk, diff --git a/rtl/core_region.sv b/rtl/core_region.sv index aae0bd35..dce0b22f 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -30,29 +30,29 @@ module core_region #( // CORE PARAMETERS - parameter CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - // parameter USE_FPU = 1, - // parameter USE_HWPE = 1, - parameter N_EXT_PERF_COUNTERS = 1, - parameter CORE_ID = 0, - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32, - parameter INSTR_RDATA_WIDTH = 32, - parameter CLUSTER_ALIAS_BASE = 12'h000, - parameter REMAP_ADDRESS = 0, - - parameter APU_NARGS_CPU = 2, - parameter APU_WOP_CPU = 1, - parameter WAPUTYPE = 3, - parameter APU_NDSFLAGS_CPU = 3, - parameter APU_NUSFLAGS_CPU = 5, + parameter int unsigned CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + // parameter bit USE_FPU = 1, + // parameter bit USE_HWPE = 1, + parameter int unsigned N_EXT_PERF_COUNTERS = 1, + parameter int unsigned CORE_ID = 0, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned INSTR_RDATA_WIDTH = 32, + parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, + parameter int unsigned REMAP_ADDRESS = 0, + + parameter int unsigned APU_NARGS_CPU = 2, + parameter int unsigned APU_WOP_CPU = 1, + parameter int unsigned WAPUTYPE = 3, + parameter int unsigned APU_NDSFLAGS_CPU = 3, + parameter int unsigned APU_NUSFLAGS_CPU = 5, - parameter FPU = 0, - parameter FP_DIVSQRT = 0, - parameter SHARED_FP = 0, - parameter SHARED_FP_DIVSQRT = 0, + parameter int unsigned FPU = 0, + parameter int unsigned FP_DIVSQRT = 0, + parameter int unsigned SHARED_FP = 0, + parameter int unsigned SHARED_FP_DIVSQRT = 0, - parameter DEBUG_START_ADDR = `DEBUG_START_ADDR, + parameter bit [31:0] DEBUG_START_ADDR = `DEBUG_START_ADDR, parameter L2_SLM_FILE = "./slm_files/l2_stim.slm", parameter ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" diff --git a/rtl/dmac_wrap.sv b/rtl/dmac_wrap.sv index 916a7d4a..939dad36 100644 --- a/rtl/dmac_wrap.sv +++ b/rtl/dmac_wrap.sv @@ -18,19 +18,21 @@ module dmac_wrap #( - parameter NB_CTRLS = 2, - parameter NB_CORES = 8, - parameter NB_OUTSND_BURSTS = 8, - parameter MCHAN_BURST_LENGTH = 256, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_WIDTH = 64, - parameter AXI_USER_WIDTH = 6, - parameter AXI_ID_WIDTH = 4, - parameter PE_ID_WIDTH = 1, - parameter TCDM_ADD_WIDTH = 13, - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 32, - parameter BE_WIDTH = DATA_WIDTH/8 + parameter int unsigned NB_CTRLS = 2, + parameter int unsigned NB_CORES = 8, + parameter int unsigned NB_OUTSND_BURSTS = 8, + parameter int unsigned MCHAN_BURST_LENGTH = 256, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 4, + parameter int unsigned PE_ID_WIDTH = 1, + parameter int unsigned TCDM_ADD_WIDTH = 13, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( input logic clk_i, @@ -42,7 +44,8 @@ module dmac_wrap XBAR_PERIPH_BUS.Slave fc_ctrl_slave, hci_core_intf.master tcdm_master[3:0], - AXI_BUS.Master ext_master, + output axi_req_t ext_master_req_o, + input axi_resp_t ext_master_resp_i, output logic term_event_cl_o, output logic term_irq_cl_o, output logic term_event_pe_o, @@ -215,54 +218,54 @@ module dmac_wrap // EXTERNAL INITIATOR //*************************************** - .axi_master_aw_valid_o ( ext_master.aw_valid ), - .axi_master_aw_addr_o ( ext_master.aw_addr ), - .axi_master_aw_prot_o ( ext_master.aw_prot ), - .axi_master_aw_region_o ( ext_master.aw_region ), - .axi_master_aw_len_o ( ext_master.aw_len ), - .axi_master_aw_size_o ( ext_master.aw_size ), - .axi_master_aw_burst_o ( ext_master.aw_burst ), - .axi_master_aw_lock_o ( ext_master.aw_lock ), - .axi_master_aw_cache_o ( ext_master.aw_cache ), - .axi_master_aw_qos_o ( ext_master.aw_qos ), - .axi_master_aw_id_o ( ext_master.aw_id[AXI_ID_WIDTH-1:0] ), - .axi_master_aw_user_o ( ext_master.aw_user ), - .axi_master_aw_ready_i ( ext_master.aw_ready ), + .axi_master_aw_valid_o ( ext_master_req_o.aw_valid ), + .axi_master_aw_addr_o ( ext_master_req_o.aw.addr ), + .axi_master_aw_prot_o ( ext_master_req_o.aw.prot ), + .axi_master_aw_region_o ( ext_master_req_o.aw.region ), + .axi_master_aw_len_o ( ext_master_req_o.aw.len ), + .axi_master_aw_size_o ( ext_master_req_o.aw.size ), + .axi_master_aw_burst_o ( ext_master_req_o.aw.burst ), + .axi_master_aw_lock_o ( ext_master_req_o.aw.lock ), + .axi_master_aw_cache_o ( ext_master_req_o.aw.cache ), + .axi_master_aw_qos_o ( ext_master_req_o.aw.qos ), + .axi_master_aw_id_o ( ext_master_req_o.aw.id[AXI_ID_WIDTH-1:0] ), + .axi_master_aw_user_o ( ext_master_req_o.aw.user ), + .axi_master_aw_ready_i ( ext_master_resp_i.aw_ready ), - .axi_master_ar_valid_o ( ext_master.ar_valid ), - .axi_master_ar_addr_o ( ext_master.ar_addr ), - .axi_master_ar_prot_o ( ext_master.ar_prot ), - .axi_master_ar_region_o ( ext_master.ar_region ), - .axi_master_ar_len_o ( ext_master.ar_len ), - .axi_master_ar_size_o ( ext_master.ar_size ), - .axi_master_ar_burst_o ( ext_master.ar_burst ), - .axi_master_ar_lock_o ( ext_master.ar_lock ), - .axi_master_ar_cache_o ( ext_master.ar_cache ), - .axi_master_ar_qos_o ( ext_master.ar_qos ), - .axi_master_ar_id_o ( ext_master.ar_id[AXI_ID_WIDTH-1:0] ), - .axi_master_ar_user_o ( ext_master.ar_user ), - .axi_master_ar_ready_i ( ext_master.ar_ready ), + .axi_master_ar_valid_o ( ext_master_req_o.ar_valid ), + .axi_master_ar_addr_o ( ext_master_req_o.ar.addr ), + .axi_master_ar_prot_o ( ext_master_req_o.ar.prot ), + .axi_master_ar_region_o ( ext_master_req_o.ar.region ), + .axi_master_ar_len_o ( ext_master_req_o.ar.len ), + .axi_master_ar_size_o ( ext_master_req_o.ar.size ), + .axi_master_ar_burst_o ( ext_master_req_o.ar.burst ), + .axi_master_ar_lock_o ( ext_master_req_o.ar.lock ), + .axi_master_ar_cache_o ( ext_master_req_o.ar.cache ), + .axi_master_ar_qos_o ( ext_master_req_o.ar.qos ), + .axi_master_ar_id_o ( ext_master_req_o.ar.id[AXI_ID_WIDTH-1:0] ), + .axi_master_ar_user_o ( ext_master_req_o.ar.user ), + .axi_master_ar_ready_i ( ext_master_resp_i.ar_ready ), - .axi_master_w_valid_o ( ext_master.w_valid ), - .axi_master_w_data_o ( ext_master.w_data ), - .axi_master_w_strb_o ( ext_master.w_strb ), - .axi_master_w_user_o ( ext_master.w_user ), - .axi_master_w_last_o ( ext_master.w_last ), - .axi_master_w_ready_i ( ext_master.w_ready ), + .axi_master_w_valid_o ( ext_master_req_o.w_valid ), + .axi_master_w_data_o ( ext_master_req_o.w.data ), + .axi_master_w_strb_o ( ext_master_req_o.w.strb ), + .axi_master_w_user_o ( ext_master_req_o.w.user ), + .axi_master_w_last_o ( ext_master_req_o.w.last ), + .axi_master_w_ready_i ( ext_master_resp_i.w_ready ), - .axi_master_r_valid_i ( ext_master.r_valid ), - .axi_master_r_data_i ( ext_master.r_data ), - .axi_master_r_resp_i ( ext_master.r_resp ), - .axi_master_r_last_i ( ext_master.r_last ), - .axi_master_r_id_i ( ext_master.r_id[AXI_ID_WIDTH-1:0] ), - .axi_master_r_user_i ( ext_master.r_user ), - .axi_master_r_ready_o ( ext_master.r_ready ), + .axi_master_r_valid_i ( ext_master_resp_i.r_valid ), + .axi_master_r_data_i ( ext_master_resp_i.r.data ), + .axi_master_r_resp_i ( ext_master_resp_i.r.resp ), + .axi_master_r_last_i ( ext_master_resp_i.r.last ), + .axi_master_r_id_i ( ext_master_resp_i.r.id[AXI_ID_WIDTH-1:0] ), + .axi_master_r_user_i ( ext_master_resp_i.r.user ), + .axi_master_r_ready_o ( ext_master_req_o.r_ready ), - .axi_master_b_valid_i ( ext_master.b_valid ), - .axi_master_b_resp_i ( ext_master.b_resp ), - .axi_master_b_id_i ( ext_master.b_id[AXI_ID_WIDTH-1:0] ), - .axi_master_b_user_i ( ext_master.b_user ), - .axi_master_b_ready_o ( ext_master.b_ready ), + .axi_master_b_valid_i ( ext_master_resp_i.b_valid ), + .axi_master_b_resp_i ( ext_master_resp_i.b.resp ), + .axi_master_b_id_i ( ext_master_resp_i.b.id[AXI_ID_WIDTH-1:0] ), + .axi_master_b_user_i ( ext_master_resp_i.b.user ), + .axi_master_b_ready_o ( ext_master_req_o.b_ready ), .term_evt_o ( {term_event_pe_o,term_event_cl_o,term_event_o} ), .term_int_o ( {term_irq_pe_o,term_irq_cl_o,term_irq_o } ), @@ -270,6 +273,6 @@ module dmac_wrap .busy_o ( busy_o ) ); - assign ext_master.aw_atop = '0; + assign ext_master_req_o.aw.atop = '0; endmodule diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index e2e33063..069a4d2e 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -17,10 +17,10 @@ import hci_package::*; module hwpe_subsystem #( - parameter N_CORES = 8, - parameter N_MASTER_PORT = 9, - parameter ID_WIDTH = 8, - parameter USE_RBE = 0 + parameter int unsigned N_CORES = 8, + parameter int unsigned N_MASTER_PORT = 9, + parameter int unsigned ID_WIDTH = 8, + parameter bit USE_RBE = 0 ) ( input logic clk, diff --git a/rtl/per2axi_wrap.sv b/rtl/per2axi_wrap.sv index 770f9dc9..42b9088e 100644 --- a/rtl/per2axi_wrap.sv +++ b/rtl/per2axi_wrap.sv @@ -18,22 +18,25 @@ module per2axi_wrap #( - parameter NB_CORES = 4, - parameter PER_ADDR_WIDTH = 32, - parameter PER_ID_WIDTH = 5, - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_WIDTH = 64, - parameter AXI_USER_WIDTH = 6, - parameter AXI_ID_WIDTH = 4, - parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8, - parameter ID_WIDTH = PER_ID_WIDTH // required for XBAR_PERIPH_BUS interface + parameter int unsigned NB_CORES = 4, + parameter int unsigned PER_ADDR_WIDTH = 32, + parameter int unsigned PER_ID_WIDTH = 5, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 4, + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8, + parameter int unsigned ID_WIDTH = PER_ID_WIDTH, // required for XBAR_PERIPH_BUS interface + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, + input logic clk_i, + input logic rst_ni, + input logic test_en_i, XBAR_PERIPH_BUS.Slave periph_slave, - AXI_BUS.Master axi_master, + output axi_req_t axi_master_req_o, + input axi_resp_t axi_master_resp_i, output logic busy_o ); @@ -63,58 +66,58 @@ module per2axi_wrap .per_slave_r_id_o ( periph_slave.r_id[PER_ID_WIDTH-1:0] ), .per_slave_r_rdata_o ( periph_slave.r_rdata ), - .axi_master_aw_valid_o ( axi_master.aw_valid ), - .axi_master_aw_addr_o ( axi_master.aw_addr ), - .axi_master_aw_prot_o ( axi_master.aw_prot ), - .axi_master_aw_region_o ( axi_master.aw_region ), - .axi_master_aw_len_o ( axi_master.aw_len ), - .axi_master_aw_size_o ( axi_master.aw_size ), - .axi_master_aw_burst_o ( axi_master.aw_burst ), - .axi_master_aw_lock_o ( axi_master.aw_lock ), - .axi_master_aw_cache_o ( axi_master.aw_cache ), - .axi_master_aw_qos_o ( axi_master.aw_qos ), - .axi_master_aw_id_o ( axi_master.aw_id[AXI_ID_WIDTH-1:0] ), - .axi_master_aw_user_o ( axi_master.aw_user ), - .axi_master_aw_ready_i ( axi_master.aw_ready ), + .axi_master_aw_valid_o ( axi_master_req_o.aw_valid ), + .axi_master_aw_addr_o ( axi_master_req_o.aw.addr ), + .axi_master_aw_prot_o ( axi_master_req_o.aw.prot ), + .axi_master_aw_region_o ( axi_master_req_o.aw.region ), + .axi_master_aw_len_o ( axi_master_req_o.aw.len ), + .axi_master_aw_size_o ( axi_master_req_o.aw.size ), + .axi_master_aw_burst_o ( axi_master_req_o.aw.burst ), + .axi_master_aw_lock_o ( axi_master_req_o.aw.lock ), + .axi_master_aw_cache_o ( axi_master_req_o.aw.cache ), + .axi_master_aw_qos_o ( axi_master_req_o.aw.qos ), + .axi_master_aw_id_o ( axi_master_req_o.aw.id[AXI_ID_WIDTH-1:0] ), + .axi_master_aw_user_o ( axi_master_req_o.aw.user ), + .axi_master_aw_ready_i ( axi_master_resp_i.aw_ready ), - .axi_master_ar_valid_o ( axi_master.ar_valid ), - .axi_master_ar_addr_o ( axi_master.ar_addr ), - .axi_master_ar_prot_o ( axi_master.ar_prot ), - .axi_master_ar_region_o ( axi_master.ar_region ), - .axi_master_ar_len_o ( axi_master.ar_len ), - .axi_master_ar_size_o ( axi_master.ar_size ), - .axi_master_ar_burst_o ( axi_master.ar_burst ), - .axi_master_ar_lock_o ( axi_master.ar_lock ), - .axi_master_ar_cache_o ( axi_master.ar_cache ), - .axi_master_ar_qos_o ( axi_master.ar_qos ), - .axi_master_ar_id_o ( axi_master.ar_id[AXI_ID_WIDTH-1:0] ), - .axi_master_ar_user_o ( axi_master.ar_user ), - .axi_master_ar_ready_i ( axi_master.ar_ready ), + .axi_master_ar_valid_o ( axi_master_req_o.ar_valid ), + .axi_master_ar_addr_o ( axi_master_req_o.ar.addr ), + .axi_master_ar_prot_o ( axi_master_req_o.ar.prot ), + .axi_master_ar_region_o ( axi_master_req_o.ar.region ), + .axi_master_ar_len_o ( axi_master_req_o.ar.len ), + .axi_master_ar_size_o ( axi_master_req_o.ar.size ), + .axi_master_ar_burst_o ( axi_master_req_o.ar.burst ), + .axi_master_ar_lock_o ( axi_master_req_o.ar.lock ), + .axi_master_ar_cache_o ( axi_master_req_o.ar.cache ), + .axi_master_ar_qos_o ( axi_master_req_o.ar.qos ), + .axi_master_ar_id_o ( axi_master_req_o.ar.id[AXI_ID_WIDTH-1:0] ), + .axi_master_ar_user_o ( axi_master_req_o.ar.user ), + .axi_master_ar_ready_i ( axi_master_resp_i.ar_ready ), - .axi_master_w_valid_o ( axi_master.w_valid ), - .axi_master_w_data_o ( axi_master.w_data ), - .axi_master_w_strb_o ( axi_master.w_strb ), - .axi_master_w_user_o ( axi_master.w_user ), - .axi_master_w_last_o ( axi_master.w_last ), - .axi_master_w_ready_i ( axi_master.w_ready ), + .axi_master_w_valid_o ( axi_master_req_o.w_valid ), + .axi_master_w_data_o ( axi_master_req_o.w.data ), + .axi_master_w_strb_o ( axi_master_req_o.w.strb ), + .axi_master_w_user_o ( axi_master_req_o.w.user ), + .axi_master_w_last_o ( axi_master_req_o.w.last ), + .axi_master_w_ready_i ( axi_master_resp_i.w_ready ), - .axi_master_r_valid_i ( axi_master.r_valid ), - .axi_master_r_data_i ( axi_master.r_data ), - .axi_master_r_resp_i ( axi_master.r_resp ), - .axi_master_r_last_i ( axi_master.r_last ), - .axi_master_r_id_i ( axi_master.r_id[AXI_ID_WIDTH-1:0] ), - .axi_master_r_user_i ( axi_master.r_user ), - .axi_master_r_ready_o ( axi_master.r_ready ), + .axi_master_r_valid_i ( axi_master_resp_i.r_valid ), + .axi_master_r_data_i ( axi_master_resp_i.r.data ), + .axi_master_r_resp_i ( axi_master_resp_i.r.resp ), + .axi_master_r_last_i ( axi_master_resp_i.r.last ), + .axi_master_r_id_i ( axi_master_resp_i.r.id[AXI_ID_WIDTH-1:0] ), + .axi_master_r_user_i ( axi_master_resp_i.r.user ), + .axi_master_r_ready_o ( axi_master_req_o.r_ready ), - .axi_master_b_valid_i ( axi_master.b_valid ), - .axi_master_b_resp_i ( axi_master.b_resp ), - .axi_master_b_id_i ( axi_master.b_id[AXI_ID_WIDTH-1:0] ), - .axi_master_b_user_i ( axi_master.b_user ), - .axi_master_b_ready_o ( axi_master.b_ready ), + .axi_master_b_valid_i ( axi_master_resp_i.b_valid ), + .axi_master_b_resp_i ( axi_master_resp_i.b.resp ), + .axi_master_b_id_i ( axi_master_resp_i.b.id[AXI_ID_WIDTH-1:0] ), + .axi_master_b_user_i ( axi_master_resp_i.b.user ), + .axi_master_b_ready_o ( axi_master_req_o.b_ready ), .busy_o ( busy_o ) ); - assign axi_master.aw_atop = '0; + assign axi_master_req_o.aw.atop = '0; endmodule diff --git a/rtl/per_demux_wrap.sv b/rtl/per_demux_wrap.sv index fc4099b8..89411fef 100644 --- a/rtl/per_demux_wrap.sv +++ b/rtl/per_demux_wrap.sv @@ -18,8 +18,8 @@ module per_demux_wrap #( - parameter NB_MASTERS = 2, - parameter ADDR_OFFSET = 10 + parameter int unsigned NB_MASTERS = 2, + parameter int unsigned ADDR_OFFSET = 10 ) ( input logic clk_i, diff --git a/rtl/periph_FIFO.sv b/rtl/periph_FIFO.sv index cb143d67..474e53f9 100644 --- a/rtl/periph_FIFO.sv +++ b/rtl/periph_FIFO.sv @@ -18,9 +18,9 @@ module periph_FIFO #( - parameter ADDR_WIDTH=32, - parameter DATA_WIDTH=32, - parameter BYTE_ENABLE_BIT=DATA_WIDTH/8 + parameter int unsigned ADDR_WIDTH=32, + parameter int unsigned DATA_WIDTH=32, + parameter int unsigned BYTE_ENABLE_BIT=DATA_WIDTH/8 ) ( input logic clk_i, diff --git a/rtl/periph_demux.sv b/rtl/periph_demux.sv index 8e5c559b..e96c49c2 100644 --- a/rtl/periph_demux.sv +++ b/rtl/periph_demux.sv @@ -20,9 +20,9 @@ module periph_demux #( - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32, - parameter BE_WIDTH = DATA_WIDTH/8 + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8 ) ( input logic clk, diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 04a215bc..e9b03346 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -29,110 +29,110 @@ import hci_package::*; module pulp_cluster #( // cluster parameters - parameter CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) - parameter NB_CORES = 8, - parameter NB_HWPE_PORTS = 9, + parameter int unsigned CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + parameter int unsigned NB_CORES = 8, + parameter int unsigned NB_HWPE_PORTS = 9, // number of DMA TCDM plugs, NOT number of DMA slave peripherals! // Everything will go to hell if you change this! - parameter NB_DMAS = 4, - parameter NB_MPERIPHS = NB_MPERIPHS, - parameter NB_SPERIPHS = NB_SPERIPHS, + parameter int unsigned NB_DMAS = 4, + parameter int unsigned NB_MPERIPHS = NB_MPERIPHS, + parameter int unsigned NB_SPERIPHS = NB_SPERIPHS, - parameter CLUSTER_ALIAS_BASE = 12'h000, + parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, - parameter TCDM_SIZE = 64*1024, // [B], must be 2**N - parameter NB_TCDM_BANKS = 16, // must be 2**N - parameter TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B] - parameter TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words] - parameter HWPE_PRESENT = 1, // set to 1 if HW Processing Engines are present in the cluster - parameter USE_HETEROGENEOUS_INTERCONNECT = 1, // set to 1 to connect HWPEs via heterogeneous interconnect; to 0 for larger LIC + parameter int unsigned TCDM_SIZE = 64*1024, // [B], must be 2**N + parameter int unsigned NB_TCDM_BANKS = 16, // must be 2**N + parameter int unsigned TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B] + parameter int unsigned TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words] + parameter bit HWPE_PRESENT = 1, // set to 1 if HW Processing Engines are present in the cluster + parameter bit USE_HETEROGENEOUS_INTERCONNECT = 1, // set to 1 to connect HWPEs via heterogeneous interconnect; to 0 for larger LIC // I$ parameters - parameter SET_ASSOCIATIVE = 4, - parameter NB_CACHE_BANKS = 2, - parameter CACHE_LINE = 1, - parameter CACHE_SIZE = 4096, - parameter ICACHE_DATA_WIDTH = 128, - parameter L0_BUFFER_FEATURE = "DISABLED", - parameter MULTICAST_FEATURE = "DISABLED", - parameter SHARED_ICACHE = "ENABLED", - parameter DIRECT_MAPPED_FEATURE = "DISABLED", - parameter L2_SIZE = 512*1024, - parameter USE_REDUCED_TAG = "TRUE", + parameter int unsigned SET_ASSOCIATIVE = 4, + parameter int unsigned NB_CACHE_BANKS = 2, + parameter int unsigned CACHE_LINE = 1, + parameter int unsigned CACHE_SIZE = 4096, + parameter int unsigned ICACHE_DATA_WIDTH = 128, + parameter L0_BUFFER_FEATURE = "DISABLED", + parameter MULTICAST_FEATURE = "DISABLED", + parameter SHARED_ICACHE = "ENABLED", + parameter DIRECT_MAPPED_FEATURE = "DISABLED", + parameter int unsigned L2_SIZE = 512*1024, + parameter USE_REDUCED_TAG = "TRUE", // core parameters - parameter ROM_BOOT_ADDR = 32'h1A000000, - parameter BOOT_ADDR = 32'h1C000000, - parameter INSTR_RDATA_WIDTH = 32, - - parameter CLUST_FPU = 1, - parameter CLUST_FP_DIVSQRT = 1, - parameter CLUST_SHARED_FP = 2, - parameter CLUST_SHARED_FP_DIVSQRT = 2, + parameter bit [31:0] ROM_BOOT_ADDR = 32'h1A000000, + parameter bit [31:0] BOOT_ADDR = 32'h1C000000, + parameter int unsigned INSTR_RDATA_WIDTH = 32, + + parameter int unsigned CLUST_FPU = 1, + parameter int unsigned CLUST_FP_DIVSQRT = 1, + parameter int unsigned CLUST_SHARED_FP = 2, + parameter int unsigned CLUST_SHARED_FP_DIVSQRT = 2, // AXI parameters - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_C2S_WIDTH = 64, - parameter AXI_DATA_S2C_WIDTH = 32, - parameter AXI_USER_WIDTH = 6, - parameter AXI_ID_IN_WIDTH = 5, - parameter AXI_ID_OUT_WIDTH = 7, - parameter AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8, - parameter AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, - parameter DC_SLICE_BUFFER_WIDTH = 8, - parameter LOG_DEPTH = 3, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_C2S_WIDTH = 64, + parameter int unsigned AXI_DATA_S2C_WIDTH = 32, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_IN_WIDTH = 5, + parameter int unsigned AXI_ID_OUT_WIDTH = 7, + parameter int unsigned AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8, + parameter int unsigned AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, + parameter int unsigned DC_SLICE_BUFFER_WIDTH = 8, + parameter int unsigned LOG_DEPTH = 3, // CLUSTER TO SOC CDC AXI PARAMETER - localparam S2C_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam S2C_W_WIDTH = axi_pkg::w_width(AXI_DATA_S2C_WIDTH,AXI_USER_WIDTH), - localparam S2C_R_WIDTH = axi_pkg::r_width(AXI_DATA_S2C_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam S2C_B_WIDTH = axi_pkg::b_width(AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam S2C_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), + localparam int unsigned S2C_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), + localparam int unsigned S2C_W_WIDTH = axi_pkg::w_width(AXI_DATA_S2C_WIDTH,AXI_USER_WIDTH), + localparam int unsigned S2C_R_WIDTH = axi_pkg::r_width(AXI_DATA_S2C_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), + localparam int unsigned S2C_B_WIDTH = axi_pkg::b_width(AXI_ID_IN_WIDTH,AXI_USER_WIDTH), + localparam int unsigned S2C_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), // CLUSTER TO SOC CDC AXI PARAMETERS - localparam C2S_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam C2S_W_WIDTH = axi_pkg::w_width(AXI_DATA_C2S_WIDTH,AXI_USER_WIDTH), - localparam C2S_R_WIDTH = axi_pkg::r_width(AXI_DATA_C2S_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam C2S_B_WIDTH = axi_pkg::b_width(AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam C2S_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - - localparam ASYNC_C2S_AW_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AW_WIDTH, - localparam ASYNC_C2S_W_DATA_WIDTH = (2**LOG_DEPTH)*C2S_W_WIDTH, - localparam ASYNC_C2S_B_DATA_WIDTH = (2**LOG_DEPTH)*C2S_B_WIDTH, - localparam ASYNC_C2S_AR_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AR_WIDTH, - localparam ASYNC_C2S_R_DATA_WIDTH = (2**LOG_DEPTH)*C2S_R_WIDTH, + localparam int unsigned C2S_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), + localparam int unsigned C2S_W_WIDTH = axi_pkg::w_width(AXI_DATA_C2S_WIDTH,AXI_USER_WIDTH), + localparam int unsigned C2S_R_WIDTH = axi_pkg::r_width(AXI_DATA_C2S_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), + localparam int unsigned C2S_B_WIDTH = axi_pkg::b_width(AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), + localparam int unsigned C2S_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), + + localparam int unsigned ASYNC_C2S_AW_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AW_WIDTH, + localparam int unsigned ASYNC_C2S_W_DATA_WIDTH = (2**LOG_DEPTH)*C2S_W_WIDTH, + localparam int unsigned ASYNC_C2S_B_DATA_WIDTH = (2**LOG_DEPTH)*C2S_B_WIDTH, + localparam int unsigned ASYNC_C2S_AR_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AR_WIDTH, + localparam int unsigned ASYNC_C2S_R_DATA_WIDTH = (2**LOG_DEPTH)*C2S_R_WIDTH, - localparam ASYNC_S2C_AW_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AW_WIDTH, - localparam ASYNC_S2C_W_DATA_WIDTH = (2**LOG_DEPTH)*S2C_W_WIDTH, - localparam ASYNC_S2C_B_DATA_WIDTH = (2**LOG_DEPTH)*S2C_B_WIDTH, - localparam ASYNC_S2C_AR_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AR_WIDTH, - localparam ASYNC_S2C_R_DATA_WIDTH = (2**LOG_DEPTH)*S2C_R_WIDTH, + localparam int unsigned ASYNC_S2C_AW_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AW_WIDTH, + localparam int unsigned ASYNC_S2C_W_DATA_WIDTH = (2**LOG_DEPTH)*S2C_W_WIDTH, + localparam int unsigned ASYNC_S2C_B_DATA_WIDTH = (2**LOG_DEPTH)*S2C_B_WIDTH, + localparam int unsigned ASYNC_S2C_AR_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AR_WIDTH, + localparam int unsigned ASYNC_S2C_R_DATA_WIDTH = (2**LOG_DEPTH)*S2C_R_WIDTH, // TCDM and log interconnect parameters - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 32, - parameter BE_WIDTH = DATA_WIDTH/8, - parameter TEST_SET_BIT = 20, // bit used to indicate a test-and-set operation during a load in TCDM - parameter ADDR_MEM_WIDTH = $clog2(TCDM_BANK_SIZE/4), // WORD address width per TCDM bank (the word width is 32 bits) + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter int unsigned TEST_SET_BIT = 20, // bit used to indicate a test-and-set operation during a load in TCDM + parameter int unsigned ADDR_MEM_WIDTH = $clog2(TCDM_BANK_SIZE/4), // WORD address width per TCDM bank (the word width is 32 bits) // DMA parameters - parameter TCDM_ADD_WIDTH = ADDR_MEM_WIDTH + $clog2(NB_TCDM_BANKS) + 2, // BYTE address width TCDM - parameter NB_OUTSND_BURSTS = 8, - parameter MCHAN_BURST_LENGTH = 256, + parameter int unsigned TCDM_ADD_WIDTH = ADDR_MEM_WIDTH + $clog2(NB_TCDM_BANKS) + 2, // BYTE address width TCDM + parameter int unsigned NB_OUTSND_BURSTS = 8, + parameter int unsigned MCHAN_BURST_LENGTH = 256, // peripheral and periph interconnect parameters - parameter LOG_CLUSTER = 5, // unused - parameter PE_ROUTING_LSB = 10, // LSB used as routing BIT in periph interco + parameter int unsigned LOG_CLUSTER = 5, // unused + parameter int unsigned PE_ROUTING_LSB = 10, // LSB used as routing BIT in periph interco // parameter PE_ROUTING_MSB = 13, // MSB used as routing BIT in periph interco - parameter EVNT_WIDTH = 8, // size of the event bus - parameter REMAP_ADDRESS = 1, // for cluster virtualization + parameter int unsigned EVNT_WIDTH = 8, // size of the event bus + parameter int unsigned REMAP_ADDRESS = 1, // for cluster virtualization - localparam ASYNC_EVENT_DATA_WIDTH = (2**LOG_DEPTH)*EVNT_WIDTH, + localparam int unsigned ASYNC_EVENT_DATA_WIDTH = (2**LOG_DEPTH)*EVNT_WIDTH, // FPU PARAMETERS - parameter APU_NARGS_CPU = 3, - parameter APU_WOP_CPU = 6, - parameter WAPUTYPE = 3, - parameter APU_NDSFLAGS_CPU = 15, - parameter APU_NUSFLAGS_CPU = 5 + parameter int unsigned APU_NARGS_CPU = 3, + parameter int unsigned APU_WOP_CPU = 6, + parameter int unsigned WAPUTYPE = 3, + parameter int unsigned APU_NDSFLAGS_CPU = 15, + parameter int unsigned APU_NUSFLAGS_CPU = 5 ) ( input logic clk_i, @@ -433,78 +433,73 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; //*************************************************** /* synchronous AXI interfaces at CLUSTER/SOC interface */ //*************************************************** - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_slave_64(); + `AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_DATA_C2S_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_slave_32(); + `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_DATA_S2C_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) + `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_master(); + typedef s2c_aw_chan_t c2s_in_aw_chan_t; + typedef c2s_w_chan_t c2s_in_w_chan_t; + typedef s2c_b_chan_t c2s_in_b_chan_t; + typedef s2c_ar_chan_t c2s_in_ar_chan_t; + `AXI_TYPEDEF_R_CHAN_T(c2s_in_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_core_instr_bus(); + `AXI_TYPEDEF_REQ_T(c2s_req_t, c2s_aw_chan_t, c2s_w_chan_t, c2s_ar_chan_t) + `AXI_TYPEDEF_RESP_T(c2s_resp_t, c2s_b_chan_t, c2s_r_chan_t) + + `AXI_TYPEDEF_REQ_T(c2s_in_req_t, c2s_in_aw_chan_t, c2s_in_w_chan_t, c2s_in_ar_chan_t) + `AXI_TYPEDEF_RESP_T(c2s_in_resp_t, c2s_in_b_chan_t, c2s_in_r_chan_t) + + `AXI_TYPEDEF_REQ_T(s2c_req_t, s2c_aw_chan_t, s2c_w_chan_t, s2c_ar_chan_t) + `AXI_TYPEDEF_RESP_T(s2c_resp_t, s2c_b_chan_t, s2c_r_chan_t) + + c2s_in_req_t s_data_slave_64_req; + c2s_in_resp_t s_data_slave_64_resp; + + s2c_req_t s_data_slave_32_req; + s2c_resp_t s_data_slave_32_resp; + + c2s_req_t s_data_master_req; + c2s_resp_t s_data_master_resp; + + c2s_in_req_t s_core_instr_bus_req; + c2s_in_resp_t s_core_instr_bus_resp; + + // ***********************************************************************************************+ + // ***********************************************************************************************+ + // ***********************************************************************************************+ + // ***********************************************************************************************+ + // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - //*************************************************** /* synchronous AXI interfaces internal to the cluster */ //*************************************************** - + + // core per2axi -> ext - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_core_ext_bus(); + c2s_in_req_t s_core_ext_bus_req; + c2s_in_resp_t s_core_ext_bus_resp; // DMA -> ext - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_dma_ext_bus(); + c2s_in_req_t s_dma_ext_bus_req; + c2s_in_resp_t s_dma_ext_bus_resp; // ext -> axi2mem - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_ext_tcdm_bus(); + c2s_req_t s_ext_tcdm_bus_req; + c2s_resp_t s_ext_tcdm_bus_resp; // cluster bus -> axi2per - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_ext_mperiph_bus(); + c2s_req_t s_ext_mperiph_bus_req; + c2s_resp_t s_ext_mperiph_bus_resp; /* reset generator */ rstgen rstgen_i ( @@ -529,19 +524,39 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ) + .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), + .slave_req_t ( c2s_in_req_t ), + .slave_resp_t ( c2s_in_resp_t ), + .master_req_t ( c2s_req_t ), + .master_resp_t ( c2s_resp_t ), + .slave_aw_chan_t ( c2s_in_aw_chan_t ), + .master_aw_chan_t ( c2s_aw_chan_t ), + .w_chan_t ( c2s_w_chan_t ), + .slave_b_chan_t ( c2s_in_b_chan_t ), + .master_b_chan_t ( c2s_b_chan_t ), + .slave_ar_chan_t ( c2s_in_ar_chan_t ), + .master_ar_chan_t ( c2s_ar_chan_t ), + .slave_r_chan_t ( c2s_in_r_chan_t ), + .master_r_chan_t ( c2s_r_chan_t ) ) cluster_bus_wrap_i ( .clk_i ( clk_cluster ), .rst_ni ( s_rst_n ), .test_en_i ( test_mode_i ), .cluster_id_i ( cluster_id_i ), - .instr_slave ( s_core_instr_bus ), - .data_slave ( s_core_ext_bus ), - .dma_slave ( s_dma_ext_bus ), - .ext_slave ( s_data_slave_64 ), - .tcdm_master ( s_ext_tcdm_bus ), - .periph_master ( s_ext_mperiph_bus ), - .ext_master ( s_data_master ) + .data_slave_req_i ( s_core_ext_bus_req ), + .data_slave_resp_o ( s_core_ext_bus_resp ), + .instr_slave_req_i ( s_core_instr_bus_req ), + .instr_slave_resp_o ( s_core_instr_bus_resp ), + .dma_slave_req_i ( s_dma_ext_bus_req ), + .dma_slave_resp_o ( s_dma_ext_bus_resp ), + .ext_slave_req_i ( s_data_slave_64_req ), + .ext_slave_resp_o ( s_data_slave_64_resp ), + .tcdm_master_req_o ( s_ext_tcdm_bus_req ), + .tcdm_master_resp_i ( s_ext_tcdm_bus_resp ), + .periph_master_req_o ( s_ext_mperiph_bus_req ), + .periph_master_resp_i( s_ext_mperiph_bus_resp), + .ext_master_req_o ( s_data_master_req ), + .ext_master_resp_i ( s_data_master_resp ) ); axi2mem_wrap #( @@ -549,28 +564,34 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ) + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) ) axi2mem_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave ( s_ext_tcdm_bus ), - .tcdm_master ( s_hci_ext ), - .busy_o ( s_axi2mem_busy ) + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .axi_slave_req_i ( s_ext_tcdm_bus_req ), + .axi_slave_resp_o ( s_ext_tcdm_bus_resp ), + .tcdm_master ( s_hci_ext ), + .busy_o ( s_axi2mem_busy ) ); axi2per_wrap #( .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) ) axi2per_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave ( s_ext_mperiph_bus ), - .periph_master ( s_mperiph_bus ), - .busy_o ( s_axi2per_busy ) + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .axi_slave_req_i ( s_ext_mperiph_bus_req ), + .axi_slave_resp_o ( s_ext_mperiph_bus_resp ), + .periph_master ( s_mperiph_bus ), + .busy_o ( s_axi2per_busy ) ); per_demux_wrap #( @@ -614,14 +635,17 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) ) per2axi_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), - .axi_master ( s_core_ext_bus ), - .busy_o ( s_per2axi_busy ) + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), + .axi_master_req_o ( s_core_ext_bus_req ), + .axi_master_resp_i ( s_core_ext_bus_resp ), + .busy_o ( s_per2axi_busy ) ); @@ -685,7 +709,9 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), .DATA_WIDTH ( DATA_WIDTH ), .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ) + .BE_WIDTH ( BE_WIDTH ), + .axi_req_t ( c2s_in_req_t ), + .axi_resp_t ( c2s_in_resp_t ) ) dmac_wrap_i ( .clk_i ( clk_cluster ), .rst_ni ( s_rst_n ), @@ -694,7 +720,8 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .cl_ctrl_slave ( s_periph_dma_bus[0]), .fc_ctrl_slave ( s_periph_dma_bus[1]), .tcdm_master ( s_hci_dma ), - .ext_master ( s_dma_ext_bus ), + .ext_master_req_o ( s_dma_ext_bus_req ), + .ext_master_resp_i ( s_dma_ext_bus_resp ), .term_event_cl_o ( s_dma_cl_event ), .term_irq_cl_o ( s_dma_cl_irq ), .term_event_pe_o ( s_dma_fc_event ), @@ -1064,66 +1091,66 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; .enable_l1_l15_prefetch_i ( s_enable_l1_l15_prefetch ), // set it to 1 to use prefetch feature //AXI read address bus ------------------------------------------- - .axi_master_arid_o ( s_core_instr_bus.ar_id ), - .axi_master_araddr_o ( s_core_instr_bus.ar_addr ), - .axi_master_arlen_o ( s_core_instr_bus.ar_len ), //burst length - 1 to 16 - .axi_master_arsize_o ( s_core_instr_bus.ar_size ), //size of each transfer in burst - .axi_master_arburst_o ( s_core_instr_bus.ar_burst ), //accept only incr burst=01 - .axi_master_arlock_o ( s_core_instr_bus.ar_lock ), //only normal access supported axs_awlock=00 - .axi_master_arcache_o ( s_core_instr_bus.ar_cache ), - .axi_master_arprot_o ( s_core_instr_bus.ar_prot ), - .axi_master_arregion_o ( s_core_instr_bus.ar_region ), // - .axi_master_aruser_o ( s_core_instr_bus.ar_user ), // - .axi_master_arqos_o ( s_core_instr_bus.ar_qos ), // - .axi_master_arvalid_o ( s_core_instr_bus.ar_valid ), //master addr valid - .axi_master_arready_i ( s_core_instr_bus.ar_ready ), //slave ready to accept + .axi_master_arid_o ( s_core_instr_bus_req.ar.id ), + .axi_master_araddr_o ( s_core_instr_bus_req.ar.addr ), + .axi_master_arlen_o ( s_core_instr_bus_req.ar.len ), //burst length - 1 to 16 + .axi_master_arsize_o ( s_core_instr_bus_req.ar.size ), //size of each transfer in burst + .axi_master_arburst_o ( s_core_instr_bus_req.ar.burst ), //accept only incr burst=01 + .axi_master_arlock_o ( s_core_instr_bus_req.ar.lock ), //only normal access supported axs_awlock=00 + .axi_master_arcache_o ( s_core_instr_bus_req.ar.cache ), + .axi_master_arprot_o ( s_core_instr_bus_req.ar.prot ), + .axi_master_arregion_o ( s_core_instr_bus_req.ar.region ), // + .axi_master_aruser_o ( s_core_instr_bus_req.ar.user ), // + .axi_master_arqos_o ( s_core_instr_bus_req.ar.qos ), // + .axi_master_arvalid_o ( s_core_instr_bus_req.ar_valid ), //master addr valid + .axi_master_arready_i ( s_core_instr_bus_resp.ar_ready ), //slave ready to accept // --------------------------------------------------------------- //AXI BACKWARD read data bus ---------------------------------------------- - .axi_master_rid_i ( s_core_instr_bus.r_id ), - .axi_master_rdata_i ( s_core_instr_bus.r_data ), - .axi_master_rresp_i ( s_core_instr_bus.r_resp ), - .axi_master_rlast_i ( s_core_instr_bus.r_last ), //last transfer in burst - .axi_master_ruser_i ( s_core_instr_bus.r_user ), - .axi_master_rvalid_i ( s_core_instr_bus.r_valid ), //slave data valid - .axi_master_rready_o ( s_core_instr_bus.r_ready ), //master ready to accept + .axi_master_rid_i ( s_core_instr_bus_resp.r.id ), + .axi_master_rdata_i ( s_core_instr_bus_resp.r.data ), + .axi_master_rresp_i ( s_core_instr_bus_resp.r.resp ), + .axi_master_rlast_i ( s_core_instr_bus_resp.r.last ), //last transfer in burst + .axi_master_ruser_i ( s_core_instr_bus_resp.r.user ), + .axi_master_rvalid_i ( s_core_instr_bus_resp.r_valid ), //slave data valid + .axi_master_rready_o ( s_core_instr_bus_req.r_ready ), //master ready to accept // NOT USED ---------------------------------------------- - .axi_master_awid_o ( s_core_instr_bus.aw_id ), - .axi_master_awaddr_o ( s_core_instr_bus.aw_addr ), - .axi_master_awlen_o ( s_core_instr_bus.aw_len ), - .axi_master_awsize_o ( s_core_instr_bus.aw_size ), - .axi_master_awburst_o ( s_core_instr_bus.aw_burst ), - .axi_master_awlock_o ( s_core_instr_bus.aw_lock ), - .axi_master_awcache_o ( s_core_instr_bus.aw_cache ), - .axi_master_awprot_o ( s_core_instr_bus.aw_prot ), - .axi_master_awregion_o ( s_core_instr_bus.aw_region ), - .axi_master_awuser_o ( s_core_instr_bus.aw_user ), - .axi_master_awqos_o ( s_core_instr_bus.aw_qos ), - .axi_master_awvalid_o ( s_core_instr_bus.aw_valid ), - .axi_master_awready_i ( s_core_instr_bus.aw_ready ), + .axi_master_awid_o ( s_core_instr_bus_req.aw.id ), + .axi_master_awaddr_o ( s_core_instr_bus_req.aw.addr ), + .axi_master_awlen_o ( s_core_instr_bus_req.aw.len ), + .axi_master_awsize_o ( s_core_instr_bus_req.aw.size ), + .axi_master_awburst_o ( s_core_instr_bus_req.aw.burst ), + .axi_master_awlock_o ( s_core_instr_bus_req.aw.lock ), + .axi_master_awcache_o ( s_core_instr_bus_req.aw.cache ), + .axi_master_awprot_o ( s_core_instr_bus_req.aw.prot ), + .axi_master_awregion_o ( s_core_instr_bus_req.aw.region ), + .axi_master_awuser_o ( s_core_instr_bus_req.aw.user ), + .axi_master_awqos_o ( s_core_instr_bus_req.aw.qos ), + .axi_master_awvalid_o ( s_core_instr_bus_req.aw_valid ), + .axi_master_awready_i ( s_core_instr_bus_resp.aw_ready ), // NOT USED ---------------------------------------------- - .axi_master_wdata_o ( s_core_instr_bus.w_data ), - .axi_master_wstrb_o ( s_core_instr_bus.w_strb ), - .axi_master_wlast_o ( s_core_instr_bus.w_last ), - .axi_master_wuser_o ( s_core_instr_bus.w_user ), - .axi_master_wvalid_o ( s_core_instr_bus.w_valid ), - .axi_master_wready_i ( s_core_instr_bus.w_ready ), + .axi_master_wdata_o ( s_core_instr_bus_req.w.data ), + .axi_master_wstrb_o ( s_core_instr_bus_req.w.strb ), + .axi_master_wlast_o ( s_core_instr_bus_req.w.last ), + .axi_master_wuser_o ( s_core_instr_bus_req.w.user ), + .axi_master_wvalid_o ( s_core_instr_bus_req.w_valid ), + .axi_master_wready_i ( s_core_instr_bus_resp.w_ready ), // --------------------------------------------------------------- // NOT USED ---------------------------------------------- - .axi_master_bid_i ( s_core_instr_bus.b_id ), - .axi_master_bresp_i ( s_core_instr_bus.b_resp ), - .axi_master_buser_i ( s_core_instr_bus.b_user ), - .axi_master_bvalid_i ( s_core_instr_bus.b_valid ), - .axi_master_bready_o ( s_core_instr_bus.b_ready ), + .axi_master_bid_i ( s_core_instr_bus_resp.b.id ), + .axi_master_bresp_i ( s_core_instr_bus_resp.b.resp ), + .axi_master_buser_i ( s_core_instr_bus_resp.b.user ), + .axi_master_bvalid_i ( s_core_instr_bus_resp.b_valid ), + .axi_master_bready_o ( s_core_instr_bus_req.b_ready ), // --------------------------------------------------------------- .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ) ); - assign s_core_instr_bus.aw_atop = '0; + assign s_core_instr_bus_req.aw.atop = '0; /* TCDM banks */ tcdm_banks_wrap #( @@ -1141,118 +1168,99 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; ); /* AXI interconnect infrastructure (slices, size conversion) */ - //******************************************************** - //**************** AXI REGISTER SLICES ******************* - //******************************************************** - // CLUSTER TO SOC - - `AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_DATA_C2S_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[AXI_DATA_C2S_WIDTH-1:0],logic[AXI_ID_OUT_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - - `AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t) - `AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t) - - c2s_req_t src_req ; - c2s_resp_t src_resp; - - `AXI_ASSIGN_TO_REQ(src_req,s_data_master) - `AXI_ASSIGN_FROM_RESP(s_data_master,src_resp) + //******************************************************** + //**************** AXI REGISTER SLICES ******************* + //******************************************************** + // CLUSTER TO SOC axi_cdc_src #( - .aw_chan_t (c2s_aw_chan_t), - .w_chan_t (c2s_w_chan_t), - .b_chan_t (c2s_b_chan_t), - .r_chan_t (c2s_r_chan_t), - .ar_chan_t (c2s_ar_chan_t), - .axi_req_t (c2s_req_t ), - .axi_resp_t(c2s_resp_t ), + .aw_chan_t (c2s_aw_chan_t), + .w_chan_t (c2s_w_chan_t), + .b_chan_t (c2s_b_chan_t), + .r_chan_t (c2s_r_chan_t), + .ar_chan_t (c2s_ar_chan_t), + .axi_req_t (c2s_req_t ), + .axi_resp_t(c2s_resp_t ), .LogDepth ( LOG_DEPTH ) - ) axi_master_cdc_i ( - .src_rst_ni ( s_rst_n ), - .src_clk_i ( clk_cluster ), - .src_req_i ( src_req ), - .src_resp_o ( src_resp ), - .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), - .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), - .async_data_master_aw_data_o ( async_data_master_aw_data_o ), - .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), - .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), - .async_data_master_w_data_o ( async_data_master_w_data_o ), - .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), - .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), - .async_data_master_ar_data_o ( async_data_master_ar_data_o ), - .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), - .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), - .async_data_master_b_data_i ( async_data_master_b_data_i ), - .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), - .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), - .async_data_master_r_data_i ( async_data_master_r_data_i ) - ); - - // SOC TO CLUSTER - + ) axi_master_cdc_i ( + .src_rst_ni ( s_rst_n ), + .src_clk_i ( clk_cluster ), + .src_req_i ( s_data_master_req ), + .src_resp_o ( s_data_master_resp ), + .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), + .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), + .async_data_master_aw_data_o ( async_data_master_aw_data_o ), + .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), + .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), + .async_data_master_w_data_o ( async_data_master_w_data_o ), + .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), + .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), + .async_data_master_ar_data_o ( async_data_master_ar_data_o ), + .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), + .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), + .async_data_master_b_data_i ( async_data_master_b_data_i ), + .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), + .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), + .async_data_master_r_data_i ( async_data_master_r_data_i ) + ); - `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_DATA_S2C_WIDTH/8-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[AXI_ADDR_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[AXI_DATA_S2C_WIDTH-1:0],logic[AXI_ID_IN_WIDTH-1:0],logic[AXI_USER_WIDTH-1:0]) - - `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) - `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) + // SOC TO CLUSTER - s2c_req_t dst_req; - s2c_resp_t dst_resp; - - `AXI_ASSIGN_FROM_REQ(s_data_slave_32,dst_req) - `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_32) - axi_cdc_dst #( - .aw_chan_t (s2c_aw_chan_t), - .w_chan_t (s2c_w_chan_t ), - .b_chan_t (s2c_b_chan_t ), - .r_chan_t (s2c_r_chan_t ), - .ar_chan_t (s2c_ar_chan_t), - .axi_req_t (s2c_req_t ), - .axi_resp_t(s2c_resp_t ), - .LogDepth ( LOG_DEPTH ) - ) axi_slave_cdc_i ( - .dst_rst_ni ( s_rst_n ), - .dst_clk_i ( clk_i ), - .dst_req_o ( dst_req ), - .dst_resp_i ( dst_resp ), - .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), - .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), - .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), - .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), - .async_data_slave_w_data_i ( async_data_slave_w_data_i ), - .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), - .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), - .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), - .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), - .async_data_slave_b_data_o ( async_data_slave_b_data_o ), - .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), - .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), - .async_data_slave_r_data_o ( async_data_slave_r_data_o ) - ); - - axi_dw_converter_intf #( - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_SLV_PORT_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_MST_PORT_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_MAX_READS ( 1 ) + .aw_chan_t (s2c_aw_chan_t), + .w_chan_t (s2c_w_chan_t ), + .b_chan_t (s2c_b_chan_t ), + .r_chan_t (s2c_r_chan_t ), + .ar_chan_t (s2c_ar_chan_t), + .axi_req_t (s2c_req_t ), + .axi_resp_t(s2c_resp_t ), + .LogDepth ( LOG_DEPTH ) + ) axi_slave_cdc_i ( + .dst_rst_ni ( s_rst_n ), + .dst_clk_i ( clk_i ), + .dst_req_o ( s_data_slave_32_req ), + .dst_resp_i ( s_data_slave_32_resp ), + .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), + .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), + .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), + .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), + .async_data_slave_w_data_i ( async_data_slave_w_data_i ), + .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), + .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), + .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), + .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), + .async_data_slave_b_data_o ( async_data_slave_b_data_o ), + .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), + .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), + .async_data_slave_r_data_o ( async_data_slave_r_data_o ) + ); + + axi_dw_converter #( + .AxiMaxReads ( 1 ), + .AxiSlvPortDataWidth ( AXI_DATA_S2C_WIDTH ), + .AxiMstPortDataWidth ( AXI_DATA_C2S_WIDTH ), + .AxiIdWidth ( AXI_ID_IN_WIDTH ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .aw_chan_t ( s2c_aw_chan_t ), + .mst_w_chan_t ( c2s_w_chan_t ), + .slv_w_chan_t ( s2c_w_chan_t ), + .b_chan_t ( s2c_b_chan_t ), + .ar_chan_t ( s2c_ar_chan_t ), + .mst_r_chan_t ( c2s_in_r_chan_t ), + .slv_r_chan_t ( s2c_r_chan_t ), + .axi_mst_req_t ( s2c_req_t ), + .axi_mst_resp_t ( s2c_resp_t ), + .axi_slv_req_t ( c2s_in_req_t ), + .axi_slv_resp_t ( c2s_in_resp_t ) ) axi_dw_UPSIZE_32_64_wrap_i ( - .clk_i ( clk_i ), - .rst_ni ( s_rst_n ), - .slv ( s_data_slave_32 ), - .mst ( s_data_slave_64 ) + .clk_i ( clk_i ), + .rst_ni ( s_rst_n ), + .slv_req_i ( s_data_slave_32_req ), + .slv_resp_o( s_data_slave_32_resp ), + .mst_req_o ( s_data_slave_64_req ), + .mst_resp_i( s_data_slave_64_resp ) ); /* event synchronizers */ diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 7760d0e9..7d865883 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -17,12 +17,12 @@ */ module tcdm_banks_wrap #( - parameter BankSize = 256, //- -> OVERRIDE - parameter NbBanks = 1, // --> OVERRIDE - parameter DataWidth = 32, - parameter AddrWidth = 32, - parameter BeWidth = DataWidth/8, - parameter IdWidth = 1 + parameter int unsigned BankSize = 256, //- -> OVERRIDE + parameter int unsigned NbBanks = 1, // --> OVERRIDE + parameter int unsigned DataWidth = 32, + parameter int unsigned AddrWidth = 32, + parameter int unsigned BeWidth = DataWidth/8, + parameter int unsigned IdWidth = 1 ) ( input logic clk_i, input logic rst_ni, diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index e7b93468..e3db5fc2 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -27,17 +27,17 @@ module xbar_pe_wrap import pulp_cluster_package::*; #( - parameter NB_CORES = 8, - parameter NB_MPERIPHS = 1, - parameter NB_SPERIPHS = 10, - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32, - parameter BE_WIDTH = 0, - parameter PE_ROUTING_LSB = 10, - parameter PE_ROUTING_MSB = 13, - parameter bit HWPE_PRESENT = 1'b1, - parameter CLUSTER_ALIAS_BASE = 12'h000, - parameter ADDREXT = 1'b0 + parameter int unsigned NB_CORES = 8, + parameter int unsigned NB_MPERIPHS = 1, + parameter int unsigned NB_SPERIPHS = 10, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned BE_WIDTH = 0, + parameter int unsigned PE_ROUTING_LSB = 10, + parameter int unsigned PE_ROUTING_MSB = 13, + parameter bit HWPE_PRESENT = 1'b1, + parameter bit [11:0] CLUSTER_ALIAS_BASE = 12'h000, + parameter bit ADDREXT = 1'b0 ) ( input logic clk_i, diff --git a/scripts/run_and_exit.tcl b/scripts/run_and_exit.tcl new file mode 100644 index 00000000..242b667c --- /dev/null +++ b/scripts/run_and_exit.tcl @@ -0,0 +1,23 @@ +if {![info exists VSIM_PATH ]} { + return -code error -errorinfo "[ERRORINFO] You must set the \"VSIM_PATH\" variable before sourcing the start script." + set VSIM_PATH "" +} + +if {![info exists APP]} { + set APP "./build/test/test" +} + +if {![info exists VSIM]} { + set VSIM vsim +} + +$VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test + +add log -r /* + +proc run_and_exit {} { + run -all + quit -code [examine -radix decimal sim:/pulp_cluster_tb/ret_val(30:0)] +} + +run_and_exit diff --git a/scripts/start.tcl b/scripts/start.tcl index e6d30cd1..69413969 100644 --- a/scripts/start.tcl +++ b/scripts/start.tcl @@ -3,7 +3,11 @@ if {![info exists VSIM_PATH ]} { set VSIM_PATH "" } -vsim +permissive -suppress 3053 -suppress 8885 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test +if {![info exists VSIM]} { + set VSIM vsim +} + +$VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test add log -r /* run -all diff --git a/tb/axi2apb_64_32.sv b/tb/axi2apb_64_32.sv deleted file mode 100644 index c98b1798..00000000 --- a/tb/axi2apb_64_32.sv +++ /dev/null @@ -1,745 +0,0 @@ -// Copyright 2014-2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Igor Loi -// Davide Rossi -// Florian Zaruba - -`define OKAY 2'b00 -`define EXOKAY 2'b01 -`define SLVERR 2'b10 -`define DECERR 2'b11 - -module axi2apb_64_32 #( - parameter int unsigned AXI4_ADDRESS_WIDTH = 32, - parameter int unsigned AXI4_RDATA_WIDTH = 64, - parameter int unsigned AXI4_WDATA_WIDTH = 64, - parameter int unsigned AXI4_ID_WIDTH = 16, - parameter int unsigned AXI4_USER_WIDTH = 10, - parameter int unsigned AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, - - parameter int unsigned BUFF_DEPTH_SLAVE = 4, - parameter int unsigned APB_NUM_SLAVES = 8, - parameter int unsigned APB_ADDR_WIDTH = 12 -) -( - input logic ACLK, - input logic ARESETn, - input logic test_en_i, - // --------------------------------------------------------- - // AXI TARG Port Declarations ------------------------------ - // --------------------------------------------------------- - //AXI write address bus -------------- // USED// ----------- - input logic [AXI4_ID_WIDTH-1:0] AWID_i , - input logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR_i , - input logic [ 7:0] AWLEN_i , - input logic [ 2:0] AWSIZE_i , - input logic [ 1:0] AWBURST_i , - input logic AWLOCK_i , - input logic [ 3:0] AWCACHE_i , - input logic [ 2:0] AWPROT_i , - input logic [ 3:0] AWREGION_i , - input logic [ AXI4_USER_WIDTH-1:0] AWUSER_i , - input logic [ 3:0] AWQOS_i , - input logic AWVALID_i , - output logic AWREADY_o , - // --------------------------------------------------------- - - //AXI write data bus -------------- // USED// -------------- - input logic [AXI_NUMBYTES-1:0][7:0] WDATA_i , - input logic [AXI_NUMBYTES-1:0] WSTRB_i , - input logic WLAST_i , - input logic [AXI4_USER_WIDTH-1:0] WUSER_i , - input logic WVALID_i , - output logic WREADY_o , - // --------------------------------------------------------- - - //AXI write response bus -------------- // USED// ---------- - output logic [AXI4_ID_WIDTH-1:0] BID_o , - output logic [ 1:0] BRESP_o , - output logic BVALID_o , - output logic [AXI4_USER_WIDTH-1:0] BUSER_o , - input logic BREADY_i , - // --------------------------------------------------------- - - //AXI read address bus ------------------------------------- - input logic [AXI4_ID_WIDTH-1:0] ARID_i , - input logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR_i , - input logic [ 7:0] ARLEN_i , - input logic [ 2:0] ARSIZE_i , - input logic [ 1:0] ARBURST_i , - input logic ARLOCK_i , - input logic [ 3:0] ARCACHE_i , - input logic [ 2:0] ARPROT_i , - input logic [ 3:0] ARREGION_i , - input logic [ AXI4_USER_WIDTH-1:0] ARUSER_i , - input logic [ 3:0] ARQOS_i , - input logic ARVALID_i , - output logic ARREADY_o , - // --------------------------------------------------------- - - //AXI read data bus ---------------------------------------- - output logic [AXI4_ID_WIDTH-1:0] RID_o , - output logic [AXI4_RDATA_WIDTH-1:0] RDATA_o , - output logic [ 1:0] RRESP_o , - output logic RLAST_o , - output logic [AXI4_USER_WIDTH-1:0] RUSER_o , - output logic RVALID_o , - input logic RREADY_i , - // --------------------------------------------------------- - - output logic PENABLE , - output logic PWRITE , - output logic [APB_ADDR_WIDTH-1:0] PADDR , - output logic PSEL , - output logic [31:0] PWDATA , - input logic [31:0] PRDATA , - input logic PREADY , - input logic PSLVERR -); - - // -------------------- - // AXI write address bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] AWID; - logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR; - logic [ 7:0] AWLEN; - logic [ 2:0] AWSIZE; - logic [ 1:0] AWBURST; - logic AWLOCK; - logic [ 3:0] AWCACHE; - logic [ 2:0] AWPROT; - logic [ 3:0] AWREGION; - logic [ AXI4_USER_WIDTH-1:0] AWUSER; - logic [ 3:0] AWQOS; - logic AWVALID; - logic AWREADY; - // -------------------- - // AXI write data bus - // -------------------- - logic [1:0][31:0] WDATA; // from FIFO - logic [AXI_NUMBYTES-1:0] WSTRB; // from FIFO - logic WLAST; // from FIFO - logic [AXI4_USER_WIDTH-1:0] WUSER; // from FIFO - logic WVALID; // from FIFO - logic WREADY; // TO FIFO - // -------------------- - // AXI write response bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] BID; - logic [ 1:0] BRESP; - logic BVALID; - logic [AXI4_USER_WIDTH-1:0] BUSER; - logic BREADY; - // -------------------- - // AXI read address bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] ARID; - logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR; - logic [ 7:0] ARLEN; - logic [ 2:0] ARSIZE; - logic [ 1:0] ARBURST; - logic ARLOCK; - logic [ 3:0] ARCACHE; - logic [ 2:0] ARPROT; - logic [ 3:0] ARREGION; - logic [ AXI4_USER_WIDTH-1:0] ARUSER; - logic [ 3:0] ARQOS; - logic ARVALID; - logic ARREADY; - // -------------------- - // AXI read data bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] RID; - logic [1:0][31:0] RDATA; - logic [ 1:0] RRESP; - logic RLAST; - logic [AXI4_USER_WIDTH-1:0] RUSER; - logic RVALID; - logic RREADY; - - enum logic [3:0] { IDLE, - SINGLE_RD, SINGLE_RD_64, - BURST_RD_1, BURST_RD, BURST_RD_64, - BURST_WR, BURST_WR_64, - SINGLE_WR,SINGLE_WR_64, - WAIT_R_PREADY, WAIT_W_PREADY - } CS, NS; - - logic W_word_sel; - - logic [APB_ADDR_WIDTH-1:0] address; - - logic read_req; - logic write_req; - - logic sample_AR; - logic [8:0] ARLEN_Q; - logic decr_ARLEN; - - logic sample_AW; - logic [8:0] AWLEN_Q; - logic decr_AWLEN; - - logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR_Q; - logic incr_ARADDR; - - logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR_Q; - logic incr_AWADDR; - - logic sample_RDATA_0; // sample the first 32 bit chunk to be aggregated in 64 bit rdata - logic sample_RDATA_1; // sample the second 32 bit chunk to be aggregated in 64 bit rdata - logic [31:0] RDATA_Q_0; - logic [31:0] RDATA_Q_1; - - assign PENABLE = write_req | read_req; - assign PWRITE = write_req; - assign PADDR = address[APB_ADDR_WIDTH-1:0]; - - assign PWDATA = WDATA[W_word_sel]; - assign PSEL = 1'b1; - - // AXI WRITE ADDRESS CHANNEL BUFFER - axi_aw_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .ADDR_WIDTH ( AXI4_ADDRESS_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_aw_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( AWVALID_i ), - .slave_addr_i ( AWADDR_i ), - .slave_prot_i ( AWPROT_i ), - .slave_region_i ( AWREGION_i ), - .slave_len_i ( AWLEN_i ), - .slave_size_i ( AWSIZE_i ), - .slave_burst_i ( AWBURST_i ), - .slave_lock_i ( AWLOCK_i ), - .slave_cache_i ( AWCACHE_i ), - .slave_qos_i ( AWQOS_i ), - .slave_id_i ( AWID_i ), - .slave_user_i ( AWUSER_i ), - .slave_ready_o ( AWREADY_o ), - .master_valid_o ( AWVALID ), - .master_addr_o ( AWADDR ), - .master_prot_o ( AWPROT ), - .master_region_o ( AWREGION ), - .master_len_o ( AWLEN ), - .master_size_o ( AWSIZE ), - .master_burst_o ( AWBURST ), - .master_lock_o ( AWLOCK ), - .master_cache_o ( AWCACHE ), - .master_qos_o ( AWQOS ), - .master_id_o ( AWID ), - .master_user_o ( AWUSER ), - .master_ready_i ( AWREADY ) - ); - // AXI WRITE ADDRESS CHANNEL BUFFER - axi_ar_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .ADDR_WIDTH ( AXI4_ADDRESS_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_ar_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( ARVALID_i ), - .slave_addr_i ( ARADDR_i ), - .slave_prot_i ( ARPROT_i ), - .slave_region_i ( ARREGION_i ), - .slave_len_i ( ARLEN_i ), - .slave_size_i ( ARSIZE_i ), - .slave_burst_i ( ARBURST_i ), - .slave_lock_i ( ARLOCK_i ), - .slave_cache_i ( ARCACHE_i ), - .slave_qos_i ( ARQOS_i ), - .slave_id_i ( ARID_i ), - .slave_user_i ( ARUSER_i ), - .slave_ready_o ( ARREADY_o ), - .master_valid_o ( ARVALID ), - .master_addr_o ( ARADDR ), - .master_prot_o ( ARPROT ), - .master_region_o ( ARREGION ), - .master_len_o ( ARLEN ), - .master_size_o ( ARSIZE ), - .master_burst_o ( ARBURST ), - .master_lock_o ( ARLOCK ), - .master_cache_o ( ARCACHE ), - .master_qos_o ( ARQOS ), - .master_id_o ( ARID ), - .master_user_o ( ARUSER ), - .master_ready_i ( ARREADY ) - ); - axi_w_buffer #( - .DATA_WIDTH ( AXI4_WDATA_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_w_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( WVALID_i ), - .slave_data_i ( WDATA_i ), - .slave_strb_i ( WSTRB_i ), - .slave_user_i ( WUSER_i ), - .slave_last_i ( WLAST_i ), - .slave_ready_o ( WREADY_o ), - .master_valid_o ( WVALID ), - .master_data_o ( WDATA ), - .master_strb_o ( WSTRB ), - .master_user_o ( WUSER ), - .master_last_o ( WLAST ), - .master_ready_i ( WREADY ) - ); - axi_r_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .DATA_WIDTH ( AXI4_RDATA_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_r_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( RVALID ), - .slave_data_i ( RDATA ), - .slave_resp_i ( RRESP ), - .slave_user_i ( RUSER ), - .slave_id_i ( RID ), - .slave_last_i ( RLAST ), - .slave_ready_o ( RREADY ), - .master_valid_o ( RVALID_o ), - .master_data_o ( RDATA_o ), - .master_resp_o ( RRESP_o ), - .master_user_o ( RUSER_o ), - .master_id_o ( RID_o ), - .master_last_o ( RLAST_o ), - .master_ready_i ( RREADY_i ) - ); - - axi_b_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_b_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - - .slave_valid_i ( BVALID ), - .slave_resp_i ( BRESP ), - .slave_id_i ( BID ), - .slave_user_i ( BUSER ), - .slave_ready_o ( BREADY ), - - .master_valid_o ( BVALID_o ), - .master_resp_o ( BRESP_o ), - .master_id_o ( BID_o ), - .master_user_o ( BUSER_o ), - .master_ready_i ( BREADY_i ) - ); - - always_comb begin - read_req = 1'b0; - write_req = 1'b0; - W_word_sel = 1'b0; // Write Word Selector - - sample_AW = 1'b0; - decr_AWLEN = 1'b0; - sample_AR = 1'b0; - decr_ARLEN = 1'b0; - - incr_AWADDR = 1'b0; - incr_ARADDR = 1'b0; - - sample_RDATA_0 = 1'b0; - sample_RDATA_1 = 1'b0; - - ARREADY = 1'b0; - AWREADY = 1'b0; - WREADY = 1'b0; - RDATA = '0; - - BVALID = 1'b0; - BRESP = `OKAY; - BID = AWID; - BUSER = AWUSER; - - RVALID = 1'b0; - RLAST = 1'b0; - RID = ARID; - RUSER = ARUSER; - RRESP = `OKAY; - - case(CS) - - WAIT_R_PREADY: begin - sample_AR = 1'b0; - read_req = 1'b1; - address = ARADDR; - - if (PREADY == 1'b1) begin// APB is READY --> RDATA is AVAILABLE - if (ARLEN == 0) begin - case (ARSIZE) - 3'h3: begin - NS = SINGLE_RD_64; - if (ARADDR[2:0] == 3'h4) - sample_RDATA_1 = 1'b1; - else sample_RDATA_0 = 1'b1; - end - - default: begin - NS = SINGLE_RD; - if (ARADDR[2:0] == 3'h4) - sample_RDATA_1 = 1'b1; - else - sample_RDATA_0 = 1'b1; - end - endcase - end else begin // ARLEN > 0 --> BURST - NS = BURST_RD_64; - sample_RDATA_0 = 1'b1; - decr_ARLEN = 1'b1; - incr_ARADDR = 1'b1; - end - end else begin // APB not ready - NS = WAIT_R_PREADY; - end - end - - WAIT_W_PREADY: begin - address = AWADDR; - write_req = 1'b1; - - if (AWADDR[2:0] == 3'h4) - W_word_sel = 1'b1; - else - W_word_sel = 1'b0; - - // There is a Pending WRITE!! - if (PREADY == 1'b1) begin // APB is READY --> WDATA is LAtched - if (AWLEN == 0) begin // single write - case (AWSIZE) - 3'h3: NS = SINGLE_WR_64; - default: NS = SINGLE_WR; - endcase - end else begin // BURST WRITE - sample_AW = 1'b1; - NS = BURST_WR_64; - end - end else begin // APB not READY - NS = WAIT_W_PREADY; - end - end - - IDLE: begin - if (ARVALID == 1'b1) begin - sample_AR = 1'b1; - read_req = 1'b1; - address = ARADDR; - - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - if (ARLEN == 0) begin - case (ARSIZE) - 3'h3: begin - NS = SINGLE_RD_64; - if (ARADDR[2:0] == 4) - sample_RDATA_1 = 1'b1; - else - sample_RDATA_0 = 1'b1; - end - default: begin - NS = SINGLE_RD; - if (ARADDR[2:0] == 4) - sample_RDATA_1 = 1'b1; - else - sample_RDATA_0 = 1'b1; - end - endcase end else begin //ARLEN > 0 --> BURST - NS = BURST_RD_64; - sample_RDATA_0 = 1'b1; - end - end else begin // APB not ready - NS = WAIT_R_PREADY; - end - end else begin - - if (AWVALID) begin //: _VALID_AW_REQ_ - if (WVALID) begin // : _VALID_W_REQ_ - write_req = 1'b1; - address = AWADDR; - - if (AWADDR[2:0] == 3'h4) - W_word_sel = 1'b1; - else - W_word_sel = 1'b0; - - // There is a Pending WRITE!! - if (PREADY == 1'b1) begin// APB is READY --> WDATA is LAtched _APB_SLAVE_READY_ - if(AWLEN == 0) begin //: _SINGLE_WRITE_ - case(AWSIZE) - 3'h3: NS = SINGLE_WR_64; - default: NS = SINGLE_WR; - endcase - end else begin // BURST WRITE - sample_AW = 1'b1; - if ((AWADDR[2:0] == 3'h4) && (WSTRB[7:4] == 0)) - incr_AWADDR = 1'b0; - else - incr_AWADDR = 1'b1; - NS = BURST_WR_64; - end - end else begin// APB not READY - NS = WAIT_W_PREADY; - end - end else begin // GOT ADDRESS WRITE, not DATA - write_req = 1'b0; - address = '0; - NS = IDLE; - end - end else begin// No requests - NS = IDLE; - address = '0; - end - end - end - - SINGLE_WR_64: begin - address = AWADDR + 4; - W_word_sel = 1'b1; // write the Second data chunk - write_req = WVALID; - if (WVALID) begin - if (PREADY == 1'b1) - NS = SINGLE_WR; - else - NS = SINGLE_WR_64; - end else begin - NS = SINGLE_WR_64; - end - end - - SINGLE_WR: begin - BVALID = 1'b1; - address = '0; - if (BREADY) begin - NS = IDLE; - AWREADY = 1'b1; - WREADY = 1'b1; - end else begin - NS = SINGLE_WR; - end - end - - BURST_WR_64: begin - W_word_sel = 1'b1; // write the Second data chunk first - write_req = WVALID & (|WSTRB[7:4]); - address = AWADDR_Q; // second Chunk, Fixzed Burst - - if (WVALID) begin - if (&WSTRB[7:4]) begin - if(PREADY == 1'b1) begin - NS = BURST_WR; - WREADY = 1'b1; // pop onother data from the WDATA fifo - decr_AWLEN = 1'b1; // decrement the remaining BURST beat - incr_AWADDR = 1'b1; // increment address - end else begin - NS = BURST_WR_64; - end - end else begin - NS = BURST_WR; - WREADY = 1'b1; // pop onother data from the WDATA fifo - decr_AWLEN = 1'b1; // decrement the remaining BURST beat - incr_AWADDR = 1'b1; // increment address - end - end else begin - NS = BURST_WR_64; - end - end - - BURST_WR: begin - address = AWADDR_Q; // second Chunk, Fixzed Burst - if (AWLEN_Q == 0) begin // last : _BURST_COMPLETED_ - BVALID = 1'b1; - if (BREADY) begin - NS = IDLE; - AWREADY = 1'b1; - end else - NS = BURST_WR; - end else begin //: _BUSRST_NOT_COMPLETED_ - W_word_sel = 1'b0; // write the Second data chunk first - write_req = WVALID & (&WSTRB[3:0]); - if (WVALID) begin - if (PREADY == 1'b1) begin - NS = BURST_WR_64; - incr_AWADDR = 1'b1; - decr_AWLEN = 1'b1; //decrement the remaining BURST beat - end else - NS = BURST_WR; - end else begin - NS = BURST_WR_64; - end - end - end - - BURST_RD_64: begin - read_req = 1'b1; - address = ARADDR_Q; - - if (ARLEN_Q == 0) begin // burst completed - NS = IDLE; - ARREADY = 1'b1; - end else begin - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - decr_ARLEN = 1'b1; - sample_RDATA_1 = 1'b1; - NS = BURST_RD; - - if (ARADDR_Q[2:0] == 3'h4) - incr_ARADDR = 1'b1; - else - incr_ARADDR = 1'b0; - end - else begin - NS = BURST_RD_64; - end - end - end - - BURST_RD: begin - RVALID = 1'b1; - RDATA[0] = RDATA_Q_0; - RDATA[1] = RDATA_Q_1; - RLAST = (ARLEN_Q == 0) ? 1'b1 : 1'b0; - address = ARADDR_Q; - - if (RREADY) begin // ready to send back the rdata - if (ARLEN_Q == 0) begin // burst completed - NS = IDLE; - ARREADY = 1'b1; - end else begin //: _READ_BUSRST_NOT_COMPLETED_ - read_req = 1'b1; - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - sample_RDATA_0 = 1'b1; - NS = BURST_RD_64; - incr_ARADDR = 1'b1; - decr_ARLEN = 1'b1; - end else begin - NS = BURST_RD_1; - end - end - end else begin // NOT ready to send back the rdata - NS = BURST_RD; - end - end - - BURST_RD_1: begin - read_req = 1'b1; - address = ARADDR_Q; - - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - sample_RDATA_0 = 1'b1; - NS = BURST_RD_64; - incr_ARADDR = 1'b1; - decr_ARLEN = 1'b1; - end else begin - NS = BURST_RD_1; - end - end - - SINGLE_RD: begin - RVALID = 1'b1; - RDATA[0] = RDATA_Q_0; - RDATA[1] = RDATA_Q_1; - RLAST = 1; - address = '0; - - if (RREADY) begin // ready to send back the rdata - NS = IDLE; - ARREADY = 1'b1; - end else begin // NOT ready to send back the rdata - NS = SINGLE_RD; - end - end - - SINGLE_RD_64: begin - read_req = 1'b1; - address = ARADDR + 4; - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - NS = SINGLE_RD; - if(ARADDR[2:0] == 3'h4) - sample_RDATA_0 = 1'b1; - else - sample_RDATA_1 = 1'b1; - end else begin - NS = SINGLE_RD_64; - end - end - - default: begin - NS = IDLE; - address = '0; - end - endcase - end - - // ----------- - // Registers - // ----------- - always_ff @(posedge ACLK, negedge ARESETn) begin - if (ARESETn == 1'b0) begin - CS <= IDLE; - //Read Channel - ARLEN_Q <= '0; - AWADDR_Q <= '0; - //Write Channel - AWLEN_Q <= '0; - RDATA_Q_0 <= '0; - RDATA_Q_1 <= '0; - ARADDR_Q <= '0; - end else begin - CS <= NS; - - if (sample_AR) begin - ARLEN_Q <= {ARLEN,1'b0} + 2; - end else if (decr_ARLEN) begin - ARLEN_Q <= ARLEN_Q - 1; - end - - if (sample_RDATA_0) - RDATA_Q_0 <= PRDATA; - - if (sample_RDATA_1) - RDATA_Q_1 <= PRDATA; - - case ({sample_AW, decr_AWLEN}) - 2'b00: AWLEN_Q <= AWLEN_Q; - 2'b01: AWLEN_Q <= AWLEN_Q - 1; - 2'b10: AWLEN_Q <= {AWLEN, 1'b0} + 1; - 2'b11: AWLEN_Q <= {AWLEN, 1'b0}; - endcase - - case ({sample_AW, incr_AWADDR}) - 2'b00: AWADDR_Q <= AWADDR_Q; - 2'b01: AWADDR_Q <= AWADDR_Q + 4; - 2'b10: AWADDR_Q <= {AWADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000}; - 2'b11: AWADDR_Q <= {AWADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000} + 4; - endcase - - case({sample_AR, incr_ARADDR}) - 2'b00: ARADDR_Q <= ARADDR_Q; - 2'b01: ARADDR_Q <= ARADDR_Q + 4; - 2'b10: ARADDR_Q <= {ARADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000}; - 2'b11: ARADDR_Q <= {ARADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000} + 4; - endcase - end - end -endmodule diff --git a/tb/mock_uart_axi.sv b/tb/mock_uart_axi.sv index 46049d23..dc730db3 100644 --- a/tb/mock_uart_axi.sv +++ b/tb/mock_uart_axi.sv @@ -33,70 +33,76 @@ module mock_uart_axi #( logic uart_pready; logic uart_pslverr; - axi2apb_64_32 #( - .AXI4_ADDRESS_WIDTH ( AxiAw ), - .AXI4_RDATA_WIDTH ( AxiDw ), - .AXI4_WDATA_WIDTH ( AxiDw ), - .AXI4_ID_WIDTH ( AxiIw ), - .AXI4_USER_WIDTH ( AxiUw ), - .BUFF_DEPTH_SLAVE ( 2 ), - .APB_ADDR_WIDTH ( 32 ) - ) i_axi2apb_64_32_uart ( - .ACLK ( clk_i ), - .ARESETn ( rst_ni ), - .test_en_i ( 1'b0 ), - .AWID_i ( uart.aw_id ), - .AWADDR_i ( uart.aw_addr ), - .AWLEN_i ( uart.aw_len ), - .AWSIZE_i ( uart.aw_size ), - .AWBURST_i ( uart.aw_burst ), - .AWLOCK_i ( uart.aw_lock ), - .AWCACHE_i ( uart.aw_cache ), - .AWPROT_i ( uart.aw_prot ), - .AWREGION_i( uart.aw_region ), - .AWUSER_i ( uart.aw_user ), - .AWQOS_i ( uart.aw_qos ), - .AWVALID_i ( uart.aw_valid ), - .AWREADY_o ( uart.aw_ready ), - .WDATA_i ( uart.w_data ), - .WSTRB_i ( uart.w_strb ), - .WLAST_i ( uart.w_last ), - .WUSER_i ( uart.w_user ), - .WVALID_i ( uart.w_valid ), - .WREADY_o ( uart.w_ready ), - .BID_o ( uart.b_id ), - .BRESP_o ( uart.b_resp ), - .BVALID_o ( uart.b_valid ), - .BUSER_o ( uart.b_user ), - .BREADY_i ( uart.b_ready ), - .ARID_i ( uart.ar_id ), - .ARADDR_i ( uart.ar_addr ), - .ARLEN_i ( uart.ar_len ), - .ARSIZE_i ( uart.ar_size ), - .ARBURST_i ( uart.ar_burst ), - .ARLOCK_i ( uart.ar_lock ), - .ARCACHE_i ( uart.ar_cache ), - .ARPROT_i ( uart.ar_prot ), - .ARREGION_i( uart.ar_region ), - .ARUSER_i ( uart.ar_user ), - .ARQOS_i ( uart.ar_qos ), - .ARVALID_i ( uart.ar_valid ), - .ARREADY_o ( uart.ar_ready ), - .RID_o ( uart.r_id ), - .RDATA_o ( uart.r_data ), - .RRESP_o ( uart.r_resp ), - .RLAST_o ( uart.r_last ), - .RUSER_o ( uart.r_user ), - .RVALID_o ( uart.r_valid ), - .RREADY_i ( uart.r_ready ), - .PENABLE ( uart_penable ), - .PWRITE ( uart_pwrite ), - .PADDR ( uart_paddr ), - .PSEL ( uart_psel ), - .PWDATA ( uart_pwdata ), - .PRDATA ( uart_prdata ), - .PREADY ( uart_pready ), - .PSLVERR ( uart_pslverr ) + AXI_LITE #( + .AXI_DATA_WIDTH(AxiDw), + .AXI_ADDR_WIDTH(AxiAw) + ) uart_lite_wide(); + + AXI_LITE #( + .AXI_DATA_WIDTH(32), + .AXI_ADDR_WIDTH(AxiAw) + ) uart_lite(); + + axi_to_axi_lite_intf #( + .AXI_ADDR_WIDTH ( AxiAw ), + .AXI_DATA_WIDTH ( AxiDw ), + .AXI_ID_WIDTH ( AxiIw ), + .AXI_USER_WIDTH ( AxiUw ), + .AXI_MAX_WRITE_TXNS(1), + .AXI_MAX_READ_TXNS (1), + .FALL_THROUGH (1'b1), + .FULL_BW (1'b1) + ) i_axi_to_axi_lite_intf ( + .clk_i, + .rst_ni, + .testmode_i(test_i), + .slv (uart), + .mst (uart_lite_wide) + ); + + axi_lite_dw_converter_intf #( + .AXI_ADDR_WIDTH (AxiAw), + .AXI_SLV_PORT_DATA_WIDTH(AxiDw), + .AXI_MST_PORT_DATA_WIDTH(32) + ) i_axi_lite_dw_converter_intf ( + .clk_i ( clk_i ), + .rst_ni( rst_ni ), + .slv ( uart_lite_wide ), + .mst ( uart_lite ) + ); + + typedef struct packed { + int unsigned idx; + logic [AxiAw-1:0] start_addr; + logic [AxiAw-1:0] end_addr; + } rule_t; + + rule_t [0:0] rule; + assign rule[0] = '{0, '0, '1}; + + axi_lite_to_apb_intf #( + .NoApbSlaves (1), + .NoRules (1), + .AddrWidth (AxiAw), + .DataWidth (32), + .PipelineRequest (1'b0), + .PipelineResponse(1'b0), + .rule_t (rule_t) + ) i_axi_lite_to_apb_intf ( + .clk_i, + .rst_ni, + .slv ( uart_lite ), + .paddr_o ( uart_paddr ), + .pprot_o ( ), + .pselx_o ( uart_psel ), + .penable_o ( uart_penable ), + .pwrite_o ( uart_pwrite ), + .pwdata_o ( uart_pwdata ), + .pstrb_o ( ), + .pready_i ( uart_pready ), + .prdata_i ( uart_prdata ), + .pslverr_i ( uart_pslverr ), + .addr_map_i(rule) ); /* pragma translate_off */ diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 6087e08a..757d4aab 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -146,7 +146,21 @@ module pulp_cluster_tb; .clk_i ( s_clk ), .rst_ni ( s_rstn ), .axi_req_i ( axi_memreq ), - .axi_rsp_o ( axi_memrsp ) + .axi_rsp_o ( axi_memrsp ), + .mon_w_valid_o (), + .mon_w_addr_o (), + .mon_w_data_o (), + .mon_w_id_o (), + .mon_w_user_o (), + .mon_w_beat_count_o(), + .mon_w_last_o (), + .mon_r_valid_o (), + .mon_r_addr_o (), + .mon_r_data_o (), + .mon_r_id_o (), + .mon_r_user_o (), + .mon_r_beat_count_o(), + .mon_r_last_o () ); mock_uart_axi #(