From 812177f40c8e730bede1e230accf1118cbe60bd2 Mon Sep 17 00:00:00 2001 From: Jack Chen Date: Thu, 9 Jul 2020 13:33:19 +0800 Subject: [PATCH] rtl: remove RST Time registers --- README.md | 19 +++++++------------ rtl/layer_code.sv | 10 ++++------ rtl/layer_conf.sv | 34 +++++++++++++--------------------- rtl/layer_ctrl.sv | 2 +- rtl/top.sv | 20 +++++--------------- rtl/ws281x_code.sv | 2 +- rtl/ws281x_ctrl.sv | 19 +++++++------------ 7 files changed, 38 insertions(+), 68 deletions(-) diff --git a/README.md b/README.md index 8c04f87..371b173 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ WS281X Cube Controller based on MAX10 FPGA. * 4-Wire SPI Interface * High Refresh Rate (Up to 500fps@8x8x8) * 8 Data Lines in Parallel (64 LEDs per line) -* Configurable Waveform Generator (T0H, T0L, T1H, T1L, RST) +* Configurable Waveform Generator (T0H, T0L, T1H, T1L) * Configurable LED Serial Connection Sequence (Addr Linked List) ## Commands @@ -22,21 +22,16 @@ WS281X Cube Controller based on MAX10 FPGA. | 2nd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | | 3rd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | | 4th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | -| 5th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | -| 6th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | | -* 1st Param: T0H Time, unit: 10 ns -* 2nd Param: T0L Time, unit: 10 ns -* 3rd Param: T1H Time, unit: 10 ns -* 4th Param: T1L Time, unit: 10 ns -* 5th Param: RST Time H, unit: 10 ns -* 6th Param: RST Time L, unit: 10 ns +* 1st Param: T0H Time, range: 1-255, unit: 10 ns +* 2nd Param: T0L Time, range: 1-255, unit: 10 ns +* 3rd Param: T1H Time, range: 1-255, unit: 10 ns +* 4th Param: T1L Time, range: 1-255, unit: 10 ns Limits: -* T0H + T0L <= 255 = 2550 ns = 2.55 us -* T1H + T1L <= 255 = 2550 ns = 2.55 us -* RST <= 65535 = 655350 ns = 655.35 us +* T0H + T0L <= 257 = 2570 ns = 2.57 us +* T1H + T1L <= 257 = 2570 ns = 2.57 us ### ADDR_WR diff --git a/rtl/layer_code.sv b/rtl/layer_code.sv index 8da64c1..6e2fe42 100644 --- a/rtl/layer_code.sv +++ b/rtl/layer_code.sv @@ -15,11 +15,10 @@ module layer_code( input logic [7:0] wr_data_in, input logic [3:0] wr_byte_en_in, - input logic [ 7:0] t0h_cnt_in, - input logic [ 7:0] t0l_cnt_in, - input logic [ 7:0] t1h_cnt_in, - input logic [ 7:0] t1l_cnt_in, - input logic [15:0] rst_cnt_in, + input logic [7:0] t0h_cnt_in, + input logic [7:0] t0l_cnt_in, + input logic [7:0] t1h_cnt_in, + input logic [7:0] t1l_cnt_in, output logic ws281x_code_out ); @@ -50,7 +49,6 @@ ws281x_ctrl ws281x_ctrl( .wr_done_in(wr_done_in), .rd_data_in(rd_data), - .rst_cnt_in(rst_cnt_in), .bit_rdy_out(bit_rdy), .bit_data_out(bit_data), diff --git a/rtl/layer_conf.sv b/rtl/layer_conf.sv index 7d2263d..313debf 100644 --- a/rtl/layer_conf.sv +++ b/rtl/layer_conf.sv @@ -13,24 +13,21 @@ module layer_conf( input logic [5:0] wr_addr_in, input logic [7:0] wr_data_in, - output logic [ 7:0] t0h_cnt_out, - output logic [ 7:0] t0l_cnt_out, - output logic [ 7:0] t1h_cnt_out, - output logic [ 7:0] t1l_cnt_out, - output logic [15:0] rst_cnt_out + output logic [7:0] t0h_cnt_out, + output logic [7:0] t0l_cnt_out, + output logic [7:0] t1h_cnt_out, + output logic [7:0] t1l_cnt_out ); -logic [ 7:0] t0h_cnt; -logic [ 7:0] t0l_cnt; -logic [ 7:0] t1h_cnt; -logic [ 7:0] t1l_cnt; -logic [15:0] rst_cnt; +logic [7:0] t0h_cnt; +logic [7:0] t0l_cnt; +logic [7:0] t1h_cnt; +logic [7:0] t1l_cnt; assign t0h_cnt_out = t0h_cnt; assign t0l_cnt_out = t0l_cnt; assign t1h_cnt_out = t1h_cnt; assign t1l_cnt_out = t1l_cnt; -assign rst_cnt_out = rst_cnt; always_ff @(posedge clk_in or negedge rst_n_in) begin @@ -39,22 +36,17 @@ begin t0l_cnt <= 8'h00; t1h_cnt <= 8'h00; t1l_cnt <= 8'h00; - rst_cnt <= 16'h0000; end else begin if (wr_en_in) begin - case (wr_addr_in[2:0]) - 3'h0: + case (wr_addr_in[1:0]) + 2'b00: t0h_cnt <= wr_data_in; - 3'h1: + 2'b01: t0l_cnt <= wr_data_in; - 3'h2: + 2'b10: t1h_cnt <= wr_data_in; - 3'h3: + 2'b11: t1l_cnt <= wr_data_in; - 3'h4: - rst_cnt[15:8] <= wr_data_in; - 3'h5: - rst_cnt[ 7:0] <= wr_data_in; endcase end end diff --git a/rtl/layer_ctrl.sv b/rtl/layer_ctrl.sv index dc957b2..ae6cb3c 100644 --- a/rtl/layer_ctrl.sv +++ b/rtl/layer_ctrl.sv @@ -32,7 +32,7 @@ logic [2:0] data_en; logic [5:0] wr_addr; -wire conf_done = (wr_addr == 6'd5); +wire conf_done = (wr_addr == 6'd3); wire code_done = code_wr[0]; wire addr_done = (wr_addr == 6'd63); diff --git a/rtl/top.sv b/rtl/top.sv index c0519ca..084135c 100644 --- a/rtl/top.sv +++ b/rtl/top.sv @@ -32,11 +32,10 @@ logic wr_done; logic [5:0] wr_addr; logic [3:0] wr_byte_en; -logic [ 7:0] t0h_cnt; -logic [ 7:0] t0l_cnt; -logic [ 7:0] t1h_cnt; -logic [ 7:0] t1l_cnt; -logic [15:0] rst_cnt; +logic [7:0] t0h_cnt; +logic [7:0] t0l_cnt; +logic [7:0] t1h_cnt; +logic [7:0] t1l_cnt; sys_ctrl sys_ctrl( .clk_in(clk_in), @@ -84,8 +83,7 @@ layer_conf layer_conf( .t0h_cnt_out(t0h_cnt), .t0l_cnt_out(t0l_cnt), .t1h_cnt_out(t1h_cnt), - .t1l_cnt_out(t1l_cnt), - .rst_cnt_out(rst_cnt) + .t1l_cnt_out(t1l_cnt) ); layer_code layer_code7( @@ -102,7 +100,6 @@ layer_code layer_code7( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[7]) ); @@ -121,7 +118,6 @@ layer_code layer_code6( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[6]) ); @@ -140,7 +136,6 @@ layer_code layer_code5( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[5]) ); @@ -159,7 +154,6 @@ layer_code layer_code4( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[4]) ); @@ -178,7 +172,6 @@ layer_code layer_code3( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[3]) ); @@ -197,7 +190,6 @@ layer_code layer_code2( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[2]) ); @@ -216,7 +208,6 @@ layer_code layer_code1( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[1]) ); @@ -235,7 +226,6 @@ layer_code layer_code0( .t0l_cnt_in(t0l_cnt), .t1h_cnt_in(t1h_cnt), .t1l_cnt_in(t1l_cnt), - .rst_cnt_in(rst_cnt), .ws281x_code_out(ws281x_code_out[0]) ); diff --git a/rtl/ws281x_code.sv b/rtl/ws281x_code.sv index ae26e09..803151c 100644 --- a/rtl/ws281x_code.sv +++ b/rtl/ws281x_code.sv @@ -31,7 +31,7 @@ logic bit_done, bit_code; wire [7:0] t0_sum = t0h_cnt_in + t0l_cnt_in; wire [7:0] t1_sum = t1h_cnt_in + t1l_cnt_in; -wire cnt_done = (bit_cnt[8:1] == cnt_sum); +wire cnt_done = (bit_cnt[8:0] == {cnt_sum, 1'b0} - 2'b11); wire t0h_time = (bit_cnt[8:1] < t0h_cnt_in); wire t1h_time = (bit_cnt[8:1] < t1h_cnt_in); diff --git a/rtl/ws281x_ctrl.sv b/rtl/ws281x_ctrl.sv index f2d4aac..8aad524 100644 --- a/rtl/ws281x_ctrl.sv +++ b/rtl/ws281x_ctrl.sv @@ -13,7 +13,6 @@ module ws281x_ctrl( input logic wr_done_in, input logic [31:0] rd_data_in, - input logic [15:0] rst_cnt_in, output logic bit_rdy_out, output logic bit_data_out, @@ -25,12 +24,13 @@ module ws281x_ctrl( parameter [1:0] IDLE = 2'b00; // Idle parameter [1:0] READ_RAM = 2'b01; // Read RAM Data parameter [1:0] SEND_BIT = 2'b10; // Send Bit Code -parameter [1:0] SEND_RST = 2'b11; // Send RST Code +parameter [1:0] SYNC_BIT = 2'b11; // Sync Bit Code logic [1:0] ctl_sta; logic bit_st; logic [4:0] bit_sel; +logic [8:0] bit_syn; logic bit_rdy, bit_data; @@ -38,13 +38,11 @@ logic rd_done; logic [ 5:0] rd_addr; logic [23:0] rd_data; -logic [16:0] rst_cnt; - wire ram_next = (bit_sel == 5'd23); wire ram_done = (rd_addr == 6'h00); wire bit_next = bit_st | bit_done_in; -wire rst_done = (rst_cnt[16:1] == rst_cnt_in); +wire syn_done = (bit_syn[8:1] == 8'hfe); assign bit_rdy_out = bit_rdy; assign bit_data_out = bit_data; @@ -66,8 +64,6 @@ begin rd_done <= 1'b0; rd_addr <= 6'h00; rd_data <= 24'h00_0000; - - rst_cnt <= 17'h0_0000; end else begin case (ctl_sta) IDLE: @@ -75,15 +71,16 @@ begin READ_RAM: ctl_sta <= rd_done ? SEND_BIT : ctl_sta; SEND_BIT: - ctl_sta <= (bit_next & ram_next) ? (ram_done ? SEND_RST : READ_RAM) : ctl_sta; - SEND_RST: - ctl_sta <= rst_done ? IDLE : ctl_sta; + ctl_sta <= (bit_next & ram_next) ? (ram_done ? SYNC_BIT : READ_RAM) : ctl_sta; + SYNC_BIT: + ctl_sta <= syn_done ? IDLE : ctl_sta; default: ctl_sta <= IDLE; endcase bit_st <= (ctl_sta != SEND_BIT) & ((ctl_sta == IDLE) | bit_st); bit_sel <= (ctl_sta == SEND_BIT) ? bit_sel + bit_next : 5'h00; + bit_syn <= (ctl_sta == SYNC_BIT) ? bit_syn + 1'b1 : 9'h000; bit_rdy <= (ctl_sta == SEND_BIT) & bit_next; bit_data <= (ctl_sta == SEND_BIT) & bit_next ? rd_data[5'd23 - bit_sel] : bit_data; @@ -91,8 +88,6 @@ begin rd_done <= rd_en_out; rd_addr <= rd_done ? rd_data_in[29:24] : rd_addr; rd_data <= rd_done ? rd_data_in[23:0] : rd_data; - - rst_cnt <= (ctl_sta == SEND_RST) ? rst_cnt + 1'b1 : 17'h0_0000; end end