Interrupts

Apart from the special reset, which can be considered a pseudo-interrupt, the Z80 provides two types of interrupts.

The maskable interrupt (INT)

The maskable interrupt can be enabled and disabled by using the ei and di instructions respectively, which control the state of the interrupt enable flip-flops (IFF1 and IFF2). The CPU does not accept this kind of interrupt directly after an ei instruction, but only after the one following ei is executed. This is so that ISRs can return without the danger of being interrupted immediately after re-enabling interrupts if the /INT line is still active, which could cause a stack overflow.

As in ei, all forms of reti and retn defer the acceptance of the maskable interrupt for one instruction, but this only occurs when IFF1 and IFF2 do not have the same state prior to the execution of either of these instructions, which can only be caused by an earlier NMI response.

This interrupt has three operation modes, which are selected through the im instruction:

Interrupt mode 0

Interrupt mode 1

Interrupt mode 2

The non-maskable interrupt (NMI)

The non-maskable interrupt takes priority over the maskable interrupt and cannot be disabled under software control. Its usual function is to provide immediate response to important signals. The CPU responds to an NMI by storing PC on the stack and jumping to the ISR located at address 0066h. The interrupt enable flip-flop 1 (IFF1) is reset to prevent any INT from being accepted during the execution of this routine, which is usually exited by using a reti or retn instruction to restore the original state of IFF1.

Some technical documents from Zilog include an erroneous timing diagram showing an NMI acknowledge cycle of 4 T-states. However, documents from other manufacturers and third parties specify that this M-cycle has 5 T-states, as has been confirmed by low-level tests and electronic simulations.

The CPU does not accept a second NMI during the NMI response. Therefore, it is not possible to chain two NMI responses in a row without executing at least one instruction between them.