Packed SIMD gcc, binutils

[jjscheel]

Technical Group

Packed SIMD Task Group tech-p-ext

ratification-pkg

Packed SIMD

Technical Liaison

Kevin Chen

Task Category

Compilers/Toolchain

Task Sub Category

• gcc
• binutils
• gdb
• intrinsics
• Java
• KVM
• ld
• llvm
• Linux kernel
• QEMU
• Spike

Ratification Target

1Q2025

Statement of Work (SOW)

Component names:

• GCC Toolchain
• LLVM Toolchain
• Qemu
• Spike

Requirements:
(prose describing what has to be done and what the end result is)

Deliverables:

Accepted PRs to the upstream communities for each of the components:

Acceptance Criteria:

• Follow the GNU Tool Chain Sign-Off Criteria to have an accepted gcc PR
• No guidelines available for LLVM, QEMU, and Spike communities

Projected timeframe: (best guess date)

SOW Signoffs: (delete those not needed)

• Task group liaison sign-off date:
• Development partner sign-off date:
• Toolchains & Runtimes sign-off date (if gcc, LLVM, binutils, gdb work):

Waiver

• Freeze
• Ratification

Pull Request Details

No response

[lazyparser]

@pz9115 and @ChunyuLiao may provide more info on this area.

[pz9115]

We had already updated porting the Packed SIMD gcc into GCC13 in downstream repo,
https://github.com/plctlab/riscv-gcc/tree/gcc13-p-rebase
porting Binutils into 2.41 is WIP.

[jjscheel]

Good to know. Thanks.

But the spec hasn't even been reviewed internally and thus may change!

[ChunyuLiao]

llvm has some patches under review, but are not active.
[RISCV] Implement the MC layer support of P extension https://reviews.llvm.org/D95588
[RISCV] Support experimental 'P' extension 0.9.11 https://reviews.llvm.org/D108189
[RISCV] Implement intrinsics for P extension https://reviews.llvm.org/D99158
[RISCV] Add vector types to GPR for P extension and explict type to existing codegen patterns https://reviews.llvm.org/D100288
[RISCV] Support Zbpbo extension v0.9.11 https://reviews.llvm.org/D128604

[pz9115]

P-ext TG has been active recently， discussing some instruction design in the community, waiting for their update.

https://lists.riscv.org/g/tech-p-ext/topic/102843596#268

[jjscheel]

Good to know. However, any work before Architecture Review completes may need to be re-done. I'm going to leave in "Blocked" state, but please do any work which you deem reasonable given the risk.

[pz9115]

Agree!

[jjscheel]

I reached out to the P-Ext Chair and they will indeed need help with toolchain. I need to get them enabled. Work is on my end.

[pz9115]

John Hauser sent a new version draft specification for Packed SIMD, still wait it move into a stable specification，maybe need take a few month.

https://lists.riscv.org/g/tech-p-ext/message/291

[jjscheel]

Specification work continues by John Hauser.

[jjscheel]

@fuhle044, please see the first entry for the issue (this is our SOW) and propose new text (as a comment) for the Requirements, Deliverables, and Acceptance Criteria sections.

[jjscheel]

@lazyparser, am I correct in assuming you plan on working on LLVM too? Are there any other pieces besides these 3?

[fuhle044]

Yes, LLVM will be included.

…

-rich

On Wed, Jul 24, 2024, 8:20 AM Jeff Scheel ***@***.***> wrote: @lazyparser <https://github.com/lazyparser>, am I correct in assuming you plan on working on LLVM too? Are there any other pieces besides these 3? — Reply to this email directly, view it on GitHub <#22 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AOB2QNVONEGH6NJFXDRN7ALZN7A23AVCNFSM6AAAAAAV6T6MHKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDENBYGI4DOOBZGA> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[pz9115]

We have a SOW here, and need Rich help to add the P spec link that need to be implement.

https://docs.google.com/document/d/1dCnLq8eSgOnD-bYrembB5aU4IVejn2q4OSJceVRIJpU/edit?usp=sharing

[jjscheel]

@pz9115, @fuhle044, I have taken the SOW information and put it into the first entry above SOW. Please review and provide any comments.

[jjscheel]

@lazyparser please see my previous comments about the SOW. I'd appreciate your feedback as well.

[pz9115]

We found a draft doc here https://lists.riscv.org/g/tech-p-ext/files/Drafts/RVP-baseInstrs-A-010.pdf, but it still need add encoding and some instructions descriptions to make sure we can implement it clear in toolchain part.

[jjscheel]

I have requested specification changes in an email to the TG: https://lists.riscv.org/g/tech-p-ext/topic/specification_details/108017701

[pz9115]

Keep waiting specificaction doc.

[jjscheel]

I talked with Rich Fuhler at RISC-V Summit NA and encouraged him to update Asciidoc version of document with all other design information. Offered to help as needed.

I did not get a target date for this work completing, but they understand that it's needed.

[pz9115]

Find the new draft p-ext instructions and encoding docs in https://www.jhauser.us/RISCV/ext-P/

Now working on the Binutils part, plans to complete it within the next month

• Add instructions endocing marco.
• Support register pair feature.
• Support register operands check.
• Add testcases.

https://github.com/ruyisdk/riscv-binutils/tree/p-dev

[jjscheel]

@pz9115, I think we have to be a little careful with the document you found given that it's not in the official repo for the spec. But, it's likely a safe starting place for your work.

[pz9115]

Still work in progress.